Fairchild Semiconductor 74LVTH322374 Datasheet
74LVTH322374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25
Ω Series Resistors in the Outputs (Preliminary)
Preliminary
February 2001
Revised August 2001
74LVTH322374 Low Voltage 32-Bit D-Type Fli p-Flop with 3-STATE Outputs and 25
Outputs (Preliminary)
General Description
The LVTH322374 contains thirty-tw o non-inverting D-ty pe
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The dev ice is byte controlled. A buffered clock (CP) and Output E nable (OE
each byte and can be shorted together for full 32-bit operation.
The LVTH322374 is designed with equival ent 25
resistance in both the HIGH and LOW states of th e o utp ut.
This design reduces line noise in applications such as
memory address drivers, clock d rivers, and bus transc eivers/transmitters.
The LVTH322374 data inputs includ e bushold, eliminat ing
the need for external pull-up resistors to hold unused
inputs.
These flip-flops ar e designed for low voltage (3.3 V) V
applications, but with the capability to provide a TTL inter-
face to a 5V enviro nment. The LVTH322374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
) are common to
Ω series
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs elimi nate th e need fo r extern al pullup resistors to hold unused inputs
■ Live insertion/extraction per mi tt ed
■ Power Up/Power Do wn high imp edance provid es gli tch-
free bus loading
■ Outputs include equiv alent series resistance of 25
make external termination resistors unnecessary and
reduce overshoot and undershoot
■ ESD performance:
Human-body model
CC
Machine model
Charged-device model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
> 2000V
> 200V
Ordering Code:
Order Number Package Number Package Description
74LVTH322374GX
(Note 1)
Note 1: BGA package available in Tape and Reel only.
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Logic Symbol
Ω to
> 1000V
Ω
Series Resistors in the
© 2001 Fairchild Semiconductor Corporation DS500429 www.fairchildsemi.com
Preliminary
Connection Diagram
74LVTH322374
(Top Thru View)
Pin Descriptions for FBGA
Pin Names Description
OE
CP
I
0–I31
O
0–O31
n
n
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
123456
A O
B O
C O
D O
E O
F O
G O
H O
J O
K O
L O
M O
N O
P O
R O
T O
O0OE1CP
1
O2GND GND I
3
O4V
5
7
9
11
13O12
14O15
17O16
19O18
21O20VCC2VCC2I20
23O22
25O24
27O26VCC2VCC2I26
29O28
30O31
CC1VCC1I4
O6GND GND I
O8GND GND I
O10V
CC1VCC1I10
GND GND I
OE2CP2I
OE3CP3I
GND GND I
GND GND I
GND GND I
GND GND I
OE4CP4I
1I0
I
1
I
2
3
I
5
I
6
7
I
8
9
I
11
I
12
13
I
15
14
I
16
17
I
18
19
I
21
I
22
23
I
24
25
I
27
I
28
29
I
31
30
Truth Tables
Inputs Outputs Inputs Outputs
CP
1
LL X O
OE
1
I0–I
7
O0–O
7
LH H
LL L
o
CP
2
LLX O
OE
I8–I
2
15
O8–O
15
LH H
LL L
o
XH X Z XHX Z
Inputs Outputs Inputs Outputs
CP
3
LL X O
OE
3
I16–I
23
O16–O
23
LH H
LL L
o
CP
4
LLX O
OE
I24–I
4
31
O24–O
31
LH H
LL L
o
XH X Z XHX Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
O
= Previous Oo before HIGH-to-LOW of CP
o
Functional Description
The LVTH322374 consists of thirt y-two edge-triggered flip-flops with ind ividual D-type inpu ts and 3-STATE true outputs.
The device is byte controll ed with e ach byte function ing identi cally, but independent o f the other. The control pins can be
shorted together to obta in full 32 -bit opera tion. E ach byt e has a buffered clock and buffered Output Enab le comm on to a ll
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP
Output Enable (OE
the high impedance state. Operation of the OE
) LOW, the contents of the flip-flops are avail ab le at th e out puts. When OEn is HIGH, the outputs go to
n
input does not affect the state of the flip-flops.
n
www.fairchildsemi.com 2
) transition. With the
n
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