Fairchild Semiconductor 74LVTH322373 Datasheet
74LVT322373 • 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25
Ω Series Resistors in the Outputs
May 2002
Revised May 2002
Resistors in the Outputs
74LVT322373 • 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25
General Description
The LVT322373 and LVTH322373 contain thirty-two no ninverting latches with 3- STATE outputs and ar e intended
for bus oriented applications. The device is byte contr olled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Dat a appears on the bus
when the Output Enable (OE
the outputs are in a high impedance state.
The LVTH322373 data inputs includ e bushold, eliminat ing
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed ope ration similar to 5V
ABT while maintaining a low power dissipation.
) is LOW. When OE is HIGH,
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feat ure (74LVT322373)
■ Live insertion/extraction per mi tt ed
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs include equiv alent series resistance of 25
make external termination resistors unnecessary and
CC
reduce overshoot and undershoot
■ ESD performance:
Human-body model
Machine model
Charged-device model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
> 2000V
> 200V
Ordering Code:
Order Number Package Number Package Descript io n
74LVT322373G
(Note 1) (Note 2)
74LVTH322373G
(Note 1) (Note 2)
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA96A
(Preliminary)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Logic Symbol
Ω to
> 1000V
© 2002 Fairchild Semiconductor Corporation DS500742 www.fairchildsemi.com
Ω
Series
Connection Diagram
74LVT322373 • 74LVTH322373
(Top Thru View)
Pin Descriptions
Pin Names Description
OE
LE
I
0–I31
O
0–O31
n
n
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
123456
A O
B O
C O
D O
E O
F O
G O
H O
J O
K O
L O
M O
N O
P O
R O
T O
O0OE1LE
1
O2GND GND I
3
O4V
5
7
9
11
13O12
14O15
17O16
19O18
21O20VCC2VCC2I20
23O22
25O24
27O26VCC2VCC2I26
29O28
30O31
CC1VCC1I4
O6GND GND I
O8GND GND I
O10V
CC1VCC1I10
GND GND I
OE2LE2I
OE3LE3I
GND GND I
GND GND I
GND GND I
GND GND I
OE4LE4I
1I0
I
1
I
2
3
I
5
I
6
7
I
8
9
I
11
I
12
13
I
15
14
I
16
17
I
18
19
I
21
I
22
23
I
24
25
I
27
I
28
29
I
31
30
Truth Table
Inputs Outputs Inputs Outputs
LE
1
OE
1
I0–I
7
O0–O
7
LE
2
OE
I8–I
2
15
O8–O
15
XH X Z XHX Z
HL L L HLL L
HL H H HLH H
LL X O
0
LLX O
0
Inputs Outputs Inputs Outputs
LE
3
OE
3
I16–I
23
O16–O
23
LE
4
OE
I24–I
4
31
O24–O
31
XH X Z XHX Z
HL L L HLL L
HL H H HLH H
LL X O
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedan ce Oo = Previous Oo prior to HIGH- to -LO W tr ans iti on of LE
0
LLX O
0
Functional Description
The LVT322373 and LVTH322373 contain thirty-two D-type latches with 3-STAT E standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full
32-bit opera t i on. Th e f o ll o wi ng de s c rip t ion a pp l ie s to ea c h byt e. Wh en t he Lat c h En a ble ( LE
enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input
changes. When LE
HIGH-to-LOW transition of LE
is LOW, the latches store information that was present on the D inputs a setup time preceding the
n
. The 3-STA TE standard outputs are controlled by the Output Enable (OEn) input. When OE
n
is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into the latches.
www.fairchildsemi.com 2
) input is HIGH, data on the D
n
n
n
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