Fairchild Semiconductor 74LVTH322245, 74LVT322245 Datasheet

May 2002
Revised May 2002

74LVT322245 • 74LVTH322245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs

and 25

Ω Series Resistors in A Port Outputs

74L VT3 22245 • 74LVTH322245 Low V olt age 32-Bit Transceiver with 3-STA TE Outputs and 25

A Port Outputs

General Description

The LVT322245 and LVTH322245 contain thirty-two no n­invertin g bidi rec tio nal bu ff er s wit h 3-STAT E outp uts and ar e
intended for bus orien ted applications. The de vice is byte
controlled. Each byte has separate control inputs which
can be shorted toget her for full 32-bit ope ration. The T/R
inputs determine the direction of data flow through the
device. The OE
placing them in a high impedance state.

The LVT322245 and LVTH322245 are designed with
equivalent 25
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.

The LVTH322245 data inputs includ e bushold, eliminat ing
the need for external pull-up resistors to hold unused
inputs.

These non-inverting transceivers are designed for low-volt­age (3.3V) V

vide a TTL interface to a 5V environment. The
LVT322245 and LVTH322245 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.

inputs disable bo th the A and B ports by

Ω series resistance in both the HIGH and

applications, but with the capability to pro-

CC

Features

■ Input and output interface capability to systems at
5V V

CC

■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322245)

■ Also available without bushold feature (74LVT322245)

■ Live insertion/extraction per mi tt ed

■ Power Up/Power Down high impedance provides

glitch-free bus loading

■ A Port outputs include equivalent series resistance of
25

Ω making external termina tion resistors unnecessary

and reducing overshoot and undershoot

■ A Port outputs source/sink
B Port outputs source/sink

■ ESD performance:
Human-body model
Machine model
Charged-device model

■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

> 2000V

> 200V

Ordering Code:

Order Number Package Number Package Description

74LVT322245G
(Note 1) (Note 2)

74LVTH322245G
(Note 1) (Note 2)

Note 1: Ordering code “G” indicates TRAYS.
Note 2: Devices also available in TAPE and REEL. Specify by appending the suffix letter “X” to the ordering code.

BGA96A

(Preliminary)

BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

±12 mA

−32 mA/+64 mA

> 1000V

Logic Symbol

© 2002 Fairchild Semiconductor Corporation DS500408 www.fairchildsemi.com

Ω

Series Resistors in

Connection Diagram

74LVT322245 • 74LVTH322245

(Top Thru View)

FBGA Pin Descriptions

Pin Names Description

OE
T/R
A

0–A31

B

0–B31

n

n

Output Enable Input (Active LOW)
Transmit/Receive Input

Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs

Pin Assignments for FBGA

123456

A B
B B
C B
D B
E B
F B
G B

H B
J B

K B
L B
M B
N B
P B
R B

T B

B0T/R1OE1A

1

B2GND GND A

3

B4V

5
7

9
11
13B12

14B15
17B16

19B18
21B20VCC2VCC2A20A21
23B22
25B24
27B26VCC2VCC2A26A27
29B28

30B31

CC1VCC1A4

B6GND GND A
B8GND GND A

B10V

CC1VCC1A10A11

GND GND A

T/R2OE2A
T/R3OE3A

GND GND A

GND GND A
GND GND A

GND GND A

T/R4OE4A

A

0

A

2

A
A

6

A

8

12A13
15A14
16A17

18A19

22A23
24A25

28A29
31A30

1
3
5
7
9

Truth Tables

Inputs

OE

T/R

1

1

L L Bus B0–B7 Data to Bus A0–A
L H Bus A0–A7 Data to Bus B0–B
H X HIGH-Z State on A0–A7, B0–B

Inputs

OE

T/R

2

2

L L Bus B8–B15 Data to Bus A8–A
L H Bus A8–A15 Data to Bus B8–B
H X HIGH-Z State on A8–A15, B8–B

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

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Outputs

7
7

7

Outputs

15
15

15

OE

Inputs

3

T/R

3

Outputs

L L Bus B16–B23 Data to Bus A16–A
L H Bus A16–A23 Data to Bus B16–B
H X HIGH-Z State on A16–A23, B16–B

OE

Inputs

4

T/R

4

Outputs

L L Bus B24–B31 Data to Bus A24–A
L H Bus A24–A31 Data to Bus B24–B
H X HIGH-Z State on A24–A31, B24–B

23
23

23

31
31

31