Fairchild Semiconductor 74ACTQ657SPC, 74ACTQ657SCX, 74ACTQ657SC, 74ACTQ657CW Datasheet
© 2000 Fairchild Semiconductor Corporation DS010636 www.fairchildsemi.com
January 1990
Revised September 2000
74ACQ657 • 74ACTQ657 Quiet Series
Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checke r a nd
3-STATE Outputs
74ACQ657 • 74ACTQ657
Quiet Series
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The ACQ/ACTQ657 contains eight non-inverting buffers
with 3-STATE outputs and an 8-bit parity generator/
checker. Intended for bus orien ted ap plicat ions, the device
combines the 245 and the 280 functions in one package.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in
addition to a split ground bus or superior performance.
Features
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guarante ed pin-to-pin skew AC performance
■ Combines the 245 and the 280 functions in one package
■ 300 mil 24-pin slim dual-in-line package
■ Outputs source/sink 24 mA
■ ACTQ has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, Qui et Series , FACT Quiet Series, an d GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
0–A7
Data Inputs/3-STATE Outputs
B
0–B7
Data Inputs/3-STATE Outputs
T/R
Transmit/Receive Input
OE
Enable Input
PARITY Parity Input/3-STATE Output
ODD/EVEN ODD/EVEN Parity Input
ERROR
Error 3-STATE Output
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74ACQ657 • 74ACTQ657
Functional Description
The Transmit/Receive (T/R) input determines the dir ection
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A-Port to the
B-Port; Receive (active LOW) enables data from the B-Port
to the A-Port.
The Output Enable (OE
) input disables the parity and
ERROR
outputs and both the A and B Port s by placing
them in a HIGH-Z condition when th e Output E nable inp ut
is HIGH.
When transmitting (T/R
HIGH), the parity generator detects
whether an even or odd nu mber of bits on the A-Port are
HIGH and compares these wi th the condition of the pa rity
select (ODD/EVEN
). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R
LOW), the parity select and number
of HIGH inputs on port B a re compar ed to the con dition of
the Parity input. If an even number of bits on the B-Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR
will be HIGH to indicate no error. If an
odd number of bits on the B-Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Number of
Inputs
Input/
Outputs
Inputs That Output
Are High OE
T/R ODD/EVEN Parity ERROR Outputs Mode
0, 2, 4, 6, 8 L H H H Z Transmit
LHLLZTransmit
L L H H H Receive
LLHLLReceive
L L L H L Receive
LLLLHReceive
1, 3, 5, 7 L H H L Z Transmit
LHLHZTransmit
LLHHLReceive
LLHLHReceive
L L L H H Receive
LLLLLReceive
Immaterial H X X Z Z Z
Inputs
Outputs
OE
T/R
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X High-Z State
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74ACQ657 • 74ACTQ657
Functional Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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