Fairchild Semiconductor 74ACTQ541SCX, 74ACTQ541SC, 74ACTQ541PC, 74ACTQ541MTCX, 74ACTQ541MTC Datasheet

© 1999 Fairchild Semiconductor Corporation DS010932 www.fairchildsemi.com

March 1993
Revised November 1999

74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs

74ACTQ541
Quiet Series Octa l Buff e r/Line Driver

with 3-STATE Outputs

General Description

The 74ACTQ541 is an octal buffer/line driver designed to
be employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.

This device is similar in function to the 74ACTQ244 while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout ar rangement makes this de vice
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.

The 74ACTQ541 utilizes FACT Quiet Series technology
to guarantee quiet outp ut switchi ng and im proved dyna mic
threshold performance . FACT Quiet Series feat ure s GTO
output control and und ershoot corre ctor in additio n to split
ground bus for superior performance.

Features

■ ICC and IOZ reduced by 5 0%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Guarante ed pin-to-pin skew AC per formance

■ Inputs and outputs on opposite sides of package for

easy board layout

■ Non-inverting 3-STATE outputs

■ Guarante ed 4 kV minimum ESD immunity

■ TTL compatible inputs

■ Outputs source/sink 24 mA

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Truth T able

H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance

FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACTQ541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Name Pin Description

OE

1

– OE23-STATE Output Enable (Active-LOW)

I

0

–I

7

Inputs

O

1

– O

7

Outputs

Inputs

Outputs

OE

1

OE

2

I

LLHH
HXXZ
XHXZ
LLLL

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74ACTQ541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 4: Plastic DIP package.
Note 5: Max number of output s d ef ined as (n). Data inputs ar e driven 0V to 3V. One output @ GND.
Note 6: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V

ILD

),

0V to threshold (V

IHD

), f = 1 MHz.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C
DC Latch-up Source or Sink Current ± 300 mA
Junction Temperature (T

J

)140°C

Supply Voltage V

CC

4.5V to 5.5V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9

VI

OUT

= −50 µA

Output Voltage 4.5 4.49 4.4 4.4

4.5 3.86 3.76
V

VIN = VIL or VIH (Note 2)
IOH = −24 mA

−24 mA

5.5 4.86 4.76

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 4.5 0.001 0.1 0.1

4.5 0.36 0.44
V

VIN = VIL or VIH (Note 2)
I

OH

= 24 mA

24 mA

5.5 0.36 0.44

I

IN

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

I

OZ

Maximum 3-STATE

5.5 ±0.25 ±2.5 µA

VI = VIL, V

IH

Leakage Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent
Supply Current

5.5 4.0 40.0 µAVIN = VCC or GND

V

OLP

Quiet Output

5.0 1.1 1.5 V

Figure 1, Figure 2

Maximum Dynamic V

OL

(Note 4)(Note 5)

V

OLV

Quiet Output

5.0 −0.6 −1.2 V

Figure 1, Figure 2

Minimum Dynamic V

OL

(Note 4)(Note 5)

V

IHD

Minimum HIGH Level

5.0 1.9 2.2 V (Note 4)(Note 6)

Dynamic Input Voltage

V

ILD

Maximum LOW Level

5.0 1.2 0.8 V (Note 4)(Note 6)

Dynamic Input Voltage

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74ACTQ541

AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V ± 0.5V
Note 8: Skew is defined as t he absolute value of t he difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guarantee d by design.

Capacitance

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units

(V)

C

L

= 50 pF CL = 50 pF

(Note 7) Min Typ Max Min Max

t

PLH

Propagation Delay

5.0

2.0 4.5 7.0 2.0 7.5
ns

t

PHL

Data to Output 2.0 5.5 7.0 2.0 7.5

t

PZH

Output Enable Time

5.0

2.0 5.0 9.0 2.0 9.5
ns

t

PZL

2.0 6.5 9.0 2.0 9.5

t

PHZ

Output Disable Time

5.0

1.5 5.5 7.5 1.5 8.0
ns

t

PLZ

1.5 5.5 7.5 1.5 8.0

t

OSHL

Output to Output 0.5 1.0 1.0

ns

t

OSLH

Skew Data to Output (Note 8) 0.5 1.0 1.0

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 70 pF VCC = 5.0V