Fairchild Semiconductor 74ACTQ16244SSCX, 74ACTQ16244SSC, 74ACTQ16244MTDX, 74ACTQ16244MTD, 74ACTQ16244CW Datasheet
© 1999 Fairchild Semiconductor Corporation DS010925 www.fairchildsemi.com
May 1991
Revised November 1999
74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
74ACTQ16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16244 utiliz es Fairchild’s Quiet Series technology to guarantee quiet output switching and improved
dynamic threshold perf ormance. FACT Quiet Series fe atures GTO output control for superior performance.
Features
■ Utilizes Fairchild’s FACT Quiet Series technology
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte and nibble
■ 16-bit version of the ACTQ244
■ Outputs source/sink 24 mA
■ Additional specs for multiple output switching
■ Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Description
FACT, FACT Quiet Series, and GTO are trademarks of F airchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ16244SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0–I15
Inputs
O
0–O15
Outputs
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74ACTQ16244
Connection Diagram
Logic Diagram
Functional Description
The ACTQ16244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is nibble
(4 bits) controlled with each nibble functioning ide ntically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The 3STAT E outputs are contr olled by an Output E nable (OE
n
)
input for each nibble. When OE
n
is LOW, the outputs are in
2-state mode. Wh en OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Tr uth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Inputs Outputs
OE
1
I0–I
3
O0–O
3
LL L
LH H
HX Z
Inputs Outputs
OE
2
I4–I
7
O4–O
7
LL L
LH H
HX Z
Inputs Outputs
OE
3
I8–I
11
O8–O
11
LL L
LH H
HX Z
Inputs Outputs
OE
4
I12–I
15
O12–O
15
LL L
LH H
HX Z
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74ACTQ16244
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum rating s are those values beyond w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specific at ions.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Max number of data input s (n ) s w it c hing. (n − 1) input switching 0V to 3V input under test switching 3V to threshold (V
ILD
)
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= − 0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source/Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin ±50 mA
Junction Temperature +140°C
Storage Temperature −65°C to +150°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
TA = +25°C
TA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOH = 24 mA
5.5 0.36 0.44 I
OH
= 24 mA (Note 2)
I
OZ
Maximum 3-STATE
5.5 ± 0.5 ± 5.0 µA
VI = VIL, V
IH
Leakage Current VO = VCC, GND
I
IN
Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC −2.1V
I
CC
Max Quiescent Supply Current 5.5 8.0 80.0 µAVIN = VCC or GND (Note 6)
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) −75 mA V
OHD
= 3.85V Min
V
OLP
Quiet Output Maximum Dynamic V
OL
5.0 0.5 0.8 V Figure 1, Figure 2
(Note 5)(Note 6)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0 −0.5 −1.0 V Figure 1, Figure 2
(Note 5)(Note 6)
V
OHP
Maximum Overshoot 5.0 VOH + 1.0 VOH + 1.5 V (Note 4)(Note 6)
V
OHV
Minimum VCC Droop 5.0 VOH − 1.0 VOH − 1.8 V (Note 4)(Note 6)
V
IHD
Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7)
V
ILD
Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)
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