Fairchild Semiconductor 74ACT16245SSCX, 74ACT16245SSC, 74ACT16245MTDX, 74ACT16245MTD Datasheet
© 1999 Fairchild Semiconductor Corporation DS500296 www.fairchildsemi.com
August 1999
Revised October 1999
74ACT16245 16-Bit Transceiver with 3-STATE Outputs
74ACT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The ACT16245 contain s sixte en non- inverti ng bidir ectio nal
buffers with 3-STATE outputs and is inten ded for bus o riented applications. The device is byte controlled. Each has
separate control inputs which can be shorted tog ether for
full 16-bit operation. The T/R
inputs determine the direction
of data flow through the device. The OE
inputs disa bl e b oth
the A and B por ts by placing them in a high impedance
state.
Features
■ Bidirectional non-inverting buffers
■ Separate control logic for each byte
■ 16-bit version of the ACT245
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbol
Pin Description
Connection Diagram
FACT is a trade m ark of F airchild Semicondu ctor Corporation.
Order Number Package Number Package Description
74ACT16245SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
T/R
Transmit/Receive Input
A
0–A15
Side A Inputs/Outputs
B
0–B15
Side B Outputs/Inputs
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74ACT16245
Functional Description
The ACT16245 contains sixteen non-inverting bidirectional
buffers wi th 3- S TA T E ou tp u ts . Th e de v ic e i s byt e co ntr olled
with each byte funct ioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation. The following description
applies to each byte. When the T/R
input is HIGH, then Bus
A data is transmitted to Bus B. When the T/R
input is LOW,
Bus B data is transmitted to Bus A. The 3-STATE outputs
are controlled by an Output Enable (OE
n
) input for each
byte. When OE
n
is LOW, the outputs are in 2-state mode.
When OE
n
is HIGH, the outp uts ar e in th e high impedance
mode, but this d oes not interfere with ente ring new data
into the inputs.
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Inputs Outputs
OE
1
T/R
1
L L Bus B0–B7 Data to Bus A0–A
7
L H Bus A0–A7 Data to Bus B0–B
7
H X HIGH-Z State on A0–A7, B0–B
7
Inputs Outputs
OE
2
T/R
2
LLBus B
8–B15
Data to Bus A8–A
15
LHBus A
8–A15
Data to Bus B8–B
15
H X HIGH-Z State on A8–A15, B8–B
15
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74ACT16245
Absolute Maximum Ratings(Note 1) Recomm ended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut load ing vari ables. Fairchild does n ot
recommend operat ion of FACT circuits outside da t abook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds assoc iated with output under t es t .
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Supply Voltage (VCC) −0.5V to + 7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC +0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC +0.5V
DC Output Source/Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin ± 50 mA
Storage Temperature −65°C to +150°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to+85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2. 0 or VCC − 0.1V
V
IL
Maximum LOW 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0. 8 or VCC − 0.1V
V
OH
Minimum HIGH 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
OZT
Maximum I/O
5.5 ±0.5 ±5.0 µA
VI = VIL, V
IH
Leakage Current VO = VCC, GND
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
Leakage Current
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC −2.1V
I
CC
Max Quiescent
5.5 8.0 80.0 µAVIN = VCC or GND
Supply Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note3) −75 mA V
OHD
= 3.85V Min
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