Emerson MVME3100 Series, MVME3100-1152, MVME3100-1263, MVME721-101 Programmer's Reference Manual

MVME3100 Single Board Computer
Programmer’s Reference
6806800G37A
April 2008
©
Copyright 2008 Emerson
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2008 Emerson Electric Co.
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While reasonable efforts have been made to assure the accuracy of this document, Emerson assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Emerson reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Emerson to notify any person of such revision or changes.
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Contents
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Board Description and Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 Default Processor Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.2 MOTLoad’s Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.3 VME Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.4 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.5 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.6 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.7 System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.8 Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.9 PCI Bus Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3.10 Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.11 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.12 PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.13 PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.14 Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.15 Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.16 External Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.1 Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.3 Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.3.16.4 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3.17 Geographical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2 Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 MPC8540 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 Local Bus Controller Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6 User Configuration EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7 VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8 RTM VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.9 Ethernet PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.10 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
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Contents
2.11 PCI IDSEL Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.12 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.13 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.14 MPC8540 Real-Time Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.15 MPC8540 LBC Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.1 Emerson Network Power - Embedded Computing Documents . . . . . . . . . . . . . . . . . . . . . . . . 45
A.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
List of Figures
Figure 1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
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List of Figures
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
List of Tables
Table 1-1 MVME3100 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-2 MVME712-101 RTM Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 1-3 Default Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-4 MOTLoad’s Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-5 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-6 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-7 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-8 System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-9 Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-10 PCI Bus A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-11 PCI Bus B Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-12 PCI Bus C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-13 Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 1-14 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-15 PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-16 PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-17 Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-18 Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-19 Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 1-20 Tick Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 1-21 Tick Timer Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 1-22 Tick Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2-1 MPC8540 Power-on Reset Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-2 MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 2-3 LBC Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-4 I2C Bus Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-5 PHY Types and MII Management Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-6 Flash Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-7 IDSEL and Interrupt Mapping for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-8 Planar PCI Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 2-9 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-10 Clock Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table A-1 Emerson Network Power - Embedded Computing Publications . . . . . . . . . . . . . . . . . 45
Table A-2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table A-3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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List of Tables
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
About this Manual
Overview of Contents
This manual is divided into the following chapters and appendices:
Chapter 1, Board Description and Memory Maps, provides a brief product description and a
block diagram. The remainder of the chapter provides information on memory maps and system and configuration registers.
Chapter 2, Programming Details, provides additional programming information including IDSEL
mapping, interrupt assignments for the MPC8540 interrupt controller, Flash memory, two-wire serial interface addressing, and other device and system considerations.
Appendix A, Related Documentation, provides a listing of related Emerson manuals, vendor
documentation, and industry specifications.
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
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About this Manual
Abbreviations
Abbreviation Description
ATA Advanced Technology Attachment
CHRP Common Hardware Reference Platform
CMC Common Mezzanine Card
COM Communication
CPU Central Processing Unit
DDR Double Data Rate
DMA Direct Memory Access
DRAM Dynamic Random Access Memory
ECC Error Correction Code
FIFO First In First Out
GA General Availability
GMII Gigabit Media Independent Interface
GPCM General Purpose Chip select Machine
I/O Input/Output
IEEE Institute of Electrical and Electronics Engineers
KB Kilobytes
LBC Local Bus Controller
LED Light Emitting Diode
MB Megabyte
MHz Megahertz
MIIM MII Management
NVRAM Non Volatile RAM
PCI Peripheral Connect Interface
PCI-X Peripheral Component Interconnect -X
PHY Physical Layer
PIC Programmable Interrupt Controller
PIM PCI Mezzanine Card Input/Output Module
PLD Programmable Logic Device
PMC PCI Mezzanine Card (IEEE P1386.1)
POR Power-On Reset
PReP PowerPC Reference Platform
PrPMC Processor PMC
QUART Quad Universal Asynchronous Receiver/Transmitter
R/W Read/Write
RAM Random Access Memory
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Abbreviation Description
ROM Read Only Memory
RTC Real Time Clock
RTM Rear Transition Module
RTOS Real Time Operating System
SATA Serial AT Attachment
SBC Single Board Computer
SDRAM Synchronous Dynamic Random Access Memory
SIG Special Interest Group
SMT Surface Mount Technology
SPD Serial Presence Detect
TSEC Triple Speed Ethernet Controllers
TSOP Thin Small Outline Package
UART Universal Asynchronous Receiver/Transmitter
UNIX UNIX operating system
USB Universal Serial Bus
About this Manual
VIO Input/Output Voltage
VITA VMEbus International Trade Association
VME VersaModule Eurocard
VMEbus VersaModule Eurocard bus
Conventions
The following table describes the conventions used throughout this manual.
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word Screen Used for on-screen output and code related
Courier + Bold Used to characterize user input and to separate it
Reference Used for references and for table and figure
are 0 through F), for example used for addresses and offsets
elements or commands in body text
from system output
descriptions
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
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About this Manual
Notation Description
[text] Notation for software buttons to click on the screen
... Repeated item for example node 1, node 2, ...,
and parameter description
node 12
. . .
.. Ranges, for example: 0..4 means one of the
| Logical OR
Omission of information from example/command that is not necessary at the time being
integers 0,1,2,3, and 4 (used in registers)
Indicates a hazardous situation which, if not avoided, could result in death or serious injury
Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury
Indicates a property damage message
No danger encountered. Pay attention to important information
Summary of Changes
This manual has been revised and replaces all prior editions.
Part Number Publication Date Description
V3100A/PG1 First edition
6806800G37A April 2008 Updated to Emerson style.
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know what you think about our manuals and how we can make them better.
Mail comments to us by filling out the following online form:
http://www.emersonnetworkpowerembeddedcomputing.com/ > Contact Us > Online Form
In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part number, and revision of the manual and tell us how you used it.
About this Manual
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
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About this Manual
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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Board Description and Memory Maps
1.1 Introduction
This chapter briefly describes the board level hardware features of the MVME3100 single-board computer, including a table of features and a block diagram. The remainder of the chapter provides memory map information including a default memory map, MOTLoad’s processor memory map, a default PCI memory map, MOTLoad’s PCI memory map, system I/O memory map, and other configuration registers.
1.2 Overview
The MVME3100 is a single-slot, single-board computer based on the MPC8540 PowerQUICC III™ integrated processor. The MVME3100 provides serial ATA (sATA), USB 2.0, 2eSST VMEbus interfaces, dual 64-bit/100 MHz PMC sites, up to 256 MB of flash, dual 10/100/1000 Ethernet, one 10/100 Ethernet, and five serial ports. This board supports front and rear I/O and a single SODIMM module for DDR memory. Access to rear I/O is available with a rear transition module (RTM).
1
The MVME3100 Single-Board Computer Programmer’s Reference provides general programming information, including memory maps, interrupts, and register data for the MVME3100 family of boards. This document should be used by anyone who wants general, as well as technical information about the MVME3100 products.
As of the printing date of this manual, the MVME3100 supports the models listed below.
Model Number Description
MVME3100-1152 677 MHz MPC8540 PowerQUICC III
SDRAM, 64MB flash, Gigabit Ethernet, SATA, IEEE handles
MVME3100-1263 833 MHz MPC8540 PowerQUICC III integrated processor, 512MB DDR
SDRAM, 128MB flash, Gigabit Ethernet, SATA, USB, PCI expansion connector, IEEE handles
MVME721-101 Rear Transition Module, direct connect, 75mm, PIM socket for PMC-1 I/O,
four serial, 10/100/1000 Enet, 10/100 Enet
integrated processor, 256MB DDR
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