Denon DHT-500 Service Manual
For Europe model
SERVICE MANUAL
MODEL
HOME THEATER SYSTEM
HOME THEATER SYSTEM (DHT-500SD) consists of DVD SURROUND
RECEIVER (ADV-500SD) and SPEAKER SYSTEM (SYS-500SD).
DHT-500SD
注 意
Ver. 3
Please refer t o t he
MODIFICATION NOTICE.
For purposes of improvement, specifications and
●
design are subject to change without notice.
Please use this service manual with referring to
●
the operating instructions without fail.
Some illustrations using in this service manual are
●
slightly different from the actual set.
Denon Brand Company, D&M Holdings Inc.
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
● 本機の仕様は性能改良のため、予告なく変更すること
● 補修用性能部品の保有期間は、製造打切後
●
● 本文中に使用しているイラストは、説明の都合上現物
TOKYO, JAPAN
があります。
8年です。
修理の際は､必ず取扱説明書を参照の上、作業を行って,
ください。
と多少異なる場合があります。
X0198V.03 DE/CDM 0607
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the power
cord is less than 460 kohms, the unit is defective.
LASER RADIATION
Do not stare into beam or view directly with optical instruments, class 3A laser product.
DHT-500SD
CAUTION
Please heed the points listed below during servicing and inspection.
◎ Heed the cautions!
Spots requiring particular attention when servicing, such as
the cabinet, parts, chassis, etc., have cautions indicated on
labels or seals. Be sure to heed these cautions and the cautions indicated in the handling instructions.
◎ Caution concerning electric shock!
(1) An AC voltage is impressed on this set, so touching inter-
nal metal parts when the set is energized could cause
electric shock. Take care to avoid electric shock, by for example using an isolating transformer and gloves when
servicing while the set is energized, unplugging the power
cord when replacing parts, etc.
(2)There are high voltage parts inside. Handle with extra care
when the set is energized.
◎
Caution concerning disassembly and assembly!
Though great care is taken when manufacturing parts from
sheet metal, there may in some rare cases be burrs on the
edges of parts which could cause injury if fingers are moved
across them. Use gloves to protect your hands.
◎ Only use designated parts!
The set's parts have specific safety properties (fire resistance, voltage resistance, etc.). For replacement parts, be
sure to use parts which have the same properties. In particular, for the important safety parts that are marked ! on wiring
diagrams and parts lists, be sure to use the designated parts.
◎ Be sure to mount parts and arrange the
wires as they were originally!
For safety reasons, some parts use tape, tubes or other insulating materials, and some parts are mounted away from the
surface of printed circuit boards. Care is also taken with the
positions of the wires inside and clamps are used to keep
wires away from heating and high voltage parts, so be sure to
set everything back as it was originally.
◎ Inspect for safety after servicing!
Check that all screws, parts and wires removed or disconnected for servicing have been put back in their original positions, inspect that no parts around the area that has been
serviced have been negatively affected, conduct an insulation
check on the external metal connectors and between the
blades of the power plug, and otherwise check that safety is
ensured.
(Insulation check procedure)
Unplug the power cord from the power outlet, disconnect the
antenna, plugs, etc., and turn the power switch on. Using a
500V insulation resistance tester, check that the insulation resistance between the terminals of the power plug and the externally exposed metal parts (antenna terminal, headphones
terminal, microphone terminal, input terminal, etc.) is 1MΩ or
greater. If it is less, the set must be inspected and repaired.
CAUTION
Many of the electric and structural parts used in the set have
special safety properties. In most cases these properties are
difficult to distinguish by sight, and using replacement parts
with higher ratings (rated power and withstand voltage) does
not necessarily guarantee that safety performance will be preserved. Parts with safety properties are indicated as shown
below on the wiring diagrams and parts lists is this service
manual. Be sure to replace them with parts with the designated part number.
(1) Schematic diagrams ... Indicated by the ! mark.
(2) Parts lists ... Indicated by the ! mark.
Concerning important safety parts
Using parts other than the designated parts
could result in electric shock, fires or other
dangerous situations.
注 意
サービス、点検時にはつぎのことにご注意願います。
◎注意事項をお守りください！
サービスのとき特に注意を必要とする個所についてはキャ
ビネット、部品、シャーシなどにラベルや捺印で注意事項を
表示しています。これらの注意書きおよび取扱説明書などの
注意事項を必ずお守りください。
◎感電に注意！
(1) このセットは、交流電圧が印加されていますので通電時
に内部金属部に触れると感電することがあります。従っ
て通電サービス時には、絶縁トランスの使用や手袋の着
用、部品交換には、電源プラグを抜くなどして感電にご
注意ください。
(2) 内部には高電圧の部分がありますので、通電時の取扱に
は十分ご注意ください。
◎分解、組み立て作業時のご注意！
板金部品の端面の『バリ』は、部品製造時に充分管理をして
おりますが、板金端面は鋭利となっている箇所が有りますの
で、部品端面に触れたまま指を動かすとまれに怪我をする場
合がありますので十分注意して作業して下さい。手の保護の
ために手袋を着用してください。
◎指定部品の使用！
セットの部品は難燃性や耐電圧など安全上の特性を持った
ものとなっています。従って交換部品は、使用されていたも
のと同じ特性の部品を使用してください。特に配線図、部品
表に
!印で指定されている安全上重要な部品は必ず指定の
ものをご使用ください。
◎部品の取付けや配線の引きまわしは、
元どおりに！
安全上、テープやチューブなどの絶縁材料を使用したり、プ
リント基板から浮かして取付けた部品があります。また内部
配線は引きまわしやクランパーによって発熱部品や高圧部
品に接近しないように配慮されていますので、これらは必ず
元どおりにしてください。
◎サービス後は安全点検を！
サービスのために取り外したねじ、部品、配線などが元どお
りになっているか、またサービスした個所の周辺を劣化させ
てしまったところがないかなどを点検し、外部金属端子部
と、電源プラグの刃の間の絶縁チェックをおこなうなど、安
全性が確保されていることを確認してください。
（絶縁チェックの方法）
電源コンセントから電源プラグを抜き、アンテナやプラグな
どを外し、電源スイッチを入れます。500V 絶縁抵抗計を用
いて、電源プラグのそれぞれの端子と外部露出金属部［アン
テナ端子、ヘッドホン端子マイク端子、入力端子など］との
間で、絶縁抵抗値が１ MΩ 以上であること、この値以下の
ときはセットの点検修理が必要です。
注 意
本機に使用している多くの電気部品、および機構部品は安全
上、特別な特性を持っています。この特性はほとんどの場合、
外観では判別つきにくく、またもとの部品より高い定格（定
格電力、耐圧）を持ったものを使用しても安全性が維持され
るとは、限りません。安全上の特性を持った部品は、この
サービスマニュアルの配線図、部品表につぎのように表示し
ていますので必ず指定されている部品番号のものを使用願
います。
(1) 配線図…!マークで表示しています。
(2) 部品表…!マークで表示しています。
安全上重要な部品について
指定された部品と異なるものを使用した場合に
は、感電、火災などの危険を生じる恐れがあり
ます。
2
BLOCK DIAGRAM
MAIN P.W.B. UNIT ASS'Y
FRONT P.W.B. UNIT ASS'Y
VFD P.W.B.
MECHANISM(DVD LOADER:RL-874) P.W.B. UNIT ASS'Y
ST92F150CVT1
FROM DVD LOADER
3
TO AMP P.W.B. UNIT ASS'Y
TO CONNECTING P.W.B.
DSP P.W.B.
UNIT ASS'Y
AMP P.W.B. UNIT ASS'Y
CONNECTING P.W.B.
(TO VFD P.W.B. and Main P.W.B. UNIT ASS'Y)
HEAD PHONE P.W.B.
SMPS P.W.B. UNIT ASS'Y
DHT-500SD
LEVEL DIAGRAM
DHT-500SD
4
SEMICONDUCTORS / 半導体一覧表
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
● IC's
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注 ): IC No. の前の記号は、基板の名称を表します。
AMP: AMP P.W.B. ME: MECHANISM P.W.B. FR: FRONT P.W.B. SM: SMPS P.W.B.
MA: MAIN P.W.B. DS: DSP P.W.B.
ES6128F (ME: U9)
VSS
HA1
HA0
HCS3FX#
HCS1FX#
HIOCS16#
HRD#
HWR#
VEE
VSS
HIORDY
HRST#
HIRQ
HRDQ#
HWRQ#
HD15
HD14
VCC
VSS
HD13
HD12
HD11
HD10
HD9
HD8
HD7
VEE
VSS
HD6
HD5
HD4
HD3
HD2
HD1
HD0
VCC
VSS
HSYNC#
VSS
HA1
HA0
HCS3FX#
HCS1FX#
HIOCS16#
HRD#
HWR#
VEE
156
155
154
153
152
151
150
149
VEE
VEE
VEE
VEE
AUX[0]
AUX[0]
AUX[1]
AUX[1]
AUX[2]
AUX[2]
VSS
VSS
VEE
VEE
AUX[3]
AUX[3]
AUX[4]
AUX[4]
AUX[5]
AUX[5]
AUX[6]
AUX[6]
AUX[7]
AUX[7]
LOE#
LOE#
VSS
VSS
VCC
VCC
LCS0#
LCS0#
LCS1#
LCS1#
LCS2#
LCS2#
LCS3#
LCS3#
VSS
VEE
VSS
LD10
LD10
LD11
LD11
VSS
VEE
LD12
LD12
LD13
LD13
LD14
LD14
LD15
LD15
LWRLL#
LWRLL#
LWRHL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN0
CAMIN1
CAMIN1
VSS
156
155
154
153
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
LA4
LA5
LA6
LA4
LA5
LA6
VEE
VEE
HA2
HA2
VSS
LD0
LD0
LD1
LD1
LD2
LD2
LD3
LD3
LD4
LD4
VEE
VSS
LD5
LD5
LD6
LD6
LD7
LD7
LD8
LD8
LD9
LD9
VSS
VEE
VSS
VEE
LA0
LA0
LA1
LA1
LA2
LA2
LA3
LA3
VSS
157
157
158
158
159
159
160
160
161
161
162
162
163
163
164
164
165
165
166
166
167
167
168
168
169
169
170
170
171
171
172
172
173
173
174
174
175
175
176
176
177
177
178
178
179
179
180
180
181
181
182
182
183
183
184
184
185
185
186
186
187
187
188
188
189
189
190
190
191
191
192
192
193
193
194
194
195
195
196
196
197
197
198
198
199
199
200
200
201
201
202
202
203
203
204
204
205
205
206
206
207
207
208
208
148
152
151
150
149
148
LA7
LA8
LA9
LA7
LA8
LA9
VSS
VSS
VCC
VCC
ES6128 F Terminal Function
VSS
147
147
LA10
LA10
HIORDY
HRST#
146
145
146
145
LA11
LA12
LA11
LA12
HIRQ
144
144
LA13
LA13
HRDQ#
143
143
LA14
LA14
HWRQ#
HD15
142
141
142
141
LA15
LA16
LA15
LA16
HD14
140
140
VSS
VSS
VCC
139
139
VEE
VEE
VSS
138
138
LA17
LA17
HD13
137
137
LA18
LA18
HD12
136
136
LA19
LA19
HD11
135
135
LA20
LA20
HD10
134
134
LA21
LA21
HD9
133
133
RESET#
RESET#
HD8
132
132
TDMDX
TDMDX
HD7
131
131
VSS
VSS
VEE
130
130
VEE
VEE
VSS
129
129
TDMDR
TDMDR
HD6
128
128
TDMCLK
TDMCLK
HD5
127
127
TDMFS
TDMFS
HD4
126
126
TDMTSC#
TDMTSC#
HD3
125
125
TWS/SEL_PLL2
TWS/SEL_PLL2
HD2
124
124
TSD0/SEL_PLL0
TSD0/SEL_PLL0
HD1
123
123
VSS
VSS
HD0
122
122
VCC
VCC
VCC
121
121
TSD1/SEL_PLL1
TSD1/SEL_PLL1
VSS
120
120
TSD2
TSD2
VSYNC#
HSYNC#
VSYNC#
119
118
119
118
TSD3
TSD3
MCLK
MCLK
PCLKQSCN
PCLK2XSCN
YUV7
PCLKQSCN
PCLK2XSCN
YUV7
117
116
115
117
116
115
NC
NC
TBCK
TBCK
SPDIF/PLL3
SPDIF/PLL3
YUV6
YUV6
114
114
VSS
VSS
YUV5
YUV5
113
113
VCC
VCC
VSS
VSS
112
112
RSD
RSD
ADVEE
ADVEE
111
111
RWS
RWS
YUV4
YUV4
110
110
RBCK
RBCK
YUV3
YUV3
109
109
NC
NC
YUV2
YUV2
108
108
XIN
XIN
YUV1
YUV1
107
107
XOUT
XOUT
YUV0
YUV0
106
106
AVEE
AVEE
DCLK
DCLK
105
105
104
104
103
103
102
102
101
101
100
100
52
52
VSS
VSS
99
99
98
98
97
97
96
96
95
95
94
94
93
93
92
92
91
91
90
90
89
89
88
88
87
87
86
86
85
85
84
84
83
83
82
82
81
81
80
80
79
79
78
78
77
77
76
76
75
75
74
74
73
73
72
72
71
71
70
70
69
69
68
68
67
67
66
66
65
65
64
64
63
63
62
62
61
61
60
60
59
59
58
58
57
57
56
56
55
55
54
54
53
53
DHT-500SD
VEE
VEE
VSS
VSS
DSCK
DSCK
DQM
DQM
DCS0#
DCS0#
VEE
VEE
VSS
VSS
DCS1#
DCS1#
DB15
DB15
DB14
DB14
DB13
DB13
DB12
DB12
VEE
VEE
VSS
VSS
DB11
DB11
DB10
DB10
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB6
VSS
VSS
VCC
VCC
DB5
DB5
DB4
DB4
DB3
DB3
DB2
DB2
DB1
DB1
DB0
DB0
VSS
VSS
VEE
VEE
DMBS1
DMBS1
DMBS0
DMBS0
DRAS#
DRAS#
DWE#
DWE#
DSCK_EN
DSCK_EN
DCAS#
DCAS#
VEE
VEE
VSS
VSS
DMA11
DMA11
DMA10
DMA10
DMA9
DMA9
DMA8
DMA8
DMA7
DMA7
DMA6
DMA6
VSS
VSS
VEE
VEE
DMA5
DMA5
DMA4
DMA4
DMA3
DMA3
DMA2
DMA2
DMA1
DMA1
DMA0
DMA0
1, 18, 27, 59,
68, 75, 92, 99,
104, 130, 148, VEE I I/O power supply.
157, 159, 164,
183, 193, 201
8, 17, 26, 34,
43, 52, 60, 67,
76, 84, 91, 98,
103, 112, 120, VSS I Ground.
129, 138, 147,
156, 163, 171,
177, 184, 192,
200, 208
23:19, 16:10,
7:2, 207:204
9, 35, 44, 83,
121, 139, 172
LA[21:0] O Device address output.
VCC I Core power supply.
FunctionI/OPin No. Pin Name
5
DHT-500SD
Pin No. Pin Name
24 RESET# I Reset input, active low.
25 TDMDX O TDMtransmit data.
28 TDMDR I TDM receive data.
29 TDMCLK I TDM clock input.
30 TDMFS I TDM frame sync.
31 TDMTSC# O TDMoutput enable.
TWS O Audio transmit frame sync.
SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
SEL_PLL2 SEL_PLL1 SEL_PLL0 ClockType
0 0 0 VCO off.
001DCLK
32 0 1 0 Bypass mode
0 1 1 DCLK x 2
1 0 0 DCLK x 4.5
1 0 1 DCLK x 3
1 1 0 DCLK x 3.5z
1 1 1 DCLK x 4
33
36
37 TSD[2] O Audio transmit serial data output 2.
38 TSD[3] O Audio transmit serial data output 3.
39 MCLK I/O Audio master clock for audio DAC.
40 TBCK O Audio transmit bit clock.
41 SEL_PLL3 Clock Source
42,48 NC No connect pins. Leave open.
45 RSD I Audio receive serial data.
46 RWS I Audio receive frame sync.
47 RBCK I Audio receive bit clock.
49 XIN I Crystal input.
50 XOUT O Crystal output.
51 AVEE I Analog power for PLL.
66:61, 58:53 DMA[11:0] O DRAM address bus [11:0]
69 DCAS# O DRAM column address strobe,
70 DSCK_EN O DRAM clock enable.
71 DWE# O DRAM write enable.
72 DRAS# O DRAM row address strobe.
73 DMBS0 O SDRAM bank select 0.
74 DMBS1 O SDRAM bank select 1.
96:93, 90:85,
82:77
97, 100 DCS[1:0]# O SDRAM chip select [1:0]
101 DQM O Data input/output mask.
102 DSCK O Output clock to SDRAM.
105 DCLK I 27 MHz clock input to PLL.
106 UDAC O Video UDAC output.
107 VREF I Internal voltage to video DAC.
108 CDAC O Video CDAC output.
109 COMP I Compensation input.
110 RSET I DAC current adjustment resistor input.
111 ADVEE I Analogpower for video DAC.
113 YDAC O Video YDAC output.
TSD0 O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
TSD1 O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
SPDIF O S/PDIF output.
SEL_PLL3 I Clock source select.
0 Crystal oscillator
1 DCLK input
DB[15:0] I/O DRAM data bus [15:0]
FunctionI/O
6
DHT-500SD
Pin No. Pin Name
114 VDAC O Video VDAC output.
115 YUV7 O YUV7 pixel output data.
116 PCLK2XSCN I/O 27 MHz video output pixel clock.
117 PCLKQSCN O 13.5 MHz video output pixel clock.
118 VSYNC# I/O Vertical sync, active low.
119 HSYNC# I/O Horizontal sync, active low.
127:122 HD[5:0] I/O Host data I/O [5:0].
128 HD[6] I/O Host data I/O [6].
131 HD[7] I/O Host data I/O [7].
132 HD[8] I/O Host data bus 8.
133 HD[9] I/O Host data bus line 9.
134 HD[10] I/O Host data bus line 10.
135 HD[11] I/O Host data bus line 11.
136 HD[12] I/O Host data bus line 12.
137 HD[13] I/O Host data bus line 13.
140 HD[14] I/O Host data bus line 14.
141 HD[15] I/O Host data bus line 15.
142 HWRQ# O Host write request.
143 HRRQ# O Host read request.
144 HIRQ I/O Host interrupt.
145 HRST# O Host reset.
146 HIORDY I HostI/O ready.
149 HWR# I/O Host write.
150 HRD# O Host read.
151 HIOCS16# I Device16-bit data transfer.
152 HCS1FX# O Host select 1.
153 HCS3FX# O Host select 3.
158, 155:154 HA[2:0] I/O Host address bus.
160 AUX[0] O I
162 AUX[2] I/O Auxiliary ports 2.
165 AUX[3] I/O Auxiliary ports 3.
169:166 AUX[7:3] I/O Auxiliary ports 7:3.
170 LOE# O Device output enable.
176:173 LCS[3:0]# O Chip select [3:0].
197:194,
191:185, LD[15:0] I/O EPROM device data bus.
182:178
198 LWRLL# O Device low-byte write enable.
199 LWRHL# O Device high-byte write enable.
202 CAMIN0 I CameraYUV 0.
203 CAMIN1 I CameraYUV 1.
161 AUX[1]OI
2
C DATA.
2
CCLK.
FunctionI/O
7
M5705 (ME: U1)
AVSS-DS
XSRFIN
XSIPIN
AVDD5-D S
XSDSSLV
XSRSLINT
XSAWRC
XSRFGC
XSEFGC
XSFOCUS
XSTRACK
XSSLEG
AVDD5-D A
XSMOTOR
AVSS-DA
XSRFRPLP
XSTELP
XSVREF2
XSRFRP
XSTEXI
AVSS-AD
XSTEI
XSFEI
XSAEI
AVDD5-A D
XSSBAD
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG(3)
XSFLAG(2)
XSFLAG(1)
XSFLAG(0)
XMP1_7
XMP1_6
XMP1_4
XSAWRCVCO
XSVREFO
XSPDOFTR2
XSVR_PLL
XSFTROPI
XSFDO
AVSS_PL
XSPLLFTR2
AVDD5_PL
XSFDIREF
XSPDIREF
GND
XTSLRF
XTPLCK
VDD
XRA(3)
XRA(2)
XRA(1)
XRA(0)
XRA(4)
XRA(5)
XRA(6)
GND
XRA(7)
XRA(10)
XRA(11)
VDD
XRA(8)
XRA(9)
XROEJ
VDD
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
1
2
3
4
5
6
VDD
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GND
28
29
30
31
32
33
34
35
36
37
38
39
40
41
GND
42
NC
43
44
45464748495051525354555657585960616263646566676869707172737475767778798081828384858687
VDD
VDD
GND
XOSC1
XOSC2
XMP1_3
XMFSCSJ
XMP1_2
XGPIO(2)
XMP1_1
XMRSTJ
XGPO(1)
XGPO(0)
XCRSTJ
XMPSENJ
XMALE
XMP1_0
XMD(0)
XMD(1)
XMD(2)
XMD(3)
XMD(4)
XMD(5)
XMD(6)
XMD(7)
146
XMCSJ
XMRDJ
XMWRJ
XMA(11)
XMA(10)
XMINT1J
4M DRAM
M5705
XRCASJ
XRRASJ
145
144
VDD
XMA(9)
XRSDCLK
XRWEJ
143
142
XMA(8)
XMA(7)
XRD(7)
141
XMA(6)
XRD(8)
140
XMA(5)
XRD(6)
139
XMA(4)
GND
138
XMA(3)
XRD(9)
137
XMA(2)
XRD(5)
136
XMA(1)
XRD(10)
XRD(4)
135
134
XMA(0)
XMA(12)
XRD(11)
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
88
GND
99
98
97
96
95
94
93
92
91
90
89
XRD(3)
XRD(12)
GND
XRD(2)
XRD(13)
XRD(1)
XRD(14)
XRD(0)
XRD(15)
XHD(7)
XHD(8)
XHD(6)
XHD(9)
XHD(5)
XHD(10)
XHD(4)
XHD(11)
VDD
XHD(3)
XHD(12)
XHD(2)
XHD(13)
GND
XHD(1)
XHD(14)
XHD(0)
XHD(15)
XHDRQ
XHIOWJ
XHIORJ
XHIORDY
XHDACKJ
XHINT
XHCS16J
XHA(1)
XHPDIAGJ
XHA(0)
XHA(2)
XHCS1J
XHCS3J
XHDASPJ
XMA(15)
XMA(14)
XMA(13)
DHT-500SD
ATAPI
M
Motor
Driver
Data
Separator
Digital
Servo
DVD-DSP
CD-DSP
RAM
Arbiter
Targe t
Search
&
MPEG
I/F
C3 ECC
EDC
MCU
ROM
M5705 Terminal Function
Pin Name
Type
2 XSRFIN I/A Analog RF signal input after passing through the equalizer
3 XSIPIN I/A Inverting input pin of data slicer
5 XSDSSLV O/A Slice level output pin
6 XSRSLINT I/A Reference current setting pin for analog data slicer
8 XSAWRC O/A Output for enlarge VCO range. Analog output from DAC buffer
9 XSRFGC O/A RFgain control output
10 XSEFGC O/A E,F gain control output
11 XSFOCUS O/A Output voltage level for focusing buffer IC
12 XSTRACK O/A Output voltage level for tracking buffer IC
13 XSSLEG O/A Output voltage level for sledge buffer IC
15 XSMOTOR O/A Output voltage level for spindle motor buffer IC
17 XSRFRPLP I/A High bandwidth low pass filter input for RFRP
18 XSTELP I/A High bandwidth low pass filter input forTE
19 XSVREF2 I/A 2.1V reference voltage input
20 XSRFRP I/A RF ripple/envelope signal input
21 XSTEXI I/A Tracking zero crossing input signal
23 XSTEI I/A Tracking error input signal
24 XSFEI I/A Focus error input signal
25 XSCEI I/A
1. Center error input signal
2. Photo Interrupt input
DescriptionPin No.
PC
MPEG
DEC.
8
DHT-500SD
Pin Name
27 XSSBAD I/A Sub-beam addition signal input
166 XSPDIREF I/A
167 XSFDIREF I/A
169 XSPLLFTR2 I/A Data PLL loop filter pin#2
171 XSFDO O/A Output node of frequency detector charge pump circuit
172 XSFTROPI I/A Input node of loop filter OP circuit
173 XSVR_PLL I/A PLL reference voltage input
174 XSPDOFTR2 I/A Phase detector filter pin#1
175 XSVREFO O/A Reference voltage output
176 XSAWRCVCO I/A Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29 XSDFCT I Detect detection signal input
30 XSCSJ O Chip select signal for accessing control registers
31 XSCLK O Clock output for accessing control registers
32 XSDATA I/O Registers data input/output pin
33 XSLDC O Laser diode on/off control output for both CD/DVD
34 XSFGIN I Motor Hall sensor input
35 XSSPDON O Spindle motor on output
36, 37, 38, 39 XSFLAG[3:0] O These pins are used to monitor some status of servo control block
48, 51, 52 XGPIO[2:0] I/O
40 XMP1_7 I/O Internal microcontroller programmable I/O port 1.7.
41 XMP1_6 I/O Internal microcontroller programmable I/O port 1.6.
43 XMP1_5 I/O This pin is now changed to be NC.
44 XMP1_4 I/O Internal microcontroller programmable I/O port 1.4.
45 XMP1_3 I/O Internal microcontroller programmable I/O port 1.3.
47 XMP1_2 I/O Internal microcontroller programmable I/O port 1.2.
49 XMP1_1 I/O Internal microcontroller programmable I/O port 1.1.
57 XMP1_0 I/O
46 XMFSCSJ I/O Output chip select connected to external flash ROM chip enable pin
54 XMPSENJ I/O Output program store enable connected to external ROM PSENJ pin.
56 XMALE I/O This signal is used as address latch signal in address/data mux mode
70 XMCSJ I/O
71 XMRDJ I/O
72 XMWRJ I/O This signal is used as the Wire Strobe signal
73 XMINT1J I/O
74, 75, 77, 78,
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65,
66, 67, 68, 69 bus for the 8-bit processor mode.
163 XTPLCK I/O PLCK test pin
164 XTSLRF I/O SLRF test pin
59 XOSC1 I Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60 XOSC2 O Crystal output
53 XCRSTJ I
94 XHCS1J I This pin is used to select the command block task file registers
93 XHCS3J I This pin is used to select the control block task file registers
103 XHIORJ I Asserted by the host during a host I/O read operation
104 XHIOWJ I Asserted by the host during a host I/O write operation
105 XHDRQ O
101 XHDACKJ I
99 XHCS16J O
50 XHRSTJ I Host Reset. The reset of ATA bus
100 XHINT O
XMA[15:0] I/O These pins are used as address bus
XMD[7:0] I/O
Type
Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
These pins are used as data bus for the 16-bit processor mode, or the address/data mux
Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
1.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2.
MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
DescriptionPin No.
9
DHT-500SD
Pin Name
97 XHPDIAGJ I/O This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92 XHDASPJ I/O
102 XHIORDY I/O
95, 96, 98 XHA[2:0] I
106, 107, 108, 2.
109, 111, 112, 3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116, bit3-0 and VCD I/F is as follow
117, 118, 119, HD0—CD-DATA
120, 121, 122, HD1—CD-LRCK
123 HD2—CD-BCK
143 XRSDCLK O This signal is the clock output for SDRAM
147 XROEJ O
142 XRWEJ O This signal is asserted low when a buffer memory write operation is active
144 XRRASJ O
145 XRCASJ O
148, 149, 151,
152, 153, 155,
156, 157, 158,
159, 160, 161
124, 125, 126,
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4 AVDD5_DS Analog Power +5V for Data Slicer part
14 AVDD5_DA Analog Power +5V for DAC part
26 AVDD5_AD Analog Power +5V for ADC part
168 AVDD5_PL Analog Power +5V for Data PLL part
7, 55, 58, 76,
115, 146,
150, 162
1 AVSS_DS Analog Ground for Data Slicer part
16 AVSS_DA Analog Ground for DAC part
22 AVSS_AD Analog Ground for ADC part
170 AVSS_PL Analog Ground for Data PLL part
28, 42, 61,
88, 110, 130,
138, 154, 165
XHD[15.0] I/O
XRA[11:0] O 1: Normal operation
XRD[15:0] I/O These signals are the 8-bit parallel data lines to/from the buffer memory.
VDD Power +3.3V for digital core logic and pad
GND Digital Ground core logic and pad.
Type
This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
HD3—CD-C2PO
This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
0: By registers to decide input/output
RA[6] : System test pin output
0: System test pin output
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (inter nal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
DescriptionPin No.
10
SP3721A (ME: U2)
CDRF
CDRDDC
DHT-500SD
HOLD1
VNA
FNN
FNP
DIP
DIN
RX
BYP
SIGO
VPA
AIP
AIN
ATON
ATOP
49505152535455565758596061626364
DVDRFP
DVDRFN
PD1
PD2
CP
CN
A2
B2
C2
D2
1
2
3
4
5
6
7
8
9
10
11
D
12
C
13
B
14
A
15
F
16
E
NC
VCI2
CDTE
TOP VIEW
VNB
DVDLD
DVDPD
CDLD
CDPD
VC
LDON#
VCI
VPB
VIIRR
VIP
32313029282726252423222120191817
VIB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FDCHG#
SDEN
SDATA
SCLK
LCP
LCN
CE
FE
TE
MEI
MEV
TPH
DFT
PI
MIN
MEVO
MLPF
SP3721A Terminal Function
Pin Name
Type
1, 2 DVDREP, DVDREN I RF Signal Inputs.Differential RF signal attenuator input pins
63 CDRF I RF Signal Inputs.Single-ended RF signal attenuator input pin
59, 60 AIP, AIN I AGC Amplifier Inputs.Differential AGC amplifier input pins
53, 54 DIP, DIN I
Analog inputs for RF Single Buffer.Differential analog inputs to the RF single-ended output buffer
and full wave rectifier
Low Impedance Enable.A TTL compatible input pin that activates the FDCHG switches. A low
32 FDCHG# I
level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for
the MIRR bottom hold circuit. (open high)
49 HOLD1 I
Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge
pump and holds the RF AGC amplifier gain at its present value.(open high)
11~14 D, C, B, A I Photo Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs
5~8 A2, B2, C2, D2 I
Photo Detector Interface Inputs.AC coupled inputs for the DPD from the main beam Photo
detector matrix outputs
15~16 F, E I CD tracking Error Inputs. Inputs from the CD photo detector error outputs.
3~4 PD1, PD2 I CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs
40 MEI I Mirror Envelope Inputs.The SIGO envelope input pin
35 MIN I
RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal
output. (PI)
21 DVDPD I APC Input. DVD APC input pin from the monitor photo diode
23 CDPD I APC Input. CD APC input pin from the monitor photo diode
25 LDON# I APC Output On/Off.APC output control pin. A low level activates the LD output. (open high)
61, 62 ATON/ATOP O DifferentialAttenuator Output. Attenuator outputs
51, 52 FNN, FNP O Differential Normal Output. Filter normal outputs
57 SIGO O Single Ended Normal Output. Single-ended RF output
64 CDRFDC O CD RF Signal Output. Single ended CD RF summing output
42 FE O FocusingError Signal Output. Focus error output reference to VCI
41 TE O Tracking Error Signal Output. Tracking error output reference to VCI
DescriptionPin No.
11
DHT-500SD
Pin Name
43 CE O Center Error Signal Output. Center error output reference to VCI
34 NEVO O SIGO Bottom Envelope Output. Bottom envelope for mirror detection
37 DFT O
29 MIRR O Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output
36 PI O
22 DVDLD O APC output. DVD APC output pin to control the laser power
24 CDLD O APC output. CD APC output pin to control the laser power
56 BYP I/O The RF AGC integration capacitor CBYP, is connected between BYP and VPA
9 CP I/O
10 CN I/O
45 LCP — Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin
44 LCN — Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin
30 MP — MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB
31 MB — MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB
39 MEV — Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB
17 CDTE — CD Tracking. E-F Opamp output for feedback
38 TPH — PI Top Hold pin. An external capacitance is connected to between this pin and VPB
26 VC —
27 VCI — Reference Voltage input. DC bias voltage input for the servo input reference
18 VCI2 — Reference Voltage input. DC bias voltage input for the servo input reference
55 RX —
33 MLPF — MIRR signal LPF pin. An external capacitance is connected between this pin and VPB
19 NC — No Connect
48 SDEN I
47 SDATA I/O
46 SCLK I
58 VPA Power. Power supply pin for the RF block and serial port
28 VPB Power. Power supply pin for the servo block
50 VNA Ground. Ground pin for the RF block and serial port
20 VNB Ground. Ground pin for the servo bolck
Type
Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also
the servo AGC output can be monitored at this pin, when CAR bits 7-4 are ‘0011’
Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection.
Reference to VCI
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CN pin
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CP pin
Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix).
Output Impedance is less than 50ohms
Reference Resistor Input. An external 8.2kohm, 1% resistor is connected from this pin to ground
to establish a precise PTAT (proportional to absolute temperature) reference current for the filter
Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be
left open)
Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers
is applied to this input ( Not to be left open)
Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data
applied to SDATA (Not to be left open)
DescriptionPin No.
12
HY57V651620BTC-75 (ME: U11)
DHT-500SD
DD
V
DQ0
V
DDQ
DQ1
DQ2
SSQ
V
DQ3
DQ4
DDQ
V
DQ5
DQ6
V
SSQ
DQ7
DD
V
LDQM
/W E
/CAS
/RAS
/CS
BA0
BA1
A10/ A P
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
SS
V
DQ15
V
SSQ
DQ14
DQ13
DDQ
V
DQ12
DQ11
SSQ
V
DQ10
DQ9
V
DDQ
DQ 8
SS
V
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock
CKE Clock Enable
CS
BA0,BA1 Bank Address
A0 ~ A11 Address
RAS
, CAS,WE
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
V
DD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
V
DDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Chip Select Enables or disables all inputs except CLK, CKE and DQM
Row Address Strobe,
Column Address Strobe,
Write Enable
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Selects bank to be activated during RAS
Selects bank to be read/written during CAS
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS
, CAS and WE define the operation
Refer function truth table for details
activity
activity
13
T431616A-8S(ME:U5)
DHT-500SD
DD
V
DQ0
DQ1
SSQ
V
DQ2
DQ3
DDQ
V
DQ4
DQ5
V
SSQ
DQ6
DQ7
DDQ
V
LDQM
WE
CAS
RAS
CS
BA
A10/ AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SS
V
DQ15
DQ14
V
SSQ
DQ13
DQ12
DDQ
V
DQ11
DQ10
SSQ
V
DQ9
DQ8
V
DDQ
N.C / RFU
UDQM
CL K
CK E
N.C
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK System Clock
CS
CKE Clock Enable
A0 ~ A10/AP
BA Bank Select Address
RAS
CAS
WE
L(U)DQM Data Input/Output Mask
DQ0 ~ DQ15
DD/VSS Power Supply/Ground
V
VDDQ/VSSQ
N.C/RFU
Chip Select
Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output
Data Output Power/Ground
No Connection/Reserved
for Future Use
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Powe and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
SHZ after the clock and masks the output.
14
MX29LV800ABTC-70 (ME: U10)
NC
WE
NC
NC
1
2
3
4
5
6
7
A9
8
A8
9
10
11
12
13
14
15
16
17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
A15
A14
A13
A12
A11
A10
A19
RESET
RY/BY
A18
A17
BLOCK DIAGRAM
DHT-500SD
48
A16
47
BYTE
46
GND
45
Q15/A-1
44
Q7
43
Q14
42
Q6
41
Q13
40
Q5
39
Q12
38
Q4
37
VCC
36
Q11
35
Q3
34
Q10
33
Q2
32
Q9
31
Q1
30
Q8
29
Q0
28
OE
27
GND
26
CE
25
A0
CE
OE
WE
RESET
A0-A19
CONTROL
INPUT
LOGIC
ADDRESS
LATCH
AND
BUFFER
PROGRAM/ERASE
HIGH VOLTAGE
X-DECODER
FLASH
ARRAY
Y-DECODER
Y-PASS GATE
SENSE
AMPLIFIER
ARRAY
SOURCE
PGM
DATA
HV
HV
WRITE
S TAT E
MACHINE
(WSM)
STATE
REGISTER
COMMAND
DA TA
DECODER
COMMAND
DATA LATCH
Q0-Q15/A-1
PROGRAM
DATA L AT C H
I/O BUFFER
15
BH7862FS (MAIN:IC11)
DHT-500SD
01CTRAP
02MUTE1 MUTE1
CIN
03
04GND
05YIN
06VCC
07GND
08PYIN
09GND
10PYTRAP
11VCC
12PbIN
13GND
14PrIN
15MUTE2
1.5-6M
20k
CLAMP
CLAMP
20k
20k
MUTE2
BPF
LPF
12M
LPF
LPF
LPF
6M
6M
6M
6dB
6dB
6dB
6dB
6dB
75ohm
75ohm
75ohm
75ohm
75ohm
TEST
32
31
30
29
28
27
22
21
20
19
18
COUT
TEST
MIXOUT
MIXFB
GND
YTRAP
GND26
YOUT25
YFB24
GND23
PYOUT
PYFB
GND
PbOUT
N.C.
16PrTRAP
6dB
75ohm
BH7862FS Terminal Function
Pin No.
Port
1 CTRAP
10 PYTRAP
16 PrTRAP
Pin for LC resonation
27 YTRAP
2 MUTE1 Mute control pin, L: C, MIX,Y simultaneous mute
3CIN
12 PbIN Signal input pin, chroma signal & color-difference signal
14 PrIN
4, 7, 9, 13, 20, 23, 26, 28
GND GND pin
5 YIN Signal input pin, luminance signal
8 PYIN
6
11 Powersupply for PY, Pb, Pr
VCC
Powersupply for C, MIX,Y
15 MUTE2 Mute control pin, L: PY,Pb, Pr simultaneous mute
17 PrOUT
19 PbOUT
Signal output pin, color-difference signal
18 N.C.
21 PYFB
22 PYOUT
24 YFB
25 YOUT
29 MIXFB
30 MIXOUT
Signal output pin, luminance signal (progressive)
Signal output pin, luminance signal (interlace)
Signal output pin,Y/C MIX signal
31 TEST TEST pin
32 COUT Signal output pin, chroma signal
Description
17
PrOUT
16
AT49F001N-70JC(ME:U3)
I
4
3
1
0
7
G
*
P
A12
A15
A16
432
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
/O0
14151617181920
ND
I/O1
I/O2
*Note: This pin is a DC on the AT49F001N(T).
FAN8024BDTF(ME:U6)
RESET
VCCWENC
1
323130
I/O3
I/O4
I/O5
29
28
27
26
25
24
23
22
21
I/O6
DHT-500SD
Pin Configurations
Pin Name Function
A0 - A16 Addresses
A1
A1
A8
A9
A1
OE
A1
CE
I/O
CE
OE
Chip Enable
Output Enable
WE Write Enable
RESET
RESET
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
STBY
REF
IN4
CAP4.1
CAP4.2
7
5
.
-
IN2.2
IN3
K
X
2
67
OUT2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
+
S
T
D
-
+
K
0
-
2
+
K
0
1
12345
IN1
K
0
1
K
5
.
-
+
K
5
.
7
CAP1.1
7
K
0
2
-
7
.
K
5
+
IN2.1
CAP1.2
VCCGND
X
FB1
GND
2
0
1
GND
K
PVCC2
V
P
C
C
2
1
0
K
+
-
5
2
K
V
P
V
C
C
89
VCC
FB4
PGND2
DO3−DO3+
5
1
K
-
+
1
C
C
VCC1
10 11
PGND1
Loading
Driver
Sled
Driver
−
DO2
DO4−DO4+
Actuator
Driver
V
P
C
C
1
V
P
2
C
C
V
C
C
Actuator
Driver
12
13 14
−
DO1+
DO1
DO2+
Pin Definitions
Pin Number Pin Name I/O Pin Function Description
1 IN1 I CH1 input
2 CAP1.1 - Connection with capacitor
3 CAP1.2 - for CH1
4 IN2.1 I OP-AMP CH2 input(+)
5 IN2.2 I OP-AMP CH2 input(-)
6 OUT2 O OP-AMP CH2 output
7 FB1 I Feedback for CH1
8 V C C - Signal Vcc
9 PVCC1 - Power Supply 1
10 PGND1 - Power Ground 1
11 DO2
−
O Drive2 Output (-)
12 DO2+ O Drive2 Output (+)
13 DO1
−
O Drive1 Output (-)
14 DO1+ O Drive1 Output (+)
15 DO4+ O Drive4 Output (+)
16 DO4
−
O Drive4 Output (-)
17 DO3+ O Drive3 Output (+)
18 DO3
−
O Drive3 Output (-)
19 PGND2 - Power Ground 2
20 FB4 - Feedback for CH4
21 PVCC2 - Power Supply 2
22 VCCGND - Vcc ground
23 IN3 I CH3 input
24 CAP4.2 - Connection with capacitor
25 CAP4.1 - for CH4
26 IN4 I CH4 input
27 RE F I Bias voltage input
28 S T BY I Stand-by input
17
FAN8423D3TF(ME:U7)
CS1
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1234567
NC
Pin Definitions
Pine Number Pin Name I/O Pin Function Description
1 NC - No connection
2 A3 O Output (A3)
3 NC - No connection
4 A2 O Output (A2)
5 NC - No connection
6 NC - No connection
7 A1 O Output (A1)
8 GND - Ground
9 H1+ I Hall signal (H1+)
10 H1- I Hall signal (H1-)
11 H2+ I Hall signal (H2+)
12 H2- I Hall signal (H2-)
13 H3+ I Hall signal (H3+)
14 H3- I Hall signal (H3-)
15 VH I Hall bias
16 NC - No connection
17 PC1 - Phase compensation capacitor
18 SB I Short brake
19 FG3X O FG waveform (3X)
20 DIR O Rotational direction output
21 ECR I Output current control reference
22 EC I Output current control voltage
23 S/S I Power save (Start/Stop switch)
24 FG1X O FG waveform (1X)
25 VCC - Supply voltage (Signal)
26 NC - No connection
27 VM - Supply voltage (Motor)
28 CS1 - Output current detection
DHT-500SD
GND
VM
NC
VCC
FG1X
FG1X
Generator
A3
A2
NC
NC
S/S
Stop
Start
NC
EC
Current Sense
Amp
A1
-
+
Output
Current Limit
GND
Absolute
Values
Upper
Lower
ECR
DIR
FG3X
SB
PC1
Short
Brake
FG3X
Generator
tion
Logic
Reverse Rota-
tor
tion
Direc-
Distribu-
Distribu-
8
91011121314
GND
Detec-
Selector
Commutation
H1+
Hall Amp
H1-
H2-
H2+
NC
TSD
H3+
VH
Hall
H3-
CS4392(ME:U16)
RST
VL
SDATA
SCLK
LRCK
MCLK
M3
(SCL/CCLK) M2
(SDA/CDIN) M1
(AD0/CS) M0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AMUTEC
AOUTA-
AOUTA+
VA
AGND
AOUTB+
AOUTB-
BMUTEC
CMOUT
FILT+
RST
SCLK
LRCK
SDATA
M1
(SDA/CDIN) (SCL/CCLK) (AD0/CS)
SERIAL
PORT
M2 M0
M3
MODE SELECT
( CONTROL PORT)
VOLUME
CONTROL
MIXER
VOLUME
CONTROL
INTERPOLATION
FILTER
INTERPOLATION
FILTER
18
AMUTEC BMUTEC CMOUT FILT+
EXTERNAL
MUTE CONTROL
MCLK
△
DAC
△
DAC
Σ
Σ
REFERENCE
ANALOG
FILTER
ANALOG
FILTER
AOUTA+
AOUTA-
AOUTB+
AOUTB-
SN74HCU04PWR (ME: U8)
Block Diagram
1
1A
1Y
2A
2Y
3A
3Y
GND
2
3
4
5
6
7
14
13
12
11
10
9
8
AT24C02N(ME: U13)
DHT-500SD
Vcc
6A
6Y
5A
5Y
4A
4Y
A0
A1
A2
GND
1
2
3
4
VCC
8
WP
7
SCL
6
SDA
5
NPC1117ST20T3(ME: Q4)
LM117S-3V3 (DS:IC33)
LM117S-2V5 (DS:IC32)
3
V6309M(ME: Q5)
IN
V
OUT
2
1
KA78L08AZ (SM: IC93)
FRONT
VIEW
GND
Input
Output
OUT
ADJ/GND
KA79L08AZ (MA: IC17)
FRONT
VIEW
GND
Input
Output
19
LC75725E(FR:IC91)
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DHT-500SD
S24
BLK
VFL
S8
S7
S6
S5
S4
S3
S2
S1
Vss
OSC0
OSC1
V
BLK
CE
CL
49
50
51
52
53
54
55
56
57
58
59
DD
60
61
62
63
64
DI
G11
DRIVER
DIGIT
1 2 3 4 5 6 7 8 9 10111213141516
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
VFL
G10G2G1
S43
S42
SEGMENT DRIVER
MPX
LATCH
VFL
S43
S42
S41
32
S25
31
S26
S27
30
29
S28
28
S29
27
S30
26
S31
25
S32
24
S33
23
S34
22
S35
21
S36
20
S37
19
S38
18
S39
17
S40
S2
S1
GRID
CONTROL
DIMMER
TIMING
GENERATOR
SHIFT REGISTER
TIMING
GENERATOR
DIVIDER
OSCI
OSCO
CLOCK
GENERATOR
Terminal Function
Pin No. I/O Name Function
O
O
-
O
I
-
I
I
I
I
FL
V
G1~G11
S1~S43
Vss
DD
CL
DI
Power supply pin to ligic block
CE : Chip enable
CL : Sync clock
DI : Transfer data
1,13 Power supply pin to driver block
2~12 Digit output pin
14~56 Segment output pin
57 power supply pin
58 OSCO Pin for oscillator
59 OSCI Pin for oscillator
60 V
61 BLK Display off input pin
62 CE Input for serial data transfer
63
64
DI
CL
ADDRESS
DETECTOR
CE
VSS
DD
V
20
ST92F150CVT1(MAIN:IC11)
Pin Configuration (Top-view TQFP100)
P9.5/A19
100 99 98 97 96 95 94 9392 91 90 89 8887 86 8584 83 82 81 8079 78 7776
1
A20/P9.6
2
A21/P9.7
V
V
/P3.4
3
4
5
6
7
8
9
10
11
12
13
14
SS
15
DD
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 3132 33 3435 36 37 38 3940 41 4243 44 45 46 4748 49 50
MOSI/P3.6
TX0/WAIT
RX0/WKUP6/WDOUT/P5.1
/WKUP5/P5.0
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS
MISO/P3.5
*V
must be kept low in standard operating mode.
TEST
DHT-500SD
SS
P9.4/A18
P9.2/A16
P9.3/A17
P9.0/RDI
P9.1/TDO
RW
REG
V
TINPA0/P2.0
SCK/WKUP0/P3.7
DD
HW0SW1
P7.7/AIN15/7/WKUP13
RESET
OSCOUT
P7.6/AIN14/WKUP12
OSCIN
P7.5/AIN13/WKUP11
V
V
ST92F150CVT1
(MAIN:IC11)
SS
DD
V
V
REG
V
TINPB0/P2.1
TINPB1/P2.5
TINPA1/P2.4
TOUTA0/P2.2
TOUTB0/P2.3
TOUTB1/P2.7
TOUTA1/P2.6
P7.4/AIN12/WKUP3
P7.1/AIN9
P7.3/AIN11
P7.0/AIN8/CK_AF
P7.2/AIN10
TEST
*V
A8/P1.0
P8.7/AIN7
AVSSAVDDP8.6/AIN6
P8.5/AIN5
75
P8.4/AIN4
74
P8.3/AIN3
73
P8.2/AIN2
72
P8.1/AIN1/WKUP15
71
P8.0/AIN0/WKUP14
70
NC
69
P6.5/WKUP10/INTCLK
68
P6.4/NMI
67
P6.3/INT3/INT5
66
P6.2/INT2/INT4/DS2
65
P6.1/INT6/RW
64
P6.0/INT0/INT1/CLOCK2/8
63
P0.7/A7/D7
62
V
DD
61
V
SS
P0.6/A6/D6
60
P0.5/A5/D5
59
P0.4/A4/D4
58
P0.3/A3/D3
57
P0.2/A2/D2
56
P0.1/A1/D1
55
P0.0/A0/D0
54
AS
53
DS
52
P1.7/A15
51
NC
A9/P1.1
WKUP6
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
Architectural Block Diagram
FLASH
128/64 Kbytes
3TM
E
1Kbyte
RAM
AS
DS
RW
WAIT
NMI
DS2
RW*
INT[5:0]
INT6*
WKUP[13:0]
WKUP[15:14]*
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
V
REG
2/4 Kbytes
256 bytes
Register File
8/16 bits
CPU
Interrupt
Management
ST9 CORE
RCCU
ST. TIMER
EF TIMER 0 *
EF TIMER 1 *
MF TIMER 0
MF TIMER 1
VOLTAGE
REGULATOR
MEMORY BUS
REGISTER BUS
* Not available on 64-pin version.
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8* and Port9*.
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports
1,9*
Fully
Prog.
I/Os
I2CBUS
WATCHDOG
SPI
ADC
SCI M
SCI A*
CAN_0
A[7:0]
D[7:0]
A[10:8]
A[21:11]*
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
P7[7:0]
P8[7:0]*
P9[7:0]*
SDA
SCL
WDOUT
HW0SW1
MISO
MOSI
SCK
SS
AV
DD
AV
SS
AIN[15:8]
AIN[7:0]*
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
RDI
TDO
RX0
TX0
21
NJM2279(MAIN:IC13)
BA7660F(MAIN:IC12)
MUTE
DHT-500SD
1
16
CC
V
INA
GND
INB
GND
N.C.
INC
2
3
4
5
6
7
6dB
75ǡ6dB
75ǡ6dB
75ǡ
15
14
13
12
11
10
OUTA1
OUTA2
OUTB1
OUTB2
N.C.
OUTC1
MUTE (1pin)
GND
OUTC2
8
9
H3c
LNORMA
h
MUTE
L
TC9162AN/AF(AMP:IC59) TC9164AN/AF(MAIN:IC14)
22
CS42528(DSP:IC51)
DHT-500SD
23
MX29LV400T/B(DSP:IC53)
48 TSOP (Standard Type) (12mm x 20mm)
NC
NC
WE
NC
NC
NC
1
2
3
4
5
6
7
A9
8
A8
9
10
11
12
13
14
15
16
17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
A15
A14
A13
A12
A11
A10
RSEET
RY/BY
A17
BLOCK DIAGRAM
MX29LV400T/B
DHT-500SD
48
A16
47
BYTE
46
GND
45
Q15/A-1
44
Q7
43
Q14
42
Q6
41
Q13
40
Q5
39
Q12
38
Q4
37
VCC
36
Q11
35
Q3
34
Q10
33
Q2
32
Q9
31
Q1
30
Q8
29
Q0
28
OE
27
GND
26
CE
25
A0
CE
OE
WE
RESET
A0-A17
CONTROL
INPUT
LOGIC
ADDRESS
LATCH
AND
BUFFER
PROGRAM/ERASE
HIGH VOLTAGE
X-DECODER
MX29LV400T/B
FLASH
ARRAY
Y-DECODER
Y-PASS GATE
SENSE
AMPLIFIER
ARRAY
SOURCE
PGM
DATA
HV
HV
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
COMMAND
DA TA
DECODER
COMMAND
DATA LATCH
Q0-Q15/A-1
PROGRAM
DATA LATCH
I/O BUFFER
24
PCM1754(DSP:IC55)
PIN ASSIGNMENTS
DHT-500SD
PCM1754
(TOP VIEW)
BCK
DATA
LRCK
DGND
V
V
OUT
V
OUT
NC
CC
L
R
1
2
3
4
5
6
7
8
FUNCTIONAL BLOCK DIAGRAM
BCK
LRCK
DATA
(FMT) ML
(MUTE) MC
(DEMP) MD
Audio
Serial
Port
Oversampling
Serial
Control
Port
16
15
14
13
12
11
10
9
4ı /8ı
Digital
Filter
and
Function
Control
SCK
FMT
MUTE
DEMP
TEST
ZEROA
V
COM
AGND
Enhanced
Multi-Level
Delta-Sigma
Modulator
DAC
DAC
Output Amp
and
Low-Pass Filter
Output Amp
and
Low-Pass Filter
V
OUT
V
COM
V
OUT
L
R
(TEST)
SCK
†
Open-DrainOutput for the PCM1755
( ): PCM1754
System
Clock
Manager
System Clock
Zero Detect
†
ZEROL/NA
†
(ZEROA)
ZEROR/ZEROA
Power Supply
CC
V
DGND
AGND
25
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