Dell XPS 13 9370 boardview

A

B

C

D

E

MODEL NAME :
PCB NO :
BOM P/N :

ZZZ

1 1

MB_PCB

LA-E671P
43xxxxx

CAZ60

Dell/Compal Confidential

2 2

Schematic Document

Italia

@ : N o p o p C o m p o n e n t
@ C O N N @ : R e s e r v e C o n n e c t o r C o m p o n e n t

3 3

2017-09-15

@ E M C @ : R e s e r v e E M C C o m p o n e n t
C O N N @ : C o n n e c t o r C o m p o n e n t

Rev: 1.0 ( A00 )

X P S @ : f o r I t a l i a
L @ : f o r I t a l i a - L
R F @ : R F S o l u t i o n C o m p o n e n t
X D P @ : X D P D e b u g C o m p o n e n t
E M C @ : E M C C o m p o n e n t
U 2 2 @ : U 2 2 C P U S u p p o r t
U 2 3 @ : U 2 3 C P U S u p p o r t
U 4 2 @ : U 4 2 C P U S u p p o r t

4 4

U 2 2 U 2 3 @ : U 2 2 a n d U 2 3 C P U S u p p o r t
D E B U G @ : f o r O t h e r D e b u g
6 5 0 @ : T P M
7 5 0 @ : T P M
D C I @ : f o r D C I D e b u g

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/12/16 2016/12/13

2016/12/16 2016/12/13

2016/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P01-Cover Page

P01-Cover Page

P01-Cover Page

Document Number Re v

Document Number Re v

Document Number Re v

LA-E671P

LA-E671P

LA-E671P

E

1 61Tuesday, October 17, 2017

1 61Tuesday, October 17, 2017

1 61Tuesday, October 17, 2017

1.0

1.0

1.0

A

B

C

D

E

DP 1.2 X1

eDP 1.3

I2C

DP 1.2 X2
PCIe Gen3 X 4

USB3.0
USB2.0

USB2.0

PCIE Gen2

USB2.0

I2C

SMBus

Intel

Kaby Lake
ULT

15W TDP

Page 7 ~ 20

Memory Bus (LPDDR3)

Dual Channel

1.2V LPDDR3 1866 MHz Non-Interleave

SPI

SATA3 X1 / PCIE X4

USB2.0
PCIE

HDA

Channel A
LPDDR3 8Gb or 16Gb (x32) * 2

P.21

Channel B
LPDDR3 8Gb or 16Gb (x32) * 2

P.22

SPI ROM
128/256Mb

TPM2.0

Nuvoton

M.2 Socket3 M-Key
SSD

WLAN1216
WLAN

BT4.0

Audio Codec
ALC3271

I2S

DMIC

Audio AMP
ALC1309

P.09

P.27

P.30

P.28

P.24

P.25

Audio/B with FPC

Headphone Jack

( iPhone & Nokia compatible)

Int. Speaker

P.26

P.25

eDP Panel Conn.

+ Touch Screen

(IPT)

1 1

TI PD
TPS65982

P.43

TI PD
TPS65982

TI PD
TPS65982

P.45

IR Digital Camera

2 2

uSD 4.0

Fingerprint

P.37

USB TypeC Conn.

USB TypeC Conn.

USB TypeC Conn.

P.37

P.46

P.46P.44

P.47

DMIC

CardReader

P.29 P.29

P.36

RTS5242

Alpine Ridge
Thunderbolt

P.41

DP Switch
TI TUSB546

P.31

Precision Touch Pad

P.36

3 3

Fan conn. x 2

P.30

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

P.35

P.34~ 35

P.49~ 61

PS/2

EC
MEC 5105

ESPI

P.38

User Interface

Battery Gauge LED

P.32

BCBUS

KBC/B

Keyboard Controller

4 4

A

B

ECE1117B

C

KSIO

Int.KBD

Front Side LED + 4 MIC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

Document Number Re v

Document Number Re v

Document Number Re v

LA-E671P

LA-E671P

LA-E671P

E

2 61Tuesday, October 17, 2017

2 61Tuesday, October 17, 2017

2 61Tuesday, October 17, 2017

1.0

1.0

1.0

A

B

C

D

E

2+2 CPU Option

UCPU1 QNB1_ 2+2@

SA0000B2Y0L

UCPU1 QL YJ_2+2_R3@

1 1

SA0000A377L

DRAM Option DRAM Config Option

Micron 4G/1866

SA00009XU1L

Micron 8G/1866

SA00009U71L

2 2

Mircon 16G/1866

SA00009ZN1L

Hynix 4G/1866

SA00008G64L

Hynix 8G/1866

SA00008FJ4L

Hynix 16G/1866

SA0000AEN0L

UD41 M4G_1866@

SA00009XU1L

UD41 M8G_1866@

SA00009U71L

UD41 M16G_1866@

SA00009ZN1L

UD41

H4G_1866@

SA00008G64L

H9CCNNN8GTALAR-NUD

UD41

H8G_1866@

SA00008FJ4L

H9CCNNNBJTALAR-NUD

UD41

H16G_1866@

SA0000AEN0L

H9CCNNNCLGALAR-NUD

2+3 CPU Option

UCPU1 QM 6R_2+3_R3@

SA0000AHS1L

UD42 M4G_1866@

SA00009XU1L

UD42 M8G_1866@

SA00009U71L

UD42 M16G_1866@

SA00009ZN1L

UD42

H4G_1866@

SA00008G64L

H9CCNNN8GTALAR-NUD

UD42

H8G_1866@

SA00008FJ4L

H9CCNNNBJTALAR-NUD

UD42

H16G_1866@

SA0000AEN0L

H9CCNNNCLGALAR-NUD

UD43 M4G_1866@

SA00009XU1L

UD43 M8G_1866@

SA00009U71L

UD43 M16G_1866@

SA00009ZN1L

UD43

H4G_1866@

SA00008G64L

H9CCNNN8GTALAR-NUD

UD43

H8G_1866@

SA00008FJ4L

H9CCNNNBJTALAR-NUD

UD43

H16G_1866@

SA0000AEN0L

H9CCNNNCLGALAR-NUD

UD44 M4G_1866@

SA00009XU1L

UD44 M8G_1866@

SA00009U71L

UD44 M16G_1866@

SA00009ZN1L

UD44

H4G_1866@

SA00008G64L

H9CCNNN8GTALAR-NUD

UD44

H8G_1866@

SA00008FJ4L

H9CCNNNBJTALAR-NUD

UD44

H16G_1866@

SA0000AEN0L

H9CCNNNCLGALAR-NUD

4+2 CPU Option

UCPU1 QNEE_4 +2_R3@

SA0000AWS2L

UCPU1 QNEF_ 4+2_R3@

SA0000AWB3L

MEM_CON FIG0 MEM_ CONFIG1 MEM_CONFIG2

RH51

RH52

RH51

10K_0402_5%~D

RH52

SD028100280

10K_0402_5%~D

RH51

SD028100280

10K_0402_5%~D

RH52

SD028100280

10K_0402_5%~D

UCPU1 QNBF_ 4+2_R3@

SA0000AWC2L

UCPU1 QNBE_4 +2_R3@

SA0000AWR2L

M4G_1866@

SD028100280

10K_0402_5%

M8G_1866@

SD028100280

10K_0402_5%

M16G_1866@

SD028100280

H4G_1866@

H8G_1866@

H16G_1866@

RH54

SD028100280

10K_0402_5%

RH53

SD028100280

10K_0402_5%

RH53

SD028100280

10K_0402_5%~D

RH54

SD028100280

10K_0402_5%~D

RH54

SD028100280

10K_0402_5%~D

RH53

SD028100280

10K_0402_5%~D

M4G_1866@

M8G_1866@

M16G_1866@

H4G_1866@

H8G_1866@

H16G_1866@

AR Option

UT2

AR_SLL42@

SA00009ZV3L

DSL6340 SLL42 B2

RH56

M4G_1866@

SD028100280

10K_0402_5%

RH56

M8G_1866@

SD028100280

10K_0402_5%

RH56

M16G_1866@

SD028100280

10K_0402_5%~D

RH55

H4G_1866@

SD028100280

10K_0402_5%~D

RH55

H8G_1866@

SD028100280

10K_0402_5%~D

RH55

H16G_1866@

SD028100280

10K_0402_5%~D

RH57

M4G_1866@

SD028100280

10K_0402_5%

RH57

M8G_1866@

SD028100280

10K_0402_5%

RH57

M16G_1866@

SD028100280

10K_0402_5%~D

RH57

H4G_1866@

SD028100280

10K_0402_5%~D

RH57

H8G_1866@

SD028100280

10K_0402_5%~D

RH57

H16G_1866@

SD028100280

10K_0402_5%~D

TPM Option

U7

TPM750@

SA0000AQ200

TPM750 - ES FW:7.1.0.0

MEM_CON FIG4MEM_CON FIG3

RH60

M4G_1866@

SD028100280

10K_0402_5%

RH60

M8G_1866@

SD028100280

10K_0402_5%

RH60

M16G_1866@

SD028100280

10K_0402_5%~D

RH60

H4G_1866@

SD028100280

10K_0402_5%~D

RH60

H8G_1866@

SD028100280

10K_0402_5%~D

RH60

H16G_1866@

SD028100280

10K_0402_5%~D

3 3

4 4

LA-E671P

LA-E671P

LA-E671P

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P03-BoM Option

P03-BoM Option

P03-BoM Option

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

LA-E671P

Date: Sheet of

Date: Sheet of

Date: Sheet of

3 61Tuesday, October 17, 2017

3 61Tuesday, October 17, 2017

3 61Tuesday, October 17, 2017

E

1.0

1.0

1.0

A

Board ID Table for AD channel

USB PORT# DESTINATION

1

2

3

4

5

6

7

8

9

10

1

PD PORT3

NC

NC

NC

IR Camera & Cam

NC

NGFF WLAN BT

NC

NC

Fingerprint

DP MX (PS8743B)

2

DDI PORT# DESTINATION

1

2

Alpine Ridge

Alpine Ridge

X00240K
X01
X02
X03
A00

SOURCE

MEC5105

MEC5105

MEC5105SMB04_CLK

MEC5105

MEC5105

MEC5105

PCH

PCH

PCH

PCH

PCHI2C2_CLK

REV

BATTERY

Charger

PD1

V

PD2

V

PWR_MON

V

Italia
CAZ60

5105

4+2 2+3 3+2CPU

PCH

USB 2.0
Port
Mapping

XDP

Audio

AMP

eDP

Touch Pad

Touch S

IR_THER_S

V

V

PCH

USB 3.0

V

Port
Mapping

V

V

V

PCH

DDI
Port
Mapping

V

V

CE75RE194

4700p
4700p

130K

4700p

62K

4700p

33K

4700p

8.2K

4.3K

4700p
4700p

2K
1K

4700p

BOARD_ID rise t i me i s meas ur ed fr o m 5 %~68 %.

SMBUS Control Table

SMB00_CLK
SMB00_DATA

SMB01_CLK
SMB01_DATA

SMB02_CLKVMEC5105
SMB02_DATA

SMB04_DATA

SMB05_CLK
SMB05_DATA

SMB07_CLK
SMB07_DATA

SMB10_CLK
SMB10_DATA

PCH_SML1CLK

PCH_SML1DATA

SMBCLK

SMBDATA

1 1

I2C0_CLK
I2C0_DATA

I2C2_DATA

I2C1_CLK
I2C1_DATA

I2C2_DATA

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

FLEX CLK#

CLKOUT_LPC_0

CLKOUT_LPC_1

DESTINATIONDIFFERENTIAL CLK#

Alpine Ridge

NGFF WLAN

NC

M.2 SSD

NC

Card Reader

DESTINATION

ESPI 5105

NC

PCI EXPRESS PORT#

Lane 1 Card Reader

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Lane 9

Lane 10

Lane 11

Lane 12 / SATA 2

DESTINATION

NC

NGFF WLAN

NC

Alpine Ridge

Alpine Ridge

Alpine Ridge

Alpine Ridge

M.2 SSD

M.2 SSD

M.2 SSD

M.2 SSD

SATA PORT#

SATA-0

SATA-1A

SATA-1B

SATA-2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

DESTINATION

NC

NC

NC

M.2 SSD

Compal Secret Data

Compal Secret Data

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P04-Notes List

P04-Notes List

P04-Notes List

Document Number Re v

Document Number Re v

Document Number Re v

LA-E671P

LA-E671P

LA-E671P

4 61Tuesday, October 17, 2017

4 61Tuesday, October 17, 2017

4 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

SY8210A
(PU600)

Type C X 3

D D

ISL88738
(PU300)

SY8286
(PU700)

TPS62134A
(PU1400)

TPS62134B
(PU1401)

4

SIO_SLP_S4# &
SUS_ON_EC

5500 mA

SM_PG_CTRL

600mA

SIO_SLP_SUS#

880mA 240mA

SIO_SLP_S0# &
RUN_ON_P

SIO_SLP_SUS#

2570 mA

+1.2V_DDR

+0.6VS

+1.0VA

+1.0VS_VCCIO

+1.0V_PRIM_CORE

TPS22961

(UZ5)

3

SIO_SLP_S0# &
RUN_ON_P

260mA

+VCCPLL_OC

RUN_ON_P

200mA

+5VS

2

+1.0V_MPHYGT

+1.0V_MPHYAON

TPS22961

(UZ3)

TPS22961

(UZ4)

SIO_SLP_SUS# &
SUS_ON_P

SIO_SLP_S0# &
RUN_ON_P

40mA3100 mA

1

CPU PWR

PCH PWR

GPU PWR

Peripheral Device PWR

+1.0V_VCCST

+1.0V_VCCSTG

SY8288C

B+

BATTERY

(JT100)

C C

(PU501)

TLV6215
(PU800)

SY8286B
(PU500)

ALWON

530mA

SIO_SLP_SUS#

210mA

+5VALW

+1.8VA

AOZ1331

(U12)

AUD_PWR_EN

3150 mA

+5VS_AUDIO

AOZ1331

(U14)

AUD_PWR_EN

400mA

+1.8VS_AUDIO

+V1.8S_EDRAM

ALWON

590mA

TPS62134C
(PU1500)

TPS62134C
(PU1501)

B B

TLV62150R

(PU900)

ISL95829
(PU1000)

AP22850

IMVP_VR_ON_P

2500 mA

IMVP_VR_ON_P

2000 mA

SUS_ON_P

+VCC_EDRAM

+VCC_EOPIO

660mA

+3VALW

SY6288C

(UZ2)

AP22850

(U10)

AOZ1331
(U11)

AOZ1331

(U13)

TPS22961

(UZ1)

AOZ1331

(U14)

ENVDD

545mA

TP_PW_EN

35mA

PCH_PWR_EN
(SIO_SLP_SUS#)

535mA

AUX_EN_WOWL

620mA

3.3V_TS_EN

300mA

AUD_PWR_EN

50mA

+LCDVDD

+3VS_TP

+3V_PCH

+3VS_NGFF

+3VS_TS

+3VS_AUDIO

RUN_ON_P

2500 mA

RUN_ON_P

480mA

+3.3VDX_SSD

+3VS

SD_PWR_EN

1200 mA

+3VS_CR

A A

5100 mA

IMVP_VR_ON

6400 0mA

IMVP_VR_ON

+VCC_GT+VCC_SA

5

2900 0mA

IMVP_VR_ON

+VCC_CORE

+INV_PWR_SRC

590mA

EN_INVPWR

+1.8VU

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P05-Power rails

P05-Power rails

P05-Power rails
LA-E671P

LA-E671P

LA-E671P

1

5 61Tuesday, October 17, 2017

5 61Tuesday, October 17, 2017

5 61Tuesday, October 17, 2017

1.0

1.0

1.0

A

B

C

D

E

F

G

H

2.2K

R7
R8

1 1

2 2

KBL-U

W3 V3

E11 D 8

SMB03

R9
W2

SML1_SMBDATA

SML1_SMBCLK

SMB00

SMB01

MEM_SMBCLK

MEM_SMBDATA

1K

1K

D7

UPD2_SMBCLK

E7

UPD2_SMBDAT

B3

IR_THER_SEN_SMBCLK

E5

IR_THER_SEN_SMBDAT

+3V_PCH

2.2K

2.2K

2.2K

2.2K

+3.3V_EC5105

+3.3V_EC5105

2.2K

+3VS

53
51

XDP

B3
C3

B5
A1

L2
K2

TI PD2

PD2_Debug

IR_THER_S

TI PD address selection 0x70_TBD

PD_Debug address selection 0xEC_TBD

4.7K

KBC

SMB02

C12
E10

CLK_TP_SIO
DAT_TP_SIO

4.7K

2.2K

2.2K

C3
B4

UPD1_SMBCLK

UPD1_SMBDAT

SMB04

MEC 5105

3 3

SMB05

SMB06

SMB07

F7

B6

A12

PWR_MONITOR_EC_SMBCLK
PWR_MONITOR_EC_SMBDAT

M4

UPD3_SMBCLK

M7

UPD3_SMBDAT

0 ohm
0 ohm

EC_I2C_CLK
EC_I2C_DAT

2.2K

2.2K

+3VS_TP

+3.3V_EC5105

+3.3V_EC5105

0 ohm
0 ohm

2.2K

2.2K

PWRM_SCL

PWRM_SDA

2.2K

2.2K

+3VS_PWRM

8
9

L2
K2

B5
A1

7
8

6
7

C4
D4N10

B5
A5

TP

PD1_Debug

TI PD1

+DVDD

AMP

Audio

MAX34407

TI PD3

TP address :0x42_TBD

PD_Debug address selection 0xEC_TBD

TI PD address selection 0x70_TBD

I2C address selection L= 0x20H (L= 0x20H ; H= 0x22H)_TBD

2.2K

+3.3V_EC5105

4 4

A

SMB10

N2

PBAT_CHARGER_SMBCLK

M3

PBAT_CHARGER_SMBDAT

B

2.2K

C

100 ohm
100 ohm

D

8

BATTERY

7

CONN

22

Charger

21

Battery address selection 0x16_TBD

Charger address selection 0x12_TBD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2013/07/04 2013/10/28

2013/07/04 2013/10/28

2013/07/04 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

F

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

G

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P06-SMBus block diagram

P06-SMBus block diagram

P06-SMBus block diagram

Document Number Re v

Document Number Re v

Document Number Re v

LA-E671P

LA-E671P

LA-E671P

6 61Tuesday, October 17, 2017

6 61Tuesday, October 17, 2017

6 61Tuesday, October 17, 2017

H

1.0

1.0

1.0

5

CAD Note:Trace width=5 mils, Isolat i on Spaci ng=25 mil,

4

3

2

1

+3VS

CPU_DP1_CTRL_CLK

RC1 2.2K_0402_5%
RC3 2.2K_0402_5%
RC5 2.2K_0402_5%

D D

RC7 2.2K_0402_5%

12

CPU_DP1_CTRL_DATA

12

CPU_DP2_CTRL_CLK

12

CPU_DP2_CTRL_DATA

12

Alpine Ridge

+1.0VS_VCCIO

DDI1_PTX_TBRX_N0<41>
DDI1_PTX_TBRX_P0<41>
DDI1_PTX_TBRX_N1<41>
DDI1_PTX_TBRX_P1<41>
DDI1_PTX_TBRX_N2<41>
DDI1_PTX_TBRX_P2<41>
DDI1_PTX_TBRX_N3<41>
DDI1_PTX_TBRX_P3<41>

DDI2_PTX_TBRX_N0<41>
DDI2_PTX_TBRX_P0<41>
DDI2_PTX_TBRX_N1<41>
DDI2_PTX_TBRX_P1<41>
DDI2_PTX_TBRX_N2<41>
DDI2_PTX_TBRX_P2<41>
DDI2_PTX_TBRX_N3<41>
DDI2_PTX_TBRX_P3<41>

CPU_DP1_CTRL_CLK<41>

CPU_DP1_CTRL_DATA<41> CPU_DP1_HPD <41>

CPU_DP2_CTRL_CLK<41>

CPU_DP2_CTRL_DATA<41>

1 2

RC8 24.9_0402_1%

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA CPU_DP1_HPD

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

EDP_COMP

COMPENSATION PU FOR eDP

Max length=600 mils.

C C

UCPU1I

@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

B B

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356

SKL_U LT

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

CSI2_COMP

MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4

EMMC_RCOMP

1 2

RC9 100_0402_1%

1 2

RC10 200_0402_1%

UCPU1A

@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

DDR Memory Conf i gur at i no Type Str ap pin

+1.8VA

RH51 10K_0402_5%@
RH53 10K_0402_5%@
RH55 10K_0402_5%@
RH57 10K_0402_5%@
RH59 10K_0402_5%@

A A

12
12
12
12
12

MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4

RH52 10K_0402_5%@
RH54 10K_0402_5%@
RH56 10K_0402_5%@
RH58 10K_0402_5%@
RH60 10K_0402_5%@

12
12
12
12
12

SKL-U

DDI

DISPLAY SIDEBANDS

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

1 OF 20

GPIO Pin

GPP_ F13

GPP_ F14

GPP_ F15

Pin Name

MEM_C ONF IG0

MEM_C ONF IG1

MEM_C ONF IG2

GPP_ F16 MEM_CONFIG3

GPP_ F17 MEM_CONFIG4

GPIO Pin

GPP_ F13

GPP_ F14

GPP_ F15

GPP_ F16

GPP_ F17

GPIO Pin

GPP_ F13

GPP_ F14

Pin Name

MEM_C ONF IG0

MEM_C ONF IG1

MEM_C ONF IG2

MEM_C ONF IG3

MEM_C ONF IG4

Pin Name

MEM_C ONF IG0

MEM_C ONF IG1

GPP_ F15

GPP_ F16

GPP_ F17

MEM_C ONF IG3

MEM_C ONF IG4

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52
G50

F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

1600 Mbps

1866 Mbps

2133 Mbps

eDP_TXN_P0 <37>
eDP_TXP_P0 <37>

CPU_DP2_HPD

EDP_HPD

Micron 4G

0

0

0

eDP_TXN_P1 <37>
eDP_TXP_P1 <37>
eDP_TXN_P2 <37>
eDP_TXP_P2 <37>
eDP_TXN_P3 <37>
eDP_TXP_P3 <37>

eDP_AUXN <37>
eDP_AUXP <37>

CPU_DDI1_AUXN <41>
CPU_DDI1_AUXP <41>
CPU_DDI2_AUXN <41>

CPU_DDI2_AUXP <41>

PAD~D
PAD~D

CPU_DP2_HPD <41>
I2C2_IRQ_TS <37>

EDP_HPD <37>

PANEL_BKLEN <37>
EDP_BIA_PWM <37>
ENVDD_PCH <33,38>

Micron 8G

1

0 1

0

@

T1

@

T2

Mircon 16G

0 1

0

Hynix 4G

1

0 11

Support QHD

+3VS

EDP_HPD
CPU_DP1_HPD
CPU_DP2_HPD

01

0

1 2

RH83 100K_0402_5%

Hynix 16GHynix 8G

0 1

0

1 1

1 1

I2C2_IRQ_TS

12

RC2100K_0402_5%

12

RC4100K_0402_5%

12

RC6100K_0402_5%

Samsung 8GSamsung 4G

Samsung 16G

0

0

0

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0

Micron 4G

1

0

0

Micron 8G

0

1 1

0

Mircon 16G

Hynix 4G

1 0

0

0

1 11

Hynix 16GHynix 8G

10

0

1

1 1 1 1 1 1 1

0 0 0 0 0 0 0

Micron 4G Samsung 16G

Micron 8G

0

1

0

0

1

Mircon 16G

1

1

0MEM_C ONF IG2

0

1

Hynix 4G

0

1

0

1

Hynix 8G Hynix 16G

1

0

0

1

1 11

0 0 0

11

Samsung 4G Samsung 8G

10

1

1

Samsung 8GSamsung 4G

1

1

1

0

0

0

1

1

Samsung 16G

0

0

0

0

1

1

0

0 0

1

1

1

0

0

0

1

0

1

1

1

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P07-MCP(1/14)DDI,EDP,CSI2,EMMC

P07-MCP(1/14)DDI,EDP,CSI2,EMMC

P07-MCP(1/14)DDI,EDP,CSI2,EMMC
LA-E671P

LA-E671P

LA-E671P

1

7 61Tuesday, October 17, 2017

7 61Tuesday, October 17, 2017

7 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

LPDDR3, Ballout for side by side(Non-Interleave)

4

3

2

1

UCPU1B

@

DDR_A_D0

AL71

DDR_A_D1
DDR_A_D2

D D

DDR_A_D[32..47]<21>

DDR_B_D[0..15]<22>

C C

DDR_B_D[32..47]<22>

B B

DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

SKL-U

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]

DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_ODT[1]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

2 OF 20

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0

DDR_VTT_CNTL

DDR_A_CLK#0 <21,23>
DDR_A_CLK0 <21,23>
DDR_A_CLK#1 <21,23>
DDR_A_CLK1 <21,23>

DDR_A_CKE0 <21,23>
DDR_A_CKE1 <21,23>
DDR_A_CKE2 <21,23>
DDR_A_CKE3 <21,23>

DDR_A_CS#0 <21,23>
DDR_A_CS#1 <21,23>
DDR_A_ODT0 <21,23>

DDR_A_CA1_0 <21,23>
DDR_A_CA1_1 <21,23>
DDR_A_CA1_2 <21,23>
DDR_A_CA1_3 <21,23>
DDR_A_CA1_4 <21,23>
DDR_A_CA1_5 <21,23>
DDR_A_CA1_6 <21,23>
DDR_A_CA1_7 <21,23>
DDR_A_CA1_8 <21,23>
DDR_A_CA1_9 <21,23>

DDR_A_CA2_0 <21,23>
DDR_A_CA2_1 <21,23>
DDR_A_CA2_2 <21,23>
DDR_A_CA2_3 <21,23>
DDR_A_CA2_4 <21,23>
DDR_A_CA2_5 <21,23>
DDR_A_CA2_6 <21,23>
DDR_A_CA2_7 <21,23>
DDR_A_CA2_8 <21,23>
DDR_A_CA2_9 <21,23>

DDR_A_DQS#0 <21>
DDR_A_DQS0 <21>
DDR_A_DQS#1 <21>
DDR_A_DQS1 <21>
DDR_A_DQS#4 <21>
DDR_A_DQS4 <21>
DDR_A_DQS#5 <21>
DDR_A_DQS5 <21>
DDR_B_DQS#0 <22>
DDR_B_DQS0 <22>
DDR_B_DQS#1 <22>
DDR_B_DQS1 <22>
DDR_B_DQS#4 <22>
DDR_B_DQS4 <22>
DDR_B_DQS#5 <22>
DDR_B_DQS5 <22>

@

T3

PAD~D

@

T4

PAD~D

+V_DDR_REF_CA <23>
+V_DDR_REFA_R <23>
+V_DDR_REFB_R <23>

UCPU1C

@

DDR_A_D[16..31]<21>DDR_A_D[0..15]<21>

DDR_A_D[48..63]<21>

DDR_B_D[16..31]<22>

DDR_B_D[48..63]<22>

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]

DDR CH - B

DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

3 OF 20

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <22,23>
DDR_B_CLK#1 <22,23>
DDR_B_CLK0 <22,23>
DDR_B_CLK1 <22,23>

DDR_B_CKE0 <22,23>
DDR_B_CKE1 <22,23>
DDR_B_CKE2 <22,23>
DDR_B_CKE3 <22,23>

DDR_B_CS#0 <22,23>
DDR_B_CS#1 <22,23>
DDR_B_ODT0 <22,23>

DDR_B_CA1_0 <22,23>
DDR_B_CA1_1 <22,23>
DDR_B_CA1_2 <22,23>
DDR_B_CA1_3 <22,23>
DDR_B_CA1_4 <22,23>
DDR_B_CA1_5 <22,23>
DDR_B_CA1_6 <22,23>
DDR_B_CA1_7 <22,23>
DDR_B_CA1_8 <22,23>
DDR_B_CA1_9 <22,23>

DDR_B_CA2_0 <22,23>
DDR_B_CA2_1 <22,23>
DDR_B_CA2_2 <22,23>
DDR_B_CA2_3 <22,23>
DDR_B_CA2_4 <22,23>
DDR_B_CA2_5 <22,23>
DDR_B_CA2_6 <22,23>
DDR_B_CA2_7 <22,23>
DDR_B_CA2_8 <22,23>
DDR_B_CA2_9 <22,23>

DDR_A_DQS#2 <21>
DDR_A_DQS2 <21>
DDR_A_DQS#3 <21>
DDR_A_DQS3 <21>
DDR_A_DQS#6 <21>
DDR_A_DQS6 <21>
DDR_A_DQS#7 <21>
DDR_A_DQS7 <21>
DDR_B_DQS#2 <22>
DDR_B_DQS2 <22>
DDR_B_DQS#3 <22>
DDR_B_DQS3 <22>
DDR_B_DQS#6 <22>
DDR_B_DQS6 <22>
DDR_B_DQS#7 <22>
DDR_B_DQS7 <22>

@

T5

PAD~D

@

T6

PAD~D

@

T7

PAD~D

+1.2V_DDR

NC
A
GND

@

1 2

UC9

5

VCC

4

Y

@

1

@

CC92

0.1U_0402_10V7K

2

+3VS

12

@

RE241
100K_0402_5%

SM_PG_CTRL <52>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DDR_VTT_CNTL

A A

5

1
2
3

SN74AUP1G07DCKR_SC70

RC383 0_0402_1%

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

1 2

RC11 200_0402_1%

1 2

RC12 80.6_0402_1%

1 2

RC13 162_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(2/14)LPDDR3

P08-MCP(2/14)LPDDR3

P08-MCP(2/14)LPDDR3
LA-E671P

LA-E671P

LA-E671P

1

8 61Tuesday, October 17, 2017

8 61Tuesday, October 17, 2017

8 61Tuesday, October 17, 2017

0.1

0.1

0.1

5

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_SO

MEDIACARD_IRQ#

CL_CLK<28>
CL_DAT<28>
CL_RST#<28>

SIO_RCIN#
ESPI_ALERT#

PCH_SPI_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#

PCH_SPI_SI<15>

1 2

1 2
1 2

PCH_SPI_IO2<15>

PCH_SPI_CS2#<27>

TPM_PIRQ#<27>

MEDIACARD_IRQ#<29>

MEDIACARD_IRQ#

SIO_RCIN#
ESPI_ALERT#

ESPI_ALERT#<38>

D D

+3V_PCH

RC17 10K_0402_5%@

+3.3V_1.8V_ESPI

RC21 10K_0402_5%@
RC24 10K_0402_1%

C C

AV2

AW3

AV3

AW2

AU4
AU3
AU2
AU1

AW13

AY11

M2
M3

J4
V1
V2

M1

G3
G2
G1

4

UCPU1E

@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL-U_BGA1356

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

GPP_C5
SML1_SMBCLK

SML1_SMBDAT
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

PCI_CLK_LPC0
PCI_CLK_LPC1

CLKRUN#

PWR_MONITOR_SMBCLK <35>

PWR_MONITOR_SMBDAT <35>

SML1_SMBCLK <38>

SML1_SMBDAT <38>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <38,39>
ESPI_RESET# <38>

1 2

RC19 EMC@15_0402_5%

1 2

RC22 22_0402_5% @

2

ESPI_IO0 <38,39>
ESPI_IO1 <38,39>
ESPI_IO2 <38,39>
ESPI_IO3 <38,39>

MEM_SMBCLK

MEM_SMBDATA

RC387 0_0402_1%@

+3VS

6

@

5

DMN66D0LDW-7_SOT363-6

3 4

QC1B

@

DMN66D0LDW-7_SOT363-6

1 2

ESPI_CLK_5105 <38,39>

RC388 0_0402_1%@

2

DDR_XDP_SMBCLK

1

QC1A

DDR_XDP_SMBDAT
DDR_XDP_SMBCLK

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDAT

PVT_0008

1 2

DDR_XDP_SMBDAT

CLKRUN#

1

DDR_XDP_SMBCLK <15>

DDR_XDP_SMBDAT <15>

12

RN12.2K_0402_5%

12

RN22.2K_0402_5%

12

RC168.2K_0402_5%

+3V_PCH

1 2

RC18 1K_0402_5%@

1 2

RC20 1K_0402_5%@

1 2

RC23 1K_0402_5%

1 2

RC25 1K_0402_5%

+3VS

SPI_SI_VROM

PCH_SPI_CLK_TPM<27>
PCH_SPI_SI_TPM<27>

SPI_CLK_VROM

PVT_0012

+3V_PCH

ROM is Quad SPI

PCH_SPI_CS0#_R

SPI_SO_VROM
SPI_IO2_VROM SPI_CLK_VROM

B B

SPI ROM FOR ME ( 32 MByte )

U1

1

CS#

2

HOLD#_RESET#

DO

3

WP#

4

GND

W25Q256FVEIQ_WSON8

VCC

CLK

8
7
6
5

DI

1 2

0.1U_0402_25V6

SPI_IO3_VROM
SPI_SI_VROM

CC4

PCH_SPI_SO_TPM<27>

SPI_SO_VROM
SPI_IO2_VROM
SPI_IO3_VROM

RP1

1 8
2 7
3 6
4 5

33_8P4R_5%

RP2

1 8
2 7
3 6
4 5

33_8P4R_5%

SPI_CLK_VROM

33_0402_5%

RC28@

1 2

33P_0402_50V8J

1 2

from CPU to SPI ROM

JSPI1

1

1

2

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_IO2
PCH_SPI_IO3

+3V_PCH

+3VALW

A A

Serial Peripheral Interface (SPI) Topology Guidelines

1 2

RC30 0_0402_1%@

1 2

RC31 0_0402_1%@

1 2

RC32 0_0402_1%@

1 2

RC33 0_0402_1%@

1 2

RC34 0_0402_1%@

1 2

RC35 0_0402_1%@

1 2

RC36 0_0402_1%@

1 2

RC37 0_0402_5%

@

PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CLK_R
PCH_SPI_CS0#_R
PCH_SPI_IO2_R
PCH_SPI_IO3_R

PCH SPI

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND_1

22

GND_2

ACES_50696-0200M-P01

CONN@

TPM

JSPI

5

4

PCH_SPI_SI_R

PCH_SPI_CLK_R

PCH_SPI_SO_R
PCH_SPI_IO2_R

PCH_SPI_IO3_R

+3V_PCH

RH61 1K_0402_5%~D@

RH62 1K_0402_5%~D@

CC5@

Option 1: Implement a 1 k Ohm pull-down resistor on the signal and de-populate the
required 1 kOhm pull-up resistor(MOW WW5).
In this case, customers mu st ensure that the SPI
flash device on the platform has HOLD f unctionality disabled by d efault.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RH63 1K_0402_5%~D@

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

ESPI_CLK_5105

1 2

1 2

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Reserve for RF

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_IO3

2

12

EMC@12P_0402_50V8J

CC2

PCH_SMB_ALERT#

1 2

RC26 2.2K_0402_5%

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

GPP_C5

1 2

RC27 4.7K_0402_5%

EC interface

HIGH
LOW(DEFAULT)

@

GPP_B23

RC29

1 2

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

RC29 DCI need pop 4.7 k ohm

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P09-MCP(3/14)SPI,SMB,LPC

P09-MCP(3/14)SPI,SMB,LPC

P09-MCP(3/14)SPI,SMB,LPC
LA-E671P

LA-E671P

LA-E671P

1

ENABLE
DISAB LE

ESPI

LPC

150K_0402_1%

ENABLE
DISAB LE

9 61Tuesday, October 17, 2017

9 61Tuesday, October 17, 2017

9 61Tuesday, October 17, 2017

+3V_PCH

+3V_PCH

+3V_PCH

1.0

1.0

1.0

5

4

3

2

1

UCPU1F

@

LPSS ISH

+3VS

HOST_SD_WP#

1 2

D D

RC38 10K_0402_5%

RC39 10K_0402_5%

RH64 49.9K_0402_1%

RH65 49.9K_0402_1%

1 2

1 2

1 2

SIO_EXT_SCI#

UART1_TXD

UART1_RXD

change to net name ==> I2C0_SDA_TS and I2C0_SCK_TS

+3V_PCH

SIO_EXT_WAKE#

1 2

RC40 10K_0402_5%

TS_I2C_RST#<37>

TS

TP

eDP

PWRMON ITOR

PWR_MONITOR_I2CSDA<35>
PWR_MONITOR_I2CCLK<35>

TPM_DET

DBC_EN<37>

NRB_BIT

@

PAD~D

SIO_EXT_SCI#
GPP_B22

HOST_SD_WP#

SIO_EXT_WAKE#

I2C1_SDA_TP
I2C1_SCK_TP

3.3V_TS_EN<33>

SBIOS_TX<39>

HOST_SD_WP#<29>

SIO_EXT_WAKE#<38>

T8

I2C0_SDA_TS<37>

I2C0_SCK_TS<37>

I2C1_SDA_TP<36>

I2C1_SCK_TP<36>

I2C2_SDA_EDP_PCH<37>

I2C2_SCK_EDP_PCH<37>

change to net name ==> I2C2_SDA_EDP_PCH and I2C2_SCK_EDP_PCH

C C

TBT_PWR_EN

RH70 100K_0402_5%~D

12

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

TPM_DET
TPM_DET

TPM BOM Optional

+3V_PCH

NRB_BIT

1 2

RC45 2.2K_0402_5%@

NO REBOOT STRAP

HIGH

B B

LOW(DEFAULT)
Weak IPD

+3V_PCH

12

@

2.2K_0402_5%
RC46

GPP_B22

No REBOOT

REBOOT ENABLE

TPM_DET

TPM

UART1_TXD
UART1_RXD

1 = W/TPM
0 = W/O TPM

+5VS

SKL-U

12

RH71100K_0402_5%

1 2

RH72100K_0402_5% @

JUART1

1

1

2

2

3

3

4

4

5

GND

6

GND

CVILU_CI1804M1VRA-NH

CONN@

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

+3V_PCH

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

GPP_D9
GPP_D10
GPP_D11
GPP_D12

6 OF 20

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

DCI_CLK <31>
DCI_DATA <31>

DDR_CHB_EN
DDR_CHA_EN
BID_BC
PCH_TBT_PERST#

UART1_RXD
UART1_TXD

SUPPLIER_ID0
SUPPLIER_ID1

TBT_PWR_EN

PCH_TBT_PERST# <41>

PCH_MUTE# <24>

@

PAD~D

+3.3V_1.8V_PGPPA +3.3V_1.8V_PGPPA

1 2

@

1 2

RH88 RH89

*

V V

V V
V V

PVT_0011

T9

100K_0402_5%
RH87

100K_0402_5%
RH88

RH86RH87

+3VS

DDR_CHA_EN
DDR_CHB_EN

DDR_CHA_EN
DDR_CHB_EN

PCH_TBT_PERST#

PCH_TBT_PERST#

Produc t

XPS
L

POP
RH84
RH85

1 2

RH66 100K_0402_5%~D

1 2

RH67 100K_0402_5%~D

1 2

RH68 SHORT PADS@

1 2

RH69 SHORT PADS@

RC395

@

1 2

High
Low

@

12

RH90100K_0402_5%~D

+3V_PCH

1 2

1 2

1 2

@

1 2

RH84
100K_0201_5%

RH85
100K_0201_5%

100K_0402_5%
RH86

100K_0402_5%
RH89

10K_0402_5%

BID_BC

STATUS

SUPPLIER_ID0SUPPLIER_ID1

+3V_PCH

XPS@

L@

REV

0 0

VV

0 1
1 0
1 1

Supplier A
Supplier B
Supplier C
Supplier D

BOOT BIOS Dest i nat i on(Bi t 6)

HIGH
LOW(DEFAULT)

LPC
SPI

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P10-MCP(4/14)GSPI,I2C,UART,ISH

P10-MCP(4/14)GSPI,I2C,UART,ISH

P10-MCP(4/14)GSPI,I2C,UART,ISH

LA-E671P

LA-E671P

LA-E671P

1

10 61Tuesday, October 17, 2017

10 61Tuesday, October 17, 2017

10 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

4

3

2

1

UCPU1H

@

PCIE/US B3/SATA

D D

C C

M.2 SSD
PCIe Gen3 x 4

B B

Cardreade r
PCIe Gen2 x 1

WLAN
PCIe Gen2 x 1

Alpine Ridge
PCIe Gen3 x 4

SATA SSD

PCIE_PRX_CARDTX_N1<29>
PCIE_PRX_CARDTX_P1<29>
PCIE_PTX_CARDRX_N1<29>
PCIE_PTX_CARDRX_P1<29>

PCIE_PRX_WLANTX_N3<28>
PCIE_PRX_WLANTX_P3<28>
PCIE_PTX_WLANRX_N3<28>
PCIE_PTX_WLANRX_P3<28>

PCIE_PRX_TBTX_N5<41>
PCIE_PRX_TBTX_P5<41>
PCIE_PTX_TBRX_N5<41>
PCIE_PTX_TBRX_P5<41>

PCIE_PRX_TBTX_N6<41>
PCIE_PRX_TBTX_P6<41>
PCIE_PTX_TBRX_N6<41>
PCIE_PTX_TBRX_P6<41>

PCIE_PRX_TBTX_N7<41>
PCIE_PRX_TBTX_P7<41>
PCIE_PTX_TBRX_N7<41>
PCIE_PTX_TBRX_P7<41>

PCIE_PRX_TBTX_N8<41>
PCIE_PRX_TBTX_P8<41>
PCIE_PTX_TBRX_N8<41>
PCIE_PTX_TBRX_P8<41>

PCIE_PRX_SSDTX_N9<30>
PCIE_PRX_SSDTX_P9<30>
PCIE_PTX_SSDRX_N9<30>
PCIE_PTX_SSDRX_P9<30>

PCIE_PRX_SSDTX_N10<30>
PCIE_PRX_SSDTX_P10<30>
PCIE_PTX_SSDRX_N10<30>
PCIE_PTX_SSDRX_P10<30>

1 2

RC50 100_0402_1%

CPU_XDP_PRDY#<15>
CPU_XDP_PREQ#<15>

PCIE_PRX_SSDTX_N11<30>
PCIE_PRX_SSDTX_P11<30>
PCIE_PTX_SSDRX_N11<30>
PCIE_PTX_SSDRX_P11<30>
SATA_PRX_SSDTX_N2<30>
SATA_PRX_SSDTX_P2<30>
SATA_PTX_SSDRX_N2<30>
SATA_PTX_SSDRX_P2<30>

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USB3RN1 <31>
USB3RP1 <31>
USB3TN1 <31>

USB3TP1 <31>

USB20_N1 <45>
USB20_P1 <45>

USB20_N5 <37>
USB20_P5 <37>

USB20_N7 <28>
USB20_P7 <28>

USB20_N10 <36>

USBCOMP
USB2_ID

VBUSSENSE
TBT_A_USB_OC0#

TBT_B_USB_OC1#
MUX_C_USB_OC2#
USB_OC3#

GPP_E1

USB20_P10 <36>

RC47 113_0402_1%
RC48 0_0402_1%@
RC49 1K_0402_5%

1 2

RC389 0_0402_5%@

@

1 2

RC52 0_0201_5%

1 2
1 2
1 2

TBT_A_USB_OC0# <43>
TBT_B_USB_OC1# <44>
MUX_C_USB_OC2# <45>

USB3.0 DP MX (PS8743B)

USB2.0 for USB PD PORT3

CAM & IR CAM

NGFF (WLAN)

Fingerprint

PVT_0008

B+_CAM_EN <37,38>
SSD_DEVSLP <30>

SSD_IFDET <30>

+3V_PCH

TBT_A_USB_OC0#
TBT_B_USB_OC1#
MUX_C_USB_OC2#
USB_OC3#

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P11-MCP(5/14)PCIE,USB,SATA

P11-MCP(5/14)PCIE,USB,SATA

P11-MCP(5/14)PCIE,USB,SATA

LA-E671P

LA-E671P

LA-E671P

1 2

RC53 10K_0402_5%

1 2

RC54 10K_0402_5%

1 2

RC55 10K_0402_5%

1 2

RC56 10K_0402_5%

11 61Tuesday, October 17, 2017

11 61Tuesday, October 17, 2017

1

11 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

Alpine Ridge--->

D D

WLAN--->

SDD--->

PVT_0011

Card Reader --->

+3VA_TBT

1 2

RC396 1K_0402_5%@

+3V_PCH_DSW

C C

B B

1 2

RC73 1K_0402_5%

1 2

RC74 10K_0402_5%

+1.0V_VCCST

1 2

RC79 1K_0402_5%

+3V_PCH

1 2

RC83 10K_0402_5%@

H_VCCST_PWRGD_P<15,36,38,39>

100P_0402_50V8J~D

CA1

1

2

EMC@

PCH_RSMRST#<15,38>

CLK0_PCIE_TBT#<41>
CLK0_PCIE_TBT<41>

CLKREQ_PCIE#0<41>

CLK1_PCIE_WLAN#<28>
CLK1_PCIE_WLAN<28>

CLKREQ_PCIE#1<28>

CLK_PCIE_SSD#<30>
CLK_PCIE_SSD<30>

CLKREQ_PCIE#3<30>

CLKREQ_PCIE#4<30>

CLK_PCIE_MMI#<29>
CLK_PCIE_MMI<29>

CLKREQ_PCIE#5<29>

PCH_PCIE_WAKE#

PCH_PCIE_WAKE#

LAN_WAKE#

H_VCCST_PWRGD_P

ME_SUS_PWR_ACK

@

T10

PAD~D

H_VCCST_PWRGD_PH_CPUPWRGD

100P_0402_50V8J~D

CA2

1

2

EMC@

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

IMVP_VR_PG<56>

PCH_RSMRST#

H_VCCST_PWRGD_P

1 2

RC58 10K_0402_5%

1 2

RC62 10K_0402_5%

1 2

RC63 10K_0402_5%@

1 2

RC65 10K_0402_5%

1 2

RC67 10K_0402_5%@

1 2

RC70 10K_0402_5%

1
2

RC390

@

1 2

0_0402_5%

1 2

RC381 10K_0402_5%

1 2

RC85 1K_0402_5%@

1 2

RC86 60.4_0402_1%

SYS_PWROK<15,38>

PCH_DPWROK_R<39>

ME_SUS_PWR_ACK<38>

SUSACK#<38>

PCH_PCIE_WAKE#<38,39,41>

LAN_WAKE#<38>

3.3V_CAM_EN#<33>

ME_SUS_PWR_ACK

PCH_PCIE_WAKE#
LAN_WAKE#

ESD Request:place near CPU side

RC90

POP

NO Support Deep sleep

DE-POP

Support Deep sleep

PCH_DPWROK_R PCH_RSMRST#

A A

1

2

RC90 0_0402_5%

@

0.01U_0402_16V7K

100K_0402_5%~D

12

CC12

RC92

1 2

5

PM_SYS_RESET#<15>

D42
C42

AR10

B42
A42

AT7
D41

C41
AT8

D40
C40

AT10

B40
A40

AU8

E40
E38

AU7

+3VS

PVT_0002

5

UC10

P

B

O

A

G

TC7SH08FU_SSOP5~D

3

IMVP_VR_PG_R

PCH_PLTRST#
SYS_RESET#

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD

IMVP_VR_PG_R

4

UCPU1J

@

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

IMVP_VR_PG_R

4

UCPU1K

@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

4

SKL_U LT

CLOCK SIGNALS

PCH_PLTRST#_EC<27,28,29,30,39,41>

SYSTEM POWER MANAGEMENT

1 2

@

RC87 0_0402_1%

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SKL-U

3

1 2

SUSCLK

RC57 1K_0402_5%@

CLK_ITPXDP_N_R

F43

CLK_ITPXDP_P_R

E43
BA17

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

E37
E35

E42
AM18

AM20
AN18

AM16

SUSCLK
XTAL24_IN

XTAL24_OUT
XCLK_BIASREF
PCH_RTCX1

PCH_RTCX2

SRTCRST#

PCH_RTCRST#

CMOS1 must take care short & touch risk on layout placement

12

RC76

100K_0402_5%

PCH_BATLOW#
AC_PRESENT

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

SYS_RESET#_R

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AT11
AP15
BA16
AY16

AN15

SLP_SUS#

AW15

SLP_LAN#

BB17
AN16

BA15
AY15
AU13

AU11
AP16

INTRUDER#

AM10
AM11

11 OF 20

1 2

RC89 1K_0402_5%

3

1 2

RC60 47_0402_5%EMC@

1 2

RC61 47_0402_5%EMC@

CC93 0.1U 16V K X5R 0201EMC@

1 2

RC64 2.7K_0402_1%

1 2

RC68 20K_0402_5%

1 2

CC9 1U_0402_6.3V6K

1 2

RC71 20K_0402_5%

1 2

CC11 1U_0402_6.3V6K

1

1

SHORT PADS~D

@

CMOS1

+3VS

5

1

P

B

4

O

2

A

G

UC2

TC7SH08FU_SSOP5~D

3

PVT_0002

1 2

RC80 8.2K_0402_5%

1 2

RC82 10K_0402_5%

SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#

AC_PRESENT
PCH_BATLOW#

PME#
INTRUDER#

VRALERT#

+3VS

12

SYS_RESET#

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

SIO_SLP_S0# <27,34,60>
SIO_SLP_S3# <36,38,39,41>
SIO_SLP_S4# <36,38>
SIO_SLP_S5# <38>

SIO_SLP_SUS# <33,36,38,53,54,60>

PAD~D

SIO_SLP_WLAN# <38>
SIO_SLP_A# <38>

SIO_PWRBTN# <12,15,38>

AC_PRESENT <38>

PAD~D

MPHYP_PWR_EN <34>

RC88

10K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

+1.0V_CLK

2

2

1 2

+3V_PCH_DSW

@

T11

@

T12

Deciphered Date

Deciphered Date

Deciphered Date

CLK_ITPXDP_N <15>
CLK_ITPXDP_P <15>

SUSCLK <28,30>

PCH_PLTRST#

RC77

@

10K_0402_5%

XTAL24_IN
XTAL24_OUT

2

RC375 33_0201_1%
RC376 33_0201_1%

PCH_RTCX1
PCH_RTCX2

+RTCVCC

INTRUDER#

VRALERT#

2

U22U23@

12
12

U22U23@

RC69 0_0402_1%

PVT_0008

+RTCVCC

1 2

RC78 1M_0402_5%

1 2

RC81 10K_0402_5%

+3V_PCH

1

CC6

1 2

15P_0402_50V8J

U22U23@

CC7

1 2

15P_0402_50V8J

U22U23@

CC8

1 2

6.8P_0402_50V8J

YC2
9PF 20PPM 9H03280012

ESR MAX=50k ohm

CC10

1 2

6.8P_0402_50V8J

RC66
10M_0402_5%

1 2

1 2

U22U23@

@

U22U23@

1M_0402_1%

RC59

1 2

PCH_RTCX2_R

3

4

YC1
24MHZ_12PF_X3G024000DC1H

1

2

12

APS CONN

JAPS1

+3V_PCH

+3VALW

+3V_PCH

PCH_RTCRST#<38>
SIO_PWRBTN#<12,15,38>

SIO_SLP_S3#
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#
SIO_SLP_S0#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CONN@

ACES_50506-01841-P01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P12-MCP(6/14)CLK,PM,RTC

P12-MCP(6/14)CLK,PM,RTC

P12-MCP(6/14)CLK,PM,RTC

LA-E671P

LA-E671P

LA-E671P

1

12 61Tuesday, October 17, 2017

12 61Tuesday, October 17, 2017

12 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

D D

C C

HDA_SDOUT HDA_SDIN0 HDA_RST#

2

RF@

CR24

2.2P_0201_25V

1

2

RF@

CR25

2.2P_0201_25V

1

4

2

RF@

CR26

2.2P_0201_25V

1

3

2

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he SPI f l ash to be updat ed usi ng FPT.

HDA_SDOUT

ME_FWP_EC<38>

+3VS_AUDIO

12

RC110
1K_0402_5%

1

ME_EN

12

RH731K_0402_5%~D

12

R10_0402_1% @

2
3

4
5

@

SW1

@

G
G

SSAL120100_3P

1

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short

UCPU1G

@

1 2

HDA_SYNC_R<24>

HDA_BIT_CLK_R<24>

HDA_SDOUT_R<24>

HDA_SDIN0<24>

RTD3_USB_PWR_EN<41>

HDA_BIT_CLK_R

1

B B

CC13

22P_0402_50V8J

Close to RC112

+3V_PCH

1 2

RC41 100K_0402_5%~D

2

RTD3_CIO_PWR_EN<41>
TBT_FORCE_PWR<41>

TBT_BATLOW#<41>

KB_DET#<35>

KB_DET#

RC111 33_0402_5%

1 2

RC112 33_0402_5%

1 2

RC113 33_0402_5%

RC115 0_0402_1%@
RC117 0_0402_1%@

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0

HDA_RST#

T15PAD~D @

SPKR<24>

PCH_RTD3_CIO_PWR_EN
PCH_TBT_FORCE_PWR

KB_DET#

SPKR

12
12

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

AW5

J5

AK7
AK6
AK9

H5
D7

D8
C8

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

SKL-U

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

7 OF 20

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

CAM_CBL_DET#

SD_RCOMP

1 2

RC116 200_0402_1%

CAM_CBL_DET# <37>
TBT_CIO_PLUG_EVENT# <41>

SSD_PWR_EN <33>

SPK_DET# <25>

Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default posit i on)

CAM_CBL_DET#

1 2

RC114 100K_0402_5%~D

+3VS

+3V_PCH +3V_PCH

A A

1 2

RC118 2.2K_0402_5%@

TOP SWAP STRAP

HIGH
LOW(DEFAULT)

ENABLE
DISAB LE

SPKR

5

RC119 4.7K_0402_5%

@

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

1 2

HDA_SDOUT

DISABLE

ENABLE

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P13-MCP(7/14)MISC,JTAG,HDA,SDIO

P13-MCP(7/14)MISC,JTAG,HDA,SDIO

P13-MCP(7/14)MISC,JTAG,HDA,SDIO

LA-E671P

LA-E671P

LA-E671P

1

13 61Tuesday, October 17, 2017

13 61Tuesday, October 17, 2017

13 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

No stall(Normal Operat i on)

D D

4

DG Note:
CAZ60 layout at DVT2 remove it XDP nets

CFG[0..15]<15>

3

2

1

UCPU1S

@

1 2

RC120 10K_0402_1%

@

Stall reset sequence

HIGH(DEFAULT)
LOW

C C

1 2

RC123 1K_0402_5%

eDP enable

HIGH(DEFAULT)
LOW

B B

CFG0

sta ll

CFG4

Disa bled
Enabled

10K_0402_1%

@
@

10K_0402_1%

+1.0VA_XDP

XDP_ITP_PMODE<15>

@

T80

PAD~D

1 2

RC121

@

T78

PAD~D

1 2

RC122

@

T81

PAD~D

@

T79

PAD~D

@

T82

PAD~D

@

T83

PAD~D

@

T84

PAD~D

@

T85

PAD~D

@

T86

PAD~D

@

T87

PAD~D

CFG12<15>

@

T88

PAD~D

CFG14<15>

@

T89

PAD~D

CFG16<15>
CFG17<15>

CFG18<15>
CFG19<15>

RC124 49.9_0402_1%
RC125 1.5K_0402_5%

@

T23

PAD~D

@

T25

PAD~D

VSS_F65_G65

1 2

CFG_RCOMP

12
12

U42@

RC391
0_0201_5%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60
A52

J71
J68

F65
G65

F61
E61

SKL-U_BGA1356

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP
ITP_PMODE
RSVD_AY2

RSVD_AY1
RSVD_D1

RSVD_D3
RSVD_K46

RSVD_K45
RSVD_AL25

RSVD_AL27
RSVD_C71

RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70

RSVD_TP_BA68
RSVD_J71

RSVD_J68
VSS_F65

VSS_G65
RSVD_F61

RSVD_E61

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5

TP4

A69
B69

AY3
D71

C70
C54

D54
AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

RC126 100K_0402_5%

1 2

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

LPM_ZVM_N <61>

PAD~D
PAD~D

MSM_N <61>

T16
T17

T18
T19

T20
T21

T22

T24
T26

@
@

T27
T28

Support for KBL-R U4+2

XTAL24_IN_RU
XTAL24_OUT_RU

RC377 33_0201_1%
RC378 33_0201_1%

ZVM# for SKYLAKE-U 2+3e

+1.0V_VCCST

MSM# for SKYLAKE-U 2+3e

XTAL24_OUT_RU

U42@

12
12

U42@

AW69
AW68

AU56

AW48

C7
U12
U11
H11

UCPU1T

@

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

SKL-U_BGA1356

SKL-U

SPARE

U42@

1M_0402_1%

3

4

RC374

1

2

1 2

U42@

F6

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

YC3
24MHZ_12PF_X3G024000DC1H

20 OF 20

XTAL24_IN_RU

E3
C11
B11
A11
D12
C12
F52

CC91

1 2

15P_0402_50V8J

U42@

CC90

1 2

15P_0402_50V8J

U42@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P14-MCP(8/14)CFG,RSVD

P14-MCP(8/14)CFG,RSVD

P14-MCP(8/14)CFG,RSVD

LA-E671P

LA-E671P

LA-E671P

1

14 61Tuesday, October 17, 2017

14 61Tuesday, October 17, 2017

14 61Tuesday, October 17, 2017

1.0

1.0

1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

5

4

3

2

1

+1.0V_VCCST

+1.0V_VCCSTG

+3V_PCH

D D

+3V_PCH

+1.0VA_XDP

+1.0V_VCCSTG

C C

1 2

RC218 1K_0402_1%

1 2

RC219 49.9_0402_1%@

1 2

RC221 1K_0402_1%

1 2

RH81 10K_0201_5%

+3VS

@

1 2

RH82 10K_0201_5%

1 2

RC225 100K_0201_5%XDP@

1 2

RC226 1K_0402_5%XDP@

RC230 51_0402_5%@

12

PU/PD for CPU JTAG signals

+1.0V_VCCSTG

RC239 51_0402_5%
RC240 51_0402_5%
RC242 100_0402_1%

R1

RC244 51_0402_5%

R2

RC217 51_0402_5%@

PU/PD for PCH JTAG signals

+1.0V_VCCSTG

B B

RC252 51_0402_5%

R5

RC254 51_0402_5%

R4

RC255 100_0402_1%

R3

RC257 51_0402_5%@
RC258 51_0402_5%@

R6

12
12

1 2

12
12

Connect to XDP Conn.
(Option w/ CPU JTAG)

12
12

1 2

12
12

12

CC89@ 0.1U_0402_25V6

Place near JXDP1.47

A A

RESET_OUT#_R

5

H_THERMTRIP#_R
H_CATERR#

H_PROCHOT#

SIO_EXT_SMI#

TOUCH_SCREEN_PD#

PVT_0018

XDP_PRSENT#

XDP_RST#

CPU_XDP_PREQ#

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

CPU_XDP_TCK
CPU_XDP_TRST#

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

PCH_JTAGX
PCH_JTAG_TCK

TOUCH_SCREEN_PD#<37>
TP_INTR#<36,38>

<XDP Misc.>

CC87

0.1U_0201_10V6K

Place near JXDP1.41Place near JXDP1.48

1

XDP@

2

4

CPU MISC

XDP_TDI
XDP_TMS

XDP_TDO
XDP_TDI
XDP_TMS

XDP_TCK0
XDP_TCK1

RC253

1 2

XDP@

RC256

1 2

XDP@

1K_0402_1%

Deciphered Date

Deciphered Date

Deciphered Date

SKL-U

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

XDP_OB S0

T70@

XDP_OB S1

T73@

XDP CONN

+1.0VA_XDP +1.0VA_XDP

XDP_PIN1

1K_0402_1%

1
3
5
7
9

61
62

E-T_6601K-Y61N-04L

2

JXDP1

1
3
5
7
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
61

GND

CONN@

CPU_XDP_TCK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

PCH_JTAG_TRST#

C61

PCH_JTAGX

A59

2
4
6
8

10

GND

+1.0VA_XDP+1.0VA +1.0VA_XDP

RC251

1 2

XDP@

0_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

XDP_RST#

46

XDP_DBRESET#

48
50

XDP_TDO

52

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58

XDP_PRSENT#

60

63

CFG8_1
CFG9_1

CFG10_1
CFG11_1

CFG13_1

CFG15_1

CFG17 <14>
CFG16 <14>

@

PAD~D

@

PAD~D

@

PAD~D

@

PAD~D

CFG19 <14>
CFG18 <14>

CFG12 <14>

@

PAD~D

CFG14 <14>

@

PAD~D

CLK_ITPXDP_P <12>
CLK_ITPXDP_N <12>

0.1U_0201_10V6K

T102
T101

T122
T121

T103

T104

CC85

XDP@

CFG8 <14>
CFG9 <14>

CFG10 <14>
CFG11 <14>

CFG13 <14>

CFG15 <14>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P15-MCP(9/14)XDP

P15-MCP(9/14)XDP

P15-MCP(9/14)XDP

LA-E671P

LA-E671P

LA-E671P

1

1

1

CC86

XDP@

0.1U_0201_10V6K

2

2

<XDP CLK>

From CPU

15 61Tuesday, October 17, 2017

15 61Tuesday, October 17, 2017

15 61Tuesday, October 17, 2017

1.0

1.0

1.0

UCPU1D

@

D63

A54
C65
C63

A65
C55

D55

B54
C56

A6

A7
BA5
AY5

AT16

AU16

H66
H65

SKL-U_BGA1356

12

CPU_XDP_PREQ#
CPU_XDP_PRDY#

CFG0_1
CFG1_1

CFG2_1
CFG3_1

XDP_OBS0_1
XDP_OBS1_1

CFG4_1
CFG5_1

CFG6_1
CFG7_1

PWRGD_XDP
XDP_PWRBTN#

RESET_OUT#_R

XDP_TCK1
XDP_TCK0

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

XDP_TDO
XDP_TCK0

XDP_TRST#

XDP_TRST#

RESET_OUT#_R
XDP_PRSENT#

XDP_PWRBTN#
XDP_DBRESET#
XDP_RST#
PWRGD_XDP

CFG3_1

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

RC107

49.9_0402_1%

DDR_XDP_SMBDAT<9>
DDR_XDP_SMBCLK<9>

3

H_CATERR#
H_PROCHOT#_RH_PROCHOT#

H_THERMTRIP#_R

SKTOCC#
XDP_BPM#0

XDP_BPM#1
XDP_BPM#2_R
XDP_BPM#3_R

SIO_EXT_SMI#
TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

RC108

RC109

49.9_0402_1%

49.9_0402_1%

1 2

RC227 0_0201_5%XDP@

1 2

RC228 0_0201_5%XDP@

1 2

RC229 0_0201_5%XDP@

1 2

RC231 0_0201_5%XDP@

1 2

RC232 0_0201_5%XDP@

1 2

RC233 0_0201_5%XDP@

1 2

RC234 0_0201_5%XDP@

1 2

RC235 0_0201_5%XDP@

1 2

RC236 0_0201_5%XDP@

1 2

RC237 0_0201_5%XDP@

1 2

RC238 0_0201_5%XDP@

Closed to CPU

1 2

RC370 0_0402_5%@

1 2

RC241 1K_0201_5%XDP@

1 2

RC243 1K_0201_5%XDP@

1 2

RC245 0_0201_5%XDP@

1 2

RC246 0_0201_5%XDP@

1 2

RC247 0_0201_5%XDP@

1 2

RC248 0_0201_5%XDP@
RC249 0_0402_5%XDP@

1 2

RC250 1K_0402_5%XDP@

1 2

RC371 1K_0402_5%@

CPU_XDP_PREQ#<11>
CPU_XDP_PRDY#<11>

@

T112

PAD~D

@

T111

PAD~D

@

T113

PAD~D

@

T114

PAD~D

@

T116

PAD~D

@

T115

PAD~D

@

T117

PAD~D

@

T118

PAD~D

@

T120

PAD~D

@

T119

PAD~D

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

PECI_EC<38>
H_PROCHOT#<38,50,56>

H_THERMTRIP#<39>

TOUCH_SCREEN_PD#

<To CPU JTAG>

<To PCH JTAG>

SYS_PWROK<12,38>

PCH_SPI_SI<9>

PCH_SPI_IO2<9>

H_VCCST_PWRGD_P<12,36,38,39>

<XDP SMBUS>

Link to PCH SMB

XDP_PWRBTN#XDP_DBRESET#

CC88

0.1U_0201_10V6K

1

XDP@

2

1 2

RC220 499_0402_1%

1 2

RC222 60.4_0402_1%
RC223 0_0402_5%@

PVT_0008

RC379 0_0402_1%@

AUD_PWR_EN<33>

SIO_PWRBTN#<12,38>
PM_SYS_RESET#<12>
XDP_ITP_PMODE<14>
PCH_RSMRST#<12,38>

DG Note:
CAZ60 layout at DVT2 remove it XDP nets

12

T50 @
T51 @

12

12

12

RC106

49.9_0402_1%

CPU_XDP_TDO
CPU_XDP_TCK
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TRST#

PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TRST#
PCH_JTAGX
PCH_JTAG_TCK

XDP_BPM#0
XDP_BPM#1

CFG0<14>
CFG1<14>

CFG2<14>
CFG3<14>

CFG4<14>
CFG5<14>

CFG6<14>
CFG7<14>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

D D

+VCC_EDRAM: 1V, 2.5A
+V1.8S_EDRAM: 1.8V, 50mA
+VCC_EOPIO: 0.8~1V, 2A

C C

+VCC_EDRAM Decoupling Requirment
Back Side (underneath the package):
10U_0402*1 pcs + 1U_0201*6 pcs

+VCC_EDRAM +VCC_EOPIO

+VCC_CORE: 0.55~1.5V, 29A

+1.8VA

PVT_0008

R2 @ 0_0603_5%

+VCC_EOPIO Decoupling Requirment
Back Side (underneath the package):
10U_0402*2 pcs

1 2

+VCC_EDRAM

+V1.8S_EDRAM

+VCC_EOPIO

+V1.8S_EDRAM

@

T29

PAD~D

@

T30

PAD~D

RC152 @ 0_0603_5%

VCC_EDRAM_SENSE<61>
VSS_EDRAM_SENSE<61>

VCC_EOPIO_SENSE<61>
VSS_EOPIO_SENSE<61>

BSC BSC

1

1

CC21

CC20

CC19

B B

2

10U_0402_6.3V6M

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CC22

CC23

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

1

1

CC24

CC25

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CC27

CC26

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

+VCC_CORE +VCC_CORE

+VCC_CORE_G0
+VCC_CORE_G1

1 2

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

G30

AK32
AB62

G61

AC63
AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

K32

P62
V62

H63

@

SKL-U_BGA1356

UCPU1L

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

CPU POWER 1 OF 4

1.5V@29A

1V@2.5A

1V@0.05A

1V@2A

SKL-U

VCC_SENSE
VSS_SENSE

VCCSTG_G20

SVID ALERT

VR_SVID_ALERT#<56>

SVID DATA

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VIDALERT#

VIDSCK

VIDSOUT

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

H_CPU_SVIDALRT#

B63

VIDSCLK_R

A63

VIDSOUT_R

D64
G20

+1.0V_VCCSTG_R

+1.0V_VCCST

+1.0V_VCCST

RC153 @ 0_0603_5%

56_0402_1%

12

RC154

100_0402_1%

12

RC156

+VCC_CORE

12

Close CPU

RC150

100_0402_1%

VCC_SENSE <56>

RC151

100_0402_1%

VSS_SENSE <56>

+1.0V_VCCSTG

12

1 2

PVT_0008

CAD Note: Place the PU resistors close to CPU
RC154 close to CPU 1000 - 1500mils

H_CPU_SVIDALRT#

12

RC155220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC156close to CPU 1000 - 1500mils

VIDSOUT_R

12

VR_SVID_DATA<56>

SVID CLK

VR_SVID_CLK<56>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

+1.0V_VCCST

Deciphered Date

Deciphered Date

Deciphered Date

100_0402_1%

@

12

RC158

2

RC1570_0402_1% @

CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils

12

VIDSCLK_R

RC1590_0402_1% @

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P16-MCP(10/14)PWR-VCC CORE

P16-MCP(10/14)PWR-VCC CORE

P16-MCP(10/14)PWR-VCC CORE

LA-E671P

LA-E671P

LA-E671P

1.0

1.0

16 61Tuesday, October 17, 2017

16 61Tuesday, October 17, 2017

1

16 61Tuesday, October 17, 2017

1.0

5

4

3

2

1

+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A

D D

C C

Close CPU

VCCGT_SENSE<56>

B B

VSSGT_SENSE<56>

+VCCGT +VCCGT

+VCCIA_GT

K52

+VCCGT

12

RC160

100_0402_1%

12

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

M62
N63
N64
N66
N67
N69

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58

J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71

J70

J69

UCPU1M

@

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL-U_BGA1356

SKL-U

CPU POWER 2 OF 4

1.5V@54A

1.5V@7A

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70

VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCCIA_GT

+VCCGT

AK52 K52

VCCGTX for SKYLAKE-U 2+3e
Merged the GT and GTx rail

T31 PAD~D @
T32 PAD~D @

Note: 4+2 Co-layout Only can use SD00001VZ00

+VCCIA_GT +VCCGT+VCC_CORE

R275U42@

1/2W 0.0002 +-5%

1 2

R277U42@

1/2W 0.0002 +-5%

1 2

@

1 2

AK52

R279 0_0402_5%

@

1 2

R280 0_0402_5%

KBL-R U42 Only Design

KBL-R U42 Compatible Design for
(KBL-R U42/KBL U22/KBL U23e) support

AK52 and K52 Kaby Lake Silicon Ball Connectivity Recap from PDG (568813_KBL_R_U42_PDG_Addendum_Rev0p9, Page 12)

+VCCIA_GT

+VCCGT

Do not Connect AK52 and K52 Balls,
Keep as NC

Do not Connect AK52 and K52 Balls,
Keep as NC

R276U22U23@

1/2W 0.0002 +-5%

1 2

R278U22U23@

1/2W 0.0002 +-5%

1 2

RC161

100_0402_1%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P17-MCP(11/14)PWR-VCCGT

P17-MCP(11/14)PWR-VCCGT

P17-MCP(11/14)PWR-VCCGT

LA-E671P

LA-E671P

LA-E671P

1

17 61Tuesday, October 17, 2017

17 61Tuesday, October 17, 2017

17 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

4

3

2

1

+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A

D D

C C

+VCC_SA: 1.15V, 5.1A

1 2

RC162 0_0402_1%

PVT_0008

+1.0V_VCCST

close to package

1

2

@

PSC

CC28

1U_0402_6.3V6K

PVT_0009

+1.2V_MEM_CPUCLK+1.2V_DDR

+1.0V_VCCSTG

1

@

2

CC97

0.1U_0402_10V7K

BSC

underneath the package

1

CC29

2

@

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

+VCCPLL_OC +1.0V_VCCST

PSC

1

CC30

2

1U_0201_6.3V6M

+1.2V_DDR

1V@0.12A
1V@0.04A

1.2V@ 0.2 6A
1V@0.12A

close to packageclose to package

1

CC96

@

2

PVT_0009

+1.0VS_VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

VCCIO_SENSE

AM23

VSSIO_SENSE

AM22
H21

H20

14 OF 20

1 2

RC166 100_0402_1%

+VCCSA

+1.0VS_VCCIO

12

12

12

RC165
0_0201_5%

RC164

100_0402_1%

VSSSA_SENSE <56>
VCCSA_SENSE <56>

Close CPU

RC163

100_0402_1%

VCCIO_SENSE <60>

CPU POWER 3 OF 4

1.2V@3.5A

1.15V @5. 1A

SKL-U

0.95V @3. 1A

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

+VCCSA

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

UCPU1N

@

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

SKL-U_BGA1356

PSC

1

CC31

2

0.1U_0402_10V7K

1U_0402_6.3V6K

+1.2_DDR Decoupling Requirment
Back Side (underneath the package):
10U_0402*2 pcs + 1U_0201*4 pcs (@)
Primary Side (close to package):
10U_0402*4 pcs + 22U_0603*3 pcs

B B

+1.2V_DDR

PSC

1

1

1

CC32

CC33

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC34

CC35

2

2

22U_0603_6.3V6M

10U_0402_6.3V6M

1

1

CC38

CC37

CC36

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

BSC

1

1

CC45

2

2

@

10U_0402_6.3V6M

A A

5

1

1

CC46

2

@

10U_0402_6.3V6M

1

1

CC48

CC47

@

1U_0201_6.3V6M

4

CC49

2

@

1U_0201_6.3V6M

CC50

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

+1.0VS_VCCIO Decoupling Requirment
Back Side (underneath the package):
10U_0402*2 pcs + 1U_0201*4 pcs (@)
Primary Side (close to package):
1U_0402*4 pcs

+1.0VS_VCCIO

PSC

1

1

CC39

2

2

1U_0402_6.3V6K

1

1

CC40

1U_0402_6.3V6K

CC42

CC41

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

BSC

1

1

1

CC51

CC52

2

2

2

@

@

10U_0402_6.3V6M

10U_0402_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

CC54

2

@

1U_0201_6.3V6M

1

CC55

CC56

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

CC53

2

@

1U_0201_6.3V6M

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

+1.2V_MEM_CPUCLK (VDDQC) Place on CPU
Back Side (underneath the package):
1U_0201*1 pcs (@)
Primary Side (close to package):
10U_0402 * 1 pcs

+1.2V_DDR

BSC

PSC

1

1

CC44

CC43

2

2

@

1U_0201_6.3V6M

10U_0402_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P18-MCP(12/14)PWR-VCCIO,MEM

P18-MCP(12/14)PWR-VCCIO,MEM

P18-MCP(12/14)PWR-VCCIO,MEM

LA-E671P

LA-E671P

LA-E671P

1

18 61Tuesday, October 17, 2017

18 61Tuesday, October 17, 2017

18 61Tuesday, October 17, 2017

1.0

1.0

1.0

5

4

3

2

1

PCH PWR

D D

C C

B B

+3VALW +1.8VA +1.0VA +1.0V_PRIM_CORE

1

2

+1.0VA

+3V_PCH +3.3V_SPI

47U_0603_6.3V

CC60

47U_0603_6.3V

1

2

PVT_0008

RC168

0_0603_5%

1 2

@

RC169

0_0603_5%

1 2

@

RC170

0_0603_5%

1 2

@

CC61

47U_0603_6.3V

CC62

1

2

+1.0V_MPHYAON

+1.0V_DTS

47U_0603_6.3V

1

2

PVT_0008

+1.0V_MPHYGT

+1.0V_SRAM

RC171
0_0603_5%

1 2

@

+1.0V_APLLEBB

RC172
0_0603_5%

1 2

@

PVT_0008

RC173

0_0603_5%

1 2

PVT_0008

+1.0V_AMPHYPLL+1.0V_MPHYGT

@

close UC1.K15 and <120mil

1

CC80

2

@

1U_0402_6.3V6K

CC63

1

CC65

CC66

2

@

1U_0402_6.3V6K

close UC1.AL1 and <120mil

CC71

1U_0402_6.3V6K

close UC1.AJ19 and <400mil

close UC1.AF20 and <400mil

1

CC78

2

@

+1.0V_APLLEBB

1U_0402_6.3V6K

+3V_PCH

12

R3
0_0201_5%

1

2.2P_0201_25V
CC77

RF@

2

RF@

+1.8VA

1

2

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

RA65

BLM18EG221TN1D_2P~D

1 2

+3V_PCH

1

Place near AJ19

CC94

2

RF@

0.1U_0402_10V7K

RC176
0_0603_5%

1 2

@

1

CC64

2

1U_0402_6.3V6K

close UC1.K17 and <120mil

47U_0603_6.3V

CC70

1

1

2

2

@

+1.0V_SRAM

2

RF@

CC95

2.2P_0201_25V

1

+1.8V_PGPP

PVT_0008

+1.0VA+1.0V_PRIM_CORE+1.0V_MPHYAON

close UC1.AB19 and <400mil

1

CC67

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0VA

+3V_PCH_DSW

VCCHDA

+3.3V_SPI

+3V_PCH

close UC1.N18 and <120mil

1

2

+1.0VA

CC79

1U_0402_6.3V6K

close UC1.V15 and <100mil

1

2.2P_0201_25V
CE96

RF@

2

1.0V@0.696A

1.0V@2.57A

1.0V@0.022A

1.0V @2.1 A

1.0V@0.088A

1.0V@0.026A

3.3V@0.118A

3.3V@0.068A

3.3V@0.011A

1.0V@0.642A

3.3V@0.075A

1.0V@0.033A

RC177

RF@

BLM18EG221TN1D_2P~D

1 2

+1.0V_APLL+1.0VA

AB19
AB20

AF18
AF19

AB17

AD17
AD18
AJ17

AJ19
AJ16
AF20

AF21

AJ21
AK20

P18

V20
V21

AL1
K17

L1

N15
N16
N17
P15
P16

K15
L15

V15

Y18

T19
T20

N18

12

@

SKL-U_BGA1356

1

2

+1.8VA +3.3V_1.8V_PGPPA

RC384

1 2

0_0402_1%

UCPU1O

CPU POWER 4 OF 4

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0
VCCMPHYAON_1P0

VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15

VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0
VCCPRIM_1P0_AB17

VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17

VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA
VCCSPI
VCCSRAM_1P0

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB

R4

RF@

0_0201_5%

2.2P_0201_25V
CE84

RF@

+3.3V_1.8V_ESPI

RC386

@

SKL-U

+3VALW +3V_PCH_DSW

1 2

@

0_0402_1%

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

RC174

0_0603_5%

1 2

@

PVT_0008

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

1

2

1 2

PVT_0008

+3.3V_1.8V_PGPPA

1.0V@0.085A

1.0V@0.161A

1.8V@0.006A

3.3V@0.001A

3.0V@0.001A

close UC1.BB10 and <120mil

1.0V@0.135A

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

CC81

CC82

1

2

RC167

0_0603_5%

@

+3.3V_PGPP

+1.8V_PGPP
+3.3V_PGPP

close UC1.V19 and <120mil

+1.0V_DTS

+1.0V_CLK

CORE_VID0 <60>
CORE_VID1 <60>

close UC1.AG15 and <120milclose UC1.Y16 and <400milclose UC1.T16 and <400mil

1

CC57

2

@

1U_0402_6.3V6K

+3V_PCH +1.8VA

12

close UC1.AA1 and <400mil

close UC1.AK19 and <120mil

1

1

CC72

2

CC76

2

0.1U_0402_10V7K

RC175

0_0603_5%

1 2

PVT_0008

CC68

4.7P_0402_50V8C

1

CC73

2

1U_0402_6.3V6K

0.1U_0402_10V7K

@

1

CC58

2

@

1U_0402_6.3V6K

1

CC69

2

1U_0402_6.3V6K

close UC1.AK17 and <120mil

+RTCVCC

1

CC74

2

+1.0V_CLK+1.0VA

close UC1.A10 and <120mil

1

CC83

2

@

1U_0402_6.3V6K

+3V_PCH

1

2

0.1U_0402_10V7K

+3.3V_PGPP+3V_PCH

1

CC59

2

@

1U_0402_6.3V6K

CC75

1U_0402_6.3V6K

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/12/16 2016/12/13

2015/12/16 2016/12/13

2015/12/16 2016/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P19-MCP(13/14)PCH PWR

P19-MCP(13/14)PCH PWR

P19-MCP(13/14)PCH PWR

Document Number Re v

Document Number Re v

Document Number Re v

LA-E671P

LA-E671P

LA-E671P

1

19 61Tuesday, October 17, 2017

19 61Tuesday, October 17, 2017

19 61Tuesday, October 17, 2017

1.0

1.0

1.0