Dell XPS 13 7390 boardview

A

B

C

D

E

MODEL NAME :

PCB NO :

LA-G172P

Centenario (DDP31)

BOM P/N :

1 1

ZZZ1 LA-G172P_MB

Dell/Compal Confidential

2 2

Schematic Document

(CENTENARIO ICE Lake U)

3 3

2019-05-29

Rev: 1.0 (A00)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

P001 - Cover

LA-G172P

E

1 101Wednesday, May 29, 2019

1.0 (A00)

A

SSD 20x16 BGA 128G/256GB / 512GB

1 1

RFFEM

uSD Connector

M.2 SSD-Key B Debug

WLAN/BT 5.1 Solder down Harrison Peak AX 22560 &Killer 1435-S 1216 SIP

SD4.0/SDXC

SD_WP

p.52

p.68

p.67

6 1 2 1

GPIO (BIOS Controlled)

TBT ~4dB/2"

2SBU

Burnside Bridge TBT Re-Timer

TPS65987-DH

USB Type-C TBT with PD

2 2

(Left)

VBUS

USB (Top)

USB (Bottom)

p.43

VBUS

PP_HV1

PP_HV2

CC

2CC VCONN

I2C2

I2C1

p.42

SPI

USB2/I2C MUXES_L

p.50

CHRG_IN

5VALW

I2C

to EC

I2C

USB

TBT ~4dB/2"

2SBU

Burnside Bridge TBT Re-Timer

TPS65987-DH

USB Type-C TBT with PD (Right)

USB (Top)

VBUS

3 3

p.45

USB (Bottom)

VBUS

PP_HV1

PP_HV2

CC

VCONN2CC

I2C2

I2C1

p.44

SPI

USB2/I2C MUXES_R

p.50

CHRG_IN

5VALWB

I2C

to EC

I2C

USB

B

TPM1.2/2.0 ST ST33TPHF2XSPI

Card Reader 4.0 RealTek RTS5242 PCIe to SD

p.46,47

p.48,49

PCH SPI Flash ROM 32M

p.70p.70

SMBUS

TBT ~15dB / 7"

LSx / AUX

I2C

SMBUS

TBT ~15dB / 7"

LSx / AUX

I2C

p.9

p.66

PCIe Gen3 x 4lanes

PCIe Gen3 x 2lanes

PCIe Gen2 x 1lane

USB2.0

CNVi Gen2

PCIe Gen2 x 1lane

RT SPI Flash ROM 8M

p.46

PD SPI Flash ROM 8M

p.42

RT SPI Flash ROM 8M

p.48

PD SPI Flash ROM 8M

p.44

SPI

SPI#0

PCIe#9,10,11,12

PCIe#13,14

PCIe#3

USB2#3

CNVi Gen2

PCIe#16

SML#0

TBT#0

LSx / AUX

SML#1

USB2#8

IceLake-U 4+2

TBT#2

LSx / AUX

USB2#9

DDI#A

I2C#0

CSI2-E#1

I2C#3

ISH_I2C#1

SMB

DMIC

HDA

ISH_I2C#0

USB2#1

USB3#2

ISH_GP#5

C

eDP x4 lanes

I2C

Memory Bus (LPDDR4 / x)

Dual Channel 3733MHz

Memory Bus (LPDDR4 / x)

Dual Channel 3733MHz

MIPI CSI-2 x 1lanes

I2C ISH_I2C

SMB

DMIC

HDA

ISH_I2C

USB2.0

USB3.1

NB_LID#

D

LPDDR4 4GB X32x4 Memory Down LPDDR4x 8/16/32 GB X32x4 Memory Down

LPDDR4/x - ChA

p.23,24

LPDDR4/x - ChB

p.23,24

MIPI60 Debug

p.79

DMIC

Audio Codec with Amplifier ALC3281-CG

p.56

USB DCI Debug

p.79

Universal Headset Jack

2xSpeaker

p.57

Hinge up

13.3" 16:10 Sharp FHD+/UHD+ eDP v1.4b LED Driver Artic sand ARC3C0845

Touch Screen Controller Wacom G14T-W90xx

Middle Board

Gyro + Accelerometer ST LSM6DS3USTR

e-compass ST LIS2MDLTR

Sensor Board

Gyro + Accelerometer ST LSM6DS3USTR

e-compass ST LIS2MDLTR

p.38

E

UFCAM module

RGB camera OV01A

CAM LED

AMS TSL2584TSV

DMIC

2xDMIC

Fingerprint module

Fingerprint Controller

EC UART Debug/80 port

SPI Programmer

PD Programmer/I2C

DCI Debug

GOODIX GF5288+HT32

Power Button

MIPI60 Debug

APS Debug

BIOS UART Debug

JESPI Debug

p.77

PWRBTN#

p.77

to Battery Gauge FPC

to PD & USB2/I2C MUXES

4 4

RT Programmer

VCCIN Controller MP2940AGRT

Coin Cell

Charger

Battery Connector

A

B

USB2.0

USB2#5

GPP_D13 GPP_D14

SMBUS

ISH_GP#6

I2C#1

eSPI

SMB#03 GPIO

GPIO

p.91

p.83

BATBTN#

SMBUS

GPIO

EC MEC5105

SMB#04

SMB#05

SMB#10

GPIO

GPIO 161 (VCI_IN2#)

PWM#0

PWM#1

BCM#1

PS/2

SMB#00

LED

p.82

p.33

Hinge Down

TAB_LID#

I2C

TAB_LID#

NB_LID#

PWM

BC Bus

PS/2

SMBUS

C

Fan 1

Fan 2

p.77

KB Transfer Board

+3V_NB_LID

Hall Sensor BU52058

2nd Accelerometer ST LNG2DMTR

KB Controller ECE1117

+3V_NB_LID

Keyboard

Touchpad

Battery Gauge

LNG2DMTR

D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P002 - Block Diagram

Size Document Number Rev

LA-G172P

Date: Sheet of

E

2 101Friday, May 24, 2019

1.0 (A00)

A

Board ID Table

3.3V +/- 5%Vcc

0 1 2 3 4 5 6 7

RBoard ID

240K +/- 5% 4700p 130K +/- 5% 62K +/- 5% 33K +/- 5%

8.2K +/- 5%

4.3K +/- 5% 2K +/- 5% 1K +/- 5% 4700p

C

4700p 4700p 4700p 4700p 4700p 4700p

SMBUS Control Table

SOURCE

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

EC_SMB03_CLK EC_SMB03_DAT

EC_SMB04_CLK EC_SMB04_DAT

EC_SMB05_CLK EC_SMB05_DAT

EC_SMB10_CLK EC_SMB10_DAT

EC_SMB00_CLK EC_SMB00_DAT

PCH

MEC5105

PCH

V

BATT Connector

V

Charger

V

REV

M00 X00 X01 X02 X03

VCCIN ControllerPDController

V

PCB Revision

0.1

0.2

0.3

0.4

0.5

V

MIPI60

V

USB/I2C MUX

V

BurnSide Bridge

V V

Accel+Gyro

V

PCIE/USB3.1

Flexible I/O

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Interface DESTINATION

PCI-E#1 / USB 3.1#1

PCI-E#2 / USB 3.1#2

PCI-E#3 / USB 3.1#3

PCI-E#4 / USB 3.1#4

PCI-E#5 / USB 3.1#5

PCI-E#6 / USB 3.1#6

PCI-E#7

PCI-E#8

PCI-E#9

PCI-E#10

PCI-E#11 / SATA#0

PCI-E#12 / SATA#1a

PCI-E#13

PCI-E#14

PCI-E#15 / SATA#1b

None

USB DCI Debug

WLAN PCIe Gen2(Reserve)

None

BGA SSD PCIe x4 GEN3

M.2 SSD Debug(Reserve)

None

15

1 1

USB 2.0 CLK

DESTINATIONUSB 2.0 PORT#

1

2

3

4

5

6

7

8

9

10

USB DCI Debug

None

BT(Reserve)

None

FPR

None

Type-C_L

Type-C_R

None

CLK

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

WLAN(Reserve)

M.2 SSD(Reserve)

SSD

None

Card Reader

None

FLEX CLOCKS DESTINATION

ESPI_CLK

EC eSPI

Thunderbolt

TBT

Displayport

DDI

PCI-E#16 / SATA#2

Card Reader PCIE GEN2

TBT PORT# DESTINATION

0

1

USB Type-C_L

None

2 USB Type-C_R

3

None

DDI PORT# DESTINATION

A

B

4 Lane eDP

None

CSI2

C/D

F

G/H

DESTINATIONCSI2 PORT#

None

UFE

None

Symbol Note :

: means de-pop

@

: means Digital Ground

: means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

Compal Electronics, Inc.

P003 - Notes List

LA-G172P

3 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

Power Rail

Audio Power Rail

D D

Type-C Port-L

Type-C Port-R

C C

VCCIN

IMVP_VR_ON_EN

1.8V_PRIM_PG

0.6V_VDDQ_EN_P

B B

A A

1.1V_MEM_EN

SSD_PWR3_EN_P

SSD_PWR2_EN_P

TDC 36A Peak Current 62A (MP2940A) Page:91,92,93

VCCIN_AUX TDC 10A Peak Current 26A (MP2941) Page:89,90

+0.6V_VDDQ (LPDDR4X only) TDC 1.25A Peak Current 1.79A (NB691) Page:87

+1.1V_MEM TDC 4A Peak Current 5.7A (RT6243B) Page:86

+SSD_PWR3 TDC 1.4A Peak Current 2A (NB693) Page:95

+SSD_PWR2 TDC 1.4A Peak Current 2A (NB691) Page:94

+VCC1.05_OUT_FET

+1.1V_MEM

U735 AOZ1336D

U734 AOZ1336D

Q15 SI3457BDV

PD1 Controller TPS65987DH

EC MEC5105

PD2 Controller TPS65987DH

SSD_PWR3_EN

SSD_PWR2_EN

EN_INVPWR

B+B+

UC13 AOZ1334DI-01

UC12 AOZ1334DI-01

UC27 AOZ1334DI-01

+SSD_PWR_3

+1.8V_1.2V_SSD

+INV_PWR_SRC

Centenario POWER BLOCK DIAGRAM

VCCST_EN

VCCSTG_EN

VCC_SFR_OC_EN

+VCCST_CPU

+VCCSTG_CPU

+VCC_SFR_OC

2S2P Battery 51W

Buck-boost Charger ISL9538B (NVDC) Page:83

B+

ALWON_5VALW

ALWON_5VALW B

B+

PCH_PRIM_EN

ALWON_3VALW

B+

+5VALW TDC 5A Peak Current 7.2A (NB502) Page:85

+5VALWB TDC 3.5A Peak Current 5A (NB502) Page:85

+1.8VPRIM TDC 2.56A Peak Current 3.65A (NB691) Page:88

+3.3VALW TDC: 5.1A Peak Current 7.22A (NB502) Page:84

U36 AOZ1336DI

UPD1 TPS65987DH

UC28 AOZ1336DI

U55 SY6288

U60 AOZ1336DI

UPD2 TPS65987DH

UC22 AOZ1334DI-01

UC25 AOZ1336DI

UC24 AOZ1336DI

UC23 AOZ1334DI-01

U7 SY6288

U31 AOZ1331DI

U34 AOZ1331DI

UC30 AOZ1336DI

U51 AOZ1336DI

U733 AOZ1336DI

UC31 SY6288

UT1 AOZ1336DI

UT2 AOZ1336DI

AUD_PWR_EN

RUN_ON_P

3.3V_CAM_EN

RUN_ON_P

CPU_C10_GATE#

AUD_PWR_EN

RUN_ON_P

SUS_ON_P

ENVDD

VCCDSW_EN_GPIO

WLAN_PW R_EN

TS_EN_R

RUN_ON_P

AUD_PWR_EN

SSD_PWR1_EN

SD_PWR_EN

3.3V_TBT_L_EN

3.3V_TBT_R_EN

+5VS_AUDIO

+5VALWB_L_TBT

+5VS

+CAM_PWR

+5VBS

+5VALWB_R_TBT

+VCC1P8A

+1.8VS_AUDIO

+1.8VS

+1.8V_MEM

+LCDVDD

+3V_PRIM

+3VALW_DSW

+3VS_WLAN

+3VS_TS

+3VS

+3VS_AUDIO

+3.3VDX_SSD

+3VS_CR

+3.3V_TBT_L

+3.3V_TBT_R

UKBC26 AOZ1336DI

UMID1 RT9078N

UMID2 RT9078N

UMID3 RT9078N

Transfer Board

TP_EN

+TRN_3VS_TP

Middle Board

+MID_CAM_PWR

+MID_UF_AVDD_2.8V

+MID_UF_DVDD_1.2V

+MID_UF_VDD_1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2

2017/08/24 2017/08/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P004 - Power MAP

LA-G172P

1

4 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

Power On Sequence

[AC in] for VBU_L/VBU_R

TBT_VBUS

+3V_LDO

PD Output

+CHG_VIN_20V

PD Output

CHR Output

B+

ACAV_INEC Input

D D

EC Output ALWON

+3VALW

VR Output

+5VALW (+5VALWB)

VR Output

ALW_PWRGD_3V_5V

VR Output

EC Input

POWER_SW_IN#

EC pay attention timing

VCCDSW_EN_GPIO

+3VALW_DSW/+3V_PRIM(U31)

EC Output

PCH_DPWROK

PCH Output

SIO_SLP_SUS#

+1.8V_PRIM(PU500)

VR Output

PCH Output

+VCC1.05_OUT_PCH

PCH Output

+VCC1.05_OUT_FET

+VCCST_CPU(UC13)

1.8V_PRIM_PG

C C

B B

VR Output

+VCCIN_AUX(PU900)

PCH Output

VCCIN_AUX_VR_PG

VR Output

PCH_RSMRST#

EC Output

ESPI_RESET#

PCH Output

EC Output AC_PRESENT

POWER_SW_IN# 16ms < T < 4s

PCH Output

SIO_SLP_S5#

SIO_SLP_S4#PCH Output

SIO_SLP_S3#PCH Output

PCH Output

CPU_C10_GATE#

SIO_SLP_S0#PCH Output

RUN_ON_ECEC Output

+1.1V_MEM(PU700)

VR Output

+0.6V_VDDQ(PU800)

VR Output

+1.8V_MEM(UC23)

+VCCSTG_CPU(UC12)

+VCC1P8A(UC22)

+VCC_SFR_OC(UC27)

+3VS(UC30)

+1.8VS(UC24)

+5VS(UC28)/+5VBS(U60)

+3.3VDX_SSD(U733)

+SSD_PWR2(PU1500)

+SSD_PWR3(PU1400)

RUNPWROK(ALL_SYS_PWRGD)EC Input

EC Output

IMVP_VR_ON_P(VCCST_PWRGD)

+VCCIN(PU1100)VR Output

PCH_PWROK_PVR Output

CPUPWRGD

SYS_PWROKEC Output

PCH_PLTRST#_ECPCH Output

Ta

Tb

Tc

Td

Te

Tf +5VALW (+5VALWB) Tf

Tg Tg

Th

200ms < Th

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

[Battery only, AC absent]

B+

CHR Output

PWR_SW_IN#

EC Output

ALWON Td

VR Output

+3VALW

VR Output

ALW_PWRGD_3V_5V

VR Output

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

T31

T32

T33

T34

TBT_VBUS

Ta

+3V_LDO

Tb

+CHG_VIN_20V

Tc

200ms < Th

Te

T35

T36

T37

B+

Td Te

ALWON

Tf

ALWON

Tg

+3VALW

Th

ITEM Measure Point

VCCDSW_EN_GPIO

T1

+3VALW_DSW/+3V_PRIM

T2

PCH_DPWROK

T3

SIO_SLP_SUS#

T4

+1.8V_PRIM

T5

+1.8V_PRIM

T6

+VCC1.05_OUT_FET

T7

+1.8V_PRIM

T8

1.8V_PRIM_PG

T9

+VCCIN_AUX

T10

VCCIN_AUX_VR_PG

T11

PCH_RSMRST#

T12

ESPI_RESET#

T13

SIO_SLP_S5#

T14

SIO_SLP_S4#

T15

SIO_SLP_S4#

T16

SIO_SLP_S4#

T17

SIO_SLP_S4#

T18

SIO_SLP_S4#

T19

SIO_SLP_S4#

T20

SIO_SLP_S4#

T21

SIO_SLP_S4#

T22

SIO_SLP_S4#

T23

SIO_SLP_S4#

T24

RUN_ON_EC

T25

RUN_ON_EC

T26

RUN_ON_EC

T27

RUN_ON_EC

T28

RUN_ON_EC

T29

RUN_ON_EC

T30

+3VS

T31

RUNPWROK

T32

IMVP_VR_ON_P

T33

+VCCIN

T34

PCH_PWROK_P

T35

CPUPWRGD

T36

SYS_PWROK

T37

[AC in]

+3V_LDO

To

+CHG_VIN_20V

To

B+

To

ACAV_IN

To

ALWONACAV_IN

To

+3VALW

To

+5VALW (+5VALWB) ALWON

To

ALW_PWRGD_3V_5V

To

+3VALW_DSW/+3V_PRIM

To

PCH_DPWROK

To

SIO_SLP_SUS#

To

+1.8V_PRIM

To

+VCC1.05_OUT_PCH

To

+VCC1.05_OUT_FET

To

+VCCST_CPU

To

1.8V_PRIM_PG

To

+VCCIN_AUX

To

VCCIN_AUX_VR_PG

To

PCH_RSMRST#

To

ESPI_RESET#

To

AC_PRESENT

To

SIO_SLP_S4#

To

SIO_SLP_S3#

To

CPU_C10_GATE#

To

SIO_SLP_S0#

To

RUN_ON_EC

To

+1.1V_MEM

To

+0.6V_VDDQ

To

+1.8V_MEM

To

+1.8V_MEM

To

+VCC1P8A

To

+VCC_SFR_OC

To

+3VS

To

+1.8VS

To

+5VS/+5VBS

To

+3.3VDX_SSD

To

+SSD_PWR2

To

+SSD_PWR3

To

RUNPWROK

To

IMVP_VR_ON_P

To

+VCCIN

To

PCH_PWROK_P

To

CPUPWRGD

To

SYS_PWROK

To

PCH_PLTRST#_EC

To

TimeMeasure PointITEM

Time

[Battery only, AC absent]

Measure PointITEM Time

B+

Tc

POWER_SW_IN# Low pluse width

Th

POWER_SW_IN#

Td

ALWON +3VALW

Te Tf

+3VALW ALW_PWRGD_3V_5V

Tg

POWER_SW_IN#

To

ALWON

To To

+5VALW (+5VALWB)

To To

Power Down Sequence

EC pay attention timing

PCH_PLTRST#

CPUPWRGD

PCH_CLK_OUTPUTS

SIO_SLP_S3#

CPU_C10_GATE#

SYS_PWROK

PCH_PWROK_P

IMVP_VR_ON_P(VCCST_PWRGD)

RUNPWROK(ALL_SYS_PWRGD)

+VCCIN

3VS/+1.8VS/+5VS/+5VBS

+VCCSTG_CPU

SIO_SLP_S4#

+1.1V_MEM

+0.6V_VDDQ

+1.8V_MEM

+VCC_SFR_OC

SIO_SLP_S5#

+VCC1P05_OUTPUT_PLL

PCH_RSMRST#

PCH_DPWROK

+3VALW_DSW/+3V_PRIM

SIO_SLP_SUS#

ESPI_RESET#

SIO_SLP_S0#

+1.8V_PRIM

+VCC1.05_OUT_PCH

+VCCIN_AUX

+VCCST_CPU

SUSCLK

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P005 - Power Sequence

Size Document Number Rev

LA-G172P

Date: Sheet of

1

5 101Friday, May 24, 2019

1.0 (A00)

5

D D

eDP

PVT_10

DVT1_76

+3V_PRIM

RH74210K_0201_5%

12

C C

RH60310K_0201_5%

12

RH675100K_0201_5%

12

RH717100K_0201_5% @

12

RH718100K_0201_5% @

12

DVT1_30

USB_OC1#

USB_OC2#

EDP_HPD

CPU_TCP0_HPD

USB_OC1#

DVT1_30

4

UC1A

EDP_TXN0(38) EDP_TXP0(38) EDP_TXN1(38) EDP_TXP1(38) EDP_TXN2(38) EDP_TXP2(38) EDP_TXN3(38) EDP_TXP3(38)

EDP_AUXN(38) EDP_AUXP(38)

TBT_0_LSX_TX(46) TBT_0_LSX_RX(46)

TBT_2_LSX_TX(48) TBT_2_LSX_RX(48)

EDP_HPD(38,58)

DVT1_30

TS_INT#(38)

ENVDD_PCH(38) PANEL_BKLEN(10,38) EDP_BIA_PWM(38)

TP99

TP69

TBT_0_LSX_RX

TBT_1_LSX_RX

TBT_2_LSX_RX

TBT_3_LSX_RX

EDP_HPD

CPU_TCP0_HPD

USB_OC1# USB_OC2#

PAD~D

1

PAD~D

1

RC3150_0201_1%

12

RSVD_1

TP@

DISP_UTILS KB_DET#

TP@

DP_RCOMP

Y5

DDIA_TXN_0

Y3

DDIA_TXP_0

Y1

DDIA_TXN_1

Y2

DDIA_TXP_1

V2

DDIA_TXN_2

V1

DDIA_TXP_2

V3

DDIA_TXN_3

V5

DDIA_TXP_3

W4

DDIA_AUX_N

W3

DDIA_AUX_P

AE3

DDIB_TXN_0

AE5

DDIB_TXP_0

AE2

DDIB_TXN_1

AE1

DDIB_TXP_1

AC5

DDIB_TXN_2

AC3

DDIB_TXP_2

AC1

DDIB_TXN_3

AC2

DDIB_TXP_3

AD3

DDIB_AUX_N

AD4

DDIB_AUX_P

DP15

GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN

DJ17

GPP_E23/DDPA_CTRLDATA/BK4/SBK4

DL40

GPP_H16/DDPB_CTRLCLK

DP42

GPP_H17/DDPB_CTRLDATA

DL17

GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD

DK17

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD

DN17

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD

DP17

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD

DK34

GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD

DL34

GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD

DN33

GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD

DL33

GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD

DW11

GPP_E14/DPPE_HPDA/DISP_MISCA

CV42

GPP_A18/DDSP_HPDB/DISP_MISCB

CV39

GPP_A19/DDSP_HPD1/DISP_MISC1

CY43

GPP_A20/DDSP_HPD2/DISP_MISC2

CR41

GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3

CT41

GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4

DV14

GPP_E17

DN21

EDP_VDDEN

DL19

EDP_BKLTEN

DU19

EDP_BKLTCTL

J3

RSVD_1

D2

DISP_UTILS

R2

DISP_RCOMP

ICL-U_BGA1526

@

3

GPP_A21 GPP_A22

BB5 BB6 AV6 AV5 BH2 BH1 BF1 BF2

AY5 AY6

AR5 AR6 AL5 AL3 BD2 BD1 BB1 BB2

AN3 AN5

BF6 BF5 BJ5 BJ6 BL1 BL2 BM2 BM1

BG6 BG5

BP6 BP5 BV5 BV6 BR1 BR2 BT2 BT1

BT6 BT5

AY1 AY2

CT38 CV43 CV41

TCRCOMP_DN TCRCOMP_DP

RTC_DET#

RH734 0_0201_5%

DVT1_62

TCP0_TX_N0 TCP0_TX_P0 TCP0_TX_N1

TCP0_TX_P1 TCP0_TXRX_N0 TCP0_TXRX_P0 TCP0_TXRX_N1 TCP0_TXRX_P1

TCP0_AUX_N

DDI

TBT / USB / DP

1 0f 19

TCP0_AUX_P

TCP1_TX_N0

TCP1_TX_P0

TCP1_TX_N1

TCP1_TX_P1 TCP1_TXRX_N0 TCP1_TXRX_P0 TCP1_TXRX_N1 TCP1_TXRX_P1

TCP1_AUX_N TCP1_AUX_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1 TCP2_TXRX_N0 TCP2_TXRX_P0 TCP2_TXRX_N1 TCP2_TXRX_P1

TCP2_AUX_N TCP2_AUX_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1 TCP3_TXRX_N0 TCP3_TXRX_P0 TCP3_TXRX_N1 TCP3_TXRX_P1

TCP3_AUX_N TCP3_AUX_P

TC_RCOMP_N TC_RCOMP_P

GPP_A17/DISP_MISCC

2

TBT_0_TTX_DRX_N0 (46) TBT_0_TTX_DRX_P0 (46) TBT_0_TTX_DRX_N1 (46) TBT_0_TTX_DRX_P1 (46) TBT_0_TRX_DTX_N0 (46) TBT_0_TRX_DTX_P0 (46) TBT_0_TRX_DTX_N1 (46) TBT_0_TRX_DTX_P1 (46)

TBT_0_DP_AUXN (46) TBT_0_DP_AUXP (46)

TBT_2_TTX_DRX_N0 (48) TBT_2_TTX_DRX_P0 (48) TBT_2_TTX_DRX_N1 (48) TBT_2_TTX_DRX_P1 (48) TBT_2_TRX_DTX_N0 (48) TBT_2_TRX_DTX_P0 (48) TBT_2_TRX_DTX_N1 (48) TBT_2_TRX_DTX_P1 (48)

TBT_2_DP_AUXN (48) TBT_2_DP_AUXP (48)

RC1 150_0201_1%

1 2

@

1 2

RTC_DET#_R (63)

3.3V_CAM_EN (71) KB_DET# (63)

TBT_L

TBT_R

1

+3V_PRIM

RH672 10K_0201_5%

1 2

+3V_PRIM +3V_PRIM +3V_PRIM +3V_PRIM

B B

12

R6172

@

4.7K_0201_5%

TBT_0_LSX_RX

RC691 20K_0201_5%

1 2

TBT LSX #0 PINS VCCIO CONFIGURATION

HIGH

LOW

3.3V

1.8V

12

R6173

@

4.7K_0201_5%

TBT_1_LSX_RX TBT_2_LSX_RX TBT_3_LSX_RX

RC692

@

20K_0201_5%

1 2

TBT LSX #1 PINS VCCIO CONFIGURATION

HIGH

LOW

3.3V

1.8V

12

R6174

@

4.7K_0201_5%

RC693 20K_0201_5%

1 2

TBT LSX #2 PINS VCCIO CONFIGURATION

HIGH

LOW

3.3V

1.8V

TBT LSX #3 PINS VCCIO CONFIGURATION

HIGH

LOW

12

RC694 20K_0201_5%

1 2

R6175

@

4.7K_0201_5%

@

3.3V

1.8V

PLACE CLOSE TO THE SIGNAL TO AVOID STUB

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

Compal Electronics, Inc.

P006 - ICL-U(1/13)TCSS,EDP

LA-G172P

1

6 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

Memory connection follow J72913-201 Rev 01_20181217

D D

UC1B

LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)

DDR_A_D0_0(23) DDR_A_D0_1(23) DDR_A_D0_2(23) DDR_A_D0_3(23) DDR_A_D0_4(23) DDR_A_D0_5(23) DDR_A_D0_6(23) DDR_A_D0_7(23) DDR_A_D1_0(23) DDR_A_D1_1(23) DDR_A_D1_2(23) DDR_A_D1_3(23) DDR_A_D1_4(23) DDR_A_D1_5(23) DDR_A_D1_6(23) DDR_A_D1_7(23) DDR_A_D2_0(23) DDR_A_D2_1(23) DDR_A_D2_2(23) DDR_A_D2_3(23)

C C

B B

A A

DDR_A_D2_4(23) DDR_A_D2_5(23) DDR_A_D2_6(23) DDR_A_D2_7(23) DDR_A_D3_0(23) DDR_A_D3_1(23) DDR_A_D3_2(23) DDR_A_D3_3(23) DDR_A_D3_4(23) DDR_A_D3_5(23) DDR_A_D3_6(23) DDR_A_D3_7(23) DDR_B_D0_0(23) DDR_B_D0_1(23) DDR_B_D0_2(23) DDR_B_D0_3(23) DDR_B_D0_4(23) DDR_B_D0_5(23) DDR_B_D0_6(23) DDR_B_D0_7(23) DDR_B_D1_0(23) DDR_B_D1_1(23) DDR_B_D1_2(23) DDR_B_D1_3(23) DDR_B_D1_4(23) DDR_B_D1_5(23) DDR_B_D1_6(23) DDR_B_D1_7(23) DDR_B_D2_0(23) DDR_B_D2_1(23) DDR_B_D2_2(23) DDR_B_D2_3(23) DDR_B_D2_4(23) DDR_B_D2_5(23) DDR_B_D2_6(23) DDR_B_D2_7(23) DDR_B_D3_0(23) DDR_B_D3_1(23) DDR_B_D3_2(23) DDR_B_D3_3(23) DDR_B_D3_4(23) DDR_B_D3_5(23) DDR_B_D3_6(23) DDR_B_D3_7(23)

DDR_COMP_0

RC12100_0201_1%

12

RC13100_0201_1% RC14100_0201_1%

DDR_COMP_1 DDR_COMP_2

12 12

CA48

DDRA_DQ0_0/DDR0_DQ0_0

CA47

DDRA_DQ0_1/DDR0_DQ0_1

CA49

DDRA_DQ0_2/DDR0_DQ0_2

BV49

DDRA_DQ0_3/DDR0_DQ0_3

CA45

DDRA_DQ0_4/DDR0_DQ0_4

BV47

DDRA_DQ0_5/DDR0_DQ0_5

BV45

DDRA_DQ0_6/DDR0_DQ0_6

BV48

DDRA_DQ0_7/DDR0_DQ0_7

CC42

DDRA_DQ1_0/DDR0_DQ1_0

CC39

DDRA_DQ1_1/DDR0_DQ1_1

CC43

DDRA_DQ1_2/DDR0_DQ1_2

CE38

DDRA_DQ1_3/DDR0_DQ1_3

CC38

DDRA_DQ1_4/DDR0_DQ1_4

CE39

DDRA_DQ1_5/DDR0_DQ1_5

CE42

DDRA_DQ1_6/DDR0_DQ1_6

CE43

DDRA_DQ1_7/DDR0_DQ1_7

BT48

DDRA_DQ2_0/DDR0_DQ2_0

BT47

DDRA_DQ2_1/DDR0_DQ2_1

BT49

DDRA_DQ2_2/DDR0_DQ2_2

BN49

DDRA_DQ2_3/DDR0_DQ2_3

BT45

DDRA_DQ2_4/DDR0_DQ2_4

BN47

DDRA_DQ2_5/DDR0_DQ2_5

BN45

DDRA_DQ2_6/DDR0_DQ2_6

BN48

DDRA_DQ2_7/DDR0_DQ2_7

BV42

DDRA_DQ3_0/DDR0_DQ3_0

BV39

DDRA_DQ3_1/DDR0_DQ3_1

BV43

DDRA_DQ3_2/DDR0_DQ3_2

BW38

DDRA_DQ3_3/DDR0_DQ3_3

BV38

DDRA_DQ3_4/DDR0_DQ3_4

BW39

DDRA_DQ3_5/DDR0_DQ3_5

BW42

DDRA_DQ3_6/DDR0_DQ3_6

BW43

DDRA_DQ3_7/DDR0_DQ3_7

AY48

DDRB_DQ0_0/DDR0_DQ4_0

AY47

DDRB_DQ0_1/DDR0_DQ4_1

AY49

DDRB_DQ0_2/DDR0_DQ4_2

AU45

DDRB_DQ0_3/DDR0_DQ4_3

AY45

DDRB_DQ0_4/DDR0_DQ4_4

AU47

DDRB_DQ0_5/DDR0_DQ4_5

AU48

DDRB_DQ0_6/DDR0_DQ4_6

AU49

DDRB_DQ0_7/DDR0_DQ4_7

AY42

DDRB_DQ1_0/DDR0_DQ5_0

AY38

DDRB_DQ1_1/DDR0_DQ5_1

AY43

DDRB_DQ1_2/DDR0_DQ5_2

BB39

DDRB_DQ1_3/DDR0_DQ5_3

AY39

DDRB_DQ1_4/DDR0_DQ5_4

BB38

DDRB_DQ1_5/DDR0_DQ5_5

BB42

DDRB_DQ1_6/DDR0_DQ5_6

BB43

DDRB_DQ1_7/DDR0_DQ5_7

AR48

DDRB_DQ2_0/DDR0_DQ6_0

AR47

DDRB_DQ2_1/DDR0_DQ6_1

AR49

DDRB_DQ2_2/DDR0_DQ6_2

AM45

DDRB_DQ2_3/DDR0_DQ6_3

AR45

DDRB_DQ2_4/DDR0_DQ6_4

AM47

DDRB_DQ2_5/DDR0_DQ6_5

AM48

DDRB_DQ2_6/DDR0_DQ6_6

AM49

DDRB_DQ2_7/DDR0_DQ6_7

AT42

DDRB_DQ3_0/DDR0_DQ7_0

AT39

DDRB_DQ3_1/DDR0_DQ7_1

AR43

DDRB_DQ3_2/DDR0_DQ7_2

AT38

DDRB_DQ3_3/DDR0_DQ7_3

AR38

DDRB_DQ3_4/DDR0_DQ7_4

AR39

DDRB_DQ3_5/DDR0_DQ7_5

AR42

DDRB_DQ3_6/DDR0_DQ7_6

AT43

DDRB_DQ3_7/DDR0_DQ7_7

D47

DDR_RCOMP_0

E46

DDR_RCOMP_1

C47

DDR_RCOMP_2

ICL-U_BGA1526

@

2 of 19

DDRA_CLK_N/DDR0_CLK_N_0 DDRA_CLK_P/DDR0_CLK_P_0 DDRB_CLK_N/DDR0_CLK_N_1 DDRB_CLK_P/DDR0_CLK_P_1

DDRA_CKE0/DDR0_CKE0

DDRA_CKE1/NC DDRB_CKE0/NC

DDRB_CKE1/DDR0_CKE1

DDRA_CS_0/DDR0_CS#0

DDRA_CS_1/NC DDRB_CS_0/NC

DDRB_CS_1/DDR0_CS#1

DDRB_CA4/DDR0_BA0

NC/DDR0_BA1

DDRA_CA5/DDR0_BG0

NC/DDR0_BG1

NC/DDR0_MA0 NC/DDR0_MA1

DDRB_CA5/DDR0_MA2

NC/DDR0_MA3

NC/DDR0_MA4 DDRA_CA0/DDR0_MA5 DDRA_CA2/DDR0_MA6 DDRA_CA4/DDR0_MA7 DDRA_CA3/DDR0_MA8 DDRA_CA1/DDR0_MA9

NC/DDR0_MA10 NC/DDR0_MA11 NC/DDR0_MA12

DDRB_CA0/DDR0_MA13

DDRB_CA2/DDR0_MA14WE# DDRB_CA1/DDR0_MA15CAS# DDRB_CA3/DDR0_MA16RAS#

NC/DDR0_ODT_0 NC/DDR0_ODT_1

DDRA_DQSN_0/DDR0_DQSN_0

DDRA_DQSP_0/DDR0_DQSP_0

DDRA_DQSN_1/DDR0_DQSN_1

DDRA_DQSP_1/DDR0_DQSP_1

DDRA_DQSN_2/DDR0_DQSN_2

DDRA_DQSP_2/DDR0_DQSP_2

DDRA_DQSN_3/DDR0_DQSN_3

DDRA_DQSP_3/DDR0_DQSP_3

DDRB_DQSN_0/DDR0_DQSN_4

DDRB_DQSP_0/DDR0_DQSP_4

DDRB_DQSN_1/DDR0_DQSN_5

DDRB_DQSP_1/DDR0_DQSP_5

DDRB_DQSN_2/DDR0_DQSN_6

DDRB_DQSP_2/DDR0_DQSP_6

DDRB_DQSN_3/DDR0_DQSN_7

DDRB_DQSP_3/DDR0_DQSP_7

NC/DDR0_PAR

NC/DDR0_ACT#

NC/DDR0_ALERT#

RSVD_73 DDR0_VREF_CA DDR1_VREF_CA

DDR_VTT_CTL

DRAM_RESET#

BL48 BL47 BF42 BF43

BG49 BJ47 BF38 BF41

BM38 BM42 BP42 BG42

BM43 BG39

BB49 BD47

BB48 BL49 BG38 BL45 BJ46 BG48 BE45 BG45 BG47 BE47 BJ38 BB47 BE48 BM39 BG43 BJ42 BM41

BJ39 BB45

BY47 BY46 CC41 CE41 BR47 BR46 BV41 BW41 AV46 AV47 AY41 BB41 AN46 AN47 AR41 AT41

BF39 BE49 BD46

M38 C44 B45 M39 DK47

DDR_A_CLK# (23) DDR_A_CLK (23) DDR_B_CLK# (23) DDR_B_CLK (23)

DDR_A_CKE0 (23) DDR_A_CKE1 (23) DDR_B_CKE0 (23) DDR_B_CKE1 (23)

DDR_A_CS#0 (23) DDR_A_CS#1 (23) DDR_B_CS#0 (23) DDR_B_CS#1 (23)

DDR_B_CA4 (23)

DDR_A_CA5 (23)

DDR_B_CA5 (23)

DDR_A_CA0 (23) DDR_A_CA2 (23) DDR_A_CA4 (23) DDR_A_CA3 (23) DDR_A_CA1 (23)

DDR_B_CA0 (23) DDR_B_CA2 (23) DDR_B_CA1 (23) DDR_B_CA3 (23)

DDR_A_DQS#0 (23) DDR_A_DQS0 (23) DDR_A_DQS#1 (23) DDR_A_DQS1 (23) DDR_A_DQS#2 (23) DDR_A_DQS2 (23) DDR_A_DQS#3 (23) DDR_A_DQS3 (23) DDR_B_DQS#0 (23) DDR_B_DQS0 (23) DDR_B_DQS#1 (23) DDR_B_DQS1 (23) DDR_B_DQS#2 (23) DDR_B_DQS2 (23) DDR_B_DQS#3 (23) DDR_B_DQS3 (23)

+1.1V_MEM

BF39,BE49 SDS CRB P.8 NC

M_0_ALERT_N

M38,C44,B45 SDS CRB P.8 NC

DDR_VTT_CTRL DDR_DRAMRST#

RH11 0_0201_5%@

1 2

1

TP37

TP@

PAD~D

RH12 470_0201_1%

1 2

RH42 0_0201_5%@

M39 (DDR_VTT_CTL) is DDR4 System Memory Power Gate Control Buffer use , LPDDR4/x don't use. Processor EDS Rev0p7 P.118,119 #572795 SDS CRB NC

C44(DDR0_VREF_CA),B45(DDR1_VREF_CA) for DDR4 used only LPDDR4/4x has all Vref Internal inside the DRAMS Rev.0.91 PDG P.112 #572907

1 2

1

CC740

0.1U_0201_10V6K

2

DVT1_34

DDR_DRAMRST#_R (23,24)

@

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P007 - ICL-U(2/13)LPDDR4/x

LA-G172P

1

7 101Friday, May 24, 2019

1.0 (A00)

5

D D

4

3

2

1

Memory connection follow J72913-201 Rev 01_20181217

UC1C

DDR_C_D0_0(24) DDR_C_D0_1(24) DDR_C_D0_2(24) DDR_C_D0_3(24) DDR_C_D0_4(24) DDR_C_D0_5(24) DDR_C_D0_6(24) DDR_C_D0_7(24) DDR_C_D1_0(24) DDR_C_D1_1(24) DDR_C_D1_2(24) DDR_C_D1_3(24) DDR_C_D1_4(24) DDR_C_D1_5(24) DDR_C_D1_6(24) DDR_C_D1_7(24)

C C

B B

DDR_C_D2_0(24) DDR_C_D2_1(24) DDR_C_D2_2(24) DDR_C_D2_3(24) DDR_C_D2_4(24) DDR_C_D2_5(24) DDR_C_D2_6(24) DDR_C_D2_7(24) DDR_C_D3_0(24) DDR_C_D3_1(24) DDR_C_D3_2(24) DDR_C_D3_3(24) DDR_C_D3_4(24) DDR_C_D3_5(24) DDR_C_D3_6(24) DDR_C_D3_7(24) DDR_D_D0_0(24) DDR_D_D0_1(24) DDR_D_D0_2(24) DDR_D_D0_3(24) DDR_D_D0_4(24) DDR_D_D0_5(24) DDR_D_D0_6(24) DDR_D_D0_7(24) DDR_D_D1_0(24) DDR_D_D1_1(24) DDR_D_D1_2(24) DDR_D_D1_3(24) DDR_D_D1_4(24) DDR_D_D1_5(24) DDR_D_D1_6(24) DDR_D_D1_7(24) DDR_D_D2_0(24) DDR_D_D2_1(24) DDR_D_D2_2(24) DDR_D_D2_3(24) DDR_D_D2_4(24) DDR_D_D2_5(24) DDR_D_D2_6(24) DDR_D_D2_7(24) DDR_D_D3_0(24) DDR_D_D3_1(24) DDR_D_D3_2(24) DDR_D_D3_3(24) DDR_D_D3_4(24) DDR_D_D3_5(24) DDR_D_D3_6(24) DDR_D_D3_7(24)

AK48 AK45 AK49 AG47 AK47 AG45 AG48 AG49

AJ38 AL39 AJ39 AL43 AL38 AJ42 AL42

AJ43 AB49 AB48 AE49 AE47 AE48 AB47 AB45 AE45 AD38 AD39 AE39 AE43 AE38 AD43 AD42 AE42

J48 J45 J49

G47

J47 G45 G48 E48

J38 G39 G38 G42

J39

J42 G43

J43 B43 D43 A43 C40 C43 D40 B40 A40 B35 D35 A35 D38 C35 C38 B38 A38

LP4(NIL) / DDR4(NIL)

DDRC_DQ0_0/DDR1_DQ0_0 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_DQ0_2/DDR1_DQ0_2 DDRC_DQ0_3/DDR1_DQ0_3 DDRC_DQ0_4/DDR1_DQ0_4 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_DQ0_6/DDR1_DQ0_6 DDRC_DQ0_7/DDR1_DQ0_7 DDRC_DQ1_0/DDR1_DQ1_0 DDRC_DQ1_1/DDR1_DQ1_1 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_DQ1_4/DDR1_DQ1_4 DDRC_DQ1_5/DDR1_DQ1_5 DDRC_DQ1_6/DDR1_DQ1_6 DDRC_DQ1_7/DDR1_DQ1_7 DDRC_DQ2_0/DDR1_DQ2_0 DDRC_DQ2_1/DDR1_DQ2_1 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_DQ2_3/DDR1_DQ2_3 DDRC_DQ2_4/DDR1_DQ2_4 DDRC_DQ2_5/DDR1_DQ2_5 DDRC_DQ2_6/DDR1_DQ2_6 DDRC_DQ2_7/DDR1_DQ2_7 DDRC_DQ3_0/DDR1_DQ3_0 DDRC_DQ3_1/DDR1_DQ3_1 DDRC_DQ3_2/DDR1_DQ3_2 DDRC_DQ3_3/DDR1_DQ3_3 DDRC_DQ3_4/DDR1_DQ3_4 DDRC_DQ3_5/DDR1_DQ3_5 DDRC_DQ3_6/DDR1_DQ3_6 DDRC_DQ3_7/DDR1_DQ3_7 DDRD_DQ0_0/DDR1_DQ4_0 DDRD_DQ0_1/DDR1_DQ4_1 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_DQ0_6/DDR1_DQ4_6 DDRD_DQ0_7/DDR1_DQ4_7 DDRD_DQ1_0/DDR1_DQ5_0 DDRD_DQ1_1/DDR1_DQ5_1 DDRD_DQ1_2/DDR1_DQ5_2 DDRD_DQ1_3/DDR1_DQ5_3 DDRD_DQ1_4/DDR1_DQ5_4 DDRD_DQ1_5/DDR1_DQ5_5 DDRD_DQ1_6/DDR1_DQ5_6 DDRD_DQ1_7/DDR1_DQ5_7 DDRD_DQ2_0/DDR1_DQ6_0 DDRD_DQ2_1/DDR1_DQ6_1 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQ2_4/DDR1_DQ6_4 DDRD_DQ2_5/DDR1_DQ6_5 DDRD_DQ2_6/DDR1_DQ6_6 DDRD_DQ2_7/DDR1_DQ6_7 DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DQ3_1/DDR1_DQ7_1 DDRD_DQ3_2/DDR1_DQ7_2 DDRD_DQ3_3/DDR1_DQ7_3 DDRD_DQ3_4/DDR1_DQ7_4 DDRD_DQ3_5/DDR1_DQ7_5 DDRD_DQ3_6/DDR1_DQ7_6

DDRD_DQ3_7/DDR1_DQ7_7

ICL-U_BGA1526

@

3 of 19

LP4(NIL) / DDR4(NIL)

DDRC_CLK_N/DDR1_CLK_N_0 DDRC_CLK_P/DDR1_CLK_P_0 DDRD_CLK_N/DDR1_CLK_N_1 DDRD_CLK_P/DDR1_CLK_P_1

DDRC_CKE0/DDR1_CKE0

DDRC_CKE1/NC DDRD_CKE0/NC

DDRD_CKE1/DDR1_CKE1

DDRC_CS_0/DDR1_CS#0

DDRC_CS_1/NC DDRD_CS_0/NC

DDRD_CS_1/DDR1_CS#1

DDRD_CA4/DDR1_BA0

NC/DDR1_BA1

DDRC_CA5/DDR1_BG0

NC/DDR1_BG1

NC/DDR1_MA0 NC/DDR1_MA1

DDRD_CA5/DDR1_MA2

NC/DDR1_MA3

NC/DDR1_MA4 DDRC_CA0/DDR1_MA5 DDRC_CA2/DDR1_MA6 DDRC_CA4/DDR1_MA7 DDRC_CA3/DDR1_MA8 DDRC_CA1/DDR1_MA9

NC/DDR1_MA10 NC/DDR1_MA11

NC/DDR1_MA12

DDRD_CA0/DDR1_MA13

DDRD_CA2/DDR1_MA14WE# DDRD_CA1/DDR1_MA15CAS# DDRD_CA3/DDR1_MA16RAS#

NC/DDR1_ODT_0 NC/DDR1_ODT_1

DDRC_DQSN_0/DDR1_DQSN_0

DDRC_DQSP_0/DDR1_DQSP_0

DDRC_DQSN_1/DDR1_DQSN_1

DDRC_DQSP_1/DDR1_DQSP_1

DDRC_DQSN_2/DDR1_DQSN_2

DDRC_DQSP_2/DDR1_DQSP_2

DDRC_DQSN_3/DDR1_DQSN_3

DDRC_DQSP_3/DDR1_DQSP_3

DDRD_DQSN_0/DDR1_DQSN_4

DDRD_DQSP_0/DDR1_DQSP_4

DDRD_DQSN_1/DDR1_DQSN_5

DDRD_DQSP_1/DDR1_DQSP_5

DDRD_DQSN_2/DDR1_DQSN_6

DDRD_DQSP_2/DDR1_DQSP_6

DDRD_DQSN_3/DDR1_DQSN_7

DDRD_DQSP_3/DDR1_DQSP_7

NC/DDR1_PAR

NC/DDR1_ACT#

NC/DDR1_ALERT#

Y48 Y47 M43 M42

U45 V46 M41 P43

V42 V39 Y39 T39

T38 T42

R45 N47

P42 Y49 U48 Y45 U47 R49 U49 M47 M45 R47 P39 N46 R48 Y41 V41 Y42 V47

V43 V38

AH46 AH47 AJ41 AL41 AC47 AC46 AE41 AD41 H47 H46 G41 J41 C42 D42 D36 C36

P38 M48 M49

P38,M48 SSD CRB NC

M_1_ALERT_N

RH13 0_0201_5%@

DDR_C_CLK# (24) DDR_C_CLK (24) DDR_D_CLK# (24) DDR_D_CLK (24)

DDR_C_CKE0 (24) DDR_C_CKE1 (24) DDR_D_CKE0 (24) DDR_D_CKE1 (24)

DDR_C_CS#0 (24) DDR_C_CS#1 (24) DDR_D_CS#0 (24) DDR_D_CS#1 (24)

DDR_D_CA4 (24)

DDR_C_CA5 (24)

DDR_D_CA5 (24)

DDR_C_CA0 (24) DDR_C_CA2 (24) DDR_C_CA4 (24) DDR_C_CA3 (24) DDR_C_CA1 (24)

DDR_D_CA0 (24) DDR_D_CA2 (24) DDR_D_CA1 (24) DDR_D_CA3 (24)

DDR_C_DQS#0 (24) DDR_C_DQS0 (24) DDR_C_DQS#1 (24) DDR_C_DQS1 (24) DDR_C_DQS#2 (24) DDR_C_DQS2 (24) DDR_C_DQS#3 (24) DDR_C_DQS3 (24) DDR_D_DQS#0 (24) DDR_D_DQS0 (24) DDR_D_DQS#1 (24) DDR_D_DQS1 (24) DDR_D_DQS#2 (24) DDR_D_DQS2 (24) DDR_D_DQS#3 (24) DDR_D_DQS3 (24)

12

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P008 - ICL-U(3/13)LPDDR4/x

LA-G172P

1

8 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

BOOT HALT

SPI0_MOSI(NO INTERNAL PU/PD)

0 = Enable

1 = Disable

RH643 100K_0201_5%

PCH_SPI_SI

D D

1 2

RH641 4.7K_0201_5%@

1 2

CONSENT STRAP

SPI0_IO2(NO INTERNAL PU/PD)

0 = Enable

1 = Disable

RH141 100K_0201_5%

1 2

RH142 4.7K_0201_5%@

1 2

PCH_SPI_CLK_R(66) PCH_SPI_SI_R(66) PCH_SPI_SO_R(66)

PCH_SPI_CLK_R PCH_SPI_SI_R PCH_SPI_SO_R PCH_SPI_IO2_R PCH_SPI_IO3_R PCH_SPI_CS0#_R PCH_SPI_CS1#_R

+V3.3A_1 .8A_PCH_SPI +V3.3A_1 .8A_PCH_SPI+V3.3A_1 .8A_PCH_SPI

RH719 4.99_0201_1%

1 2

RH720 4.99_0201_1%

1 2

RH721 4.99_0201_1%

1 2

RH722 4.99_0201_1%

1 2

RH723 4.99_0201_1%

1 2

RH736 0_0201_5%@

1 2

RH735 0_0201_5%@

1 2

EVT2_28

RH6401K_0201_5%

RH6341K_0201_5%

1 2 1 2 1 2 1 2 1 2

PCH_SPI_CLK

PCH_SPI_SI

PCH_SPI_IO2

DVT1_36

PCH_SPI_SI_R PCH_SPI_CLK_R PCH_SPI_SO_R PCH_SPI_IO2_R PCH_SPI_IO3_R

RH687 100K_0201_5%

1 2

MIPI60_SPI0_MOSI(79)

MIPI60_SPI0_IO2(79)

C C

SPI_SI_VROM0 SPI_CLK_VROM0 SPI_SO_VROM0 SPI_IO2_VROM0 SPI_IO3_VROM0

1 2

MIPI60@

1 2

MIPI60@

Closed to ROM

RH23 49.9_0201_1% RH24 49.9_0201_1% RH25 49.9_0201_1% RH26 49.9_0201_1% RH27 49.9_0201_1%

A0 PERSONALITY STRAP

SPI0_IO3

0 = Enable

1 = Disable

RH635 100K_0201_5%

1 2

RH636 100K_0201_5%@

1 2

PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_CS2#(66)

PCH_SPI_CS2#

Strap Pin

Strap Pin Strap Pin

NO support C-Link

Serial Peripheral Interface (SPI) Topology Guidelines

UC1E

DB42

SPI0_CLK

DD43

SPI0_MOSI

DF43

SPI0_MISO

DF42

SPI0_IO2

DD41

SPI0_IO3

DB43

SPI0_CS0#

DF41

SPI0_CS1#

DB41

SPI0_CS2#

DV16

GPP_E11/SPI1_CLK/BK1/SBK1

DT16

GPP_E13/SPI1_MOSI/BK3/SBK3

DU18

GPP_E12/SPI1_MISO/BK2/SBK2

DT18

GPP_E1/SPI1_IO2

DW18

GPP_E2/SPI1_IO3

DW16

GPP_E10/SPI1_CS_N/BK0/SBK0

DU16

GPP_E8/SATALED#/SPI1_CS1#

DV19

CL_CLK

DW19

CL_DATA

DT19

CL_RST#

ICL-U_BGA1526

@

TLS CONFIDENTIALITY

GPP_C2/SMBALERT#(INTERNAL PD 20K)

0 = TLS CONFIDENTIALITY DISABLE

1 = TLS CONFIDENTIALITY ENABLE

GPP_C2

RH692 4.7K_0201_5%

1 2

SMBUS

SPI 0

SML 0

GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK

SPI 1

MLINK

SML1

eSPI

5 of 19

GPP_C7/SML1DATA/SUSACK#

GPP_C5 (Internal 20 K internal Pull Down): SML0ALERT#

0 = Enable eSPI. (Default)

1 = Disable eSPI.

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_A5/ESPI_CLK

GPP_A0/ESPI_IO0 GPP_A1/ESPI_IO1 GPP_A2/ESPI_IO2 GPP_A3/ESPI_IO3

GPP_A4/ESPI_CS#

GPP_A6/ESPI_RESET#

PCH SPI

TPM

JSPI

NPI pop D20

PCH_SPI_CS1#_R PCH_SPI_SI_R PCH_SPI_SO_R PCH_SPI_CLK_R PCH_SPI_CS0#_R

PROM_BIOS_R(78)

PCH_SPI_IO3_R

+3V_SPI

DVT1_36

Follow Pebble Creek MLK

RH40 10K_0201_5%@

+3VS

1 2

RH727 10K_0201_5%@

1 2

RH41 10K_0201_5%@

1 2

DVT1.2_02

RH39 10K_0201_5%

1 2

ACES_50521-01041-P01_10P

SPI ROM ( 32MByte ) ROM is Quad SPI

PCH_SPI_CS0#_R SPI_SO_VROM0 SPI_IO3_VROM0 SPI_IO2_VROM0 SPI_CLK_VROM0

UH8

1

CS#

2

DO

3

IO2

4

GND

W25Q256JVEIQ_WSON8_8X6

ThemalPad

VCC

CLK

8 7

IO3

6

SPI_SI_VROM0

5

DI

9

MP pop RC745

+3V_SPI

RB751S40T1G_SOD523-2

1

CH35

0.1U_0201_10V6K

2

D20

@

+3V_PRIM

21

12

RC7450_0402_5%

PVT_03

B B

PVT_02

CLK_PCIE_N0(52)

WLAN--->

Reserved debug SSD-->

SSD-->

Card Reader--->

A A

CLK_PCIE_P0(52)

CLKREQ_PCIE#0(52)

CLK_PCIE_N1(67) CLK_PCIE_P1(67)

CLKREQ_PCIE#1(67)

CLK_PCIE_N2(68) CLK_PCIE_P2(68)

CLKREQ_PCIE#2(68)

CLK_PCIE_N4(70) CLK_PCIE_P4(70)

CLKREQ_PCIE#4(70)

JSPI1

1

2

3

4

5

6

G1

7

G2

8

9

10

CONN@

DVT1.2_17

DVT1.2_16

EVT2_28

11 12

DK33

CL2

DN34

CL3

DP34

CK3 CK4

DP36

DN40

UC1J

CJ3

CLKOUT_PCIE_N0

CJ5

CLKOUT_PCIE_P0 GPP_D5/SRCCLKREQ0#

CLKOUT_PCIE_N1

CL1

CLKOUT_PCIE_P1 GPP_D6/SRCCLKREQ1#

CLKOUT_PCIE_N2

CL5

CLKOUT_PCIE_P2 GPP_D7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_D8/SRCCLKREQ3#

CJ2

CLKOUT_PCIE_N4

CJ1

CLKOUT_PCIE_P4 GPP_H10/SRCCLKREQ4#

ICL-U_BGA1526

@

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

GPP_H11/SRCCLKREQ5#

RTC

XTAL

10 of 19

RTCX1 RTCX2

RTCRST#

SRTCRST#

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

XCLK_BIASREF

CF5 CF3 DP40

DL48 DL49

DT47 DK46

DF49

DW8 DU8

DU6

ESPI OR EC LESS

RH666 4.7K_0201_5%@

GPP_C5PCH_SPI_IO2 PCH_SPI_IO3

RH98 20K_0201_5%@

DK27 DP24 DL24

DK24 DJ24 DP22

DN22 DL22

CR47 CN45 CN48 CN49 CN47 CT45 CR46

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST# SRTCRST#

SUSCLK

XTAL_38P4M_IN_CPU XTAL_38P4M_OUT_CPU

CLK_BIASREF

GPP_C2

SML0_SMBCLK SML0_SMBDATA GPP_C5

SML1_SMBCLK_R SML1_SMBDATA_R

ESPI_CLK ESPI_IO0_R ESPI_IO1_R ESPI_IO2_R ESPI_IO3_R ESPI_CS# ESPI_RESET#

+3V_PRIM+3V_PRIM

1 2

SMB_CLK (79)

SMB_DATA (79)

SML0_SMBCLK (46,48)

SML0_SMBDATA (46,48)

RC569 49.9_0201_1% RC336 10_0201_1%

1 2

RC367 10_0201_1%

1 2

RC368 10_0201_1%

1 2

RC369 10_0201_1%

1 2

XTAL_38P4M_IN

XTAL_38P4M_OUT

10P_0201_50V8J

EVT1_30

PCH_RTCRST# (63,79)

SUSCLK (52,68)

RH14 0_0201_5%

1 2

RH15 0_0201_5%

1 2

RH475 60.4_0201_1%

1 2

SML1_SMBCLK_R SML1_SMBDATA_R

MIPI60

BB_L&BB_R (For support Vpro)

BB_L&BB_R PD_L&PD_R

12

2

CH10

1

Intel SPEC : CL = Specified Crystal Capacitive Load = 10 pF Series Resistance < or = 30 Ω Frequency Tolerance < or 100 PPM Aging ±3 PPM

SUSCLK

ESPI_CLK_5105 (58,79) ESPI_IO0 (58,79) ESPI_IO1 (58,79) ESPI_IO2 (58,79) ESPI_IO3 (58,79)

ESPI_CS# (58,79)

ESPI_RESET# (58,79)

RH17 200K _0201_1%

1 2

YH1

123

4

38.4MHZ_10PF_8Y38420005

1

CH49

@EMI@

0.1U_0201_10V6K

2

XTAL_38P4M_IN XTAL_38P4M_OUT

ESPI 1.8V

EMI Request

PCH_SPI_CLK

12

RC734

33_0201_5%

1

CC659

33P_0201_50V8J

2

@EMI@

2

1

CH11

10P_0201_50V8J

RH639 0_0201_5%@

1 2

RH638 0_0201_5%@

1 2

SML0_SMBDATA SML0_SMBCLK

SML1_SMBCLK_R SML1_SMBDATA_R

ESPI_CS# ESPI_RESET#

SMB_CLK

SML0_SMBCLK

SML1_SMBCLK_R

ESPI_CLK_5105

PCH_RTCX2

PCH_RTCX1

CH12

15P_0201_50V8J

CC655 33P_0201_50V8J

CC656 33P_0201_50V8J

CC657 33P_0201_50V8J

CC658 33P_0201_50V8J

RH16 10M_0201_1%

CRB XTAL ESR = 50K MAX

1

2

DVT1_06 DVT1_79

+RTCVCC_R

1U_0201_6.3V6K

1 2

RH573 20K_0201_5%

1 2

RH572 20K_0201_5%

1U_0201_6.3V6K

PDG_An RC delay circuit with a time delay in the range of 18–25 ms should be provided. The circuit should be connected to VCCRTC.

CH47

CH46

1

2

1

2

SML1_SMBCLK (42,44,46,48)

SML1_SMBDATA (42,44,46,48)

1 2 1 2

DVT1_61DVT1_32

RF Request

@RF@

1 2

@RF@

1 2

@RF@

1 2

@RF@

1 2

YC1

1 2

32.768KHZ_12.5PF_9H03200042

PCH_RTCRST#

SRTCRST#

PCH_RTCX2_R

RH144499_0201_1% RH143499_0201_1%

RH6061K_0201_5% RH6071K_0201_5%

RC71275K_0201_1% @ RC71175K_0201_1%

+3V_PRIM

RH637 0_0201_5%

1 2

1

CH13

15P_0201_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

Compal Electronics, Inc.

P009 - ICL-U(4/13)SPI,SMB,ESPI

LA-G172P

1

9 101Friday, May 24, 2019

1.0 (A00)

+3VS

RC222 49.9K_0201_1% RC223 49.9K_0201_1% RC655 49.9K_0201_1% RC656 49.9K_0201_1% RH713 100K_0201_5%@

1 2

+3V_PRIM

RC682 10K_0201_5%@

1 2

RH646 100K_0201_5%@

1 2

5

EVT2_28

12 12 12 12

UART2_RXD UART2_TXD UART2_RTS# UART2_CTS# PCH_TBT_PERST#

MEDIACARD_IRQ# PCH_TBT_PERST#

NO REBOOT

GPP_B18/GSPI0_MOS (Internal 20 K Pull Down)

0 = REBOOT ENABLED

RH632 2.2K_0201_5%@

1 2

RH633 2.2K_0201_5%@

1 2

D D

EVT1_34

RH300 10K_0201_5%

1 2

RH688 100K_0201_5%@

I2C2_SDA I2C2_SCL

1 = NO REBOOT

EVT2_05

NRB_BIT

PCH_TBT_PERST#

12

HDA_BIT_CLK

RH621 4.7K_0201_5%@

1 2

4

CPUNSSC CLOCK FREQ

GPP_B23 (Internal 20 K Pull Down)

0 = 38.4 MHz clock (direct from crystal) (default)

+3VS

1 = 19.2 MHz clock (from internal divider)

GPP_B23

RH647 4.7K_0201_5%@

1 2

+3V_PRIM +3V_PRIM

3

TOP SWAP OVERRIDE

GPP_B14 / SPKR (Internal 20 K Pull Down)

0 = Disable "Top Swap" mode. (Default)

1 = Enable "Top Swap" mode.

RH667 8.2K_0201_5%@

SPKR

1 2

2

1

EVT1_15EVT1_15

+3VS

RC339 10K_0201_5%@

1 2

RC338 10K_0201_5%@

1 2

RC254 0_0201_5%@

TPM_PIRQ#_R(66)

1 2

RC255 0_0201_5%@

1 2

DVT1.2_10

C C

+3V_PRIM

RH745 100K_0201_5%@

1 2

RH746 100K_0201_5%@

1 2

RH747 100K_0201_5%@

1 2

RH748 100K_0201_5%@

1 2

TPM_GPP_B17_SMI#_NMI TPM_PIRQ#

For TS lid open reserved

CPU_ID_0 CPU_ID_1

TS

TP

Reserved

UFCAM

MEDIACARD_IRQ#_R(70)

PCH_TBT_PERST#(46,48)

PANEL_BKLEN(6,38)

I2C_3_SDA_UFCAM(39) I2C_3_SCL_UFCAM(39)

0_0201_5% @

SPKR(56)

TPM_PIRQ# TPM_PIRQ#_B20

PCH_3.3V_TS_EN(71)

SBIOS_TX(79)

DVT1.2_18

UART2_RXD(79) UART2_TXD(79) UART2_RTS#(79) UART2_CTS#(79)

TS_I2C_SDA(38) TS_I2C_SCL(38)

I2C1_SDA_TP(63) I2C1_SCK_TP(63)

RH645

RH7300_0201_5% @

12

RH7310_0201_5% @

12

NRB_BIT TPM_GPP_B17_SMI#_NMI

MEDIACARD_IRQ#

12

@

12

RH7370_0201_5%

GPP_B23

PCH_TBT_PERST#

@

12

UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#

I2C2_SDA I2C2_SCL

CPU_ID_0 CPU_ID_1

RH7320_0201_5%

Strap Pin

ENBKL_TS

CPU I3/I5/I7 Option for different thermal table

Pin Name

CPU_ID_0

CPU_ID_1

I3

0

I5 I7

0

1

0

UC1F

CH48

GPP_B16/GSPI0_CLK

CF48

GPP_B18/GSPI0_MOSI

CF47

GPP_B17/GSPI0_MISO

CH49

GPP_B15/GSPI0_CS0#

CH47

GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#

CL47

GPP_B20/GSPI1_CLK

CK47

GPP_B22/GSPI1_MOSI

CK46

GPP_B21/GSPI1_MISO

CH45

GPP_B19/GSPI1_CS0#

CL48

GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#

DP21

GPP_C8/UART0_RXD

DK21

GPP_C9/UART0_TXD

DL21

GPP_C10/UART0_RTS#

DJ22

GPP_C11/UART0_CTS#

DT22

GPP_C20/UART2_RXD

DW22

GPP_C21/UART2_TXD

DV22

GPP_C22/UART2_RTS#

DU22

GPP_C23/UART2_CTS#

DT24

GPP_C16/I2C0_SDA

DT23

GPP_C17/I2C0_SCL

DW23

GPP_C18/I2C1_SDA

DU23

GPP_C19/I2C1_SCL

DU41

GPP_H4/I2C2_SDA

DV41

GPP_H5/I2C2_SCL

DW41

GPP_H6/I2C3_SDA

DT41

GPP_H7/I2C3_SCL

DT40

GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

DW40

GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

ICL-U_BGA1526

@

GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5

GSPI

UART

I2C

6 of 19

GPP_D16/ISH_UART0_CTS_N/CNV_WCEN

UART

I2C / ISH

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_B9/I2C5_SDA/ISH_I2C2_SDA

GPP_B10/I2C5_SCL/ISH_I2C2_SCL

ISH

GPP_D13/ISH_UART0_RXD GPP_D14/ISH_UART0_TXD

GPP_B5/ISH_I2C0_SDA GPP_B6/ISH_I2C0_SCL

GPP_B7/ISH_I2C1_SDA GPP_B8/ISH_I2C1_SCL

GPP_D0/ISH_GP0 GPP_D1/ISH_GP1 GPP_D2/ISH_GP2

GPP_D3/ISH_GP3 GPP_D17/ISH_GP4 GPP_D18/ISH_GP5 GPP_E15/ISH_GP6 GPP_E16/ISH_GP7

DV33 DW33 DT33 DU33

DK22 DW24 DV24 DU24

CN43 CN42

CN41 CL43

CL41 CJ39 DU36 DV36 DW36 DT36 DU34 DW34 DT14 DU14

SML0B_SMBDATA SML0B_SMBCLK

SML0BALERT#

SIO_EXT_WAKE#

UFCAM_RESET#

ISH_I2C1_SDA ISH_I2C1_SCL

ACC2_INT# ACC1_INT2# NB_MODE# TABLE_MODE# ISH_LID_CL_NB# ISH_LID_CL_TAB#

ISH_GP0 for Main A ccelerometer (Sensor Board)INT1# ISH_GP1 for 2n d Accelerometer (MB) ISH_GP2 for Main A ccelerometer (Sensor Board)INT2# ISH_GP3 for NB _MODE ISH_GP4 for ISH_ GP4# (ON TABLE) ISH_GP5 for NB _LID# ISH_GP6 for TA B_LID# ISH_GP7 for AL S_ALERT#

RC727 0_0201_5%@

SML0B_SMBDATA (58)

SML0B_SMBCLK (58)

1 2

SIO_EXT_WAKE# (58)

DBC_EN (38)

UFCAM_RESET# (39)

ISH_I2C0_SDA (63)

ISH_I2C0_SCL (63)

ISH_I2C1_SDA (39)

ISH_I2C1_SCL (39)

ACC1_INT1# (39) ACC2_INT# (63) ACC1_INT2# (39)

NB_MODE# (58)

TABLE_MODE# (58) ISH_LID_CL_NB# (58) ISH_LID_CL_TAB# (58) ALS_ALERT# (39)

EC

2nd Accelerometer

ALS,Ecompass,Main Acceleromete on SDB. Ecompass,Main Accelerometer on DB.

DVT1_04

DVT1.2_11

SIO_EXT_WAKE#

SML0B_SMBDATAACC1_INT1# SML0B_SMBCLK TABLE_MODE#

ISH_LID_CL_NB# ISH_LID_CL_TAB#

DVT1.2_11

UFCAM_RESET# TABLE_MODE# NB_MODE# ACC1_INT1# ACC1_INT2# ACC2_INT#

ACC1_INT1# ACC1_INT2# ACC2_INT#

DDR_CHA_EN DDR_CHB_EN

ISH_I2C0_SDA ISH_I2C0_SCL ISH_I2C1_SDA ISH_I2C1_SCL

HOST_SD_WP#

RC665 1K_0201_5% RC666 1K_0201_5% RC667 1K_0201_5% RC668 1K_0201_5%

RC717 10K_0201_5%

RC671 10K_0201_5%

RC672 1K_0201_5% RC673 1K_0201_5% RC680 10K_0201_5%

RC751 10K_0201_5% RC752 10K_0201_5%

RH658 100K_0201_5% RC679 10K_0201_5%@ RH610 10K_0201_5% RC738 10K_0201_5%@ RC739 10K_0201_5%@ RC740 10K_0201_5%@

RC741 10K_0201_5% RC742 10K_0201_5% RC743 10K_0201_5%

RH738 100K_0201_5%@ RH739 100K_0201_5%@

RH740 100K_0201_5%@ RH741 100K_0201_5%@

1 2 1 2

1 2 1 2 1 2

1 2 1 2

12 12 12 12

12

12 12 12

12 12

12

12 12 12

+3VS

+3V_PRIM

+3VS

EVT2_32

UC1G

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

EVT2_06

Reserved for debug

B B

SPCE p.30 PU or PD 100K-180K PDG define only JFP need to PD 10K.

12 12 12 12

12 12

RH20310K_0201_5% @ RH20210K_0201_5% @ RH20110K_0201_5% @ RH20010K_0201_5% @

RH11475K_0201_5% RH72810K_0201_5% @

GPP_A23 GPP_R5 GPP_S4 GPP_S5

CNV_RF_RESET# CLKREQ_CNV#

EVT1_23

DVT1_59

HDA_SDIN0(56)

CAM_DET#(39)

CNV_RF_RESET#(52) TS_RST#(38) CLKREQ_CNV#(52)

HDA_SDIN0

GPP_A23

RH7150_0201_5% @

12

GPP_R5

Reserved for debug

CNV_RF_RESET#

EVT2_43

GPP_S4

RH7160_0201_5% @

12

GPP_S5

Reserved for debug

HDA for AUDIO

RH113 33_0201_1%

HDA_BIT_CLK_L(56) HDA_SYNC_L(56) HDA_SDOUT_L(56)

A A

1

2

@RF@

CH50

56P_0201_25V8J

@RF@

1

CH51

2

1

2

56P_0201_25V8J

EVT1_36

1 2

RH111 33_0201_1%

1 2

RH112 33_0201_1%

1 2

CH40

@

22P_0201_50V8J

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

CY46

GPP_R0/HDA_BCLK/I2S0_SCLK

CV49

GPP_R1/HDA_SYNC/I2S0_SFRM

CY47

GPP_R2/HDA_SDO/I2S0_TXD

CV45

GPP_R3/HDA_SDI0/I2S0_RXD

DA47

GPP_R4/HDA_RST#

DP33

GPP_D19/I2S_MCLK

DC45

GPP_A23/I2S1_SCLK

DA49

GPP_R5/HDA_SDI1/I2S1_SFRM

DA45

GPP_R6/I2S1_TXD

DA48

GPP_R7/I2S1_RXD

CT49

GPP_A7/I2S2_SCLK

CT48

GPP_A8/I2S2_SFRM/CNV_RF_RESET#

CV47

GPP_A10/I2S2_RXD

CT47

GPP_A9/I2S2_TXD/MODEM_CLKREQ

CY39

GPP_S0/SNDW1_CLK

CY38

GPP_S1/SNDW1_DATA

DB39

GPP_S2/SNDW2_CLK

DD38

GPP_S3/SNDW2_DATA

DF38

GPP_S4/SNDW3_CLK/DMIC_CLK1

DD39

GPP_S5/SNDW3_DATA/DMIC_DATA1

ICL-U_BGA1526

@

GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO

GPP_S6/SNDW4_CLK/DMIC_CLK0

GPP_S7/SNDW4_DATA/DMIC_DATA0

AUDIO

7 of 19

FLASH DESCRIPTOR SECURITY OVERRIDE

GPP_R2/HDA_SDO (Internal 20 K Pull Down)

0 = ENABLE (DEFAULT)

1 = DISABLE (ME can update)

@

ME_FWP(58)

1 2

RH218 0_0201_5%

1 2

RH217 1K_0201_1%

GPP_G6/SD_CLK GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G0/SD_CMD

SD3.0

GPP_G7/SD_WP

GPP_G5/SD_CD#

GPP_H0/CNV_BT_I2S_SDO

SD3_RCOMP

SNDW_RCOMP

HDA_SDOUTME_FWP_PCH

CE46 CC48 CC49 CC47 CF45 CC45 CF49 CE47

DK38 DG38

CJ43

DG36 DG34

CV38

TBT_CIO_PLUG_EVENT# DDR_CHA_EN DDR_CHB_EN CNVI_EN#_R

GPP_H0 GPP_H1

SD3_RCOMP

WOV_DMIC_CLK0 WOV_DMIC_DATA0

SNDW_RCOMP

RH729 0_0201_5%@

RC20 200_0201_1%

DVT1_31

RH705 33_0201_5%@ RH706 33_0201_5%@

RC16 200_0201_1%

1

EVT2_32

1 2

1 1

1 2

1 2 1 2

1 2

AUD_PWR_EN (71)

TP53 PAD~D

TP@

SPK_DET# (57)

HOST_SD_WP# (70)

TP55 TP56

RF Request. Place near CPU side

EVT2_09

HDA_SDIN0

@RF@

CC727 2.2P_0201_50V8B

1 2

TP@ TP@

PAD~D PAD~D

CNVI_EN# (52,71)

PVT_08

Intel DMIC for WOV reserved

1

CC654

@

27P_0201_25V8

2

PCH_DMIC_CLK12 (39)

PCH_DMIC_DATA12 (39)

DVT1_82

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

Compal Electronics, Inc.

P010 - ICL-U(5/13)HDA,I2C,ISH

LA-G172P

1

10 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

3V SELECT STRAP

INPUT3VSEL

0 = 3.3V +/-5%

1 =3.0V +/-5%

RH301 4.7K_0201_5%@

D D

INPUT3VSEL

RH298

1 2

+3VALW_D SW

100K_0201_5%

STRAP FOR SPI 1.8V/3.3V SEL

INTRUDER#

0 = SPI voltage is 3.3V

1 = SPI voltage is 1.8V

+RTCVCC

RH641M_0201_1% @

12

INTRUDER#

RH67110K_0201_1%

12

CC6530.1U_0201_10V6K @

12

DVT1_81

UC1K

RH5940_0201_5% @

12

MIPI60_DBRESET#_R(79)

1 2

SIO_SLP_SUS# SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_S0#

SIO_SLP_WLAN#

PCH_RSMRST#_AND SYS_RESET# PCH_PLTRST#

PCH_DPWROK PCH_PWROK

INPUT3VSEL INTRUDER#

12 12 12 12

SIO_SLP_SUS#(16,47,49,58)

Microchip suggest 100K on RH575

RH5751M_0201_1%

H_THERMTRIP#

H_CATERR#

VCCST_PWRGD

H_PROCHOT#

PCH_TOUCHPAD_INTR#

SIO_SLP_S0#

PCH_DPWROK

MIPI60@

DVT1_43

RH5840_0201_5% @

12

RH5860_0201_5% @

12

RC6471K_0201_5% @

12

RC2471K_0201_5%

12

PCH_DPWROK(58)

SYS_PWROK(58,79)

VCCST_OVERRIDE

VCCSTPWRGOOD_TCSS

VCCST_PWRGD PCH_RSMRST#_AND

PECI_EC(58)

H_THERMTRIP#(58)

PCH_TOUCHPAD_INTR#(63)

SYS_PWROK SYS_PWROK_R

H_PROCHOT#(16,58,91)

DBG_PMODE(79)

12

CH480.01U_0402_16V7K

@

C C

VCCST_OVERRIDE_R(78)

PM_RSMRST_PWRGD_MIPI60(79)

+1.05V_VCCST

RH95 1K_0201_1%

RH80 49.9_0201_1%

RH588 1K_0201_5%

PLACE 'RA' CLO SE TO MCP - WIT HIN 1.5 INCH C RB P.35

VCCST_OVERRIDE_R

PLACE 1K SERIE S RESISTOR NEAR RSMRST_N AND VCCST_PWRGD “T” JUNCTION P OINT, NOT NEAR MIPI60

12

+1.05V_V CCSTG

RH96 1K_0201_5%

12

+3VS

RH631 10K_0201_5%

1 2

+3V_PRIM

RH709 100K_0201_5%

B B

1 2

SIO_SLP_S5#(79) SIO_SLP_S4#(58,78,79) SIO_SLP_S3#(58,78,79)

SIO_SLP_A#(79)

SIO_SLP_S0#(66,79) CPU_C10_GATE# (78)

SIO_SLP_WLAN#(71)

PCH_RSMRST#_AND(63,78) SYS_RESET#(79)

+3VS

RC433 8.2K_0201_5%@

RC434 8.2K_0201_5%@

H_PROCHOT# H_PROCHOT#_R

RC614 499_0201_1%

RH4 49.9_0201_1% RH5 49.9_0201_1% RH6 49.9_0201_1%@ RH7 49.9_0201_1%@

+3VS

RH655

DVT1_46 DVT1_50

D468

@

TOUCH_SCREEN_PD#_R(38)

2 1

RB751S40T1G_SOD523-2

DVT1_78

DVT1.2_19

A A

RH743

@

12

0_0201_5%

+3VALW

RC147 100K_0201_5%

1 2

3

D2

PMDXB600UNE_DFN1010B-6

S2

4

QC2B

6

D1

5

G2

G1

PMDXB600UNE_DFN1010B-6

S1

1

100K_0201_5%

1 2

TOUCH_SCREEN_PD#

12

LID_CL_TS_FP# (58,77)

2

DISPOFF_R#

QC2A

1 2

@

RH6540_0201_5% @

EVT1_19DVT1_04

RH744 0_0201_5%@

DISPOFF# (38)

PCH GLITCH ISSUE MITIGATION(PDG p.306)

RH683 100K_0201_5%

1 2

CH53 0.33U_0201_6.3V6M@

RH684 100K_0201_5%

1 2

CH54 0.33U_0201_6.3V6M@

RH685 100K_0201_5%

1 2

CH55 0.33U_0201_6.3V6M@

RH682 100K_0201_5%

1 2

CH52 0.33U_0201_6.3V6M@

RH686 100K_0201_5%

1 2

CH56 0.33U_0201_6.3V6M@

RH689 100K_0201_5%@

1 2

RH690 100K_0201_5%@

1 2

RH691 100K_0201_5%@

1 2

CH57 0.33U_0201_6.3V6M@

DVT1_32

1 2

SIO_SLP_S3#

SIO_SLP_S4#

SIO_SLP_A#

SIO_SLP_WLAN#

SIO_SLP_SUS#

SIO_SLP_S0#

PCH_PLTRST#

SIO_SLP_S5#

DM49

SLP_SUS#

DF45

GPD10/SLP_S5#

DC48

GPD5/SLP_S4#

DF47

GPD4/SLP_S3#

DH47

GPD6/SLP_A#

CL45

GPP_B12/SLP_S0#

DE49

GPD9/SPL_WLAN#

DN48

SLP_LAN#

DG49

RSMRST#

DK19

SYS_RESET#

CM49

GPP_B13/PLTRST#

DR48

DSW_PWROK

DN47

PCH_PWROK

DP19

SYS_PWROK

DN49

INPUT3VSEL

DR47

Strap Pin

INTRUDER#

ICL-U_BGA1526

@

if pop UC29, RC244 also need pop

RC430

@

1 2

+3VS

@

UC29

5

1

P

ME_RESET#

B

2

A

G

3

GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO

0_0201_5%

CC77

@

12

0.1U_0201_10V6K

SYS_RESET#_R SYS_RESET#

4

O

MC74VHC1G08DFT2G_ SC70-5

GPP_H18/CPU_C10_GATE#

GPD11/LANPHYPC/DSWLDO_MON

11 of 19

RC432 1K_0201_5%

DVT1_28

UC1D

H_CATERR# PECI_EC

H_THERMTRIP#

CPU_POPI_RCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP CPU_EOPIO_RCOMP

MEM_INTERLEAVED TOUCH_SCREEN_PD# PCH_TOUCHPAD_INTR#

GPP_E6 GPP_H2

Strap Pin

Strap Pin Strap Pin

J4

CATERR#

CD5

PECI

C3

PROCHOT#

E3

THRMTRIP#

CJ41

PROC_POPIRCOMP

DU3

PCH_OPIRCOMP

A14

RSVD_25

B14

RSVD_26

DL15

DBG_PMODE

DV11

GPP_E3/CPU_GP0

DT11

GPP_E7/CPU_GP1

CR38

GPP_B3/CPU_GP2

CR39

GPP_B4/CPU_GP3

DT12

GPP_E6

DJ38

GPP_H2/CNV_BT_I2S_SDO

DL38

GPP_H19/TIME_SYNC0

ICL-U_BGA1526

@

EMI request,Place near CPU side.

MIPI60_PCH_JTAG_TDO

MIPI60_PCH_JTAG_TDI

MIPI60_PCH_JTAGX

H_THERMTRIP#

H_PROCHOT#_R

@EMI@

CC735 0.1U_0201_25V6K

1 2

@EMI@

CC736 0.1U_0201_25V6K

1 2

@EMI@

CC737 0.1U_0201_25V6K

1 2

@EMI@

CC738 0.1U_0201_25V6K

1 2

@EMI@

CC739 0.1U_0201_25V6K

1 2

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B11/PMCALERT#

WAKE#

GPD2/LAN_WAKE#

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

GPD7

+3VS

RC244 10K_0201_5%

1 2

12

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TRST#

JTAG

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_JTAGX

PROC_PRDY#

PROC_PREQ#

4 of 19

DVT1_77

5

4

3

SIO_PWRBTN#_R

CY42

AC_PRESENT_R AC_PRESENT

DE46

PCH_BATLOW#

DH48

GPP_B11

CL39

CPU_C10_GATE#_R

DU40

GPP_H3

DG40

DL45

WAKE#

LAN_WAKE#_R LAN_WAKE#

DE47 DF48

VCCST_OVERRIDE

CE4

VCCST_PWRGD_CPU VCCST_PWRGD

CF2

VCCSTPWRGOOD_TCSS

CE3 CF1

CPUPWRGD

DC47

GPD7

@

RH57 0_0201_5%@ RH312 0_0201_5%@

RH659 0_0201_5%@ RH280 0_0201_5%@

RH207 0_0201_5%@

RH600 0_0201_5%@

RH587 60.4_0201_1%

RH595 1K_0201_5%

VCCST_PWRGD

CPUPWRGD

SYS_RESET#

1 2 1 2

1 2 1 2 1

PAD~D

TP57

1 2

1

CC649 100P_0201_50V8J

CC650 100P_0201_50V8J

CC651 0.1U_0201_10V6K

@

TP101

1 2

EMI@

@EMI@

CPUPWRGD_R

PAD~D TP@

ESD Request:place near CPU side

P3 K5 K3 P4 N1

N5 R5 K1 K2 N3 N2

P6 M6

MIPI60_CPU_JTAG_TCLK MIPI60_CPU_JTAG_TDI MIPI60_CPU_JTAG_TDO MIPI60_CPU_JTAG_TMS

MIPI60_PCH_JTAG_TRST# MIPI60_PCH_JTAG_TCLK MIPI60_PCH_JTAG_TDI MIPI60_PCH_JTAG_TDO MIPI60_PCH_JTAG_TMS MIPI60_PCH_JTAGX

MIPI60_CPU_JTAG_TCLK (79) MIPI60_CPU_JTAG_TDI (79 ) MIPI60_CPU_JTAG_TDO (79) MIPI60_CPU_JTAG_TMS (79) MIPI60_CPU_JTAG_TRST# (79)

MIPI60_PCH_JTAG_TRST# (79) MIPI60_PCH_JTAG_TCLK (79) MIPI60_PCH_JTAG_TDI (79 ) MIPI60_PCH_JTAG_TDO (79) MIPI60_PCH_JTAG_TMS (79) MIPI60_PCH_JTAGX (79)

MIPI60_PRDY# (79 ) MIPI60_PREQ# (79)

JTAG ODT DISABLE

GPP_E6

0 = JTAG ODT DISABLED

1 = JTAG ODT ENABLED

GPP_E6

RH660

RH661 4.7K_0201_5%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V_PRIM

100K_0201_5%

SIO_PWRBTN# (58,79)

AC_PRESENT (58)

TP@

TBT_I2C_INT#

1

TP70

PAD~D TP@

TBT_I2C_INT# (42,44,46,48)

PCH_PCIE_WAKE# (58)

LAN_WAKE# (58)

VCCST_PWRGD (78)

PCH_PWROK_P(91)

IMVP_VR_ON_P(78)

RH733

100K_0201_5%

PCH_PLTRST#

MC74VHC1G08DFT2G_ SC70-5

DVT1_28

MAF/SAF STRAP(eSPI Flash Sharing Mode)

GPP_H2/CNV_BT_I2S_SDI(INTERNAL PD 20K)

0 = MAF (Master Attached Flash)

1 = SAF (Slave Attached Flash)

RH618 2.2K_0201_5%@

GPP_H2

1 2

RH617 20K_0201_5%@

1 2

EVT2_33

Compal Secret Data

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

+3V_PRIM

PCH_RSMRST#_AND TBT_I2C_INT#

PCH_RSMRST#_AND

LAN_WAKE# PCH_BATLOW# AC_PRESENT PCH_PCIE_WAKE#

DVT1_41

+3VS

1 2

RH625 0_0201_5%@

1 2

+3VS

1

B

2

A

+3V_PRIM

1

B

2

A

EVT1_31

MIPI60_PCH_JTAG_TDI MIPI60_PCH_JTAG_TMS MIPI60_PCH_JTAG_TDO

MIPI60_CPU_JTAG_TDI MIPI60_CPU_JTAG_TMS MIPI60_CPU_JTAG_TDO

MIPI60_CPU_JTAG_TCLK MIPI60_PCH_JTAG_TCLK MIPI60_PCH_JTAG_TRST# MIPI60_PCH_JTAGX

@

UH6

5

P

4

O

MC74VHC1G08DFT2G_ SC70-5

G

3

+3V_PRIM

5

UH1

P

4

O

12

G

3

RH46

100K_0201_5%

TDI&TMS KEEP S TUB TO MINIMUM

TDO PLACE WITH IN 1.1INCH OF S OC

MEM_INTERLEAVED

DVT1_63

Title

Size Document Number Rev

Date: Sheet of

RH592 10K_0201_5%@

1 2

RC687 10K_0201_5%

1 2

RH591 100K_0201_5%

1 2

RH601 10K_0201_5%

1 2

RH460 100K_0201_5%

1 2

RH297 10K_0201_5%

1 2

RH653 1K_0201_5%

1 2

PCH_PWROK

DVT1_28

2

CC652

0.1U_0201_10V6K

1

PCH_PLTRST#_EC (46,48,52,58,66,67,68,70,79)

DVT1_52

PLACE WITHIN 1 .1INCH OF MCP

RC151 51_0201_5%MIPI60@

1 2

RC203 51_0201_5%MIPI60@

1 2

RC202 100_0201_5%

1 2

RC146 51_0201_5%@

1 2

RC181 51_0201_5%@

1 2

RC150 100_0201_5%

1 2

PLACE WITHIN 1 .1INCH OF SOC

RC145 51_0201_5%

1 2

RC180 51_0201_5%@

1 2

RC201 51_0201_5%@

1 2

RC344 51_0201_5%@

1 2

RH629 10K_0201_5%@

1 2

RH630 10K_0201_5%@

1 2

DIMM TYPE

HIGH

Interleave

LOW

Non-Interleave

Compal Electronics, Inc.

P011 - ICL-U(6/13)GPIO

LA-G172P

1

+3V_PRIM

+3VALW_D SW

+1.05V_VCCSTG

+3V_PRIM

1.0 (A00)

11 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

D D

PCIE_PRX_DTX_N9(68) PCIE_PRX_DTX_P9(68) PCIE_PTX_DRX_N9(68) PCIE_PTX_DRX_P9(68)

PCIE_PRX_DTX_N10(68) PCIE_PRX_DTX_P10(68) PCIE_PTX_DRX_N10(68)

PCIe SSDX4 PCIe Gen3

C C

SSD X 2 PCIe Gen3 Reserved for debug

CardreaderX1

DVT1_76

+3V_PRIM

B B

12 12

PCIe Gen2

RH60410K_0201_5% RH60510K_0201_5%

USB_OC0# USB_OC3#

PVT_10

PCIE_PTX_DRX_P10(68)

PCIE_PRX_DTX_N11(68) PCIE_PRX_DTX_P11(68) PCIE_PTX_DRX_N11(68) PCIE_PTX_DRX_P11(68) PCIE_PRX_DTX_N12(68)

PCIE_PRX_DTX_P12(68) PCIE_PTX_DRX_N12(68)

PCIE_PTX_DRX_P12(68) PCIE_PRX_DTX_N13(67) PCIE_PRX_DTX_P13(67) PCIE_PTX_DRX_N13(67) PCIE_PTX_DRX_P13(67)

PCIE_PRX_DTX_N14(67) PCIE_PRX_DTX_P14(67) PCIE_PTX_DRX_N14(67) PCIE_PTX_DRX_P14(67)

PCIE_PRX_DTX_N16(70) PCIE_PRX_DTX_P16(70) PCIE_PTX_DRX_N16(70) PCIE_PTX_DRX_P16(70)

USB_OC0# USB_OC3#

SD_PWR_EN(71)

UFCAM_LED(39)

PCIE_RCOMPN

RH1100_0201_1%

12

PCIE_RCOMPP

UC1H

CV7

PCIE7_RXN

CV6

PCIE7_RXP

DD3

PCIE7_TXN

DD5

PCIE7_TXP

CT6

PCIE8_RXN

CT7

PCIE8_RXP

DA3

PCIE8_TXN

DA5

PCIE8_TXP

CP7

PCIE9_RXN

CP6

PCIE9_RXP

DA2

PCIE9_TXN

DA1

PCIE9_TXP

CM7

PCIE10_RXN

CM6

PCIE10_RXP

CY3

PCIE10_TXN

CY4

PCIE10_TXP

CK7

PCIE11_RXN/SATA0_RXN

CK6

PCIE11_RXP/SATA0_RXP

CW2

PCIE11_TXN/SATA0_TXN

CW1

PCIE11_TXP/SATA0_TXP

CJ6

PCIE12_RXN/SATA1A_RXN

CJ7

PCIE12_RXP/SATA1A_RXP

CW5

PCIE12_TXN/SATA1A_TXN

CW3

PCIE12_TXP/SATA1A_TXP

CG7

PCIE13_RXN

CG6

PCIE13_RXP

CT3

PCIE13_TXN

CT5

PCIE13_TXP

CE6

PCIE14_RXN

CE7

PCIE14_RXP

CT2

PCIE14_TXN

CT1

PCIE14_TXP

CC5

PCIE15_RXN/SATA1B_RXN

CC6

PCIE15_RXP/SATA1B_RXP

CR3

PCIE15_TXN/SATA1B_TXN

CR4

PCIE15_TXP/SATA1B_TXP

CA6

PCIE16_RXN/SATA2_RXN

CA5

PCIE16_RXP/SATA2_RXP

CP1

PCIE16_TXN/SATA2_TXN

CP2

PCIE16_TXP/SATA2_TXP

DW12

GPP_E0/SATAXPCIE0/SATAGP0

CR42

GPP_A12/SATAXPCIE1/SATAGP1

CR43

GPP_A13/SATAXPCIE2/SATAGP2

DW14

GPP_E9/USB_OC0#

CT43

GPP_A16/USB_OC3#

DU12

GPP_E4/DEVSLP0

DU11

GPP_E5/DEVSLP1

CV48

GPP_A11/SATA_DEVSLP2

DT38

GPP_H12/M2_SKT2_CFG0

DW38

GPP_H13/M2_SKT2_CFG1

DV38

GPP_H14/M2_SKT2_CFG2

DU38

GPP_H15/M2_SKT2_CFG3

DN1

PCIE_RCOMPN

DN3

PCIE_RCOMPP

ICL-U_BGA1526

@

PCIe

PCIe / SATA

PCIe / USB3.1

PCIe / SATA

8 of 19

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN PCIE2_RXP/USB31_2_RXP

PCIE2_TXN/USB31_2_TXN

PCIE2_TXP/USB31_2_TXP

PCIE3_RXN/USB31_3_RXN PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

PCIE5_RXN/USB31_5_RXN PCIE5_RXP/USB31_5_RXP

PCIE5_TXN/USB31_5_TXN

PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN PCIE6_RXP/USB31_6_RXP

PCIE6_TXN/USB31_6_TXN

PCIE6_TXP/USB31_6_TXP

USB2.0

USB_VBUSSENSE

USB2_COMP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB_ID

RSVD_81

DJ8 DJ6 DJ2 DJ1

DG9 DG7 DJ3 DJ5

DE7 DE9 DF3 DF5

DC7 DC9 DF2 DF1

DA6 DA7 DE4 DE3

CY7 CY6 DD1 DD2

DN8 DP8

DK11 DJ11

DP13 DN13

DK10 DJ10

DL5 DL3

DP11 DN11

DK13 DJ13

DN6 DP6

DL2 DL1

DP10 DN10

USB2_ID

DL6

USB2_VBUSSENSE

DL11

USB2_COMP

DN5

CD3

USB3_PRX_DTX_N2 (79)

USB3_PRX_DTX_P2 (79)

USB3_PTX_DRX_N2 (79)

USB3_PTX_DRX_P2 (79)

PCIE_PRX_DTX_N3 (52)

PCIE_PRX_DTX_P3 (52)

PCIE_PTX_DRX_N3 (52)

PCIE_PTX_DRX_P3 (52)

USB20_N1 (79) USB20_P1 (79)

USB debug

DVT1_03

USB20_N5 (77) USB20_P5 (77)

USB20_N8 (50) USB20_P8 (50)

USB20_N9 (50) USB20_P9 (50)

USB20_N10 (52) USB20_P10 (52)

RH8 10K_0201_5%

1 2

RH9 10K_0201_5%

1 2

RH10 113_0201_1%

1 2

FPR

Type-C_L Type-C_R

BT

USB debug

WLAN

DVT1_05

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P012 - ICL-U(7/13)PCIE,USB

LA-G172P

1

12 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

EVT1_14

UC1I

Strap Pin Strap Pin

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4

EMMC_RCOMP

CNV_WT_RCOMP

CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX CNV_BRI_PTX_DRX CNV_RGI_PRX_DTX

GPP_F4

GPP_F19 GPP_F5

DVT2_02

RC17 200_0201_1%

1 2

CNV_PTX_DRX_N0 (52) CNV_PTX_DRX_P0 (52) CNV_PTX_DRX_N1 (52) CNV_PTX_DRX_P1 (52) CLK_CNV_PTX_DRX_N (52) CLK_CNV_PTX_DRX_P (52)

CNV_PRX_DTX_N0 (52) CNV_PRX_DTX_P0 (52) CNV_PRX_DTX_N1 (52) CNV_PRX_DTX_P1 (52) CLK_CNV_PRX_DTX_N (52)

RC15 150_0201_1%

RC503 22_0201_1% RC504 22_0201_1%

@

12

RC7460_0201_5%

CLK_CNV_PRX_DTX_P (52)

1 2

1 2 1 2

EVT1_15

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

DVT1_54

CNV_BRI_PRX_DTX CNV_RGI_PRX_DTX

Micron 8GB SA0000BX51L

0 1

0

CNV_BRI_PRX_DTX (52)

CNV_RGI_PTX_R_DRX (52) CNV_BRI_PTX_R_DRX (52)

CNV_RGI_PRX_DTX (52)

Micron 16GB SA0000BX61L

0

CNVi

RH724 20K_0201_5%@

1 2

RH725 20K_0201_5%@

1 2

Micron 32GB SA0000BX71L

0

1

0

Hynix 8GB SA0000BYX1L

1

0

+1.8V_PRIM

Hynix 16GB SA0000AW20L

OLD and NO SUPPORT

0

1

0

Memory Type Configuration Strap pin

+1.8V_PRIM

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

MEM_CONFIG4

0

1

0

Hynix 32GB SA0000C7V1L

3733

1

0

RH612 10K_0201_5%@

RH613 10K_0201_5%@

RH614 10K_0201_5%@

RH615 10K_0201_5%@

RH616 10K_0201_5%@

Samsung 8GB SA0000C6K1L

01

1

11

0 00000MEM_CONFIG3

0 0000MEM_CONFIG4

1 2

Samsung 16GB SA0000AU40L

OLD and NO SUPPORT

1

Samsung 32GB SA0000CGN1L

Samsung 16GB SA0000C6L1L

NEW NEW

1

0

1

0

GPP_F19

RH129 10K_0201_5%@

RH139 10K_0201_5%@

RH145 10K_0201_5%@

RH185 10K_0201_5%@

RH665 10K_0201_5%@

Hynix 16GB SA0000BYW1L

0

1

0

1

0 0

RH749 75K_0201_5%

1 2

Samsung 4GB SA0000AV71L

1

0

1

DVT2_02

Micron 4GB SA0000BWF0L

Micron 4GB EOL

0

1

0

Hynix 4GB SA0000AD11L

1

0

1

0

Hynix 32GB SA0000BWU1L

P-RTS(4266)

0

1

0

MCSI_E_CLKN MCSI_E_CLKP MCSI_E_DN0 MCSI_E_DP0

UF CAMERA

MCSI_E_CLKN(39) MCSI_E_CLKP(39) MCSI_E_DN0(39) MCSI_E_DP0(39)

DVT1_11

D D

RC8100_0201_1%

12

RT_FORCE_PWR(42,44,46,48)

UFCAM_MCLK(39)

CSI_RCOMP

For EA MIPI signal measure use

DVT1_11

MCSI_E_CLKP MCSI_E_CLKN MCSI_E_DP0

C C

MCSI_E_DN0

Need to close CPU

@

12

@

RC7480_0201_5%

12

RC7490_0201_5%

@

12

RC7500_0201_5%

D12

CSI_E_CLK_N

C12

CSI_E_CLK_P

B12

CSI_E_DN_0

A12

CSI_E_DP_0

G13

CSI_E_DN_1

F13

CSI_E_DP_1

K10

CSI_F_CLK_N

L10

CSI_F_CLK_P

L8

CSI_F_DN_0

M8

CSI_F_DP_0

M11

CSI_F_DN_1

L11

CSI_F_DP_1

D9

CSI_D_CLK_N

C9

CSI_D_CLK_P

A7

CSI_D_DN_0

B7

CSI_D_DP_0

B9

CSI_D_DN_1

A9

CSI_D_DP_1

D7

CSI_D_DN_2/CSI_C_DN_0

C7

CSI_D_DP_2/CSI_C_DP_0

D8

CSI_D_DN_3/CSI_C_CLK_N

C8

CSI_D_DP_3/CSI_C_CLK_P

G11

CSI_H_CLK_N

J11

CSI_H_CLK_P

F6

CSI_H_DN_0

G6

CSI_H_DP_0

G10

CSI_H_DN_1

F10

CSI_H_DP_1

G8

CSI_H_DN_2/CSI_G_DN_0

J8

CSI_H_DP_2/CSI_G_DP_0

K6

CSI_H_DN_3/CSI_G_CLK_N

L6

CSI_H_DP_3/CSI_G_CLK_P

B4

CSI_RCOMP

DT34

GPP_D4/IMGCLKOUT0

DP38

GPP_H20/IMGCLKOUT1

DK36

GPP_H21/IMGCLKOUT2

DL36

GPP_H22/IMGCLKOUT3

DN38

GPP_H23/IMGCLKOUT4

ICL-U_BGA1526

@

eMMC

GPP_F18/EMMC_RESET#

CSI2

CNVi

GPP_F1/CNV_BRI_RSP/UART0_RXD

GPP_F2/CNV_RGI_DT/UART0_TXD

GPP_F0/CNV_BRI_DT/UART0_RTS#

GPP_F3/CNV_RGI_RSP/UART0_CTS#

GPP_F4/CNV_RF_RESET#

GPP_F6/CNV_PA_BLANKING

GPP_F19/A4WP_PRESENT GPP_F5/MODEM_CLKREQ

9 of 19

GPP_F8/EMMC_DATA0

GPP_F9/EMMC_DATA1 GPP_F10/EMMC_DATA2 GPP_F11/EMMC_DATA3 GPP_F12/EMMC_DATA4 GPP_F13/EMMC_DATA5 GPP_F14/EMMC_DATA6 GPP_F15/EMMC_DATA7

GPP_F7/EMMC_CMD

GPP_F16/EMMC_RCLK

GPP_F17/EMMC_CLK

EMMC_RCOMP

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N

CNV_WT_D1P CNV_WT_CLKN CNV_WT_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WR_CLKN CNV_WR_CLKP

CNV_WT_RCOMP

DP27 DU30 DT30 DT29 DV30 DU29 DW30 DW29 DV28 DW28 DN27 DT28 DU28

DV45 DU45 DU44 DT44 DL42 DK42

DP44 DN44 DG42 DG44 DK44 DJ44

DT45

DL29 DP31 DL31 DN29

DJ29 DP29 DL27 DK29

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P013 - ICL-U(8/13)CSI,CNVi,EMMC

LA-G172P

1

13 101Friday, May 24, 2019

1.0 (A00)

5

D D

4

3

2

1

+VCCIN

Max1.89V/62A(Processor EDS 572795 rev 1.2)

UC1L

A19

AC12

V13

W12

Y13 K29 K31 B19 B23 B27 B29

C C

B B

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

BN10 BP11

BP9

BR10

BT11

A21

BT9 BU10 BV36

BV9

BW10 BW36

BW9

BY10

C19

C23

A23 C27 C29

CA36

CA9

CB10 CC11 CC36

CC9

CD10

CE11

A24 CE34 CE35 CF10 CF33

CG11 CG34 CG35 CH10

J30

CJ11

A27

CJ34

H1 H2 H3

CPU POWER 1 OF 3

VCCIN_1 VCCIN_2 VCCIN_3 VCCIN_4 VCCIN_5 VCCIN_6 VCCIN_7 VCCIN_8 VCCIN_9 VCCIN_10 VCCIN_11 VCCIN_12 VCCIN_13 VCCIN_14 VCCIN_15 VCCIN_16 VCCIN_17 VCCIN_18 VCCIN_19 VCCIN_20 VCCIN_21 VCCIN_22 VCCIN_23 VCCIN_24 VCCIN_25 VCCIN_26 VCCIN_27 VCCIN_28 VCCIN_29 VCCIN_30 VCCIN_31 VCCIN_32 VCCIN_33 VCCIN_34 VCCIN_35 VCCIN_36 VCCIN_37 VCCIN_38 VCCIN_39 VCCIN_40 VCCIN_41 VCCIN_42 VCCIN_43 VCCIN_44 VCCIN_45 VCCIN_46 VCCIN_47 VCCIN_48 VCCIN_49 VCCIN_50 VCCIN_51

VIDALERT# VIDSCK VIDSOUT

ICL-U_BGA1526

@

12 of 19

VCCIN_52 VCCIN_53 VCCIN_54 VCCIN_55 VCCIN_56 VCCIN_57 VCCIN_58 VCCIN_59 VCCIN_60 VCCIN_61 VCCIN_62 VCCIN_63 VCCIN_64 VCCIN_65 VCCIN_66 VCCIN_67 VCCIN_68 VCCIN_69 VCCIN_70 VCCIN_71 VCCIN_72 VCCIN_73 VCCIN_74 VCCIN_75 VCCIN_76 VCCIN_77 VCCIN_78 VCCIN_79 VCCIN_80 VCCIN_81 VCCIN_82 VCCIN_83 VCCIN_84 VCCIN_85 VCCIN_86 VCCIN_87 VCCIN_88 VCCIN_89 VCCIN_90 VCCIN_91 VCCIN_92 VCCIN_93 VCCIN_94 VCCIN_95 VCCIN_96 VCCIN_97 VCCIN_98

VCCIN_99 VCCIN_100 VCCIN_101 VCCIN_102 VCCIN_103 VCCIN_104

VCCIN_SENSE

VSSIN_SENSE

CJ35 CK10 J32 CL34 CL35 CN34 CN35 CP33 CR34 A29 CR35 CT33 CT34 CT35 CU33 D19 D21 D23 D24 D27 AA12 D29 F19 F21 F23 F24 F27 F29 G1 G19 G23 AB1 G27 G29 H19 H23 H27 H29 J18 J20 J22 J23 AB13 J26 J28 K17 K19 K21 K23 K24 K27 M1 U1

F17 G17

VCCIN_SENSE_R VSSIN_SENSE_R

RC683 0_0201_5%@

1 2

RC684 0_0201_5%@

1 2

Trace Length Match<25 mils Must be routed as differential pair to VR

VCCIN_SENSE (91) VSSIN_SENSE (91)

1.The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).

2.Route the Alert signal between the Clock and the Data signals. CAD Note: Place the PU resistors close to CPU

+1.05V_VCCST

12

SVID DATA

SOC_SVID_DAT

SVID ALERT#

SOC_SVID_ALERT#

SVID CLK

SOC_SVID_CLK

@

12

RC6030_0201_5%

+1.05V_VCCST

@

12

RC6010_0201_5%

+1.05V_VCCST

@

12

RC6050_0201_5%

RC604 100_0201_1%

12

RC602 56_0201_5%

12

RC606

100_0201_5%

1

C4195 33P_0201_50V8J

2

@

@RF@

SVID_DAT (91)

SVID_ALERT# (91)

SVID_CLK (91)

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P014 - ICL-U(9/13)CPU PWR,SVID

LA-G172P

1

14 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

+1.1V_MEM

EMC CAPS

+1.1V_MEM

PLACE <160mil FROM SOC VDDQ, WITH EACH PAIR <470mil APART

CC14010U_0402_10V6M

CC1311U _0201_6.3V6K

CC1301U _0201_6.3V6K

D D

1

2

CC1331U _0201_6.3V6K

CC1321U _0201_6.3V6K

1

2

CC1341U _0201_6.3V6K

1

2

CC1351U _0201_6.3V6K

1

2

CC13710U_0402_10V6M

CC13610U_0402_10V6M

1

2

CC13910U_0402_10V6M

CC13810U_0402_10V6M

1

2

@

CC14122U_0603_6.3V6M

1

2

@

CC14222U_0603_6.3V6M

1

2

CC64312P_0201_25V8JEMI@

1

2

CC64412P_0201_25V8JEMI@

CC6462.2P_0201_25V8CEMI@

1

2

CC6472.2P_0201_25V8CEMI@

1

2

CC6482.2P_0201_25V8CEMI@

CC64512P_0201_25V8JEMI@

1

2

CC66012P_0201_25V8J@EMI@

CC6632.2P_0201_25V8C@EMI@

1

2

Primary side cap

Follow PDG rev1.1 P.545

+1.1V_MEM

1.1V/3.5A(Processor EDS 572795 rev 1.2)

UC1M

AA37

VDDQ_1

AG36

VDDQ_2

AJ36

VDDQ_3

AL36

VDDQ_4

AL49

+VCCST_CPU +VCCSTG_CPU

C C

1

CC154

@

1U_0201_6.3V6M

2

1

CC153 1U_0201_6.3V6M

2

1

CC155

@

1U_0201_6.3V6M

2

1

CC156 1U_0201_6.3V6M

2

DVT1_19

+VCCST_CPU +1.05V_VCCST

@

1 2

RC592 0_0603_5%

+1.05V_VCCSTG+VCCSTG_OUT_LGC

@

1 2

RC659 0_0603_5%

B B

DVT1.2_12

1U_0201_6.3V6M

+VCCSTG_OUT

CC191

@

1

2

+VCCSTG_OUT_LGC

+VCCSTG_CPU

+VCCSTG_OUT

+VCCST_CPU

1.05V/0.8A

1.05V/0.15A

VDDQ_5

AN36

VDDQ_6

AP37

VDDQ_7

AR36

VDDQ_8

AR37

VDDQ_9

AT36

VDDQ_10

AT49

VDDQ_11

AA49

VDDQ_12

AV36

VDDQ_13

AW37

VDDQ_14

AY36

VDDQ_15

BA37

VDDQ_16

BA49

VDDQ_17

BB36

VDDQ_18

BD36

VDDQ_19

BE37

VDDQ_20

BF36

VDDQ_21

BF37

VDDQ_22

AB36

VDDQ_23

BF49

VDDQ_24

BG36

VDDQ_25

BJ36

VDDQ_26

BL37

VDDQ_27

BM49

VDDQ_28

BN37

VDDQ_29

BP38

VDDQ_30

CB1

VCCST

BY1

VCCSTG

F33

VCCSTG_OUT_1

G33

VCCSTG_OUT_2

E5

VCCSTG_OUT_LGC

ICL-U_BGA1526

@

CPU POWER 2 OF 3

VCCSTG_OUT_3 VCCSTG_OUT_4 VCCSTG_OUT_5 VCCSTG_OUT_6 VCCSTG_OUT_7

VCCPLL_OC_1 VCCPLL_OC_2 VCCPLL_OC_3 VCCPLL_OC_4

13 of 19

VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35 VDDQ_36 VDDQ_37 VDDQ_38 VDDQ_39 VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45 VDDQ_46 VDDQ_47

RSVD_78

RSVD_2 RSVD_3

VCC1P8A_1 VCC1P8A_2 VCC1P8A_3 VCC1P8A_4 VCC1P8A_5

RSVD_74 RSVD_75 RSVD_76

VCCPLL

VCCIO_OUT

BP39 BR37 BT38 AC35 BU37 BU49 CA39 CB49 L38 L49 N36 T49 AC37 AD35 AD36 AE36 AF49

C33

A33 B33

BG9 BJ9 BM9 BW1 BW2

R35 V34 T34 U35 AB34 W35 AA35 Y34

CD2

CG38 CG41 CG42 CG49

AD7

C33,A33,B33 is RSVD Intel recommended NC

1.8V/0.7A

+VCCSTG_OUT

DVT1.2_12

RSVD_W35 RSVD_AA35 RSVD_Y34

1

TP72

1

TP71

1

TP73

1.05V/0.09A

1.1V/0.16A

+VCCIO_OUT

TP@ TP@ TP@

PAD~D PAD~D PAD~D

+VCC1P05_OUTPUT_PLL

+VCC1P8A

+VCC_SFR_OC

VCC1P8A shape from VR to VCC1P8A pins should have: a. total length L of < 22mm between VR and BGA. b. Average width W of 1.8mm.

1

CC129 10U_0402_10V6M

2

1

CC308 22U_0603_6.3V6M

2

DVT1_18

1

CC144 1U_0201_6.3V6M

2

1

CC145 1U_0201_6.3V6M

2

+VCC1P8A

@

+VCC_SFR_OC

1

@

CC189 1U_0201_6.3V6M

2

1

CC188 10U_0402_10V6M

2

CC6642.2P_0201_25V8C@EMI@

CC66212P_0201_25V8J@EMI@

1

2

@

CC6652.2P_0201_25V8C@EMI@

CC66112P_0201_25V8J@EMI@

1

2

DVT1_19

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

+VCC1P05_OUTPUT_PLL

2

DVT1_18

1

CC147 1U_0201_6.3V6M

2

Title

Size Document Number Rev

Date: Sheet of

1

@

CC148 1U_0201_6.3V6M

2

Compal Electronics, Inc.

P015 - ICL-U(10/13)CPU PWR

LA-G172P

1.0 (A00)

15 101Friday, May 24, 2019

1

15 101Friday, May 24, 2019

5

4

3

2

1

+VCCPRIM_1P8

DVT1_19

+3V_PRIM

breakout with a 3.8mm width plane

1

CC170 1U_0201_6.3V6M

2

@

1

CC171

@

0.1U_0201_10V6K

2

PLACE NEAR DG26

breakout with a 5mm width pl ane

1

CC173 1U_0201_6.3V6M

2

@

1

CC174

@

1U_0201_6.3V6M

2

1

CC175 1U_0201_6.3V6M

2

PDG p.545 use XFL4012-601ME

SDS p.23 use UHP252012 , now use

CRB p.62 use 0.6UH/5A

GND shield around the VCC tr ace routing

1 2

@

1 2

12

1

CC177 1U_0201_6.3V6M

2

+3VALW_DSW

@

RC120 0_0603_5%

RC589

0.1_0402_1%

1

CC176 47U_0603_6.3V6M

2

breakout with a 1.4mm width plane

1

CC180

@

1U_0201_6.3V6M

2

PLACE NEAR DE31

DVT1_19

+1.8V_PRIM

@

1 2

RC587 0_0603_5%

@

DVT1_19

+1.8V_PRIM

LC10.68UH_UHP252012NF-R68M_3A_20% @

1.8V/27 A(PCH EDS 572631 rev 1.0)

D D

Trace Length Match<25 mils Must be routed as differential pair to VR

VCCIN_AUX_VCCSENSE(89) VCCIN_AUX_VSSSENSE(89)

C C

RC685 0_0201_5%@

1 2

RC686 0_0201_5%@

1 2

EVT2_35

+VCCPFUSE_3P3

+VCCPRIM_1P8

+V3.3A_1.8A_PCH_SPI

VCCDSW_EN_GPIO(78)

VCCDSW_EN(58)

ALW_PWRGD_3V_5V(58,78)

VCCIN_AUX_VCCSENSE_R VCCIN_AUX_VSSSENSE_R

+V1.05A_BYPASS

+VNN_BYPASS

RC697 0_0201_5%@

+VCCIN_AUX

1.05V/0.2A

3.3V/0.003A

1 2

UC1N

AH1

VCCIN_AUX_1

AW10

VCCIN_AUX_2

AY11

VCCIN_AUX_3

AY9

VCCIN_AUX_4

BA10

VCCIN_AUX_5

BB9

VCCIN_AUX_6

CH1

VCCIN_AUX_7

CK11

VCCIN_AUX_8

CL10

VCCIN_AUX_9

CM11

VCCIN_AUX_10

CN1

VCCIN_AUX_11

AJ1

VCCIN_AUX_12

CN10

VCCIN_AUX_13

CP11

VCCIN_AUX_14

CR10

VCCIN_AUX_15

CT11

VCCIN_AUX_16

CU10

VCCIN_AUX_17

CV1

VCCIN_AUX_18

CV11

VCCIN_AUX_19

CW10

VCCIN_AUX_20

CY11

VCCIN_AUX_21

DC1

VCCIN_AUX_22

AL1

VCCIN_AUX_23

P13

VCCIN_AUX_24

R12

VCCIN_AUX_25

T13

VCCIN_AUX_26

U12

VCCIN_AUX_27

DC11

VCCIN_AUX_28

DE12

VCCIN_AUX_29

DF12

VCCIN_AUX_30

AM1

VCCIN_AUX_31

AN1

VCCIN_AUX_32

AT11

VCCIN_AUX_33

AT9

VCCIN_AUX_34

AU10

VCCIN_AUX_35

AV9

VCCIN_AUX_36

BF9

VCCIN_AUX_VCCSENSE

BD9

VCCIN_AUX_VSSSENSE

DJ15

VCC_V1P05EXT_1P05

CY34

VCC_VNNEXT_1P05

DC33

VCCPRIM_3P3_1

DD35

VCCPRIM_1P8_1

DB34

VCCSPI

ICL-U_BGA1526

@

CPU POWER 3 OF 3

14 of 19

SIO_SLP_SUS#(11,47,49,58)

DC1

2 1

RB751S40T1G_SOD523-2

DC2

21

RB751S40T1G_SOD523-2

VCCPRIM_3P3_2 VCCPRIM_3P3_3 VCCPRIM_3P3_4

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_4 VCCPRIM_1P8_5 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_8 VCCPRIM_1P8_9

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8

VCCDPHY_1P24

VCCDSW_1P05

VCC1P05_1 VCC1P05_2 VCC1P05_3

VCCPLL

VCCPRIM_1P05_1

VCCPRIM_1P05_2

VCCPRIM_1P05_3

VCCPRIM_1P05_4

VCCRTC

VCCDSW_3P3

VCCPGPPR

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

GPP_B2/VRALERT#

VCCDSW_EN_Q

DF23 DG26 DG28

DF15 DF17 DF18 DF20 DG17 DG18 DG20 DF34

DW37

DW15

DW32

DD34

BY2 CB2 CC1

CD1

DG31

DG29

DF29

DF31

DG33

DE31

DF26

CL38 CJ38 CN38

RC699 0_0201_5%@

1 2

RC698 0_0201_5%@

1 2

+3V_PRIM

3.3V/0.202A

+VCCPRIM_1P8

1.8V/1.3A

+VCCLDOSTD_OUT_0P85

0.85V/TBDA

1.8V/0.165A

1.24V/TBDA

1.05V/TBDA

1.05V/0.09A

1

TP100

TP@

1.05V/TBDA

3.3V/0.002A

3.3V/0.004 A

3.3V,1.8V,1.5V/0.005A

CORE_VID0_R CORE_VID1_R VRALERT#

RC690 0_0201_5%@ RC689 0_0201_5%@ RC688 0_0201_5%@

PCH_PRIM_EN_R

+VCCA_CLKLDO_1P8

+VCCDPHY_1P24

+VCC1P05_OUTPUT_PLL

PAD~D

+VCC1.05_OUT_PCH

+VCCPRTC_3P3

1 2 1 2 1 2

1 2

0_0402_5%

RC505

@

+VCCDSW_1P05

+3VALW_DSW

CORE_VID0 CORE_VID1 VRALERT#_R

12

RC508

1M_0201_5%

@

12

CC511

@

0.1U_0402_25V6

+VCC1.05_OUT_FET

+3V_1.8V_HDA

CORE_VID0 (78,89) CORE_VID1 (78,89) VRALERT#_R (83)

PCH_PRIM_EN (88)

DVT1_03

1U_0201_6.3V6K

PLACE NEAR DG33

0.1uF cap should place befor e the 1uF cap.

+VCCDSW_1P05

+VCCDPHY_1P24

+VCCLDOSTD_OUT_0P85

1

CC260

2

EVT2_47

2.6mm width plane

1

CC181

0.1U_0201_10V6K

2

1uF cap should place after t he 0.1uF cap.

1

CC183 1U_0201_6.3V6M

2

PLACE NEAR DD34

DVT1_19

1

CC184

4.7U_0201_6.3V6M

2

PLACE NEAR DW32 WITHIN 3MM FROM PACKAGE

1

CC185 1U_0201_6.3V6K

2

PLACE NEAR DW37 WITHIN 3MM FROM PACKAGE

RC696

@

1 2

0_0402_5%

1

CC182 1U_0201_6.3V6M

2

PLACE NEAR DF23

PLACE NEAR DG20

0.8mm width plane

+RTCVCC+VCCPRTC_3P3

DVT1_19

+VCCA_CLKLDO_1P8

PLACE NEAR DW15

Power reserved

RC744

20K_0201_5%

+3V_PRIM

1 2

VRALERT#_R

D21

21

RB751S40T1G_SOD523-2

H_PROCHOT# (11,58,91)

CORE_VID0 CORE_VID1

RC663 RC664

12

10K_0201_5%

12

10K_0201_5%

+3VALW

CORE_VID0

CORE_VID1

@

RC609

RC611

RC610

RC612

12

10K_0201_5%

12

10K_0201_5%

12

10K_0201_5%

12

10K_0201_5%

For volume segment platform this rail is disabled.

B B

Keep the pin floating (do no t short this pin to ground).

+V1.05A_BYPASS

RC595 100K_0201_5%@

1 2

RC648 100K_0201_5%@

1 2

+VNN_BYPASS

+1.8V_PRIM

RC583

@

1 2

0_0402_5% RC582 0_0402_5%

@

1 2

+V3.3A_1.8A_PCH_SPI+3V_PRIM

1

CC30

@

0.1U_0201_10V6K

2

+1.8V_PRIM

Follow #575759 p.32

+3V_PRIM

Close to RC164

1

CC164

@

10P_0201_25V8

2

A A

5

+1.8V_PRIM

RC168 0_0402_5%

@

1 2

RC165 0_0402_5%

@

1 2

+3V_1.8V_HDA_R

LC2

BLM18EG221TN1D_2P~D

1 2

2

RF@

CC167

2.2P_0201_25V

1

EVT2_35

2

RF@

1

RC747 0_0402_5%

@

1 2

+3V_1.8V_HDA

CC168

2.2P_0201_25V

+VCCPFUSE_3P3+3V_PRIM

4

1

CC23

0.1U_0201_10V6K

2

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Date: Sheet of

Compal Electronics, Inc.

P016 - ICL-U(11/13)PCH Power

LA-G172P

1

16 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

UC1O

D D

C C

B B

A11

A46 BA45 BA47 BB11

BB3 BB7

BC37

BD3 BD38 BD39 BD41

A48 BD42 BD43 BD45 BD49

BD5 BD6 BD7 BE1 BE2 BF3

A49

BF45 BF47

BF7

BG3

BG41

BG7

BH37

BJ1

BJ2

BJ3 AA45

BJ41 BJ43 BJ45 BJ49

BJ7

BM11

BM3 BM45 BM47

BM5

AA47

BM6

BM7

BP1 BP2 BP3

BP43

BP7 BR45 BR49 AB11

AB3 AB38 AB39 AB41

A17 AB42 AB43

AB5

AB6 AC45 AC49 AD10 AD11 AD34 AD37

AE6

AF37

A3

GND 1 OF 3

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74

15 of 19

ICL-U_BGA1526

@

VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148

AF45 AF47 AG1 AG11 AG3 AG38 AG39 AG41 A31 AG42 AG43 AG5 AG9 AH2 AH37 AH45 AH49 AJ2 AJ3 A34 AK37 AL2 AL45 AL47 AL6 AM2 AM37 AN2 AN38 AN39 A36 AN41 AN42 AN43 AN45 AN49 AN6 AR1 AR11 AR2 AR3 A39 AR7 AR9 AT3 AT45 AT47 AT5 AT6 AT7 AU37 AV11 A42 AV3 AV38 AV39 AV41 AV42 AV43 AV45 AV49 AV7 AY3 A44 AY7 B17 B2 B21 B24 B3 B31 B48 BA1 BA2

BT3 BT39 BT41 BT42 BT43

BT7

BU45 BU47

BV1 BV11

BV2

BV3

BV7

BW3

BW37

BW5 BW6

BW7 BY37 BY45

BY49

C11 C13 C14 C17 C21 C24 C31 C34 C39 C48 C49

CA3 CA38 CA41 CA42 CA43

CA7 CB37 CB45 CB47

CC3

CC7 CE37 CE45 CE49

CE9

CG37 CG39 CG43 CG45 CG47

CG9

CH3

CH5

CJ37 CJ42

CJ9 CK45 CK49

CK9 CL37 CL42 CL49

CM45 CM47

CM9

CN3

CN37 CN39

CN5

CP9

CR32

C6

UC1P

GND 2 OF 3

VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222

16 of 19

ICL-U_BGA1526

@

VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CR37 CR45 CR49 CT37 CT39 CT42 CT9 CU45 CU47 CU49 CV3 CV34 CV35 CV5 CV9 CY41 CY45 CY49 CY9 D13 D17 D31 D44 D49 DA10 DA33 DA9 DB32 DB35 DB38 DB45 DB47 DB49 DC3 DC49 DC5 DC6 DD37 DD42 DE10 DE13 DE17 DE18 DE20 DE22 DE23 DE26 DE28 DE29 DE33 DE45 DE6 DF13 DF22 DF28 DF33 DF35 DF39 DG10 DG12 DG13 DG15 DG22 DG23 DG47 DG6 DH1 DH3 DH45 DH5 DJ19 DJ21 DJ27 DJ31

DJ33 DJ36 DJ42

DK3 DK4

DK49

DK6

DK8 DL10 DL13 DL44 DL47

DM47

DN15 DN19 DN24 DN31 DN36 DN42 DP45 DR49

DT1 DT10 DT15 DT20 DT27

DT3 DT32 DT37 DT42 DT49

DT6

DT7

DT8

DU1 DU10 DU15

DU2 DU20 DU27 DU32 DU37 DU48 DU49

DU7

DV2 DV44 DV48

DV8

DW1

DW10

DW2 DW20 DW27 DW44 DW46 DW48 DW49

DW7

E11 E34 E36 E39 E42

E6

UC1Q

GND 3 OF 3

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

17 of 19

ICL-U_BGA1526

@

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427

F11 F31 F45 F47 F8 G21 G24 G3 G31 G36 G49 G5 H17 H21 H24 H31 H33 H36 H45 H49 J10 J13 J16 J36 J6 K11 K33 K8 L36 L39 L41 L42 L43 L45 L47 M10 M3 M36 M5 N45 N49 P11 P41 P8 R3 R37 T11 T36 T41 T43 T45 T47 U3 U37 U5 V11 V36 V45 V49 V9 W37 Y36 Y38 Y43 Y9 DE15

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

P017 - ICL-U(12/13)GND

LA-G172P

1

1.0 (A00)

17 101Friday, May 24, 2019

5

MIPI60_CFG0#(79) MIPI60_CFG1#(79) MIPI60_CFG2#(79) MIPI60_CFG3#(79) MIPI60_CFG4#(79) MIPI60_CFG5#(79) MIPI60_CFG6#(79) MIPI60_CFG7#(79) MIPI60_CFG8#(79) MIPI60_CFG9#(79)

D D

MIPI60_CFG10#(79) MIPI60_CFG11#(79) MIPI60_CFG12#(79) MIPI60_CFG13#(79) MIPI60_CFG14#(79) MIPI60_CFG15#(79)

MIPI60_CFG_STB0_DN(79) MIPI60_CFG_STB0_DP(79)

MIPI60_CFG_STB1_DN(79) MIPI60_CFG_STB1_DP(79)

1 2

MIPI60_MBP0#(79) MIPI60_MBP1#(79)

EVT1_35

+VCCIO_OUT

TP27

TP@

RC723 10K_0201_5%@

1 2

RC724 10K_0201_5%@

1 2

C C

MBP2# MBP3#

PAD~D

TP@ TP@ TP@ TP@

TP@

TP28PAD~D TP29PAD~D TP30PAD~D TP31PAD~D

TP32PAD~D

4

UC1S

AG6

CFG_0

AE7

CFG_1

AG7

CFG_2

AD9

CFG_3

AE9

CFG_4

AB9

CFG_5

AJ6

CFG_6

AB7

CFG_7

V10

CFG_8

AJ5

CFG_9

Y10

CFG_10

AJ7

CFG_11

AB10

CFG_12

AL7

CFG_13

AL9

CFG_14

AJ9

CFG_15

V6

CFG_16

V7

CFG_17

Y6

CFG_18

Y7

RC249.9_0201_1%

1

1 1 1 1

1

CFG_RCOM

MBP2# MBP3#

TP_AV1

TP_AT2 TP_AT1 TP_AU1 TP_AU2

TP_AV2

AD6

T10

BJ11

BL10

AV1

AT2

AT1 AU1 AU2

AV2

DP3 DT2

AR10 AP10 BP36

BM36

J15

K15

C5 D4

T9 T7

T6

A5

CFG_19

CFG_RCOMP

BPM#0 BPM#1 BPM#2 BPM#3

RSVD_62 RSVD_63

RSVD_TP_17

RSVD_TP_18 RSVD_TP_20 RSVD_TP_19 RSVD_TP_21

RSVD_TP_22

RSVD_67 RSVD_68

RSVD_69 RSVD_71 RSVD_70 RSVD_72

VSS_430 VSS_431

SKTOCC# RSVD_77 RSVD_64

ICL-U_BGA1526

@

RESERVED SIGNALS

19 of 19

3

RSVD_TP_1 RSVD_TP_2

RSVD_57 RSVD_58

RSVD_TP_10 RSVD_TP_11

RSVD_79 RSVD_80

RSVD_TP_5 RSVD_TP_6

VSS_428 VSS_429

RSVD_55 RSVD_56

RSVD_65 RSVD_66

RSVD_59 RSVD_60

RSVD_TP_13 RSVD_TP_14

RSVD_TP_24 RSVD_TP_25

RSVD_TP_15 RSVD_TP_16

TP_3 TP_4

RSVD_TP_12

RSVD_TP_7 RSVD_TP_8

RSVD_TP_9

RSVD_TP_23

TP_1 TP_2

VSS_432

RSVD_TP_26

A47 B47

C1 E1

CT32 CV32

G15 F15

BW11 CA11

C16 A16

C2 A4

DP5 DR5

D14 E16

DV6 DW6

DP2 DP1

DW4 DV4

CM33 DB10

R1

DW3 DV3

DH49

DL8

DW47 DV47 DU47

P10

TP_A47 TP_B47

TP_C1 TP_E1

TP_CT32 TP_CV32

TP_G15 TP_F15

TP_BW11 TP_CA11

TP_DV6 TP_DW6

TP_DP2 TP_DP1

TP_DW4 TP_DV4

TP_CM33 TP_DB10

TP_R1

TP_DW3 TP_DV3

TP_DH49

TP_DL8

TP_DW47 TP_DV47

TP_P10

2

1

TP1

1

TP2

1

TP59 PAD~D

1

TP60 PAD~D

1

TP6

1

TP5

1

TP8 PAD~D

1

TP7 PAD~D

1

TP3 PAD~D

1

TP4 PAD~D

1

TP10

1

TP9

1

TP12

1

TP11

1

TP13

1

TP14

1

TP16

1

TP15

1

TP18

1

TP17 PAD~D

1

TP19 PAD~D

1

TP20

1

TP22

1

TP23

1

TP24

1

TP87

TP@ TP@

TP@

TP@ TP@

TP@

TP@ TP@

TP@

PAD~D PAD~D

PAD~D

PAD~D PAD~D

PAD~D

1

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

B B

A A

PAD~D

PAD~D PAD~D PAD~D

PAD~D

TP@ TP@ TP@

TP@

TP89

TP90 TP91 TP92

TP93 TP94 TP95

TP67

TP68

1

1 1 1

1

TP88

TP@

TP_N34 TP_AK10

TP_AH10 TP_BC10 TP_CH33

TP_AM10 TP_BH10 TP_J34

RSVD_L34

RSVD_M34

N34

AK10 BT36 AH10 BC10

CH33

CJ32

AM10

BH10

J34

Y11

L34

AJ11

CG32

CK33 BP41 AL11

BG11

AN11

M13 M34

DU42

DW42

D33

L13

K13

UC1R

RSVD_TP_28 RSVD_TP_29 RSVD_7 RSVD_TP_30 RSVD_TP_31 RSVD_TP_32

RSVD_12 RSVD_TP_33 RSVD_TP_34 RSVD_TP_27

RSVD_9 RSVD_10

RSVD_17 RSVD_21

RSVD_22 RSVD_20 RSVD_23 RSVD_24 RSVD_16 RSVD_18 RSVD_19

RSVD_42 RSVD_43 RSVD_44 RSVD_45 RSVD_47

ICL-U_BGA1526

@

RESERVED SIGNALS

RSVD_TP_35 RSVD_TP_36 RSVD_TP_37

RSVD_32 RSVD_33 RSVD_34

IST_TP_0

IST_TP_1 IST_TRIG_0 IST_TRIG_1

PCH_IST_TP_0 PCH_IST_TP_1

RSVD_27

RSVD_28

RSVD_35

RSVD_46

RSVD_48

RSVD_49

RSVD_50

RSVD_51

RSVD_52

RSVD_53

RSVD_54

RSVD_36

RSVD_37

RSVD_38

RSVD_39

RSVD_40

RSVD_41

DA11 CL32 CN32 CY35 DB37 DF37

BF11 BD11 BE10 BF10

CW33 CY32

CY37 CV37

G34 H34 DJ34 DK31 DK15 CP3 CP5 AN9 AN7 AF10 AE11 H5 D1 DJ40 DK40

TP_DA11 TP_CL32 TP_CN32

IST_TP_0 IST_TP_1 IST_TRIG_0 IST_TRIG_1

PCH_IST_TP_0 PCH_IST_TP_1

1

TP96

1

TP97

1

TP98

1

TP62

1

TP61

1

TP64

1

TP63

1

TP66

1

TP65

CLKIN_XTAL (52)

TP@ TP@ TP@

TP@ TP@ TP@ TP@

TP@ TP@

PAD~D PAD~D PAD~D

PAD~D PAD~D PAD~D PAD~D

PAD~D PAD~D

CLKIN_XTAL for Jefferson Peak reserved

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P018 - ICL-U(13/13)RSVD,MIPI60

LA-G172P

1

18 101Friday, May 24, 2019

1.0 (A00)

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P019 - Reserve

LA-G172P

1.0 (A00)

19 101Friday, May 24, 2019

1

19 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P020 - Reserve

LA-G172P

1.0 (A00)

20 101Friday, May 24, 2019

1

20 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P021 - Reserve

LA-G172P

1.0 (A00)

21 101Friday, May 24, 2019

1

21 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P022 - Reserve

LA-G172P

1.0 (A00)

22 101Friday, May 24, 2019

1

22 101Friday, May 24, 2019

5

4

3

2

1

Memory connection follow J72913-201 Rev 01_20181217

+VDDQ_MEM

D D

+1.1V_MEM

RD25

0_0201_5%@

1 2

DDR_A_ODTA

12

RD26

@

0_0201_5%

ODT PD reserved -- CRB P.83

+1.1V_MEM +1.1V_MEM

RD27

0_0201_5%@

1 2

DDR_A_ODTB DDR_B_ODTB

+1.8V_MEM

95mA

+1.1V_MEM

422mA

DDR_A_D2_4(7) DDR_A_D2_1(7) DDR_A_D2_3(7) DDR_A_D2_6(7) DDR_A_D2_7(7) DDR_A_D2_5(7) DDR_A_D2_2(7) DDR_A_D2_0(7) DDR_A_D3_0(7) DDR_A_D3_2(7) DDR_A_D3_1(7) DDR_A_D3_4(7) DDR_A_D3_3(7) DDR_A_D3_5(7) DDR_A_D3_6(7) DDR_A_D3_7(7)

DDR_A_DQS2(7) DDR_A_DQS#2(7)

DDR_A_DQS3(7) DDR_A_DQS#3(7)

12

RD28

@

0_0201_5%

C C

B B

ODT PD reserved -- CRB P.83

1 2

RD2 240_0201_1%

1 2

RD1 240_0201_1%

DDR_A_CA0(7) DDR_A_CA1(7) DDR_A_CA2(7) DDR_A_CA3(7) DDR_A_CA4(7) DDR_A_CA5(7)

F1

F12

G4 G9

T4 T9 U1

U12

A4 A9 F5 F8 H1 H5 H8

H12

K1

K3 K10 K12

N1

N3 N10 N12

R1

R5

R8 R12

U5

U8 AB4 AB9

H9HCNNNBUUMLHR-NLM_FBGA200

DDR_A_CA0 DDR_A_CA1 DDR_A_CA2 DDR_A_CA3 DDR_B_CA3 DDR_A_CA4 DDR_A_CA5

DDR_A_CA0 DDR_A_CA1 DDR_A_CA2 DDR_A_CA3 DDR_A_CA4 DDR_A_CA5

DDR_A_ODTA

DDR_A_ODTB

UD1C

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8

VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20 VDD2_21 VDD2_22 VDD2_23 VDD2_24

@

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

NC_1 NC_2 NC_3 NC_4 NC_5

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11 K5 K8 N5 N8

UD1 UD2

+1.8V_MEM

12

CD67

12

CD69

CD68

1U_0201_10V6M

+1.1V_MEM

12

CD70

1U_0201_10V6M

12

CD72

CD71

1U_0201_10V6M

12

CD74

CD73

1U_0201_10V6M

DDRA DDRB

UD1A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

+VDDQ_MEM

323mA

12

CD76

CD75

1U_0201_10V6M

+VDDQ_MEM

12

CK_ta

CK_ca

CK_tb

CK_cb

CKE0a

CKE1a

CKE0b

CKE1b

DMI0a DMI1a

DMI0b DMI1b

RESET

DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

DQS0_tb

DQS0_cb

DQS1_tb

DQS1_cb

A3

A10

C1 C5 C8

C12

D2 D4 D9

D11

E1 E5 E8

E12

G1 G3 G5

G8 G10 G12

J1

J3 J10 J12

K2 K4 K9

K11

N2

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD77

CD78

1U_0201_10V6M

DDR_A_CLK

J8

DDR_A_CLK#

J9

DDR_A_CLK

P8

DDR_A_CLK#

P9

DDR_A_CKE0

J4

DDR_A_CKE1

J5

DDR_A_CKE0

P4

DDR_A_CKE1

P5

DDR_A_CS#0

H4

CS0a

DDR_A_CS#1

H3

CS1a

DDR_A_CS#0

R4

CS0b

DDR_A_CS#1

R3

CS1b

C3 C10

Y3

SHORTEST PATH TO GND

Y10

DDR_DRAMRST#_R

T11

DVT1.2_03DVT1.2_03 DVT1.2_03 DVT1.2_03

AA2

DQ0b

Y2

DQ1b

V2

DQ2b

U2

DQ3b

U4

DQ4b

V4

DQ5b

Y4

DQ6b

AA4

DQ7b

AA11

DQ8b

Y11

DQ9b

V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

UD1B

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

12

CD80

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

1U_0201_10V6M

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29

12

CD79

1U_0201_10V6M

DDR_A_CLK (7) DDR_A_CLK# (7)

DDR_A_CKE0 (7)

DDR_A_CKE1 (7)

DDR_A_CS#0 (7)

DDR_A_CS#1 (7)

DDR_DRAMRST#_R (7,24)

DDR_A_D0_1 (7) DDR_A_D0_0 (7) DDR_A_D0_2 (7) DDR_A_D0_5 (7) DDR_A_D0_3 (7) DDR_A_D0_7 (7) DDR_A_D0_4 (7) DDR_A_D0_6 (7) DDR_A_D1_7 (7) DDR_A_D1_3 (7) DDR_A_D1_1 (7) DDR_A_D1_4 (7) DDR_A_D1_0 (7) DDR_A_D1_2 (7) DDR_A_D1_6 (7) DDR_A_D1_5 (7)

DDR_A_DQS0 (7)

DDR_A_DQS#0 (7)

DDR_A_DQS1 (7)

DDR_A_DQS#1 (7)

+1.1V_MEM

RD29

0_0201_5%@

1 2

DDR_B_ODTA

12

RD30 0_0201_5%

ODT PD reserved -- CRB P.84

DVT1_34 DVT1_34

1 2

12

RD31

0_0201_5%@

RD32 0_0201_5%

ODT PD reserved -- CRB P.84

+VDDQ_MEM

CD45

CD46

CD47

1

2

@EMI@

+VDDQ_MEM

1

2

@EMI@

CD27

1

12P_0201_50V8J

2

@EMI@

1

CD28

2.2P_0201_50V8B

2

@EMI@

CD48

1

12P_0201_50V8J

2

@EMI@

1

CD44

CD43

2.2P_0201_50V8B

2

@EMI@

+VDDQ_MEM

RD21 240_0201_1%

1 2

RD22 240_0201_1%

1 2

95mA

+1.1V_MEM

422mA

+1.8V_MEM

DDR_B_CA0 DDR_B_CA1 DDR_B_CA2

DDR_B_CA4 DDR_B_CA5

DDR_B_CA0 DDR_B_CA1 DDR_B_CA2 DDR_B_CA3 DDR_B_CA4 DDR_B_CA5

DDR_B_ODTA

DDR_B_ODTB

F1

F12

G4 G9 T4 T9 U1

U12

A4 A9 F5 F8 H1 H5 H8

H12

K1

K3 K10 K12

N1

N3

N10 N12

R1

R5

R8

R12

U5

U8

AB4 AB9

H9HCNNNBUUMLHR-NLM_FBGA200

DDR_B_CA0(7) DDR_B_CA1(7) DDR_B_CA2(7) DDR_B_CA3(7) DDR_B_CA4(7) DDR_B_CA5(7)

@

DDR_B_D0_4(7) DDR_B_D0_1(7)

@

DDR_B_D0_6(7) DDR_B_D0_5(7) DDR_B_D0_7(7) DDR_B_D0_3(7) DDR_B_D0_2(7) DDR_B_D0_0(7) DDR_B_D1_0(7) DDR_B_D1_2(7) DDR_B_D1_4(7) DDR_B_D1_1(7) DDR_B_D1_5(7) DDR_B_D1_3(7) DDR_B_D1_6(7) DDR_B_D1_7(7)

DDR_B_DQS0(7) DDR_B_DQS#0(7)

DDR_B_DQS1(7) DDR_B_DQS#1(7)

CD50

CD49

1

12P_0201_50V8J

2

1

CD65

2

CD91

1

12P_0201_50V8J

2

@EMI@

1

CD81

CD66

2.2P_0201_50V8B

2

@EMI@

UD2A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

UD2C

VDD1_1

VDDQ_1

VDD1_2

VDDQ_2

VDD1_3

VDDQ_3

VDD1_4

VDDQ_4

VDD1_5

VDDQ_5

VDD1_6

VDDQ_6

VDD1_7

VDDQ_7

VDD1_8

VDDQ_8 VDDQ_9

VDDQ_10

VDD2_1

VDDQ_11

VDD2_2

VDDQ_12

VDD2_3

VDDQ_13

VDD2_4

VDDQ_14

VDD2_5

VDDQ_15

VDD2_6

VDDQ_16

VDD2_7

VDDQ_17

VDD2_8

VDDQ_18

VDD2_9

VDDQ_19

VDD2_10

VDDQ_20 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20 VDD2_21 VDD2_22 VDD2_23 VDD2_24

@

+1.8V_MEM

12

CD51

1U_0201_10V6M

NC_1 NC_2 NC_3 NC_4 NC_5

DDR_B_CLK

J8

CK_ta

DDR_B_CLK#

J9

CK_ca

DDR_B_CLK

P8

CK_tb

DDR_B_CLK#

P9

CK_cb

DDR_B_CKE0

J4

CKE0a

CKE1a

CKE0b

CKE1b

RESET

DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

DQS0_tb

DQS0_cb

DQS1_tb

DQS1_cb

+VDDQ_MEM

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11 K5 K8 N5 N8

12

CD52

1U_0201_10V6M

323mA

+1.1V_MEM

12

CD54

CD53

1U_0201_10V6M

CS0a

CS1a

CS0b

CS1b

DMI0a DMI1a

DMI0b DMI1b

DQ0b DQ1b DQ2b DQ3b DQ4b DQ5b DQ6b DQ7b DQ8b DQ9b

12

CD55

1U_0201_10V6M

DDR_B_CKE1

J5

DDR_B_CKE0

P4

DDR_B_CKE1

P5

DDR_B_CS#0

H4

DDR_B_CS#1

H3

DDR_B_CS#0

R4

DDR_B_CS#1

R3

C3 C10

Y3 Y10

DDR_DRAMRST#_R

T11

AA2 Y2 V2 U2 U4 V4 Y4 AA4 AA11 Y11 V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

12

SHORTEST PATH TO GND

UD2B

A3

VSS_1

A10

VSS_2

C1

VSS_3

C5

VSS_4

C8

VSS_5

C12

VSS_6

D2

VSS_7

D4

VSS_8

D9

VSS_9

D11

VSS_10

E1

VSS_11

E5

VSS_12

E8

VSS_13

E12

VSS_14

G1

VSS_15

G3

VSS_16

G5

VSS_17

G8

VSS_18

G10

VSS_19

G12

VSS_20

J1

VSS_21

J3

VSS_22

J10

VSS_23

J12

VSS_24

K2

VSS_25

K4

VSS_26

K9

VSS_27

K11

VSS_28

N2

VSS_29

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD56

1U_0201_10V6M

CD57

1U_0201_10V6M

DDR_B_CLK (7) DDR_B_CLK# (7)

DDR_B_CKE0 (7)

DDR_B_CKE1 (7)

DDR_B_CS#0 (7)

DDR_B_CS#1 (7)

DDR_B_D3_6 (7) DDR_B_D3_2 (7) DDR_B_D3_4 (7) DDR_B_D3_5 (7) DDR_B_D3_3 (7) DDR_B_D3_1 (7) DDR_B_D3_0 (7) DDR_B_D3_7 (7) DDR_B_D2_7 (7) DDR_B_D2_3 (7) DDR_B_D2_2 (7) DDR_B_D2_1 (7) DDR_B_D2_4 (7) DDR_B_D2_0 (7) DDR_B_D2_5 (7) DDR_B_D2_6 (7)

DDR_B_DQS3 (7)

DDR_B_DQS#3 (7)

DDR_B_DQS2 (7)

DDR_B_DQS#2 (7)

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

12

CD58

1U_0201_10V6M

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

CD59

+VDDQ_MEM

12

CD60

1U_0201_10V6M

CD61

CD62

1U_0201_10V6M

12

CD64

CD63

1U_0201_10V6M

+1.8V_MEM

1

CD303

CD305

10U_0402_10V6M

2

A A

5

+1.1V_MEM

1

2

CD308

10U_0402_10V6M

1

CD306

10U_0402_10V6M

2

4

+VDDQ_MEM

1

2

CD89

1

CD90

10U_0402_10V6M

2

EMC CAPS

+1.8V_MEM

1

CD304

CD12

10U_0402_10V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.1V_MEM

1

CD7

CD307

10U_0402_10V6M

2

Compal Secret Data

2014/09/08 2013/10/28

2

Compal Secret Data

Deciphered Date

+VDDQ_MEM

1

2

CD87

1

CD88

10U_0402_10V6M

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P023 - LPDDR4/x Channel A/B

LA-G172P

1

23 101Friday, May 24, 2019

1.0 (A00)

5

4

3

2

1

Memory connection follow J72913-201 Rev 01_20181217

D D

+1.1V_MEM

RD33

0_0201_5%@

1 2

DDR_C_ODTA

12

RD34

@

0_0201_5%

ODT PD reserved -- CRB P.85

+1.1V_MEM

RD35

0_0201_5%@

1 2

DDR_C_ODTB

12

RD36

C C

0_0201_5%

@

ODT PD reserved -- CRB P.85

B B

+VDDQ_MEM +VDDQ_MEM

1 2

RD4 240_0201_1%

1 2

RD3 240_0201_1%

DDR_C_CA0(8) DDR_C_CA1(8) DDR_C_CA2(8) DDR_C_CA3(8) DDR_C_CA4(8) DDR_C_CA5(8)

DDR_C_CA0 DDR_C_CA1 DDR_C_CA2 DDR_C_CA3 DDR_C_CA4 DDR_C_CA5

DDR_C_ODTA

DDR_C_ODTB

DVT1.2_03 DVT1.2_03 DVT1.2_03 DVT1.2_03

DDR_C_D1_4(8) DDR_C_D1_1(8) DDR_C_D1_2(8) DDR_C_D1_0(8) DDR_C_D1_5(8) DDR_C_D1_7(8) DDR_C_D1_6(8) DDR_C_D1_3(8) DDR_C_D0_0(8) DDR_C_D0_2(8) DDR_C_D0_5(8) DDR_C_D0_6(8) DDR_C_D0_3(8) DDR_C_D0_7(8) DDR_C_D0_4(8) DDR_C_D0_1(8)

DDR_C_DQS1(8) DDR_C_DQS#1(8)

DDR_C_DQS0(8) DDR_C_DQS#0(8)

+1.8V_MEM

95mA

+1.1V_MEM

422mA

F1

F12

G4 G9 T4 T9 U1

U12

A4 A9 F5 F8 H1 H5 H8

H12

K1

K3 K10 K12

N1

N3 N10 N12

R1

R5

R8 R12

U5

U8 AB4 AB9

H9HCNNNBUUMLHR-NLM_FBGA200

UD3A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

UD3C

VDD1_1

VDDQ_1

VDD1_2

VDDQ_2

VDD1_3

VDDQ_3

VDD1_4

VDDQ_4

VDD1_5

VDDQ_5

VDD1_6

VDDQ_6

VDD1_7

VDDQ_7

VDD1_8

VDDQ_8 VDDQ_9

VDDQ_10

VDD2_1

VDDQ_11

VDD2_2

VDDQ_12

VDD2_3

VDDQ_13

VDD2_4

VDDQ_14

VDD2_5

VDDQ_15

VDD2_6

VDDQ_16

VDD2_7

VDDQ_17

VDD2_8

VDDQ_18

VDD2_9

VDDQ_19

VDD2_10

VDDQ_20 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20 VDD2_21 VDD2_22 VDD2_23 VDD2_24

@

NC_1 NC_2 NC_3 NC_4 NC_5

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11 K5 K8 N5 N8

+VDDQ_MEM

323mA

CK_ta

CK_ca

CK_tb

CK_cb

CKE0a

CKE1a

CKE0b

CKE1b

CS0a

CS1a

CS0b

CS1b

DMI0a DMI1a

DMI0b DMI1b

RESET

DQ0b DQ1b DQ2b DQ3b DQ4b DQ5b DQ6b DQ7b DQ8b

DQ9b DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

DQS0_tb DQS0_cb

DQS1_tb DQS1_cb

DDR_C_CLK

J8

DDR_C_CLK#

J9

DDR_C_CLK

P8

DDR_C_CLK#

P9

DDR_C_CKE0

J4

DDR_C_CKE1

J5

DDR_C_CKE0

P4

DDR_C_CKE1

P5

DDR_C_CS#0

H4

DDR_C_CS#1

H3

DDR_C_CS#0

R4

DDR_C_CS#1

R3

C3 C10

Y3 Y10

DDR_DRAMRST#_R DDR_DRAMRST#_R

T11

AA2 Y2 V2 U2 U4 V4 Y4 AA4 AA11 Y11 V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

A3

A10

C1 C5 C8

C12

D2 D4 D9

D11

E1 E5 E8

E12

G1 G3 G5

G8 G10 G12

J1

J3 J10 J12

K2 K4 K9

K11

N2

H9HCNNNBUUMLHR-NLM_FBGA200

UD3B

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29

@

DDR_C_CLK (8) DDR_C_CLK# (8)

DDR_C_CKE0 (8)

DDR_C_CKE1 (8)

DDR_C_CS#0 (8)

DDR_C_CS#1 (8)

DDR_DRAMRST#_R (7,23)

DDR_C_D3_6 (8) DDR_C_D3_5 (8) DDR_C_D3_1 (8) DDR_C_D3_0 (8) DDR_C_D3_4 (8) DDR_C_D3_2 (8) DDR_C_D3_7 (8) DDR_C_D3_3 (8) DDR_C_D2_7 (8) DDR_C_D2_3 (8) DDR_C_D2_1 (8) DDR_C_D2_5 (8) DDR_C_D2_0 (8) DDR_C_D2_6 (8) DDR_C_D2_4 (8) DDR_C_D2_2 (8)

DDR_C_DQS3 (8)

DDR_C_DQS#3 (8)

DDR_C_DQS2 (8)

DDR_C_DQS#2 (8)

N4

VSS_30

N9

VSS_31

N11

VSS_32

P1

VSS_33

P3

VSS_34

P10

VSS_35

P12

VSS_36

T1

VSS_37

T3

VSS_38

T5

VSS_39

T8

VSS_40

T10

VSS_41

T12

VSS_42

V1

VSS_43

V5

VSS_44

V8

VSS_45

V12

VSS_46

W2

VSS_47

W4

VSS_48

W9

VSS_49

W11

VSS_50

Y1

VSS_51

Y5

VSS_52

Y8

VSS_53

Y12

VSS_54

AB3

VSS_55

AB5

VSS_56

AB8

VSS_57

AB10

VSS_58

+1.1V_MEM

RD37

0_0201_5%@

1 2

DDR_D_ODTA

12

RD38

@

0_0201_5%

ODT PD reserved -- CRB P.86

+1.1V_MEM

RD39

0_0201_5%@

1 2

DDR_D_ODTB

12

RD40

@

0_0201_5%

ODT PD reserved -- CRB P.86

DDR_D_D1_3(8) DDR_D_D1_6(8) DDR_D_D1_7(8) DDR_D_D1_5(8) DDR_D_D1_0(8) DDR_D_D1_4(8) DDR_D_D1_1(8) DDR_D_D1_2(8) DDR_D_D0_2(8) DDR_D_D0_0(8) DDR_D_D0_5(8) DDR_D_D0_6(8) DDR_D_D0_7(8) DDR_D_D0_3(8) DDR_D_D0_4(8) DDR_D_D0_1(8)

DDR_D_DQS#1(8)

DDR_D_DQS0(8) DDR_D_DQS#0(8)

+1.8V_MEM

95mA

+1.1V_MEM

422mA

DDR_D_CA0(8) DDR_D_CA1(8) DDR_D_CA2(8) DDR_D_CA3(8) DDR_D_CA4(8) DDR_D_CA5(8)

RD23 240_0201_1%

1 2

RD24 240_0201_1%

1 2

DDR_D_CA0 DDR_D_CKE0 DDR_D_CA1 DDR_D_CA2 DDR_D_CA3 DDR_D_CA4 DDR_D_CA5

DDR_D_CA0 DDR_D_CA1 DDR_D_CA2 DDR_D_CA3 DDR_D_CA4 DDR_D_CA5

DDR_D_ODTA

DDR_D_ODTB

UD4C

F1

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8

VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20 VDD2_21 VDD2_22 VDD2_23 VDD2_24

@

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

NC_1 NC_2 NC_3 NC_4 NC_5

F12

G4 G9

T4 T9

U1

U12

A4 A9 F5

F8 H1 H5 H8

H12

K1

K3

K10 K12

N1 N3

N10 N12

R1 R5 R8

R12

U5 U8

AB4 AB9

H9HCNNNBUUMLHR-NLM_FBGA200

DDRDDDRC

UD4A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

+VDDQ_MEM

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11 K5 K8 N5 N8

323mA

CK_ta

CK_ca

CK_tb

CK_cb

CKE0a

CKE1a

CKE0b

CKE1b

DMI0a DMI1a

DMI0b DMI1b

RESET

DQ0b DQ1b DQ2b DQ3b DQ4b DQ5b DQ6b DQ7b DQ8b

DQ9b DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

DQS0_tb

DQS0_cb

DQS1_tb

DQS1_cb

A10

C1

C5

C8 C12

D2

D4

D9 D11

E12

G1

G3

G5

G8 G10 G12

J10 J12

K11

N2

H9HCNNNBUUMLHR-NLM_FBGA200

CS0a

CS1a

CS0b

CS1b

A3

E1 E5 E8

J1 J3

K2 K4 K9

UD4B

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29

@

J9

P8 P9

J4

J5

P4

P5

H4

H3

R4

R3

C3 C10

Y3 Y10

T11

AA2 Y2 V2 U2 U4 V4 Y4 AA4 AA11 Y11 V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

DDR_D_CLK#

DDR_D_CLK DDR_D_CLK#

DDR_D_CKE1

DDR_D_CKE0

DDR_D_CKE1

DDR_D_CS#0

DDR_D_CS#1

DDR_D_CS#0

DDR_D_CS#1

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

DDR_D_CLK

J8

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

DDR_D_CLK (8) DDR_D_CLK# (8)

DDR_D_CKE0 (8)

DDR_D_CKE1 (8)

DDR_D_CS#0 (8)

DDR_D_CS#1 (8)

DVT1_34DVT1_34

DDR_D_D3_6 (8) DDR_D_D3_7 (8) DDR_D_D3_2 (8) DDR_D_D3_0 (8) DDR_D_D3_1 (8) DDR_D_D3_4 (8) DDR_D_D3_5 (8) DDR_D_D3_3 (8) DDR_D_D2_1 (8) DDR_D_D2_4 (8) DDR_D_D2_3 (8) DDR_D_D2_5 (8) DDR_D_D2_7 (8) DDR_D_D2_6 (8) DDR_D_D2_0 (8) DDR_D_D2_2 (8)

DDR_D_DQS3 (8)DDR_D_DQS1(8)

DDR_D_DQS#3 (8)

DDR_D_DQS2 (8)

DDR_D_DQS#2 (8)

UD4UD3

12

Issued Date

CD16

1U_0201_10V6M

+1.1V_MEM+1.8V_MEM

12

+1.1V_MEM

1

2

+VDDQ_MEM

12

CD17

CD18

1U_0201_10V6M

1

CD3

CD4

10U_0402_10V6M

2

2014/09/08 2013/10/28

2

12

CD19

CD20

1U_0201_10V6M

Compal Secret Data

12

CD21

1U_0201_10V6M

Deciphered Date

CD22

1U_0201_10V6M

+VDDQ_MEM

12

CD24

CD23

1U_0201_10V6M

1

CD83

CD84

10U_0402_10V6M

2

12

CD26

CD25

1U_0201_10V6M

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P024 - LPDDR4/x Channel C/D

LA-G172P

1

24 101Friday, May 24, 2019

1.0 (A00)

+1.8V_MEM

12

CD30

CD29

1U_0201_10V6M

1

CD11

CD10

10U_0402_10V6M

2

A A

5

12

CD32

CD31

1U_0201_10V6M

+1.1V_MEM+1.8V_MEM

12

CD33

1U_0201_10V6M

1

CD5

10U_0402_10V6M

2

12

CD34

CD35

1U_0201_10V6M

1

CD6

10U_0402_10V6M

2

4

12

CD37

CD36

1U_0201_10V6M

+VDDQ_MEM+1.1V_MEM

12

CD38

1U_0201_10V6M

+VDDQ_MEM

12

CD39

CD40

1U_0201_10V6M

1

CD86

CD85

10U_0402_10V6M

2

12

CD42

CD41

1U_0201_10V6M

3

12

CD13

+1.8V_MEM

1U_0201_10V6M

1

CD8

10U_0402_10V6M

2

12

CD15

CD14

1U_0201_10V6M

1

CD9

10U_0402_10V6M

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

1 1

B

C

D

E

RD41 0_0201_5%LPDDR4X@

MEM_PG(58)

2 2

1 2

RD42 0_0201_5%@

1 2

1.1V_MEM_EN (78,86)

0.6V_VDDQ_PG (87)

1.1V_MEM_PG (86)

0.6V_VDDQ_EN

+0.6V_VDDQP:LPDDR4X

RD43 0_0201_5%LPDDR4X@

1 2

0.6V_VDDQ_EN

RD44 0_0201_5%LPDDR4@

1 2

+0.6V_VDDQ

+1.1V_MEM:LPDDR4

LPDDR4X@

RD45

0_1206_5%

1 2

+1.1V_MEM

LPDDR4@

RD46

0_1206_5%

1 2

+VDDQ_MEM

RD400

@

1 2

0_0402_5%

12

RD300

CD309

1M_0201_5%

@

0.1U_0402_25V6

0.6V_VDDQ_EN_P (87)

RD43 RD45 RD44 RD46 LPDDR4(1.1V) : @ @ LPDDR4X(1.1v&0.6V): @ @

3 3

4 4

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

A

B

2014/09/08 2013/10/28

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

P025 - LPDDR4&4X BOM OPTION

1.0 (A00)

LA-G172P

25 101Friday, May 24, 2019

E

25 101Friday, May 24, 2019

1.0 (A00)

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P026 - Reserve

LA-G172P

1.0 (A00)

26 101Friday, May 24, 2019

1

26 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P027 - Reserve

LA-G172P

1.0 (A00)

27 101Friday, May 24, 2019

1

27 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P028 - Reserve

LA-G172P

1.0 (A00)

28 101Friday, May 24, 2019

1

28 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P029 - Reserve

LA-G172P

1.0 (A00)

29 101Friday, May 24, 2019

1

29 101Friday, May 24, 2019

5

D D

4

3

2

1

C C

B B

A A

Security Classification

2014/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2014/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P030 - Reserve

LA-G172P

1.0 (A00)

30 101Friday, May 24, 2019

1

30 101Friday, May 24, 2019

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