Dell XPS 11 Schematics
A
B
C
D
E
MODEL NAME :
PCB NO :
VAZ90
LA-A161P
BOM P/N :
revision:
1 1
A00
Compal Confidential
ZZZ
ZZZ
MB_PCB
2 2
3 3
MB_PCB
Schematic Document
Jarama (Haswell Y-series)
@ : Nopop Component
CONN@ : Connector Component
vPRO@ : SPI ROM (8M+4M) Component
nvPRO@ : SPI ROM (8M) Component
CS@ : Connected Standby Component
Non-CS@ : Non-Connected Standby Component
2013-08-14
Rev: A00
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P01-Cover Page
P01-Cover Page
P01-Cover Page
LA-A161P
LA-A161P
LA-A161P
E
1 49Wednesday, August 14, 2013
1 49Wednesday, August 14, 2013
1 49Wednesday, August 14, 2013
X02
X02
X02
A
B
C
D
E
Channel A
Memory Bus (DDR3L-RS)
eDP Panel
1 1
P.19
Touch Screen
P.17
eDP 1.3* 4lan
USB2.0
Dual Channel
DDR3L-RS 1600 MHz
SATA3.0
DDR3L-RS 4Gb (x16) *4
Channel B
DDR3L-RS 4Gb (x16) * 4
Mini Card (Full)
# mSATA
P.12, 13
P.14, 15
P.26
Intel
HDMI Conn
P.18
LEVEL SHIFT
P.18
HDMI 1.4a
Haswell Y-Series
BGA 1168 Balls
SPI
SPI ROM
vPRO: (8M+4M)
non vPRO (8M)
P.07
7.5W SDP
P.24
P.26
USB3.0/USB2.0
USB3.0/USB2.0
USB2.0
I2C
USB2.0
SMLink
PS2
TO EC
I2C
PCIE *1
Card Reader
RTS5249
P.23
3 in 1
Socket
P.23
USB2.0
DP 4 lan
PCIE *2
UART
SDIO
level shift
USB2.0
PCIE
PCM
HDA
Page 5, 6, 7, 8, 9, 10, 11P.19
Audio DSP
ALC5505
P.20
level shift
HDA
NGFF Slot A-DP
WiGig/ Tri-Band
802.11abgn/ac/ad, BT3+LE
NGFF Slot A-SD
WLAN
BT
802.11abgn/ac, BT4.0+LE
Audio Codec
ALC3661
P.21
P.25
P.25
Global headset
P.21
USB 3.0 Conn.
( USB Charger Port )
USB 3.0 Conn.
2 2
( USB Charger Port )
Digital Camera
ALS+CLS
e-Compass +
Accelerometer
TCS3472
P.23
P.23
P.17
I2C
TO EC
Sensor HUB
STM32F103RC
DE303DLHCTR
Gyro Sensor
TX3GD20TR
3 3
Daughter Board
NFC Module
Conn
Touch Pad
TPM
AT97SC3204
P.24
ENE KB9012BF
FAN conn.
RTC
4 4
DC/DC Interface CKT.
Power Circuit DC/DC
A
P.32
P.31
P.30
Keyboard BL
Resistance Keyboard
P.31
B
KSI/KSO
Touch Controller
Capacitance Keyboard
LPC Bus
I2C
1 st Digital MIC
P.33
P.31
P.31
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2nd Array MIC
PWM
I2C
SMBus
2011/02/23 2013/10/28
2011/02/23 2013/10/28
2011/02/23 2013/10/28
P.19
P.19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Digital MIC Switch
Panel
Win8 KEY
P.19
Audio AMP
APA2605
P.22
Title
Title
Title
P02-Block Diagram
P02-Block Diagram
P02-Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA-A161P
LA-A161P
LA-A161P
Date: Sheet of
Date: Sheet of
Date: Sheet of
Int. Speaker
P.22P.22
Sensor HUB
AUDIO Codec GPIO
PCH GPIO
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2 49Wednesday, August 14, 2013
2 49Wednesday, August 14, 2013
E
2 49Wednesday, August 14, 2013
A00
A00
A00
A
B
C
D
E
Compal Confidential
Project Code : VAZ90
File Name :
1 1
2 2
3 3
4 4
LA-A161P
LA-A161P
LA-A161P
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P03-DaughterB block diagram
P03-DaughterB block diagram
P03-DaughterB block diagram
3 49Wednesday, August 14, 2013
3 49Wednesday, August 14, 2013
E
3 49Wednesday, August 14, 2013
A00
A00
A00
A
Board ID Table for AD channel
Ra 100K +/- 1%
SMBUS Control Table
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_DA4
1 1
PCH_SML0CLK PCH
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_SMBCLK
PCH_SMBDATA
CL_DATA
3.3V +/- 5%Vcc
VRbBoard ID
AD_BID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC
SOURCE
KB9012
KB9012
KB9012EC_SMB_CK4
NGFF BATT
min
V V
AD_BID
typV
NFCCharger
XDP
V
AD_BID
max
EC AD3
ALS
Panel T-COM
V
V
V
PCH
PCH
PCHCL_CLK
V
V
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Keyboard
V
PCB Revision
Non- VPRO 0.1 (SSI)
VPRO 0.2 (PT)
VPRO 0.3 (ST)
VPRO 1.0 (XB)
VPRO 0.1 (SSI)
Non- VPRO 0.2 (PT)
Non- VPRO 0.3 (ST)
Non- VPRO 1.0 (XB)
Link
PCH
USB
Port
Mapping
PCH
DDI
Port
Mapping
USB PORT#
0
1
2
3
4
5
6
DESTINATION
External USB3
External USB3
NGFF CARD WLAN
Touch Panel
Camera
Sensors HUB
NGFF(WiGig)
7
DDI PORT# DESTINATION
1
2
NGFF(WiGig)
HDMI
CLK
CLKOUT_PCIE1
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4
CLKOUT_PCIE5
DESTINATIONDIFFERENTIAL
WiGig
Card Reader
NGFF CARD WLAN
WiGig
FLEX CLOCKS DESTINATION
CLKOUT_LPC_0 TPM , EC LPC
CLKOUT_LPC_1
LPC Debug
SATA PCI EXPRESS
SATA0
SATA1
SATA2
SATA3
DESTINATION
m-SATA
Lane 1CLKOUT_PCIE0
Lane 2
Lane 3
Lane 4
NGFF(WiGig)
CardReader
NGFF(WLAN)
NGFF(WiGig)
Lane 5
Lane 6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
A
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DESTINATION
Symbol Note :
: means Digital Ground
: means Analog Ground
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P04-Notes List
P04-Notes List
P04-Notes List
LA-A161P
LA-A161P
LA-A161P
4 49Wednesday, August 14, 2013
4 49Wednesday, August 14, 2013
4 49Wednesday, August 14, 2013
A00
A00
A00
5
4
HSW_ULT_DDR3L
UCPU1A
UCPU1A
HSW_ULT_DDR3L
3
2
1
EDP_BKLCTL
ENBKL
PCH_ENVDD
MPCIE_RST#
TPM_IRQ#
PCI_PIRQC#
PCI_PIRQD#
TP_INT#
Sensor_RST#
AUDIO_IRQ#
DDR_PG_CNTL
AU60
AV60
AU61
AV15
AV61
D61
K61
N62
K63
C61
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
UCPU1B
UCPU1B
PROC_DETECT
CATERR
PECI
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
UCPU1I
UCPU1I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
eDP SIDEBAND
eDP SIDEBAND
PCIE
PCIE
THERMAL
THERMAL
DDR3L
DDR3L
MISC
MISC
PWR
PWR
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSW_ULT_DDR3L
2 OF 19
2 OF 19
1 OF 19
1 OF 19
9 OF 19
9 OF 19
EDPDDI
EDPDDI
DISPLAY
DISPLAY
JTAG
JTAG
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
PCH_DP_N025
PCH_DP_P025
PCH_DP_N125
PCH_DP_P125
ENBKL19
PCH_ENVDD19,29,30
MPCIE_RST#23,25
@
TP_INT#32
TS_RST#19
NGFF_WAKE#25
Sensor_RST#24
T2@T2@
H_PECI33
1 2
RC41 56_0402_5%RC41 56_0402_5%
12
RC55200_0402_1%~D RC55200_0402_1%~D
12
RC58121_0402_1% RC58121_0402_1%
12
RC60100_0402_1%~D RC60100_0402_1%~D
1 2
UC1
UC1
5
VCC
4
Y
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
PCH_DP_N225
PCH_DP_P225
PCH_DP_N325
PCH_DP_P325
PCH_DDI2_N018
PCH_DDI2_P018
PCH_DDI2_N118
PCH_DDI2_P118
PCH_DDI2_N218
PCH_DDI2_P218
PCH_DDI2_N318
PCH_DDI2_P318
T123@T123
NC
A
NGFF_WAKE#
H_CATERR#
H_PROCHOT#_RH_PROCHOT#
H_CPUPWRGD_R
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_DRAMRST#
DDR_PG_CNTL
1
2
3
NGFF(WiGig)
D D
1 2
PCH_INV_PWM19
RH123 100K_0402_5%~D@RH123 100K_0402_5%~D@
RH158 100K_0402_5%~D@RH158 100K_0402_5%~D@
RH300 1M_0402_5%~DRH300 1M_0402_5%~D
RH387 1M_0402_5%~D@RH387 1M_0402_5%~D@
+3VS
RH281 2.2K_0402_5%~DRH281 2.2K_0402_5%~D
RH282 2.2K_0402_5%~DRH282 2.2K_0402_5%~D
RH388 2.2K_0402_5%~DRH388 2.2K_0402_5%~D
RH389 2.2K_0402_5%~DRH389 2.2K_0402_5%~D
RH380 100K_0402_5%~D@RH380 100K_0402_5%~D@
C C
B B
RH455 10K_0402_5%~DRH455 10K_0402_5%~D
RH456 10K_0402_5%~DRH456 10K_0402_5%~D
RH463 10K_0402_5%~DRH463 10K_0402_5%~D
RH396 10K_0402_5%~D@RH396 10K_0402_5%~D@
RH397 10K_0402_5%~DRH397 10K_0402_5%~D
RH452 10K_0402_5%~DRH452 10K_0402_5%~D
RH381 100K_0402_5%~DRH381 100K_0402_5%~D
Avoid stub in the PWRGD path
while placing resistors RC44 & RC53
RC147 0_0402_5%~D@ RC147 0_0402_5%~D@
RC146 0_0402_5%~D
RC146 0_0402_5%~D
@
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RC44 10K_0402_5%~DRC44 10K_0402_5%~D
H_CPUPWRGD_R
12
ENBKL
PCH_ENVDD
PCH_DP_HPD
PCH_HDMI_HPD
PCH_DP_CLK
PCH_DP_DAT
PCH_HDMI_CLK
PCH_HDMI_DAT
TP_INT#
PCI_PIRQC#
PCI_PIRQD#
TPM_IRQ#
AUDIO_IRQ#
NGFF_WAKE#
Sensor_RST#
MPCIE_RST#
H_PROCHOT#33,35
SM_PG_CTRL42
EDP_BKLCTL
EDP_DISP
HDMI
+1.05VS_VCCST
RC43
RC43
62_0402_5%
62_0402_5%
1 2
Width 15 mils, Spacing 25 mils, Length < 500 mil
DDR3 Compensation Signals
+3VS +1.35V_DDR
12
RC159
RC159
220K_0402_5%~D
220K_0402_5%~D
12
@
@
RC161
RC161
2M_0402_5%
2M_0402_5%
CC240 0.1U _0402_10V7K~DCC240 0.1U _0402_10V7K~D
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
D20
A43
Width 20 mils, Spacing 25 mils,
Length < 100 mil
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
J62
K62
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
eDP_TXN_P0 19
eDP_TXP_P0 19
eDP_TXN_P1 19
eDP_TXP_P1 19
eDP_TXN_P2 19
eDP_TXP_P2 19
eDP_TXN_P3 19
eDP_TXP_P3 19
eDP_AUXN 19
eDP_AUXP 19
+EDP_COM
EDP_DISP
PCH_DP_CLK
PCH_DP_DAT
PCH_HDMI_CLK
PCH_HDMI_DAT
PCH_DP_HPD
PCH_HDMI_HPD
CPU_eDP_HPD#
XDP_PRDY#
XDP_PREQ#
CPU_XDP_TCK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
closed MCP 1000 mils
XDP_PRDY#
XDP_PREQ#
CPU_XDP_TCK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
1 2
RC36 24.9_0402_1%RC36 24.9_0402_1%
RC158 0_0402_5%~D@ RC158 0_0402_5%~D@
T226@T226@
T227@T227@
T228@T228@
T229@T229@
T230@T230@
T231@T231@
12
PCH_HDMI_CLK 18
PCH_HDMI_DAT 18
PCH_DP_AUXN 25
PCH_DP_AUXP 25
PCH_DP_HPD 25
PCH_HDMI_HPD 18
XDP_PRDY# 17
XDP_PREQ# 17
CPU_XDP_TCK 17
CPU_XDP_TMS 17
CPU_XDP_TRST# 17
CPU_XDP_TDI 17
CPU_XDP_TDO 17
XDP_BPM0# 17
XDP_BPM1# 17
T263TP@ T263TP@
T264TP@ T264TP@
T265TP@ T265TP@
T266TP@ T266TP@
T267TP@ T267TP@
T268TP@ T268TP@
T269TP@ T269TP@
+VCCIOA_OUT
CPU_eDP_HPD#
PU/PD for JTAG signals
CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TCK
CPU_XDP_TRST#
Stuffed : Dual TCK
unstuffed : Singel TCK
Stuffed : Single & Dual TCK
S
S
@
@
DII-DMN65D8LW-7~D
DII-DMN65D8LW-7~D
RC148
@RC148
@
1 2
12
0_0402_5%~D
0_0402_5%~D
RC160
RC160
100K_0402_5%~D
100K_0402_5%~D
1 2
1 2
1 2
1 2
1 2
+5VS
G
G
QC5
QC5
2
13
D
D
eDP_HPD 19
12
@
@
RC138
RC138
100K_0402_5%~D
100K_0402_5%~D
+1.05VS_VCCST
RC4551_0402_5% @RC4551_0402_5% @
RC4651_0402_5% @RC4651_0402_5% @
RC4851_0402_5% RC4851_0402_5%
R1d
RC5251_0402_5% RC5251_0402_5%
R2
RC5451_0402_5% @RC5451_0402_5% @
R9
+1.35V_DDR
A A
H_DRAMRST#
5
1 2
RC162 0_0402_5%~D@ RC162 0_0402_5%~D@
12
RC75
RC75
470_0402_5%~D
470_0402_5%~D
DDR3_DRAMRST# 12,13,14,15
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P05-MCP(1/7) DDI,EDP,PM,XDP
P05-MCP(1/7) DDI,EDP,PM,XDP
P05-MCP(1/7) DDI,EDP,PM,XDP
LA-A161P
LA-A161P
LA-A161P
1
5 49Wednesday, August 14, 2013
5 49Wednesday, August 14, 2013
5 49Wednesday, August 14, 2013
A00
A00
A00
5
D D
HSW_ULT_DDR3L
UCPU1C
DDR_A_D[0..63]12,13
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UCPU1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HSW_ULT_DDR3L
DDR CHANNEL A
DDR CHANNEL A
4
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
DDR_A_MA0
AY37
DDR_A_MA1
AR38
DDR_A_MA2
AP36
DDR_A_MA3
AU39
DDR_A_MA4
AR36
DDR_A_MA5
AV40
DDR_A_MA6
AW39
DDR_A_MA7
AY39
DDR_A_MA8
AU40
DDR_A_MA9
AP35
DDR_A_MA10
AW41
DDR_A_MA11
AU41
DDR_A_MA12
AR35
DDR_A_MA13
AV42
DDR_A_MA14
AU42
DDR_A_MA15
AJ61
DDR_A_DQS#0
AN62
DDR_A_DQS#1
AM58
DDR_A_DQS#2
AM55
DDR_A_DQS#3
AV57
DDR_A_DQS#4
AV53
DDR_A_DQS#5
AL43
DDR_A_DQS#6
AL48
DDR_A_DQS#7
AJ62
DDR_A_DQS0
AN61
DDR_A_DQS1
AN58
DDR_A_DQS2
AN55
DDR_A_DQS3
AW57
DDR_A_DQS4
AW53
DDR_A_DQS5
AL42
DDR_A_DQS6
AL49
DDR_A_DQS7
AP49
AR51
AP51
10 mil trace width
M_CLK_A_DDR#0 12,13,16
M_CLK_A_DDR0 12,13,16
DDR_A_CKE0 12,13,16
DDR_A_CKE1 12,13,16
DDR_A_CS0# 12,13,16
DDR_A_CS1# 12,13,16
DDR_A_RAS# 12,13,16
DDR_A_WE# 12,13,16
DDR_A_CAS# 12,13,16
DDR_A_BS0 12,13,16
DDR_A_BS1 12,13,16
DDR_A_BS2 12,13,16
DDR_A_MA[0..15] 12, 13,16
DDR_A_DQS#[0..7] 12,13
DDR_A_DQS[0..7] 12,13
V_DDR_REF_CA 16
V_DDR_REFA_R 16
V_DDR_REFB_R 16
3
UCPU1D
DDR_B_D[0..63]14,15
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UCPU1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
2
HSW_ULT_DDR3L
HSW_ULT_DDR3L
AM38
SB_CK#0
AN38
SB_CK0
AK38
SB_CK#1
AL38
SB_CK1
AY49
SB_CKE0
AU50
SB_CKE1
AW49
SB_CKE2
AV50
SB_CKE3
AM32
SB_CS#0
AK32
SB_CS#1
AL32
SB_ODT0
AM35
SB_RAS
AK35
SB_WE
AM33
SB_CAS
AL35
SB_BA0
AM36
SB_BA1
AU49
SB_BA2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR CHANNEL B
DDR CHANNEL B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
1
M_CLK_B_DDR#0 14,15,16
M_CLK_B_DDR0 14,15,16
DDR_B_CKE0 14,15,16
DDR_B_CKE1 14,15,16
DDR_B_CS0# 14,15,16
DDR_B_CS1# 14,15,16
DDR_B_RAS# 14,15,16
DDR_B_WE# 14,15,16
DDR_B_CAS# 14,15,16
DDR_B_BS0 14,15,16
DDR_B_BS1 14,15,16
DDR_B_BS2 14,15,16
DDR_B_MA[0..15] 14,15,16
DDR_B_DQS#[0..7] 14,15
DDR_B_DQS[0..7] 14,15
3 OF 19
3 OF 19
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4 OF 19
4 OF 19
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
P06-MCP(2/7) DDRIII
P06-MCP(2/7) DDRIII
P06-MCP(2/7) DDRIII
LA-A161P
LA-A161P
LA-A161P
1
A00
A00
6 49Wednesday, August 14, 2013
6 49Wednesday, August 14, 2013
6 49Wednesday, August 14, 2013
A00
5
12
CH2 15P_0402_50V8J~DCH2 15P_0402_50V8J~D
YH1
32.768KHZ_12.5PF_9H03200031
32.768KHZ_12.5PF_9H03200031
D D
+RTCVCC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
RH25 20K_0402_5%~DRH25 20K_0402_5%~D
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+RTCVCC
C C
PCH JTAG
+1.05V_M
R4
R3d
R5
R8
R6
+3.3V_M
vPRO:SPI ROM (8M+4M)
B B
non vPRO:SPI ROM (8M)
SPI_SO_ROM
SPI_IO2_ROM
SPI_SI_ROM
PCH_SPI_CS#
SPI_SO_ROM
SPI_CLK32 PCH_SPI_CLK
SPI_DIN32
SPI_PCH_DO2_32
SPI_DO32
A A
SPI_PCH_DO3_32
YH1
12
CH3
CH3
15P_0402_50V8J~D
15P_0402_50V8J~D
far away hot spot
1
CH4
CH4
2
1
CH5
CH5
2
1 2
RH31 330K_0402_5%~DRH31 330K_0402_5%~D
1 2
RH34 330K_0402_5%~D@RH34 330K_0402_5%~D@
INTVRMEN
H：Integrated VRM enable
*
L：Integrated VRM disable
Stuffed : Single & Dual TCK
1 2
RH40 51_0402_5%RH40 51_0402_5%
1 2
RH445 51_0402_5%RH445 51_0402_5%
1 2
RH39 51_0402_5%RH39 51_0402_5%
1 2
RH375 1K_0402_5%~D@ RH375 1K_0402_5%~D@
1 2
RH53 51_0402_5%@RH53 51_0402_5%@
1 2
RH54 1K_0402_5%~DRH54 1K_0402_5%~D
1 2
RH56 1K_0402_5%~DRH56 1K_0402_5%~D
Closed to UCPU1
RH258 33_0402_5%~DvPRO@ RH258 33_0402_5%~DvPRO@
vPRO@ RP4
vPRO@
SPI ROM ( 8MByte )
ROM is Quad SPI
U48
U48
1
/CS
2
DO(IO1)
3
/WP(IO2 )
GND4DI(IO0)
W25Q64FVSSIQ_SO8
W25Q64FVSSIQ_SO8
RH256 33_0402_5%~DvPRO@ RH256 33_0402_5%~DvPRO@
vPRO@ RP5
vPRO@
PCH_RTCX1
12
12
RH2
RH2
10M_0402_5%
10M_0402_5%
PCH_RTCX2
CMOS
12
SP@
SP@
CLRP1
CLRP1
SHORT PADS
SHORT PADS
PCH_RTCRST#
PCH_SRTCRST#
12
SP@
SP@
CLRP2
CLRP2
SHORT PADS
SHORT PADS
ME CMOS
CLP1 & CLP2 place near DIMM
PCH_INTVRMEN
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
PCH_JTAG_TCK
PCH_SPI_IO2
PCH_SPI_IO3
1 2
RP4
1 8
2 7
3 6
4 5
33_8P4R_5%
33_8P4R_5%
8
VCC
7
/HOLD(IO3)
6
CLK
5
1 2
RP5
1 8
2 7
3 6
4 5
33_8P4R_5%
33_8P4R_5%
@EMI@ MC96
@EMI@
22P_0402_50V8J~D
22P_0402_50V8J~D
Reserve for EMI please close to UCPU1E
PCH_SPI_CLKSPI_CLK_ROM
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_SI
PCH_SPI_IO3SPI_IO3_ROM
SPI_IO3_ROM
SPI_CLK_ROMSPI_IO2_ROM
SPI_SI_ROM
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_SI
PCH_SPI_IO3
HDA_BITCLK_AUDIO20
HDA_RST_AUDIO#20
HDA_SYNC_AUDIO20
HDA_SDOUT_AUDIO20
MC96
12
HDA_SDO33
From EC, for enable
ME code programing
+3V_PCH
0312-45
CardReader
CLK_REQ2#25
+3.3V_M
1
CH6
CH6
.1U_0402_16V7K~D
.1U_0402_16V7K~D
2
HDA_BIT_CLK
WiGig
WLAN
WiGig
+RTCVCC
Q351
Q351
DII-DMN65D8LW-7~D
DII-DMN65D8LW-7~D
@RH410
@
1 2
0_0402_5%~D
0_0402_5%~D
DII-DMN65D8LW-7~D
DII-DMN65D8LW-7~D
Q346
Q346
RP4
RP4
15_0804_8P4R_5%
15_0804_8P4R_5%
SD300001P00
SD300001P00
nvPRO@
nvPRO@
SPI ROM ( 4MByte )
ROM is Quad SPI
PCH_SPI_CS1#
SPI_DIN32
SPI_PCH_DO2_32
U2
vPRO@U2
vPRO@
1
/CS
2
DO/IO1
3
/WP/IO2
GND4DI/IO0
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
/HOLD/IO3
5
8
VCC
7
SPI_PCH_DO3_32
6
SPI_CLK32
CLK
5
SPI_DO32
+3.3V_M
vPRO@
vPRO@
1
CH7
CH7
.1U_0402_16V7K~D
.1U_0402_16V7K~D
2
4
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
RP3
RP3
1 8
HDA_BIT_CLK
2 7
HDA_RST#
3 6
HDA_SYNC
4 5
HDA_SDOUT
33_8P4R_5%
33_8P4R_5%
T273TP@ T273TP@
T275TP@ T275TP@
T276TP@ T276TP@
T277TP@ T277TP@
T278TP@ T278TP@
closed MCP 1000 mils
+5VALW
R1341
R1341
1M_0402_5%~D
1M_0402_5%~D
1 2
2
G
G
1 3
RH24 1K_0402_5%~DRH24 1K_0402_5%~D
D
S
D
S
CLK_PCIE0#25
CLK_PCIE025
CLK_PCIE_CD#23
CLK_PCIE_CD23
CDCLK_REQ#23
CLK_PCIE2#25
CLK_PCIE225
CLK_PCIE3#25
CLK_PCIE325
RH410
D
S
D
S
13
G
G
2
+3VS_NGFF
12
R1197
R1197
100K_0402_5%~D
100K_0402_5%~D
@EMI@ MC118
@EMI@
1 2
@EMI@ MC94
@EMI@
22P_0402_50V8J~D
22P_0402_50V8J~D
Reserve for EMI please close to U48
@EMI@ MC95
@EMI@
22P_0402_50V8J~D
22P_0402_50V8J~D
Reserve for EMI please close to U2
4
PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#17
HDA_SDIN020
PCH_JTAG_JTAGX
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TRST#17
PCH_JTAG_TCK17
PCH_JTAG_TDI17
PCH_JTAG_TDO17
PCH_JTAG_TMS17
PCH_JTAG_JTAGX17
1 2
RH91 10K_0402_5%~DRH91 10K_0402_5%~D
+3VS
RH95 10K_0402_5%~DRH95 10K_0402_5%~D
+3VS
RH100 10K_0402_5%~DRH100 10K_0402_5%~D
+3VS
RH103 10K_0402_5%~DRH103 10K_0402_5%~D
+3VS
RH107 10K_0402_5%~DRH107 10K_0402_5%~D
+3VS
PCH_GPIO20
MC118
12P_0402_50V8J~D
12P_0402_50V8J~D
RH258
RH258
15_0402_5%~D
15_0402_5%~D
SD028150A80
SD028150A80
nvPRO@
nvPRO@
@EMI@ MR256
@EMI@
MC94
12
MC95
@EMI@ MR257
@EMI@
12
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
1 2
1 2
1 2
1 2
1 2
DMIC_SW_PCH22
LPC_AD017,24,33
LPC_AD117,24,33
LPC_AD217,24,33
LPC_AD317,24,33
LPC_FRAME#17,24,33
PCH_SPI_CLK PCH_SPI_CLK
SML1CLK
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
RH453 0_0402_5%~D@RH453 0_0402_5%~D@
SML1DATA
MR256
1 2
SPI_CLK_ROM
33_0402_5%~D
33_0402_5%~D
MR257
1 2
SPI_CLK32
33_0402_5%~D
33_0402_5%~D
AW10
HDA_SDOUT
PCH_SPI_CS#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3
+3VS
2
6 1
QH4A
QH4A
1 2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1 2
RH454 0_0402_5%~D@RH454 0_0402_5%~D@
UCPU1E
UCPU1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK /I2S0_SCLK
AV11
HDA_SYNC/I2 S0_SFRM
AU8
HDA_RST/I2S _MCLK
AY10
HDA_SDI0/ I2S0_RXD
AU12
HDA_SDI1/ I2S1_RXD
AU11
HDA_SDO/I 2S0_TXD
HDA_DOCK_ EN/I2S1_TXD
AV10
HDA_DOCK_ RST/I2S1_SFRM
AY8
I2S1_SCL K
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
C43
C42
U2
PCH_GPIO18
B41
A41
Y5
PCH_GPIO19PCH_GPIO19
C41
B42
AD1
PCH_GPIO20
B38
C37
N1
PCH_GPIO21
A39
B39
U5
PCH_GPIO22
B37
A37
AU14
AW12
AY12
AW11
AV12
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
354
QH4B
QH4B
UCPU1F
UCPU1F
CLKOUT_PCIE _N0
CLKOUT_PCIE _P0
PCIECLKRQ 0/GPIO18
CLKOUT_PCIE _N1
CLKOUT_PCIE _P1
PCIECLKRQ 1/GPIO19
CLKOUT_PCIE _N2
CLKOUT_PCIE _P2
PCIECLKRQ 2/GPIO20
CLKOUT_PCIE _N3
CLKOUT_PCIE _P3
PCIECLKRQ 3/GPIO21
CLKOUT_PCIE _N4
CLKOUT_PCIE _P4
PCIECLKRQ 4/GPIO22
CLKOUT_PCIE _N5
CLKOUT_PCIE _P5
T2
PCIECLKRQ 5/GPIO23
UCPU1G
UCPU1G
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
Connect EC, ALS
3
HSW_ULT_DDR3L
HSW_ULT_DDR3L
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
A25
B25
K21
RSVD
M21
RSVD
C26
C35
C34
AK8
AL8
AN15
AP15
B35
A35
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AF2
AD2
AF4
2
QH3A
QH3A
6 1
1 2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4
CLKOUT_LPC0
CLKOUT_LPC1
LPC CLOCK CAN FEED ONLY 1 LOAD AT A TIME
TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4
SMBALERT#
SMBCLK
SMBDATA
CR_PWREN
SML0CLK
SML0DATA
SML1ALERT#
SML1CLK
SML1DATA
354
1 2
RH111 0_0402_5%~D@RH111 0_0402_5%~D@
Compal Secret Data
Compal Secret Data
Compal Secret Data
SATA_RN0/P ERN6_L3
RTC
RTC
AUDIO SATA
AUDIO SATA
JTAG
JTAG
5 OF 19
5 OF 19
HSW_ULT_DDR3L
HSW_ULT_DDR3L
CLOCK
CLOCK
SIGNALS
SIGNALS
6 OF 19
6 OF 19
HSW_ULT_DDR3L
HSW_ULT_DDR3L
LPC
LPC
SMBUS
SMBUS
C-LINKSPI
C-LINKSPI
7 OF 19
7 OF 19
PCH_SMLCLK 19,28,32,33
PCH_SMLDATA 19, 28,32,33
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
SATA_RP0/ PERP6_L3
SATA_TN0/PE TN6_L3
SATA_TP0/PE TP6_L3
SATA_RN1/P ERN6_L2
SATA_RP1/ PERP6_L2
SATA_TN1/PE TN6_L2
SATA_TP1/PE TP6_L2
SATA_RN2/P ERN6_L1
SATA_RP2/ PERP6_L1
SATA_TN2/PE TN6_L1
SATA_TP2/PE TP6_L1
SATA_RN3/P ERN6_L0
SATA_RP3/ PERP6_L0
SATA_TN3/PE TN6_L0
SATA_TP3/PE TP6_L0
SATA0GP/G PIO34
SATA1GP/G PIO35
SATA2GP/G PIO36
SATA3GP/G PIO37
XTAL24_IN
XTAL24_O UT
DIFFCLK_B IASREF
TESTLOW_ C35
TESTLOW_ C34
TESTLOW_ AK8
TESTLOW_ AL8
CLKOUT_LPC _0
CLKOUT_LPC _1
CLKOUT_ITPXD P
CLKOUT_ITPXD P_P
SMBALERT/G PIO11
SMBCLK
SMBDATA
SML0ALE RT/GPIO60
SML0CLK
SML1ALE RT/PCHHOT/GPIO73
SML0DATA
SML1CLK/ GPIO75
SML1DATA/G PIO74
CL_CLK
CL_DATA
CL_RST
SMBCLK
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
RH105 0_0402_5%~D@RH105 0_0402_5%~D@
SMBDATA
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2
SATA_PRX_DTX_N0 26
SATA_PRX_DTX_P0 26
SATA_PTX_DRX_N0 26
SATA_PTX_DRX_P0 26
closed MCP 2000 mils
EC_SMI#
PCH_GPIO35
PCH_GPIO36
mSATA_DET#
EC_SMI#
PCH_GPIO35
PCH_GPIO36
mSATA_DET#
SATA_RCOMP
PCH_SATALED#
Width = 15 mil , Spacing = 12 mi l
Close PCH within 500 mil
XCLK_BIASREF <100 MILS
+3VS
10K_0402_5%~D
10K_0402_5%~D
QH3B
QH3B
Deciphered Date
Deciphered Date
Deciphered Date
EC_SMI# 33
mSATA_DET# 26
1 2
RH43 3K_0402_1%~DRH43 3K_0402_1%~D
RH35 10K_0402_5%~DRH35 10K_0402_5%~D
1 2
RH113 3K_0402_1%~DRH113 3K_0402_1%~D
1 2
RH428 22_0402_5%~DRH428 22_0402_5%~D
1 2
RH360 22_0402_5%~DRH360 22_0402_5%~D
1 2
RH386 22_0402_5%~DRH386 22_0402_5%~D
1 2
RH76 10K_0402_5%~DRH76 10K_0402_5%~D
1 2
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
1 2
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
1 2
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
SMBALERT# 24
CR_PWREN 23
SML0CLK 26
SML0DATA 26
SML1ALERT# 24
CL_CLK 25
CL_DATA 25
CL_RST# 25
+3VS
12
12
RH98
RH98
RH99
RH99
10K_0402_5%~D
10K_0402_5%~D
2
12
PCH_SMBCLK 17
Connect XDP
PCH_SMBDATA 17
mSATA
T270TP@ T270TP@
T271TP@ T271TP@
T272TP@ T272TP@
T274TP@ T274TP@
+V1.05S_ASATA3PLL
+3VS
+V1.05S_AXCK_LCPLL
CLK_PCI_TPM 24
CLK_LPC_DEBUG 17
CLK_PCI_LPC 33
Connect NFC
1
12
MC103 10P_0402_50V8J~D@RF@MC103 10P_0402_50V8J~D@RF@
HDA_SDOUT
Reserve for RF please close to UH1
PCH_GPIO35
PCH_GPIO36
mSATA_DET#
HDA_SDO
ME debug mode , this signal has a weak internal PD
L=>security measures defined in the Flash
Descriptor will be in effect (default)
1 2
RH390 10K_0402_5%~D@RH390 10K_0402_5%~D@
1 2
RH391 200K_0402_5%~DRH391 200K_0402_5%~D
1 2
RH392 100K_0402_5%~DRH392 100K_0402_5%~D
H=>Flash Descriptor Security will be overridden
+3V_PCH
1 2
RH42 1K_0402_5%~D@ RH42 1K_0402_5%~D@
Low = Disabled
*
High = Enabled
XTAL24_IN
XTAL24_OUT
CLK_REQ0#25
CLK_REQ3#25
USB_OC2#9
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
RH117 1M_0402_5%~DR H117 1M_0402_5%~D
24MHZ_12PF_7V24000020
24MHZ_12PF_7V24000020
1
CH24
CH24
15P_0402_50V8J~D
15P_0402_50V8J~D
2
@RH417
@
1 2
0_0402_5%~D
0_0402_5%~D
DII-DMN65D8LW-7~D
DII-DMN65D8LW-7~D
Q348
Q348
@RH418
@
1 2
0_0402_5%~D
0_0402_5%~D
DII-DMN65D8LW-7~D
DII-DMN65D8LW-7~D
Q350
Q350
SML1CLK
RH469 2.2K_0402_5%~DRH469 2.2K_0402_5%~D
SMBCLK
RH470 2.2K_0402_5%~DRH470 2.2K_0402_5%~D
SMBDATA
RH471 2.2K_0402_5%~DRH471 2.2K_0402_5%~D
SML1DATA
RH472 2.2K_0402_5%~DRH472 2.2K_0402_5%~D
SML0CLK
RH70 499_0402_1%~DRH70 499_0402_1%~D
SML0DATA
RH72 499_0402_1%~DRH72 499_0402_1%~D
RH80 10K_0402_5%~DRH80 10K_0402_5%~D
SMBALERT#
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
EC_SMI#
RH82 10K_0402_5%~DRH82 10K_0402_5%~D
CR_PWREN
RH83 10K_0402_5%~DRH83 10K_0402_5%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
P07-MCP(3/7) SATA,HDA,CLK,SPI
P07-MCP(3/7) SATA,HDA,CLK,SPI
P07-MCP(3/7) SATA,HDA,CLK,SPI
LA-A161P
LA-A161P
LA-A161P
1 2
YH2
YH2
123
RH417
S
S
G
G
2
12
RH418
S
S
G
G
2
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
HDA_SDOUT
4
D
D
13
+3VS_NGFF
R1200
R1200
100K_0402_5%~D
100K_0402_5%~D
D
D
13
+3VS_NGFF
R1205
R1205
100K_0402_5%~D
100K_0402_5%~D
1
2
PCH_GPIO18
PCH_GPIO21
7 49Wednesday, August 14, 2013
7 49Wednesday, August 14, 2013
7 49Wednesday, August 14, 2013
+3VS
CH23
CH23
15P_0402_50V8J~D
15P_0402_50V8J~D
+3V_PCH
+3V_PCH
+3VS
A00
A00
A00
5
+3VS
PM_CLKRUN#
D D
SYS_RESET#
USB_OC0#27,9
SLP_WLAN#
Deep S3 support, connect to DSW power rail
PCH_GPIO27
DMIC_SW_DIS
AC_PRESENT
PCH_GPIO27
PCH_RSMRST#
SYS_PWROK
PCH_PWROK
C C
PCH_GPIO15
TLS Confidentiality
+3V_PCH
+3V_PCH
+3VS
+3V_PCH_DSW
B B
+3VS
+3VS
+3VS
+3V_PCH
A A
RH248 8.2K_0402_5%~DRH248 8.2K_0402_5%~D
RH467 10K_0402_5%~DRH467 10K_0402_5%~D
RH468 10K_0402_5%~DRH468 10K_0402_5%~D
RH402 10K_0402_5%~D@RH402 10K_0402_5%~D@
RH464 10K_0402_5%~DRH464 10K_0402_5%~D
RH466 10K_0402_5%~DRH466 10K_0402_5%~D
RH12 1M_0402_5%~DRH12 1M_0402_5%~D
RH186 1K_0402_5%~D@RH186 1K_0402_5%~D@
RH159 10K_0402_5%~DRH159 10K_0402_5%~D
RH272 10K_0402_5%~D@RH272 10K_0402_5%~D@
RH394 100K_0402_5%~DRH394 100K_0402_5%~D
Low - Intel ME Crypto Transport Layer Security (TLS)
*
cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality
vPRO@
vPRO@
RH270 1K_0402_5%~D
RH270 1K_0402_5%~D
RH294 10K_0402_5%~D@RH294 10K_0402_5%~D@
RH383 100K_0402_5%~DRH383 100K_0402_5%~D
RH295 10K_0402_5%~DRH295 10K_0402_5%~D
RH298 10K_0402_5%~DRH298 10K_0402_5%~D
RH299 10K_0402_5%~DRH299 10K_0402_5%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH296 10K_0402_5%~DRH296 10K_0402_5%~D
1 2
R1185 100K_0402_5%~DR1185 100K_0402_5%~D
RH400 100K_0402_5%~DRH400 100K_0402_5%~D
RH465 1M_0402_5%~DRH465 1M_0402_5%~D
RH457 49.9K_0402_1%~DRH457 49.9K_0402_1%~D
RH458 49.9K_0402_1%~DRH458 49.9K_0402_1%~D
RH459 49.9K_0402_1%~DRH459 49.9K_0402_1%~D
RH460 49.9K_0402_1%~DRH460 49.9K_0402_1%~D
RH384 100K_0402_5%~D@RH384 100K_0402_5%~D@
1 2
RH37 1K_0402_5%~D@ RH37 1K_0402_5%~D@
LOW=Default
*
HIGH=No Reboot
@
@
1 2
RH274 10K_0402_5%~D
RH274 10K_0402_5%~D
RH337 100K_0402_5%~D
RH337 100K_0402_5%~D
@
@
12
Deep S3 support, connect to EC
1 2
1 2
1 2
1 2
1 2
1 2
12
1 2
1 2
1 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
SENSOR_INT#
EC_RUNTIME_SCI#
PCH_GPIO17
HDA_SPKR
TPM_DET
TPM_DET
+3V_PCH_DSW
PCH_GPIO15
NFC_IRQ
UART_WAKE#
CR_WAKE#
GPIO12
MPHY_PWREN
USB0_PWR_EN
NFC_DET#
UART1_RXD
UART1_TXD
UART1_RTS#
UART1_CTS#
TS_INT#
SUSACK#33
PM_SYS_RESET#17
SYS_PWROK17,32
PCH_PWROK32
APOWER_OK29,33,41
PCH_RSMRST#33
PCH_SUSWARN#33
PBTN_OUT#33
AC_PRESENT33
PM_SLP_S0#17,33,41
+3VS
+3V_PCH
Reserve for EMI please close to UH5
Deep S3 support,
PCH_GPIO27 connect from EC PCH_WAKE#
PBTN_OUT#_R
PCH_SUSWARN#R
PCH_PWROK
PCH_RSMRST# PCH_RSMRST#_R
1.05VS_PG17,32
PBTN_SW#17,20,33
PLT_RST#17,23,24,25,33
@EMI@
@EMI@
MC104 10P_0402_50V8J~D
MC104 10P_0402_50V8J~D
I2C0_SDA
I2C0_SCK
12
RH171
RH171
100K_0402_5%~D
100K_0402_5%~D
12
PLT_RST#
4
RH461 2.2K_0402_5%~DCS@ RH461 2.2K_0402_5%~DCS@
RH462 2.2K_0402_5%~DCS@ RH462 2.2K_0402_5%~DCS@
Audio DSP
TPM BOM Optional
TPM_DET
TPM
1 = W/TPM
0 = W/O TPM
5
Sensor HUB
4
1 2
R1312 3K_0402_5%~D@ R1312 3K_0402_5%~D@
Non Deep S3 (Pop RH429)
Deep S3 (Pop RH430)
RH429 0_0402_5%~DCS@ RH429 0_0402_5%~DCS@
RH430 0_0402_5%~DNon-CS@ R H430 0_0402_5%~DNon-CS@
RH450 0_0402_5%@RH450 0_0402_5%@
RH131 0_0402_5%~DvPRO@ RH131 0_0402_5%~DvPRO@
RH134 0_0402_5%~DnvPRO@ RH134 0_0402_5%~DnvPRO@
RH133 0_0402_5%@RH133 0_0402_5%@
RH297 0_0402_5%@RH297 0_0402_5%@
RH293 0_0402_5%@RH293 0_0402_5%@
RH137 0_0402_5%@RH137 0_0402_5%@
RH447 0_0402_5%~D@ RH447 0_0402_5%~D@
RH438 0_0402_5%~D@ RH438 0_0402_5%~D@
RH439 0_0402_5%~D@ RH439 0_0402_5%~D@
O
12
12
12
12
12
12
12
12
12
DMIC_SW_DIS22
12
SLP_WLAN#33
12
12
1 2
RH168 0_0402_5%~D@RH168 0_0402_5%~D@
+3VS
5
1
P
IN1
2
IN2
G
3
UH5
UH5
SN74AHC1G08DCKR_SC70-5~D
SN74AHC1G08DCKR_SC70-5~D
closed MCP 2000 mils
T279TP@T279TP@
T281TP@T281TP@
T282TP@T282TP@
T284TP@T284TP@
T285TP@T285TP@
T286TP@T286TP@
T287TP@T287TP@
T288TP@T288TP@
AUDIO_PWREN20,29,30
KB_BL_DET31
KB_DET#31
CR_WAKE#23
NFC_RST#26
NFC_IRQ26
TPM_RST#24
BT_CS_NOTICE25
SLATE_MODE24
SENSOR_DFU_EN#24
SENSOR_HUB_I2C_WAKE24
MPHY_PWREN30
SENSOR_INT#24
EC_RUNTIME_SCI#33
SENSOR_STANDBY#24
1 2
1 2
I2C0_SDA_DSP20
I2C0_SCK_DSP20
I2C0_SDA_SNR24
I2C0_SCK_SNR24
TS_INT#19
USB0_PWR_EN27
EN_CAM30
SENSOR_EN24,30
UART_WAKE#25
DEVSLP026
WL_OFF#25
NFC_DET#26
HDA_SPKR21
4
AUDIO_PWREN
PCH_GPIO17
KB_DET#
KB_BL_DET
SENSOR_INT#
MEM_CONFIG0
MEM_CONFIG1
UART_WAKE#
AUDIO_PWREN
KB_BL_DET
GPIO12
PCH_GPIO15
KB_DET#
PCH_GPIO17
CR_WAKE#
PCH_GPIO27
NFC_IRQ
MEM_CONFIG0
MEM_CONFIG2
MEM_CONFIG1
TS_INT#
MPHY_PWREN
USB0_PWR_EN
SENSOR_INT#
TPM_DET
UART_WAKE#
EC_RUNTIME_SCI#
NFC_DET#
HDA_SPKR
+3V_PCH
SUSACK#_R
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK_R
PCH_PLTRST#
PCH_SUSWARN#R
PBTN_OUT#_R
AC_PRESENT_RAC_PRESENT
DMIC_SW_DIS
SLP_WLAN#
APWROK_R
PBTN_OUT#_R
1 2
RA7 0_0402_5%~D@ RA7 0_0402_5%~D@
RA8 0_0402_5%~D@ RA8 0_0402_5%~D@
R1225 0_0402_5%~DCS@ R1225 0_0402_5%~DCS@
R1224 0_0402_5%~DCS@ R1224 0_0402_5%~DCS@
PCH_PLTRST#
@
@
RH183
RH183
10K_0402_5%~D
10K_0402_5%~D
I2C0_SDA
I2C0_SCK
1 2
1 2
UCPU1H
UCPU1H
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
PBTN_OUT#_R 17
DSWODVREN
DSWODVREN
SSD_PWREN#
SSD_PWREN#
UCPU1J
UCPU1J
P1
BMBUSY/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
1 2
RH424 2.2K_0402_5%~D@RH424 2.2K_0402_5%~D@
1 2
RH425 2.2K_0402_5%~D@RH425 2.2K_0402_5%~D@
12
12
3
HSW_ULT_DDR3L
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
8 OF 19
8 OF 19
PCH Strap PIN
RH147 330K_0402_5%~DRH147 330K_0402_5%~D
RH151 330K_0402_5%~D@RH151 330K_0402_5%~D@
DSWODVREN - On Die DSW VR Enable
H
：
Enable
*
L：Disable
U682
U682
1
NC
2
IN A
3
GND
SN74AUP1G04DCKR_SOT23-5~D
SN74AUP1G04DCKR_SOT23-5~D
1 2
HSW_ULT_DDR3L
HSW_ULT_DDR3L
10 OF 19
10 OF 19
+3VS+3VNS_PWR
12
SERIAL IO
SERIAL IO
3
RH431 0_0402_5%~D@ RH431 0_0402_5%~D@
RH423 100K_0402_5%~DRH423 100K_0402_5%~D
GPIO
GPIO
I2C0_SDA
I2C0_SCK
2
CRB 10K
AW7
DPWROK
WAKE
SLP_S4
SLP_S3
SLP_A
+RTCVCC
SERIRQ
RSVD
RSVD
DSWODVREN
AV5
PCH_DPWROK
AJ5
WAKE#
V5
PM_CLKRUN#
AG4
SUS_STAT#
AE6
SUSCLK
AP5
AJ6
AT4
AL5
AP4
AJ7
RH132 0_0402_5%@RH132 0_0402_5%@
PM_SLP_S4#
PM_SLP_S3#
RH313 0_0402_5%~D
RH313 0_0402_5%~D
Non-CS@
Non-CS@
Deep S3 Support
Non Deep S3 (De-pop RH313)
SUSCLK
12
PM_SLP_S4# 17,33,42
PM_SLP_S3# 17,29,30,33, 40
12
PM_SLP_A# 17,29,30,33
PM_SLP_SUS# 29,30,33
12
MC102 10P_0402_50V8J~D@RF@ MC 102 10P_0402_50V8J~D@RF@
Reserve for RF please close to UH1
SSD_PWREN 26
D60
H_THERMTRIP#_R H_THERMTRIP#
V4
KB_RST#
T4
SERIRQ
AW15
PCH_OPIRCOMP
AF20
AB21
Width = 15 mil, Spacing = 12 mil
Close PCH within 500 mil
R6
L6
N6
L8
R7
L5
N7
K2
SSD_PWREN#
J1
DDR_CHA_EN
K3
DDR_CHB_EN
J2
G1
K4
UART1_RXD
G2
UART1_TXD
J3
UART1_RTS#
J4
UART1_CTS#
F2
I2C0_SDA
F3
I2C0_SCK
G4
F1
E3
F4
D3
SDIO_D0
E4
C3
E2
1 2
RC49 0_0402_5%@ RC49 0_0402_5%@
NGFF_PWREN 25,30
TP_EN 30
BT_RADIO_DIS# 25
RH448 0_0402_5%@ RH448 0_0402_5%@
TS_EN 30
UART1_RXD 25
UART1_TXD 25
UART1_RTS# 25
UART1_CTS# 25
I2C0_SDA 33
I2C0_SCK 33
I2C1_SDA 19
I2C1_SCK 19
SDIO_CLK 25
SDIO_CMD 25
SDIO_D0 25
SDIO_D1 25
SDIO_D2 25
SDIO_D3 25
I2C is daisy chain
routing with pull up
on the last device
12
DDR Memory Configuration Type Strap pin
+3V_PCH
+3VS
GPIO Pin
PCH_GPIO59
PCH_GPIO48
PCH_GPIO47
Compal Secret Data
Compal Secret Data
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
PM_CLKRUN# 24,33
SUS_STAT# 24
SUSCLK_R 25,33
PM_SLP_S5# 17,33
KB_RST# 33
SERIRQ 24,33
PM_SLP_S0#
RH271 10K_0402_5%~D@RH271 10K_0402_5%~D@
RH303 10K_0402_5%~D@RH303 10K_0402_5%~D@
RH180 10K_0402_5%~D@RH180 10K_0402_5%~D@
MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
PCH DPWROK Option for Deep S3
12
12
12
Pin Name
DSWVRMEN
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
SLP_SUS
SLP_LAN
12
12
5
VCC
4
OUT Y
THRMTRIP
RCIN/GPIO82
CPU/
CPU/
PCH_OPI_RCOMP
MISC
MISC
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
1
WAKE#
PCH_SUSWARN#R
PCH_DPWROK
WAKE_PCH#25,33
PCH_GPIO27
Non-CS@ R H309
Non-CS@
1 2
RH146 1K_0402_5%~DRH 146 1K_0402_5%~D
1 2
RH154 1M_0402_5%~DRH154 1M_0402_5%~D
1 2
RH401 100K_0402_5%~D
RH401 100K_0402_5%~D
RH309
0_0402_5%~D
0_0402_5%~D
12
1 2
RH126
CS@ RH126
CS@
0_0402_5%~D
0_0402_5%~D
RH310
@ RH310
@
0_0402_5%~D
RH427 0_0402_5%@ RH427 0_0402_5%@
0_0402_5%~D
1 2
RH128
@ RH128
@
0_0402_5%
0_0402_5%
1 2
PCH_GPIO27
0802-12
H_THERMTRIP#
KB_DET#
SERIRQ
KB_RST#
DDR_CHA_EN
DDR_CHB_EN
DDR_CHA_EN
DDR_CHB_EN
PCH_OPIRCOMP
GPIO86 have internal pull down
SDIO_D0
1 2
RC149 1K_0402_5%~DRC 149 1K_0402_5%~D
RH302 100K_0402_5%~DRH302 100K_0402_5%~D
RH29 10K_0402_5%~DRH29 10K_0402_5%~D
RH196 10K_0402_5%~DRH196 10K_0402_5%~D
RH440 100K_0402_5%~DRH440 100K_0402_5%~D
RH441 100K_0402_5%~DRH441 100K_0402_5%~D
RH442 SHORT PADS@ RH442 SHORT PADS@
RH443 SHORT PADS@ RH443 SHORT PADS@
RC156 49.9_0402_1%~DRC156 49.9_0402_1%~D
Boot BIOS Strap
0
*
RH434 1K_0402_5%~D@RH434 1K_0402_5%~D@
@
@
PCH_RSMRST#_RPCH_D PWROK
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Boot BIOS LocationPCH_GPIO86
SPI
+3V_PCH_DSW
3VALW_PG 37
12
WAKE#
0802-12
+1.05VS_VCCST+3VS
+VS_LPSS_SDIO
12
GPIO66 have internal pull down
Top-Block Swap Override mode
0 = Enable
*
1 = Disable
MEM_CONFIG2
MEM_CONFIG0
MEM_CONFIG1
Samsung 4G Hynix 4G
0 1
0
0
Title
Title
Title
P08-MCP(4/7) PM,GPIO,LPIO,MISC
P08-MCP(4/7) PM,GPIO,LPIO,MISC
P08-MCP(4/7) PM,GPIO,LPIO,MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA-A161P
LA-A161P
LA-A161P
Date: Sheet of
Date: Sheet of
Date: Sheet of
RH314 10K_0402_5%~DRH314 10K_0402_5%~D
RH316 10K_0402_5%~DRH316 10K_0402_5%~D
RH315 10K_0402_5%~DRH315 10K_0402_5%~D
Micron 4G
0
0
1
0
0
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
12
12
12
1
+3V_PCH
Deep S3 Support
Non Deep S3
EC_WAKE_SCI# 33
+3VS
8 49Wednesday, August 14, 2013
8 49Wednesday, August 14, 2013
8 49Wednesday, August 14, 2013
A00
A00
A00
5
D D
PCIE_PRX_WLANTX_N325
NGFF (WLAN)
NGFF(WiGig)
C C
CardReader
PCIE_PRX_WLANTX_P325
PCIE_PTX_WLANRX_N325
PCIE_PTX_WLANRX_P325
PCIE_PRX_DTX_N425
PCIE_PRX_DTX_P425
PCIE_PTX_DRX_N425
PCIE_PTX_DRX_P425
PCIE_PRX_DTX_N125
PCIE_PRX_DTX_P125
PCIE_PTX_DRX_N125
PCIE_PTX_DRX_P125
PCIE_PRX_CARDTX_N223
PCIE_PRX_CARDTX_P223
PCIE_PTX_CARDRX_N223
PCIE_PTX_CARDRX_P223
1 2
CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D
1 2
CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D
1 2
CH1237 0.1U_0402_10V7K~DCH1237 0.1U_0402_10V7K~D
1 2
CH1238 0.1U_0402_10V7K~DCH1238 0.1U_0402_10V7K~D
1 2
CH1242 0.1U_0402_10V7K~DCH1242 0.1U_0402_10V7K~D
1 2
CH1243 0.1U_0402_10V7K~DCH1243 0.1U_0402_10V7K~D
1 2
CH25 0.1U_0402_10V7K~DCH25 0.1U_0402_10V7K~D
1 2
CH26 0.1U_0402_10V7K~DCH26 0.1U_0402_10V7K~D
+V1.05S_AUSB3PLL
1 2
RH338 3K_0402_1%~DRH 338 3K_0402_1%~D
Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil
4
PCIE_PTX_WLANRX_N3_C
PCIE_PTX_WLANRX_P3_C
PCIE_PTX_DRX_N4_C
PCIE_PTX_DRX_P4_C
PCIE_PTX_DRX_N1_C
PCIE_PTX_DRX_P1_C
PCIE_PTX_C_CARDRX_N2
PCIE_PTX_C_CARDRX_P2
PCIE_RCOMP
F10
E10
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
UCPU1K
UCPU1K
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
HSW_ULT_DDR3L
HSW_ULT_DDR3L
PCIE USB
PCIE USB
11 OF 19
11 OF 19
3
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBRBIAS
USB_OC1#
USB1_PWR_EN
USB20_N0 27
USB20_P0 27
USB20_N1 27
USB20_P1 27
USB20_N2 25
USB20_P2 25
USB20_N3 19
USB20_P3 19
USB20_N4 19
USB20_P4 19
USB20_N5 24
USB20_P5 24
USB20_N6 25
USB20_P6 25
USB3RN0 27
USB3RP0 27
USB3TN0 27
USB3TP0 27
USB3RN1 27
USB3RP1 27
USB3TN1 27
USB3TP1 27
Within 450 mils
1 2
RH163
RH163
22.6_0402_1%
22.6_0402_1%
USB_OC0# 27,8
USB_OC1# 27
USB_OC2# 7
USB1_PWR_EN 27
2
USB3.0 (Power Share)
USB3.0 (Power Share) Debug Port
NGFF (WLAN)
Touch Panel
Camera
Sensors HUB
NGFF(WiGig)
Net USB_BIAS route impedacnes should be 50-ohm
and length less than 450-mil spacing is 15-mil .
USB_OC1#
USB1_PWR_EN
1 2
RH160 10K_0402_5%~DRH160 10K_0402_5%~D
RH403 100K_0402_5%~DRH403 100K_0402_5%~D
12
1
+3V_PCH
HSW_ULT_DDR3L
UCPU1Q
UCPU1Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
B B
A A
5
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
4
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
UCPU1R
UCPU1R
AT2
RSVD
AU44
RSVD
AV44
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSW_ULT_DDR3L
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19
17 OF 19
18 OF 19
18 OF 19
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
3
A3
DC_TEST_A3_B3
A4
A60
A61
DC_TEST_A61_B61
A62
AV1
AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
N23
RSVD
R23
RSVD
T23
RSVD
U10
RSVD
AL1
RSVD
AM11
RSVD
AP7
RSVD
AU10
RSVD
AU15
RSVD
AW14
RSVD
AY14
RSVD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P09-MCP(5/7) PCIE,USB
P09-MCP(5/7) PCIE,USB
P09-MCP(5/7) PCIE,USB
LA-A161P
LA-A161P
LA-A161P
1
9 49Wednesday, August 14, 2013
9 49Wednesday, August 14, 2013
9 49Wednesday, August 14, 2013
A00
A00
A00
5
+1.35V_DDR
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC160
CC160
2
2
D D
+1.05VS_VCCST
VIDSOUT:
Requires a pull-up to VCCIO through a pull-up resistor of 110 ±5% close to the p rocessor, and a pull-up
to VCCIO through a pull-up resistor of 110 ±5% close to Intel MVP 7.
VIDSCLK:
Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7.
C C
+1.05VDX_MODPHY
R1240 0_1206_5%R1240 0_1206_5%
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC233
CC233
1
1
2
2
close to CPU
RC93 75_0402_5%RC93 75_0402_5%
1 2
RC95 130_0402_1%RC95 130_0402_1%
SIP
1 2
0802-13
+1.05VDX_MODPHY
B B
+1.05VS
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VDX_MODPHY
Deep S3 Support
+3VALW
+3V_PCH
Non Deep S3
A A
+1.05VS +1.05VS
LH10
LH10
1 2
2.2UH_LQM21PN2R2MC0D_20%
2.2UH_LQM21PN2R2MC0D_20%
CH1208
CH1208
22U_0805_6.3V6M
22U_0805_6.3V6M
LH12
LH12
1 2
100U_A_6.3V_R70M
100U_A_6.3V_R70M
2.2UH_LQM21PN2R2MC0D_20%
2.2UH_LQM21PN2R2MC0D_20%
Non-CS@ RH348
Non-CS@
CS@ RH351
CS@
RH355
@ RH355
@
1 2
0_0603_5%~D
0_0603_5%~D
+V1.05S_APLLOPI
1
+
+
CH1212
CH1212
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
LH11
LH11
1 2
CH1210
CH1210
22U_0805_6.3V6M
22U_0805_6.3V6M
RH348
1 2
0_0603_5%~D
0_0603_5%~D
1 2
RH351
0_0603_5%~D
0_0603_5%~D
CH1224
CH1224
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+V1.05S_AXCK_DCB_L +V1.05S_AXCK_LCPLL_L +V1.05S_AXCK_LCPLL
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
1
CC161
CC161
2
CC238
CC238
1
2
12
1
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
2
5
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC163
CC163
CC162
CC162
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC239
CC239
CC234
CC234
1
2
+V1.05VS_VCCHSIO
1
CH40
CH40
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+V1.05S_AUSB3PLL
CH1209
CH1209
CH1213
CH1213
+V1.05S_ASATA3PLL
CH1211
CH1211
+3V_PCH_DSW
L61
L61
1 2
100U_A_6.3V_R70M
100U_A_6.3V_R70M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC164
CC164
2
H_CPU_SVIDALRT#
H_CPU_SVIDDAT
1
2
1
2
1
2
+
+
CH1228
CH1228
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC165
CC165
2
1
CH41
CH41
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05V_M
22U_0603_6.3V6M~D
22U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+V1.05S_AXCK_DCB
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+1.05VS
+1.5VS_3.3VS_AUDIO
+1.5VS_3.3VS_AUDIO
1
CH85
CH85
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
@
@
1
CH1239
CH1239
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
+3V_PCH
CH1220
CH1220
+1.05VS
CH1234
CH1234
1
CH1229
CH1229
2
SIP
RH340
@ RH340
@
1 2
0_0805_5%
0_0805_5%
CH1204
CH1204
22U_0603_6.3V6M~D
22U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
@
@
1
CH1214
CH1214
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
+3VS
2
22U_0603_6.3V6M~D
22U_0603_6.3V6M~D
+V1.05S_AXCK_LCPLL
+1.05VS
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RH356
@ RH356
@
1 2
0_0603_5%~D
0_0603_5%~D
4
IMVP_VR_PG32,43
+VCCIO_OUT
0802-12
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
CH39
CH39
RH405
@RH405
@
1 2
0_0603_5%~D
0_0603_5%~D
1
CH1225
CH1225
2
1
CH1235
CH1235
2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
4
+1.05VS
1
2
1
CH1241
CH1241
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
VR_SVID_ALRT#43
1.05VS_VCCST_PG17,32
+1.05VS_VCCST
1
CH1205
CH1205
2
+V1.05VS_VCCHSIO
+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL
+V1.05S_APLLOPI
+V1.05A_DCPSUS
+1.5VS_3.3VS_AUDIO
+3V_PCH_DSW
+V1.05S_AXCK_DCB
+V1.05S_AXCK_LCPLL
L62
L62
1 2
100U_1206_6.3V6M
100U_1206_6.3V6M
+1.05VS_VCCST
VR_SVID_CLK43
VR_SVID_DAT43
VR_ON43
CH1230
CH1230
12
R1211
R1211
1M_0402_5%~D
1M_0402_5%~D
IMVP_VR_PG
+VCC_CORE
VCCSENSE43
IMVP_VR_PG
+1.05VS_VCCST
UCPU1M
UCPU1M
K9
VCCHSIO
L10
VCCHSIO
M9
VCCHSIO
N8
VCC1_05
P9
VCC1_05
B18
VCCUSB3PLL
B11
VCCSATA3PLL
Y20
RSVD
AA21
VCCAPLL
W21
VCCAPLL
J13
DCPSUS3
AH14
VCCHDA
AH13
DCPSUS2
AC9
VCCSUS3_3
AA9
VCCSUS3_3
AH10
VCCDSW3_3
V8
VCC3_3
W9
VCC3_3
J18
VCCCLK
K19
VCCCLK
A20
VCCACLKPLL
J17
VCCCLK
R21
VCCCLK
T21
VCCCLK
K18
RSVD
M20
RSVD
V21
RSVD
AE20
VCCSUS3_3
AE21
VCCSUS3_3
DCPSUS can be NC, if INTVRMEN pull up
to enable Integrated VRM
1
CH1231
CH1231
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
RC97 & RC98 close to PCH
1 2
RC97 100_0402_1%~DRC97 100_0402_1%~D
1 2
RC98 0_0402_5%@ RC98 0_0402_5%@
+VCCIO_OUT
+VCCIOA_OUT
1 2
RC94 43_0402_5%~DRC94 43_0402_5%~D
1 2
RC92 0_0402_5%~D@ RC92 0_0402_5%~D@
1 2
RC96 0_0402_5%~D@ RC96 0_0402_5%~D@
1 2
RC150 0_0402_5%~D@ RC150 0_0402_5%~D@
1 2
RC151 0_0402_5%~D@ RC151 0_0402_5%~D@
1 2
RC152 0_0402_5%~D@ RC152 0_0402_5%~D@
R1179
R1179
1 2
FIVE_EN
150_0402_5%~D
150_0402_5%~D
GPIO/LPC
GPIO/LPC
LPT LP POWER
LPT LP POWER
1
2
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSIO
HSIO
OPI
OPI
USB3
USB3
HDA
HDA
VRM
VRM
FIVE_EN17
+1.05VS_VCCST
+VCC_CORE
13 OF 19
13 OF 19
3
+1.35V_DDR
4.2A
+VCC_CORE
VCCSENSE_R
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCSTPG_MCP
VR_ON_MCPVR_ON
VRPG_MCP
FIVE_EN
RTC
RTC
SPI
SPI
CORE
CORE
THERMAL SENSOR
THERMAL SENSOR
SERIAL IO
SERIAL IO
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
AC58
AB23
AD23
AA23
AE59
AD60
AD59
AA59
AE60
AC59
AG58
AC22
AE22
AE23
AB57
AD57
AG57
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
UCPU1L
UCPU1L
L59
RSVD
J58
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
F59
VCC
N58
RSVD
RSVD
E63
VCC_SENSE
RSVD
A59
VCCIO_OUT
E20
VCCIOA_OUT
RSVD
RSVD
RSVD
L62
VIDALERT
N63
VIDSCLK
L63
VIDSOUT
B59
VCCST_PWRGD
F60
VR_EN
C59
VR_READY
D63
VSS
H59
PWR_DEBUG
P62
VSS
P60
RSVD_TP
P61
RSVD_TP
N59
RSVD_TP
N61
RSVD_TP
T59
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
U59
RSVD
V59
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
C24
VCC
C28
VCC
C32
VCC
AH11
AG10
AE7
CH1206 0.1U_0402_10V7K~DCH1206 0.1U_0402_10V7K~D
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSW ULT POWER
HSW ULT POWER
12 OF 19
12 OF 19
+1.05V_M
+1.5VS
1
CH1233
CH1233
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+RTCVCC
RH346
@ RH346
@
1 2
0_0402_5%
0_0402_5%
1
2
+1.05VS
Compal Secret Data
Compal Secret Data
Compal Secret Data
+RTC_VCCSUS
1 2
+PCH_VCCDSW
+V1.05A_DCPSUS
+VS_LPSS_SDIO
+V1.05A_AOSCSUS
T280@T280 @
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
+3.3V_M
1
@
@
CH47
CH47
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
CH1218
CH1218
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+3VS
CH1226
CH1226
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+RTC_VCCSUS
Deciphered Date
Deciphered Date
Deciphered Date
2
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CH1215
CH1215
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH1222
CH1222
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
2
+VCC_CORE
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
@ RH341
@
0_0603_5%~D
0_0603_5%~D
CH1207
CH1207
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
closed to VCC1P05
1
CH1216
CH1216
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+1.05V_M
1
@
@
CH1223
CH1223
22U_0603_6.3V6M~D
22U_0603_6.3V6M~D
2
SIP
+3V_PCH
RH341
12
+V1.05A_AOSCSUS
1
@
@
CH1232
CH1232
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
+1.05VS
CH1217
CH1217
1
2
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
closed to VCCRTC
1
CH84
CH84
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VS_LPSS_SDIO
1
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
0802-12
0806-22
+VS_LPSS_SDIO
@
@
L63
L63
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
+
+
CH1240
CH1240
100U_A_6.3V_R70M
100U_A_6.3V_R70M
@
@
P10-MCP(6/7) PWR,VCC
P10-MCP(6/7) PWR,VCC
P10-MCP(6/7) PWR,VCC
LA-A161P
LA-A161P
LA-A161P
+V1.05A_AOSCSUS_L
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CH83
CH83
1
2
1
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
RH350
RH350
1 2
0_0603_5%~D
0_0603_5%~D
RH354
@RH354
@
1 2
0_0603_5%~D
0_0603_5%~D
CH1227
CH1227
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.8VS
+3VS
RH406
@ RH406
@
1 2
0_0603_5%~D
0_0603_5%~D
10 49Wednesday, August 14, 2013
10 49Wednesday, August 14, 2013
10 49Wednesday, August 14, 2013
CH82
CH82
+RTCVCC
+1.05V_M
1
2
A00
A00
A00
5
4
UCPU1S
UCPU1S
HSW_ULT_DDR3L
HSW_ULT_DDR3L
3
2
1
CFG3
CFG4
CFG_RCOMP
UCPU1O
UCPU1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
AA62
U63
AA61
U62
V63
A5
E1
D1
J20
H18
B12
HSW_ULT_DDR3L
HSW_ULT_DDR3L
15 OF 19
15 OF 19
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
RESERVED
RESERVED
PROC_OPI_RCOMP
19 OF 19
19 OF 19
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
CFG017
CFG117
D D
12
CFG4
RC811K_0402_5% RC811K_0402_5%
eDP Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0 : Enabled; An external Display
*
Port device is connected to the
Embedded Display Port
12
CFG_RCOMP
RC15349.9_0402_1%~D RC15349.9_0402_1%~D
12
PROC_OPI_COMP
RC15449.9_0402_1%~D RC15449.9_0402_1%~D
12
TD_IREF TD_IREF
RC1558.2K_0402_1% RC1558.2K_0402_1%
Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil
C C
HSW_ULT_DDR3L
HSW_ULT_DDR3L
UCPU1N
UCPU1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
B B
A A
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
VSS
AF11
VSS
AF12
VSS
AF14
VSS
AF15
VSS
AF17
VSS
AF18
VSS
AG1
VSS
AG11
VSS
AG21
VSS
AG23
VSS
AG60
VSS
AG61
VSS
AG62
VSS
AG63
VSS
AH17
VSS
AH19
VSS
AH20
VSS
AH22
VSS
AH24
VSS
AH28
VSS
AH30
VSS
AH32
VSS
AH34
VSS
AH36
VSS
AH38
VSS
AH40
VSS
AH42
VSS
AH44
VSS
AH49
VSS
AH51
VSS
AH53
VSS
AH55
VSS
AH57
VSS
AJ13
VSS
AJ14
VSS
AJ23
VSS
AJ25
VSS
AJ27
VSS
AJ29
VSS
14 OF 19
14 OF 19
5
AJ35
VSS
AJ39
VSS
AJ41
VSS
AJ43
VSS
AJ45
VSS
AJ47
VSS
AJ50
VSS
AJ52
VSS
AJ54
VSS
AJ56
VSS
AJ58
VSS
AJ60
VSS
AJ63
VSS
AK23
VSS
AK3
VSS
AK52
VSS
AL10
VSS
AL13
VSS
AL17
VSS
AL20
VSS
AL22
VSS
AL23
VSS
AL26
VSS
AL29
VSS
AL31
VSS
AL33
VSS
AL36
VSS
AL39
VSS
AL40
VSS
AL45
VSS
AL46
VSS
AL51
VSS
AL52
VSS
AL54
VSS
AL57
VSS
AL60
VSS
AL61
VSS
AM1
VSS
AM17
VSS
AM23
VSS
AM31
VSS
AM52
VSS
AN17
VSS
AN23
VSS
AN31
VSS
AN32
VSS
AN35
VSS
AN36
VSS
AN39
VSS
AN40
VSS
AN42
VSS
AN43
VSS
AN45
VSS
AN46
VSS
AN48
VSS
AN49
VSS
AN51
VSS
AN52
VSS
AN60
VSS
AN63
VSS
AN7
VSS
AP10
VSS
AP17
VSS
AP20
VSS
CFG217
CFG317
CFG417
CFG517
CFG617
CFG717
CFG817
CFG917
CFG1017
CFG1117
CFG1217
CFG1317
CFG1417
CFG1517
CFG1617
CFG1817
CFG1717
CFG1917
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
4
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Issued Date
Issued Date
Issued Date
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
PROC_OPI_COMP
AV62
D58
P22
VSS
N21
VSS
P20
R20
HSW_ULT_DDR3L
HSW_ULT_DDR3L
UCPU1P
UCPU1P
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
16 OF 19
16 OF 19
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
Compal Secret Data
Compal Secret Data
Compal Secret Data
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
Deciphered Date
Deciphered Date
Deciphered Date
VSSSENSE_R
2
RC99 & RC100 close to PCH
1 2
RC99 0_0402_5%@ RC99 0_0402_5%@
1 2
RC100 100_0402_1%~DRC100 100_0402_1%~D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VSSSENSE 43
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
P11-MCP(7/7) PWR,VSS,CFG
P11-MCP(7/7) PWR,VSS,CFG
P11-MCP(7/7) PWR,VSS,CFG
LA-A161P
LA-A161P
LA-A161P
1
11 49Wednesday, August 14, 2013
11 49Wednesday, August 14, 2013
11 49Wednesday, August 14, 2013
A00
A00
A00
5
4
3
2
1
follow INTEL PD G
1 2
CD1 0.047U_0402_16V4ZCD1 0.047U_0402_16V4Z
1 2
CD2 0.047U_0402_16V4ZCD2 0.047U_0402_16V4Z
1 2
CD3 0.047U_0402_16V4ZCD3 0.047U_0402_16V4Z
1 2
D D
DDR_A_DQS#[0..7]13,6
DDR_A_DQS[0..7]13,6
DDR_A_D[0..63]13,6
DDR_A_MA[0..15]13,16,6
All VREF traces should
have 10 mil trace width
C C
B B
CD4 0.047U_0402_16V4ZCD4 0.047U_0402_16V4Z
PLACE THESE CAPS
NEAR TO RESPECTIVE DRAM
+VREFCA
+VREFDQ_A
DDR3_DRAMRST#13,14,15,5
CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@
@
CD5
CD5
UD2
UD1
UD1
+VREFCA
+VREFDQ_A
DDR_A_BS013,16,6
DDR_A_BS113,16,6
DDR_A_BS213,16,6
M_CLK_A_DDR013,16,6
M_CLK_A_DDR#013,16,6
DDR_A_CKE013,16,6
DDR_A_CKE113,16,6
M_ODT013,16
DDR_A_CS0#13,16,6
DDR_A_CS1#13,16,6
DDR_A_RAS#13,16,6
DDR_A_CAS#13,16,6
DDR_A_WE#13,16,6
1
2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M_CLK_A_DDR0
M_CLK_A_DDR#0
DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS#0
DDR_A_DQS#1
DDR3_DRAMRST#
12
RD1 240_0402_1%RD1 240_0402_1%
12
RD79 240_0402_1%RD79 240_0402_1%
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_A_D6
F7
DDR_A_D0
F2
DDR_A_D2
F8
DDR_A_D5
H3
DDR_A_D3
H8
DDR_A_D4
G2
DDR_A_D7
H7
DDR_A_D1
D7
DDR_A_D13
C3
DDR_A_D15
C8
DDR_A_D12
C2
DDR_A_D14
A7
DDR_A_D8
A2
DDR_A_D11
B8
DDR_A_D9
A3
DDR_A_D10
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR +1.35V_DDR
+VREFCA
+VREFDQ_A
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M_CLK_A_DDR0
M_CLK_A_DDR#0
DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS#2
DDR_A_DQS#3
DDR3_DRAMRST#
RD2 240_0402_1%RD2 240_0402_1%
RD80 240_0402_1%RD80 240_0402_1%
12
12
UD2
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_A_D18
F7
DDR_A_D16
F2
DDR_A_D22
F8
DDR_A_D21
H3
DDR_A_D19
H8
DDR_A_D20
G2
DDR_A_D23
H7
DDR_A_D17
D7
DDR_A_D29
C3
DDR_A_D27
C8
DDR_A_D28
C2
DDR_A_D26
A7
DDR_A_D24
A2
DDR_A_D31
B8
DDR_A_D25
A3
DDR_A_D30
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
A A
5
CD15
CD15
CD14
CD14
1
2
1
1
2
2
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD16
CD16
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD18
CD18
CD17
CD17
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD20
CD20
CD19
CD19
12
12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD111
CD111
CD21
CD21
1
1
2
2
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD112
CD112
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
CD113
CD113
12
Issued Date
Issued Date
Issued Date
12
CD114
CD114
1
@
@
+
+
CD22
CD22
330U_B2_2VM_R15M
330U_B2_2VM_R15M
2
Compal Secret Data
Compal Secret Data
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P12-DDRIII Channel_A Lower
P12-DDRIII Channel_A Lower
P12-DDRIII Channel_A Lower
LA-A161P
LA-A161P
LA-A161P
1
12 49Wednesday, August 14, 2013
12 49Wednesday, August 14, 2013
12 49Wednesday, August 14, 2013
X02
X02
X02
5
4
3
2
1
follow INTEL PD G
1 2
CD24 0.047U_0402_16V4ZCD24 0.047U_0402_16V4Z
1 2
CD25 0.047U_0402_16V4ZCD25 0.047U_0402_16V4Z
1 2
D D
DDR_A_DQS#[0..7]12,6
DDR_A_DQS[0..7]12,6
DDR_A_D[0..63]12,6
DDR_A_MA[0..15]12,16,6
All VREF traces should
have 10 mil trace width
C C
B B
CD26 0.047U_0402_16V4ZCD26 0.047U_0402_16V4Z
1 2
CD27 0.047U_0402_16V4ZCD27 0.047U_0402_16V4Z
PLACE THESE CAPS
NEAR TO RESPECTIVE DRAM
+VREFCA
+VREFDQ_A
0.1U_0402_25V6K~D
DDR3_DRAMRST#12,14,15,5
CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN
0.1U_0402_25V6K~D
@
@
CD28
CD28
UD4
UD4
+VREFCA +VREFCA
+VREFDQ_A
DDR_A_BS012,16,6
DDR_A_BS112,16,6
DDR_A_BS212,16,6
M_CLK_A_DDR012,16,6
M_CLK_A_DDR#012,16,6
DDR_A_CKE012,16,6
DDR_A_CKE112,16,6
M_ODT012,16
DDR_A_CS0#12,16,6
DDR_A_CS1#12,16,6
DDR_A_RAS#12,16,6
DDR_A_CAS#12,16,6
DDR_A_WE#12,16,6
1
2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15 DDR_A_MA15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M_CLK_A_DDR0
M_CLK_A_DDR#0
DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS#4
DDR_A_DQS#5
DDR3_DRAMRST#
12
RD5 240_0402_1%RD5 240_0402_1%
12
RD81 240_0402_1%RD81 240_0402_1%
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_A_D39
F7
DDR_A_D37
F2
DDR_A_D34
F8
DDR_A_D32
H3
DDR_A_D35
H8
DDR_A_D33
G2
DDR_A_D38
H7
DDR_A_D36
D7
DDR_A_D44
C3
DDR_A_D47
C8
DDR_A_D45
C2
DDR_A_D46
A7
DDR_A_D41
A2
DDR_A_D42
B8
DDR_A_D40
A3
DDR_A_D43
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR +1.35V_DDR
+VREFDQ_A
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M_CLK_A_DDR0
M_CLK_A_DDR#0
DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#6
DDR_A_DQS#7
DDR3_DRAMRST#
12
RD6 240_0402_1%RD6 240_0402_1%
12
RD82 240_0402_1%RD82 240_0402_1%
UD5
UD5
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
J9
K1
J1
L2
L1
J3
K3
L3
F3
C7
G3
B7
E7
D3
T2
L8
L9
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC
BA0
BA1
BA2
CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC
RAS#
CAS#
WE#
DQSL
DQSU
DQSL#
DQSU#
DML
DMU
RESET#
ZQ0
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_A_D55
F7
DDR_A_D53
F2
DDR_A_D54
F8
DDR_A_D51
H3
DDR_A_D49
H8
DDR_A_D52
G2
DDR_A_D48
H7
DDR_A_D50
D7
DDR_A_D62
C3
DDR_A_D57
C8
DDR_A_D63
C2
DDR_A_D56
A7
DDR_A_D59
A2
DDR_A_D61
B8
DDR_A_D58
A3
DDR_A_D60
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
A A
5
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD37
CD37
CD38
CD38
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD39
CD39
CD40
CD40
1
1
2
2
10U_0603_6.3V6M~D
CD42
CD42
CD41
CD41
1
12
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD44
CD44
CD115
CD43
CD43
CD115
1
12
1
2
2
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD116
CD116
Issued Date
Issued Date
Issued Date
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD118
CD118
CD117
CD117
12
12
Compal Secret Data
Compal Secret Data
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
P13-DDRIII Channel_A Upper
P13-DDRIII Channel_A Upper
P13-DDRIII Channel_A Upper
LA-A161P
LA-A161P
LA-A161P
1
13 49Wednesday, August 14, 2013
13 49Wednesday, August 14, 2013
13 49Wednesday, August 14, 2013
A00
A00
A00
5
4
3
2
1
follow INTEL PD G
1 2
CD45 0.047U_0402_16V4ZCD45 0.047U_0402_16V4Z
1 2
CD46 0.047U_0402_16V4ZCD46 0.047U_0402_16V4Z
1 2
D D
C C
B B
CD47 0.047U_0402_16V4ZCD47 0.047U_0402_16V4Z
1 2
CD48 0.047U_0402_16V4ZCD48 0.047U_0402_16V4Z
PLACE THESE CAPS
NEAR TO RESPECTIVE DRAM
DDR_B_DQS#[0..7]15,6
DDR_B_DQS[0..7]15,6
DDR_B_D[0..63]15,6
DDR_B_MA[0..15]15,16,6
All VREF traces should
have 10 mil trace width
+VREFCA
+VREFDQ_B
0.1U_0402_25V6K~D
DDR3_DRAMRST#12,13,15,5
CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN
0.1U_0402_25V6K~D
@
@
CD49
CD49
UD6
UD6
+VREFCA
+VREFDQ_B
DDR_B_BS015,16,6
DDR_B_BS115,16,6
DDR_B_BS215,16,6
M_CLK_B_DDR015,16,6
M_CLK_B_DDR#015,16,6
DDR_B_CKE015,16,6
DDR_B_CKE115,16,6
M_ODT215,16
DDR_B_CS0#15,16,6
DDR_B_CS1#15,16,6
DDR_B_RAS#15,16,6
DDR_B_CAS#15,16,6
DDR_B_WE#15,16,6
1
2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15 DDR_B_MA15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
M_CLK_B_DDR0
M_CLK_B_DDR#0
DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS#2
DDR_B_DQS#3
12
RD7 240_0402_1%RD7 240_0402_1%
12
RD83 240_0402_1%RD83 240_0402_1%
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_B_D22
F7
DDR_B_D21
F2
DDR_B_D18
F8
DDR_B_D17
H3
DDR_B_D23
H8
DDR_B_D16
G2
DDR_B_D19
H7
DDR_B_D20
D7
DDR_B_D30
C3
DDR_B_D26
C8
DDR_B_D29
C2
DDR_B_D27
A7
DDR_B_D25
A2
DDR_B_D28
B8
DDR_B_D24
A3
DDR_B_D31
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR +1.35V_DDR
+VREFCA
+VREFDQ_B
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
M_CLK_B_DDR0
M_CLK_B_DDR#0
DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS#0
DDR_B_DQS#1
DDR3_DRAMRST#DDR3_DRAMRST#
12
RD8 240_0402_1%RD8 240_0402_1%
12
RD84 240_0402_1%RD84 240_0402_1%
UD7
UD7
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
DDR_B_D7
F7
DDR_B_D1
F2
DDR_B_D3
F8
DDR_B_D5
H3
DDR_B_D6
H8
DDR_B_D4
G2
DDR_B_D2
H7
DDR_B_D0
D7
DDR_B_D8
C3
DDR_B_D12
C8
DDR_B_D15
C2
DDR_B_D14
A7
DDR_B_D13
A2
DDR_B_D10
B8
DDR_B_D9
A3
DDR_B_D11
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD58
CD58
1
A A
5
1
2
2
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD59
CD59
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD61
CD61
CD60
CD60
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD63
CD63
CD62
CD62
1
12
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD64
CD64
12
1U_0402_6.3V6K~D
CD65
CD65
CD119
CD119
1
1
2
2
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD121
CD121
CD120
CD120
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
12
1
@
@
CD122
CD122
+
+
CD66
CD66
330U_B2_2VM_R15M
330U_B2_2VM_R15M
2
Compal Secret Data
Compal Secret Data
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P14-DDRIII Channel_B Lower
P14-DDRIII Channel_B Lower
P14-DDRIII Channel_B Lower
LA-A161P
LA-A161P
LA-A161P
1
14 49Wednesday, August 14, 2013
14 49Wednesday, August 14, 2013
14 49Wednesday, August 14, 2013
A00
A00
A00
5
4
3
2
1
follow INTEL PD G
1 2
CD68 0.047U_0402_16V4ZCD68 0.047U_0402_16V4Z
1 2
CD69 0.047U_0402_16V4ZCD69 0.047U_0402_16V4Z
1 2
DDR_B_DQS#[0..7]14,6
DDR_B_DQS[0..7]14,6
DDR_B_D[0..63]14,6
DDR_B_MA[0..15]14,16,6
CD70 0.047U_0402_16V4ZCD70 0.047U_0402_16V4Z
1 2
CD71 0.047U_0402_16V4ZCD71 0.047U_0402_16V4Z
PLACE THESE CAPS
NEAR TO RESPECTIVE DRAM
D D
All VREF traces should
have 10 mil trace width
C C
B B
+VREFCA
+VREFDQ_B
0.1U_0402_25V6K~D
DDR3_DRAMRST#12,13,14,5
CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN
0.1U_0402_25V6K~D
@
@
CD72
CD72
UD9
UD9
+VREFCA
+VREFDQ_B
DDR_B_BS014,16,6
DDR_B_BS114,16,6
DDR_B_BS214,16,6
M_CLK_B_DDR014,16,6
M_CLK_B_DDR#014,16,6
DDR_B_CKE014,16,6
DDR_B_CKE114,16,6
M_ODT214,16
DDR_B_CS0#14,16,6
DDR_B_CS1#14,16,6
DDR_B_RAS#14,16,6
DDR_B_CAS#14,16,6
DDR_B_WE#14,16,6
1
2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15 DDR_B_MA15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
M_CLK_B_DDR0
M_CLK_B_DDR#0
DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS#4
DDR_B_DQS#5
12
RD11 240_0402_1%RD11 240_0402_1%
12
RD85 240_0402_1%RD85 240_0402_1%
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_B_D39
F7
DDR_B_D33
F2
DDR_B_D38
F8
DDR_B_D37
H3
DDR_B_D34
H8
DDR_B_D32
G2
DDR_B_D35
H7
DDR_B_D36
D7
DDR_B_D45
C3
DDR_B_D47
C8
DDR_B_D44
C2
DDR_B_D42
A7
DDR_B_D40
A2
DDR_B_D46
B8
DDR_B_D41
A3
DDR_B_D43
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR +1.35V_DDR
+VREFCA
+VREFDQ_B
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
M_CLK_B_DDR0
M_CLK_B_DDR#0
DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#6
DDR_B_DQS#7
DDR3_DRAMRST#DDR3_DRAMRST#
RD12 240_0402_1%RD12 240_0402_1%
RD86 240_0402_1%RD86 240_0402_1%
12
12
UD10
UD10
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
T7
A14
M7
A15/NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE0
J9
CKE1/NC
K1
ODT0
J1
ODT1/NC
L2
CS0#
L1
CS1#/NC
J3
RAS#
K3
CAS#
L3
WE#
F3
DQSL
C7
DQSU
G3
DQSL#
B7
DQSU#
E7
DML
D3
DMU
T2
RESET#
L8
ZQ0
L9
ZQ1/NC
96-BALL
96-BALL
SDRAM DDR3L
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
MT41K256M16HA-125M:E_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
DDR_B_D48
F7
DDR_B_D52
F2
DDR_B_D50
F8
DDR_B_D55
H3
DDR_B_D53
H8
DDR_B_D51
G2
DDR_B_D54
H7
DDR_B_D49
D7
DDR_B_D60
C3
DDR_B_D62
C8
DDR_B_D61
C2
DDR_B_D63
A7
DDR_B_D57
A2
DDR_B_D58
B8
DDR_B_D56
A3
DDR_B_D59
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_DDR
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
A A
5
2
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD81
CD81
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD83
CD83
CD82
CD82
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD85
CD85
CD84
CD84
1
1
2
2
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD86
CD86
12
1U_0402_6.3V6K~D
CD88
CD88
CD87
CD87
1
12
2
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD124
CD124
Issued Date
Issued Date
Issued Date
10U_0603_6.3V6M~D
CD125
CD125
CD126
CD126
12
12
Compal Secret Data
Compal Secret Data
2011/06/02 2013/10/28
2011/06/02 2013/10/28
2011/06/02 2013/10/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD123
CD123
1
2
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P15-DDRIII Channel_B Upper
P15-DDRIII Channel_B Upper
P15-DDRIII Channel_B Upper
LA-A161P
LA-A161P
LA-A161P
1
15 49Wednesday, August 14, 2013
15 49Wednesday, August 14, 2013
15 49Wednesday, August 14, 2013
A00
A00
A00
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