DELL RS880M, SB820M Schematics

5

4

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Berry Discrete/UMA Schematics Document

D D

AMD Danube CPU S1g4

AMD GPU Madison-LP/M96-LP M2

C C

RS880M + SB820M

2010-03-08

B B

REV : A00

Wistron Corporation

A A

Title

DY : Nopop Component

5

4

3

Size Document Number Rev

A4

Date: Sheet of

2

Berry AMD Discrete/UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

1 95Monday, March 08, 2010

1

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CHARGER

Project code :91.4HH01.001

Berry DG15 Discrete/UMA Block Diagram

PCB P/N : Revision :X-Build

AMD Champlain

D D

VRAM

64Mx16bx8 (1GB)

85,86,87,88

4

CPU S1G4

35W Max

8,9,10,11

DDR III 1333

DDRIII 800/1066/1333

DDR3 800MHz

OUT

AMD Graphic

M96-M2 LP

HDMI

C C

LCD Conn

(LVDS & Camera Conn.)

57

54

HDMI(Share PCIe x 4)

LVDS(Dual Channel)

80,81,82,83

PCIe x 16

North Bridge

CPU I/F

AMD RS880M

LVDS, CRT I/F

INTEGRATED GRAHPICS

HyperTransport 16X16

IN

12,13,14,15

SIDE-PORT

64Mx16bx1 (1GB)

A-LINK 4X4

CRT

RGB CRT

South Bridge

AMD SB820M

CRT Board

USB x 2

B B

CardReader

Connector

77

Realtek RTS5159

USB2.0 x 2

Card Reader Connector

78

USB2.0

14 USB 2.0 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

2 PCIE GPP

6 SATA ports

ACPI 1.1

LPC I/F

PCI/PCI BRIDGE

20,21,22,23,24

USB 2.0

LPC Bus

SD/SDIO/MMC MS/MS Pro/xD

Azalia

Internal Analog MIC

MIC IN

A A

HP1

CODEC &

OP AMP

IDT 92HD79B1

AZALIA

30

SATA

HDD

59 59

SATA

ODD

SPI

Flash ROM

2MB

NUVOTON

NPCE781BA0DX

Touch

62 68 25

PAD

2CH SPEAKER

5

4

3

DIMM1

DIMM2

VRAM

PCIE x 1

USB 2.0 x 1

SATA x 1

PCIE x 2& USB 2.0 x 2

KBC

68

KB

18

19

14

37

USB 2.0 x 1

ThermalInt.

EMC2102

Fan

58

2

I/O Board

Connector

76

Camera Conn

(LVDS & Camera Conn.)

Bluetooth Conn

39

RJ45 CONN

10/100 NIC

Realtek RTL8103T

USB x 1

E-SATA/USB COMBO

MiniCard x 2

WLAN&WWAN

54

73

Title

Block Diagram

Size Document N umber Rev

A3

Date: Sheet of

BQ24745

INPUTS

+DC_IN_SS

+VCHGR

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

RT8205B

INPUTS

+PWR_SRC

OUTPUTS

+3.3V_RTC_LDO +5V_ALW +3.3V_ALW

CPU VDDR

RT9025

INPUTS OUTPUTS

+1.5V_SUS

+CPU_VDDR

CPU CORE

ISL6265AHRTZ-T-GP

INPUTS

+PWR_SRC

OUTPUTS

+VCC_CORE +VDDNB

AMD RS880M CORE

RT8209

INPUTS OUTPUTS

+PWR_SRC

+NB_VDDC

AMD SB820M S5 POWER

RT9025

INPUTS

+3.3V_ALW

OUTPUTS

+1.1V_ALW

DDR III SUS&VTT

RT8207

INPUTS

+PWR_SRC

OUTPUTS

+1.5V_SUS

DDR III SUS&VTT

RT8207

INPUTS

+PWR_SRC

OUTPUTS

+0.75V_DDR_VTT

AMD GPU CORE

RT8208B

INPUTS

OUTPUTS

+VGA_CORE+PWR_SRC

PCB LAYER

L1: Top L2: VCC L3: Signal L4: Signal L5: GND L6: Bottom

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

2 95Thursday, March 04 , 2010

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48

47

50

48

49

89

A00

45

A

B

C

D

E

Power Shape

Regulator LDO Switch

Power Block Diagram

4 4

Adapter

+PWR_SRC

ISL6265AHRTZ RT8209EGQW RT8207

RT8208B

AO4407A

Charger

BQ24745

Battery

3 3

+3.3V_RTC_LDO

2 2

+VCHGR

UP7534

+5V_USB1

RESISTER

RT8205B

+5V_ALW

AO4468

+5V_RUN

RESISTER

+VCC_CORE

UP7534

+5V_USB2

+VDDNB(CPU)

SI2301BDS

G5285T11U

AO4468

+3.3V_RUN

RTS5159

+1.1V_RUN

+3.3V_ALW

RT9013-25PB

PA102FMG

+3.3V_LAN

RTL8103T

+1.5V_SUS+VGA_CORE

AO4468

+1.5V_RUN

+1.8V_RUN

AO4468 APL5930

+1.5V_RUN_VGA +1.0V_RUN_VGA

APL5930

+1.8V_RUN_VGA

RT9025

VDDR(CPU)

RT9025

+1.1V_ALW

+PVDD

1 1

A

+AVDD

+3.3V_RUN_VGA

B

+LCDVDD

+3.3V_RUN_CARD

+2.5V_RUN

C

+1.2V_LOM

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

D

Date: Sheet of

Power Block Diagram

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

3 95Thursday, March 04 , 2010

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SB820M SMBus Block Diagram

D D

+3.3V_RUN

CLK GEN

SB_SMBCLK

SRN2K2J

SB820M

C C

B B

SCL0 SDA0

SCL1

SDA1

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

SMB_CLK

SMB_DATA

CPU_SIC

CPU_SID

SB_SMBCLK_R SB_SMBDATA_R

+3.3V_ALW

SRN10KJ-5-GP

SRN1KJ-7-GP

SB_SMBDATA

+1.5V_SUS

SCL SDA

SMBus Address:0xD2

SB_SMBCLK

SB_SMBDATA

DIMM 1

SCL

SDA

SMBus Address:0xA0,0x30

SB_SMBCLK

SB_SMBDATA

DIMM 2

SCL

SDA

SMBus Address:0xA4,0x34

WWAN MINI CARD

SB_SMBCLK

SMB_CLK

SB_SMBDATA

SMB_DATA

SMBus address:

WLAN MINI CARD

SMB_CLKSB_SMBCLK

SMB_DATA

SB_SMBDATA

SMBus address:

CPU S1G4

SIC

CPU_SIC

SID

CPU_SID

NPCE781

KBC SMBus Block Diagram

+5V_RUN

SRN10KJ-5-GP

TPDATA

KBC

PSDAT1

GPIO61/SCL2

GPIO62/SDA2

SCL1

SDA1

TPCLKPSCLK1

BAT_SCL

BAT_SDA

KBC_SCL1

KBC_SDA1

+KBC_PWR

+3.3V_ALW

SRN4K7J-8-GP

SRN100J-3-GP

2N7002SPT

PBAT_SMBCLK1

PBAT_SMBDAT1

+3.3V_RUN

TPDATA

TPCLK

+3.3V_RUN

TouchPad Conn.

TPDATA

TPCLK

SMBus address:

Battery Conn.

CLK_SMB

DAT_SMB

BQ24745RHDR

SCL

SDA

SMBus address:0x12

SRN4K7J-8-GP

THERM_SCL

THERM_SDA

SMBus address:0x7A

Thermal

SCL

SDA

SMBus address:

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

SMBUS BLOCK DIAGRAM

Size Document Num ber Rev

A2

Date: Sheet of

5

4

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Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

1

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Thermal Block Diagram

D D

CPU

H_THERMDA

DP1

SC470P50V3JN-2G P

H_THERMDC

C C

DN1

Thermal EMC2102

DP2

VGA_THERMDA

SC470P50V3JN-2G P

DN2

VGA_THERMDC

THERMDA

THERMDC

DPLUS

DMINUS

GPU

PMBS3904

Audio Block Diagram

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

HP1_PORT_B_L

HP1_PORT_B_R

Codec 92HD79B1

VREFOUT_A_OR_F

HP0_PORT_A_L

HP0_PORT_A_R

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

AUD_HP1_JACK_L

AUD_HP1_JACK_R

AUD_VREFOUT_B

AUD_EXT_MIC_L

AUD_EXT_MIC_R

60D4R2F

4K7R2J-2-GP

AUD_HP1_JACK_L1

Bead

AUD_HP1_JACK_R1

Bead

4K7R2J-2-GP

SPEAKER

60

HP

OUT

60

MIC

IN

60

B B

SC1U10V3KX-3GP

EMC2102_DP3

DP3

PMBS3904

DN3

SC470P50V3JN-2G P

EMC2102_DN3

System sensor, put between CPU and NB.

A A

5

4

3

PORT_C_L

PORT_C_R

VREFOUT_C

AUD_INT_MIC_R_L

AUD_VREFOUT_C

30

4K7R2J-2-GP

2

Title

Size Document N umber Rev

A3

Date: Sheet of

INT_MIC_L_R

Internal MIC

60

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

THERMAL/AUDIO BLOCK DIAGRAM

Berry AMD Discrete/UMA

5 95Thursday, March 04 , 2010

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SB820M Strapping

Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide

Name Strap Name Schematic Note

LPCCLK0

D D

EC_PWM3 EC_PWM2

LPCCLK1

PCICLK1

C C

ECEnableStrap

{ROMTYPE_1, ROMTYPE_0 }

CLKGEN

BIF_GEN2_ COMPLIANCE_Strap

PCICLK2 BootFailTmrEn

PCICLK3 DefaultStrapMode

PCICLK4 CPUClkSel

AZ_SDOUT CoreSpeedMode

B B

Embedded Controller (EC)

0 V – Disabled

*

3.3 V - Enabled

ROMTYPE_1 ROMTYPE_0 ROM TYPE

3.3V 0V

3.3V 3.3V

0V 0V

0V 3.3V

*

SPI ROM

Reserved

Firmware Hub

LPC ROM (supports both LPC and PMC ROM types)

Defines clock generator

*

External clock mode: Use 100-M Hz PCIeR

0V –

clock as reference clock and g enerate i nternal clocks only.

Integrated clock mode: Use 25- MHz crystal

3.3V–

clock and generate both intern al and external clocks

Set PCIe to Gen II mode

Force PCIe interface at Gen I mode

0V–

PCIe interfacce is at Gen II m ode

*

3.3V-

Not Applicable to SB820M but p rovision for pull-down is required.

Watchdog function

*

Disable the boot fail timer fu nction

0V–

Enable the boot fail timer fu nction

3.3V-

Default Debug Straps

Disable Debug Straps.

0V–

Select external Debug Straps

3.3V–

CPU/NB HT Clock Selection

Reserved.

0V–

*

Required setting for integrate d clock mode.

3.3V–

This strap is not used if the strap CLKGEN is configured for external clock generator mode.

Slow down core clock for low power platform.

0V–

3.3V-

Performance mode

Low Power mode

*

RS880M Strapping

Capture from 46113_rs880m_ds_nda_1.03

DAC_VSYNC

DAC_HSYNC

SUS_STAT#

STRAP_DEBUG_BUS_GPIO _ENABLE#

SIDE_PORT_EN#

LOAD_EEPROM_STRAPS#

Enables debug bus access through memory I/O pads and GPIOs. 0: Enable 1: Disable

*

Indicates if memory side-port is available or not 0: Available(UMA) 1: Not available(Discrete)

Selects loading of strap values from EEPROM. 0: I2C master can load strap values from EEPROM if connected, or use default values if EEPROM is not connected. Please refer to RS880M's reference schematics for system level implementation details. 1: Use default values

*

USB Table PCIE Routing

Pair

USB

Device

USB0 (I/O Board/ESATA)

0

USB1 (I/O Board)

1

USB2 (CRT Board)

2

USB3 (CRT Board)

3

WLAN USB

4

WWAN USB

5

RESERVED

6

RESERVED

7

RESERVED

8

BLUETOOTH

9

CARD READER

10

CAMERA (LVDS CONN)

11

RESERVED

12

RESERVED

13

LANE1

LANE2

MiniCard WLANLANE0

MiniCard WWAN

Schematic NoteStrap FunctionName

RS880M

LAN

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Table of Content

Size Document Num ber Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

1

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+3.3V_CL K_VDD+3.3V_RU N

R702

1 2

0R0603-P AD

1231-1

D D

SC10U6D3V5KX-1GP

12

C701

9/22

+3.3V_RU N +3.3V_ CLK_VDDIO

R703

1 2

0R0603-P AD

1231-1

SC10U6D3V5KX-1GP

12

C710

DY

9/22

+3.3V_RU N +3.3V_ CLK_VDDREF

R701

1 2

0R0603-P AD

C C

1231-1

1119-3

SB_PW RGD(21 ,41)

WLAN(100MHz)

WWAN(100MHz)

LAN(100MHz)

B B

VGA(27MHz)

NB(100MHz)

SB(100MHz)

TP701TP701 TP702TP702 TP703TP703 TP704TP704 TP705TP705 TP706TP706

A A

TP707TP707 TP709TP709 TP708TP708

TP_CLK_ SRC6

1

TP_CLK_ SRC6#

1

TP_CLKR EQ0#

1

TP_CLKR EQ3#

1

TP_CLKR EQ4#

1

TP_CLK_ SRC4

1

TP_CLK_ SRC4#

1

R_NB_GP P_CLK

1

R_NB_GP P_CLK#

1

CLK_PCIE_ WLAN(76) CLK_PCIE_ WLAN#(76)

CLK_PCIE_ WWAN(76) CLK_PCIE_ WWAN#(76)

CLK_PCIE_ LAN(76) CLK_PCIE_ LAN#(76)

CLK_VGA _27M_SS(82) CLK_VGA _27M_NSS(82)

NB_GPPS B_CLK(13) NB_GPPS B_CLK#(13)

SB_PCIE_C LK(20) SB_PCIE_C LK#(20)

CLK_NBH T_CLK(13) CLK_NBH T_CLK#(13)

5

12

SCD1U10V2KX-5GP

9/22

C721

1113-2

+3.3V_CLK_VDD (40 mils)

12

C703

C704

SCD1U10V2KX-5GP

12

C712

C713

SCD1U10V2KX-5GP

R706

1 2

DY

0R2J-2-GP

RN702

2 3 1

0R4P2R-P AD

RN710

2 3 1

0R4P2R-P AD

RN703

2 3 1

0R4P2R-P AD

R713 47R2J-2-G P

1 2

R714 33R2J-2-G P

1 2

RN704

2 3 1

0R4P2R-P AD

RN705

2 3 1

0R4P2R-P AD

RN706

2 3 1

0R4P2R-P AD

10/1

12

SCD1U10V2KX-5GP

12

SCD1U10V2KX-5GP

+3.3V_RU N

10KR2J-3-GP

RN

DIS

DIS DIS

DIS

RN

12

C705

SCD1U10V2KX-5GP

12

C714

SCD1U10V2KX-5GP

12

R705

EC702

EC702 SC10P50 V2JN-4GP

SC10P50 V2JN-4GP

DY

4

10/5

4

10/5

4

12

C706

SCD1U10V2KX-5GP

12

C715

SCD1U10V2KX-5GP

+3.3V_CL K_VDDREF

12

C708

C707

SCD1U10V2KX-5GP

1119-3

12

C717

C716

SCD1U10V2KX-5GP

+3.3V_CL K_VDDIO

CLKGEN_ PD#

R_VGA_2 7M_SS_CLK R_VGA_2 7M_NSS_CLK

NB_GPPS B_CLK_R NB_GPPS B_CLK#_R SB_PCIE_C LK_R SB_PCIE_C LK#_R

CLK_NBH T_CLK_R CLK_NBH T_CLK#_R

1119-3

12

C709

SCD1U10V2KX-5GP

+3.3V_CL K_VDD

R_NB_GP P_CLK R_NB_GP P_CLK# CLK_MINI1_R CLK_MINI1#_R CLK_SRC 2 CLK_SRC 2# LAN_CLK _R LAN_CLK #_R TP_CLK_ SRC4 TP_CLK_ SRC4# TP_CLK_ SRC6 TP_CLK_ SRC6#

4

U701

26

VDDATIG

25

VDDATIG_IO

48

VDDCPU

47

VDDCPU_IO

16

VDDSRC

17

VDDSRC_IO

11

VDDSRC_IO

35

VDDSB_SRC

34

VDDSB_SRC_IO

40

VDDSATA

4

VDD

55

VDDHTT

56

VDDREF

63

VDD48

51

PD#

22

SRC0T_LPRS

21

SRC0C_LPRS

20

SRC1T_LPRS

19

SRC1C_LPRS

15

SRC2T_LPRS

14

SRC2C_LPRS

13

SRC3T_LPRS

12

SRC3C_LPRS

9

SRC4T_LPRS

8

SRC4C_LPRS SRC6T/SATAT_LPRS42GNDSATA

41

SRC6C/SATAC_LPRS

6

SRC7T_LPRS/27MHZ_SS

5

SRC7C_LPRS/27MHZ_NS

37

SB_SRC0T_LPRS

36

SB_SRC0C_LPRS

32

SB_SRC1T_LPRS

31

SB_SRC1C_LPRS

54

HTT0T_LPRS/66M

53

HTT0C_LPRS/66M

ICS9LPRS4 80BKLFT-GP

71.09480.A03

1st 71.09480.A03 2nd 71.08628.003

ATIG0T_LPRS

ATIG0C_LPRS

ATIG1T_LPRS

ATIG1C_LPRS

CPUKG0T_LPRS CPUKG0C_LPRS

REF0/SEL_HTT66

REF1/SEL_SATA

NB ALINK (100MHz)

SB PCIE (100MHz)

VGA Madison (27MHz)

SMBCLK SMBDAT

CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

48MHZ_0

REF2/SEL_27

GNDATIG

GND

GNDHTT GNDREF GNDCPU

GND48

GNDSRC GNDSRC

GNDSB_SRC

GND

X1 X2

61 62

2 3

30 29 28 27

23 45 44 39 38

50 49

64

59 58 57

43 24 7 52 60 46 1

10 18

33

65

SEL_HTT66 FS0

SEL_SATA FS1

SEL_27MHz FS2

* default

3

CLKGEN_ X1 CLKGEN_ X2

SB_SMBC LK_CK SB_SMBD ATA_CK

GFX_CLK P GFX_CLK N

NB_GFX_ CLK_R NB_GFX_ CLK_R#

10/2

TP_CLKR EQ0# WLA N_CLK_REQ# WW AN_CLK_REQ # TP_CLKR EQ3# TP_CLKR EQ4#

CPU_HT_ CLK CPU_HT_ CLK#

48M_CLK

FS0 SB_14M_ CLK FS2

1

*0

1*

0

1

*

0

X-14D31818M-37GP

12

R704

DY

RN712

4

SRN33J-5 -GP-U

RN709

4

SRN0J-6-G P

4

X-14D31818M-37GP

12

10/1

0114-2

1 2 3

1

DIS

2 3

0R4P2R-P AD

1 2 3

RN707

1MR2J-L2-GP

RN

9/23

RN

0R4P2R-P AD

1

4

2 3

RN708

R710 22R2J-2-G PR710 22R2J -2-GP

1 2

SC4D7P50V2CN-1GP

1116-9

EC703

12

DY

R715 158R2F-G PR715 158R2F-G P

66 MHz 3.3V single ended HTT clock

100 MHz differential HTT clock

100 MHz non-spreading differential SRC clock

100 MHz spreading differential SRC clock 27MHz non-spreading singled clock on pin 5 and 27MHz spread clock on pin 6

100MHz differential spreading SRC clock

For EMI

1 2

Place together

C718

1 2

SC12P50 V2JN-3GP

X701

C719

1 2

SC12P50 V2JN-3GP

SB_SMBC LK_R (18,21) SB_SMBD ATA_R (18,21)

CLK_PCIE_ VGA (8 0) CLK_PCIE_ VGA# (80)

NB_GFX_ CLK (13) NB_GFX_ CLK# (13)

WLA N_CLK_REQ# (76)

WW AN_CLK_REQ # (76)

CPU_CLK (10) CPU_CLK # (10)

USB_48M _CLK (21)

CLKREQ# MAP

CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

0107-1

SB_SMBC LK_CK SB_SMBD ATA_CK

VGA(100MHz)

CPU_CLK(200MHz)

SB820M_USB(48MHz)

+3.3V_RU N

8K2R2J-3-GP

12

R711

R712

0105-3

90D9R2F-1-GP

8K2R2J-3-GP

12

R718

R717

DY

Title

Clock Generator ICS9LPRS480

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

No use CLKSRC1 WLAN CLKSRC2 WWAN CLKSRC3 LAN No use

1 2

C722 SC47P50V 2JN-3GPC722 SC47P50V 2JN-3GP

1 2

C723 SC47P50V 2JN-3GPC723 SC47P50V 2JN-3GP

Need External PU Resistor

WLA N_CLK_REQ# WW AN_CLK_REQ #

CPU_CLK CPU_CLK #

SC10P50V2JN-4GPDYEC704

SC10P50V2JN-4GP

EC704

DY

0105-1

EC705

SC10P50V2JN-4GPDYEC705

SC10P50V2JN-4GP

12

DY

0225-2

NB_14M_ CLK (13) SB_14M_ CLK (21)

Berry AMD Discrete/UMA

NB OSCIN(14MHz) SB OSCIN(14MHz)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN711

1 2 3

SRN10KJ -5-GP

7 95Thursday, March 04 , 2010

+3.3V_RU N

4

A00

5

4

3

2

1

+1.1V_RUN

SSID = CPU

D D

C C

SC22U6D3V5MX-2GP

C801

12

SKT-BGA638H176

B B

1'nd 62.10055.111 2'nd 62.10055.171

Place close to socket

SC4D7U6D3V3KX-GP

12

DY

SC4D7U6D3V3KX-GP

C802

DY

SCD22U10V2KX-1GP

C803

12

SCD22U10V2KX-1GP

C804

12

1119-3

HT_NB_CPU_CAD_H0(12) HT_NB_CPU_CAD_L0(12) HT_NB_CPU_CAD_H1(12) HT_NB_CPU_CAD_L1(12) HT_NB_CPU_CAD_H2(12) HT_NB_CPU_CAD_L2(12) HT_NB_CPU_CAD_H3(12) HT_NB_CPU_CAD_L3(12) HT_NB_CPU_CAD_H4(12) HT_NB_CPU_CAD_L4(12) HT_NB_CPU_CAD_H5(12) HT_NB_CPU_CAD_L5(12) HT_NB_CPU_CAD_H6(12) HT_NB_CPU_CAD_L6(12) HT_NB_CPU_CAD_H7(12) HT_NB_CPU_CAD_L7(12) HT_NB_CPU_CAD_H8(12) HT_NB_CPU_CAD_L8(12) HT_NB_CPU_CAD_H9(12) HT_NB_CPU_CAD_L9(12) HT_NB_CPU_CAD_H10(12) HT_NB_CPU_CAD_L10(12) HT_NB_CPU_CAD_H11(12) HT_NB_CPU_CAD_L11(12) HT_NB_CPU_CAD_H12(12) HT_NB_CPU_CAD_L12(12) HT_NB_CPU_CAD_H13(12) HT_NB_CPU_CAD_L13(12) HT_NB_CPU_CAD_H14(12) HT_NB_CPU_CAD_L14(12) HT_NB_CPU_CAD_H15(12) HT_NB_CPU_CAD_L15(12)

HT_NB_CPU_CLK_H0(12) HT_NB_CPU_CLK_L0(12) HT_NB_CPU_CLK_H1(12) HT_NB_CPU_CLK_L1(12)

HT_NB_CPU_CTL_H0(12) HT_NB_CPU_CTL_L0(12) HT_NB_CPU_CTL_H1(12) HT_NB_CPU_CTL_L1(12)

SC180P50V2JN-1GP

C805

12

DY

SC180P50V2JN-1GP

C806

12

C807

12

1.1V(1.5A) for VLDT

CPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

DANUBE

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

1 OF 6

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

HT_CPU_NB_CAD_H0 (12) HT_CPU_NB_CAD_L0 (12) HT_CPU_NB_CAD_H1 (12) HT_CPU_NB_CAD_L1 (12) HT_CPU_NB_CAD_H2 (12) HT_CPU_NB_CAD_L2 (12) HT_CPU_NB_CAD_H3 (12) HT_CPU_NB_CAD_L3 (12) HT_CPU_NB_CAD_H4 (12) HT_CPU_NB_CAD_L4 (12) HT_CPU_NB_CAD_H5 (12) HT_CPU_NB_CAD_L5 (12) HT_CPU_NB_CAD_H6 (12) HT_CPU_NB_CAD_L6 (12) HT_CPU_NB_CAD_H7 (12) HT_CPU_NB_CAD_L7 (12) HT_CPU_NB_CAD_H8 (12) HT_CPU_NB_CAD_L8 (12) HT_CPU_NB_CAD_H9 (12) HT_CPU_NB_CAD_L9 (12) HT_CPU_NB_CAD_H10 (12) HT_CPU_NB_CAD_L10 (12) HT_CPU_NB_CAD_H11 (12) HT_CPU_NB_CAD_L11 (12) HT_CPU_NB_CAD_H12 (12) HT_CPU_NB_CAD_L12 (12) HT_CPU_NB_CAD_H13 (12) HT_CPU_NB_CAD_L13 (12) HT_CPU_NB_CAD_H14 (12) HT_CPU_NB_CAD_L14 (12) HT_CPU_NB_CAD_H15 (12) HT_CPU_NB_CAD_L15 (12)

HT_CPU_NB_CLK_H0 (12) HT_CPU_NB_CLK_L0 (12) HT_CPU_NB_CLK_H1 (12) HT_CPU_NB_CLK_L1 (12)

HT_CPU_NB_CTL_H0 (12) HT_CPU_NB_CTL_L0 (12) HT_CPU_NB_CTL_H1 (12) HT_CPU_NB_CTL_L1 (12)

Wistron Corporation

A A

Title

CPU_HT_LINK I/F_(1/4)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Berry AMD Discrete/UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

8 95Thursday, March 04, 2010

1

A00

5

SSID = CPU

1231-2

Set empty: C905,C906,C903,C909,C913,C910,C915

D D

+CPU_VD DR

SC4D7U6D3V3KX-GP

C901

12

C C

+1.5V_SU S

R901 39D2R2F -L-GPR901 39D2R2F -L-GP R903 39D2R2F -L-GPR903 39D2R2F -L-GP

12

C917

SC10U6D3V3MX-GP

B B

MEM_MA_ ADD[0..15](18) MEM_MB_ ADD[0..15] (19)

A A

SC4D7U6D3V3KX-GP

C902

12

1 2 1 2

DDR3_A_ DRAMRST#(18)

MEM_MA0 _ODT0(18 ) MEM_MA0 _ODT1(18 )

MEM_MA0 _CS#0(18) MEM_MA0 _CS#1(18)

MEM_MA_ CKE0(18) MEM_MA_ CKE1(18)

MEM_MA_ CLK0_P(18) MEM_MA_ CLK0_N(18 )

MEM_MA_ CLK1_P(18) MEM_MA_ CLK1_N(18 )

MEM_MA_ BANK0(18) MEM_MA_ BANK1(18) MEM_MA_ BANK2(18)

MEM_MA_ RAS#(18) MEM_MA_ CAS#(18) MEM_MA_ WE#(18)

5

C903

12

DY

Place near to CPU

SC4D7U6D3V3KX-GP

SCD22U10V2KX-1GP

C913

C904

12

DY

C904

12

+CPU_VD DR

MEMZN

MEM_MA_ ADD0 MEM_MA_ ADD1 MEM_MA_ ADD2 MEM_MA_ ADD3 MEM_MA_ ADD4 MEM_MA_ ADD5 MEM_MA_ ADD6 MEM_MA_ ADD7 MEM_MA_ ADD8 MEM_MA_ ADD9 MEM_MA_ ADD10 MEM_MA_ ADD11 MEM_MA_ ADD12 MEM_MA_ ADD13 MEM_MA_ ADD14 MEM_MA_ ADD15

SCD22U10V2KX-1GP

C914

12

1119-3

D10 C10 B10

AD10

AF10

AE10

H16

T19 V22 U21 V19

T20 U19 U20 V20

J22 J20

N19 N20 E16 F16 Y16

AA16

P19 P20

N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19

R20 R23

J21

R19 T22 T24

SCD22U10V2KX-1GP

C905

12

DY

0.9V, 1.25A--DDR1066

1.05V, 1.75A---DDR1333

CPU1B

VDDR VDDR VDDR VDDR

MEMZP MEMZN

MA_RESET#

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS#0 MA0_CS#1 MA1_CS#0 MA1_CS#1

MA_CKE0 MA_CKE1

MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_RAS# MA_CAS# MA_WE#

SC4D7U6D3V3KX-GP

C906

1231-2

DANUBE

VDDR_SENSE

4

SC1000P50V3JN-GP-U

C907

12

2 OF 6

VDDR VDDR VDDR VDDR VDDR

MEMVREF

MB_RESET#

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS#0 MB0_CS#1 MB1_CS#0

MB_CKE0 MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_RAS# MB_CAS#

MB_WE#

4

C915

12

DY

W10 AC10 AB10 AA10 A10

Y10

W17

B18

W26 W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24

R24 U26 J26

U25 U24 U23

SC1000P50V3JN-GP-U

C908

12

DY

TP_CPU_ VDDR_SENSE

MEM_MB_ ADD0 MEM_MB_ ADD1 MEM_MB_ ADD2 MEM_MB_ ADD3 MEM_MB_ ADD4 MEM_MB_ ADD5 MEM_MB_ ADD6 MEM_MB_ ADD7 MEM_MB_ ADD8 MEM_MB_ ADD9 MEM_MB_ ADD10 MEM_MB_ ADD11 MEM_MB_ ADD12 MEM_MB_ ADD13 MEM_MB_ ADD14 MEM_MB_ ADD15

4.7UF*4

0.22UF*4 1000PF*4 180PF*4

SC180P50V2JN-1GP

C909

C910

12

DY

+0.75V_S US_CPU_M_VRE F

TP901DYTP901

1

DY

DDR3_B_ DRAMRST# (19 )

MEM_MB0 _ODT0 (19) MEM_MB0 _ODT1 (19)

MEM_MB0 _CS#0 (19) MEM_MB0 _CS#1 (19)

MEM_MB_ CKE0 (19) MEM_MB_ CKE1 (19)

MEM_MB_ CLK0_P (19) MEM_MB_ CLK0_N (1 9)

MEM_MB_ CLK1_P (19) MEM_MB_ CLK1_N (1 9)

MEM_MB_ BANK0 (19) MEM_MB_ BANK1 (19) MEM_MB_ BANK2 (19)

MEM_MB_ RAS# (19) MEM_MB_ CAS# (19) MEM_MB_ WE# (19)

12

SC180P50V2JN-1GP

C911

1119-1

C916

12

1119-3

SC1000P50V3JN-GP-U

12

3

SC180P50V2JN-1GP

SCD1U10V2KX-5GP

C919

3

C912

12

+1.5V_SU S

1KR3F-GP

12

C918

R902

12

R902

1KR3F-GP

12

R905

C920

CLOSE TO CPU

M_A_DQ[6 3..0](18)

1117-8 Remove

M_A_DM[7 ..0](18)

2

3 OF 6

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ1 0 M_A_DQ1 1 M_A_DQ1 2 M_A_DQ1 3 M_A_DQ1 4 M_A_DQ1 5 M_A_DQ1 6 M_A_DQ1 7 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 0 M_A_DQ2 1 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ2 4 M_A_DQ2 5 M_A_DQ2 6 M_A_DQ2 7 M_A_DQ2 8 M_A_DQ2 9 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ3 2 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 5 M_A_DQ3 6 M_A_DQ3 7 M_A_DQ3 8 M_A_DQ3 9 M_A_DQ4 0 M_A_DQ4 1 M_A_DQ4 2 M_A_DQ4 3 M_A_DQ4 4 M_A_DQ4 5MEMZP M_A_DQ4 6 M_A_DQ4 7 M_A_DQ4 8 M_A_DQ4 9 M_A_DQ5 0 M_A_DQ5 1 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ5 6 M_A_DQ5 7 M_A_DQ5 8 M_A_DQ5 9 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 2 M_A_DQ6 3

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS 0(18) M_A_DQS #0(18) M_A_DQS 1(18) M_A_DQS #1(18) M_A_DQS 2(18) M_A_DQS #2(18) M_A_DQS 3(18) M_A_DQS #3(18) M_A_DQS 4(18) M_A_DQS #4(18) M_A_DQS 5(18) M_A_DQS #5(18) M_A_DQS 6(18) M_A_DQS #6(18) M_A_DQS 7(18) M_A_DQS #7(18)

G12

MA_DATA0

F12

MA_DATA1

H14

MA_DATA2

G14

MA_DATA3

H11

MA_DATA4

H12

MA_DATA5

C13

MA_DATA6

E13

MA_DATA7

H15

MA_DATA8

E15

MA_DATA9

E17

MA_DATA10

H17

MA_DATA11

E14

MA_DATA12

F14

MA_DATA13

C17

MA_DATA14

G17

MA_DATA15

G18

MA_DATA16

C19

MA_DATA17

D22

MA_DATA18

E20

MA_DATA19

E18

MA_DATA20

F18

MA_DATA21

B22

MA_DATA22

C23

MA_DATA23

F20

MA_DATA24

F22

MA_DATA25

H24

MA_DATA26

J19

MA_DATA27

E21

MA_DATA28

E22

MA_DATA29

H20

MA_DATA30

H22

MA_DATA31

Y24

MA_DATA32

AB24

MA_DATA33

AB22

MA_DATA34

AA21

MA_DATA35

W22

MA_DATA36

W21

MA_DATA37

Y22

MA_DATA38

AA22

MA_DATA39

Y20

MA_DATA40

AA20

MA_DATA41

AA18

MA_DATA42

AB18

MA_DATA43

AB21

MA_DATA44

AD21

MA_DATA45

AD19

MA_DATA46

Y18

MA_DATA47

AD17

MA_DATA48

W16

MA_DATA49

W14

MA_DATA50

Y14

MA_DATA51

Y17

MA_DATA52

AB17

MA_DATA53

AB15

MA_DATA54

AD15

MA_DATA55

AB13

MA_DATA56

AD13

MA_DATA57

Y12

MA_DATA58

W11

MA_DATA59

AB14

MA_DATA60

AA14

MA_DATA61

AB12

MA_DATA62

AA12

MA_DATA63

E12

MA_DM0

C15

MA_DM1

E19

MA_DM2

F24

MA_DM3

AC24

MA_DM4

Y19

MA_DM5

AB16

MA_DM6

Y13

MA_DM7

G13

MA_DQS_H0

H13

MA_DQS_L0

G16

MA_DQS_H1

G15

MA_DQS_L1

C22

MA_DQS_H2

C21

MA_DQS_L2

G22

MA_DQS_H3

G21

MA_DQS_L3

AD23

MA_DQS_H4

AC23

MA_DQS_L4

AB19

MA_DQS_H5

AB20

MA_DQS_L5

Y15

MA_DQS_H6

W15

MA_DQS_L6

W12

MA_DQS_H7

W13

MA_DQS_L7

2

CPU1C

M_B_DQ0

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3

DANUBE

MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DQS_H0

MB_DQS_L0

MB_DQS_H1

MB_DQS_L1

MB_DQS_H2

MB_DQS_L2

MB_DQS_H3

MB_DQS_L3

MB_DQS_H4

MB_DQS_L4

MB_DQS_H5

MB_DQS_L5

MB_DQS_H6

MB_DQS_L6

MB_DQS_H7

MB_DQS_L7

Title

Size Document N umber Rev

A3

Date: Sheet of

C11

M_B_DQ1

A11

M_B_DQ2

A14

M_B_DQ3

B14

M_B_DQ4

G11

M_B_DQ5

E11

M_B_DQ6

D12

M_B_DQ7

A13

M_B_DQ8

A15

M_B_DQ9

A16

M_B_DQ1 0

A19

M_B_DQ1 1

A20

M_B_DQ1 2

C14

M_B_DQ1 3

D14

M_B_DQ1 4

C18

M_B_DQ1 5

D18

M_B_DQ1 6

D20

M_B_DQ1 7

A21

M_B_DQ1 8

D24

M_B_DQ1 9

C25

M_B_DQ2 0

B20

M_B_DQ2 1

C20

M_B_DQ2 2

B24

M_B_DQ2 3

C24

M_B_DQ2 4

E23

M_B_DQ2 5

E24

M_B_DQ2 6

G25

M_B_DQ2 7

G26

M_B_DQ2 8

C26

M_B_DQ2 9

D26

M_B_DQ3 0

G23

M_B_DQ3 1

G24

M_B_DQ3 2

AA24

M_B_DQ3 3

AA23

M_B_DQ3 4

AD24

M_B_DQ3 5

AE24

M_B_DQ3 6

AA26

M_B_DQ3 7

AA25

M_B_DQ3 8

AD26

M_B_DQ3 9

AE25

M_B_DQ4 0

AC22

M_B_DQ4 1

AD22

M_B_DQ4 2

AE20

M_B_DQ4 3

AF20

M_B_DQ4 4

AF24

M_B_DQ4 5

AF23

M_B_DQ4 6

AC20

M_B_DQ4 7

AD20

M_B_DQ4 8

AD18

M_B_DQ4 9

AE18

M_B_DQ5 0

AC14

M_B_DQ5 1

AD14

M_B_DQ5 2

AF19

M_B_DQ5 3

AC18

M_B_DQ5 4

AF16

M_B_DQ5 5

AF15

M_B_DQ5 6

AF13

M_B_DQ5 7

AC12

M_B_DQ5 8

AB11

M_B_DQ5 9

Y11

M_B_DQ6 0

AE14

M_B_DQ6 1

AF14

M_B_DQ6 2

AF11

M_B_DQ6 3

AD11

M_B_DM0

A12

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

CPU_DDR_(2/4)

M_B_DM1

B16

M_B_DM2

A22

M_B_DM3

E25

M_B_DM4

AB26

M_B_DM5

AE22

M_B_DM6

AC16

M_B_DM7

AD12

C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

Berry AMD Discrete/UMA

1

M_B_DQ[6 3..0] (19)

M_B_DM[7 ..0] (19)

M_B_DQS 0 (19) M_B_DQS #0 (19) M_B_DQS 1 (19) M_B_DQS #1 (19) M_B_DQS 2 (19) M_B_DQS #2 (19) M_B_DQS 3 (19) M_B_DQS #3 (19) M_B_DQS 4 (19) M_B_DQS #4 (19) M_B_DQS 5 (19) M_B_DQS #5 (19) M_B_DQS 6 (19) M_B_DQS #6 (19) M_B_DQS 7 (19) M_B_DQS #7 (19)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

9 95Thursday, March 04 , 2010

1

A00

5

4

3

2

1

SSID = CPU

1119-1

L1001

1 2

SC180P50V2JN-1GP

PBY160808 T-330Y-N-GP

D D

+1.5V_RU N

10/5

4

RN1001

RN1001 SRN300J -3-GP

SRN300J -3-GP

1

2 3

CPU_LDT _RST#(20)

CPU_LDT _PWRGD(20,42)

CPU_LDT _STOP#(13 ,20)

C C

1 2

R1001 0R0402-P ADR1001 0R0402-P AD

1 2

R1002 0R0402-P ADR1002 0R0402-P AD

1 2

R1003 0R0402-P ADR1003 0R0402-P AD

CPU_CLK(200MHz)

For HDT DBG

1231-1

CPU_R_L DT_RST#

CPU_R_L DT_PWRGD

CPU_R_L DT_STOP#

11/6

CPU_R_L DT_RST#

HDT_RST _R#

C1008

SC10P50V2JN-4GP

C1008

SC10P50V2JN-4GP

12

9/11 S1g4 no support LDTREQ#

+1.5V_RU N

R1012 300R2J-4-GP

1 2

DY

R1013 300R2J-4-GP

1 2

DY

R1014 300R2J-4-GP

1 2

DY

R1016 300R2J-4-GP

1 2

DY

R1017 1KR2J-1-GPR1017 1KR2J-1-GP

1 2

R1025 1KR2J-1-GPR1025 1KR2J-1-GP

1 2

RN1002 SRN1KJ-7 -GPRN1 002 SRN1KJ-7 -GP

1 2 3

RN1004

1 2 3 4 5

SRN1KJ-8 -GP

B B

+1.5V_SU S

R1026

R1026 1KR2J-1-G P

1KR2J-1-G P

1 2

CPU_TES T27

R1029

R1029 300R2J-4 -GP

300R2J-4 -GP

DY

1 2

SRN1KJ-8 -GP

TP1001TP1001 TP1003TP1003 TP1004TP1004 TP1005TP1005 TP1006TP1006 TP1007TP1007 TP1008TP1008 TP1009TP1009 TP1010TP1010 TP1011TP1011

1229-1

A A

CPU_PRO CHOT#_EC(37)

5

CPU_LDT _REQ#

CPU_DBR DY TP_CPU_ TEST14 TP_CPU_ TEST15

CPU_TES T23

CPU_TES T12

4

8 7 6

1 1 1 1 1 1 1 1 1 1

+3.3V_RU N

CPU_TES T18 CPU_TES T19

CPU_TES T20 CPU_TES T21 CPU_TES T24 CPU_TES T22

TP_CPU_ VDDIO_SUS_FB_H TP_CPU_ VDDIO_SUS_FB_L TP_CPU_ TEST28_H TP_CPU_ TEST28_L TP_CPU_ TEST17 TP_CPU_ TEST16 TP_CPU_ TEST15 TP_CPU_ TEST14 TP_CPU_ TEST8 TP_CPU_ TEST7

8K2R2J-3-GP

12

R1040

+1.5V_RU N

2K2R2J-2-GP

12

1

2

Q1005

Q1005 PMBS390 4-1-GP

PMBS390 4-1-GP

R1039

3

1129-1

510R2F-L -GP

CPU_SIC(21)

CPU_SID(21)

TALERT#(21,39)

CPU_PRO CHOT#

CPU_CLK(7) CPU_CLK #(7)

R1009

1 2

DY

0R2J-2-GP

EC1001

12

DY

1231-2

+1.5V_SU S

12

R1018

DY

12

R1020

510R2F-L -GP

For old HDT tool (3.3V level)

9/22

RN1005

SRN1KJ-7 -GP

4

DY

+1.5V_SU S

PBY160808 T-330Y-N-GP

C1001

33R, 3A

12

11/6

Cloce To CPU

C1005 SC3900P 50V2KX-2GPC 1005 SC3900P50V2KX -2GP C1006 SC3900P 50V2KX-2GPC 1006 SC3900P50V2KX -2GP

R1008 1 69R2F-GPR1008 1 69R2F-GP

1 2 1 2

0108-5

Close CPU

SCD01U16V2KX-3GPDYEC1001

SCD01U16V2KX-3GP

R1019

R1019 510R2F-L -GP

510R2F-L -GP

R1022

R1022 510R2F-L -GP

510R2F-L -GP

4

1

2 3

10KR2J-3-GP

12

DY

+1.1V_RU N

R1010 44D2R2F -GPR1010 44D2R2F -GP R1011 44D2R2F -GPR1011 44D2R2F -GP

CPU_VDD 0_RUN_FB_H(47) CPU_VDD 0_RUN_FB_L(47)

CPU_VDD 1_RUN_FB_H(47) CPU_VDD 1_RUN_FB_L(47)

1231-1

312

PMBS390 4-1-GP

R1037

Q1004 PM BS3904-1-GP

LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

+2.5V_RU N_VDDA+2.5V_RU N

2.5V(250mA) for VDDA

SCD22U10V2KX-1GP

SC10U10V5ZY-1GP

C1002

2K2R2J-2-GP

Q1001

1 2

SCD1U10V2KX-5GP

1 2 1 2

1 2

12

R1032

+1.8V_RU N+3.3V_R UN

2K2R2J-2-GP

DY

312

DY

C1007

12

DY

R1023

0R0402-P AD

1231-11231-1

11/6

1KR2J-1-GP

12

R1036

C1002

12

CPU_R_L DT_PWRGD CPU_R_L DT_STOP# CPU_LDT _REQ#

CPU_SIC CPU_SID CPU_ALE RT#

CPU_DBR DY CPU_TMS CPU_TCK CPU_TRS T# CPU_TDI

CPU_TES T23

CPU_TES T18 CPU_TES T19

CPU_TES T25_H CPU_TES T25_L

CPU_TES T21 CPU_TES T20 CPU_TES T24 CPU_TES T22 CPU_TES T12 CPU_TES T27

CPU_TES T9

12

R1033

CPU_ALE RT#

HDT_RST _R#HDT_RST #

12

CPU_SIC

CPU_SID

SC3300P50V3KX-1GP

C1003

CPUCLK_ IN CPUCLK_ IN#

CPU_HTR EF0 CPU_HTR EF1

3

C1004

12

F10

AF4 AF5 AE6

AB6

G10 AA9 AC9 AD9 AF9

AD7

H10

AB8 AF7 AE7 AE8 AC8 AF8

AA6

F8 F9

A9 A8

B7 A7

C6

R6 P6

F6 E6

Y6

G9

E9 E8

C2

A3 A5 B3 B5 C1

CPU_PW RGD_SVID_REG(47)

CPU1D

VDDA VDDA

CLKIN_H CLKIN_L

RESET# PWROK LDTSTOP# LDTREQ#

SIC SID ALERT#

HT_REF0 HT_REF1

VDD0_FB_H VDD0_FB_L

VDD1_FB_H VDD1_FB_L

DBRDY TMS TCK TRST# TDI

TEST23

TEST18 TEST19

TEST25_H TEST25_L

TEST21 TEST20 TEST24 TEST22 TEST12 TEST27

TEST9 TEST6

RSVD#A3 RSVD#A5 RSVD#B3 RSVD#B5 RSVD#C1

H_THERM TRIP#(21,37,39,4 2,82)

DANUBE

THERMTRIP#

VDDIO_FB_H

VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

+KBC_PW R

10KR2J-3-GP

RSVD#W18

PROCHOT#

MEMHOT#

THERMDC THERMDA

TEST28_H

TEST28_L

TEST29_H

TEST29_L

RSVD#H18 RSVD#H19

RSVD#AA7

RSVD#D5 RSVD#C5

8K2R2J-3-GP

4 OF 6

M11

VSS

W18

A6

SVC

A4

SVD

AF6 AC7 AA8

W7 W8

W9 Y9

H6 G6

E10

DBREQ#

AE9

TDO

J7 H8

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

C3

TEST7

K8

TEST10

C4

TEST8

C9 C8

H18 H19 AA7 D5 C5

11/11

+1.5V_RU N

2K2R2J-2-GP

R1027

312

PMBS390 4-1-GP

+1.8V_RU N+3.3V_RU N

2K2R2J-2-GP

R1034

Q1003 PM BS3904-1-GPQ1003 PMBS390 4-1-GP

312

1 2

DY

2K2R2J-2-GP

Q1002

12

DY

12

R1041 0R2J-2-GP

1225-4

+1.5V_SU S

9/25

4

RN1006

RN1006 SRN1KJ-7 -GP

SRN1KJ-7 -GP

1

2 3

CPU_PRO CHOT# CPU_MEM HOT#

TP_CPU_ VDDIO_SUS_FB_H TP_CPU_ VDDIO_SUS_FB_L

R1015

CPU_DBR EQ#

CPU_TDO

TP_CPU_ TEST28_H TP_CPU_ TEST28_L

TP_CPU_ TEST17 TP_CPU_ TEST16 TP_CPU_ TEST15 TP_CPU_ TEST14

TP_CPU_ TEST7 CPU_TES T10

TP_CPU_ TEST8

CPU_TES T29H CPU_TES T29L

12

R1035

R1015

1 2

300R2J-4 -GP

1 2

R1021 300R3-GP

1 2

R1024 80D6R2F-L-GPR 1024 80D6R2F -L-GP

R1028

CPU_THE RMTRIP#

CPU_R_L DT_PWRGD

0112-2

2

+1.5V_SU S

9/14

300R2J-4-GP

1KR2J-1-GP

12

R1007

R1006

CPU_SVC (47) CPU_SVD (47)

CPU_THE RMTRIP#

1

TP1002TP1002

S1G4 not support MEMHOT

H_THERM DC (39) H_THERM DA (39)

CPU_VDD NB_RUN_FB_H (47) CPU_VDD NB_RUN_FB_L (47 )

+1.5V_SU S

+1.1V_RU N

DY

CPU_PRO CHOT# (20)

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

HDT Connectors

CPU_DBR EQ#

CPU_DBR DY

CPU_TCK CPU_TMS CPU_TDI

CPU_TRS T#

CPU_TDOC PU_TDO

CPU_R_L DT_RST#

1.5V

HDT_RST #

3.3V

Title

CPU_Control&Debug_(3/4)

Size Document N umber Rev

A3

Date: Sheet of

+1.5V_SU S

1 2

DY

R1038 0R2J-2-GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

1

HDT1

1

DY

3 5 7

9 11 13 15 17 19 21 23

SMC-CONN 26A-FP

10 95Thursday, March 04 , 2010

2

4 6 8 10 12 14 16 18 20 22 24 26

A00

5

4

3

2

1

SSID = CPU

D D

6 OF 6

CPU1F

AA4

VSS

AA11

VSS

AA13

VSS

AA15

VSS

AA17

VSS

AA19

VSS

AB2

VSS

AB7

VSS

AB9

VSS

AB23

VSS

AB25

VSS

AC11

VSS

AC13

VSS

AC15

VSS

AC17

VSS

AC19

VSS

AC21

VSS

AD6

C C

B B

AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

B11

B13

B15

B17

B19

B21

B23

B25

D11

D13

D15

D17

D19

D21

D23

D25

H21

H23

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B4

VSS

B6

VSS

B8

VSS

B9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D6

VSS

D8

VSS

D9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

E4

VSS

F2

VSS

F11

VSS

F13

VSS

F15

VSS

F17

VSS

F19

VSS

F21

VSS

F23

VSS

F25

VSS

H7

VSS

H9

VSS VSS VSS

J4

VSS

J6

VSS

J8

VSS

J10

VSS

J12

DANUBE

VSS

J14

VSS

J16

VSS

J18

VSS

K2

VSS

K7

VSS

K9

VSS

K11

VSS

K13

VSS

K15

VSS

K17

VSS

L6

VSS

L8

VSS

L10

VSS

L12

VSS

L14

VSS

L16

VSS

L18

VSS

M7

VSS

M9

VSS

AC6

VSS

M17

VSS

N4

VSS

N8

VSS

N10

VSS

N16

VSS

N18

VSS

P2

VSS

P7

VSS

P9

VSS

P11

VSS

P17

VSS

R8

VSS

R10

VSS

R16

VSS

R18

VSS

T7

VSS

T9

VSS

T11

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

+1.5V_SU S

1231-2

(36A) for 35W S1G4 VDD

+VCC_CO RE +VCC_CO RE

+VDDNB

Bottom Side Decoupling Bottom Side Decoupling

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SCD22U10V2KX-1GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

C1103

C1101

DY

C1101

12

1231-2 1231-2

22uF *2 10uF *2

0.22uF *1

0.01uF *1 180pF *1

0.9V(4A) for VDDNB

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

DY

12

SC10U6D3V5KX-1GP

C1115

C1116

12

SCD22U10V2KX-1GP

C1104

C1105

12

SC180P50V2JN-1GP

SCD01U16V2KX-3GP

C1102

C1107

C1106

12

1119-3

C1117

22UF *3

1231-2

1.5V(3A) for VDDIO

Bottom Side Decoupling

SC10U6D3V5KX-1GP

12

SCD22U10V2KX-1GP

C1131

C1130

12

DY

SCD22U10V2KX-1GP

C1132

12

SCD1U10V2KX-5GP

C1134

SCD1U10V2KX-5GP

1119-1

C1120

12

SCD01U16V2KX-3GP

C1135

12

SC180P50V2JN-1GP

C1133

12

CPU1E

G4

VDD

H2

VDD

J9

VDD

J11

VDD

J13

VDD

J15

VDD

K6

VDD

K10

VDD

K12

VDD

K14

VDD

L4

VDD

L7

VDD

L9

VDD

L11

VDD

L13

VDD

L15

VDD

M2

VDD

M6

VDD

M8

VDD

M10

VDD

N7

VDD

N9

VDD

N11

VDD

K16

VDDNB

M16

VDDNB

P16

VDDNB

T16

VDDNB

V16

VDDNB

H25

VDDIO

J17

VDDIO

K18

VDDIO

K21

VDDIO

K23

VDDIO

K25

VDDIO

L17

VDDIO

M18

VDDIO

M21

VDDIO

M23

VDDIO

M25

VDDIO

N17

VDDIO

C1121

12

DANUBE

5 OF 6

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

SCD01U16V2KX-3GP

DY

12

SCD22U10V2KX-1GP

SCD01U16V2KX-3GP

C1108

12

SC22U6D3V5MX-2GP

C1110

C1109

12

DY

1119-3

22uF *2 10uF *2

0.22uF *1

0.01uF *1 180pF *1

Place near to CPU

SC180P50V2JN-1GP

DY

SC180P50V2JN-1GP

C1118

12

DY

SCD22U10V2KX-1GP

C1119

C1122

12

DY

1119-3

SC22U6D3V5MX-2GP

C1111

12

SCD22U10V2KX-1GP

C1123

12

0.01UF *1

0.1UF *2

0.22UF *4

4.7UF *4 180PF *2

SC10U6D3V5KX-1GP

C1112

C1141

12

SC4D7U6D3V3KX-GP

SCD22U10V2KX-1GP

C1125

C1124

12

DY

1231-2 1231-2

1119-3

10UF *2

0.22UF *2 180PF *1

C1114

+1.5V_SU S

SC4D7U6D3V3KX-GP

C1129

C1126

C1127

12

DY

C1129

C1128

12

9/14

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_Power_(4/4)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

11 95Thursday, March 04 , 2010

1

A00

5

HT_CPU_ NB_CAD_H0(8)

SSID = N.B

RS880M : 71.RS880.M05

D D

C C

Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24

B B

9/11

WLAN LAN WWAN

A A

A-LINK

5

ALINK_NBR X_SBTX_P0(20) ALINK_NBR X_SBTX_N0(20) ALINK_NBR X_SBTX_P1(20) ALINK_NBR X_SBTX_N1(20) ALINK_NBR X_SBTX_P2(20) ALINK_NBR X_SBTX_N2(20) ALINK_NBR X_SBTX_P3(20) ALINK_NBR X_SBTX_N3(20)

HT_CPU_ NB_CAD_L0(8) HT_CPU_ NB_CAD_H1(8 ) HT_CPU_ NB_CAD_L1(8) HT_CPU_ NB_CAD_H2(8 ) HT_CPU_ NB_CAD_L2(8) HT_CPU_ NB_CAD_H3(8 ) HT_CPU_ NB_CAD_L3(8) HT_CPU_ NB_CAD_H4(8 ) HT_CPU_ NB_CAD_L4(8) HT_CPU_ NB_CAD_H5(8 ) HT_CPU_ NB_CAD_L5(8) HT_CPU_ NB_CAD_H6(8 ) HT_CPU_ NB_CAD_L6(8) HT_CPU_ NB_CAD_H7(8 ) HT_CPU_ NB_CAD_L7(8)

HT_CPU_ NB_CAD_H8(8 ) HT_CPU_ NB_CAD_L8(8) HT_CPU_ NB_CAD_H9(8 ) HT_CPU_ NB_CAD_L9(8) HT_CPU_ NB_CAD_H10(8) HT_CPU_ NB_CAD_L10(8) HT_CPU_ NB_CAD_H11(8) HT_CPU_ NB_CAD_L11(8) HT_CPU_ NB_CAD_H12(8) HT_CPU_ NB_CAD_L12(8) HT_CPU_ NB_CAD_H13(8) HT_CPU_ NB_CAD_L13(8) HT_CPU_ NB_CAD_H14(8) HT_CPU_ NB_CAD_L14(8) HT_CPU_ NB_CAD_H15(8) HT_CPU_ NB_CAD_L15(8)

HT_CPU_ NB_CLK_H0(8) HT_CPU_ NB_CLK_L0(8) HT_CPU_ NB_CLK_H1(8) HT_CPU_ NB_CLK_L1(8)

HT_CPU_ NB_CTL_H0(8) HT_CPU_ NB_CTL_L0(8) HT_CPU_ NB_CTL_H1(8) HT_CPU_ NB_CTL_L1(8)

R1201 301R2F-GPR 1201 301 R2F-GP

1 2

9/15

PCIE_NRX_ GTX_P15 PCIE_NRX_ GTX_N15 PCIE_NRX_ GTX_P14 PCIE_NRX_ GTX_N14 PCIE_NRX_ GTX_P13 PCIE_NRX_ GTX_N13 PCIE_NRX_ GTX_P12 PCIE_NRX_ GTX_N12 PCIE_NRX_ GTX_P11 PCIE_NRX_ GTX_N11 PCIE_NRX_ GTX_P10 PCIE_NRX_ GTX_N10 PCIE_NRX_ GTX_P9 PCIE_NRX_ GTX_N9 PCIE_NRX_ GTX_P8 PCIE_NRX_ GTX_N8 PCIE_NRX_ GTX_P7 PCIE_NRX_ GTX_N7 PCIE_NRX_ GTX_P6 PCIE_NRX_ GTX_N6 PCIE_NRX_ GTX_P5 PCIE_NRX_ GTX_N5

LANE REVERSAL

PCIE_NRX_ GTX_P4 PCIE_NRX_ GTX_N4 PCIE_NRX_ GTX_P3 PCIE_NRX_ GTX_N3 PCIE_NRX_ GTX_P2 PCIE_NRX_ GTX_N2 PCIE_NRX_ GTX_P1 PCIE_NRX_ GTX_N1 PCIE_NRX_ GTX_P0 PCIE_NRX_ GTX_N0

PCIE_RXP0(7 6) PCIE_RXN0(76) PCIE_RXP1(7 6) PCIE_RXN1(76) PCIE_RXP2(7 6) PCIE_RXN2(76)

4

U1A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCA LP HT_TXCA LP HT_RXCA LN

C23 A24

RS880M-1 -GP

U1B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS880M-1-GP

4

HT_RXCTL1N

HT_RXCALP HT_RXCALN

PART 1 OF 6

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N

HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP HT_TXCALN

A5

GFX_TX0P

B5

GFX_TX0N

A4

GFX_TX1P

B4

GFX_TX1N

C3

GFX_TX2P

B2

GFX_TX2N

D1

GFX_TX3P

D2

GFX_TX3N

E2

GFX_TX4P

E1

GFX_TX4N

F4

GFX_TX5P

F3

GFX_TX5N

F1

GFX_TX6P

F2

GFX_TX6N

H4

GFX_TX7P

H3

GFX_TX7N

H1

GFX_TX8P

H2

GFX_TX8N

J2

GFX_TX9P

J1

GFX_TX9N

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

AC8 AB8

GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

PCIE I/F GFX

PCE_CALRP

PCE_CALRN

3

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24

HT_TXCA LN

B25

PCIE_NTX_ GRX_C_P15 PCIE_NTX_ GRX_C_N15 PCIE_NTX_ GRX_C_P14 PCIE_NTX_ GRX_C_N14 PCIE_NTX_ GRX_C_P13 PCIE_NTX_ GRX_C_N13 PCIE_NTX_ GRX_C_P12 PCIE_NTX_ GRX_C_N12 PCIE_NTX_ GRX_C_P11 PCIE_NTX_ GRX_C_N11 PCIE_NTX_ GRX_C_P10 PCIE_NTX_ GRX_C_N10 PCIE_NTX_ GRX_C_P9 PCIE_NTX_ GRX_C_N9 PCIE_NTX_ GRX_C_P8 PCIE_NTX_ GRX_C_N8 PCIE_NTX_ GRX_C_P7 PCIE_NTX_ GRX_C_N7 PCIE_NTX_ GRX_C_P6 PCIE_NTX_ GRX_C_N6 PCIE_NTX_ GRX_C_P5 PCIE_NTX_ GRX_C_N5 PCIE_NTX_ GRX_C_P4 PCIE_NTX_ GRX_C_N4 PCIE_NTX_ GRX_C_P3 PCIE_NTX_ GRX_C_N3 PCIE_NTX_ GRX_C_P2 PCIE_NTX_ GRX_C_N2 PCIE_NTX_ GRX_C_P1 PCIE_NTX_ GRX_C_N1 PCIE_NTX_ GRX_C_P0 PCIE_NTX_ GRX_C_N0

PCIE_C_TX P0 PCIE_C_TX N0 PCIE_C_TX P1 PCIE_C_TX N1 PCIE_C_TX P2 PCIE_C_TX N2

ALINK_NBT X_SBRX_C_P0 ALINK_NBT X_SBRX_C_N0 ALINK_NBT X_SBRX_C_P1 ALINK_NBT X_SBRX_C_N1 ALINK_NBT X_SBRX_C_P2 ALINK_NBT X_SBRX_C_N2 ALINK_NBT X_SBRX_C_P3 ALINK_NBT X_SBRX_C_N3

PCE_PCA L PCE_NCA L

Place < 100mils from pin AC8 and AB8

3

HT_NB_C PU_CAD_H0 (8) HT_NB_C PU_CAD_L0 (8) HT_NB_C PU_CAD_H1 (8) HT_NB_C PU_CAD_L1 (8) HT_NB_C PU_CAD_H2 (8) HT_NB_C PU_CAD_L2 (8) HT_NB_C PU_CAD_H3 (8) HT_NB_C PU_CAD_L3 (8) HT_NB_C PU_CAD_H4 (8) HT_NB_C PU_CAD_L4 (8) HT_NB_C PU_CAD_H5 (8) HT_NB_C PU_CAD_L5 (8) HT_NB_C PU_CAD_H6 (8) HT_NB_C PU_CAD_L6 (8) HT_NB_C PU_CAD_H7 (8) HT_NB_C PU_CAD_L7 (8)

HT_NB_C PU_CAD_H8 (8) HT_NB_C PU_CAD_L8 (8) HT_NB_C PU_CAD_H9 (8) HT_NB_C PU_CAD_L9 (8) HT_NB_C PU_CAD_H10 (8) HT_NB_C PU_CAD_L10 (8) HT_NB_C PU_CAD_H11 (8) HT_NB_C PU_CAD_L11 (8) HT_NB_C PU_CAD_H12 (8) HT_NB_C PU_CAD_L12 (8) HT_NB_C PU_CAD_H13 (8) HT_NB_C PU_CAD_L13 (8) HT_NB_C PU_CAD_H14 (8) HT_NB_C PU_CAD_L14 (8) HT_NB_C PU_CAD_H15 (8) HT_NB_C PU_CAD_L15 (8)

HT_NB_C PU_CLK_H0 (8) HT_NB_C PU_CLK_L0 (8) HT_NB_C PU_CLK_H1 (8) HT_NB_C PU_CLK_L1 (8)

HT_NB_C PU_CTL_H0 (8) HT_NB_C PU_CTL_L0 (8) HT_NB_C PU_CTL_H1 (8) HT_NB_C PU_CTL_L1 (8)

R1202 301R2F-GPR 1202 301 R2F-GP

1 2

1119-3

C1231 SCD1U10 V2KX-5GPC 1231 SCD1U 10V2KX-5GP

1 2

C1232 SCD1U10 V2KX-5GPC 1232 SCD1U 10V2KX-5GP

1 2

C1229 SCD1U10 V2KX-5GPC 1229 SCD1U 10V2KX-5GP

1 2

C1230 SCD1U10 V2KX-5GPC 1230 SCD1U 10V2KX-5GP

1 2

C1227 SCD1U10 V2KX-5GPC 1227 SCD1U 10V2KX-5GP

1 2

C1228 SCD1U10 V2KX-5GPC 1228 SCD1U 10V2KX-5GP

1 2

C1225 SCD1U10 V2KX-5GPC 1225 SCD1U 10V2KX-5GP

1 2

C1226 SCD1U10 V2KX-5GPC 1226 SCD1U 10V2KX-5GP

1 2

C1223 SCD1U10 V2KX-5GP

1 2

C1224 SCD1U10 V2KX-5GP

1 2

C1221 SCD1U10 V2KX-5GP

1 2

C1222 SCD1U10 V2KX-5GP

1 2

C1219 SCD1U10 V2KX-5GP

1 2

C1220 SCD1U10 V2KX-5GP

1 2

C1217 SCD1U10 V2KX-5GP

1 2

C1218 SCD1U10 V2KX-5GP

1 2

C1215 SCD1U10 V2KX-5GP

1 2

C1216 SCD1U10 V2KX-5GP

1 2

C1213 SCD1U10 V2KX-5GP

1 2

C1214 SCD1U10 V2KX-5GP

1 2

C1211 SCD1U10 V2KX-5GP

1 2

C1212 SCD1U10 V2KX-5GP

1 2

C1209 SCD1U10 V2KX-5GP

1 2

C1210 SCD1U10 V2KX-5GP

1 2

C1207 SCD1U10 V2KX-5GP

1 2

C1208 SCD1U10 V2KX-5GP

1 2

C1205 SCD1U10 V2KX-5GP

1 2

C1206 SCD1U10 V2KX-5GP

1 2

C1203 SCD1U10 V2KX-5GP

1 2

C1204 SCD1U10 V2KX-5GP

1 2

C1201 SCD1U10 V2KX-5GP

1 2

C1202 SCD1U10 V2KX-5GP

1 2

C1264 SCD1U10 V2KX-5GPC 1264 SCD1U 10V2KX-5GP

1 2

C1261 SCD1U10 V2KX-5GPC 1261 SCD1U 10V2KX-5GP

1 2

C1266 SCD1U10 V2KX-5GPC 1266 SCD1U 10V2KX-5GP

1 2

C1262 SCD1U10 V2KX-5GPC 1262 SCD1U 10V2KX-5GP

1 2

C1265 SCD1U10 V2KX-5GPC 1265 SCD1U 10V2KX-5GP

1 2

C1263 SCD1U10 V2KX-5GPC 1263 SCD1U 10V2KX-5GP

1 2

9/11

C1237 SCD1U10 V2KX-5GPC 1237 SCD1U 10V2KX-5GP

1 2

C1238 SCD1U10 V2KX-5GPC 1238 SCD1U 10V2KX-5GP

1 2

C1239 SCD1U10 V2KX-5GPC 1239 SCD1U 10V2KX-5GP

1 2

C1240 SCD1U10 V2KX-5GPC 1240 SCD1U 10V2KX-5GP

1 2

C1241 SCD1U10 V2KX-5GPC 1241 SCD1U 10V2KX-5GP

1 2

C1242 SCD1U10 V2KX-5GPC 1242 SCD1U 10V2KX-5GP

1 2

C1243 SCD1U10 V2KX-5GPC 1243 SCD1U 10V2KX-5GP

1 2

C1244 SCD1U10 V2KX-5GPC 1244 SCD1U 10V2KX-5GP

R1203 1K27R2F-L-GPR1203 1K27R2F-L-GP

1 2

R1204 2KR2F-3-GPR1204 2 KR2F-3-GP

1 2

DIS

DIS DIS

DIS

PCIE_NTX_ GRX_P[12..15]

PCIE_NTX_ GRX_N[12..15]

PCIE_NTX_ GRX_P[0..11]

PCIE_NTX_ GRX_N[0..11]

PCIE_NRX_ GTX_P[0..15]

PCIE_NRX_ GTX_N[0..15]

PCIE_NTX_ GRX_P15 PCIE_NTX_ GRX_N15 PCIE_NTX_ GRX_P14 PCIE_NTX_ GRX_N14 PCIE_NTX_ GRX_P13 PCIE_NTX_ GRX_N13 PCIE_NTX_ GRX_P12 PCIE_NTX_ GRX_N12 PCIE_NTX_ GRX_P11 PCIE_NTX_ GRX_N11 PCIE_NTX_ GRX_P10 PCIE_NTX_ GRX_N10 PCIE_NTX_ GRX_P9 PCIE_NTX_ GRX_N9 PCIE_NTX_ GRX_P8 PCIE_NTX_ GRX_N8 PCIE_NTX_ GRX_P7 PCIE_NTX_ GRX_N7 PCIE_NTX_ GRX_P6 PCIE_NTX_ GRX_N6 PCIE_NTX_ GRX_P5 PCIE_NTX_ GRX_N5 PCIE_NTX_ GRX_P4 PCIE_NTX_ GRX_N4 PCIE_NTX_ GRX_P3 PCIE_NTX_ GRX_N3 PCIE_NTX_ GRX_P2 PCIE_NTX_ GRX_N2 PCIE_NTX_ GRX_P1 PCIE_NTX_ GRX_N1 PCIE_NTX_ GRX_P0 PCIE_NTX_ GRX_N0

PCIE_TXP0 (76) PCIE_TXN0 (76) PCIE_TXP1 (76) PCIE_TXN1 (76) PCIE_TXP2 (76) PCIE_TXN2 (76)

ALINK_NBT X_SBRX_P0 (20) ALINK_NBT X_SBRX_N0 (20 ) ALINK_NBT X_SBRX_P1 (20) ALINK_NBT X_SBRX_N1 (20 ) ALINK_NBT X_SBRX_P2 (20) ALINK_NBT X_SBRX_N2 (20 ) ALINK_NBT X_SBRX_P3 (20) ALINK_NBT X_SBRX_N3 (20 )

+1.1V_RU N_VDDPCIE

2

A-LINK

2

PCIE_NTX_ GRX_P[12..15] (5 7)

PCIE_NTX_ GRX_N[12..15] (57)

PCIE_NTX_ GRX_P[0..11] (80 )

PCIE_NTX_ GRX_N[0..11] (80)

PCIE_NRX_ GTX_P[0..15] (80 )

PCIE_NRX_ GTX_N[0..15] (80)

9/15

LANE REVERSAL

WLAN LAN WWAN

1

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AMD-RS880M_HT LINK&PCIe(1/4)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

12 95Thursday, March 04 , 2010

1

A00

5

UMA DAC Signal:

SSID = N.B

RS880M : 71.RS880.M05

+1.1V_RU N

D D

C C

1 2

UMA

BLM15AG 221SS1D-GP

+1.8V_RU N

1 2

UMA

BLM15AG 221SS1D-GP

+1.8V_RU N

1 2

BLM15AG 221SS1D-GP

220R, 0.3A

1.1V, 65mA

L1308

L1307

L1301

SC1U6D3V2KX-GP

12

UMA/DIS

1.8V, 20mA

SC2D2U6D3V3KX-GP

12

UMA/DIS

Layout Note Trace at least 15 mil

1.8V, 20mA

+1.8V_VD DA18HTPLL

SC1U6D3V2KX-GP

12

PLLVDD

C1312

10/8

PLLVDD1 8

C1311

C1302

SCD1U10V2KX-5GP

1119-3

12

C1303

GREEN/BLUE: Connected to GND through two separate 150-



1% resistors.

RED: Connected to GND through two separate 133resistors.(For match resistor on CRT/B 150- 1%)

+3.3V_RU N +3.3V_RU N_AVDD

R1342

1 2

0R3J-0-U-G P

0106-2

+1.8V_RU N

R1333

1 2

0R3J-0-U-G P

+1.8V_RU N

1119-1

R1344

UMA

0R3J-0-U-G P

UMA: DAC_CLK and DATA with 5V-tolerant. not need level shift

10/8

9/22

R1343

1 2

0R0603-P AD

SC22U6D3V5MX-2GP

C1301

12

B B

CPU_LDT _STOP#(10 ,20)

A A

ALLOW _LDTSTOP(20)

1.8V, 120mA

+1.8V_VD DA18PCIEPLL

SC2D2U6D3V3KX-GP

R1309

300R2J-4 -GP

5

SCD1U10V2KX-5GP

C1305

C1304

12

C1305

12

1119-3

9/25

12

R1322 0R2J-2-GP

1 2

U1301

1

A1

2

GND A23Y2

1 2

R1316

R1316 0R0402-P AD

0R0402-P AD

ALLOW_LDTSTOP: 1 = LDTSTOP# can be asserted 0 = LDTSTOP# has to be de-asserted

DY

6

Y1

5

VCC

4

NC7W Z07P6X-1GP

+1.8V_RU N

12

R1315

R1315 1KR2J-1-G P

1KR2J-1-G P

NB_ALLO W_LDTSTOP

SCD1U10V2KX-5GP

+1.8V_RU N+1.5V_RU N

12

4K7R2F-G P

12

C1314

+1.1V_RU N

R1312

R1313

R1311

2K2R2J-2 -GP

NB_LDT_ STOP#

4

UMA

+1.8V_RU N_AVDDDI

UMA

+1.8V_RU N_AVDDDQ

12

M_RED(77)

M_GREEN(77)

M_BLUE(77)

Trace at least 10 mil

PLTRST# _NB_GPU(20,37,80 )

NB_PW RGD_IN(41)

SC180P5 0V2JN-1GP

NB_14M_ CLK(7)

1231-2

LDDC_CL K(55 )

LDDC_DA TA(55) NB_DDC_ DATA0(57) NB_DDC_ CLK0(57)

1 2

9/15

4

SC1U6D3V2KX-GP

3.3V, 110mA

C1307

12

UMA/DIS

10/8

SCD1U10V2KX-5GP

1.8V, 20mA

C1306

12

UMA/DIS

1.8V, 4mA

12

C1308

SC2D2U6 D3V3KX-GP

UMA/DIS

VGA_HSYNC(77)

VGA_VSYNC(77) DDC_CLK _CON(77 ) DDC_DAT A_CON(77 )

12

EC1301

1 2

R1341 0R0402-P ADR1341 0R 0402-PAD

SCD1U10V2KX-5GP

10/7

12

R1318

R1318 2KR2J-1-G P

2KR2J-1-G P



1%

9/22

UMA

R1326 1 50R2F-1-GP

1 2

UMA

1 2

R1327 1 50R2F-1-GP

UMA

1 2

R1328 1 50R2F-1-GP

12

SC180P5 0V2JN-1GP

C1315

12

DY

VGA_HSYNC VGA_VSYNC DDC_CLK _CON DDC_DAT A_CON

1 2

R1306 7 15R2F-GPR1306 7 15R2F-GP

+1.8V_VD DA18HTPLL

+1.8V_VD DA18PCIEPLL

9/16

EC1302

10/2

NB_LDT_ STOP# NB_ALLO W_LDTSTOP

CLK_NBH T_CLK(7) CLK_NBH T_CLK#(7)

NB_GFX_ CLK(7) NB_GFX_ CLK#(7)

TP1306TP1306 TP1307TP1307

NB_GPPS B_CLK(7) NB_GPPS B_CLK#(7)

TP1305TP1305

1 2

R1319 150R2F-1 -GPR 1319 150R2 F-1-GP

3

DAC_RSE T

PLLVDD PLLVDD1 8

NB_REFC LK_P

NB_REFC LK_N

NB_GFX_ CLK NB_GFX_ CLK#

NB_GPP_ CLK

1

NB_GPP_ CLK#

1

1120-6

STRP_DA TA

TP_NB_R ESERVED

1

RS780_A UX_CAL

3

SPM_Disable

SPM_Enable

U1C

F12

AVDD1

E12

AVDD2

F14

AVDDDI

G15

AVSSDI

H15

AVDDQ

H14

AVSSQ

E17

C_Pr

F17

Y

F15

COMP_Pb

G18

RED

G17

REDb

E18

GREEN

F18

GREENb

E19

BLUE

F19

BLUEb

A11

DAC_HSYNC

B11

DAC_VSYNC

F8

DAC_SCL

E8

DAC_SDA

G14

DAC_RSET

A12

PLLVDD

D14

PLLVDD18

B12

PLLVSS

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESET#

A10

POWERGOOD

C10

LDTSTOP#

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN

F11

REFCLK_N

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP

V3

GPPSB_REFCLKN

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N

A8

DDC_CLK0/AUX0P

B7

DDC_CLK1/AUX1P

A7

DDC_DATA1/AUX1N

B10

STRP_DATA

G11

RESERVED

C8

AUX_CAL

RS880M-1-GP

+3.3V_RU N

3KR2J-2-GP

12

3KR2J-2-GP

12

R1302

R1304

3KR2J-2-GP

DY

12

R1303

VGA_VSYNC VGA_HSYNC

R1305

PART 3 OF 6

CRT/TVOUT

PM

CLOCKs PLL PWR

MIS.

*DEFAULT

LVTM

11/6

R1314

4K7R2J-2 -GP

NB_SUS_ STAT#

R1321

3KR2J-2-G P

2

1

STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)

Enables debug bus access through memory I/O pads and GPIOs. 1 : Disable

*

0 : Enable

SIDE_PORT_EN# ( RS880M use DAC_HSYNC)

1 = Memory Side port Not available 0 = Memory Side port available

DIS

UMA_SPM

LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)

Selects Loading of STRAPS From EEPROM 1 : use Default Values

*

0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected

TXOUT_L0P

TXOUT_L0N

TXOUT_L1P

TXOUT_L1N

TXOUT_L2P

TXOUT_L2N

TXOUT_L3P

TXOUT_L3N

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXCLK_LP

TXCLK_LN TXCLK_UP TXCLK_UN

VDDLTP18

VSSLTP18

VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2

VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

VDDLTP1 8_R

VDDLT18 _R

VGA_TXA OUT0+ (55) VGA_TXA OUT0- (55) VGA_TXA OUT1+ (55) VGA_TXA OUT1- (55) VGA_TXA OUT2+ (55) VGA_TXA OUT2- (55)

VGA_TXB OUT0+ (55) VGA_TXB OUT0- (55) VGA_TXB OUT1+ (55) VGA_TXB OUT1- (55) VGA_TXB OUT2+ (55) VGA_TXB OUT2- (55)

VGA_TXA CLK+ (55) VGA_TXA CLK- (55) VGA_TXB CLK+ (55) VGA_TXB CLK- (55)

1.8V, 15mA

1.8V, 300mA

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

C1310

12

UMA/DIS

UMA

1119-1

220R, 0.3A

L1305

1 2

BLM15AG 221SS1D-GP

L1306

1 2

PBY160808 T-221Y-N-GP

C1313

12

PBY160808 T-221Y-N-GP

12

220R, 2A

C1309

SC2D2U6 D3V3KX-GP

UMA/DIS

11/12-4

LVDS_DIGON

LVDS_BLON

LVDS_ENA_BL

TMDS_HPD

HPD

SUS_STAT#

THERMALDIODE_P THERMALDIODE_N

TESTMODE

+3.3V_RU N

1 2

12

DY

2

E9 F7 G12

RN1301

1 2 3

UMA

SRN10KJ -5-GP

TP_TMDS _HPD

D9

HDMI_HPD_ DET

D10

NB_SUS_ STAT#

D12

AE8 AD8

TESTMOD E_NB

D13

Title

Size Document N umber Rev

A3

Date: Sheet of

SRN10KJ -5-GP

TP1308TP1308

1

R1317

1 2

0R2J-2-GP

1K8R2F-GP

12

R1320

AMD-RS880M_LVDS&CRT_(2/4)

NB_LCDP WR_EN (55) NB_BL_P WM (55 ) NB_BL_E N (55)

9/22

4

0225-1

UMA

Berry AMD Discrete/UMA

HDMI_HPD_ DET (57,82)

SUS_STA T# (21)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

13 95Thursday, March 04 , 2010

1

+1.8V_RU N

UMA

A00

5

SSID = N.B

4

3

2

1

MEM_VDD Q

U1401

D D

SPM_VRE F1 SPM_VRE F2

R1408 2 43R2F-2-GP

1 2

UMA_SPM

C C

B B

SPM_ZQ

SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_CLK P SPM_CLK N

SPM_CKE

SPM_DM1 SPM_DM0

SPM_W E# SPM_CAS # SPM_RAS #

U1401

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

K4W 1G1646E-HC12-GP

UMA_SPM_Samsung

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

SPM_DQ2

E3

SPM_DQ1

F7

SPM_DQ5

F2

SPM_DQ3

F8

SPM_DQ7

H3

SPM_DQ0

H8

SPM_DQ4

G2

SPM_DQ6

H7

SPM_DQ1 3

D7

SPM_DQ8

C3

SPM_DQ1 0

C8

SPM_DQ1 2

C2

SPM_DQ1 5

A7

SPM_DQ1 1

A2

SPM_DQ1 4

B8

SPM_DQ9

A3

SPM_DQS 1P

C7

SPM_DQS 1N

B7

SPM_DQS 0P

F3

SPM_DQS 0N

G3

SPM_ODT

K1

SPM_CS#

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

MEM_VDD Q

12

R1411

R1411 10KR2J-3 -GP

10KR2J-3 -GP

UMA_SPM

SCD1U10V2KX-5GP

C1415

12

DY

10/7

SP_DDR3 _RST# (21)

9/15

MEM_VDD Q

SPM_CLK P SPM_CLK N

UMA_SPM

R1409 40D2R2F -GP

1 2

R1410 40D2R2F -GP

1 2

UMA_SPM

R1401 100R2F-L 1-GP-U

1 2

DY

SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_RAS # SPM_CAS # SPM_W E# SPM_CS# SPM_CKE SPM_ODT

MEM_COM PP MEM_COM PN

U1D

AB12

MEM_A0

AE16

MEM_A1

V11

MEM_A2

AE15

MEM_A3

AA12

MEM_A4

AB16

MEM_A5

AB14

MEM_A6

AD14

MEM_A7

AD13

MEM_A8

AD15

MEM_A9

AC16

MEM_A10

AE13

MEM_A11

AC14

MEM_A12

Y14

MEM_A13

AD16

MEM_BA0

AE17

MEM_BA1

AD17

MEM_BA2

W12

MEM_RAS#

Y12

MEM_CAS#

AD18

MEM_WE#

AB13

MEM_CS#

AB18

MEM_CKE

V14

MEM_ODT

V15

MEM_CKP

W14

MEM_CKN

AE12

MEM_COMPP

AD12

MEM_COMPN

RS880M-1 -GP

1.8V(0.015A) for IOPLLVDD18

1.1V(0.026A) for IOPLLVDD

PAR 4 OF 6

IOPLLVDD1 8

IOPLLVDD

MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC

MEM_DQ2/DVO_DE

MEM_DQ3/DVO_D0

MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3

MEM_DQ9/DVO_D5 MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7

MEM_DQ13/DVO_D9

MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11

MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN

MEM_DM1/DVO_D8

SBD_MEM/DVO_I/F

SC2D2U6D3V3KX-GP

C1401

12

UMA_SPM

SC2D2U6D3V3KX-GP

C1402

12

UMA_SPM

MEM_DQ12

MEM_DQS1P MEM_DQS1N

IOPLLVDD18

MEM_VREF

L1401

1 2

0R0402-P AD

L1402

1 2

0R0402-P AD

MEM_DQ4

MEM_DM0

IOPLLVDD

IOPLLVSS

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23

AE18

+1.8V_RU N

1231-1

+1.1V_RU N

1231-1

SPM_DQ0 SPM_DQ1 SPM_DQ2 SPM_DQ3 SPM_DQ4 SPM_DQ5 SPM_DQ6 SPM_DQ7 SPM_DQ8 SPM_DQ9 SPM_DQ1 0 SPM_DQ1 1 SPM_DQ1 2 SPM_DQ1 3 SPM_DQ1 4 SPM_DQ1 5

SPM_DQS 0P SPM_DQS 0N SPM_DQS 1P SPM_DQS 1N

SPM_DM0 SPM_DM1

IOPLLVDD1 8

IOPLLVDD

SPM_VRE F0

MEM_VDD Q

1KR3F-GP

12

R1402

UMA_SPM

SPM_VRE F0

UMA_SPM

1KR3F-GP

12

R1405

UMA_SPM

UMA_SPM/DIS_NOSPM

A A

C1404

12

UMA_SPM

C1403

12

5

SCD1U10V2KX-5GP

SPM_VRE F1

MEM_VDD Q

R1403

UMA_SPM

R1406

UMA_SPM

1KR3F-GP

12

1KR3F-GP

12

SCD1U10V2KX-5GP

C1406

12

UMA_SPM

SCD1U10V2KX-5GP

C1405

12

UMA_SPM

MEM_VDD Q

SCD1U10V2KX-5GP

1KR3F-GP

12

R1404

UMA_SPM

SPM_VRE F2

UMA_SPM

4

1KR3F-GP

12

R1407

SCD1U10V2KX-5GP

C1408

12

UMA_SPM

SCD1U10V2KX-5GP

C1407

12

UMA_SPM

1.5V(0.35A) for IOPLLVDD

SCD1U10V2KX-5GP

C1413

SCD1U10V2KX-5GP

C1410

C1409

12

UMA_SPM

SC1U6D3V2KX-GP

C1414

12

UMA_SPM

3

SC1U6D3V2KX-GP

12

UMA_SPM

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

12

UMA_SPM

MEM_VDD Q

SC10U6D3V5KX-1GP

C1411

12

UMA_SPM

C1412

R1412

1 2

UMA_SPM

0R3J-0-U-G P

+1.5V_RU N

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AMD-RS880M_SidePort_(3/4)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

14 95Thursday, March 04 , 2010

1

A00

5

4

3

2

1

SSID = N.B

D D

+1.1V_RU N

C C

+1.1V_RU N

B B

A A

1231-1

R1501

1 2

0R0603-P AD

R1505

1 2

0R0603-P AD

R1503

1 2

0R0603-P AD

+1.8V_RU N

L1505

1 2

PBY160808 T-221Y-N-GP

220R, 2A

1119-1

+1.8V_RU N

UMA

R1502

1 2

0R3J-0-U-G P

40 mils

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

C1501

12

40 mils

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

C1511

12

1231-2

20 mils

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

C1514

12

DY

40 mils

SC4D7U6D3V3KX-GP

C1528

12

15 mils

SC1U6D3V2KX-GP

C1534

12

15 mils

SC1U10V3KX-3GP

C1542

12

UMA/DIS

9/15

Layout Note

5

1.1V(0.6A) for VDDHT

+1.1V_RU N_VDDHT

SCD1U10V2KX-5GP

C1502

12

DY

1.1V(0.7A) for VDDHTRX

+1.1V_RU N_VDDHTRX

SCD1U10V2KX-5GP

C1507

12

DY

1.1V(0.4A) for VDDHTTX

+1.2V_RU N_VDDHTTX

SCD1U10V2KX-5GP

C1515

12

DY

C1503

C1506

12

DY

SCD1U10V2KX-5GP

C1513

C1512

12

DY

SCD1U10V2KX-5GP

C1517

C1516

12

1231-2

1.8V(0.7A) for VDDA18PCIE

SCD1U10V2KX-5GP

C1529

12

DY

+1.8V_RU N_VDDA18PCIE

C1530

12

SCD1U10V2KX-5GP

C1531

12

DY

1.8V(0.01A) for VDD18

1.8V(0.025A) for VDD18

C1518

SCD1U10V2KX-5GP

C1532

VDD18_M EM

U1F

A25

M20

W22 W24 W25

AD25

M14

W11

W15 AC12 AA14

AB11 AB15 AB17 AB19 AE20 AB21

D23 E22 G22 G24 G25 H19

N22 P20 R19 R22 R24 R25 H20 U22 V19

Y21

N13 P12 P15 R11 R14 T12 U14 U11 U15 V12

Y18

K11

J22 L17 L22 L24 L25

L12

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

RS880M-1 -GP

PART 6/6

U1E

J17

VDDHT_1

K16 L16

M16

P16

R16

T16

H18 G19

F20 E21

D22

B23 A23

AE25 AD24 AC23 AB22 AA21

Y20

W19

V18

U17

T17

R17

P17

M17

J10 P10 K10

C1533

12

M10

R10

AA9 AB9 AD9 AE9 U10

AE11 AD11

L10 W9

H9

T10

Y9

F9

G9

VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2

RS880M-1 -GP

PART 5/6

POWER

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDD_MEM1

VDD_MEM2

VDD_MEM3

VDD_MEM4

VDD_MEM5

VDD_MEM6

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD33_1 VDD33_2

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

1.1V(2.5A) for VDDPCIE

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

DY

SC1U6D3V2KX-GP

C1504

C1509

12

C1509

12

SC4D7U6D3V3KX-GP

C1508

12

1231-2 1231-2

0.95~1.1V(12A) for VDDC

SCD1U10V2KX-5GP

12

C1520

C1519

10/8 10/8

12

SBD MEM ENABLE

1.5V(0.1A) for VDD_MEM

VDD_MEM _SDP

UMA_SPM/DIS_NOSPM

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

C1541

12

UMA_SPM

3.3V(0.06A) for VDD33

SCD1U10V2KX-5GP

C1535

12

DY

SCD1U10V2KX-5GP

C1537

12

DY

UMA_SPM

1231-2

C1536

SCD1U10V2KX-5GP

C1538

+1.1V_RU N_VDDPCIE

C1510

C1522

SCD1U10V2KX-5GP

12

130 mils

C1505

550 mils

SCD1U10V2KX-5GP

12

DY

SC1U6D3V2KX-GP

12

DY

SCD1U10V2KX-5GP

12

DY

1231-2 1231-2

12

C1540

15 mils

SCD1U10V2KX-5GP

C1539

12

UMA_SPM

15 mils

Layout Note

1215-1

SCD1U10V2KX-5GP

C1525

C1524

12

+1.1V_RU N

G1501

1 2

GAP-CLOS E-PWR-3-GP

G1502

1 2

GAP-CLOS E-PWR-3-GP

G1503

1 2

GAP-CLOS E-PWR-3-GP

G1504

1 2

GAP-CLOS E-PWR-3-GP

+NB_VCORE

+NB_VDD C

SC10U6D3V5KX-1GP

C1526

12

+1.5V_RU N

R1506

0R3J-0-U-G P

1 2

UMA_SPM

+3.3V_RU N

12

10/5

9/11

C1527

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

1231-2

1117-2

0104-1

R1507

1 2

PBY160808 T-330Y-N-GP

R1508

1 2

PBY160808 T-330Y-N-GP

R1509

1 2

PBY160808 T-330Y-N-GP

R1510

1 2

PBY160808 T-330Y-N-GP

R1511

1 2

PBY160808 T-330Y-N-GP

4

3

2

+1.1V_RU N+NB_VDD C

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AMD-RS880M_PWR&GD_(4/4)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

1

A00

15 95Thursday, March 04 , 2010

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 95Thursday, March 04 , 2010

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

17 95Thursday, March 04 , 2010

A00

5

4

3

2

1

SSID = MEMORY

11/10

DM1

C1822

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 41-GP-U

62.10017.N41

H =5.2mm

4

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

M_A_DM0

11

DM0

M_A_DM1

28

DM1

M_A_DM2

46

DM2

M_A_DM3

63

DM3

M_A_DM4

136

DM4

M_A_DM5

153

DM5

M_A_DM6

170

DM6

M_A_DM7

187

DM7

SB_SMBDATA

200

SDA

SB_SMBCLK

202

SCL

PM_EXTTS#0

198

199

197

SA0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1.5V, 3.5A

+1.5V_SUS

MEM_MA_RAS# ( 9) MEM_MA_WE# (9) MEM_MA_CAS# ( 9)

MEM_MA0_CS#0 ( 9) MEM_MA0_CS#1 ( 9)

MEM_MA_CKE0 ( 9) MEM_MA_CKE1 ( 9)

MEM_MA_CLK0_P (9) MEM_MA_CLK0_N (9)

MEM_MA_CLK1_P (9) MEM_MA_CLK1_N (9)

M_A_DM[7..0] (9)

9/23

Note: SA0 = 0, SA1 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

Layout Note: Place these Caps near SO-DIMMA.

+1.5V_SUS

PM_EXTTS#0

1 2

DY

R18064K7R2J -2-GPDYR18064K7R2J -2-GP

0107-4

SB_SMBDATA(19,76)

+3.3V_RUN

3.3V, 2mA

SCD1U10V2KX-5GP

C1802

12

9/23

SB_SMBCLK(19,76)

SB_SMBCLK SB_SMBDATA

RN

0R4P2R-PAD

1

4 2 3

RN1801

DY

1 2

C1823 SC10P50V2JN -4GP

1 2

C1824 SC10P50V2JN -4GP

DY

SB_SMBDATA_R (7,21) SB_SMBCLK_R (7,21)

SODIMM A DECOUPLING (ONE CAP PER POWER PIN)

+1.5V_SUS

SCD1U10V2KX-5GP

12

C1812

SC10U10V5ZY-1GP

12

DY

3

C1813

C1806

C1805

C1804

12

C1814

C1815

SC10U10V5ZY-1GP

12

DY

SCD1U10V2KX-5GP

C1808

C1809

C1807

12

1225-1

SE330U2VDM-L-GP

TC1801

C1817

C1816

SC10U10V5ZY-1GP

12

DY

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM1

Berry AMD Discrete/UMA

1

18 95Thursday, March 04, 2010

A00

MEM_MA_ADD[0..15](9)

D D

MEM_MA_BANK2(9)

MEM_MA_BANK0(9) MEM_MA_BANK1(9)

M_A_DQ[63..0](9)

C C

M_A_DQS#0(9) M_A_DQS#1(9) M_A_DQS#2(9) M_A_DQS#3(9)

B B

+V_DDR_RE F

SCD1U10V2KX-5GP

SCD01U50V3KX-4GP

SCD1U10V2KX-5GP

9/14

C1825

12

SCD1U10V2KX-5GP

C1810

12

M_A_DQS#4(9) M_A_DQS#5(9) M_A_DQS#6(9) M_A_DQS#7(9)

M_A_DQS0(9) M_A_DQS1(9) M_A_DQS2(9) M_A_DQS3(9) M_A_DQS4(9) M_A_DQS5(9) M_A_DQS6(9) M_A_DQS7(9)

MEM_MA0_ODT0(9) MEM_MA0_ODT1(9)

9/23

C1811

12

DDR3_A_DR AMRST#(9)

0108-3

10/7

+0.75V_DDR_VT T

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

SCD1U10V2KX-5GP

12

DY

0.75V, 0.5A

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

C1819

C1820

C1821

Place these caps close to VTT1 and

A A

VTT2.

5

12

1231-2

C1821

12

DY

5

+V_DDR_RE F

SCD01U50V3KX-4GP

12

MEM_MB_ADD[0..15](9)

MEM_MB_BANK2(9)

MEM_MB_BANK0(9) MEM_MB_BANK1(9)

M_B_DQ[63..0](9)

M_B_DQS#0(9) M_B_DQS#1(9) M_B_DQS#2(9) M_B_DQS#3(9) M_B_DQS#4(9) M_B_DQS#5(9) M_B_DQS#6(9) M_B_DQS#7(9)

M_B_DQS0(9) M_B_DQS1(9) M_B_DQS2(9) M_B_DQS3(9) M_B_DQS4(9) M_B_DQS5(9) M_B_DQS6(9) M_B_DQS7(9)

MEM_MB0_ODT0(9) MEM_MB0_ODT1(9)

SCD1U10V2KX-5GP

C1905

C1904

12

DDR3_B_DR AMRST#(9)

10/7

+0.75V_DDR_VT T

SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

C1918

C1919

12

DY

SSID = MEMORY

D D

C C

B B

SCD1U10V2KX-5GP

9/14 9/23

C1922

12

0108-3

Place these caps close to VTT1 and VTT2.

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

SCD1U10V2KX-5GP

12

DY

0.75V, 0.5A

C1920

12

4

C1921

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 40-GP-U

H = 9.2mm

11/10

NP1

NP2

110

RAS#

113

WE#

115

CAS#

114

CS0#

121

CS1#

73

CKE0

74

CKE1

101

CK0

103

CK0#

102

CK1

104

CK1#

M_B_DM0

11

DM0

M_B_DM1

28

DM1

M_B_DM2

46

DM2

M_B_DM3

63

DM3

M_B_DM4

136

DM4

M_B_DM5

153

DM5

M_B_DM6

170

DM6

M_B_DM7

187

DM7

SB_SMBDATA

200

SDA

SB_SMBCLK

202

SCL

PM_EXTTS#1

198

EVENT#

199

VDDSPD

197

SA0

201

SA1

77

NC#1

122

NC#2

125

NC#/TEST

1.5V, 3.5A

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

SO-DIMMB is placed farther from the Processor than SO-DIMMA

+1.5V_SUS

MEM_MB_RAS# (9) MEM_MB_WE# (9) MEM_MB_CAS# (9)

MEM_MB0_CS#0 ( 9) MEM_MB0_CS#1 ( 9)

MEM_MB_CKE0 (9) MEM_MB_CKE1 (9)

MEM_MB_CLK0_P (9) MEM_MB_CLK0_N (9)

MEM_MB_CLK1_P (9) MEM_MB_CLK1_N (9)

M_B_DM[7..0] (9)

9/23

+3.3V_RUN

9/23

3

SB_SMBDATA ( 18,76) SB_SMBCLK (18,76)

3.3V, 2mA

SCD1U10V2KX-5GP

C1902

12

9/23

Note: SA0 = 0, SA1 = 1 SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

Layout Note: Place these Caps near SO-DIMMB.

+3.3V_RUN

C1912

+1.5V_SUS

SCD1U10V2KX-5GP

12

SC10U10V5ZY-1GP

12

DY

2

+1.5V_SUS

PM_EXTTS#1

1 2

DY

R19064K7R 2J-2-GPDYR19064K7R 2J-2-GP

SODIMM B DECOUPLING (ONE CAP PER POWER PIN)

SCD1U10V2KX-5GP

C1909

C1910

C1911

12

C1916

SC10U10V5ZY-1GP

12

DY

C1911

12

C1917

SC10U10V5ZY-1GP

12

DY

C1913

SCD1U10V2KX-5GP

C1907

C1906

C1908

12

C1915

C1914

SC10U10V5ZY-1GP

12

DY

1

1231-2

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM2

Berry AMD Discrete/UMA

1

19 95Thursday, March 04, 2010

A00

5

SSID = S.B

C2001 SC150P5 0V2KX-GPC20 01 SC150P5 0V2KX-GP

1 2

ALINK_NBR X_SBTX_P0(12) ALINK_NBR X_SBTX_N0(12) ALINK_NBR X_SBTX_P1(12)

D D

Place R <100mils form pins AD29,AD28

C C

ALINK_NBR X_SBTX_N1(12) ALINK_NBR X_SBTX_P2(12) ALINK_NBR X_SBTX_N2(12) ALINK_NBR X_SBTX_P3(12) ALINK_NBR X_SBTX_N3(12)

ALINK_NBT X_SBRX_P0(12) ALINK_NBT X_SBRX_N0(12) ALINK_NBT X_SBRX_P1(12) ALINK_NBT X_SBRX_N1(12) ALINK_NBT X_SBRX_P2(12) ALINK_NBT X_SBRX_N2(12) ALINK_NBT X_SBRX_P3(12) ALINK_NBT X_SBRX_N3(12)

+1.1V_RU N_PCIE_VDDR

NOTE: SB8XX ONLY SUPPORTS 2 GPP PORT 2 AND 3 IS NOT SUPPORTED. (From CRB)

SB820M : 71.SB820.M02

R2024 22R2J-2-G PR2024 22R2J -2-GP

C2002 S CD1U10V2KX-5G PC2002 S CD1U10V2KX-5G P

1 2

C2003 S CD1U10V2KX-5G PC2003 S CD1U10V2KX-5G P

1 2

C2004 S CD1U10V2KX-5G PC2004 S CD1U10V2KX-5G P

1 2

C2005 S CD1U10V2KX-5G PC2005 S CD1U10V2KX-5G P

1 2

C2006 S CD1U10V2KX-5G PC2006 S CD1U10V2KX-5G P

1 2

C2007 S CD1U10V2KX-5G PC2007 S CD1U10V2KX-5G P

1 2

C2008 S CD1U10V2KX-5G PC2008 S CD1U10V2KX-5G P

1 2

C2009 S CD1U10V2KX-5G PC2009 S CD1U10V2KX-5G P

1 2

R2002 590R2F-GPR 2002 590 R2F-GP

1 2

R2007 2KR2F-3-GPR2007 2 KR2F-3-GP

1 2

ALINK_NBR X_SBTX_C_P0 ALINK_NBR X_SBTX_C_N0 ALINK_NBR X_SBTX_C_P1 ALINK_NBR X_SBTX_C_N1 ALINK_NBR X_SBTX_C_P2 ALINK_NBR X_SBTX_C_N2 ALINK_NBR X_SBTX_C_P3 ALINK_NBR X_SBTX_C_N3

9/23

SB_PCIE_C LK(7) SB_PCIE_C LK#(7 )

B B

1nd 82.30020.791

A A

SC12P50 V2JN-3GP

R2017 1MR2J-1-G PR2017 1MR2J-1-GP

1 2

X2001

1 2

XTAL-25M HZ-96GP

C2014

1113-1

1 2

XTAL-25M HZ-96GP

5

1 2

2nd 82.30020.851

25M_X1

25M_X2

C2015

C2015 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

4

PCIE_RST# _SB

A_RST#_ RA_RST#

SB_PCIE_C ALRP SB_PCIE_C ALRN

SB_PCIE_C LK SB_PCIE_C LK#

25M_X1

25M_X2

4

9/11

U2A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M-1-GP

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

REQ2#/CLK_REQ8#/GPIO41

PCI INTERFACELPC

REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

ALLOW_LDTSTP/DMA_ACTIVE#

CLOCK GENERATOR

CPU

RTC

3

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR# REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44 GNT2#/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

PROCHOT#

LDT_PG LDT_STP# LDT_RST#

32K_X1

32K_X2

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

3

W2 W1 W3 W4

PCLK_FW H_R

Y1

PCI_RST#

V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2

1119-1

AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6

SB_GPIO46

AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

LPCCLK0 _R

H24

LPCCLK1 _R

H25

LPC_LAD 0

J27

LPC_LAD 1

J26

LPC_LAD 2

H29

LPC_LAD 3

H28 G28

TP_LPC_ LDRQ0#

J25

TP_LPC_ LDRQ1#

AA18 AB19

G21 H21 K19 G22 J24

32K_X1

C1

32K_X2_ R

C2

RTC_CLK

D2

INTRUDER_ ALERT#

B2 B1

1

TP_PCI_AD 28 TP_PCI_AD 29

R2029 22R2J-2-G P

1 2

DY

TP2008TP2008

9/24

9/16

PCI_AD23 (24)

PCI_AD25 (24) PCI_AD26 (24) PCI_AD27 (24)

1

TP2009TP2009

1

TP2001TP2001

9/25

GP_PCIE_R ST#(2 1)

A_RST#

TP2004TP2004

1

9/23

1118-2

RN2008

1

4

2 3

SRN22-3-G P

1

TP2005TP2005

1

R2018 1 0R2J-2-GPR2018 10R2 J-2-GP

1

TP2007TP2007

to EC

TP2006TP2006

ALLOW _LDTSTOP (13)

CPU_PRO CHOT# (10) CPU_LDT _PWRGD (10,4 2) CPU_LDT _STOP# (10,13) CPU_LDT _RST# (10)

1 2

SCD1U10V2KX-5GP

C2017

12

DY

2

PCI_CLK1 (24) PCI_CLK2 (24) PCI_CLK3 (24) PCLK_FW H (24 ,70)

11/6

R2025

R2025 22R2J-2-G P

PCIE_RST# _SB PLTRST# _LAN_WLA N

22R2J-2-G P

STRAP PIN

12

C2013

SC150P5 0V2KX-GP

DY

1 2

9/22

VDDR_SE L (24,51)

+3.3V_AL W

SCD1U10V2KX-5GP

C2010

U2001

1

DY

B

VCC

2

A

3

PM_CLKR UN# (37 )

1 2

C2018 SC10P50 V2JN-4GP

LPCCLK1 (24)

LPC_LAD 0 (3 7,70) LPC_LAD 1 (3 7,70) LPC_LAD 2 (3 7,70) LPC_LAD 3 (3 7,70)

LPC_LFR AME# (37,7 0)

+RTC_CE LL

Y

GND

74LVC1G 08GW-1-GP

1 2

R2021

R2021 0R0402-P AD

0R0402-P AD

DY

LPC Bus Routing first connects to MINICARD then connects to KBC

INT_SERIRQ (37)

RTCCLK_ KBC (37 )

RTC_CLK (39)

2

5

4

1231-1

12

DY

PLTRST#

11/6

9/23

PCLK_KB C (24,37)

32K_X1

32K_X2_ R 32K_X2

Title

SB820M_PCIE&PCI_(1/5)

Size Document N umber Rev

A3

Date: Sheet of

+3.3V_RU N

11/6

12

R2026

R2026 10KR2J-3 -GP

10KR2J-3 -GP

11/6

R2028

12

DY

0R2J-2-GP

1231-1

R2005

12

0R0402-P AD

R2008

0R0402-P AD

R2016

12

0R0402-P AD

1231-1

Berry AMD Discrete/UMA

PLTRST# _NB_GPU (13,3 7,80)

12

PLTRST# _EC (37)

12

R2014

20MR3-GP

X-32D768 KHZ-38GPU

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

PLTRST# _LAN_WLA N (70,7 6,78)

1119-1

GPU,NB

KBC

11/12-1

1 2

C2011

SC18P50 V2JN-1-GP

4

1

2 3

X2002

1 2

C2012

SC15P50 V2JN-2-GP

11/12-1

20 95Friday, March 05, 201 0

1

A00

5

4

3

2

1

SSID = S.B

+3.3V_RU N

D D

+3.3V_AL W

C C

B B

+3.3V_AL W

A A

1119-5

RN2101

1 2 3

SRN4K7J -8-GP

4

9/23

9/22

RN2103

1

4

2 3

SRN10KJ -5-GP

R2132

1 2

VRAMUMA_SPM_Hynix

R2132 10KR2J-3 -GP

10KR2J-3 -GP

R2108

DY

2K2R2J-2 -GP

R2110

DY

2K2R2J-2 -GP

R2112

DY

2K2R2J-2 -GP

R2113

R2113 10KR2J-3 -GP

10KR2J-3 -GP

R2114

DY

10KR2J-3 -GP

R2115

R2115 10KR2J-3 -GP

10KR2J-3 -GP

R2116

DY

10KR2J-3 -GP

R2117

DY

10KR2J-3 -GP

R2118

DY

10KR2J-3 -GP

10KR2J-3 -GP R2119

R2119

DY

10KR2J-3 -GP

R2133

R2133 0R2J-2-GP

0R2J-2-GP

10/1

RN2102

1

8

2

7

3

6

4 5

SRN10KJ -6-GP

R2124 1 0KR2J-3-GPR2124 1 0KR2J-3-GP

1 2

RN2104

1

4

2 3

SRN10KJ -5-GP

9/23

SB_SMBDATA_R SB_SMBC LK_R

SMB_DAT A

SMB_CLK

9/22

TALERT#

SB_TEST 2

SB_TEST 1

SB_TEST 0

PCIE_W AKE#

KBC_RSM RST#

SIO_EXT_W AKE#

SIO_EXT_S CI#

SIO_EXT_S MI#

SB_SDIN_C ODEC

ACZ_BIT_C LK

SP_VRAM _SEL

0225-4

GBE_COL GBE_CRS GBE_RXE RR GBE_MDIO

GBE_PHY_INTR

SCL2 SDA2

SCD1U10V2KX-5GP

C2104

12

SCD1U10V2KX-5GP

C2103

12

1116-3

SB_AZ_C ODEC_BITCLK(30) SB_AZ_C ODEC_SDOUT(30)

SB_AZ_C ODEC_SYNC(30) SB_AZ_C ODEC_RST#(30)

0113-1

SIO_RCIN#

12

C2105

C2105 SCD047U 10V2KX-2GP

SCD047U 10V2KX-2GP

SB_SDIN_C ODEC(30)

9/25

9/16

R21060R04 02-PAD R21060R 0402-PAD

SCD1U10V2KX-5GP

C2101

12

DY

R21280R 2J-2-GP

GbE MAC Not Enabled

TP_PCI_PM E#

1

PM_PW RBTN#_R

SUS_STA T#

SB_TEST 0 SB_TEST 1 SB_TEST 2

SYS_RESET #

1

SB_THER MTRIP#

PM_RSMR ST#_R

Close SB

9/23

SB_SMBC LK_R SB_SMBD ATA_R

SMB_CLK

SMB_DAT A

CLK_REQ 2#

1

SP_VRAM _SEL

SB_GPIO51

1

GEVENT7 #

SB_OSCINSB_ OSCIN

9/23

USB_OC7 #

1

USB_OC6 #

1

USB_OC4 #

1

USB_OC3 #

1

USB_OC2 #

1

USB_OC# 2_3 USB_OC# 0_1

ACZ_BIT_C LK

ACZ_SYNC_ R ACZ_RST #_R

GBE_COL GBE_CRS

GBE_MDIO

GBE_RXE RR

GBE_PHY_INTR

SPI_CS2#

1

GPO160

1

SIO_EXT_W AKE#(37)

PM_SLP_ S3#(37,41,42,4 9,52,89) PM_SLP_ S5#(37 ,49)

PM_PW RBTN#(37) SB_PW RGD(7,41) SUS_STA T#(13)

10/7 10/7

SIO_A20GA TE(37) SIO_RCIN#(37) SIO_EXT_S CI#(3 7) SIO_EXT_S MI#(37)

PCIE_W AKE#(76)

H_THERM TRIP#(1 0,37,39,42,82)

NB_PW RGD(41 )

KBC_RSM RST#(37)

GP_PCIE_R ST#(20 )

ACZ_SPK R(30) SB_SMBC LK_R(7,18 ) SB_SMBD ATA_R(7,18 )

SP_DDR3 _RST#(14)

SB_14M_ CLK(7)

1 2

C2102 SC180P5 0V2JN-1GP

R2111

R2111 0R0402-P AD

0R0402-P AD

1231-1

GP_PCIE_R ST# GP_PCIE_R ST#

R2131

9/22

USB_OC# 2_3(63) USB_OC# 0_1(63)

ACZ_SDA TAOUT_R(24)

33R2J-2-G PR2120 33R2J-2-G PR2120 33R2J-2-G PR2121 33R2J-2-G PR2121

9/16

EC2101

12

SC180P5 0V2JN-1GP

33R2J-2-G PR2122 33R2J-2-G PR2122 33R2J-2-G PR2123 33R2J-2-G PR2123

TP2135TP2135 TP2134TP2134

SC180P50V2JN-1GP

DY

1 2 1 2

DY

1 2 1 2

EC2102

12

TP2101TP2101

9/23

1 2

1231-1

DY

TP2120TP2120

1 2

R2109 0R0402-P ADR2109 0R0402-P AD

1 2

TP2127TP2127

TP2113TP2113

1 2

UMA_SPM

0R2J-2-GP

1 2

DY

TP2133TP2133 TP2129TP2129

TALERT#(10,39)

TP2132TP2132 TP2131TP2131 TP2130TP2130

9/24

TP_DEBU G_DAT

1

TP_DEBU G_CLK

1

TP2116TP2116 TP2117TP2117

EC Not Implemented

5

4

U2D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

CLK_REQ3#/SATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SATA_IS4#/FANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GPIO65/OSCIN/IDLEEXT#

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB820M-1 -GP

3

Part 4 of 5

HD AUDIO

GBE LAN

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P USB_HSD13N

USB 1.1USB MISCEMBEDDED CTRL

USB_HSD12P

ACPI / WAKE UP EVENTS

GPIO

USB OC

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P

USB 2.0

USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

A10

G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB_48M _CLK

USB_RCO MP

USB_PP5 USB_PN5

USB_PP1 USB_PN1

SCL2 SDA2

EC Not Implemented

2

USB_48M _CLK (7)

SC180P50V2JN-1GP

USB_PP5 (76) USB_PN5 (76)

SC180P50V2JN-1GP

DY

EC2103

12

USB

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Device

USB0 (I/O Board/ESATA)

USB1 (I/O Board)

USB2 (CRT Board)

USB3 (CRT Board)

WLAN USB

WWAN USB

RESERVED

BLUETOOTH

CARD READER

CAMERA (LVDS CONN)

RESERVED

1 2

R2102

R2102 11K8R2F -GP

11K8R2F -GP

USB_PP1 1 (54) USB_PN1 1 (54)

USB_PP1 0 (78) USB_PN1 0 (78)

USB_PP9 (73) USB_PN9 (73)

USB_PP4 (76) USB_PN4 (76)

USB_PP3 (77) USB_PN3 (77)

USB_PP2 (77) USB_PN2 (77)

USB_PP1 (76) USB_PN1 (76)

USB_PP0 (76) USB_PN0 (76)

Not use

CPU_SIC (10) CPU_SID (10 )

SB_GPO1 99 (24) SB_GPO2 00 (24)

Strap Pin / define to use LPC or SPI ROM

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SB820M_USB&GPIO_(2/5)

Size Document N umber Rev

A3

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

1

A00

21 95Thursday, March 04 , 2010

A00

SSID = S.B

9/15

XTAL 1'nd 82.30020.851

DY

C2209

1 2

SC12P50 V2JN-3GP

DY

C2210

1 2

SC12P50 V2JN-3GP

2'nd 82.30020.791

XTAL-25MHZ-102-GP

12

DY

10MR2J-L-GP

X2201

SATA HDD

SATA ODD

E-SATA

12

R2204

DY

SATA_TX P0(59) SATA_TX N0(59)

SATA_RX N0(59) SATA_RX P0(5 9)

SATA_TX P1(59) SATA_TX N1(59)

SATA_RX N1(59) SATA_RX P1(5 9)

SATA_TX P2(76) SATA_TX N2(76)

SATA_RX N2(76) SATA_RX P2(7 6)

PLACE SATA AC DECOUPLING CAPS CLOSE TO SB820M

+1.1V_RU N_AVDD_SATA

SATA_X1

SATA_X2

C2201 SCD01U5 0V2ZY-1GPC2 201 SCD0 1U50V2ZY-1GP

1 2

C2202 SCD01U5 0V2ZY-1GPC2 202 SCD0 1U50V2ZY-1GP

1 2

C2203 SCD01U5 0V2ZY-1GPC2 203 SCD0 1U50V2ZY-1GP

1 2

C2204 SCD01U5 0V2ZY-1GPC2 204 SCD0 1U50V2ZY-1GP

1 2

C2205 SCD01U5 0V2ZY-1GPC2 205 SCD0 1U50V2ZY-1GP

1 2

C2206 SCD01U5 0V2ZY-1GPC2 206 SCD0 1U50V2ZY-1GP

1 2

C2208 SCD01U5 0V2ZY-1GPC2 208 SCD0 1U50V2ZY-1GP

1 2

C2207 SCD01U5 0V2ZY-1GPC2 207 SCD0 1U50V2ZY-1GP

1 2

C2211 SCD01U5 0V2ZY-1GPC2 211 SCD0 1U50V2ZY-1GP

1 2

C2214 SCD01U5 0V2ZY-1GPC2 214 SCD0 1U50V2ZY-1GP

1 2

SATA_TX P0_C SATA_TX N0_C

SATA_RX N0_C SATA_RX P0_C

SATA_TX P1_C SATA_TX N1_C

SATA_RX N1_C SATA_RX P1_C

SATA_TX P2_C SATA_TX N2_C

SATA_RX N2 SATA_RX P2

10/6

Very Close to SB820

1KR2F-3-G P

R2201

1 2 1 2

R2202 931R2F-1 -GPR2202 931R2F-1 -GP

SATA_LE D#(66)

SATA_X1

SATA_X2

SPI ROM in KBC side

SATA_CA LP SATA_CA LN

AH10

AJ10

AG10

AF10

AG12

AF12

AJ12

AH12

AH14

AJ14

AG14

AF14

AG17

AF17

AJ17

AH17

AJ18

AH18

AH19

AJ19

AB14 AA14

AD11

AD16

AC16

9/24

U2B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_TX2P SATA_TX2N

SATA_RX2N SATA_RX2P

SATA_TX3P SATA_TX3N

SATA_RX3N SATA_RX3P

SATA_TX4P SATA_TX4N

SATA_RX4N SATA_RX4P

SATA_TX5P SATA_TX5N

SATA_RX5N SATA_RX5P

SATA_CALRP SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1#/GPIO165

G2

ROM_RST#/GPIO161

SB820M-1-GP

Part 2 of 5

SERIAL ATA

HW MONITOR

SPI ROM

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE#/GPIOD145

FC_AVD#/GPIOD146

FC_WE#/GPIOD148 FC_CE1#/GPIOD149 FC_CE2#/GPIOD150

FC_INT1/GPIOD144 FC_INT2/GPIOD147

FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137

FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

FLASH

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

TEMP_COMM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

NC#G27 NC2#Y2

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6 Y9

W7 V9 W8

B6 A6 A5 B5 C7

A3 B4 A4 C5 A7 B7 B8 A8

G27 Y2

GPIOD[150:128] are open drain GPIO pins where as GPO160 is an open drain GPO pin. These pins are not programmed to GPIO mode by default.

If use as GPIO, need to pull up to 1.8V_RUN

TEMPIN0 TEMPIN1 TEMPIN2 TEMPIN3

VIN0 VIN1 VIN2 VIN3 MEM_1V5 VIN5 VIN6 VIN7

10/9

MEM_1V5 (51)

9/22

1119-1

Move to P.51

TEMPIN0 TEMPIN1 TEMPIN2 TEMPIN3

9/16

1 2 3 4 5

10/1

VIN2 VIN0 VIN1 VIN3

10/9

VIN7 VIN6 VIN5

1 2 3 4 5

RN2201

8 7 6

SRN10KJ -6-GP

RN2202

8 7 6

SRN10KJ -6-GP

RN2203

8 7 6

SRN10KJ -6-GP

+3.3V_AL W

1116-1

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

SB820M_SATA-IDE_(3/5)

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

22 95Thursday, March 04 , 2010

A00

5

4

3

2

1

+3.3V_RU N

1231-1

D D

+1.8V_RU N

1231-1

+3.3V_RU N

BLM15AG 221SS1D-GP

1119-1

9/15

+1.1V_RU N +1.1V_RUN _PCIE_VDDR

C C

PBY160808 T-330Y-N-GP

+3.3V_RU N

BLM15AG 221SS1D-GP

1119-1

9/15

+1.1V_RU N +1.1V_RUN _AVDD_SATA

1 2

PBY160808 T-330Y-N-GP

33R, 3A

B B

1119-1

+3.3V_AL W +3.3V_AVD D_USB

1 2

PBY160808 T-221Y-N-GP

220R, 2A

+1.1V_AL W +1.1V_AVD D_USB

1 2

BLM15AG 221SS1D-GP

220R, 0.3A

R2301

1 2

0R0603-P AD

R2302

1 2

0R0603-P AD

L2301

1 2

220R, 0.3A

L2303

1 2

33R, 3A

L2304

1 2

220R, 0.3A

L2305

L2307

L2309

+3.3V_SB _VDDIO

+1.8V_SB _VDDIO_FC

9/17

+3.3V_VD DPL_PCIE

+3.3V_VD DPL_SATA

SC10U6D3V5KX-1GP

SC2D2U6D3V3KX-GP

SC10U6D3V5KX-1GP

SC2D2U6D3V3KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC2D2U6D3V3KX-GP

TC2301

12

Removed

C2313

12

TC2303

12

C2325

12

TC2304

12

C2337

12

C2343

12

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

DY

78mA

SCD1U10V2KX-5GP

DY

C2320

C2331

C2339

C2302

12

SCD1U10V2KX-5GP

SC10U10V5ZY-1GP

SCD1U10V2KX-5GP

DY

0.15mA

C2307

12

DY

11mA

690mA

SCD1U10V2KX-5GP

C2321

12

DY

15mA

1350mA

SCD1U10V2KX-5GP

C2332

12

534mA

C2340

12

88mA

C2303

12

AC21

AA19

AE25

AC22

AE28

C2322

12

AD14

AH20 AG19 AE18 AD18 AE16

C2333

12

SCD1U10V2KX-5GP

C2301

12

C2314

12

SC1U6D3V2KX-GP

C2319

12

DY

C2326

12

SC1U6D3V2KX-GP

C2330

12

DY

SC10U6D3V5KX-1GP

C2338

12

C2344

12

SSID = S.B

U2C

AH1

VDDIO_33_PCIGP

V6

VDDIO_33_PCIGP

Y19

VDDIO_33_PCIGP

AE5

VDDIO_33_PCIGP VDDIO_33_PCIGP

AA2

VDDIO_33_PCIGP

AB4

VDDIO_33_PCIGP

AC8

VDDIO_33_PCIGP

AA7

VDDIO_33_PCIGP

AA9

VDDIO_33_PCIGP

AF7

VDDIO_33_PCIGP VDDIO_33_PCIGP

AF22

VDDIO_18_FC VDDIO_18_FC

AF24

VDDIO_18_FC VDDIO_18_FC

POWER

VDDPL_33_PCIE

U26

VDDAN_11_PCIE

V22

VDDAN_11_PCIE

V26

VDDAN_11_PCIE

V27

VDDAN_11_PCIE

V28

VDDAN_11_PCIE

V29

VDDAN_11_PCIE

W22

VDDAN_11_PCIE

W26

VDDAN_11_PCIE

VDDPL_33_SATA

AJ20

VDDAN_11_SATA

AF18

VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA

A18

VDDAN_33_USB_S

A19

VDDAN_33_USB_S

A20

VDDAN_33_USB_S

B18

VDDAN_33_USB_S

B19

VDDAN_33_USB_S

B20

VDDAN_33_USB_S

C18

VDDAN_33_USB_S

C20

VDDAN_33_USB_S

D18

VDDAN_33_USB_S

D19

VDDAN_33_USB_S

D20

VDDAN_33_USB_S

E19

VDDAN_33_USB_S

C11

VDDAN_11_USB_S

D11

VDDAN_11_USB_S

SB820M-1 -GP

Part 3 of 5

PCI/GPIO I/O

FLASH I/O

GBE LAN

PCI EXPRESSSERIAL ATA

USB I/O

PLL CLKGEN I/O

VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11

CORE S03.3V_S5 I/O

VDDCR_11 VDDCR_11

VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK

VDDRF_GBE_S

VDDIO_33_GBE_S

VDDCR_11_GBE_S VDDCR_11_GBE_S

VDDIO_GBE_S VDDIO_GBE_S

VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S

VDDCR_11_S VDDCR_11_S

VDDIO_AZ_S

CORE S5

VDDCR_11_USB_S VDDCR_11_USB_S

VDDPL_33_SYS

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

N13 R15 N17 U13 U17 V12 V18 W12 W18

K28 K29 J28 K26 J21 J20 K21 J22

V1

M10

GBE PHY not used

L7 L9

M6 P8

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

+3.3VALW _VDDIO_AZ

M8

A11 B11

3.3V_RUN _VDDPL

M21

1.1V_ALW _VDDPL

L22

F19

D6

3.3V_ALW _VDDXL

L20

790mA

SCD1U10V2KX-5GP

382mA

49mA

113mA

58mA

C2304

12

SCD1U10V2KX-5GP

C2315

12

15mA

1 2

R2303

1231-1

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

DY

0R0402-P AD

U2E

Part 5 of 5

Y14

VSSIO_SATA

Y16

VSSIO_SATA

AB16

VSSIO_SATA

AC14

+1.1V_RU N

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC2D2U6D3V3KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

12

DY

SC10U6D3V5KX-1GP

C2311

C2318

C2323

C2327

C2335

C2311

12

SC10U6D3V5KX-1GP

12

+3.3V_AL W

SC2D2U6D3V3KX-GP

12

+1.1V_AL W

SC1U6D3V2KX-GP

12

SC10U6D3V5KX-1GP

12

TC2302

C2324

C2328

C2336

+1.1V_RU N+1.1V_RU N_SB_CLKGEN

1 2

R2304 0R0603-P ADR2 304 0R0603-PA D

1231-1

+1.1V_AL W+1.1V_AL W_VDDR_US B

L2306

1 2

BLM15AG 221SS1D-GP

220R, 0.3A

C2310

12

SC1U6D3V2KX-GP

C2308

C2316

12

C2309

12

DY

SC1U6D3V2KX-GP

12

+3.3V_AL W

SC2D2U6D3V3KX-GP

12

SCD1U10V2KX-5GP

12

DY

SC1U6D3V2KX-GP

C2317

C2329

C2334

1119-1

9/17

16mA

+3.3V_AV DD_USB

SCD1U10V2KX-5GP

C2347

12

SC2D2U6D3V3KX-GP

C2348

12

AE12 AE14

AF11 AF13 AF16

AG8

AH7 AH11 AH13 AH16

AJ11 AJ13 AJ16

G11

M19

M22 M24 M26

AF9

AJ7

B10 K11

D10 D12 D14 D17

F12 F14 F16

F18

H12 H14 H16 H18 J11 J19 K12 K14 K16 K18 H19

P21 P20

P22 P24 P26 T20 T22 T24 V20 J23

A9

B9

E9 F9

C9

D9

Y4

D8

VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA VSSIO_SATA

VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB

EFUSE

VSSAN_HWM

VSSXL

VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK

SB820M-1 -GP

Part 5 of 5

GROUND

VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK

VSSPL_SYS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8

M20

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

A A

3.3V_ALW _VDDXL

SCD1U10V2KX-5GP

9/15

DY

C2341

12

5

SC2D2U6D3V3KX-GP

12

1 2

BLM15AG 221SS1D-GP

C2342

220R, 0.3A

L2308

+3.3V_AL W

5mA

65mA 46mA

+1.1V_AL W +3.3V_RU N

L2312

1.1V_ALW _VDDPL 3.3V_RUN _VDDPL

SC2D2U6D3V3KX-GP

L2312

1 2

C2349

BLM15AG 221SS1D-GP

12

4

1 2

SC2D2U6D3V3KX-GP

C2350

BLM15AG 221SS1D-GP

12

L2313

220R, 0.3A220R, 0.3A

12mA

10/1

Removed

3

+3.3V_AL W

SCD1U10V2KX-5GP

12

DY

2

C2345

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SB820M_POWER&GND_(4/5)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Berry AMD Discrete/UMA

23 95Thursday, March 04 , 2010

1

A00

5

SSID = S.B

4

3

2

1

REQUIRED STRAPS

D D

9/15

PCI_CLK1(2 0) PCI_CLK2(2 0) PCI_CLK3(2 0)

9/23

C C

PCLK_KB C(20 ,37)

PCLK_FW H(20,70)

LPCCLK1(20)

SB_GPO2 00(21 ) SB_GPO1 99(21 )

ACZ_SDA TAOUT_R(21)

+3.3V_RU N +3.3V_ ALW

R240410KR2J-3-GPDYR240410KR2J-3-GP

R240110KR2J-3-GPDYR240110KR2J-3-GP

R240310KR2J-3-GPDYR240310KR2J-3-GP

R240210KR2J-3-GPDYR240210KR2J-3-GP

R241610KR2J-3-GPDYR241610KR2J-3-GP

12

DY

12

R241710KR2J-3-GP R241710KR2J-3-GP

12

DY

12

R241810KR2J-3-GP R241810KR2J-3-GP

DY

12

R241910KR2J-3-GPDYR241910KR2J-3-GP

12

DY

12

DY

R240510KR2J-3-GPDYR240510KR2J-3-GP

12

R242010KR2J-3-GP R242010KR2J-3-GP

12

DY

9/15

R24082K2R2F-GP R24082K2R2F-GP

R24072K2R2F-GPDYR24072K2R2F-GP

R240610KR2J-3-GPDYR240610KR2J-3-GP

12

R242110KR2J-3-GP R242110KR2J-3-GP

12

DY

R240910KR2J-3-GPDYR240910KR2J-3-GP

12

DY

R24232K2R2F-GPDYR24232K2R2F-GP

R24222K2R2F-GP R24222K2R2F-GP

R242410KR2J-3-GP R242410KR2J-3-GP

12

DY

DEBUG STRAPS

PCI_AD23 (20)

PCI_AD25 (20) PCI_AD26 (20) PCI_AD27 (20)

1119-1 Removed

R24142K2R2J-2-GPDYR24142K2R2J-2-GP

R24132K2R2J-2-GPDYR24132K2R2J-2-GP

DY

R24122K2R2J-2-GPDYR24122K2R2J-2-GP

R24112K2R2J-2-GPDYR24112K2R2J-2-GP

12

DY

R24152K2R2J-2-GPDYR24152K2R2J-2-GP

12

DY

12

DY

9/22

VDDR_SE L (20,51)

B B

REQUIRED SYSTEM STRAPS

PCLK_KBC PCLK_FWH

(PCI_CLK4)(PCI_CLK3)

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

non_Fusion CLOCK mode

DEFAULT

Fusion CLOCK mode

PULL HIGH

PULL LOW

AZ_SDOUT#

LOW POWER MODE

PERFORMANCE MODE

DEFAULT

PCI_CLK1

Allow PCIE GEN2

DEFAULT

Force PCIE GEN1

PCI_CLK2

WatchDOG (NB_PWRGD) ENABLED

WatchDog (NB_PWRGD) DISABLED

DEFAULT

USE this pin to determine INT/EXT CLK

LPCCLK0

ENABLE EC

DISABLE EC

DEFAULT

LPCCLK1

CLKGEN ENABLED

(Use Internal)

DEFAULT

CLKGEN DISABLED

(Use External)

SB_GPO200 , SB_GPO199

ROM TYPE:

H, H = Reserved

H, L = SPI ROM

L, H = LPC ROM

L, L = FWH ROM

DEFAULT

PULL HIGH

PULL LOW

USE PCI PLL

BYPASS PCI PLL

PCI_AD26PCI_AD27

Disable ILA AUTORUN

Enable ILA AUTORUN

PCI_AD25 PCI_AD23

USE FC PLL

BYPASS FC PLL

PCI_AD24

USE DEFAULT PCIE STRAPS

USE EEPROM PCIE STRAPS

Disable PCI MEM BOOT

(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)

Enable PCI MEM BOOT

Note: SB820M has 15K internal PU FOR PCI_AD[27:23]

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

SB820M_STRAPPING_(5/5)

A3

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

24 95Friday, March 05, 201 0

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Reserved

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

2

Reserved

Berry AMD Discrete/UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 95Thursday, March 04, 2010

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

Date: Sheet of

Reserved

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

26 95Thursday, March 04 , 2010

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

27 95Thursday, March 04 , 2010

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

28 95Thursday, March 04 , 2010

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Berry AMD Discrete/UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

29 95Thursday, March 04 , 2010

A00

DELL RS880M, SB820M Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual