DELL PWA FP381, PWB DY483 Schematics

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PWA FP381, PWB DY483,

JM7-INTEGRATED

JM7 M/B PCBJM7 M/B PCB

A A

SCHEM UW474.
VER : 1A

POWER

AC/BATT
CONNECTOR

PG 54

DDR2-SODIMM1

B B

PG 15,16

DDR2-SODIMM2

PG 15,16

Internal Media Bay
CD-ROM

SMART CARD

OZ77CR6LN

PG 28

C C

AUDIO/AMP

PG 38,39

S/PDIF
for Dock

PG 43

D D

1

SYSTEM
RESET CIRCUIT

BATT
SELECTOR

BATT
CHARGER

RUN POWER SW

+3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V

PG 26

USB1.0

Audio
Jacks

PG 39

USER
INTERFACE

PG 36

533/667 MHZ DDR II

533/667 MHZ DDR II

IDE

SATA - HDD

PG 26

MDC

PG 30

RJ11
for Dock

PG 43

Keyboard
Controllor

Keyboard Touchpad/

PG 36

2

PG 44

PG 45

PG 46

PG 53

Tip
Ring

PG 30

PG 34

SATA

USB2.0 (P4)

IHDA

SPI

BCECE1077

FLASH

PG 34

Merom

(478 Micro-FCPGA)

Crestline

1299 uFCBGA
PG 5,6,7,8,9,10

DMI interface

ICH8-M

676 BGA

PG 11,12,13,14

SIO

MEC5025
128KB Flash
TMKBC

128 Pins VTQFP

PG 31

SPI PS/2

Stick point

PG 35

3

PG 3,4

(Symbol Rev.09)

667/800 MHz FSB

(Symbol Rev.09)

(Symbol Rev.09)

LPC

BC

128 Pins VTQFP

Serial Port

USB2.0 (P0,P1)
USB2.0 (P2,P3)
USB2.0 (P8)

USB2.0 (P5)
PCIEx1

SIO

ECE5018
Expander
USB 2.0 Hub(4)

PG 32

PG 33

4

33MHz PCI

PCIEx1
USB2.0 (P6)
PCIEx2
USB2.0 (P9)
USB2.0 (P7)

IrDA

PG 35

REGULATOR

+1.5V_RUN/+1.05V_VCCP

REGULATOR

+1.8V_SUS/+1.25V_RUN
/+0.9V_DDR_VTT

LVDS

SDVO

TVOUT
VGA

(EXT SIDE)
(EXT BACK)

Biometric

PG 35

BCM5755M
/BCM5752

DOCK LPC

FAN & THERMAL

EMC4001

PG 37

5

PG 48

PG 49

SI1362

PG 18

POWER USB & USB

PG 33

CARDBUS/1394

OZ711EZ1TN

MINI-CARD

WLAN
PG 29

Bluetooth

PG 40

6

POWER

CPU VR

DC/DC

+3.3V_ALW/+5V_ALW/+15V_ALW

Panel Connector

CRT CONN.

PG 25

PG 51

PG 52

Q-SWITCH

PG 42

PG 27

EXPRESS-CARD

R5538
PG 28

MINI-CARD

WWAN

PG 29

PG 35

E-Switch

PI3L500

+3.3V_LAN

PG 41

RJ45/Magnetics

Title

Title

Title

Schematic Block Diagram1

Schematic Block Diagram1

Schematic Block Diagram1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

JM7 1A

JM7 1A

JM7 1A

Date: Sheet

Date: Sheet

Date: Sheet

PG 24

PG 41

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

CLOCK

CK410M+LP

PG 17

DOCKING
CONNECTOR

PG 43

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157Monday, June 26, 2006

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8

INDEX Power States

Pg# Description

Schematic Block Diagram

1
2

Front Page

3-4

Merom

5-10

Crestline
ICH8M

A A

B B

C C

11-14

DDRII SO-DIMM(200P)

15-16

17

Clock Generator

18-23

VGA

24

LCD Conn. & SSP

25

CRT Conn

26

SATA & IDE Conn

27

PCCARD/Conn & 1394
Express Card & Smart Card

28
29

Mini Card
MDC Conn.

30
31

SIO (MEC5025)

32

SIO (MEC5018)

33

SERIAL PORT & USB

34

Flash ROM, RTC & ECE1077
TP,BT & FIR

35
36

Switch,Keyboard & LED
FAN & Thermal

37

Audio CODEC(STAC9205)/Phone Jack

38-39

LOM (Nineveh)/Switch

40-41
42-43

Docking Conn/Q-Switch
System Reset Circuit

44

Battery Selector & Charger

45-46

47

DDR2_1.8VSUS, 0.9V

48

1.5VSUS,1.05V(VTT)

49

VGA DC/DC,1.25V,1.05V
CPU_MAX8786(3phase)

50

D/D Power

51
52

RUN Power Switch

53

DCIN,Batt
PAD& SCREW

54
55

EMI CAP
SMBUS BLOCK

56

Power Rail S3/M1

+3.3V_ALW
+5V_ALW
+3.3V_LAN

+1.8V_SUS
+0.9V_DDR_VTT
+5V_SUS
+3.3V_SUS
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.25V_RUN
+1.5V_RUN
+1.05V_VCCP
VCC_VCRE
+LCDVCC
+5V_MOD

Control
Signal

S0/M0

S3/M1 S4/M1

S3/
M-off

S4/
M-off

S5/
M-off

D D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

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3

4

5

6

Date: Sheet

COMPUTER

Index & Power Status

Index & Power Status

Index & Power Status

JM7 1A

JM7 1A

JM7 1A

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257Monday, June 26, 2006

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7

8

H_A#[3..16]5

A A

H_ADSTB#05
H_REQ#[0..4]5

H_A#[17..35]5

B B

H_ADSTB#15

H_A20M#11

H_FERR#11

H_IGNNE#11
H_STPCLK#11

H_INTR11
H_NMI11
H_SMI#11

C C

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

U6A

U6A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

ADDR GROUP 0

ADDR GROUP 0

CONTROL

CONTROL

ADDR GROUP 1

ADDR GROUP 1

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

RESERVED

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_THERMDA H_THERMDC

R352 56R352 56

H_IERR#

1 2

H_RESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

R353 56R353 56

H_PROCHOT#
H_THERMDA
H_THERMDC

H_THERMTRIP#

H_THERMTRIP#

R360 56R360 56

1 2

C101

C101

2200P/50V_NC

2200P/50V_NC

12

1 2

H_ADS# 5
H_BNR# 5
H_BPRI# 5

H_DEFER# 5
H_DRDY# 5
H_DBSY# 5
H_BR0# 5

+1.05V_VCCP

H_INIT# 11
H_LOCK# 5

H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5

H_HIT# 5
H_HITM# 5

ITP_DBRESET# 13,31

+1.05V_VCCP

T44PAD T44PAD

H_THERMDA 37

H_THERMDC 37
H_THERMTRIP# 37

+1.05V_VCCP

CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17

+1.05V_VCCP

12

H_PROCHOT#

Layout Note:
Place R646
close to

R356

R356
51/F_NC

51/F_NC

CPU.

H_RESET# 5

Layout Note:
Place voltage
divider within

0.5" of GTLREF
pin

+1.05V_VCCP

R339

R339
1K/F

1K/F

1 2

R338

R338
2K/F

2K/F

1 2

+1.05V_VCCP

+3.3V_ALW

2

Q57

Q57

31

2N7002W-7-F_NC

2N7002W-7-F_NC

1 2

H_D#[0..63]5

H_DSTBN#05
H_DSTBP#05
H_DINV#05

H_D#[0..63]5

H_DSTBN#15
H_DSTBP#15
H_DINV#15

CPU_MCH_BSEL06,17
CPU_MCH_BSEL16,17
CPU_MCH_BSEL26,17

Voltage Level shift

R351

R351

2.2K_NC

2.2K_NC

CPU_PROCHOT# 31

Populate ITP700Flex for bringup

+1.05V_VCCP

Layout Note:

12

R751R7
51

R6 0R6 0

R8 22.6/FR8 22.6/F

ITP_TCK

ITP_TRST#

12

R3
39/FR339/F

1 2

1 2

12

R2
150R2150

JITP1

JITP1

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLKN

9

BCLKP

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

2

12

R9
51/FR951/F

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO
ITP_TRST#

H_RESET# ITP_DBRESET#

ITP_TCK

D D

Layout Note:
Place R8 close ITP.

CLK_CPU_ITP#17
CLK_CPU_ITP17

R5 27/FR5 27/F

12

R4 649/FR4 649/F

12

1

Place couple 0.1uF Decoupling
caps with in 0.1" ITP connector.

+1.05V_VCCP +3.3V_ALW

C3 0.1U/10VC3 0.1U/10V

27

VTT0
VTT1

VTAP

DBR#
DBA#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

NC0

NC1
GND_0
GND_1

ITP700Flex_NC

ITP700Flex_NC

28
26

25
24

23
21
19
17
15
13
4
6
29
30

C2 0.1U/10VC2 0.1U/10V

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

3

12

12

R10 150R10 150

Signal Resistor Value Connect To Resistor Placement

ITP700 layout guidelines

150 ohm ± 5%

TDI

39 ohm ± 1%

TMS

500 to 680

TRST#

12

ohm ± 5%

27 ohm ± 1%

TCK

TDO

51 ohm ± 5% Place the pull-up near ITP

22.6 ohm ± 1%
series resistor

RESET# VCCP

and pullup 51
ohm ± 1%.

4

VCCP
VCCP

GND

GND

VCCP

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

R358 1K/F_NCR358 1K/F_NC

1 2

R355 1K/F_NCR355 1K/F_NC

1 2

C401 0.1U/10V_NCC401 0.1U/10V_NC

12

R357 0_NCR357 0_NC

1 2

U6B

U6B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6

Y22

D[32]#

AB24

D[33]#

V24

D[34]#

V26

D[35]#

V23

D[36]#

T22

D[37]#

U25

D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

SLP#

PSI#

T7

PADT7PAD

T42

T42

PAD

PAD

BCLK

133
166
200

U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

MISC

MISC

PWRGOOD

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB
533 0 0
667
800

Place the pull-up near CPU
Within 200ps of ITP connector

Place the pull-down near CPU
Connect to TCK pin of CPU and then

connect it to FBO pin of ITP connector
in daisy chain. Place the pull-down
near TCK0 pin of ITP connector

Connect to CPURST# pin of GMCH through
the series resistor placed within
200ps of ITP connector. Place the
pull-up after the series resistor from
ITP connector.

5

6

Title

Title

Title

Merom Processor (HOST BUS)

Merom Processor (HOST BUS)

Merom Processor (HOST BUS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

JM7 1A

JM7 1A

JM7 1A

Date: Sheet

Date: Sheet

Date: Sheet

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

CPU_TEST3
CPU_TEST5

H_D#[0..63]

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_D#[0..63] 5

H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5

H_D#[0..63] 5

H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5

H_DPRSTP# 6,11,51
H_DPSLP# 11
H_DPWR# 5
H_PWRGOOD 11
H_CPUSLP# 5
H_PSI# 51

BSEL2 BSEL1 BSEL0

1

0

COMP0
COMP1
COMP2
COMP3

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

1

1

00

1

R344

R344

R343

R343

54.9/F

54.9/F

27.4/F

27.4/F

1 2

1 2

R350

R350

R347

R347

27.4/F

27.4/F

54.9/F

54.9/F

1 2

1 2

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357Wednesday, June 28, 2006

357Wednesday, June 28, 2006

357Wednesday, June 28, 2006

8

1

2

3

4

5

6

7

8

+VCC_CORE +VCC_CORE

+VCC_CORE

A A

+VCC_CORE

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

12

12

C415

C415
10U/4V

10U/4V

C405

C405
10U/4V

10U/4V

12

12

C73

C73
10U/4V

10U/4V

C406

C406
10U/4V

10U/4V

12

12

C72

C72
10U/4V

10U/4V

C69

C69
10U/4V

10U/4V

12

12

C71

C71
10U/4V

10U/4V

C68

C68
10U/4V

10U/4V

12

12

C70

C70
10U/4V

10U/4V

C425

C425
10U/4V

10U/4V

8 inside cavity, north side, secondary layer.

+VCC_CORE

12

B B

+VCC_CORE

12

C410

C410
10U/4V

10U/4V

C434

C434
10U/4V

10U/4V

12

12

C411

C411
10U/4V

10U/4V

C435

C435
10U/4V

10U/4V

12

12

C407

C407
10U/4V

10U/4V

C412

C412
10U/4V

10U/4V

12

12

C408

C408
10U/4V

10U/4V

C432

C432
10U/4V

10U/4V

12

12

C409

C409
10U/4V

10U/4V

C433

C433
10U/4V

10U/4V

8 inside cavity, south side, secondary layer.

+VCC_CORE

12

C419

C419
10U/4V

10U/4V

12

C429

C429
10U/4V

10U/4V

12

C439

C439
10U/4V

10U/4V

12

C438

C438
10U/4V

10U/4V

12

C437

C437
10U/4V

10U/4V

12

C436

C436
10U/4V

10U/4V

6 inside cavity, north side, primary layer.

+VCC_CORE

C C

12

C89

C89
10U/4V

10U/4V

12

C88

C88
10U/4V

10U/4V

12

C87

C87
10U/4V

10U/4V

12

C86

C86
10U/4V

10U/4V

12

C85

C85
10U/4V

10U/4V

12

C84

C84
10U/4V

10U/4V

6 inside cavity, south side, primary layer.

+1.05V_VCCP

12

Layout out:
Place these inside socket cavity on North side secondary.

D D

C416

C416

0.1U/10V

0.1U/10V

12

C426

C426

0.1U/10V

0.1U/10V

12

C417

C417

0.1U/10V

0.1U/10V

12

C427

C427

0.1U/10V

0.1U/10V

12

C418

C418

0.1U/10V

0.1U/10V

12

C428

C428

0.1U/10V

0.1U/10V

+PWR_SRC

12

C59

C59

+

+

100U/25V

100U/25V

Layout Note:
Need to add 100uF cap on PWR_SRC for cap singing.
Place on PWR_SRC near +VCC_CORE.

U6C

U6C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

12

+

+

C78

C78
100U/25V

100U/25V

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

.

12

C99

C99

+

+

100U/25V

100U/25V

VCCSENSE

VSSSENSE

+1.05V_VCCP

12

+

+

VID0 51
VID1 51
VID2 51
VID3 51
VID4 51
VID5 51
VID6 51

VCCSENSE 51

VSSSENSE 51

12

C113

C113

+

+

100U/25V_NC

100U/25V_NC

C430

C430
220U/4V

220U/4V

12

C443

C443

0.01U/25V

0.01U/25V

Layout Note:
Place C105 near PIN
B26.

+VCC_CORE

VCCSENSE
VSSSENSE

Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.

+1.5V_RUN

12

12

R336

R336
100/F

100/F

12

R334

R334
100/F

100/F

C446

C446
10U/4V

10U/4V

U6D

U6D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

COMPUTER

Merom Processor (POWER)

Merom Processor (POWER)

Merom Processor (POWER)

JM7 1A

JM7 1A

JM7 1A

7

of

of

of

457Wednesday, June 28, 2006

457Wednesday, June 28, 2006

457Wednesday, June 28, 2006

8

1

2

3

4

5

6

7

8

U9A

M10
N12

W10

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9
AE11
AH12

AH5

AE7

AE5

AH2
AH13

E2
G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7
Y9

P4
W3
N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U9A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

CRESTLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_D#[0..63]3

A A

+1.05V_VCCP

12

R374

R374
221/F

221/F

H_SWING

12

R373

R373
100/F

100/F

B B

+1.05V_VCCP

12

R413

R413

54.9/F

54.9/F

12

R372

R372

24.9/F

24.9/F

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil

C C

spacing.

12

R410

R410

54.9/F

54.9/F

1 2

H_SCOMP
H_SCOMP#

H_RCOMP

C454

C454

0.1U/10V

0.1U/10V

+1.05V_VCCP

R376

R376
1K/F

1K/F

1 2

12

R375

R375
2K/F

2K/F

H_D#[0..63]

H_RESET#3

H_CPUSLP#3

12

C457

C457

0.1U/10V

0.1U/10V

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_REF

H_A#[3..35]

H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3

H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3

H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3

H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3

H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3

H_RS#0 3
H_RS#1 3
H_RS#2 3

H_A#[3..35] 3

Layout Note:
Place the 0.1 uF

D D

1

2

decoupling capacitor
within 100 mils from
GMCH pins.

3

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

4

5

6

Date: Sheet

COMPUTER

Crestline (HOST)

Crestline (HOST)

Crestline (HOST)

JM7 1A

JM7 1A

JM7 1A

7

of

of

of

557Wednesday, June 28, 2006

557Wednesday, June 28, 2006

557Wednesday, June 28, 2006

8

1

+1.8V_SUS

12

R446

R446
1K/F

SM_RCOMP_VOH

12

A A

SM_RCOMP_VOL

12

Santa Rosa Platform MOW WW15
For 4Gb DRAM support,
change Pin-BJ29 to DDR_A_MA14,
change Pin-BE24 to DDR_B_MA14.

+3.3V_RUN

B B

+1.05V_VCCP

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

C C

+3.3V_RUN

THERMTRIP_MCH#37

D D

12

C539

C539

0.01U/25V

0.01U/25V

C542

C542

0.01U/25V

0.01U/25V

R402 10KR402 10K
R395 10KR395 10K

CPU_MCH_BSEL03,17
CPU_MCH_BSEL13,17
CPU_MCH_BSEL23,17

C538

C538

2.2U/6.3V

2.2U/6.3V

12

C546

C546

2.2U/6.3V

2.2U/6.3V

DDR_A_MA1415,16
DDR_B_MA1415,16

1 2
1 2

R406 56_NCR406 56_NC

1 2

PAD

PAD
PAD

PAD

R391 4.02K/F_NCR391 4.02K/F_NC

PAD

PAD
PAD

PAD
PAD

PAD

R382 4.02K/F_NCR382 4.02K/F_NC

PAD

PAD
PAD

PAD
PAD

PAD
PAD

PAD
PAD

PAD
PAD

PAD

R405 4.02K/F_NCR405 4.02K/F_NC

PAD

PAD
PAD

PAD

R403 4.02K/F_NCR403 4.02K/F_NC
R394 4.02K/F_NCR394 4.02K/F_NC

PM_BMBUSY#13

H_DPRSTP#3,11,51
PM_EXTTS#015
PM_EXTTS#115
ICH_PWRGD13,44

DPRSLPVR13,51

SB_NB_PCIE_RST#12

PLTRST#12,18,28,29,31,32,40

1

1K/F

12

R447

R447

3.01K/F

3.01K/F

12

R444

R444
1K/F

1K/F

PM_EXTTS#0
PM_EXTTS#1

THERMTRIP_MCH#

T45

T45
T12

T12

12

T56

T56
T49

T49
T46

T46

12

T58

T58
T48

T48
T52

T52
T50

T50
T47

T47
T54

T54

12

T57

T57
T55

T55

12
12

PM_EXTTS#0
PM_EXTTS#1

PLTRST#_R
THERMTRIP_MCH#

1 2

R389 0R389 0

R419 0_NCR419 0_NC

1 2

R422 0R422 0

1 2

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

P36
P37
R35

N35
AR12
AR13

AM12

AN13

J12

AR37

AM36

AL36

AM37

D20

H10

B51

BJ20
BK22
BF19
BH20
BK18

BJ18
BF23
BG23
BC23
BD24

BJ29
BE24
BH39

AW20

BK20

C48
D47
B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23
F23
N23
G23

J20
C20
R24

L23

J23
E23
E20
K23
M20
M24

L32
N33

L35

G41

L39

L36

J36

AW49

AV20

N20
G36

BJ51
BK51
BK50
BL50
BL49

BL3
BL2
BK1
BJ1

E1

A5
C51
B50
A50
A49
BK2

CRESTLINE_1p0

CRESTLINE_1p0

R421 100R421 100

2

U9B

U9B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

PLTRST#_R

12

2

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

CFGRSVD

CFGRSVD

PM

PM

GRAPHICS VIDME

GRAPHICS VIDME

NC

NC

MISC

MISC

3

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

3

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR3 15
M_CLK_DDR4 15

M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#3 15
M_CLK_DDR#4 15

DDR_CKE0_DIMMA 15,16
DDR_CKE1_DIMMA 15,16
DDR_CKE3_DIMMB 15,16
DDR_CKE4_DIMMB 15,16

DDR_CS0_DIMMA# 15,16
DDR_CS1_DIMMA# 15,16
DDR_CS2_DIMMB# 15,16
DDR_CS3_DIMMB# 15,16

M_ODT0 15,16
M_ODT1 15,16
M_ODT2 15,16
M_ODT3 15,16

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

V_DDR_MCH_REF

T51

T51
T11

T11
T10

T10
T8
T9

MCH_CLVREF

SDVO_CTRLCLK 18

SDVO_CTRLDATA 18
CLK_3GPLLREQ# 17
MCH_ICH_SYNC# 13

R407

R407
20K

20K

1 2

1 2

4

MCH_DREFCLK 17
MCH_DREFCLK# 17
DREF_SSCLK 17
DREF_SSCLK# 17

CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17

DMI_MRX_ITX_N0 12
DMI_MRX_ITX_N1 12
DMI_MRX_ITX_N2 12
DMI_MRX_ITX_N3 12

DMI_MRX_ITX_P0 12
DMI_MRX_ITX_P1 12
DMI_MRX_ITX_P2 12
DMI_MRX_ITX_P3 12

DMI_MTX_IRX_N0 12
DMI_MTX_IRX_N1 12
DMI_MTX_IRX_N2 12
DMI_MTX_IRX_N3 12

DMI_MTX_IRX_P0 12
DMI_MTX_IRX_P1 12
DMI_MTX_IRX_P2 12
DMI_MTX_IRX_P3 12

Non-iAMT

MCH_CLVREF

PAD

PAD
PAD

PAD
PAD

PAD
PADT8PAD
PADT9PAD

CL_CLK0 13
CL_DATA0 13
ICH_CL_PWROK 13,31

ICH_CL_RST0# 13

R3780R378
0

C508

C508

0.1U/10V

0.1U/10V

1 2

4

5

BIA_PWM24
PANEL_BKEN32

SMRCOMPP
SMRCOMPN

TV_CVBS43

+1.25V_RUN

12

12

1 2

R416

R416
1K/F

1K/F

R418

R418
392/F

392/F

L_IBG

R401

R401

2.4K

2.4K

UMA

TV_Y43
TV_C43

CFG5

CFG9

CFG16

CFG19

CFG20

+1.8V_SUS

R437

R437
20/F

20/F

R443

R443
20/F

20/F

G_CLK_DDC225
G_DAT_DDC225

12

12

R387

R387
150/F

150/F

1 2

VGA_BLU25,43
VGA_GRN25,43
VGA_RED25,43

VGAHSYNC25
VGAVSYNC25

+3.3V_RUN

DMI X2 Select
PCI Express

Graphic Lane
FSB Dynamic

ODT
DMI Lane

Reversal

SDVO/PCIE
Concurrent
Operation

LCD_DDCCLK24
LCD_DDCDAT24
ENVDD24

LCD_ACLK-24
LCD_ACLK+24
LCD_BCLK-24
LCD_BCLK+24

LCD_A0-24
LCD_A1-24
LCD_A2-24

LCD_A0+24
LCD_A1+24
LCD_A2+24

LCD_B0-24
LCD_B1-24
LCD_B2-24

LCD_B0+24
LCD_B1+24
LCD_B2+24

SDVO_CRTL_DATA SDVO Present.

5

LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDAT

T53PAD T53PAD

R381

R381
150/F

150/F

1 2

R365 10KR365 10K
R366 10KR366 10K
R364 2.2KR364 2.2K
R363 2.2KR363 2.2K

L_IBG

R398

R398
150/F

150/F

1 2

VGA_BLU
VGA_GRN
VGA_RED

R390 30/FR390 30/F

1 2

R379 1.3K/FR379 1.3K/F

1 2

R384 30/FR384 30/F

1 2

1 2
1 2

12
12

Low=DMIx2
High=DMIx4(Default)

Low= Reveise Lane
High=Normal operation

Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).

Low=Normal(default).
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port

Low=No SDVO Device Present
(default)
High=SDVO Device Present

M35

LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDAT

6

U9C

U9C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN
TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0

CRESTLINE_1p0

6

UMA

7

VCC3G_PCIE_R

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

LVDS

LVDS

TV VGA

TV VGA

1 2

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9

PEG_TX#_10
PEG_TX#_11

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

R396

R396

R400

R400

150/F

150/F

150/F

150/F

1 2

DVO_RED#_C
DVO_GREEN#_C
DVO_BLUE#_C
DVO_CLK#_C

DVO_RED_C
DVO_GREEN_C
DVO_BLUE_C
DVO_CLK_C

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50

PEG_RX_0

L50

PEG_RX_1

M47

PEG_RX_2

U44

PEG_RX_3

T49

PEG_RX_4

T41

PEG_RX_5

W45

PEG_RX_6

W41

PEG_RX_7

AB50

PEG_RX_8

Y48

PEG_RX_9

AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45

PEG_TX_0

T38

PEG_TX_1

T46

PEG_TX_2

N50

PEG_TX_3

R51

PEG_TX_4

U43

PEG_TX_5

W42

PEG_TX_6

Y47

PEG_TX_7

Y39

PEG_TX_8

AC38

PEG_TX_9

AD47
AC50
AD43
AG39
AE50
AH43

VGA_BLU
VGA_GRN
VGA_RED

R393

R393

Layout Note:

150/F

150/F

Place 150 ohm
termination resistors

1 2

close to GMCH.

C475 0.1U/10VC475 0.1U/10V

1 2

C489 0.1U/10VC489 0.1U/10V

1 2

C483 0.1U/10VC483 0.1U/10V

1 2

C471 0.1U/10VC471 0.1U/10V

1 2

C473 0.1U/10VC473 0.1U/10V

1 2

C486 0.1U/10VC486 0.1U/10V

1 2

C480 0.1U/10VC480 0.1U/10V

1 2

C469 0.1U/10VC469 0.1U/10V

1 2

DVO_RED#_C
DVO_GREEN#_C
DVO_BLUE#_C
DVO_CLK#_C

DVO_RED_C
DVO_GREEN_C
DVO_BLUE_C
DVO_CLK_C

8

+VCC_PEG

R397 24.9/FR397 24.9/F

1 2

SDVOB_INT- 18

SDVOB_INT+ 18

UMA

SDVOB_RED- 18
SDVOB_GREEN- 18
SDVOB_BLUE- 18
SDVOB_CLK- 18

SDVOB_RED+ 18
SDVOB_GREEN+ 18
SDVOB_BLUE+ 18
SDVOB_CLK+ 18

DC Blocked Cap.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

Crestline (VGA,DMI)

Crestline (VGA,DMI)

Crestline (VGA,DMI)

JM7 1A

JM7 1A

JM7 1A

7

of

of

of

657Wednesday, June 28, 2006

657Wednesday, June 28, 2006

657Wednesday, June 28, 2006

8

1

2

3

4

5

6

7

8

DDR_A_D[0..63]15

A A

B B

C C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8

AN10

AN9
AM9

AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9

U9D

U9D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

DDR_A_BS0

BB19

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

DDR_A_WE#

DDR_A_BS0 15,16
DDR_A_BS1 15,16
DDR_A_BS2 15,16

DDR_A_CAS# 15,16
DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..13] 15,16

DDR_A_RAS# 15,16

T59 PADT59 PAD

DDR_A_WE# 15,16

DDR_B_D[0..63]15

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44

BJ43
BL43
BK47
BK49
BK43
BK42

BJ41
BL41

BJ37

BJ36
BK41

BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BL9
BK5
BL5
BK9

BJ8
BJ6

BF4
BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

U9E

U9E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1

SB_BS_2
SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

DDR_B_WE#

DDR_B_BS0 15,16
DDR_B_BS1 15,16
DDR_B_BS2 15,16

DDR_B_CAS# 15,16
DDR_B_DM[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_MA[0..13] 15,16

DDR_B_RAS# 15,16

T60 PADT60 PAD

DDR_B_WE# 15,16

D D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

COMPUTER

Crestline (DDR2)

Crestline (DDR2)

Crestline (DDR2)

JM7 1A

JM7 1A

JM7 1A

7

of

of

of

757Wednesday, June 28, 2006

757Wednesday, June 28, 2006

757Wednesday, June 28, 2006

8

5

+1.05V_VCCP

D D

+1.8V_SUS

C C

+1.05V_VCCP

B B

A A

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

5

U9G

U9G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRESTLINE_1p0

CRESTLINE_1p0

VCC CORE

VCC CORE

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

4

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

4

+1.05V_VCCP

Layout Note:
370 mils from edge.

Layout Note:
370 mils from edge.

C512

C512

0.1U/10V

0.1U/10V

+

+

12

C488

C488

0.1U/10V

0.1U/10V

12

C126

C126
220U/2.5V

220U/2.5V

12

C509

C509

0.1U/10V

0.1U/10V

12

+

+

C118

C118
220U/2.5V

220U/2.5V

Layout Note:
Inside GMCH cavity for VCC_AXG.

12

C482

C482

0.1U/10V

0.1U/10V

12

12

C466

C466

0.47U/10V

0.47U/10V

+

+

12

C530

C530

0.22U/10V

0.22U/10V

12

C133

C133
220U/2.5V_NC

220U/2.5V_NC

12

C494

C494
1U/10V

1U/10V

12

12

+

+

+

+

C532

C532

0.22U/10V

0.22U/10V

3

C447

C447
220U/2.5V

220U/2.5V

12

C144

C144
220U/2.5V_NC

220U/2.5V_NC

+1.05V_VCCP

12

C470

C470
10U/6.3V

10U/6.3V

+1.05V_VCCP

Non-iAMT

12

C529

C529

0.47U/10V

0.47U/10V

3

+1.05V_VCCP

+3.3V_RUN

R368 10R368 10

1 2

12

Layout Note:
Inside GMCH cavity.

12

12

C441

C441
22U/10V

22U/10V

C492

C492
22U/4V

22U/4V

C490

C490

0.22U/10V

0.22U/10V

12

C499

C499

0.1U/10V

0.1U/10V

12

C182

C182
22U/4V

22U/4V

Layout Note:
Place close to GMCH edge.

12

12

C528

C528

C519

C519

1U/10V

1U/10V

1U/10V

1U/10V

D28

+VCC_GMCH_L

12

C487

C487

0.22U/10V

0.22U/10V

Layout Note:
Inside GMCH cavity.

12

12

D28

CH751H-40HPT

CH751H-40HPT

12

C497

C497

0.1U/10V

0.1U/10V

12

C506

C503

C503

0.1U/10V

0.1U/10V

C511

C511

0.22U/10V

0.22U/10V

C506

0.1U/10V

0.1U/10V

12

C510

C510

0.22U/10V

0.22U/10V

+1.8V_SUS

12

Layout Note:
Place C901 where LVDS
and DDR2 taps.

C230

C230

0.1U/10V

0.1U/10V

2

U9F

U9F

21

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37

U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

T30
T34
T35

CRESTLINE_1p0

CRESTLINE_1p0

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

VCC NCTF

VCC NCTF

POWER

POWER

VCC AXM NCTF

VCC AXM NCTF

1

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

VSS NCTF

VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+1.05V_VCCP

VCC_SM

12

+

+

C202

C202
330U/6.3V

330U/6.3V

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

12

12

C544

C544

C545

C545

22U/4V

22U/4V

22U/4V

22U/4V

Layout Note:
Place on the edge.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

Crestline (VCC,NCTF)

Crestline (VCC,NCTF)

Crestline (VCC,NCTF)

JM7 1A

JM7 1A

JM7 1A

1

of

of

of

857Wednesday, June 28, 2006

857Wednesday, June 28, 2006

857Wednesday, June 28, 2006

5

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

12

PJP30PJP30

C107

C107

0.1U/10V

0.1U/10V

L48

L48
10uH/100MA

10uH/100MA

L30

L30
10uH/100MA

10uH/100MA

R87 0R87 0

1 2

3

2

40mA MAx.

10uH+-20%_100mA

12

12

PJP29PJP29

1 2

12

C175

C175

+

+

100U/6.3V

100U/6.3V

12

C533

C533
22U/4V

22U/4V

+1.25V_RUN

12

C180

C180

0.1U/10V

0.1U/10V

L29

L29

+3.3V_RUN

D D

Non-iAMT

+1.25V_RUN

L50

L50
BLM11A121S

BLM11A121S

L51

L51
BLM11A121S

BLM11A121S
R420

R420

0.5/F/0603

0.5/F/0603

1 2

+VCCA_MPLL_L

12

C167

C167
22U/10V

22U/10V

C C

1 2

BLM18PG181SN1

BLM18PG181SN1

45mA MAx.

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

+VCCA_HPLL

12

12

C161

C161
22U/10V

22U/10V

+VCCA_MPLL

12

12

C498

C498

0.1U/10V

0.1U/10V

12

C507

C507

0.1U/10V

0.1U/10V

+VCCA_CRTDAC

+1.25V_RUN

+1.25V_RUN

0.1Caps should be
placed 200 mils
with in its pins.

Non-iAMT

+1.25V_RUN

+1.25V_RUN

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

B B

L49

L49

1 2

BLM21PG221SN1D

BLM21PG221SN1D

+VCCA_PEG_PLL

12

R417

R417
1/F/0603

1/F/0603

12

C496

C496
10U/6.3V

10U/6.3V

1 2

12

C485

C485

0.1U/10V

0.1U/10V

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

L28

L28

+3.3V_RUN

22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.

+VCC_TVBG_R +VCC_TVBG

A A

+1.5V_RUN

TV DAC Voltage Follower Circuit -700 mV.

R86 0R86 0

3

D8

D8

2 1

CH751H-40HPT_NC

CH751H-40HPT_NC

1 2

BLM18PG181SN1

BLM18PG181SN1

12

1

C111

C111

2

22nF/3P_NC

22nF/3P_NC

+VCC_TVDAC_L

5

12

C106

C106

0.1U/10V

0.1U/10V

R78 10_NCR78 10_NC

1 2

12

R79 0.03/FR79 0.03/F

+3.3V_RUN

+VCC_TVDACA +VCC_TVDACA_R

12

C103

C102

C102
10U/6.3V

10U/6.3V

12

C103

0.1U/10V

0.1U/10V

+VCC_TVDACB

12

C104

C104

0.1U/10V

0.1U/10V

12

C105

C105

0.1U/10V

0.1U/10V

+VCCA_CRTDAC_R

1

C112

C112
22nF/3P_NC

22nF/3P_NC

+VCCA_DPLLA

12

C464

C464

+

+

470U/4V

470U/4V

+VCCA_DPLLB

12

C128

C128

+

+

470U/4V

470U/4V

C505

C505

4.7U/6.3V

4.7U/6.3V

1 2

12

C520

C520
1U/10V

1U/10V

Non-iAMT

12

C484

C484

0.1U/10V

0.1U/10V

R83 0R83 0

1 2
123

R84 0R84 0

1 2
123

R85 0R85 0

1 2
123

4

12

C459

C459

0.1U/10V

0.1U/10V

12

C130

C130

0.1U/10V

0.1U/10V

12

12

Place PJP54 for
+1.8V_SUS

+1.8V_SUS

+1.8V_RUN

C108

C108
22nF/3P_NC

22nF/3P_NC

+VCC_TVDACB_R

C109

C109
22nF/3P_NC

22nF/3P_NC

+VCC_TVDACC_R+VCC_TVDACC

C110

C110
22nF/3P_NC

22nF/3P_NC

4

+3.3V_RUN

C518

C518
22U/4V

22U/4V

C523

C523
1U/10V

1U/10V

12

C690

C690

0.1U/10V

0.1U/10V

+3.3V_RUN

12

1 2

1 2

C115

C115
1000P/50V

1000P/50V

C468

C468

0.1U/10V

0.1U/10V

12

C526

C526
22U/4V

22U/4V

12

C535

C535

0.1U/10V

0.1U/10V

PJP9PJP9

PJP11PJP11

+VCCA_CRTDAC_R

+VCC_TVBG_R

+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL

+VCC_TX_LVDS

12

+VCCA_PEG_PLL

+VCCA_SM

12

C504

C504
1U/10V

1U/10V

+VCCA_SM_CK
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R

+VCCD_TVDAC_R

+VCCQ_TVDAC_R

+VCCA_PEG_PLL
+VCCD_LVDS

12

C137

C137
1U/10V

1U/10V

+1.5V_RUN

L47

L47

1 2

BLM18PG181SN1

BLM18PG181SN1

FB_180ohm+-25%_
100mHz_1500mA_

0.09ohm DC

J32

A33
B33

A30
B32

B49

H49

AL2

AM2

A41
B41

K50
K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25

B25

C27

B27
B28
A28

M32

L29
N28
AN2
U48

J41

H42

12

C138

C138
10U/6.3V_NC

10U/6.3V_NC

+VCCQ_TVDAC

3

U9H

U9H

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

+VTTLF1
+VTTLF2
+VTTLF3

12

C444

C444

0.1U/10V

0.1U/10V

12

C448

C448

0.1U/10V

0.1U/10V

3

POWER

POWER

D TV/CRTLVDS

D TV/CRTLVDS

12

C495

C495

0.47U/10V

0.47U/10V

R354 0R354 0

1 2
123

C442

C442
22nF/3P_NC

22nF/3P_NC

R359 0R359 0

1 2
123

C449

C449
22nF/3P_NC

22nF/3P_NC

CRTPLLA PEGA SMTV

CRTPLLA PEGA SMTV

A CK A LVDS

A CK A LVDS

12

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

AXD

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

DMI

CRESTLINE_1p0

CRESTLINE_1p0

C456

C456

0.47U/10V

0.47U/10V

+VCCD_TVDAC_R

+VCCQ_TVDAC_R

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14

VTT

VTT

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

12

C455

C455

0.47U/10V

0.47U/10V

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

2

+1.05V_VCCP

C477

C477

2.2U/6.3V

2.2U/6.3V

12

C474

C474

4.7U/6.3V

4.7U/6.3V

12

Place on the edge.

12

C476

C476

0.47U/6.3V

0.47U/6.3V

12

C479

C479

4.7U/6.3V

4.7U/6.3V

Place on the edge.

+VCC_AXD_L +VCC_AXD_R

12

C517

C517
1U/10V

1U/10V

+1.25V_RUN

+VCC_SM_CK

+VCC_TX_LVDS

+3.3V_RUN

12

C460

C460

0.1U/10V

0.1U/10V

+VCC_RXR_DMI

+VTTLF1
+VTTLF2
+VTTLF3

2

1 2

12

C198

C198
22U/10V

22U/10V

Place caps close
to VCC_AXD.

12

C116

C116
1000P/50V

1000P/50V

+VCC_PEG

12

+

+

C146

C146
220U/4V

220U/4V

12

+

+

C166

C166
220U/4V

220U/4V

+VCC_SM_CK

12

C199

C199
22U/10V

22U/10V

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

VCC_HV

D27

D27
CH751H-40HPT_NC

CH751H-40HPT_NC

+1.05V_VCCP

12

+

+

C154

C154
220U/4V

220U/4V

L54 0L54 0

Reserved L81 pad for
inductor.

+1.25V_RUN

12

C502

C502

0.1U/10V

0.1U/10V

R102 0/1206R102 0/1206

1 2

12

For EMI

+

+

fine tune.

C121

C121
220U/4V

220U/4V

12

C147

C147
10U/6.3V

10U/6.3V

12

C156

C156
10U/6.3V

10U/6.3V

12

C534

C534

0.1U/10V

0.1U/10V

Crestline (POWER)

Crestline (POWER)

Crestline (POWER)

JM7 1A

JM7 1A

JM7 1A

Non­iAMT

+1.25V_RUN

PJP31PJP31

12

Place PJP62 for
+1.8V_SUS

+VCC_TX_LVDS_R

R127 0/1206R127 0/1206

1 2

For EMI
fine tune.

R134 0/1206R134 0/1206

1 2

For EMI
fine tune.

R449 0/1206R449 0/1206

12

R436

R436
1/F/0603

1/F/0603

+VCC_SM_CK_L

12

C540

C540
10U/6.3V

10U/6.3V

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

1 2

For EMI
fine tune.

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+3.3V_RUN

+1.25V_RUN

12

C451

C451
1U/10V

1U/10V

Place caps close
to VCC_AXF

PJP8PJP8

PJP10PJP10

957Wednesday, June 28, 2006

957Wednesday, June 28, 2006

957Wednesday, June 28, 2006

1

21

+VCC_HV_L

12

R367

R367
10_NC

10_NC

12

C453

C453
10U/6.3V

10U/6.3V

+1.8V_SUS

12

+1.8V_RUN

12

+1.8V_SUS

of

of

of

5

U9I

U9I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

D D

C C

B B

A A

5

AB20
AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

AL1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

CRESTLINE_1p0

VSS

VSS

4

4

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U9J

U9J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

CRESTLINE_1p0

3

VSS

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

2

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

COMPUTER

Crestline (VSS)

Crestline (VSS)

Crestline (VSS)

JM7 1A

JM7 1A

JM7 1A

1

of

of

of

10 57Wednesday, June 28, 2006

10 57Wednesday, June 28, 2006

10 57Wednesday, June 28, 2006

1

1

2

3

4

5

6

7

8

+RTC_CELL +RTC_CELL

12

R520

R520
332K/F

332K/F

ICH_INTVRMEN ICH_LAN100_SLP

12

R522

R522
0_NC

0_NC

ICH8M LAN100 SLP Strap

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

U18A

U18A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

ICH8M REV 1.0

R563

R563
1K_NC

1K_NC

1 2

1 2

R542

R542
1K_NC

1K_NC

ACZ_SDOUT

ICH_RSVD 13

RTC

RTC

CPUPWRGD/GPIO49

LAN / GLAN

LAN / GLAN

IHDA

IHDA

SATA

SATA

5

(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LPC

LPC

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#

INTR

CPU

CPU

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

IDE

IDE

DA0

DA1

DA2

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

12

R550

R550
332K/F

332K/F

12

R539

R539
0_NC

0_NC

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

LPC_LAD0 31,32,40
LPC_LAD1 31,32,40
LPC_LAD2 31,32,40
LPC_LAD3 31,32,40

LPC_LFRAME# 31,32,40

LPC_LDRQ0# 32

IDE_DD[0..15]

LPC_LDRQ1# 32
SIO_A20GATE 31

H_A20M# 3
H_DPRSTP# 3,6,51

H_DPSLP# 3

H_INIT# 3
H_INTR 3

SIO_RCIN# 31

H_NMI 3
H_SMI# 3

H_STPCLK# 3

IDE_DA0 26
IDE_DA1 26
IDE_DA2 26

IDE_DCS1# 26
IDE_DCS3# 26

IDE_DIOR# 26
IDE_DIOW# 26
IDE_DDACK# 26
IDE_IRQ 26
IDE_DIORDY 26
IDE_DDREQ 26

SIO_A20GATE

H_DPRSTP#
H_DPSLP#

H_FERR#

SIO_RCIN#

THERMTRIP#_ICH

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8

IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

6

+1.05V_VCCP

R519

R519

R518

R518

56_NC

56_NC

56_NC

56_NC

1 2

H_DPRSTP#
H_DPSLP#
H_FERR#

H_FERR# 3
H_PWRGOOD 3
H_IGNNE# 3

T88PAD T88PAD

IDE_DD[0..15] 26

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN)

ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN)

ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN)

JM7 1A

JM7 1A

JM7 1A

7

SIO_A20GATE
SIO_RCIN#

THERMTRIP#_ICH

1 2

R566

R566
10K

10K

1 2

+1.05V_VCCP

11 57Wednesday, June 28, 2006

11 57Wednesday, June 28, 2006

11 57Wednesday, June 28, 2006

8

+3.3V_RUN

of

of

of

R52856R528
56

1 2

R558

R558
10K

10K

1 2

R51756R517
56

1 2

C646

C646
27P/50V_NC

27P/50V_NC

R515 10MR515 10M

W2

W2

1 4
2 3

32.768KHZ

32.768KHZ

R527

R527
20K

20K

1 2

ICH_RTCRST#
ICH_INTRUDER#

12

C638

C638
1U/10V

1U/10V

12

R514 0R514 0

1 2

ACZ_BIT_CLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

Place within 500mils
of ICH8 ball

XOR Chain Entrance Strap

ICH RSVD

HDA SDOUT

0
0
1
1

ICH_RTCX2ICH_RTCX1

12

Reserved for
Intel Nineveh
design.

+1.5V_PCIE_ICH

ICH_AZ_CODEC_SDIN038
ICH_AZ_MDC_SDIN130

SATA_RX0-26
SATA_RX0+26

CLK_PCIE_SATA#17
CLK_PCIE_SATA17

Description

0

RSVD
Enter XOR Chain

1

Normal Operation (Default)

0

Set PCIE port config bit 1

1

3

C625

C625
15P/50V

15P/50V

T25 PADT25 PAD

T30 PADT30 PAD
T28 PADT28 PAD
T89 PADT89 PAD
T90 PADT90 PAD
T92 PADT92 PAD
T98 PADT98 PAD

T29 PADT29 PAD

R521 24.9/FR521 24.9/F

1 2

T31 PADT31 PAD
T111PADT111PAD

R585 24.9/FR585 24.9/F

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
ICH_INTRUDER#
ICH_INTVRMEN

ICH_LAN100_SLP
GLAN_CLK

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

GLAN_COMP
ACZ_BIT_CLK

ACZ_SYNC
ACZ_RST#

ACZ_SDOUT

SATA_ACT#_R

SATA_TX0-_C
SATA_TX0+_C

SATABIAS

12

+3.3V_RUN

4

32.768KHZ

12

C618

C649

C649
27P/50V_NC

27P/50V_NC

+3.3V_RUN

12

C618
15P/50V

15P/50V

+RTC_CELL

12

R5341MR534
1M

R551 33R551 33

1 2

R552 33R552 33

1 2

1 2

R547 33R547 33

1 2

R546 33R546 33

1 2

R556 33R556 33

1 2

R555 33R555 33

1 2

R562 33R562 33

1 2

R557 33R557 33

1 2

SATA_TX0-_C
SATA_TX0+_C

R571

R571
10K

10K

SATA_ACT#_R

2

A A

B B

ICH_AZ_MDC_BITCLK30
ICH_AZ_CODEC_BITCLK38

1 2

ICH_AZ_MDC_SYNC30
ICH_AZ_CODEC_SYNC38
ICH_AZ_MDC_RST#30
ICH_AZ_CODEC_RST#38
ICH_AZ_MDC_SDOUT30
ICH_AZ_CODEC_SDOUT38

Place all series terms close to ICH8 except for SDIN input
lines,which should be close to source.Placement of R292, R286,

C C

R283 & R289 should equal distance to the T split trace point as
R291, R285, R284 & R290 respective. Basically,keep the same
distance from T for all series termination resistors.

SATA_TX0-26
SATA_TX0+26

Distance between the ICH-8 M and cap on the "P"
signal should be identical distance between the
ICH-6 M and cap on the "N" signal for same pair.

This circuit is
only needed if the
platform has the
SNIFFER.

LED_MASK#32,35

D D

SATA_ACT#36

C668 3900P/25VC668 3900P/25V
C667 3900P/25VC667 3900P/25V

1

2

3 1

Q68

Q68
2N7002W-7-F

2N7002W-7-F
R575 0_NCR575 0_NC

1 2

12
12

1

Place TX DC blocking caps close ICH8.

PCIE_TX1-29
PCIE_TX1+29

PCIE_TX2-29
PCIE_TX2+29

A A

B B

C C

D D

PCIE_TX4-28
PCIE_TX4+28

PCIE_TX6-/GLAN_TX-40
PCIE_TX6+/GLAN_TX+40

Layout Note:
Place R288,R324 and R282
within 500 mils from ICH.

R523 15_NCR523 15_NC

SPI_CS0#34

PCI_AD[0..31]27,42

1 2

R262 0R262 0

1 2

PCI_PIRQA#42

T107 PADT107 PAD
T109 PADT109 PAD

PCI_PIRQD#27

1

C621 0.1U/10VC621 0.1U/10V
C622 0.1U/10VC622 0.1U/10V

C620 0.1U/10VC620 0.1U/10V
C619 0.1U/10VC619 0.1U/10V

C623 0.1U/10VC623 0.1U/10V
C624 0.1U/10VC624 0.1U/10V

C626 0.1U/10VC626 0.1U/10V
C627 0.1U/10VC627 0.1U/10V

U17

U17

4

7SH08_NC

7SH08_NC

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+3.3V_ALW

5

2
1

2

ICH_EC_SPI_CLK31

ICH_EC_SPI_DO31

ICH_EC_SPI_DIN31

R52615R526
15

1 2

SIO_SPI_CS# 31

U18B

U18B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

ICH8M REV 1.0

2

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

ICH_SPI_CS#

Non-iAMT

OC6#
OC4#
OC5#
OC7#

+3.3V_SUS

PCI

PCI

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCIE_RX1-29
PCIE_RX1+29

MiniWWAN

PCIE_RX2-29
PCIE_RX2+29

MiniWLAN

PCIE_RX4-28
PCIE_RX4+28

Express Card

PCIE_RX6-/GLAN_RX-40
PCIE_RX6+/GLAN_RX+40

Giga Bit LOM

R530 15R530 15

1 2

R531 15R531 15

1 2

USB_OC0_1#33
USB_OC2_3#33

RP48

RP48

6
7
8
9

10

10P8R-10K

10P8R-10K

A4

REQ0#

D7

GNT0#

E18
C18
B19
F18
A11
C10

C17

C/BE0#

E15

C/BE1#

F16

C/BE2#

E17

C/BE3#

C8

IRDY#

D9

PAR

G6

PCIRST#

D16

DEVSEL#

A7

PERR#

B7

PLOCK#

F10

SERR#

C16

STOP#

C9

TRDY#

A17

FRAME#

AG24

PLTRST#

B10

PCICLK

G7

PME#

F8
G11
F12
B3

3

ICH_EC_SPI_CLK_R
ICH_SPI_CS#
ICH_SPI_CS1#_R

ICH_EC_SPI_DO_R

USB_OC0_1#
USB_OC2_3#
OC4#

OC5#
OC6#
OC7#
OC8#
OC9#

+3.3V_SUS

5
4
3
2
1

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#
SB_NB_PCIE_RST#

PCI_IRDY#
PCI_RST#_G

PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

3

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

OC8#
USB_OC2_3#
USB_OC0_1#
OC9#

4

U18D

U18D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

ICH8M REV 1.0

ICH8M REV 1.0

Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

ICH_SPI_CS1#_R
PCI_GNT0#

PCI_REQ0# 43
PCI_GNT0# 42
PCI_REQ1# 27
PCI_GNT1# 27
SB_WWAN_PCIE_RST# 29
SB_WLAN_PCIE_RST# 29
SB_LOM_PCIE_RST# 40
SB_NB_PCIE_RST# 6

PCI_C_BE0# 27,42
PCI_C_BE1# 27,42
PCI_C_BE2# 27,42
PCI_C_BE3# 27,42

PCI_IRDY# 27,42
PCI_PAR 27,42

PCI_DEVSEL# 27,42
PCI_PERR# 27,42
PCI_PLOCK# 42
PCI_SERR# 27,42
PCI_STOP# 27,42
PCI_TRDY# 27,42
PCI_FRAME# 27,42

CLK_PCI_ICH 17
ICH_PME# 32

DOCK
Cardbus or

Cardbus/1394
1394/MediaCard

4

5

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

PCI-Express

PCI-Express

Direct Media Interface

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

SPI

SPI

USB

USB

USBRBIAS#

DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS

R5781KR578
1K

1 2

1 2

T25
Y23

Y24
G3

G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

R529

R529
1K_NC

1K_NC

DMI_COMP

USBRBIAS

PCI
SPI1001

SB_NB_PCIE_RST#

A16 away override strap.

SB_NB_PCIE_RST#

GNT0

GNT1

GNT2

PIRQA

PIRQD
PIRQC

PIRQD

5

REQ0

REQ1

REQ2

6

DMI_MTX_IRX_N0 6
DMI_MTX_IRX_P0 6

DMI_MRX_ITX_N0 6
DMI_MRX_ITX_P0 6

DMI_MTX_IRX_N1 6
DMI_MTX_IRX_P1 6

DMI_MRX_ITX_N1 6
DMI_MRX_ITX_P1 6

DMI_MTX_IRX_N2 6
DMI_MTX_IRX_P2 6

DMI_MRX_ITX_N2 6
DMI_MRX_ITX_P2 6

DMI_MTX_IRX_N3 6
DMI_MTX_IRX_P3 6

DMI_MRX_ITX_N3 6
DMI_MRX_ITX_P3 6

CLK_PCIE_ICH# 17
CLK_PCIE_ICH 17

R537 24.9/FR537 24.9/F

12

+1.5V_PCIE_ICH

ICH_USBP0- 33
ICH_USBP0+ 33
ICH_USBP1- 33
ICH_USBP1+ 33
ICH_USBP2- 33
ICH_USBP2+ 33
ICH_USBP3- 33
ICH_USBP3+ 33
ICH_USBP4- 28
ICH_USBP4+ 28
ICH_USBP5- 35
ICH_USBP5+ 35
ICH_USBP6- 28
ICH_USBP6+ 28
ICH_USBP7- 35
ICH_USBP7+ 35
ICH_USBP8- 43
ICH_USBP8+ 43
ICH_USBP9- 29
ICH_USBP9+ 29

R581

R581

22.6/F

22.6/F

1 2

Ext Side Top
Ext Side Bottom
Ext Back Bottom
Power USB
Smart Card
Biometric
Express Card
Blue Tooth
Dock
WWAN

Boot BIOS Strap

GNT0# SPI_CS1#

No stuff

No stuff

11LPC

No stuff

Stuff
No stuff

Stuff

R559

R559
1K_NC

1K_NC

1 2

Low = A16 swap override enabled.
High = Default.

CLK_PCI_ICH

R564

R564
10_NC

10_NC

1 2

C655

C655

8.2P/16V_NC

8.2P/16V_NC

1 2

Reserved for EMI.
Place resister and cap
close to ICH.

6

7

Place within 500mils of ICH8

PCI Pullups

6
7
8
9

+3.3V_RUN

PCI_DEVSEL#
ICH_GPIO4_PIRQG#

+3.3V_RUN

+3.3V_RUN

PCI_PIRQD#

ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_PLOCK#
PCI_PERR#

SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#

BIOS should not enable the
internal GPIO pull up resistor.

Non-iAMT

PCI_RST#_G

PCI_PLTRST#

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+3.3V_SUS

C691

C691

1 2

0.047U/10V

0.047U/10V

+3.3V_SUS

C614

C614

1 2

0.047U/10V

0.047U/10V

ICH8-M (USB,DMI,PCIE,PCI)

ICH8-M (USB,DMI,PCIE,PCI)

ICH8-M (USB,DMI,PCIE,PCI)

JM7 1A

JM7 1A

JM7 1A

10

6
7
8
9

10

6
7
8
9

10

Add Buffers as needed for
Loading and fanout concerns.

5

U42

U42

2
1

7SH32

7SH32

5

U39

U39

2
1

7SH32

7SH32

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

RP43

RP43

10P8R-8.2K

10P8R-8.2K
RP45

RP45

10P8R-8.2K

10P8R-8.2K
RP46

RP46

10P8R-8.2K

10P8R-8.2K

R543 20KR543 20K
R554 20KR554 20K
R565 20KR565 20K

4

PCI_RST# 27,28,42

4

PLTRST# 6,18,28,29,31,32,40

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

8

PCI_STOP#
PCI_FRAME#
PCI_REQ1#

PCI_SERR#
ICH_GPIO3_PIRQF#
ICH_GPIO2_PIRQE#
PCI_TRDY#

PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_IRDY#

12
12
12

of

of

of

12 57Wednesday, June 28, 2006

12 57Wednesday, June 28, 2006

12 57Wednesday, June 28, 2006

8

1

2

3

4

5

6

7

8

Place these close to ICH7.

CLK_ICH_48M

CLK_ICH_14M

R535 10KR535 10K
R560 100KR560 100K

1 2

R516 10K_NCR516 10K_NC
R549 1MR549 1M
R579 1MR579 1M

+3.3V_RUN

R524

R524

3.24K/F

3.24K/F

1 2

CL_VREF1

12

12

R525

R525

C644

C644

453/F

453/F

0.1U/10V_NC

0.1U/10V_NC

12

R582

R582
10_NC

10_NC

12

C666

C666

4.7P/50V_NC

4.7P/50V_NC

12

R574

R574
10_NC

10_NC

12

C664

C664

4.7P/50V_NC

4.7P/50V_NC

12

12
12
12

+3.3V_ALW

1 2

12

13 57Wednesday, June 28, 2006

13 57Wednesday, June 28, 2006

13 57Wednesday, June 28, 2006

8

R536

R536

3.24K/F_NC

3.24K/F_NC

R533

R533
453/F_NC

453/F_NC

of

of

of

RSV_ICH_CL_RST1#

12

ICH_RI#

12

SIO_EXT_SCI#

12

ICH_PCIE_WAKE#

12

ICH_SMBCLK
ICH_SMBDATA
RSV_ICH_CL_RST1#

ICH_RI#
RSV_LPCPD#

SIO_EXT_SCI#

CLKRUN#
ICH_PCIE_WAKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD

RSVD_GPIO6
SIO_EXT_WAKE#

PCIE_MCARD1_DET#
USB_MCARD1_DET#
PCIE_MCARD2_DET#
USB_MCARD2_DET#

RSVD_GPIO38
RSVD_GPIO39
RSVD_GPIO48

SPKR
MCH_ICH_SYNC#_R

12

R577

R577
1K_NC

1K_NC

SPKR

Low = Default.
High = No Reboot.

3

Non-iAMT

U18C

U18C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

ICH8M REV 1.0

SMbus address D2

These are for
backdrive issue.

ICH_SMBDATA28,29,40 MEM_SDATA 15

4

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

SMB

Clocks

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS

GPIO

SYS

GPIO

Power MGTController Link

Power MGTController Link

GPIO

GPIO

MISC

MISC

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

+3.3V_RUN

2

Q41

Q41

3 1

2N7002W-7-F

2N7002W-7-F

+3.3V_RUN

2

Q42

Q42

3 1

2N7002W-7-F

2N7002W-7-F

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_RST#

2

1

4

RP42

RP42
4P2R-2.2K

4P2R-2.2K

3

5

AJ12
AJ10
AF11
AG11

CLK_ICH_14M

AG9

CLK_ICH_48M

G5

ICH_SUSCLK

D3
AG23

AF21
AD18

RSV_SIO_S4_STATE#

AH27

ICH_PWRGD

AE23

DPRSLPVR

AJ14

ICH_BATLOW#

AE21
C2

RSV_ICH_LAN_RST#

AH20

ICH_RSMRST#

AG27
E1

ICH_CL_PWROK

E3

RSV_SIO_SLP_M#

AJ25
F23

RSV_ICH_CL_CLK1

AE18
F22

RSV_ICH_CL_DATA1

AF19

CL_VREF0

D24

CL_VREF1

AH23
AJ23
AJ27

AJ24

GPIO14

GPIO14

AF22

RSV_WOL_EN

AG19

Non-iAMT

+3.3V_RUN

1 2

MEM_SCLK 15ICH_SMBCLK28,29,40

R568

R568

8.2K

8.2K

R538 8.2KR538 8.2K

R544 10KR544 10K

UMA Package:RC0402-C
Discrete Package: RC0402

CLK_ICH_14M 17
CLK_ICH_48M 17

T113PAD T113PAD

SIO_SLP_S3# 31

T84PAD T84PAD

SIO_SLP_S5# 31

T24PAD T24PAD

ICH_PWRGD 6,44
DPRSLPVR 6,51

12

+3.3V_SUS

SIO_PWRBTN# 31

T100PAD T100PAD

ICH_RSMRST# 31
CLK_PWRGD 17
ICH_CL_PWROK 6,31

T85PAD T85PAD

CL_CLK0 6

T104PAD T104PAD

CL_DATA0 6

T97PAD T97PAD

T87PAD T87PAD

ICH_CL_RST0# 6

T22PAD T22PAD

T23PAD T23PAD

T93PAD T93PAD

T95PAD T95PAD

12

+3.3V_SUS

6

ICH_PWRGD
DPRSLPVR
ICH_RSMRST#
RSV_ICH_LAN_RST#

Non-iAMT

ICH_CL_PWROK

Non-iAMT

CL_VREF0

12

C635

C635

0.1U/10V

0.1U/10V

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

ICH8-M (PM,GPIO,SMB,CL)

ICH8-M (PM,GPIO,SMB,CL)

ICH8-M (PM,GPIO,SMB,CL)

JM7 1A

JM7 1A

JM7 1A

7

A A

+3.3V_SUS

RP44

RP44

1
3

4P2R-2.2K

4P2R-2.2K

+3.3V_RUN

R570

R570

8.2K

8.2K

1 2
12

R569

B B

C C

+3.3V_RUN

+3.3V_RUN

D D

+3.3V_ALW

R569

10_NC

10_NC

Option to " Disable "
clkrun. Pulling it down
will keep the clks
running.

R261 2.2K_NCR261 2.2K_NC

R561 10KR561 10K
R567 10K_NCR567 10K_NC
R193 10KR193 10K
R267 10KR267 10K
R573 10KR573 10K
R265 10KR265 10K
R572 10KR572 10K
R269 100KR269 100K

1 2

R268 100KR268 100K

1 2

R576 100KR576 100K

1 2

R266 100KR266 100K

R458 10KR458 10K

1

CLKRUN#

12

12
12
12
12
12
12
12

12

12

Non-iAMT

ICH_SMBDATA

2

ICH_SMBCLK

4

IMVP_PWRGD

RSV_THRM#
MCH_ICH_SYNC#_R
IRQ_SERIRQ
RSVD_GPIO6
RSVD_GPIO38
RSVD_GPIO39
RSVD_GPIO48
PCIE_MCARD1_DET#
USB_MCARD1_DET#
PCIE_MCARD2_DET#
USB_MCARD2_DET#

SIO_EXT_SMI#

MCH_ICH_SYNC#6

+3.3V_SUS

R541 10KR541 10K
R545 10KR545 10K
R532 10KR532 10K
R548 1KR548 1K

ICH_SMBCLK28,29,40
ICH_SMBDATA28,29,40

ITP_DBRESET#3,31
PM_BMBUSY#6
SIO_EXT_SCI#31

H_STP_PCI#17
H_STP_CPU#17

CLKRUN#27,31,32
ICH_PCIE_WAKE#32

IRQ_SERIRQ27,31,32,40

IMVP_PWRGD31,44,51

USB_IDE#26
SIO_EXT_WAKE#32

SIO_EXT_SMI#31

PCIE_MCARD1_DET#29
USB_MCARD1_DET#29
PCIE_MCARD2_DET#29
USB_MCARD2_DET#29

IDE_RST_MOD26
SATA_CLKREQ#17

SPKR38

ICH_RSVD11

T94 PADT94 PAD
T105 PADT105 PAD
T96 PADT96 PAD

T112 PADT112 PAD

T106 PADT106 PAD

T26 PADT26 PAD

T33 PADT33 PAD

T91 PADT91 PAD

T83 PADT83 PAD

T114 PADT114 PAD
T32 PADT32 PAD
T102 PADT102 PAD

R263 0R263 0

+3.3V_RUN

1 2

No Reboot strap.

SPKR

2

1

+RTC_CELL

R264 100R264 100

+5V_RUN

+3.3V_RUN

A A

Non-iAMT

+5V_SUS

+3.3V_SUS

B B

C C

Non-iAMT

Place C929
close to A24.

+1.5V_RUN

D D

1 2

2 1

CH751H-40HPT

CH751H-40HPT

R276 10R276 10

1 2

2 1

CH751H-40HPT

CH751H-40HPT

+1.5V_RUN

12

L58

L58
BLM21PG331SN1D

BLM21PG331SN1D

12

+

+

C287

C287
220U/4V

220U/4V

+1.5V_RUN

12

R2770R277
0

+VCCSATPLL_L

12

L40

L40
10uH/100MA

10uH/100MA

10uH+-20%_100mA

+VCCSATPLL

12

C665

C665
1U/10V

1U/10V

+VCCGLANPLL

C634

C634

0.1U/10V

0.1U/10V

1 2

1

D18

D18

D19

D19

12

C611

C611
1U/10V

1U/10V

+ICH_V5REF_RUN

C303

C303

0.1U/10V

0.1U/10V

1 2

+ICH_V5REF_SUS

C312

C312

0.1U/10V

0.1U/10V

1 2

FB_330ohm+-25%_100mHz_

1.5A_0.09 ohm DC

C637

C637
22U/10V

22U/10V

C315

C315
10U/6.3V

10U/6.3V

12

C617

C617
22U/10V

22U/10V

+1.5V_RUN

12

12

Non-iAMT

+3.3V_RUN

+1.5V_PCIE_ICH

C633

C633

0.1U/10V

0.1U/10V

1 2

+1.5V_PCIE_ICH

1 2

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

C671

C671

0.1U/10V

0.1U/10V

1 2

T103PADT103PAD
T99 PADT99 PAD

C645

C645

0.1U/10V

0.1U/10V

2

C640

C640

2.2U/10V

2.2U/10V

1 2

12

C302

C302

4.7U/6.3V

4.7U/6.3V

2

C612

C612

0.1U/10V

0.1U/10V

1 2

+VCCSATPLL

12

C669

C669
1U/10V

1U/10V

12

C657

C657
1U/10V

1U/10V

C608

C608

0.1U/10V

0.1U/10V

1 2

TP_VCCSUSLAN1
TP_VCCSUSLAN2

+VCCGLANPLL

+3.3V_RUN

AD25

AA25
AA26
AA27
AB27
AB28
AB29

G24
H23
H24

K24
K25

M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27

U24
U25
V23
V24
V25

W25

Y25

AE7
AF7
AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC10

AC9
AA5

AA6
G12

G17

AC7
AD7

W23

G18

G20
A24
A26

A27
B26
B27
B28

B25

A16

D28
D29
E25
E26
E27
F24
F25

J23
J24

L23
L24
L25

T23
T24
T27
T28
T29

AJ6

AJ7

F17

F19

T7

G4

H7

D1

F1
L6

L7
M6
M7

U18F

U18F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

ICH8M REV 1.0

3

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCA3GP ATXARX

VCCA3GP ATXARX

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCCP_COREVCCPSUSVCCPUSB

VCCP_COREVCCPSUSVCCPUSB

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]

IDE

IDE

VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]

PCI

PCI

VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

GLAN POWER

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

4

C648

C648

0.1U/10V

0.1U/10V

1 2

+1.5V_DMIPLL

0.01U/25V

0.01U/25V

+VCC_DMI

+V_CPU_IO

C653

C653

0.1U/10V

0.1U/10V

1 2

TP_VCCSUS1.05_1
TP_VCCSUS1.05_2

TP_VCCSUS1.5_1
TP_VCCSUS1.5_2
+VCCSUS3_3[0~6]

+VCCSUS3_3[7~19]

TP_VCCCL1.05
+VCCCL1_5

+3.3V_RUN

Non-iAMT

4

C659

C659

0.1U/10V

0.1U/10V

1 2

C630

C630

1 2

C628

C628

0.1U/10V

0.1U/10V

1 2

C629

C629

0.1U/10V

0.1U/10V

1 2

C660

C660

0.1U/10V

0.1U/10V

1 2

C636

C636

0.1U/10V

0.1U/10V

1 2

Non-iAMT

5

+1.05V_VCCP

+1.05V_VCCP +1.5V_RUN

D33

D33

1

2

BAT54C

BAT54C

1uH+-20%_800mA

L59

L59
1uH_800MA

C615

C615

10U/6.3V

10U/6.3V

T108PAD T108PAD
T27PAD T27PAD

T101PAD T101PAD
T110PAD T110PAD

T86PAD T86PAD

12

C291

C291
22U/10V

22U/10V

C673

C673

0.1U/10V

0.1U/10V

1 2

C663

C663

0.1U/10V

0.1U/10V

1 2

1 2

1uH_800MA

1 2

+1.25V_RUN

+3.3V_RUN

C658

C658

0.1U/10V

0.1U/10V

C643

C643

0.1U/10V_NC

0.1U/10V_NC

1 2

+1.5V_DMIPLL_R

12

+3.3V_RUN+3.3V_SUS

C656

C656

0.1U/10V

0.1U/10V

1 2

Non-iAMT

12

C313

C313

0.022U/16V

0.022U/16V

12

C642

C642
1U/10V_NC

1U/10V_NC

5

R540

R540

3

1 2

10/0805

10/0805

+V_CPU_IO

12

C654

C654

0.1U/10V

0.1U/10V

R512 1R512 1

12

C631

C631

0.022U/16V

0.022U/16V

12

C661

C661

0.1U/10V

0.1U/10V

6

+1.5V_RUN

12

12

+3.3V_SUS

6

C639

C639

0.1U/10V

0.1U/10V

+1.05V_VCCP

12

7

U18E

U18E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

C641

C641

4.7U/10V

4.7U/10V

Title

Title

Title

ICH8-M (POWER,GND)

ICH8-M (POWER,GND)

ICH8-M (POWER,GND)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

JM7 1A

JM7 1A

JM7 1A

Date: Sheet

Date: Sheet

Date: Sheet

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

ICH8M REV 1.0

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

8

of

of

of

14 57Wednesday, June 28, 2006

14 57Wednesday, June 28, 2006

14 57Wednesday, June 28, 2006

8

1

DDR_A_D0
DDR_A_D5

DDR_A_D3
DDR_A_D2

DDR_A_D12
DDR_A_D9

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D16

DDR_A_D18
DDR_A_D22

DDR_A_D28
DDR_A_D29

DDR_A_DM3

DDR_A_D26
DDR_A_D31

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

M_ODT1
DDR_A_D37

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D34
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D53

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D51

DDR_A_D60
DDR_A_D57

DDR_A_DM7
DDR_A_D63

DDR_A_D59

MEM_SCLK

+1.8V_SUS

A is required to route to Top
SoDIMM for AMTto function.
Ch.A SODIMM needs to be
populated for Intel AMT support.

DDR_A_DQS#0

A A

B B

DDR_CKE0_DIMMA6,16

DDR_A_BS27,16

DDR_A_BS07,16
DDR_A_WE#7,16

DDR_A_CAS#7,16
DDR_CS1_DIMMA#6,16

M_ODT16,16

C C

D D

MEM_SDATA13
MEM_SCLK13
+3.3V_RUN

Non-iAMT

DDR_A_DQS0

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_DQS#2
DDR_A_DQS2

SMbus address A0 SMbus address A4

1

2

V_DDR_MCH_REF

JDIM1

JDIM1

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

CLOCK 0,1

2

3

+1.8V_SUS

TOP BOT

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

84

A15

86

A14

88

VDD11

90

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

TYC_1775804-2

TYC_1775804-2

DDR_A_D4
DDR_A_D1

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D8

DDR_A_D13
DDR_A_DM1

DDR_A_D11
DDR_A_D10

DDR_A_D17
DDR_A_D21

PM_EXTTS#0 PM_EXTTS#1
DDR_A_DM2

DDR_A_D23
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D27

DDR_CKE1_DIMMA 6,16

DDR_A_MA14 6,16 DDR_B_MA14 6,16

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA# 6,16

M_ODT0

DDR_A_MA13

DDR_A_D36
DDR_A_D32

DDR_A_DM4
DDR_A_D38

DDR_A_D35
DDR_A_D45

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D49

DDR_A_D52

DDR_A_DM6
DDR_A_D55

DDR_A_D50
DDR_A_D56

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D58

R247

R247

R250

R250

10K

10K

10K

10K

1 2

1 2

3

DDR_A_DM[0..7] 7
DDR_A_D[0..63] 7
DDR_A_DQS[0..7] 7
DDR_A_DQS#[0..7] 7
DDR_A_MA[0..13] 7,16

V_DDR_MCH_REF

12

C571

C571

0.1U/10V

0.1U/10V

M_CLK_DDR0 6
M_CLK_DDR#0 6

PM_EXTTS#0 6

DDR_A_BS1 7,16
DDR_A_RAS# 7,16

M_ODT0 6,16

+3.3V_RUN

12

C583

C583

2.2U/6.3V

2.2U/6.3V

M_CLK_DDR1 6
M_CLK_DDR#1 6

4

12

C573

C573

2.2U/6.3V

2.2U/6.3V

DDR_CKE3_DIMMB6,16

DDR_B_BS27,16

DDR_B_BS07,16
DDR_B_WE#7,16

DDR_B_CAS#7,16

DDR_CS3_DIMMB#6,16

Non-iAMT

12

C582

C582

0.1U/10V

0.1U/10V

Non-iAMT

+3.3V_RUN

4

5

+1.8V_SUS +1.8V_SUS

V_DDR_MCH_REF

JDIM2

JDIM2

1

VREF

3

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D2

DDR_B_D12
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D15
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DM3

DDR_B_D31
DDR_B_D26

DDR_B_BS2

DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

M_ODT36,16

M_ODT3
DDR_B_D37

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D43 DDR_B_D46

DDR_B_D42
DDR_B_D52

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54

DDR_B_D56
DDR_B_D60

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATAMEM_SDATA

MEM_SCLK

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

FOX_AS0A426-M2SN-7F

FOX_AS0A426-M2SN-7F

CLOCK 2,3

CKE 2,3CKE 0,1

5

6

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

84

A15

86

A14

88

VDD11

90

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D13

DDR_B_D8
DDR_B_DM1

DDR_B_D14
DDR_B_D10

DDR_B_D16
DDR_B_D21

DDR_B_DM2
DDR_B_D19

DDR_B_D22
DDR_B_D25

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D27

DDR_CKE4_DIMMB 6,16

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB# 6,16

M_ODT2

DDR_B_MA13

DDR_B_D36
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D47
DDR_B_D48

DDR_B_D55

DDR_B_DM6
DDR_B_D50

DDR_B_D53DDR_B_D51
DDR_B_D57

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

R469 10KR469 10K

R463

R463
10K

10K

1 2

6

12

7

DDR_B_DM[0..7] 7
DDR_B_D[0..63] 7
DDR_B_DQS[0..7] 7
DDR_B_DQS#[0..7] 7
DDR_B_MA[0..13] 7,16

V_DDR_MCH_REF

M_CLK_DDR3 6
M_CLK_DDR#3 6

PM_EXTTS#1 6

+1.8V_SUS

12

C232

C232

2.2U/6.3V

2.2U/6.3V

+1.8V_SUS

12

12

C580

C580

0.1U/10V

0.1U/10V

C578

C578

2.2U/6.3V

2.2U/6.3V

Place these Caps near So-Dimm1.

12

12

C231

C231

C277

C277

2.2U/6.3V

2.2U/6.3V

2.2U/6.3V

2.2U/6.3V

Place these Caps near So-Dimm2.

DDR_B_BS1 7,16
DDR_B_RAS# 7,16

M_ODT2 6,16

M_CLK_DDR4 6
M_CLK_DDR#4 6

12

C584

C584

2.2U/6.3V

2.2U/6.3V

+1.8V_SUS

Place these Caps near So-Dimm1.

12

C279

C279

0.1U/10V

0.1U/10V

+1.8V_SUS

Place these Caps near So-Dimm2.

12

C586

C586

0.1U/10V

0.1U/10V

+3.3V_RUN

12

C219

C219

2.2U/6.3V

2.2U/6.3V

12

C567

C567

2.2U/6.3V

2.2U/6.3V

12

C280

C280

0.1U/10V

0.1U/10V

12

C585

C585

0.1U/10V

0.1U/10V

Non-iAMT

12

C226

C226

0.1U/10V

0.1U/10V

12

C589

C589

2.2U/6.3V

2.2U/6.3V

12

C233

C233

0.1U/10V

0.1U/10V

12

C569

C569

0.1U/10V

0.1U/10V

Non-iAMT

+3.3V_RUN

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

DDR2 SO-DIMM (200P) X 2

DDR2 SO-DIMM (200P) X 2

DDR2 SO-DIMM (200P) X 2

JM7 1A

JM7 1A

JM7 1A

7

12

C284

C284

2.2U/6.3V

2.2U/6.3V

12

C564

C564

2.2U/6.3V

2.2U/6.3V

12

C234

C234

0.1U/10V

0.1U/10V

12

C568

C568

0.1U/10V

0.1U/10V

8

12

C281

C281

2.2U/6.3V

2.2U/6.3V

12

C566

C566

2.2U/6.3V

2.2U/6.3V

of

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15 57Wednesday, June 28, 2006

15 57Wednesday, June 28, 2006

15 57Wednesday, June 28, 2006

8

1

2

3

4

5

6

7

8

+0.9V_DDR_VTT

A A

B B

C C

D D

1

Please these resistor
closely DIMMB,all
trace length<750 mil.

12

C605

C605

0.1U/10V

0.1U/10V

+0.9V_DDR_VTT

12

C296

C296

0.1U/10V

0.1U/10V

2

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

12

C604

C604

0.1U/10V

0.1U/10V

12

C294

C294

0.1U/10V

0.1U/10V

DDR_B_MA[0..13]7,15 DDR_A_MA[0..13] 7,15

DDR_B_RAS#7,15
DDR_B_BS17,15

M_ODT26,15

DDR_B_BS07,15

DDR_B_WE#7,15
DDR_B_CAS#7,15

M_ODT16,15

DDR_CS0_DIMMA#6,15
DDR_CS1_DIMMA#6,15
DDR_CKE0_DIMMA6,15
DDR_CKE1_DIMMA6,15

DDR_A_MA146,15

12

12

12

C607

C607

C606

C606

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

12

C295

C295

C211

C211

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

DDR_B_MA7
DDR_B_MA11

DDR_B_MA4
DDR_B_MA6

DDR_B_BS1 DDR_A_BS1

DDR_B_MA13
M_ODT2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA0
DDR_B_MA2

R204 56R204 56

DDR_A_MA1

R206 56R206 56
R253 56R253 56
R205 56R205 56
R215 56R215 56
R252 56R252 56
R254 56R254 56

3

12

C601

C601

0.1U/10V

0.1U/10V

12

C297

C297

0.1U/10V

0.1U/10V

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

1 2
1 2
1 2
1 2
1 2
1 2
1 2

RP34

RP34

4P2R-S-56

4P2R-S-56
RP33

RP33

4P2R-S-56

4P2R-S-56
RP31

RP31

4P2R-S-56

4P2R-S-56
RP30

RP30

4P2R-S-56

4P2R-S-56
RP39

RP39

4P2R-S-56

4P2R-S-56
RP38

RP38

4P2R-S-56

4P2R-S-56
RP37

RP37

4P2R-S-56

4P2R-S-56
RP36

RP36

4P2R-S-56

4P2R-S-56
RP40

RP40

4P2R-S-56

4P2R-S-56
RP32

RP32

4P2R-S-56

4P2R-S-56

12

C597

C597

0.1U/10V

0.1U/10V

12

C298

C298

0.1U/10V

0.1U/10V

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

TOP

12

C598

C598

0.1U/10V

0.1U/10V

BOT

12

C299

C299

0.1U/10V

0.1U/10V

+0.9V_DDR_VTT

4

12

12

C554

C554

C555

C555

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

12

12

C217

C217

C210

C210

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

RP14

RP14

1
3

4P2R-S-56

4P2R-S-56

RP13

RP13

1
3

4P2R-S-56

4P2R-S-56

RP11

RP11

1
3

4P2R-S-56

4P2R-S-56

RP10

RP10

1
3

4P2R-S-56

4P2R-S-56

RP7

RP7

1
3

4P2R-S-56

4P2R-S-56

RP6

RP6

1
3

4P2R-S-56

4P2R-S-56

RP5

RP5

1
3

4P2R-S-56

4P2R-S-56

RP9

RP9

1
3

4P2R-S-56

4P2R-S-56

RP8

RP8

1
3

4P2R-S-56

4P2R-S-56

RP12

RP12

1
3

4P2R-S-56

4P2R-S-56

R486 56R486 56
R492 56R492 56
R464 56R464 56
R487 56R487 56
R488 56R488 56
R474 56R474 56
R465 56R465 56

12

C551

C551

0.1U/10V

0.1U/10V

12

12

C212

C212

0.1U/10V

0.1U/10V

DDR_A_MA7

2

DDR_A_MA11

4

DDR_A_MA4

2

DDR_A_MA6

4

DDR_A_RAS#DDR_B_RAS#

2
4

DDR_A_MA13

2

M_ODT0

4

DDR_A_BS2

2

DDR_A_MA12

4

DDR_A_MA9

2

DDR_A_MA8

4

DDR_A_MA5

2

DDR_A_MA3

4

DDR_A_MA10

2

DDR_A_BS0

4

DDR_A_WE#

2

DDR_A_CAS#

4

DDR_A_MA0

2

DDR_A_MA2

4

12
12
12
12
12
12
12

5

C552

C552

0.1U/10V

0.1U/10V

C213

C213

0.1U/10V

0.1U/10V

C553

C553

0.1U/10V

0.1U/10V

12

C214

C214

0.1U/10V

0.1U/10V

DDR_A_RAS# 7,15
DDR_A_BS1 7,15

M_ODT0 6,15

DDR_A_BS2 7,15

DDR_A_BS0 7,15

DDR_A_WE# 7,15
DDR_A_CAS# 7,15

M_ODT3 6,15

DDR_B_BS2 7,15
DDR_CS2_DIMMB# 6,15
DDR_CS3_DIMMB# 6,15
DDR_CKE3_DIMMB 6,15
DDR_CKE4_DIMMB 6,15

DDR_B_MA14 6,15

12

12

12

12

12

C293

C293

C556

C556

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

12

C603

C603

C215

C215

0.1U/10V

0.1U/10V

0.1U/10V

0.1U/10V

Please these resistor
closely DIMMA,all
trace length<750 mil.

6

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

DDR2 RES ARRAY

DDR2 RES ARRAY

DDR2 RES ARRAY

JM7 1A

JM7 1A

JM7 1A

7

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of

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16 57Wednesday, June 28, 2006

16 57Wednesday, June 28, 2006

16 57Wednesday, June 28, 2006

8

1

Non-iAMTNon-iAMT

+3.3V_RUN +3.3V_RUN

R442

A A

B B

C C

D D

R442
10K_NC

10K_NC

1 2

R438

R438
10K_NC

10K_NC

1 2

+3.3V_RUN

Non-iAMT

Enable ITP

10K

10K
R431

R431

1 2

PCI_ICH

+3.3V_RUN

L55

L55

1 2

BLM21PG600SN1D

BLM21PG600SN1D

120 ohms@100Mhz

L52

L52

1 2

BLM21PG600SN1D

BLM21PG600SN1D

120 ohms@100Mhz

1

R156

R156
10K_NC

10K_NC

1 2

PCI_LOMFSA

R155

R155
10K

10K

1 2

0=UMA
1 = Disc. GRFX down

12

C550

C550

0.1U/10V

0.1U/10V

12

R175 2.2R175 2.2

1 2

12

C522

C522

0.1U/10V

0.1U/10V

R432 2.2R432 2.2

1 2

R433 1R433 1

1 2

2

Add capacitor pads for improving WWAN.

C193 27P/50V_NCC193 27P/50V_NC

1 2

C191 27P/50V_NCC191 27P/50V_NC

1 2

C514 27P/50V_NCC514 27P/50V_NC

1 2

C171 27P/50V_NCC171 27P/50V_NC

1 2

C169 27P/50V_NCC169 27P/50V_NC

1 2

C579 27P/50V_NCC579 27P/50V_NC

1 2

C184 27P/50V_NCC184 27P/50V_NC

1 2

C516 27P/50V_NCC516 27P/50V_NC

1 2

C181 27P/50V_NCC181 27P/50V_NC

1 2

C190 27P/50V_NCC190 27P/50V_NC

1 2

+3.3V_RUN

R427 10K_NCR427 10K_NC

1 2

CLK_SMCARD_48M28
CLK_ICH_48M13
CPU_MCH_BSEL03,6
CPU_MCH_BSEL13,6
CPU_MCH_BSEL23,6
CLK_SIO_14M32
CLK_ICH_14M13
CLK_PCI_501832
CLK_PCI_502531
CLK_PCI_PCCARD27
CLK_PCI_DOCK43
CLK_PCI_TPM40

MCH_DREFCLK6
MCH_DREFCLK#6

CLK_PCI_ICH12
CLK_PWRGD13

UMA without iAMT

+CK_VDD_MAIN

C547

C547

0.1U/10V

0.1U/10V

2

12

C541

C541

0.1U/10V

0.1U/10V

+CK_VDD_A

+CK_VDD_MAIN2

12

C527

C527

0.1U/10V

0.1U/10V

+CK_VDD_48

12

C536

C536

0.047U/10V

0.047U/10V

+CK_VDD_REF

12

C548

C548

0.1U/10V

0.1U/10V

12

12

12

12

C543

C543

0.047U/10V

0.047U/10V

C521

C521
10U/6.3V

10U/6.3V

C537

C537

4.7U/6.3V

4.7U/6.3V

C531

C531

0.047U/10V

0.047U/10V

12

C197

C197

0.1U/10V

0.1U/10V

3

CLK_SMCARD_48M
CLK_ICH_48M
CLK_SIO_14M
CLK_ICH_14M
CLK_PCI_5018
CLK_PCI_5025
CLK_PCI_PCCARD
CLK_PCI_DOCK
CLK_PCI_TPM
CLK_PCI_ICH

Non-iAMT

PCI_PCCARD

R439 15R439 15

1 2

R440 15R440 15

1 2

R441 8.2KR441 8.2K

1 2

R425 8.2KR425 8.2K

1 2

R424 15R424 15
R150 15R150 15
R151 15R151 15
R426 15R426 15
R428 33R428 33
R429 33R429 33
R157 33R157 33

R434 33R434 33

3

4

2

12

C194

C194

4.7U/6.3V

4.7U/6.3V

12

C549

C549
10U/6.3V

10U/6.3V

12
12
12
12
12
12
12

3
1

12

RP20

RP20
4P2R-S-33

4P2R-S-33

4

+CK_VDD_MAIN2

+CK_VDD_MAIN
+CK_VDD_48
+CK_VDD_REF
CLK_XTAL_IN

CLK_XTAL_OUT
FSA

FSB
FSC

CLKREF
PCI_SIO

PCI_PCCARD
PCI_DOCK
PCI_LOM

27M_NSS
27M_SS

PCI_ICH

CLK_SCLK
CLK_SDATA

SMbus address D2

These are for
backdrive issue.

4

12

C525

C525
27P/50V

27P/50V

U34

U34

1

VDD_SRC_01

49

VDD_SRC_02

54

VDD_SRC_03

65

VDD_SRC_04

30

VDD_PCI_01

36

VDD_PCI_02

12

VDD_CPU

40

VDD_48

18

VDD_REF

20

XIN

19

XOUT

41

48M/FSA

45

FSB/TEST_MODE

23

REF0/FSC_TEST_SEL

22

REF1

27

PCI1

32

PCI2/TME

33

PCI3

34

PCI4/FCTSEL1

43

DOT96T/27M_NSS

44

DOT96C/27M_SS

37

PCIF0/ITP_SEL

39

VTT_PWRDG#/PD(CKPWRGD/PD#)

16

SCLK

17

SDATA

15

VSS_01

31

VSS_02

35

VSS_03

21

VSS_04

4

VSS_05

42

VSS_06

68

VSS_07

CKG_SMBDAT31

CKG_SMBCLK31

Y3

Y3

1 2

14.318MHZ

14.318MHZ

CK505

CK505

+3.3V_ALW

+3.3V_RUN

R149

R149

2.2K

2.2K

1 2

3 1

2N7002W-7-F

2N7002W-7-F
R148 0_NCR148 0_NC

1 2

+3.3V_ALW

+3.3V_RUN

R162

R162

2.2K

2.2K

1 2

3 1

2N7002W-7-F

2N7002W-7-F
R167 0_NCR167 0_NC

1 2

5

12

C524

C524
27P/50V

27P/50V

CPUT2_ITP/SRCT_10

CPUC2_ITP/SRCC_10

SRCT_0/LCD100MT

SRCC_0/LCD100MC

2

Q22

Q22

2

Q23

Q23

5

CLK_XTAL_OUTCLK_XTAL_IN

14.318MHz

PCI_STP#

CPU_STP#

CPUT1_MCH
CPUC1_MCH

CPUT0
CPUC0

PGMODE

SRCT_9
SRCC_9

CLKREQ9#

SRCT_8
SRCC_8

CLKREQ8#

SRCT_7
SRCC_7

CLKREQ7#

SRCT_6
SRCC_6

CLKREQ6#

SRCT_5
SRCC_5

CLKREQ5#

SRCT_4
SRCC_4

CLKREQ4#

SRCT_3
SRCC_3

CLKREQ3#

SRCT_2
SRCC_2

CLKREQ2#

SRCT_1/SATAT

SRCC_1/SATAC

CLKREQ1#

CY28547LFXC

CY28547LFXC

Non-iAMT

2

4

RP16

RP16
4P2R-2.2K

4P2R-2.2K

1

3

CLK_SDATA

CLK_SCLK

VDDA

VSSA

7
8

25
24

11
10

14
13

6
5

9
3

2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46

47
48

6

+CK_VDD_A

MCH_BCLK
MCH_BCLK#

CPU_BCLK
CPU_BCLK#

CPU_ITP
CPU_ITP#

PGMODE

R445 10K_NCR445 10K_NC

PCIE_MINI1
PCIE_MINI1#

PCIE_MINI2
PCIE_MINI2#

PCIE_ICH
PCIE_ICH#

PCIE_EXPCARD
PCIE_EXPCARD#

PCIE_LOM
PCIE_LOM#

MCH_3GPLL
MCH_3GPLL#

R154 475/FR154 475/F

PCIE_SATA
PCIE_SATA#

DOT96_SSC
DOT96_SSC#

6

Populate for Napa platforms only.

RP19

3
1

3
1

3
1

3
1

3
1

1
3

1
3

1
3

1
3
12

1
3

4
2

RP19
4P2R-S-33

4P2R-S-33
RP17

RP17
4P2R-S-33

4P2R-S-33
RP22

RP22
4P2R-S-33

4P2R-S-33

RP24

RP24
4P2R-S-33

4P2R-S-33
RP29

RP29
4P2R-S-33

4P2R-S-33
RP26

RP26
4P2R-S-33

4P2R-S-33

RP27

RP27
4P2R-S-33

4P2R-S-33
RP28

RP28
4P2R-S-33

4P2R-S-33
RP25

RP25
4P2R-S-33

4P2R-S-33

RP23

RP23
4P2R-S-33

4P2R-S-33

RP21

RP21
4P2R-S-33

4P2R-S-33

4
2

4
2

4
2

1 2
4

2
4

2
2

4

2
4

2
4

2
4

2
4

3
1

PCI_LOM = FCTSEL1

FCTSEL1
(PIN34)

0=UMA
1 = Disc.

GRFX down

PIN43 PIN44 PIN47 PIN48

DOT96T

27Mout

Title

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Date: Sheet

7

CLK_3GPLLREQ#
SATA_CLKREQ#
LOM_CLKREQ#
CARD_CLK_REQ#
MINI1CLK_REQ#
MINI2CLK_REQ#

PGMODE

H_STP_PCI# 13
H_STP_CPU# 13

CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

CLK_CPU_ITP 3
CLK_CPU_ITP# 3

+3.3V_RUN

CLK_PCIE_MINI1 29
CLK_PCIE_MINI1# 29

MINI1CLK_REQ# 29
CLK_PCIE_MINI2 29
CLK_PCIE_MINI2# 29

MINI2CLK_REQ# 29
CLK_PCIE_ICH 12
CLK_PCIE_ICH# 12

CLK_PCIE_EXPCARD 28
CLK_PCIE_EXPCARD# 28

CARD_CLK_REQ# 28
CLK_PCIE_LOM 40
CLK_PCIE_LOM# 40

LOM_CLKREQ# 40
CLK_MCH_3GPLL 6
CLK_MCH_3GPLL# 6

CLK_3GPLLREQ# 6

CLK_PCIE_SATA 11
CLK_PCIE_SATA# 11

SATA_CLKREQ# 13
DREF_SSCLK 6

DREF_SSCLK# 6

R147 10KR147 10K
R153 10KR153 10K
R190 10KR190 10K
R152 10KR152 10K
R192 10KR192 10K
R195 10KR195 10K

R448 10K_NCR448 10K_NC

1 2

+3.3V_RUN

12
12
12
12
12
12

Non-iAMT

Broadcom

8

FSC FSB FSA CPU SRC PCI

100

1
0

1

0

1

0
00
1

0

1

1
1

1

DOT96C

27MSSout

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

JM7 1A

JM7 1A

JM7 1A

7

100

1
10
1
0
0
0
0
1

96/
100M_T

133
166
200
266
333
400

RSVD

100
100
100
100
100
100
100

96/
100M_C

SRCT0 SRCC0

330
33
33
33
33
33
33
33

of

of

of

17 57Wednesday, June 28, 2006

17 57Wednesday, June 28, 2006

17 57Wednesday, June 28, 2006

8

5

D D

+3.3V_RUN

R74

R74

R73

R73

4.7K

4.7K

4.7K

4.7K

1 2

1 2

C C

+3.3V_RUN

12

12

+5V_RUN

B B

1 2

R72

R72
1K_NC

1K_NC

R711KR71
1K

R70

R70

2.2K

2.2K

SDVO_CTRLDATA
SDVO_CTRLCLK

SIL_A1

R69

R69

2.2K

2.2K

1 2

DVI_SDAT
DVI_SCLK

DVI_DETECT43 SDVOB_RED+ 6

SDVO_CTRLDATA6

SDVO_CTRLCLK6
PLTRST#6,12,28,29,31,32,40

DVI_TX0+43
DVI_TX0-43
DVI_TX1+43
DVI_TX1-43
DVI_TX2+43
DVI_TX2-43
DVI_CLK+43
DVI_CLK-43

DVI_SDAT43

DVI_SCLK43

SIL_AVCC

4

R68 220R68 220

1 2

SIL_A1
SDVO_CTRLDATA
SDVO_CTRLCLK

DVI_TX0+
DVI_TX0­DVI_TX1+
DVI_TX1­DVI_TX2+
DVI_TX2­DVI_CLK+
DVI_CLK-

EXT_SWING
DVI_SDAT
DVI_SCLK

U5

U5

SIL 1362ACLU Tx

SIL 1362ACLU Tx
64 Pin TQFP

64 Pin TQFP

29

HTPLG

6

CONFIG/

CONFIG/

A1

4

SDSDA

PROGRAM

PROGRAM

5

SDSCL

2

RESET#

17

TX0+

16

TX0-

20

TX1+

19

I2C

I2C

TX1-

23

TX2+

Master

Master

22

TX2-

14

TXC+

13

TXC-

25

EXT_SWING

9

SDADCC

8

SCLDDC

30

TEST

7

GND1

31

GND2

18

AGND1

24

AGND2

12

AGND/PGND1

27

PGND2

39

SGND1

45

SGND2

3

SPGND

SI1362ACLU

SI1362ACLU

SDVO

SDVO

SDVOB_CLK+

SDVOB_CLK­SDVOB_INT+

SDVOB_INT-

POWER/

POWER/
GROUND

GROUND

3

SDVOB_R+

SDVOB_R-

SDVOB_G+

SDVOB_G-

SDVOB_B+

SDVOB_B-

EXT_RES

VCC1
VCC2

VCC3
AVCC1
AVCC2

PVCC1
PVCC2

SVCC1
SVCC2

SPVCC

OVCC

37
38
40
41
43
44
46
47

INT+

32
33
35

10
28
34
15
21

11
26

36
42

48
1

C77 0.1U/10VC77 0.1U/10V

INT-

C80 0.1U/10VC80 0.1U/10V

R75 1KR75 1K

SIL_VCC

SIL_AVCC

SIL_PVCC1
SIL_PVCC2

SIL_SVCC

SIL_SPVCC

C83

C83

0.1U/10V

0.1U/10V

12

12

Placed this capacitor
close to OVCC.

12
12

12

+3.3V_RUN

C93

C93
10U/6.3V

10U/6.3V

SDVOB_RED- 6
SDVOB_GREEN+ 6
SDVOB_GREEN- 6
SDVOB_BLUE+ 6
SDVOB_BLUE- 6
SDVOB_CLK+ 6
SDVOB_CLK- 6

2

SDVOB_INT+ 6
SDVOB_INT- 6

SIL_VCC

12

C82

C82

0.1U/10V

0.1U/10V

SIL_AVCC

12

C62

C62

0.1U/10V

0.1U/10V

SIL_PVCC1

12

C65

C65
10U/6.3V

10U/6.3V

SIL_PVCC2

12

C64

C64
10U/6.3V

10U/6.3V

SIL_SVCC

12

C90

C90

0.1U/10V

0.1U/10V

12

C75

C75
10U/6.3V

10U/6.3V

12

C63

C63

0.1U/10V

0.1U/10V

L23

L23

1 2

BLM11A121S

BLM11A121S

12

C67

C67

0.1U/10V

0.1U/10V

L24

L24

1 2

BLM11A121S

BLM11A121S

12

C66

C66

0.1U/10V

0.1U/10V

12

C91

C91

0.1U/10V

0.1U/10V

12

C74

C74

0.1U/10V

0.1U/10V

L22

L22

1 2

BLM11A121S

BLM11A121S

12

C60

C60
10U/6.3V

10U/6.3V

+3.3V_RUN

+3.3V_RUN

L27

L27

1 2

BLM18PG181SN1

BLM18PG181SN1

12

C98

C98
10U/6.3V

10U/6.3V

1

L25

L25

1 2

BLM11A121S

BLM11A121S

12

C422

C422

0.1U/10V

0.1U/10V

+3.3V_RUN

+1.8V_RUN

+1.8V_RUN

L26

DVI_TX0+

R346 110/FR346 110/F

DVI_TX1+
DVI_TX2+
DVI_CLK+

Put these 4 Resistors and 4 Capacitors close to the TX
pin of SDVO device.

A A

5

4

1 2

R345 110/FR345 110/F

1 2

R349 110/FR349 110/F

1 2

R348 110/FR348 110/F

1 2

C414 0.1U/10VC414 0.1U/10V

1 2

C413 0.1U/10VC413 0.1U/10V

1 2

C421 0.1U/10VC421 0.1U/10V

1 2

C420 0.1U/10VC420 0.1U/10V

1 2

3

DVI_TX0­DVI_TX1­DVI_TX2­DVI_CLK-

2

SIL_SPVCC

12

C97

C97
10U/6.3V

10U/6.3V

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Date: Sheet

L26

1 2

BLM11A121S

BLM11A121S

12

C92

C92

0.1U/10V

0.1U/10V

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

SiI 1362

SiI 1362

SiI 1362

JM7 1A

JM7 1A

JM7 1A

+3.3V_RUN

of

of

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18 57Wednesday, June 28, 2006

18 57Wednesday, June 28, 2006

18 57Wednesday, June 28, 2006

1