Dell precision 7520 Schematics

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COMPAL CONFIDENTIAL

1 1

MODEL NAME : PCB NO : BOM P/N : GPIO MAP:

CAP00

LA-E311P

431A4X31L01

Gen7 GPIO Master_XXXX

CRANE15

2 2

REV : 1.0(A00)

2016.11.21

@ : Nopop Component

EMC@ : EMI/ESD/RF part

CONN@ : Connector Component

XDP@ : Total debug Component (pop them until ST)

3 3

Layout Dell logo

Kaby Lake H-type (2 chip)

4 4

DATE: 1403-06

PCB 1TS LA -E311P REV0 MB 1

Part

Description

Number

DAA000CS010

PCB 1TS LA-E311P REV1 MB 1

A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPEC IFICATIONS CONTAINS CONFIDENTI AL TRADE SECRET AND OTHER PROPRIE TARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHO UT THE EXPRESS WRITTEN AUTHORI ZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS WAY BE US ED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

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Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-E311P

1 71Wednesday, N ovember 23, 2016

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1.0

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eDP Panel Conn

P.30

Docking DP Port1

1 1

2 2

On I/O board

3 3

SATA Port 1

USB2 Port 7 USB2 Port 5

USB3.0 Port 6

Docking

4 4

DP1

Docking DP2

mDP

1.3 Conn

HDMI1.4b Conn

UPD TPS65982D

Type-C Conn

Port 3

RTS5242 SD4.0/MMC

SDXC

DAI

RGB

LAN

LPC

SW2 DP

P.6

SW1 DP

DP MUX PS8331

mDP

SW6 DP2

TBT_DP1

SW6 DP1

TBT AR-SP

Port 5~8

Intel Jacksonville WGI219LM

LAN switch

PI3L720ZHEX

Docking LAN

E-Dock

eDP MUX PS8331

P.31

DP DEMUX PS8468

TBT_DP0

PCIE

On Display TBT board

Port 4

RJ45

P.43

P.29

DDI1

DPC

SW4 DP

P.37

Lane x4

P.33

DDI2

SW3 DP

Docking CRT

DDI3

DPB

DP DEMUX PS8338

P.32

Docking DP Port2

M.2 Card slot_3 2280 SSD

TS3V712 VGA 2:1 SW

SW5 DP

DP1.3 MUX HD3SS214

DP MUX PS8331

P.34

Port 5~8 Port 2

TBT AR-SP

P.5~8

On Display I/O board

DP_D

DP_C

MXM Conn. TYPE A

DP_B

DPA

DP_A

DP_F

DP to VGA RTD2166

P.35

P.36

PCIE BUS

Port 9~12

SATA Port 0 SATA Port 4

P.41

SMSC SIO ECE5048

Port 17,18

M.2 Card slot_2 WWAN/LTE/HCA/ Cache

USB2 Port8 USB2 Port 6

BC BUS

P.47

FAN CONN

SW5 DP

DP redriver

mDP 1.3 Conn

HDMI1.4b Conn

mDP

PS8460

DP to HDMI retimer PS8407A

On Display Entry board

SW4 DP

PEG x16 (Gen3)

P.18

VGA

M.2 Card slot_1 WLAN/BT

P.40

SMSC KBC MEC5085

P.28

Micro SIM Card

Free Fall Sensor

LNG2DMTR

P.40

P.43

P.40

P.48

KB/TP CONN

eDP

Intel

DDI3

KABYLAKE-H/

DDI1

DDI2

SKYLAKE-H 44e

PEG

BGA CPU 1440 Pins

Intel SKYLAKE-H BGA 837 Pins

LPC BUS

SPI

P.50

P.6~13

DMI x4 gen 2

P.18~26

W25Q128FVSIQ

128Mb 4K sector

W25Q32FVSSIQ

32Mb 4K sector

Discrete TPM NPCT650JB2YX

(DDR4) Memory Bus

1.2V DDR4 2400/2667M Hz (Overclocking)

SATA Port 3 PCIE Port 15,16

SATA3.0

USB3.0

USB2.0

HD Audio

P.22

P.39

Audio Codec ALC3254

On I/O board

P.4

SATA/PCIE Repeater PS8558B

USB3 Port 3

USB2 Port 2

USB3 Port 4

USB2 Port 3

USB3 Port 5

USB2 Port 4

USB3 Port 1

USB2 Port 1

USB2 Port 11

USB2 Port 9

USB Port 10

On USH/B

Universal Jack

Int. Speaker

DDR4 ECC-SO-DIMM X4

P.44

USB 3.0 Repeater

PS8713B

USB Power Share SLGC55544CVTR

USB 3.0 Repeater

PS8713B

USB Power Share SLGC55544CVTR

USB 3.0 Repeater

PS8713B

USB Power Share SLGC55544CVTR

Digital Camera

Touch screen

LYNX(CV2) BRCM58100

SPI

P.4

P.14~17BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

SATA EXPRESS HDD

P.7

P.7 P.7

P.8

P.8 P.8

P.9

P.43

USB 3.0 Conn Right Side

USB Charger

USB 3.0 Conn Right Side

USB Charger

USB 3.0 Conn Right Side

USB Charger

USB 3.0 Conn Left Side

P.12

P.30

USB Charger

TDA8034HN

Smart Card

SPI

RFID/NFC

Fingerprint CONN

P.9P.9

P.12

On Display board

P.39

On I/O board

A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D

Title

Size Document Number Rev

Date: Sheet of

Block Diagram

LA-E311P

E

2 71Wednesday, November 23, 2016

1.0

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1

POWER STATES

Signal

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON OFF

S4 (Suspend to DISK) / M1 ON ON OFF

S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

SLP S3#

HIGH

LOW HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP

SLP S4#

HIGH HIGH HIGH

LOW

S5#

S4 STATE#

SLP M#

HIGH

ALWAYS PLANE

ON ON

RUN

CLOCKS

PLANE

ON ON ON

OFF

OFF OFF

OFF

PCH

PM TABLE

+PWR_SRC

+5V_ALW

C C

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

B B

A A

power plane

+3.3V_ALW

+3.3V_ALW2 +1.0V_VCCST

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+3.3V_RTC_LDO

+1.8V_ALW

+1.0V_PRIM

ON

Stack up

+3.3V_SUS

+1.2V_MEM

+2.5V_MEM

+5V_RUN

+3.3V_RUN

+1.5V_RUN +VCC_CORE

+0.675V_DDR_VTT

+3.3V_MXM

+5V_MXM

+MXM_PWR_SRC

ON ON

ON

OFF

OFFOFF

OFFON

OFF

(M-OFF)

+VCC_EDRAM

+VCC_EOPIO

+VCC_GTU

+VCC_GT

+1.0V_VCCSTG

+VCC_SA

ON

OFF

OFFOFF

USB3.0 DESTINATION

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Left Side JUSB1

M.2 Slot-2 (WWAN/LTE/HCA)

Right Side JUSB1

Right Side JUSB2

Right Side JUSB3

Docking

SATA

SATA 0

SATA 1

SATA 2

SATA 3

SATA 4

SATA 5

DESTINATION

2280 SSD

Dock ESATA

NA

SATAe HDD

M.2 Slot-2 (cache)

NA

USH

PCI EXPRESS

USB PORT# DESTINATION

1

Left Side JUSB1

2

Right Side JUSB1

3

Right Side JUSB2

4

Right Side JUSB3

5

Docking USB3.0

6

M.2 Slot-1 (BT)

7

Docking USB 2.0

M.2 Slot-2 (WWAN/LTE/HCA)8

9

Touch Screen

10

USH

11

Camera

12

NA

13

NA

14

NA

0

1

BIO

NA

DESTINATION

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5~8

Lane 9~12

Lane 13~14

Lane 15~16

Lane 17~18

NA

M.2 Slot-1 (WLAN)

MMI(Card reader)

10/100/1G LOM

TBT-Alpine Ridge

M.2 Slot-3(SSD 2280)

(Dock ESATA),NA(LANE reservsal)

SATA-Express HDD(LANE reservsal)

M.2 Slot-2(WWAN/LTE/Optane)

5

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

LA-E311P

3 71Wednesday, N ovember 23, 2016

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Docking

D D

ADAPTER

BATTERY

CHARGER

C C

SIO_SLP_S4#

RT8207 (PU200)

NVRAM_PWR_EN

B B

+V_DDR_REF

0.6V_DDR_VTT_ON

+1.2V_MEM

AOZ1336

+0.6V_DDR_VTT

(UZ21)

+3.3V_SSD1

AOZ1336

(UZ24)

4

+PWR_SRC

EN_INVPWR

3.3V_RUN_GFX_ON

IMVP_VR_ON

SIO_SLP_S3#

1.2V_SUS_PWRGD

IMVP_VR_ON

SIO_SLP_SUS#

FDC654P

(Q21)

SI4835DDY

(Q186)

NCP81205MNTXG

(PU1100)

NB681GD (PU1800)

NCP81210MNTWG

(PU1600)

TPS62134C

(PU500)

TPS51212

(PU800)

+3.3V_ALW

3.3V_WWAN_EN

+3.3V_WWAN

PCH_ALW_ON

AOZ1336

(UZ27)

+3.3V_ALW_PCH

3.3V_RUN_GFX_ON

EM5209VF

(UZ26)

+3.3V_MXM

SIO_SLP_LAN#

SIO_SLP_WLAN#

AUX_EN_WOWL

EM5209VF

(UZ25)

+3.3V_LAN

+3.3V_WLAN +LCDVDD

SYX198DQNC

(PU300)

EM5209VF

+3.3V_RUN

3

+BL_PWR_SRC

+MXM_PWR_SRC

+VCC_CORE

+VCC_EOPIO

+VCC_GTU

+VCC_EDRAM

RUN_ON

(UZ20)

ALWON

+VCC_GT

+VCC_IO

RUN_ON

+1.0V_PRIM

TPS51285B

(PU101)

ENVDD_PCH

G524B1T11U

MXM_ENVDD

(U33)

+VCC_SA

SIO_SLP_S0#

SIO_SLP_S3#

LCD_VCC_TEST_EN

SIO_SLP_S4#

+5V_ALW

SIO_SLP_SUS#

SY8032ABC

(PU900)

+1.8V_ALW

2

AOZ1336

(UZ23)

TPS22961

(UZ18)

SIO_SLP_S4#

SY8003DFC

(PU400)

+2.5V_MEM

RUN_ON

3.3V_RUN_GFX_ON

+1.0V_RUN

+1.0V_VCCSTG(UZ19)

+1.0V_VCCST

EM5209VF

(UZ20)

Left IO Board

USB_PWR_SHR_VBUS_EN

USB1_VBUS_EN

USB2_VBUS_EN

USB3_VBUS_EN

Right IO Board

+5V_RUN

EM5209VF

(UZ26)

SLGC55544CVTR

+1.0V_VCCSFR

(UI1)

(UI3)

(UI5)

1

+5V_HDD

+5V_MXM

+5V_USB_PWR1

+5V_USB_PWR2

+5V_USB_PWR3

RUN_ON

AOZ1336

(UZ22)

+1.8V_RUN

AOZ1336

(UZ31)

+1.2V_RUN

+3.3V_CAM_EN#

LP2301

(Q24)

+CAMERA_VDD

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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4

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Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Rail

LA-E311P

1

4 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

SMBUS Address [0x9a]

MEM_SMBCLK

AW44

BB43

MEM_SMBDATA

PCH

D D

1D

C C

KBC

AW42AW45

SML1_SMBDATA

SML1_SMBCLK

B6A5

1D

BB39

1A

1C1CB59

1E

AY44

B4

A3

A56

A50

B53

LAN_SMBCLK

LAN_SMBDATA

2.2K

DOCK_TNY_SMB_CLK

DOCK_TNY_SMB_DAT

CHARGER_PBAT_SMBCLK

CHARGER_PBAT_SMBDAT

USH_SMBCLK

USH_SMBDAT

+3.3V_ALW_PCH

2.2K

4

2.2K

+3.3V_ALW_PCH

+3.3V_LAN

+3.3V_ALW

2.2K

28

31

LOM

127

DOCKING

129

L2

K2

+3.3V_ALW

100 ohm

DMN66D0LDW

SMBUS Address [0xC8]

SMBUS Address

APR_EC: 0x48 SPR_EC: 0x70 MSLICE_EC: 0x72 USB: 0x59 AUDIO: 0x34 SLICE_BATTERY: 0x17 SLICE_CHARGER: 0x13

TYPE C connector

K7

TI PD

L7

AR Chip

TBT DP/B

7

6

12

11

5

6

B6

B7

BATTERY CONN

Charger

LYNX(CV2)

3

IE/BME

EC

TI PD

AR Chip

SMBUS Address [0x16]

SMBUS Address [0xa4]

2

253

254

253

254

253

254

253

254

53

51

DIMM1

DIMM2

DIMM3

DIMM4

XDP1

SMBUS Address [A0h] A0h --> 1010 0000

SMBUS Address [A4h] A4h --> 1010 0100

SMBUS Address [TBD]

1

SMBUS Address SMB_ADM1032: 0x98 SMB_DIAG_DUMP: 0x04 SMB_DIAG_DUMP2: 0x05 SMB_BLACKTOP: 0x60

JTHB1

2.2K

+3.3V_RUN

1

4

2.2K

LNG2DMTR

SMBUS Address [TBD]

MEC 5085

B B

4.7K

+3.3V_TP

B50

A47

B49

UPD_GPU_SMBCLK

B48

UPD_GPU_SMBDAT

I2C_1_SCL_EC

I2C_1_SDA_EC

1G

1H

A A

4.7K

2.2K

+3.3V_RUN

DMN66D0LDW

19

18

TP

SMBUS Address [0xFF]

@4.7K

+3.3V_MXM

@4.7K

70

68

MXM

4.7K

SMBUS Address [TBD]

+3.3V_TBT_SX

24

UPD

23

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SMBUS Bolck Diagram

LA-E311P

5 71Wednesday, November 23, 2016

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PEG_CRX _C_GTX_P[0..15]

PEG_CRX _C_GTX_N[0..15]

PEG_CTX _C_GRX_P[0..15]

SKYLAKE_HALO

E25

PEG_RXP[0]

D25

PEG_RXN[0]

E24

PEG_RXP[1]

F24

PEG_RXN[1]

E23

PEG_RXP[2]

D23

PEG_RXN[2]

E22

PEG_RXP[3]

F22

PEG_RXN[3]

E21

PEG_RXP[4]

D21

PEG_RXN[4]

E20

PEG_RXP[5]

F20

PEG_RXN[5]

E19

PEG_RXP[6]

D19

PEG_RXN[6]

E18

PEG_RXP[7]

F18

PEG_RXN[7]

D17

PEG_RXP[8]

E17

PEG_RXN[8]

F16

PEG_RXP[9]

E16

PEG_RXN[9]

D15

PEG_RXP[10]

E15

PEG_RXN[10]

F14

PEG_RXP[11]

E14

PEG_RXN[11]

D13

PEG_RXP[12]

E13

PEG_RXN[12]

F12

PEG_RXP[13]

E12

PEG_RXN[13]

D11

PEG_RXP[14]

E11

PEG_RXN[14]

F10

PEG_RXP[15]

E10

PEG_RXN[15]

G2

PEG_RCOMP

D8

DMI_RXP[0]

E8

DMI_RXN[0]

E6

DMI_RXP[1]

F6

DMI_RXN[1]

D5

DMI_RXP[2]

E5

DMI_RXN[2]

J8

DMI_RXP[3]

J9

DMI_RXN[3]

SKL-H_BG A1440

CPU1C

3 OF 14

3

D D

12

PEG_CRX _C_GTX_N15

PEG_CRX _C_GTX_N14

PEG_CRX _C_GTX_N13

PEG_CRX _C_GTX_N12

PEG_CRX _C_GTX_N11

PEG_CRX _C_GTX_P10 PEG_CRX _C_GTX_N10

PEG_CRX _C_GTX_P9 PEG_CRX _C_GTX_N9

5

PEG_CRX _C_GTX_P8 PEG_CRX _C_GTX_N8

PEG_CRX _C_GTX_P7 PEG_CRX _C_GTX_N7

PEG_CRX _C_GTX_P6 PEG_CRX _C_GTX_N6

PEG_CRX _C_GTX_P5 PEG_CRX _C_GTX_N5

PEG_CRX _C_GTX_N4

PEG_CRX _C_GTX_N3

PEG_CRX _C_GTX_N2

PEG_CRX _C_GTX_N1

PEG_CRX _C_GTX_P0 PEG_CRX _C_GTX_N0

+VCC_IO

12

RC224.9_040 2_1%

C C

B B

PEG_COM P

CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

A A

CC32 0.22U_0402_10V 6K

12

CC16 0.22U_0402_10V 6K

12

CC31 0.22U_0402_10V 6K

12

CC15 0.22U_0402_10V 6K

12

CC30 0.22U_0402_10V 6K

12

CC14 0.22U_0402_10V 6K

12

CC29 0.22U_0402_10V 6K

12

CC13 0.22U_0402_10V 6K

12

CC28 0.22U_0402_10V 6K

12

CC12 0.22U_0402_10V 6K

12

CC27 0.22U_0402_10V 6K

12

CC11 0.22U_0402_10V 6K

12

CC26 0.22U_0402_10V 6K

12

CC10 0.22U_0402_10V 6K

12

CC25 0.22U_0402_10V 6K

12

CC9 0.22U_04 02_10V6K

12

CC24 0.22U_0402_10V 6K

12

CC8 0.22U_04 02_10V6K

12

CC23 0.22U_0402_10V 6K

12

CC7 0.22U_04 02_10V6K

12

CC22 0.22U_0402_10V 6K

12

CC6 0.22U_04 02_10V6K

12

CC21 0.22U_0402_10V 6K

12

CC5 0.22U_04 02_10V6K

12

CC20 0.22U_0402_10V 6K

12

CC4 0.22U_04 02_10V6K

12

CC19 0.22U_0402_10V 6K

12

CC3 0.22U_04 02_10V6K

12

CC18 0.22U_0402_10V 6K

12

CC2 0.22U_04 02_10V6K

12

CC17 0.22U_0402_10V 6K

12

CC1 0.22U_04 02_10V6K

DMI_CRX_P TX_P0<20> DMI_CRX_P TX_N0<20>

DMI_CRX_P TX_P1<20> DMI_CRX_P TX_N1<20>

DMI_CRX_P TX_P2<20> DMI_CRX_P TX_N2<20>

DMI_CRX_P TX_P3<20> DMI_CRX_P TX_N3<20>

4

PEG_CRX _GTX_P15PEG_CRX _C_GTX_P15 PEG_CRX _GTX_N15

PEG_CRX _GTX_P14PEG_CRX _C_GTX_P14 PEG_CRX _GTX_N14

PEG_CRX _GTX_P13PEG_CRX _C_GTX_P13 PEG_CRX _GTX_N13

PEG_CRX _GTX_P12PEG_CRX _C_GTX_P12 PEG_CRX _GTX_N12

PEG_CRX _GTX_P11PEG_CRX _C_GTX_P11 PEG_CRX _GTX_N11

PEG_CRX _GTX_P10 PEG_CRX _GTX_N10

PEG_CRX _GTX_P9 PEG_CRX _GTX_N9

PEG_CRX _GTX_P8 PEG_CRX _GTX_N8

PEG_CRX _GTX_P7 PEG_CRX _GTX_N7

PEG_CRX _GTX_P6 PEG_CRX _GTX_N6

PEG_CRX _GTX_P5 PEG_CRX _GTX_N5

PEG_CRX _GTX_P4PEG_C RX_C_GTX_P4 PEG_CRX _GTX_N4

PEG_CRX _GTX_P3PEG_C RX_C_GTX_P3 PEG_CRX _GTX_N3

PEG_CRX _GTX_P2PEG_C RX_C_GTX_P2 PEG_CRX _GTX_N2

PEG_CRX _GTX_P1PEG_C RX_C_GTX_P1 PEG_CRX _GTX_N1

PEG_CRX _GTX_P0 PEG_CRX _GTX_N0

PEG_COM P

DMI_CRX_P TX_P0 DMI_CRX_P TX_N0

DMI_CRX_P TX_P1

DMI_CRX_P TX_P2 DMI_CRX_P TX_N2

DMI_CRX_P TX_P3 DMI_CTX_P RX_P3 DMI_CRX_P TX_N3 DMI_CTX_P RX_N3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Rev_1.0

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

PEG_CTX _GRX_P15

B25

PEG_CTX _GRX_N15

A25

PEG_CTX _GRX_P14

B24

PEG_CTX _GRX_N14

C24

PEG_CTX _GRX_P13

B23

PEG_CTX _GRX_N13

A23

PEG_CTX _GRX_P12

B22

PEG_CTX _GRX_N12

C22

PEG_CTX _GRX_P11

B21

PEG_CTX _GRX_N11

A21

PEG_CTX _GRX_P10

B20

PEG_CTX _GRX_N10

C20

PEG_CTX _GRX_P9 PEG_CTX _C_GRX_P9

B19 A19

PEG_CTX _GRX_P8

B18

PEG_CTX _GRX_N8

C18

PEG_CTX _GRX_P7

A17

PEG_CTX _GRX_N7

B17

PEG_CTX _GRX_P6

C16

PEG_CTX _GRX_N6

B16

PEG_CTX _GRX_P5 PEG_CTX _C_GRX_P5

A15 B15

PEG_CTX _GRX_P4

C14

PEG_CTX _GRX_N4

B14

PEG_CTX _GRX_P3 PEG_CTX _C_GRX_P3

A13

PEG_CTX _GRX_N3 PEG_CTX_C _GRX_N3

B13

PEG_CTX _GRX_P2

C12

PEG_CTX _GRX_N2

B12

PEG_CTX _GRX_P1

A11

PEG_CTX _GRX_N1

B11

PEG_CTX _GRX_P0

C10

PEG_CTX _GRX_N0

B10

B8 A8

C6 B6

B5 A5

D4 B4

DMI_CTX_P RX_P0 DMI_CTX_P RX_N0

DMI_CTX_P RX_P1 DMI_CTX_P RX_N1DMI_CRX_P TX_N1

DMI_CTX_P RX_P2 DMI_CTX_P RX_N2

2

PEG_CTX _C_GRX_N[0..15]

12

CC64 0.22U_0402_10V 6K

12

CC50 0.22U_0402_10V 6K

12

CC63 0.22U_0402_10V 6K

12

CC77 0.22U_0402_10V 6K

12

CC72 0.22U_0402_10V 6K

12

CC62 0.22U_0402_10V 6K

12

CC61 0.22U_0402_10V 6K

12

CC49 0.22U_0402_10V 6K

12

CC60 0.22U_0402_10V 6K

12

CC76 0.22U_0402_10V 6K

12

CC71 0.22U_0402_10V 6K

12

CC59 0.22U_0402_10V 6K

12

CC58 0.22U_0402_10V 6K

12

CC48 0.22U_0402_10V 6K

12

CC57 0.22U_0402_10V 6K

12

CC75 0.22U_0402_10V 6K

12

CC70 0.22U_0402_10V 6K

12

CC56 0.22U_0402_10V 6K

12

CC55 0.22U_0402_10V 6K

12

CC47 0.22U_0402_10V 6K

12

CC54 0.22U_0402_10V 6K

12

CC74 0.22U_0402_10V 6K

12

CC69 0.22U_0402_10V 6K

12

CC46 0.22U_0402_10V 6K

12

CC52 0.22U_0402_10V 6K

12

CC73 0.22U_0402_10V 6K

12

CC51 0.22U_0402_10V 6K

12

CC53 0.22U_0402_10V 6K

12

CC68 0.22U_0402_10V 6K

12

CC45 0.22U_0402_10V 6K

12

CC67 0.22U_0402_10V 6K

12

CC44 0.22U_0402_10V 6K

DMI_CTX_P RX_P0 <20> DMI_CTX_P RX_N0 <20>

DMI_CTX_P RX_P1 <20> DMI_CTX_P RX_N1 <20>

DMI_CTX_P RX_P2 <20> DMI_CTX_P RX_N2 <20>

DMI_CTX_P RX_P3 <20> DMI_CTX_P RX_N3 <20>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (1/8)

PEG_CRX _C_GTX_P[0..15] <18>

PEG_CRX _C_GTX_N[0..15] <18>

PEG_CTX _C_GRX_P[0..15] <18>

PEG_CTX _C_GRX_N[0..15] <18>

PEG_CTX _C_GRX_P15 PEG_CTX _C_GRX_N15

PEG_CTX _C_GRX_P14 PEG_CTX _C_GRX_N14

PEG_CTX _C_GRX_P13 PEG_CTX _C_GRX_N13

PEG_CTX _C_GRX_P12 PEG_CTX _C_GRX_N12

PEG_CTX _C_GRX_P11 PEG_CTX _C_GRX_N11

PEG_CTX _C_GRX_P10 PEG_CTX _C_GRX_N10

PEG_CTX _C_GRX_N9PEG_CTX _GRX_N9

PEG_CTX _C_GRX_P8 PEG_CTX _C_GRX_N8

PEG_CTX _C_GRX_P7 PEG_CTX _C_GRX_N7

PEG_CTX _C_GRX_P6 PEG_CTX _C_GRX_N6

PEG_CTX _C_GRX_N5PEG_CTX _GRX_N5

PEG_CTX _C_GRX_P4 PEG_CTX _C_GRX_N4

PEG_CTX _C_GRX_P2 PEG_CTX _C_GRX_N2

PEG_CTX _C_GRX_P1 PEG_CTX _C_GRX_N1

PEG_CTX _C_GRX_P0 PEG_CTX _C_GRX_N0

LA-E311P

1

1.0

6 71Wednesd ay, November 23, 201 6

1.0

Vinaﬁx.com

5

+1.0V_PRIM

D D

RC216 0_0603_1%@

1 2

+1.0V_PRIM_XDP

0.1U_0402_25V6

12

+1.0V_PRIM_XDP

0.1U_0402_25V6

@

12

CC37

@

CC33

Place near JXDP1

XDP@

PCH_RSMRST#_R H_VCCST_PWRGD_XDP

@

T191

PAD~D

SIO_PWRBTN#<23,48>

RESET_OUT#<23,48>

H_PROCHOT#

PCH_THERMTRIP#

PCH_JTAGX

VCCST_PWRGD

H_CATERR#

+1.0V_VCCST

56.2_0402_1%

12

RC155

220_0402_5%

12

RC156

SN74AHC1G08DCKR _SC70-5

5

CFG0

12

VR_SVID_DATA

CPU_VIDALERT#

RC327 0 _0402_5%@

UC5

PCH_SPI_D0<22,39>

+1.0V_PRIM_XDP

+VCC_IO

+1.0V_VCCSTG

C C

RC180 1K_0402_5%

+1.0V_VCCST

B B

VR_SVID_DATA<63,66>

VR_SVID_ALERT#<63,66>

A A

1 2

CPU_XDP_PREQ#

12

RC13851_0402_ 5% @

FIVR_EN_R

12

RC132150_0402_5%

12

RC3261K_ 0402_5%

12

RC1661K_ 0402_5% @

12

RC1641K_0402_5%

12

RC17249.9_0402_1% @

VR_SVID_DATA

VR_SVID_ALERT#

IMVP_VR_ON_EC<48>

SIO_SLP_S3#<11,23,39,46,48>

100_0402_5%

RC157

+3.3V_ALW

1

2

PCH_JTAG_TCK<23>

1 2

5

P

IN1

IN2

G

3

1 2

RC124

1K_0402_5%

1 2

RC217 0 _0402_5%@ RC126 1 K_0402_5%XDP@

1 2 1 2

RC128 0 _0402_5%XDP@

1 2

RC129 0 _0402_5%@

DDR_XDP_WAN_SMBDAT<14,15,16,17,23,43>

DDR_XDP_WAN_SMBCLK<14,15,16,17,23,43>

PCH_RSMRST#

PCH_RSMRST#<48>

ALW_PWRGD_3V_5V<53>

VR_SVID_CLK<63,66>

H_PROCHOT#<48,59,63,66>

DDR_PG_CTRL<14>

VCCST_PWRGD<48>

H_PWRGD<23> PLTRST_CPU#<19>

H_PM_SYNC<19> H_PM_DOWN<19> H_PECI<19,48>

PCH_THERMTRIP#<14,15,16,17,19,48>

IMVP_VR_ON

4

O

IMVP_VR_ON <57,58,63,66>

CPU_XDP_PREQ# CPU_XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_OBS0_R XDP_OBS1_R

CFG4 CFG5

CFG6 CFG7

SIO_PWRBTN#

FIVR_EN_R

SYS_PWROK_R

PCH_JTAG_TCK CPU_XDP_TCLK

PCH_CPU_BCLK_R_D<21> PCH_CPU_BCLK_R_D#<21>

PCH_CPU_PCIBCLK_R_D<21> PCH_CPU_PCIBCLK_R_D#<21>

CPU_24MHZ_R_D<21> CPU_24MHZ_R_D#<21>

VR_SVID_CLK

DDR_PG_CTRL

H_PWRGD PLTRST_CPU#

H_PECI

UC6

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSO P5

4

+1.0V_PRIM_XDP

XDP_PRSNT_PIN1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2 OBSDATA_A09OBSDATA_C0 OBSDATA_A111OBSDATA_C1

13

GND4 OBSDATA_A215OBSDATA_C2 OBSDATA_A317OBSDATA_C3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8 OBSDATA_B027OBSDATA_D0 OBSDATA_B129OBSDATA_D1

31

GND10 OBSDATA_B233OBSDATA_D2 OBSDATA_B335OBSDATA_D3

37

GND12 PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1 VCC_OBS_AB43VCC_OBS_CD

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

+3.3V_ALW

CC274

1 2

0.1U_0402_25V6K

UC4

5

SN74AHC1G08DCKR _SC70-5

1

P

IN1

4

O

2

IN2

G

3

PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D #

PCH_CPU_PCIBCLK_R_ D PCH_CPU_PCIBCLK_R_ D#

CPU_24MHZ_R_D CPU_24MHZ_R_D#

1 2

RC158 4 99_0402_1%

1 2

RC159 60.4_0 402_1%

1 2

RC168 2 0_0402_5%

1 2

RC169 0_0402_5%@

1 2 1 2

RC319 0 _0402_5%@ RC171 0 _0402_5%@

+3.3V_ALW

5

VCCST_PWRGD

4

Y

4

CPU XDP

XDP@

1 2

CFG3

GND1 OBSFN_C0 OBSFN_C1

GND3

GND5

GND7 OBSFN_D0 OBSFN_D1

GND9

GND11

GND13

ITPCLK#/HOOK5

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

CONN@SAMTE_BSH-030-01-L-D -A

1 2

RC154 0_0402_5%@

TD0

TDI

TMS

BH31 BH32 BH29 BR30

BT13

BT31 BP35 BM34 BP31 BT34

BR33

BM30

B31 A32

D35 C36

E31 D31

H13

J31

BN1

+1.0V_PRIM_XDP

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

CPU1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

PCH_XDP_CLK_DP PCH_XDP_CLK_DN

CPU_XDP_HOOK6 XDP_DBRESET#

CPU_XDP_TDO CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_PRS

12

SKYLAKE_HALO

RC121 1K_0402_5%

1 2

RC122 0_0402_5%@

PM_RSMRST#_AND PCH_RSMRST#_R

CPU_VIDALERT#

VR_SVID_DATA H_PROCHOT#_RH_PROCHOT#

VCCST_PWRGD_C PUVCC ST_PWRGD

H_PM_SYNC H_PM_DOWN_RH_PM_DOWN

H_THERMTRIP#PCH_THERM TRIP#

H_SKTOCC# SKL_CNL#

H_CATERR#

RC318 10K_0402_5%

5 OF 14

3

PCH_XDP_CLK_DP <21> PCH_XDP_CLK_DN <21>

1 2

RC144 0 _0402_5%XDP@

XDP_DBRESET# <23>

CPU_XDP_TRST# <25>

1 2

RC127 1 K_0402_5%XDP@

PCH_RSMRST#_R <23>

Rev_1.0

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

3

ITP_PMODE_CPU

PCH_SPI_D2_XDP

Place near JXDP1.41

BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

BR27 BT27 BM31 BT30

BT28 BL32 BP28 BR28

BP30 BL30 BP27

BT25

2

CPU_XDP_HOOK6

XDP_DBRESET#

PCH_SPI_D0

ITP_PMODE_CPU <23>

PCH_SPI_D2_XDP <22>

+3.3V_ALW

1.5K_0402_5%

XDP@

12

RC241

SIO_PWRBTN#

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG17 CFG16 CFG19 CFG18

XDP_OBS0 XDP_OBS1

CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCLK

CPU_XDP_TRST# CPU_XDP_PREQ# CPU_XDP_PRDY#

12

0.1U_0402_25V6

XDP@

12

CC269

CPU_XDP_TDO

CPU_XDP_TRST#

CPU_XDP_TCLK

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TCLK

CPU_XDP_PREQ#

CPU_XDP_PRDY#

8/22

1 2 1 2

RC312 0_04 02_5%@ RC313 0_04 02_5%@

PAD~D PAD~D PAD~D PAD~D

PAD~D PAD~D PAD~D

RC222

49.9_0402_1%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

XDP_OBS0_R XDP_OBS1_R

@

T184

@

T185

@

T180

@

T181

@

T179

@

T190

@

T189

RC307 0_0402_5%@

RC308 0_0402_5%@

RC309 0_0402_5%@

RC143 0_0402_5%@

RC315 0_0402_5%XDP@

RC314 0_0402_5%XDP@

RC6 2.2K_0 402_5%XDP@

RC316 3 K_0402_5%

RC133 1 .5K_0402_5%XDP@

1 2

8/24

1 2

2

12

+1.0V_PRIM_XDP

+3.3V_ALW_PCH

+1.0V_VCCSTG

RC13551_0402_5%

RC33051_0402_5% @

RC30651_0402_5%

PCH_JTAG_TMS <23>

PCH_JTAG_TDI <23>

PCH_JTAG_TDO <23>

PCH_JTAGX <23>

PCH_XDP_PREQ# <25>

PCH_XDP_PRDY# <25>

XDP_DBRESET#

RC143 for XDP debug

1

0.1U_0402_25V6

XDP@

CC35

12

SYS_PWROK_R

0.1U_0402_25V6

12

CC36@

Place near JXDP1.47

CFG0

CFG2

CFG4

CFG5

CFG6

CFG7

Title

Size Document Number Rev

Date: Sheet of

Stall reset sequence after PCU

12

PLL lock until de-asserted

RC321

@

1K_0402_5%

No Stall

Stall

12

PEG LANE REVERSAL

RC181 1K_0402_5%

*

12

RC322 1K_0402_5%

PCI Express* Bifurcation

12

RC323

@

1K_0402_5%

1x8, 2x4

Reserved

2x8

RC324

@

1K_0402_5%

1x16

PEG Training

(default) PEG Train immediately following RESET# de-assertion

PEG Wait for BIOS for training

Compal Electronics, Inc.

SKYLAKE-H (2/8)

LA-E311P

1

12

RC325

@

1K_0402_5%

NORMAL

LANE REVERSED

eDP enable

Disabled

Enabled

1

0

1

0

1

0

[6:5]

00

01

10

11

1

0

7 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

4

3

2

1

DDR_A_D[0..63]<14,15>

D D

C C

DDR_A_CB[0..7]<14,15>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_CB0 DDR_A_CB1 DDR_A_CB2 DDR_A_CB3 DDR_A_CB4 DDR_A_CB5 DDR_A_CB6 DDR_A_CB7

CPU1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

Interleave / Non-Interleaved

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKL-H_BGA1440

SKYLAKE_HALO

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT #

DDR CH - A

1 OF 14

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[2] DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR3L / LPDDR3 / DDR4

DDR0_MA[3] DDR0_MA[4]

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[0]

DDR0_DQSP[1] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[8]

DDR0_DQSN[8]

Rev_1.0

DDR0_PAR

DDR_A_CLK0 DDR_B_CLK#0

AG1

DDR_A_CLK#0

AG2

DDR_A_CLK#1 DDR_B_CLK1

AK1

DDR_A_CLK1

AK2

DDR_A_CLK2

AL3

DDR_A_CLK#2

AK3

DDR_A_CLK3

AL2

DDR_A_CLK#3

AL1

DDR_A_CKE0

AT1

DDR_A_CKE1

AT2

DDR_A_CKE2

AT3

DDR_A_CKE3

AT5

DDR_A_CS#0

AD5

DDR_A_CS#1

AE2

DDR_A_CS#2

AD2

DDR_A_CS#3

AE5

DDR_A_ODT0

AD3

DDR_A_ODT1

AE4

DDR_A_ODT2

AE1

DDR_A_ODT3

AD4

DDR_A_BA0

AH5

DDR_A_BA1

AH1

DDR_A_BG0

AU1

DDR_A_MA16

AH4

DDR_A_MA14

AG4

DDR_A_MA15

AD1

DDR_A_MA0

AH3

DDR_A_MA1

AP4

DDR_A_MA2

AN4

DDR_A_MA3

AP5

DDR_A_MA4

AP2

DDR_A_MA5

AP1

DDR_A_MA6

AP3

DDR_A_MA7

AN1

DDR_A_MA8

AN3

DDR_A_MA9

AT4

DDR_A_MA10

AH2

DDR_A_MA11

AN2

DDR_A_MA12

AU4

DDR_A_MA13

AE3

DDR_A_BG1

AU2

DDR_A_ACT#

AU3

DDR_A_PARITY

AG3

DDR_A_ALERT#

AU5

DDR_A_DQS#0

BR5

DDR_A_DQS#1

BL3

DDR_A_DQS#2

BG3

DDR_A_DQS#3

BD3

DDR_A_DQS4

AB3

DDR_A_DQS5

V3

DDR_A_DQS6

R3

DDR_A_DQS7

M3

DDR_A_DQS0

BP5

DDR_A_DQS1

BK3

DDR_A_DQS2

BF3

DDR_A_DQS3

BC3

DDR_A_DQS#4

AA3

DDR_A_DQS#5

U3

DDR_A_DQS#6

P3

DDR_A_DQS#7

L3

DDR_A_DQS8

AY3

DDR_A_DQS#8

BA3

DDR_A_CLK0 <15> DDR_A_CLK#0 <15> DDR_A_CLK#1 <15> DDR_A_CLK1 <15> DDR_A_CLK2 <14> DDR_A_CLK#2 <14> DDR_A_CLK3 <14> DDR_A_CLK#3 <14>

DDR_A_CKE0 <15> DDR_A_CKE1 <15> DDR_A_CKE2 <14> DDR_A_CKE3 <14>

DDR_A_CS#0 <15> DDR_A_CS#1 <15> DDR_A_CS#2 <14> DDR_A_CS#3 <14>

DDR_A_ODT0 <15> DDR_A_ODT1 <15> DDR_A_ODT2 <14> DDR_A_ODT3 <14>

DDR_A_BA0 <14,15> DDR_A_BA1 <14,15> DDR_A_BG0 <14,15>

DDR_A_MA16 < 14,15> DDR_A_MA14 < 14,15> DDR_A_MA15 < 14,15>

DDR_A_MA[0..13] <14,15>

DDR_A_BG1 <14,15> DDR_A_ACT# <14,15>

DDR_A_PARITY < 14,15> DDR_A_ALERT# <14,15>

DDR_A_DQS#[0..3] <14,15>

DDR_A_DQS[4..7] <14,15>

DDR_A_DQS[0..3] <14,15>

DDR_A_DQS#[4..7] <14,15>

DDR_A_DQS8 <14,15> DDR_A_DQS#8 <14,15>

DDR_B_D[0..63]<16,17>

DDR_B_CB[0..7]<16,17>

1 2 1 2

RD18 121_0402_1%

1 2

RD21 75_0402_1% RD22 100_0402_1%

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_CB0 DDR_B_CB1 DDR_B_CB2 DDR_B_CB3 DDR_B_CB4 DDR_B_CB5 DDR_B_CB6 DDR_B_CB7

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

CPU1B

Interleave / Non-Interleaved

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

SKYLAKE_HALO

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT #

DDR CH - B

2 OF 14

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR3L / LPDDR3 / DDR4

DDR1_MA[3] DDR1_MA[4]

DDR1_ALERT#

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

Rev_1.0

DDR1_PAR

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK0

DDR_B_CLK#1

DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1 DDR_B_CS#2 DDR_B_CS#3

DDR_B_ODT0 DDR_B_ODT1 DDR_B_ODT2 DDR_B_ODT3

DDR_B_MA16 DDR_B_MA14 DDR_B_MA15

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT#

DDR_B_PARITY DDR_B_ALERT#

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS8 DDR_B_DQS#8

DDR_B_CLK0 <17> DDR_B_CLK#0 <17> DDR_B_CLK#1 <17> DDR_B_CLK1 <17> DDR_B_CLK2 <16> DDR_B_CLK#2 <16> DDR_B_CLK3 <16> DDR_B_CLK#3 <16>

DDR_B_CKE0 <17> DDR_B_CKE1 <17> DDR_B_CKE2 <16> DDR_B_CKE3 <16>

DDR_B_CS#0 <17> DDR_B_CS#1 <17> DDR_B_CS#2 <16> DDR_B_CS#3 <16>

DDR_B_ODT0 <17> DDR_B_ODT1 <17> DDR_B_ODT2 <16> DDR_B_ODT3 <16>

DDR_B_MA16 <16,17> DDR_B_MA14 <16,17> DDR_B_MA15 <16,17>

DDR_B_BA0 <16,17> DDR_B_BA1 <16,17> DDR_B_BG0 <16,17>

DDR_B_BG1 <16,17> DDR_B_ACT# <16,17>

DDR_B_PARITY <16,17> DDR_B_ALERT# <16,17>

DDR_B_DQS8 <16,17> DDR_B_DQS#8 <16,17>

+DDR_VREF_CA

@

T199

PAD~D

+DDR_VREF_B_DQ

DDR_B_MA[0..13] <16,17>

DDR_B_DQS#[0..7] <16,17>

DDR_B_DQS[0..7] <16,17>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (3/8)

LA-E311P

8 71Wednesday, November 23, 2016

1

1.0

Vinaﬁx.com

5

CPU_DP1_P0<31> CPU_DP1_N0<31> CPU_DP1_P1<31>

Dock Port1

D D

TBT

C C

mDP/TBT

CPU_DP1_P2<31> CPU_DP1_N2<31> CPU_DP1_P3<31> CPU_DP1_N3<31>

CPU_DP1_AUXP<31> CPU_DP1_AUXN<31>

CPU_DP2_P0<34> CPU_DP2_N0<34> CPU_DP2_P1<34> CPU_DP2_N1<34> CPU_DP2_P2<34> CPU_DP2_N2<34> CPU_DP2_P3<34> CPU_DP2_N3<34>

CPU_DP2_AUXP<34> CPU_DP2_AUXN<34>

CPU_DP3_P0<33> CPU_DP3_N0<33> CPU_DP3_P1<33> CPU_DP3_N1<33> CPU_DP3_P2<33> CPU_DP3_N2<33> CPU_DP3_P3<33> CPU_DP3_N3<33>

CPU_DP3_AUXP<33> CPU_DP3_AUXN<33>

4

CPU_DP1_P0 CPU_DP1_N0 CPU_DP1_P1

CPU_DP1_P2 CPU_DP1_N2 CPU_DP1_P3 CPU_DP1_N3

CPU_DP1_AUXP CPU_DP1_AUXN

CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3

CPU_DP2_AUXP CPU_DP2_AUXN

CPU_DP3_P0 CPU_DP3_N0 CPU_DP3_P1 CPU_DP3_N1 CPU_DP3_P2 CPU_DP3_N2 CPU_DP3_P3 CPU_DP3_N3

CPU_DP3_AUXP CPU_DP3_AUXN

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKL-H_BGA1440

CPU1D

3

SKYLAKE_HALO

4 OF 14

Rev_1.0

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

2

D29 E29 F28 E28 B29 A29 B28 C28

C26 B26

A33

D37

G27 G25 G29

EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1CPU_DP1_N1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXP EDP_AUXN

@

T194

PAD~D

EDP_COMP

AUD_AZACPU_SCLK AUD_AZACPU_SDO AUD_AZACPU_SDI

AUD_AZACPU_SDI AUD_AZACPU_SDI_R

1 2

RC66 20_0402_5%

EDP_TXP0 <29> EDP_TXN0 <29> EDP_TXP1 <29> EDP_TXN1 <29>CPU_DP1_N1<31> EDP_TXN2 <29> EDP_TXP2 <29> EDP_TXN3 <29> EDP_TXP3 <29>

EDP_AUXP <29> EDP_AUXN <29>

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

EDP_COMP

AUD_AZACPU_SCLK <23> AUD_AZACPU_SDO <23>

AUD_AZACPU_SDI_R <23>

1

+VCC_IO

12

RC124.9_0402_1%

B B

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

SKYLAKE-H (4/8)

LA-E311P

9 71Wednesday, November 23, 2016

1

1.0

Vinaﬁx.com

5

D D

+VCC_EDRAM_FUSEPRG_ED2 +1.8V_RUN_EDRAM_ED2

1 2

RC226 100_0603_1%@

VCC_EDRAM_SENSE<57>

VSS_EDRAM_SENSE<57>

1 2 1 2

RC223 0_0603_5%@

C C

1 2 1 2

RC176 100_0603_1%@ RC224 0_0603_5%@

1 2

RC230 100_0603_1%@

1 2 1 2

RC227 49.9_0402_1%

1 2

RC228 49.9_0402_1% RC229 49.9_0402_1%

+VCC_EOPIO

+VCC_EOPIO_ED2

VCC_EOPIO_SENSE<58> VSS_EOPIO_SENSE<58>

+1.8V_RUN_EDRAM

+VCC_EDRAM_FUSEPRG

+1.8V_RUN_EDRAM_ED2

+VCC_EDRAM_FUSEPRG_ED2

CPU_ZVM#<57,58> CPU_MSM#<58>

4

+VCC_EDRAM

3.3A

+VCC_EDRAM_ED2

100_0603_1%~D

12

@

RC173

VCC_EDRAM_SENSE VSS_EDRAM_SENSE

VCC_EDRAM_SENSE_ED2 VSS_EDRAM_SENSE_ED2

3.2A

1 2

RC175 100_0603_1%@

VCC_EOPIO_SENSE_ED3 VSS_EOPIO_SENSE_ED3

CPU_ZVM#_ED2 CPU_MSM#_ED2

CPU_EOPIO_RCOMP EDRAM_OPIO_RCOMP EDRAM_OPIO_RCOMP_ED2

BK17 BK19

BM17 BN17

BK23 BK26 BK27

BM24

BM16

BM22

BP15 BR15

BP16 BR16

BN15 BM15

BP17 BN16

BM14

AW13

AU13 AY13

BR25 BP25

BJ17 BJ19 BJ20

BK20 BL16 BL17 BL18 BL19 BL20 BL21

BJ23 BJ26 BJ27

BL23 BL24 BL25 BL26 BL27 BL28

BL15

BL22

BT15

BT16

BL14

BJ35 BJ36

AT13

BT29

CPU1J

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_S ENSE VSSOPC_ SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO _SENSE VSSEOPI O_SENSE

RSVD RSVD

VCC_OPC_ 1P8 VCC_OPC_ 1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCO MP OPCE_RCO MP2

SKL-H_BGA1440

SKYLAKE_HALO

10 OF 14

Rev_1.0

3

T1PAD~D @ T2PAD~D @ T3PAD~D @ T4PAD~D @

T5PAD~D @ T6PAD~D @

T7PAD~D @

T9PAD~D @ T10PAD~D @ T11PAD~D @ T8PAD~D @

T14PAD~D @ T13PAD~D @ T15PAD~D @ T12PAD~D @

PCH_2_CPU_TRIGGER<25>

CPU_2_PCH_TRIGGER<25>

PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R

TP_SKL_F30 TP_SKL_E30

T18PAD~D @ T19PAD~D @

T21PAD~D @ T20PAD~D @

T23PAD~D @ T24PAD~D @ T22PAD~D @

TP_SKL_F30 TP_SKL_E30

2

CPU1K

D1

RSVD_TP

E1

RSVD_TP

E3

RSVD_TP

E2

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

RSVD

H24

RSVD

BN33

RSVD

BL34

RSVD

N29

RSVD

R14

RSVD

AE29

RSVD

AA14

RSVD

A36

RSVD

A37

RSVD

H23

PROC_TRIGIN

J23

PROC_TRIGOU T

F30

RSVD

E30

RSVD

B30

RSVD

C30

RSVD

G3

RSVD

J3

RSVD

BR35

RSVD

BR31

RSVD

BH30

RSVD

SKL-H_BGA1440

CPU_2_PCH_TRIGGER_RCPU_2_PCH_TRIGGER

1 2

RC177 30_0402_5%

1 2 1 2

RC178 0_0402_5%@ RC179 0_0402_5%@

SKYLAKE_HALO

11 OF 14

Rev_1.0

RSVD_TP RSVD_TP

RSVD RSVD

RSVD_TP RSVD_TP

RSVD RSVD

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

1

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18

VSS

BJ16 BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18

VSS

BJ34 BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

T26 PAD~D@ T25 PAD~D@

T28 PAD~D@ T27 PAD~D@

T29 PAD~D@ T30 PAD~D@

T31 PAD~D@ T32 PAD~D@

T34 PAD~D@ T33 PAD~D@

T36 PAD~D@ T35 PAD~D@

T37 PAD~D@ T38 PAD~D@

T39 PAD~D@T16PAD~D @ T40 PAD~D@T17PAD~D @

T42 PAD~D@RC174 100_0603_1%@ T41 PAD~D@ T44 PAD~D@

T43 PAD~D@ T45 PAD~D@ T46 PAD~D@ T47 PAD~D@ T48 PAD~D@ T49 PAD~D@

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (5/8)

LA-E311P

10 71Wednesday, November 23, 2016

1

1.0

Vinaﬁx.com

5

+VCC_GT +VCC_SA

D D

C C

B B

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ37 BJ38 BL36 BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

CPU1H

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

SKYLAKE_HALO

8 OF 14

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

+VCC_GT

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

+VCC_IO

+1.0V_VCCSTG +1.0V_VCCST

RC317 0_0402_5%@

1 2

4

SKYLAKE_HALO

CPU1I

J30

VCCSA

K29

VCCSA

K30

VCCSA

K31

VCCSA

K32

VCCSA

K33

VCCSA

K34

VCCSA

K35

VCCSA

L31

VCCSA

L32

VCCSA

L35

VCCSA

L36

VCCSA

L37

VCCSA

L38

VCCSA

M29

VCCSA

M30

VCCSA

M31

VCCSA

M32

VCCSA

M33

VCCSA

M34

VCCSA

M35

VCCSA

M36

VCCSA

AG12

VCCIO

G15

VCCIO

G17

VCCIO

G19

VCCIO

G21

VCCIO

H15

VCCIO

H16

VCCIO

H17

VCCIO

H19

VCCIO

H20

VCCIO

H21

VCCIO

H26

VCCIO

H27

VCCIO

J15

VCCIO

J16

VCCIO

J17

VCCIO

J19

VCCIO

J20

VCCIO

J21

VCCIO

J26

VCCIO

J27

VCCIO

SKL-H_BGA1440

9 OF 14

+VCC_VDDQ_CLK +1.2V_MEM

1 2

RC220 0_0402_5%@

Rev_1.0

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCPLL_O C VCCPLL_O C

VCCST

VCCSTG

VCCPLL VCCPLL

VCCSA_SE NSE VSSSA_S ENSE

VCCIO_SE NSE VSSIO_S ENSE

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12

BH13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

+1.2V_MEM

12A

+VCC_VDDQ_CLK

+VCC_SFR_OC

+1.0V_VCCST

+1.0V_VCCSTG

+1.0V_VCCSFR

VCC_SA_SENSE VSS_SA_SENSE

VCC_IO_SENSE VSS_IO_SENSE

3

VCC_SA_SENSE <63> VSS_SA_SENSE <63>

VCC_IO_SENSE <55> VSS_IO_SENSE < 55>

2

+1.2V_MEM

PDDG page19, if don`t support DS3, contact to VDDQ directly

+5V_ALW

0.1U_0402_10V7K

@

1U_0402_6.3V6K

1

12

CZ96

CZ97

2

SIO_SLP_S3#_UZ30

SIO_SLP_S3#<7,11,23, 39,46,48>

SIO_SLP_SUS#<48,60,61>

SIO_SLP_S4#<11,23,39,48,54,56>

RC332 0_0402_5%@

1 2

+3.3V_ALW

5

1

IN1

2

IN2

3

P

O

G

C1471

@

1 2

0.1U_0402_10V7K

4

UC7

SN74AHC1G08DCKR_SC70-5

RC302 0_0402_5%@

UZ30

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

12

6

VOUT

5

GND

+VCC_SFR_OC

0.1U_0402_10V7K

12

1

CZ95

VOUT

GND

+1.0V_VCCSTG

12

+1.0V_VCCSTG_C

6

5

@

PJP7 PAD-OPEN1x3m

9/8

1 2

CZ82 10U_0402_6.3V6M

+1.0V_PRIM

+5V_ALW

9/8

10U_0402_6.3V6M

0.1U_0402_10V7K

@

1

12

CZ90

CZ89

2

SIO_SLP_S4#<11,23,39,48,54,56>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

RC303 0_0402_5%@

1 2

2

+1.0V_VCCST source

UZ18

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A TR=12.5us@Vin=1.05V

+1.0V_VCCST_UZ18

6

VOUT

5

GND

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

PJP6

@

PAD-OPEN1x1m

9/8

12

CZ63 10U_0402_6.3V6M

Compal Electronics, Inc.

SKYLAKE-H (6/8)

+1.0V_VCCST +1.0V_VCCSFR

12

1 2

RC304 0_0603_5%@

LA-E311P

11 71W ednesday, November 23, 2016

1

1.0

+1.0V_VCCSTG source

+1.0V_PRIM

UZ19

1

VIN1

2

0.1U_0402_10V7K

@

CZ86

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A TR=12.5us@Vin=1.05V

4

+5V_ALW

10U_0402_6.3V6M

9/8

1

12

CZ88

2

+3.3V_ALW

C1421

@

1 2

0.1U_0402_10V7K

A A

SIO_SLP_S3#<7,11,23, 39,46,48>

5

RC331 0_0402_5%@

1 2

220P_0402_25V8J

SIO_SLP_S0#<23, 39>

CC273

@

5

1

P

IN1

4

O

2

IN2

G

UC1

RC320 0_0402_5%@

1 2

SN74AHC1G08DCKR_SC70-5

3

1

2

Vinaﬁx.com

5

PLACE CAP IN

+VCC_EOPIO

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC173

2

D D

+VCC_EDRAM

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC177

2

10U_0603_6.3V6M~D

1

CC182

2

C C

+1.2V_MEM

+1.2V_MEM DECOUPLING

10U_0603_6.3V6M~D

1

CC161

2

22U_0603_6.3V6M

B B

12

CC81

SOCKET EDGE TOP

+1.8V_RUN_EDRAM

10U_0603_6.3V6M~D

1

CC174

CC169

2

10U_0603_6.3V6M~D

CC170

10U_0603_6.3V6M~D

1

CC179

CC176

CC175

2

10U_0603_6.3V6M~D

1

CC180

CC184

CC181

2

10U_0603_6.3V6M~D

1

CC164

CC168

2

22U_0603_6.3V6M

12

CC83

CC82

10U_0603_6.3V6M~D

1

CC190

2

10U_0603_6.3V6M~D

1

CC178

2

10U_0603_6.3V6M~D

1

CC183

2

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC163

2

CC84

10U_0603_6.3V6M~D

CC166

+VCC_VDDQ_CLK +1.0V_VCCSTG

10U_0603_6.3V6M~D

9/8

1

CC185

2

+VCC_IO

PLACE CAP BACKSIDE

9/12

1

2

1

2

+1.0V_VCCST

10U_0603_6.3V6M~D

1

CC171

2

10U_0603_6.3V6M

1

CC188

CC189

2

1U_0402_6.3V6K

2

CC194

CC193

1

10U_0603_6.3V6M~D

1

CC165

CC172

2

10U_0402_6.3V6M

2

CC186

1

10U_0603_6.3V6M

CC187

10U_0603_6.3V6M~D

CC167

PLACE CAP BACKSIDE

+1.0V_VCCSFR +1.0V_VCCST

10U_0402_6.3V6M

2

CC195

1

+VCC_SA

10U_0603_6.3V6M

@

1

CC272

2

4

1U_0402_6.3V6K

CC192

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K

2

1

3

+VCC_SFR_OC +VCC_GT +VCC_GTU

SKYLAKE_HALO

AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37 AL38

AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

CPU1N

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

14 OF 14

1U_0402_6.3V6K

2

CC191

1

10U_0603_6.3V6M~D

1

CC197

CC198

2

1U_0402_6.3V6K

2

CC203

CC204

1

1U_0402_6.3V6K

2

CC210

CC209

1

10U_0603_6.3V6M~D

1

CC201

CC196

2

22U_0603_6.3V6M

12

CC213

CC205

PLACE CAP SIDE

10U_0603_6.3V6M~D

1

CC199

CC200

CC202

2

22U_0603_6.3V6M

12

CC211

CC208

CC212

Rev_1.0

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENS E

VSSGTX_S ENSE

VSSGT_SE NSE

VCCGTX_SEN SE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

AH38 AH35 AH37 AH36

VCCGT_SENSE VSSGTX_SENSE VSSGT_SENSE VCCGTX_SENSE

2

VCCGT_SENSE <63> VSSGTX_SENSE <66> VSSGT_SENSE <63> VCCGTX_SENSE <66>

1

+VCC_CORE +VCC_CORE

SKYLAKE_HALO

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38

K13 K14 L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

CPU1G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

7 OF 14

Rev_1.0

VCC_SENS E VSS_SEN SE

V32

VCC

V33

VCC

V34

VCC

V35

VCC

V36

VCC

V37

VCC

V38

VCC

W13

VCC

W14

VCC

W29

VCC

W30

VCC

W31

VCC

W32

VCC

W35

VCC

W36

VCC

W37

VCC

W38

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

Y36

VCC

L14

VCC

P29

VCC

P30

VCC

P31

VCC

P32

VCC

P33

VCC

P34

VCC

P35

VCC

P36

VCC

R13

VCC

R31

VCC

R32

VCC

R33

VCC

R34

VCC

R35

VCC

R36

VCC

R37

VCC

R38

VCC

T29

VCC

T30

VCC

T31

VCC

T32

VCC

T35

VCC

T36

VCC

T37

VCC

T38

VCC

U29

VCC

U30

VCC

U31

VCC

U32

VCC

U33

VCC

U34

VCC

U35

VCC

U36

VCC

V13

VCC

V14

VCC

V31

VCC

P14

VCC

AG37 AG38

VCC_SENSE VSS_SENSE

VCC_SENSE <63> VSS_SENSE <63>

1 2

RC221 49.9_0402_1%@

A A

VCC_SENSEVSS_SENSE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (7/8)

LA-E311P

12 71W ednesday, November 23, 2016

1

1.0

Vinaﬁx.com

5

4

3

2

1

SKYLAKE_HALO

CPU1M

BB4

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AV38

AV37

AU34

AU33

AU12

AU11

AU10

AT30

AT29

AR38

AR37

AR14

AR13

AP34

AP33

AP12

AP11

AP10

AN30

AN29

AN12

AM38

AM37

AM12

AL34

AL33

AL14

AL12

AL10

BB3 BB2 BB1

BA9 BA8 BA7 BA6

B9

AW5 AW4 AW3 AW2 AW1

AU9 AU8 AU7 AU6

AT6

AR5 AR4 AR3 AR2 AR1

AP9 AP8

AN6 AN5

AM5 AM4 AM3 AM2 AM1

AL9 AL8 AL7 AL4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

13 OF 14

SKYLAKE_HALO

CPU1F

Y38

VSS

Y37

D D

C C

B B

Y14 Y13 Y11 Y10

Y9 Y8

Y7 W34 W33 W12

W5 W4 W3 W2

W1 V30 V29 V12

V6 U38 U37

U6 T34 T33 T14 T13 T12 T11 T10

T9

T8

T7

T5

T4

T3

T2

T1 R30 R29 R12 P38 P37 P12

P6 N34 N33 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

M14 M13 M12

M6 L34 L33 L30 L29 K38 K11 K10

K9 K8 K7 K5 K4 K3 K2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

6 OF 14

Rev_1.0

NCTFVSS

K1

VSS

J36

VSS

J33

VSS

J32

VSS

J25

VSS

J22

VSS

J18

VSS

J10

VSS

J7

VSS

J4

VSS

H35

VSS

H32

VSS

H25

VSS

H22

VSS

H18

VSS

H12

VSS

H11

VSS

G28

VSS

G26

VSS

G24

VSS

G23

VSS

G22

VSS

G20

VSS

G18

VSS

G16

VSS

G14

VSS

G12

VSS

G10

VSS

G9

VSS

G8

VSS

G6

VSS

G5

VSS

G4

VSS

F36

VSS

F31

VSS

F29

VSS

F27

VSS

F25

VSS

F23

VSS

F21

VSS

F19

VSS

F17

VSS

F15

VSS

F13

VSS

F11

VSS

F9

VSS

F8

VSS

F5

VSS

F4

VSS

F3

VSS

F2

VSS

E38

VSS

E35

VSS

E34

VSS

E9

VSS

E4

VSS

D33

VSS

D30

VSS

D28

VSS

D26

VSS

D24

VSS

D22

VSS

D20

VSS

D18

VSS

D16

VSS

D14

VSS

D12

VSS

D10

VSS

D9

VSS

D6

VSS

D3

VSS

C37

VSS

C31

VSS

C29

VSS

C27

VSS

D38

Rev_1.0

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30

VSS

AK29

VSS

AK4

VSS

AJ38

VSS

AJ37

VSS

AJ6

VSS

AJ5

VSS

AJ4

VSS

AJ3

VSS

AJ2

VSS

AJ1

VSS

AH34

VSS

AH33

VSS

AH12

VSS

AH6

VSS

AG30

VSS

AG29

VSS

AG11

VSS

AG10

VSS

AG8

VSS

AG7

VSS

AG6

VSS

AF14

VSS

AF13

VSS

AF12

VSS

AF4

VSS

AF3

VSS

AF2

VSS

AF1

VSS

AE34

VSS

AE33

VSS

AE6

VSS

AD30

VSS

AD29

VSS

AD12

VSS

AD11

VSS

AD10

VSS

AD9

VSS

AD8

VSS

AD7

VSS

AD6

VSS

AC38

VSS

AC37

VSS

AC12

VSS

AC6

VSS

AC5

VSS

AC4

VSS

AC3

VSS

AC2

VSS

AC1

VSS

AB34

VSS

AB33

VSS

AB6

VSS

AA30

VSS

AA29

VSS

AA12

VSS

A30

VSS

A28

VSS

A26

VSS

A24

VSS

A22

VSS

A20

VSS

A18

VSS

A16

VSS

A14

VSS

A12

VSS

A10

VSS

A9

VSS

A6

VSS

B37 B3 A34 A4 A3

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BL29 BK29 BK15 BK14

BH14 BH12

BG38 BG13 BG12

BF33 BF12 BE29

BC34 BC12 BB12

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BJ32 BJ31 BJ25 BJ22

C17 C13

C9

BT9 BT5

BR7

BP7

BN9 BN7 BN4 BN2

BM9 BM6 BM2

BH9 BH8 BH5 BH4 BH1

BE6 BD9

CPU1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

SKYLAKE_HALO

12 OF 14

Rev_1.0

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

C25

VSS

C23

VSS

C21

VSS

C19

VSS

C15

VSS

C11

VSS

C8

VSS

C5

VSS

BM29

VSS

BM25

VSS

BM18

VSS

BM11

VSS

BM8

VSS

BM7

VSS

BM5

VSS

BM3

VSS

BL38

VSS

BL35

VSS

BL13

VSS

BL6

VSS

BK25

VSS

BK22

VSS

BK13

VSS

BK6

VSS

BJ30

VSS

BJ29

VSS

BJ15

VSS

BJ12

VSS

BH11

VSS

BH10

VSS

BH7

VSS

BH6

VSS

BH3

VSS

BH2

VSS

BG37

VSS

BG14

VSS

BG6

VSS

BF34

VSS

BF6

VSS

BE30

VSS

BE5

VSS

BE4

VSS

BE3

VSS

BE2

VSS

BE1

VSS

BD38

VSS

BD37

VSS

BD12

VSS

BD11

VSS

BD10

VSS

BD8

VSS

BD7

VSS

BD6

VSS

BC33

VSS

BC14

VSS

BC13

VSS

BC6

VSS

BB30

VSS

BB29

VSS

BB6

VSS

BB5

VSS

C2 BT36 BT35 BT4 BT3 BR38

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

SKYLAKE-H (8/8)

LA-E311P

1

1.0

13 71W ednesday, November 23, 2016

1.0

Vinaﬁx.com

5

All VREF traces should have 10 mil trace width

D D

C C

B B

*

A A

DDR_A_DQS#[0..7]<8,15>

DDR_A_DQS[0..7]<8,15>

DDR_A_D[0..63]<8,15>

DDR_A_MA[0..13]<8,15 >

+1.2V_MEM

DIMM Select

SA0 SA1

0

DIMM4

DIMM1

1100

1

DIMM3

+2.5V_MEM

1U_0402_6.3V6K

1

CD3

CD2

2

10U_0603_6.3V6M

CD15

CD89

1

2

1U_0402_6.3V6K

1

CD4

CD5

2

Layout Note: Place near JDIMM1.258

+0.6V_DDR_VTT

10U_0603_6.3V6M

CD98

1

2

SA2

0DIMM2

0

1

0

10U_0603_6.3V6M

1U_0402_6.3V6K

1

2

CD7

CD9

CD6

1U_0402_6.3V6K

12

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1

CD17

2

RD17

@

0_0402_5%

RD30

@

0_0402_5%

CD8

1

2

1

2

10U_0603_6.3V6M

CD12

1U_0402_6.3V6K

CD94

+3.3V_RUN

1

2

1

2

12

10U_0603_6.3V6M

CD13

1U_0402_6.3V6K

CD96

RD8

@

0_0402_5%

DIMM1_SA0 DIMM1_SA1 DIMM1_SA2

RD28

@

0_0402_5%

10U_0603_6.3V6M

1

CD90

1

+

2

1U_0402_6.3V6K

1

CD97

2

+V_DDR_REFCA_A

10U_0603_6.3V6M

CD11

CD10

1

2

1U_0402_6.3V6K

1

CD93

CD95

2

1U_0402_6.3V6K

CD19

+3.3V_RUN+3.3V_RUN

12

RD13

@

0_0402_5%

12

RD29

@

0_0402_5%

330U_2V_M

CD14

0.1U_0402_10V6K

1

2

+3.3V_RUN

2.2U_0402_6.3V6M

1

CD76

2

12

RD57

@

0_0603_5%

+3.3V_RUN_DIMM1

0.1U_0402_10V6K

1

CD21

2

4

DDR_A_CB0<8,15>

DDR_A_CB5<8,15>

DDR_A_DQS#8<8,15> DDR_A_DQS8<8,15>

DDR_A_CB3<8,15>

DDR_A_CB2<8,15>

DDR_A_CKE2<8>

DDR_A_BG1<8,15> DDR_A_BG0<8,15>

DDR_A_CLK2<8> DDR_A_CLK#2<8>

DDR_A_PARITY<8,15>

DDR_A_BA1<8,15>

DDR_A_CS#2<8>

DDR_A_MA14<8,15>

DDR_A_ODT2<8>

DDR_A_CS#3<8>

DDR_A_ODT3<8>

@

CD75

2.2U_0402_6.3V6M

@

1

CD22

2

+2.5V_MEM

JDIMM1 STD Type H=9.2

JDIMM1

1

DDR_A_D4

DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D18

DDR_A_D29

DDR_A_D28

DDR_A_D27

DDR_A_D30

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE2

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK2 DDR_A_CLK#2

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#2 DDR_A_MA14 DDR_A_MA16

DDR_A_ODT2 DDR_A_CS#3

DDR_A_ODT3

T51PAD~D @

DDR_A_D33

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_D62

DDR_A_D58

+3.3V_RUN_DIMM1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_80888-6021 CONN@

3

VSS11

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

DQS3_c

VSS38

VSS40

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

VSS56

VSS58

DM4_n/DBI4_n

VSS59

VSS61

VSS63

VSS65

VSS67

DQS5_c

DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

DM6_n/DBI6_n

VSS79

VSS81

VSS83

VSS85

VSS87

DQS7_c

DQS7_t

VSS90

VSS92

VSS94

2

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD2

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

A0

BA0

A13

SA2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA SA0

VTT

SA1

GND2

DDR_A_D1

4 6

DDR_A_D5

8 10 12 14

DDR_A_D6

16 18

DDR_A_D2

20 22

DDR_A_D9

24 26

DDR_A_D8

28 30

DDR_A_DQS#1

32

DDR_A_DQS1

34 36

DDR_A_D10

38 40

DDR_A_D11

42 44

DDR_A_D16

46 48

DDR_A_D17

50 52 54 56

DDR_A_D19

58 60

DDR_A_D23

62 64

DDR_A_D24

66 68

DDR_A_D25

70 72

DDR_A_DQS#3

74

DDR_A_DQS3

76 78

DDR_A_D26

80 82

DDR_A_D31

84 86

DDR_A_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_A_CB4

DDR_A_CB7

DDR_A_CB6

DDR_A_DRAMRST# DDR_A_CKE3

DDR_A_ACT# DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM1_EVENT#

DDR_A_CLK3 DDR_A_CLK#3

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0

DDR_A_MA15 DDR_A_MA13

DIMM1_SA2

DDR_A_D36

DDR_A_D32

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D59

DDR_A_D63

DIMM1_SA0

DIMM1_SA1

DDR_A_CB1 <8,15>

DDR_A_CB4 <8,15>

DDR_A_CB7 <8,15>

DDR_A_CB6 <8,15>

1 2

CD92 0 .1U_0402_10V6K@

DDR_A_CKE3 <8 >

DDR_A_ACT# <8,15> DDR_A_ALERT# <8,15>

DDR_A_CLK3 <8> DDR_A_CLK#3 <8>

DDR_A_BA0 <8,15> DDR_A_MA16 <8,15>

DDR_A_MA15 <8,15>

T50 PAD~D@

+V_DDR_REFCA_A

DDR_XDP_WAN_SMBDAT <7,15,16,17,23,43>DDR_XDP_WAN_SMBCLK<7,15,16,17,23,43>

+0.6V_DDR_VTT

+V_DDR_REFCA_A

CPU

+1.2V_MEM

12

0.1U_0402_10V6K

1

2

+DDR_VREF_CA +V_DDR_REFCA_B

1

2

12

DDR_PG_CTRL<7>

STD

JDIMM1

D

A

JDIMM2

STD REV

RD7 470_0402_1%

1 2

RD6 0_0402 _5%@

1 2

RD15 0_0402_ 5%@

@

CD16

PCH_THERMTRIP#JDIMM1_EVENT#

1 2

RD3 1K_0402_ 5%@

+V_DDR_REFCA_B

1 2

RD45 2_0402_1%@

+V_DDR_REFCA_A

1 2

RD23 2_0402_1%

0.022U_0402_16V7K

CD127

24.9_0402_1% RD16

UD1

1

NC

VCC

2

A

Y

3

GND

74AUP1G07GW_TSSOP5

JDIMM3

JDIMM4

+3.3V_RUN

5

4

STD

Top Side

C B

Bottom Side

DDR_A_DRAMRST# DDR_B_DRAMRST#

PCH_THERMTRIP# <7,15,16,17,19,48>

0.1U_0402_10V6K

1

2

330K_0402_5%

12

RD61

+1.2V_MEM

CD144@ 0.1U_0402_25V6

0.6V_DDR_VTT_ON

1

DDR_A_DRAMRST# <15>DDR4_DRAMRST#_PCH<23> DDR_B_DRAMRST# <16,17>

+1.2V_MEM

1K_0402_5%

12

RD9

@

1K_0402_5%

12

CD128

RD10

1 2

0.6V_DDR_VTT_ON <54>

0.1U_0402_10V6K

@

CD129

1

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

DDRIII-SODIMM SLOT1

Size Document Number Rev

Date: Sheet of

LA-E311P

1

14 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

DDR_A_DQS#[0..7]<8,14>

DDR_A_DQS[0..7]<8,14>

DDR_A_D[0..63]<8,14>

D D

C C

B B

DIMM2

*

DIMM4

DIMM1 1

DIMM3

A A

DDR_A_MA[0..13]<8,14 >

+2.5V_MEM

1

2

+1.2V_MEM

1

2

1

2

Layout Note: Place near JDIMM2.258

DIMM Select

SA0 SA1

0

0 1

0

1 1

5

1U_0402_6.3V6K

CD33

10U_0603_6.3V6M

CD91

1U_0402_6.3V6K

CD20

+0.6V_DDR_VTT

SA2

0

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD35

CD38

2

10U_0603_6.3V6M

CD18

CD31

1

2

1U_0402_6.3V6K

1

CD24

CD23

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD105

1

CD36

2

12

RD26

@

0_0402_5%

12

RD35

@

0_0402_5%

10U_0603_6.3V6M

CD37

CD25 change to SGA20331E10

10U_0603_6.3V6M

CD27

CD32

CD28

1

2

1U_0402_6.3V6K

1

CD103

CD100

CD101

2

1U_0402_6.3V6K

1

CD30

2

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

@

RD20

@

0_0402_5%

DIMM2_SA0 DIMM2_SA1 DIMM2_SA2

12

RD36

@

0_0402_5%

10U_0603_6.3V6M

CD34

1

2

1U_0402_6.3V6K

1

CD102

2

+V_DDR_REFCA_A

RD19

RD31

4

DDR_A_D1

DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6

DDR_A_D2

DDR_A_D9

DDR_A_D8

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D19

DDR_A_D23

DDR_A_D24

DDR_A_BA1<8,14>

DDR_A_CS#0<8>

DDR_A_MA14<8,14>

DDR_A_CS#1<8>

+2.5V_MEM

DDR_A_D25

DDR_A_D26

DDR_A_D31

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#0 DDR_A_MA14

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

T53PAD~D @

DDR_A_D36

DDR_A_D32

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_D59

DDR_A_D63

+3.3V_RUN_DIMM2

330U_D2_2V_Y

@

1

CD25

CD99

+

2

CD104

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD77

CD78

2

+3.3V_RUN

12

RD58

@

0_0603_5%

+3.3V_RUN_DIMM2

0.1U_0402_10V6K

1

CD29

2

4

DDR_A_CB0<8,14>

DDR_A_CB5<8,14>

DDR_A_DQS#8<8,14> DDR_A_DQS8<8,14>

DDR_A_CB3<8,14>

DDR_A_CB2<8,14>

DDR_A_CKE0<8>

DDR_A_BG1<8,14> DDR_A_BG0<8,14>

DDR_A_CLK0<8> DDR_A_CLK#0<8>

DDR_A_PARITY<8,14>

DDR_A_ODT0<8>

DDR_A_ODT1<8>

2.2U_0402_6.3V6M

@

1

CD26

2

3

JDIMM2 STD Type H=4

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0106-P005A CONN@

3

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15 DQS1_c DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35 DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42 CB4/NC

VSS44 CB0/NC

VSS46

VSS47 CB6/NC

VSS49 CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

RAS_n/A16

VDD16

CAS_n/A15

A13

VDD18

C0/CS2_n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0

VTT

SA1

GND2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

+1.2V_MEM+1.2V_MEM

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_A_D4

DDR_A_D0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_D22

DDR_A_D18

DDR_A_D29

DDR_A_D28

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D27

DDR_A_D30

DDR_A_CB1

DDR_A_CB4

DDR_A_CB7

DDR_A_CB6

DDR_A_DRAMRST# DDR_A_CKE1

DDR_A_ACT# DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM2_EVENT#

DDR_A_CLK1 DDR_A_CLK#1

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0 DDR_A_MA16

DDR_A_MA15 DDR_A_MA13

DIMM2_SA2

DDR_A_D33

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62

DDR_A_D58

DIMM2_SA0

DIMM2_SA1

DDR_A_CB1 <8,14>

DDR_A_CB4 <8,14>

DDR_A_CB7 <8,14>

DDR_A_CB6 <8,14>

1 2

CD122 0.1U_0402_10V6K@

DDR_A_CKE1 <8 >

DDR_A_ACT# <8,14> DDR_A_ALERT# <8,14>

DDR_A_CLK1 <8> DDR_A_CLK#1 <8>

DDR_A_BA0 <8,14> DDR_A_MA16 <8,14>

DDR_A_MA15 <8,14>

T52 PAD~D@

+V_DDR_REFCA_A

DDR_XDP_WAN_SMBDAT <7,14,16,17,23,43>DDR_XDP_WAN_SMBCLK<7,14,16,17,23,43>

+0.6V_DDR_VTT

CPU

+V_DDR_REFCA_A

A

JDIMM2

RD4 1K_0402_ 5%@

JDIMM1

DDR_A_DRAMRST#

1 2

Top Side

D

Bottom Side

PCH_THERMTRIP#JDIMM2_EVENT#

JDIMM3

B

JDIMM4

1

C

DDR_A_DRAMRST# <14>

PCH_THERMTRIP# <7,14,16,17,19,48>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDRIII-SODIMM SLOT2

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

LA-E311P

1

15 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

DDR_B_DQS#[0..7]<8,17>

DDR_B_DQS[0..7]<8,17>

DDR_B_D[0..63]<8,17>

DDR_B_MA[0..13]<8,17 >

D D

+2.5V_MEM

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD51

CD53

CD55

2

10U_0603_6.3V6M

CD106

1

2

1U_0402_6.3V6K

1

CD40

2

+0.6V_DDR_VTT

SA2

0

CD56

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1

2

RD38

@

0_0402_5%

RD40

@

0_0402_5%

10U_0603_6.3V6M

CD45

CD46

CD50

1

2

1U_0402_6.3V6K

1

CD111

CD108

CD109

2

+V_DDR_REFCA_B

1U_0402_6.3V6K

CD48

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD37

@

0_0402_5%

12

RD42

@

0_0402_5%

10U_0603_6.3V6M

CD39

CD49

1

2

1U_0402_6.3V6K

1

CD41

CD42

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CD113

1

CD54

2

12

2

+1.2V_MEM

1

2

C C

1

2

Layout Note: Place near JDIMM3.258

B B

DIMM Select

SA0 SA1

0

0 1

1 1

5

0

DIMM2

DIMM4

DIMM1 1

DIMM3

*

A A

CD52

1

2

1

CD110

2

RD27

@

0_0402_5%

DIMM3_SA0 DIMM3_SA1 DIMM3_SA2

RD39

@

0_0402_5%

4

JDIMM3 STD Type H=5.2

DDR_B_D4

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6

DDR_B_D3

DDR_B_D10

DDR_B_D9

DDR_B_D12

DDR_B_D13

DDR_B_D18

DDR_B_D22

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D20

DDR_B_D25

DDR_B_CB4<8,17>

DDR_B_CB2<8,17>

DDR_B_DQS#8<8,17> DDR_B_DQS8<8,17>

DDR_B_CB7<8,17>

DDR_B_CB5<8,17>

DDR_B_BG1<8,17> DDR_B_BG0<8,17>

DDR_B_CLK2<8> DDR_B_CLK#2<8>

DDR_B_PARITY<8,17>

DDR_B_BA1<8,17>

DDR_B_CS#2<8>

DDR_B_MA14<8,17>

DDR_B_ODT2<8>

DDR_B_CS#3<8>

DDR_B_ODT3<8>

+2.5V_MEM

DDR_B_D30

DDR_B_D29

DDR_B_D31

DDR_B_CB2

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CB5

DDR_B_CKE2

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK2 DDR_B_CLK#2

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS#2 DDR_B_MA14

DDR_B_ODT2 DDR_B_CS#3

DDR_B_ODT3

T55PAD~D @

DDR_B_D35

DDR_B_D34

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_D56

DDR_B_D60

+3.3V_RUN_DIMM3

DDR_B_CB4

DDR_B_CB7

10U_0603_6.3V6M

330U_2V_M

1

CD43

CD107

+

2

1U_0402_6.3V6K

CD112

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD80

CD79

2

+3.3V_RUN

12

@

0_0603_5%

+3.3V_RUN_DIMM3

0.1U_0402_10V6K

1

2

4

DDR_B_CKE2<8>

RD59

2.2U_0402_6.3V6M

@

1

CD47

CD44

2

3

JDIMM3

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_80888-2021 CONN@

3

2

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

RAS_n/A16

VDD16

CAS_n/A15

A13

VDD18

C0/CS2_n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0 VTT SA1

GND2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DDR_B_D5

4 6

DDR_B_D0

8 10 12 14

DDR_B_D2

16 18

DDR_B_D7

20 22

DDR_B_D8

24 26

DDR_B_D14

28 30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36

DDR_B_D11

38 40

DDR_B_D15

42 44

DDR_B_D17

46 48

DDR_B_D16

50 52 54 56

DDR_B_D23

58 60

DDR_B_D21

62 64

DDR_B_D28

66 68

DDR_B_D27

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D26

80 82

DDR_B_D24

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRAMRST# DDR_B_CKE3

DDR_B_ACT# DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM3_EVENT#

DDR_B_CLK3 DDR_B_CLK#3

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DIMM3_SA2

DDR_B_D38

DDR_B_D39

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D58

DDR_B_D63

DIMM3_SA0

DIMM3_SA1

DDR_B_CB1 <8,17>

DDR_B_CB3 <8,17>

DDR_B_CB6 <8,17>

DDR_B_CB0 <8,17>

1 2

CD123 0.1U_0402_10V6K@

DDR_B_CKE3 <8 >

DDR_B_ACT# <8,17> DDR_B_ALERT# <8,17>

DDR_B_CLK3 <8> DDR_B_CLK#3 <8>

DDR_B_BA0 <8,17> DDR_B_MA16 <8,17>

DDR_B_MA15 <8,17>

T54 PAD~D@

+V_DDR_REFCA_B

DDR_XDP_WAN_SMBDAT <7,14,15,17,23,43>DDR_XDP_WAN_SMBCLK<7,14,15,17,23,43>

+0.6V_DDR_VTT

+V_DDR_REFCA_B

2

Top Side

A

JDIMM2

RD5 1K_0402_ 5%@

RD41 2_0402_1%

0.022U_0402_16V7K

1

CD136

2

24.9_0402_1%

12

RD34

1 2

RD11 0_0402_5%@

JDIMM1

D

Bottom Side

DDR_B_DRAMRST#

1 2

1

2

CPU

+DDR_VREF_B_DQ

+DIMM_DQ_R_VREF_B +V_DDR_REFCA_B

DELL CONFIDENTIAL/PROPRIETARY

Title

DDRIII-SODIMM SLOT3

Size Document Number Rev

Date: Sheet of

1

JDIMM3

C B

JDIMM4

DDR_B_DRAMRST# <14,17>

PCH_THERMTRIP#JDIMM3_EVENT#

+DIMM_DQ_R_VREF_B

1

2

RD14 0_0402_5%@

0.1U_0402_10V6K

@

CD143

Compal Electronics, Inc.

0.1U_0402_10V6K

@

CD137

1 2

0.1U_0402_10V6K

1

2

LA-E311P

1

PCH_THERMTRIP# <7,14,15,17,19,48>

+1.2V_MEM

1K_0402_5%

12

RD43

1

2

1K_0402_5%

@

12

RD44

CD138

1

2

+1.2V_MEM

12

16 71Wednesday, November 23, 2016

0.1U_0402_10V6K

@

CD139

0.1U_0402_10V6K

@

CD140

0.1U_0402_10V6K

1K_0402_5%

@

RD46

CD142

1

2

1K_0402_5%

@

RD47

1.0

Vinaﬁx.com

5

DDR_B_DQS#[0..7]<8,16>

DDR_B_DQS[0..7]<8,16>

DDR_B_D[0..63]<8,16>

DDR_B_MA[0..13]<8,16 >

D D

+2.5V_MEM

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD71

CD74

2

10U_0603_6.3V6M

CD67

CD57

1

2

1U_0402_6.3V6K

1

CD59

CD60

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD121

1

CD72

2

12

RD53

@

0_0402_5%

12

RD55

@

0_0402_5%

10U_0603_6.3V6M

CD73

CD61 change to SGA20331E10

10U_0603_6.3V6M

CD63

CD68

CD64

1

2

1U_0402_6.3V6K

1

CD119

CD116

CD117

2

1U_0402_6.3V6K

1

CD66

2

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD52

@

0_0402_5%

12

RD56

@

0_0402_5%

1U_0402_6.3V6K

1

CD69

2

+1.2V_MEM

10U_0603_6.3V6M

CD114

1

2

C C

B B

1U_0402_6.3V6K

1

CD58

2

Layout Note: Place near JDIMM4.258

+0.6V_DDR_VTT

DIMM Select

SA2

SA0 SA1

0

0 1

1 1

0

DIMM2

DIMM4

*

DIMM1 1

DIMM3

A A

10U_0603_6.3V6M

CD70

1

2

1U_0402_6.3V6K

1

CD118

2

+V_DDR_REFCA_B

RD51

@

0_0402_5%

DIMM4_SA0 DIMM4_SA1 DIMM4_SA2

RD54

@

0_0402_5%

4

JDIMM4 REV Type H=4

DDR_B_D5

DDR_B_D0

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2

DDR_B_D7

DDR_B_D8

DDR_B_D14

DDR_B_D11

DDR_B_D15

DDR_B_D17

DDR_B_D16

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D21

DDR_B_D28

DDR_B_D27

10U_0603_6.3V6M

330U_D2_2V_Y

@

1

CD115

CD61

1

+

2

1U_0402_6.3V6K

1

CD120

2

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD82

CD81

2

+3.3V_RUN

12

1

2

RD60

@

0_0603_5%

+3.3V_RUN_DIMM4

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD65

CD62

2

DDR_B_CB4<8,16>

DDR_B_CB2<8,16>

DDR_B_DQS#8<8,16> DDR_B_DQS8<8,16>

DDR_B_CB7<8,16>

DDR_B_CB5<8,16>

DDR_B_CKE0<8>

DDR_B_BG1<8,16> DDR_B_BG0<8,16>

DDR_B_CLK0<8> DDR_B_CLK#0<8>

DDR_B_PARITY<8,16>

DDR_B_ODT0<8>

DDR_B_ODT1<8>

DDR_B_BA1<8,16>

DDR_B_CS#0<8>

DDR_B_MA14<8,16>

DDR_B_CS#1<8>

+2.5V_MEM

DDR_B_D24

DDR_B_CB2

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CB5

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS#0 DDR_B_MA14

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

T57PAD~D @

DDR_B_D38

DDR_B_D39

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_D58

DDR_B_D63

+3.3V_RUN_DIMM4

DDR_B_D26

DDR_B_CB4

DDR_B_CB7

3

JDIMM4

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0107-P005A CONN@

VSS11

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

DQS3_c

VSS38

VSS40

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

VSS56

VSS58

DM4_n/DBI4_n

VSS59

VSS61

VSS63

VSS65

VSS67

DQS5_c

DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

DM6_n/DBI6_n

VSS79

VSS81

VSS83

VSS85

VSS87

DQS7_c

DQS7_t

VSS90

VSS92

VSS94

GND2

2

+1.2V_MEM+1.2V_MEM

A

JDIMM2

RD12 1K_0402_5 %@

Top Side

JDIMM1

D

Bottom Side

DDR_B_DRAMRST#

1 2

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD2

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

A0

BA0

A13

SA2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA SA0 VTT SA1

DDR_B_D4

4 6

DDR_B_D1

8 10 12 14

DDR_B_D6

16 18

DDR_B_D3

20 22

DDR_B_D10

24 26

DDR_B_D9

28 30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36

DDR_B_D12

38 40

DDR_B_D13

42 44

DDR_B_D18

46 48

DDR_B_D22

50 52 54 56

DDR_B_D19

58 60

DDR_B_D20

62 64

DDR_B_D25

66 68

DDR_B_D30

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D29

80 82

DDR_B_D31

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRAMRST# DDR_B_CKE1

DDR_B_ACT# DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM4_EVENT#

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DIMM4_SA2

DDR_B_D35

DDR_B_D34

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D56

DDR_B_D60

DIMM4_SA0

DIMM4_SA1

DDR_B_CB1 <8,16>

DDR_B_CB3 <8,16>

DDR_B_CB6 <8,16>

DDR_B_CB0 <8,16>

1 2

CD124 0.1U_0402_10V6K@

DDR_B_CKE1 <8 >

DDR_B_ACT# <8,16> DDR_B_ALERT# <8,16>

DDR_B_CLK1 <8> DDR_B_CLK#1 <8>

DDR_B_BA0 <8,16> DDR_B_MA16 <8,16>

DDR_B_MA15 <8,16>

T56 PAD~D@

+V_DDR_REFCA_B

DDR_XDP_WAN_SMBDAT <7,14,15,16,23,43>DDR_XDP_WAN_SMBCLK<7,14,15,16,23,43>

+0.6V_DDR_VTT

+V_DDR_REFCA_B

CPU

JDIMM3

C

B

JDIMM4

PCH_THERMTRIP#JDIMM4_EVENT#

1

DDR_B_DRAMRST# <14,16>

PCH_THERMTRIP# <7,14,15,16,19,48>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

DDRIII-SODIMM SLOT4

Size Document Number Rev

Date: Sheet of

LA-E311P

1

17 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

PEG_CRX_C_GTX_P[ 0..15]<6>

PEG_CRX_C_GTX_N[0. .15]<6>

PEG_CTX_C_GRX_P[ 0..15]<6>

PEG_CTX_C_GRX_N[0. .15]<6>

D D

PEG_CRX_C_GTX_P[ 0..15]

PEG_CRX_C_GTX_N[0. .15]

PEG_CTX_C_GRX_P[ 0..15]

PEG_CTX_C_GRX_N[0. .15]

+3.3V_MXM

1 2

R3 4.3K_0402_ 5%

1 2

R5 4.3K_0402_ 5%

1 2

R1977 10K_0402_5%

1 2

R1978 10K_0402_5%@

DAT_DDC2_MXM

CLK_DDC2_MXM

DGPU_PWROK

MXM_CLK_REQ#

4

+3.3V_MXM

10K_0402_5%

12

R4

DGPU_PEX_RST#

G

8/25

MXM_ALERT#

2

13

D

S

Q5 DMN65D8LW-7_ SOT323-3

DGPU_ALERT# <47>

3

GPU_SMBDAT_R

GPU_SMBCLK_R

+3.3V_MXM

4.7K_0402_5%

12

@

R1

+3.3V_MXM

4.7K_0402_5%

12

@

R2

DMN66D0LDW-7 _SOT363-6

Q295B

DMN66D0LDW-7 _SOT363-6

2

8/25

2

61

Q295A

354

UPD_GPU_SMBDAT <46,48>

UPD_GPU_SMBCLK <46,48>

CLKREQ_PEG#0<21>

DMN65D8LW-7_ SOT323-3

1 3

D

1

DGPU_PWROK

2

G

MXM_CLK_REQ#CLKREQ_PEG#0

S

Q6

+MXM_PWR_SRC

JMXM1A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

+5V_MXM

0.1U_0402_16V7K

10U_0805_6.3V6M

1

C7

C328

+5V_MXM

2

100mil(2.5A, 5VIA)

1 2

R1970 0_0402_5%@

1 2

R1971 0_0402_5%@

MXM_VGA_DIS#<47>

C C

B B

DGPU_PEX_RST#

8/30

A A

100K_0402_5%

12

R3750

MXM_DPC_HPD

MXM_DPA_HPD

MXM_DPB_HPD

MXM_ENVDD<30>

MXM_PANEL_BKEN<30>

MXM_BIA_PWM<30>

T215PAD~D @

T208PAD~D @ T207PAD~D @

GC6_FB_EN<24>

T209PAD~D @

PEG_CRX_C_GTX_N15

PEG_CRX_C_GTX_N14

PEG_CRX_C_GTX_N13

PEG_CRX_C_GTX_N12

PEG_CRX_C_GTX_N11

PEG_CRX_C_GTX_N10

PEG_CRX_C_GTX_N9

PEG_CRX_C_GTX_N8

PEG_CRX_C_GTX_N7

PEG_CRX_C_GTX_N6

PEG_CRX_C_GTX_N5

PEG_CRX_C_GTX_N4

PEG_CRX_C_GTX_N3 PEG_CRX_C_GTX_P3

+3.3V_ALW

0.1U_0402_1 0V7K

5

P

IN1

4

O

IN2

G

3

SN74AHC1G08DCKR_SC70 -5

1 2

R19 0_0 402_5%@

D7

2 1

RB751VM-40TE-17_ SOD323-2

D8

2 1

RB751VM-40TE-17_ SOD323-2

D18

2 1

RB751VM-40TE-17_ SOD323-2

5

DPE_HPD

GC6_FB_EN

PEG_CRX_C_GTX_P1 5

PEG_CRX_C_GTX_P1 4

PEG_CRX_C_GTX_P1 3

PEG_CRX_C_GTX_P1 2

PEG_CRX_C_GTX_P1 1

PEG_CRX_C_GTX_P1 0

PEG_CRX_C_GTX_P9

PEG_CRX_C_GTX_P8

PEG_CRX_C_GTX_P7

PEG_CRX_C_GTX_P6

PEG_CRX_C_GTX_P5

PEG_CRX_C_GTX_P4

C90

@

1 2

1

2

U16

PWR_SRC

19

GND

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

GND

35

GND

37

5V

39

5V

41

5V

43

5V

45

5V

47

GND

49

GND

51

GND

53

GND

55

PEX_STD_SW#

57

VGA_DISABLE#

59

PNL_PWR_EN

61

PNL_BL_EN

63

PNL_BL_PWM

65

HDMI_CEC

67

DVI_HPD

69

LVDS_DDC_DAT

71

LVDS_DDC_CLK

73

GND

75

OEM1

OEM

77

OEM3

OEM

79

OEM5

OEM

81

OEM7

OEM

83

GND

85

PEX_RX15#

87

PEX_RX15

89

GND

91

PEX_RX14#

93

PEX_RX14

95

GND

97

PEX_RX13#

99

PEX_RX13

101

GND

103

PEX_RX12#

105

PEX_RX12

107

GND

109

PEX_RX11#

111

PEX_RX11

113

GND

115

PEX_RX10#

117

PEX_RX10

119

GND

121

PEX_RX9#

123

PEX_RX9

125

GND

127

PEX_RX8#

129

PEX_RX8

131

GND

133

PEX_RX7#

135

PEX_RX7

137

GND

139

PEX_RX6#

141

PEX_RX6

143

GND

145

PEX_RX5#

147

PEX_RX5

149

GND

151

PEX_RX4#

153

PEX_RX4

155

GND

157

PEX_RX3#

159

PEX_RX3

161

GND

JAE_MM70-314-3 10B1-1-R300

DGPU_HOLD_RST# <24>

PLTRST_GPU# <22>

100K_0402_5%

12

R51

MXM_DP_HDMI_HPD <47>

E1 E2

E3 E4

MXM_PWR_LEVEL

CONN@

PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC

GND GND GND GND GND GND GND GND GND

PRSNT_R#

WAKE#

PWR_GOOD

PWR_EN

RSVD RSVD RSVD RSVD

PWR_LEVEL

TH_OVERT# TH_ALERT#

TH_PWM

GPIO0 GPIO1 GPIO2

SMB_DAT

SMB_CLK

GND OEM OEM OEM OEM GND

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

LInk CIS

MXM_DPB_HPD_GATE

MC74VHC1G09DFT2G_SC7 0-5

2 4 6 8 10 12 14 16 18

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160

+3.3V_MXM

OEM0 OEM2 OEM4 OEM6

+3.3V_MXM

4

O

100K_0402_5%

12

R37

4

400mil(10A)

10U_0805_25VAK

680P_0603_50V7K

1

C2

2

1 2

R1973 0_0402_5%@

1 2

R1972 0_0402_5%@

MXM_DPF_HPD

MXM_PWR_LEVEL MXM_OVERT# MXM_ALERT#

GPU_SMBDAT_R GPU_SMBCLK_R

SYSTEM

GPU_EVENT#_D

D94 RB751VM-40TE-17_SOD323-2

PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P1 5

PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P1 4

PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P1 3

PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P1 2

PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P1 1

PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P1 0

PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P9

PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P8

PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P7

PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P6

PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P5

PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P4

PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P3

5

DGPU_PEX_RST#_D

1

P

IN1

2

IN2

G

U14

3

SN74AHC1G08DCKR_SC70 -5

+3.3V_ALW

0.1U_0402_1 0V7K

5

U17

1

B

Y

VCC

2

A

G

3

4

+MXM_PWR_SRC

0.1U_0603_25V7K

68P_0402_50V8J

1

C1

C4

C3

2

8/29

VGA_ID <47> MXM_PRESENTR# <19> PCIE_WAKE# <40 ,41,46,47>

DGPU_PWROK

DGPU_PWROK <23,47> DGPU_PWR_EN <47>

MXM_DPF_HPD <35>

MXM_PWR_LEVEL <59>

MXM_PIN80_R for 3D function usage (JMXM1_pin 80). 310 pin connector=Pin80 314 pin connector=pin84

T210 PAD~D@ T211 PAD~D@

GPU_EVENT#

2 1

T212 PAD~D@

MXM_DPB_HPD <33>

C92

@

1 2

R155

@

1 2

0_0402_5%

11/11

R156

1 2

0_0402_5%

ACAV_IN_U17

DP to VGA

Docking port1

GPU_EVENT# <24>

TBT/ Docking DP port 2

ACAV_IN <48,59,6 2>

GPU_PWR_LEVEL <47>

JMXM1B

163

PEG_CRX_C_GTX_N2 PEG_CRX_C_GTX_P2

PEG_CRX_C_GTX_N1 PEG_CRX_C_GTX_P1

PEG_CRX_C_GTX_N0 PEG_CRX_C_GTX_P0

CLK_PEG_N0<21> CLK_PEG_P0<21>

MXM_DPF_AUXN<35> MXM_DPF_AUXP<35>

MXM_DPC_N0<31> MXM_DPC_P0<31>

MXM_DPC_N1<31> MXM_DPC_P1<31>

MXM_DPC_N2<31> MXM_DPC_P2<31>

MXM_DPC_N3<31> MXM_DPC_P3<31>

MXM_DPC_AUXN<31> MXM_DPC_AUXP<31 >

MXM_DPA_AUXN<32 > MXM_DPA_AUXP< 32>

MXM_PRESENTL#<19>

CLK_PEG_N0 CLK_PEG_P0

MXM_DPF_AUXN MXM_DPF_AUXP

MXM_DPF_N0

MXM_DPF_N0<35>

MXM_DPF_P0

MXM_DPF_P0<35>

MXM_DPF_N1

MXM_DPF_N1<35>

MXM_DPF_P1

MXM_DPF_P1<35>

MXM_DPA_N0<32> MXM_DPA_P0<32>

MXM_DPA_N1<32> MXM_DPA_P1<32>

MXM_DPA_N2<32> MXM_DPA_P2<32>

MXM_DPA_N3<32> MXM_DPA_P3<32>

DPF

MXM_DPC_N0 MXM_DPC_P0

MXM_DPC_N1 MXM_DPC_P1

MXM_DPC_N2 MXM_DPC_P2

MXM_DPC_N3 MXM_DPC_P3

MXM_DPC_AUXN MXM_DPC_AUXP

MXM_DPA_N0 MXM_DPA_P0

MXM_DPA_N1 MXM_DPA_P1

MXM_DPA_N2 MXM_DPA_P2

MXM_DPA_N3 MXM_DPA_P3

MXM_DPA_AUXN MXM_DPA_AUXP MXM_PRESENTL#

GND

165

PEX_RX2#

167

PEX_RX2

169

GND

171

PEX_RX1#

173

PEX_RX1

175

GND

177

PEX_RX0#

179

PEX_RX0

181

GND

183

PEX_REFCLK#

185

PEX_REFCLK

187

GND

189

RSVD

191

RSVD

193

RSVD

195

RSVD

197

RSVD

199

LVDS_UCLK#

201

LVDS_UCLK

203

GND

205

LVDS_UTX3#

207

LVDS_UTX3

209

GND

211

LVDS_UTX2#

213

LVDS_UTX2

215

GND

217

LVDS_UTX1#

219

LVDS_UTX1

221

GND

223

LVDS_UTX0#

225

LVDS_UTX0

227

GND

229

DP_C_L0#

231

DP_C_L0

233

GND

235

DP_C_L1#

237

DP_C_L1

239

GND

241

DP_C_L2#

243

DP_C_L2

245

GND

247

DP_C_L3#

249

DP_C_L3

251

GND

253

DP_C_AUX#

255

DP_C_AUX

257

RSVD

259

RSVD

261

RSVD

263

RSVD

265

RSVD

267

RSVD

269

RSVD

271

RSVD

273

RSVD

275

RSVD

277

RSVD

279

RSVD

281

GND

283

DP_A_L0#

285

DP_A_L0

287

GND

289

DP_A_L1#

291

DP_A_L1

293

GND

295

DP_A_L2#

297

DP_A_L2

299

GND

301

DP_A_L3#

303

DP_A_L3

305

GND

307

DP_A_AUX#

309

DP_A_AUX

310

PRSNT_L#

311

GND

JAE_MM70-314-3 10B1-1-R300

PEX_CLK_REQ#

VGA_DDC_DAT VGA_DDC_CLK

LInk CIS

+3.3V_MXM +3.3V_MXM

5

DGPU_PEX_RST#_D DGPU_PEX_RST#_D

1

P

IN1

4

O

2

IN2

G

U25

3

SN74AHC1G08DCKR_SC70 -5

D95

3

@

21

RB751VM-40TE-17_ SOD323-2

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CO NTAINS CONFIDE NTIAL TRADE SECRET AN D OTHER PROPRI ETARY INFORMATI ON OF DELL INC . ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHO RIZATION OF DEL L. IN ADDITION , NEITHER THIS SH EET NOR THE IN FORMATION IT CO NTAINS WAY BE USED BY OR DISC LOSED TO ANY T HIRD PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT .

DGPU_PEX_RST# DGPU_PEX_RST#_D DGPU_PWROK

+3.3V_MXM

12

MXM_DPA_HPD_GATEMXM_DPC_HPD_GATE

10K_0402_5%

@

R71

1 2

1000P_0402_50V7K

R72 0_0 402_5%@

@

1

C1470

2

CONN@

PEX_TX2#

PEX_TX2

PEX_TX1#

PEX_TX1

PEX_TX0#

PEX_TX0

PEX_RST#

VGA_VSYNC VGA_HSYNC

VGA_RED

VGA_GREEN

VGA_BLUE

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0

DP_D_L0#

DP_D_L0

DP_D_L1#

DP_D_L1

DP_D_L2#

DP_D_L2

DP_D_L3#

DP_D_L3

DP_D_AUX#

DP_D_AUX DP_C_HPD DP_D_HPD

DP_B_L0#

DP_B_L0

DP_B_L1#

DP_B_L1

DP_B_L2#

DP_B_L2

DP_B_L3#

DP_B_L3

DP_B_AUX#

DP_B_AUX DP_B_HPD DP_A_HPD

4

O

100K_0402_5%

12

2

162

GND

164 166 168

GND

170 172 174

GND

176 178 180

GND

182 184 186 188 190 192 194

GND

196 198 200 202

GND

204 206 208

GND

210 212 214

GND

216 218 220

GND

222 224 226

GND

228 230 232

GND

234 236 238

GND

240 242 244

GND

246 248 250

GND

252 254 256

GND

258 260 262 264 266

RSVD

268

RSVD

270

RSVD

272

GND

274 276 278

GND

280 282 284

GND

286 288 290

GND

292 294 296

GND

298 300 302 304 306

3V3

308

3V3

312

GND

C94

@

1 2

0.1U_0402_1 0V7K

5

1

P

IN1

2

IN2

G

3

SN74AHC1G08DCKR_SC70 -5

R135

U27

PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P2

PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P1

PEG_CTX_C_GRX_N0 PEG_CTX_C_GRX_P0

MXM_CLK_REQ# DGPU_PEX_RST# DAT_DDC2_MXM CLK_DDC2_MXM VSYNC_MXM HSYNC_MXM

RED_MXM GREEN_MXM BLUE_MXM

DPE

MXM_EDP_N0 MXM_EDP_P0

MXM_EDP_N1 MXM_EDP_P1

MXM_EDP_N2 MXM_EDP_P2

MXM_EDP_N3 MXM_EDP_P3

MXM_EDP_AUXN MXM_EDP_AUXP MXM_DPC_HPD_GATE MXM_EDP_HPD

+3.3V_MXM

MXM_DPB_N0 MXM_DPB_P0

MXM_DPB_N1 MXM_DPB_P1

MXM_DPB_N2 MXM_DPB_P2

MXM_DPB_N3 MXM_DPB_P3

MXM_DPB_AUXN MXM_DPB_AUXP MXM_DPB_HPD_GATE MXM_DPA_HPD_GATE

+3.3V_MXM

MXM_DPA_HPD <32>MXM_DPC_HPD <31>

MXM_OVERT#

DAT_DDC2_MXM <36>

CLK_DDC2_MXM <36> VSYNC_MXM <36> HSYNC_MXM <36>

RED_MXM <36> GREEN_MXM <36> BLUE_MXM <36>

MXM_EDP_N0 <29> MXM_EDP_P0 <29>

MXM_EDP_N1 <29> MXM_EDP_P1 <29>

MXM_EDP_N2 <29> MXM_EDP_P2 <29>

MXM_EDP_N3 <29> MXM_EDP_P3 <29>

MXM_EDP_AUXN <29> MXM_EDP_AUXP <29>

MXM_EDP_HPD <29>

MXM_DPB_N0 <33> MXM_DPB_P0 <33>

MXM_DPB_N1 <33> MXM_DPB_P1 <33>

MXM_DPB_N2 <33> MXM_DPB_P2 <33>

MXM_DPB_N3 <33> MXM_DPB_P3 <33>

MXM_DPB_AUXN <33> MXM_DPB_AUXP <33>

40mil(1A)

+3.3V_MXM

10U_0603_6.3V6M

1

C332

2

+3.3V_MXM +3.3V_ALW

10K_0402_5%

12

R10

DGPU_PEX_RST#

G

2

S

Q4 DMN65D8LW-7_ SOT323-3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

To VGA SW

eDP MUX

TBT/mDP

0.1U_0402_10V6K

1

C8

2

10K_0402_5%

12

R11

13

THERMATRIP3# <48>

D

Compal Electronics, Inc.

LA-E311P

1

MXM

18 71Wednesday, Nov ember 23, 2016

1.0

Vinaﬁx.com

5

+3.3V_ALW

TBT_CIO_PLUG_EVENT#

1 2

RH341 10 K_0402_5%@

+3.3V_ALW_PCH

D D

C C

RH366 10 K_0402_5%

+3.3V_RUN

RH319 10 K_0402_5%

RH317 10 K_0402_5%

RH76 10K_0402_5%

RA58 10K_04 02_5%

RH90 10K_0402_5%

RH91 10K_0402_5%

RH321 10 K_0402_5%

RH323 10 K_0402_5%

RH324 10 K_0402_5%

RH354 10 K_0402_5%

RH326 10 K_0402_5%

RH322 10 K_0402_5%

1 2

TBT_CIO_PLUG_EVENT#

CAM_MIC_CBL_DET#

MXM_PRESENTL#

BIOS_REC

SPK_DET#

CONTACTLESS_DET#

MXM_PRESENTR#

SATA_EXP_IFDET

SATAGP1

HDD_DET#

SATAGP5

SATAGP6

SATAGP7

M.2 SSD Slot#3

Tell EC don't read GFX Temp.in GC6 High: Read; Low: Don`t read

GC6_THM_ON<47>

Dock

M.2 SSD Slot#3

4

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

1 2

PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#

CAM_MIC_CBL_DET#

TBT_CIO_PLUG_EVENT# MXM_PRESENTL# CONTACTLESS_DET#

MXM_PRESENTR#

SPK_DET#

PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11

BIOS_REC

CS_CTR

SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12

PCH_CL_CLK1<40>

PCH_CL_DATA1<40>

PCH_CL_RST1#<40>

CAM_MIC_CBL_DET#<30>

TBT_CIO_PLUG_EVENT#<46>

MXM_PRESENTL#<18>

CONTACTLESS_DET#<39>

MXM_PRESENTR#<18>

SPK_DET#<46>

PCIE_PTX_DRX_P11<41> PCIE_PTX_DRX_N11<41> PCIE_PRX_DTX_P11<41> PCIE_PRX_DTX_N11<41>

RH342 0_0402_5%@

SATA_PTX_DRX_N1<45> SATA_PTX_DRX_P1<45 > SATA_PRX_DTX_N1<45> SATA_PRX_DTX_P1<45 >

PCIE_PTX_DRX_P12<41> PCIE_PTX_DRX_N12<41> PCIE_PRX_DTX_P12<41> PCIE_PRX_DTX_N12<41>

3

SPT-H_PCH

CLINK

FAN

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

HOST

THERMTRIP#

PLTRST_PROC#

PM_DOWN

PM_SYNC

3 OF 12REV = 1.3

PCIE_PRX_DTX_N9

G31

PCIE_PRX_DTX_P9

H31

PCIE_PTX_DRX_N9

C31

PCIE_PTX_DRX_P9

B31

PCIE_PRX_DTX_N10

G29

PCIE_PRX_DTX_P10

E29

PCIE_PTX_DRX_N10

C32

PCIE_PTX_DRX_P10

B32

PCIE_PRX_DTX_N15

F41

PCIE_PRX_DTX_P15

E41

PCIE_PTX_DRX_N15

B39

PCIE_PTX_DRX_P15

A39

PCIE_PRX_DTX_N16

D43

PCIE_PRX_DTX_P16

E42

PCIE_PTX_DRX_N16

A41

PCIE_PTX_DRX_P16

A40

PCIE_PRX_DTX_N17

H42

PCIE_PRX_DTX_P17

H40

PCIE_PTX_DRX_N17

E45

PCIE_PTX_DRX_P17

F45

PCIE_PRX_DTX_N18

K37

PCIE_PRX_DTX_P18

G37

PCIE_PTX_DRX_N18

G45

PCIE_PTX_DRX_P18

G44

PCH_SATA_LED#

AD44

M2_SLOT3_PEDET

AG36

SATAGP1

AG35

HDD_DET#

AG39

SATA_EXP_IFDET

AD35

M2_SLOT2_PCIE#_SATA

AD31

SATAGP5

AD38

SATAGP6

AC43

SATAGP7

AB44

BIA_PWM_PCH

W36

PANEL_BKEN_PCH

W35

ENVDD_PCH

W42

PCH_THERMTRIP#_R PCH_THERMTRIP#

AJ3

PCH_PECI H_PECI

AL3

H_PM_SYNC_R

PECI

AJ4

PLTRST_CPU#

AK2

H_PM_DOWN

AH2

2

PCIE_PRX_DTX_N9 <4 1>

PCIE_PRX_DTX_P9 <41> PCIE_PTX_DRX_N9 <4 1> PCIE_PTX_DRX_P9 <41>

PCIE_PRX_DTX_N10 <41>

PCIE_PRX_DTX_P10 <41> PCIE_PTX_DRX_N10 <41> PCIE_PTX_DRX_P10 <41 >

PCIE_PRX_DTX_N15 <44>

PCIE_PRX_DTX_P15 <44> PCIE_PTX_DRX_N15 <44> PCIE_PTX_DRX_P15 <44 >

PCIE_PRX_DTX_N16 <44>

PCIE_PRX_DTX_P16 <44> PCIE_PTX_DRX_N16 <44> PCIE_PTX_DRX_P16 <44 >

PCIE_PRX_DTX_N17 <40>

PCIE_PRX_DTX_P17 <40> PCIE_PTX_DRX_N17 <40> PCIE_PTX_DRX_P17 <40 >

PCIE_PRX_DTX_N18 <40>

PCIE_PRX_DTX_P18 <40> PCIE_PTX_DRX_N18 <40> PCIE_PTX_DRX_P18 <40 >

PCH_SATA_LED# <49>

M2_SLOT3_PEDET <41>

HDD_DET# <43> SATA_EXP_IFDET <43,44> M2_SLOT2_PCIE#_SATA <47>

BIA_PWM_PCH <30> PANEL_BKEN_PCH <30> ENVDD_PCH <30,48>

RH75 620_0402_5%

1 2

9/12

RH73 13_0402_5%

1 2

RH360 30 _0402_5%

1 2

M.2 SSD Slot#3

SATA Express

M.2 SSD Slot#4

SPSGP0

SPSGP3

SPSGP4

PLTRST_CPU# <7> H_PM_DOWN <7>

M2_SLOT3_PEDET 0=SATA

01SATA_EXP_IFDET

1

M2_SLOT2_PCIE#_SATA (SLOT2_CONFIG_1)

PCH_THERMTRIP# <7,14,15,16,17,48> H_PECI <7,48> H_PM_SYNC <7>

1

1=PCIE

0=SATA

1=PCIE

0=SATA 1=PCIE

RH365 10K_0402_5%

PCH_PECI

12

RH74

@

10K_0402_5%

H_PM_DOWN

12

@

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Date: Sheet of

SKYLAKE PCH-H (1/9)

LA-E311P

1

19 71Wednesday, November 23, 2016

1.0

Vinaﬁx.com

5

D D

4

3

2

1

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

1 2

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIECOMP# PCIECOMP

PCIE_PTX_DRX_N2

PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N2

PCIE_PRX_DTX_P2

PCIE_PRX_DTX_N3

PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3

PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4

PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4

PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N5

PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5

PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6

PCIE_PRX_DTX_P6

PCIE_PTX_DRX_N6

PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7

PCIE_PRX_DTX_P7

PCIE_PTX_DRX_N7

PCIE_PTX_DRX_P7

PCIE_PRX_DTX_N8

PCIE_PRX_DTX_P8

PCIE_PTX_DRX_N8

PCIE_PTX_DRX_P8

DMI_CTX_PRX_N0<6>

DMI_CTX_PRX_P0<6> DMI_CRX_PTX_N0<6> DMI_CRX_PTX_P0<6>

DMI_CTX_PRX_N1<6>

DMI_CTX_PRX_P1<6> DMI_CRX_PTX_N1<6> DMI_CRX_PTX_P1<6>

DMI_CTX_PRX_N2<6>

DMI_CTX_PRX_P2<6>

WLAN

LAN

TBT

DMI_CRX_PTX_N2<6> DMI_CRX_PTX_P2<6>

DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P3<6> DMI_CRX_PTX_N3<6> DMI_CRX_PTX_P3<6>

RH192 100_ 0402_1%

PCIE_PTX_DRX_N2<40> PCIE_PTX_DRX_P2<4 0>

PCIE_PRX_DTX_N2<40>

PCIE_PRX_DTX_P2<4 0>

PCIE_PRX_DTX_N3<46>

PCIE_PRX_DTX_P3<4 6> PCIE_PTX_DRX_N3<46> PCIE_PTX_DRX_P3<4 6>

PCIE_PRX_DTX_N4<37>

PCIE_PRX_DTX_P4<3 7> PCIE_PTX_DRX_N4<37> PCIE_PTX_DRX_P4<3 7>

PCIE_PRX_DTX_N5<46>

PCIE_PRX_DTX_P5<4 6> PCIE_PTX_DRX_N5<46> PCIE_PTX_DRX_P5<4 6>

PCIE_PRX_DTX_N6<46>

PCIE_PRX_DTX_P6<4 6> PCIE_PTX_DRX_N6<46> PCIE_PTX_DRX_P6<4 6>

PCIE_PRX_DTX_N7<46>

PCIE_PRX_DTX_P7<4 6> PCIE_PTX_DRX_N7<46> PCIE_PTX_DRX_P7<4 6>

PCIE_PRX_DTX_N8<46>

PCIE_PRX_DTX_P8<4 6> PCIE_PTX_DRX_N8<46> PCIE_PTX_DRX_P8<4 6>

C C

Card reader

B B

A A

SPT-H_PCH

DMI

PCIe/USB 3

USB 2.0

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_VBUSSENSE

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_COMP

RSVD_AB13

USB2_ID

GPD7/RSVD

2 OF 12REV = 1.3

AF5 AG7 AD5 AD7 AG8 AG10 AE1 AE2 AC2 AC3 AF2 AF3 AB3 AB2 AL8 AL7 AA1 AA2 AJ8 AJ7 W2 W3 AD3 AD2 V2 V1 AJ11 AJ13

AD43 AD42 AD39 AC44 Y43 Y41 W44 W43

AG3 AD10 AB13 AG2

BD14

USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB2_COMP USB2_VBUSSENSE

USB2_ID

3.3V_CAM_EN#

USB20_N1 <46>

----->Left Side JUSB1

USB20_P1 <46> USB20_N2 <46>

----->Right Side JUSB1

USB20_P2 <46> USB20_N3 <46>

----->Right Side JUSB2

USB20_P3 <46> USB20_N4 <46>

----->Right Side JUSB3

USB20_P4 <46> USB20_N5 <45>

----->MLK DOCK

USB20_P5 <45> USB20_N6 <40>

----->M.2 Slot-1 (WLAN/BT/WiGig)

USB20_P6 <40>

----->MLK DOCK

USB20_N7 <45> USB20_P7 <45> USB20_N8 <40>

----->M.2 Slot-2 (WWAN/LTE/HCA)

USB20_P8 <40>

USB20_N9 <30>

----->Touch Screen

USB20_P9 <30>

USB20_N10 <39>

----->USH

USB20_P10 <39> USB20_N11 <30>

----->Camera

USB20_P11 <30>

USB_OC0# <46> USB_OC1# <46> USB_OC2# <46> USB_OC3# <46>

1 2 1 2

RH193 11 3_0402_1% RH355 1K_ 0402_5%

1 2

RH356 0 _0402_5%@

3.3V_CAM_EN# <30 >

USB_OC1# USB_OC2# USB_OC3# USB_OC0#

RPH6

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Date: Sheet of

SKYLAKE PCH-H (2/9)

LA-E311P

1

20 71W ednesday, November 23, 2016

1.0

Vinaﬁx.com

5

D D

4

3

2

1

1 2

RH152 0_040 2_5%@

1M_0402_1%

SPT-H_PCH

RH153

1 2

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

7 OF 12REV = 1.3

3

4

YH2 24MHZ_12 PF_X3G024 000DC1H

1

2

XTAL24_O UT_R

PCH_XDP_ CLK_DN_R

L1

PCH_XDP_ CLK_DP_R

L2

PCH_CPU_P CIBCLK_D# P CH_CPU_PCIBC LK_R_D#

J1

PCH_CPU_P CIBCLK_D

J2

CLK_PEG _N0

N7

CLK_PEG _P0

N8

CLK_PCIE _N1

L7

CLK_PCIE _P1

L5

CLK_PCIE _N2

D3

CLK_PCIE _P2

F2

CLK_PCIE _N3

E5

CLK_PCIE _P3

G4

CLK_PCIE _N4

D5

CLK_PCIE _P4

E6

CLK_PCIE _N5

D8

CLK_PCIE _P5

D7

CLK_PCIE _N6

R8

CLK_PCIE _P6

R7

CLK_PCIE _N7

U5

CLK_PCIE _P7

U7

W10 W11

N3 N2

P3 P2

R3 R4

CH13

1 2

15P_040 2_50V8J

CH14

1 2

15P_040 2_50V8J

1 2 1 2

RH154 0_040 2_5%@

1 2

RH155 0_040 2_5%@

1 2

RH168 0_040 2_5%@ RH167 0_040 2_5%@

CLK_PEG _N0 <1 8> CLK_PEG _P0 <18>

CLK_PCIE _N1 <46> CLK_PCIE _P1 <46>

CLK_PCIE _N2 <40> CLK_PCIE _P2 <40>

CLK_PCIE _N3 <37> CLK_PCIE _P3 <37>

CLK_PCIE _N4 <46> CLK_PCIE _P4 <46>

CLK_PCIE _N5 <43> CLK_PCIE _P5 <43>

CLK_PCIE _N6 <40> CLK_PCIE _P6 <40>

CLK_PCIE _N7 <41> CLK_PCIE _P7 <41>

PCH_XDP_ CLK_DN PCH_XDP_ CLK_DP

PCH_CPU_P CIBCLK_R_D

MXM

Card reader

M.2 Slot2 WWAN

LAN

TBT

HDD

M.2 Slot1 WLAN

M.2 Slot3 SSD2

PCH_XDP_ CLK_DN < 7> PCH_XDP_ CLK_DP <7> PCH_CPU_P CIBCLK_R_D# <7> PCH_CPU_P CIBCLK_R_D <7>

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKL-H-PCH_B GA837

XTAL24_IN_R

XTAL24_OUT_R1

CLKREQ_P EG#0<18>

CLKREQ_P CIE#1<46>

CLKREQ_P CIE#2<40>

CLKREQ_P CIE#3<37>

CLKREQ_P CIE#4<46>

CLKREQ_P CIE#5<43>

CLKREQ_P CIE#6<40>

CLKREQ_P CIE#7<41>

CH4

1 2

CH5

1 2

CPU_24MHZ_ R_D CPU_24MHZ_ R_D#

PCH_CPU_B CLK_R_D PCH_CPU_B CLK_R_D#

RH128 10K_040 2_5%

+3.3V_RUN

RH124 10K_040 2_5%

+3.3V_RUN

RH125 10K_040 2_5%

+3.3V_RUN

RH126 10K_040 2_5%

+3.3V_RUN

RH127 10K_040 2_5%

+3.3V_RUN

RH131 10K_040 2_5%

+3.3V_RUN

RH132 10K_040 2_5%

+3.3V_RUN

RH133 10K_040 2_5%

+3.3V_RUN

PCH_RTCX1_R

12

YH1

32.768K HZ_12.5PF_9 H03200042

RH43 0_0 402_5%@

CPU_24MHZ_ R_D<7> CPU_24MHZ_ R_D#<7>

PCH_CPU_B CLK_R_D<7> PCH_CPU_B CLK_R_D#<7>

MXM

Card reader

C C

B B

M.2 Slot2 WWAN

M.2 Slot1 WLAN

M.2 Slot3 SSD1

LAN

TBT

HDD

18P_040 2_50V8J

RH169 0_040 2_5%@ RH170 0_040 2_5%@

RH161 0_040 2_5%@ RH166 0_040 2_5%@

+1.0V_CLK 5

12

8/25 move to p.18

1 2

1 2 1 2

1 2

RH171 2. 7K_0402_1 %

CLKREQ_P EG#0

CLKREQ_P CIE#1

CLKREQ_P CIE#2

CLKREQ_P CIE#3

CLKREQ_P CIE#4

CLKREQ_P CIE#5

CLKREQ_P CIE#6

CLKREQ_P CIE#7

PCH_RTCX1

12

RH44 10M_040 2_5%

PCH_RTCX2

PCH_CPU_NS SC_CLK_D PCH_CPU_NS SC_CLK_D#

PCH_CPU_B CLK_D PCH_CPU_B CLK_D#

XTAL24_OUT_R1 XTAL24_IN_R

XCLK_RBI AS

PCH_RTCX1 PCH_RTCX2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (3/9)

LA-E311P

21 71Wed nesday, November 23, 2 016

1

1.0

Vinaﬁx.com

5

D D

C C

+3.3V_AL W_PCH

+3.3V_RUN

PCH_SPI_ D3

RH335 1K _0402_5%@

1 2

RH334 1K_0 402_5%@

1 2

SIO_EXT_S MI#

12

RH31010K_0402_ 5%

TOUCHPAD_INTR#

12

RH36410K_0402_ 5%

+3.3V_SP I

RH180 0_0402 _5%XDP @

1 2

MEDIACARD_IRQ#<46>

PCH_SPI_CLK<39>

PCH_SPI_CS#2<39>

FFS_INT2<43> TPM_PIRQ#<39>

PCH_SPI_D2_XDP<7>

PCH_SPI_ D2_XDP

Intel required for pre-ES1/ES2 sample

+3.3V_SP I

PCH_SPI_ D2_0_R

1 2

R3664 1K_0402_5 %

B B

A A

5

R3668 1K_0402_5 %

+3.3V_SP I

PCH_SPI_ D3_0_R

1 2

PCH_SPI_ CS#0_R1 PCH_SPI_ CS#0_R2 PCH_SPI_ D1_R1 PCH_SPI_ D1_0_R

PCH_SPI_ D2_1_R

1 2

R3665 1K_0402_5 %@

R3666 1K_0402_5 %@

PCH_SPI_ CS#1_R1 PCH_SPI_ CS#1_R2

PCH_SPI_ D2_R1

1 2

PCH_SPI_ CLK_1_R

PCH_SPI_ D3_1_R

R936 0 _0402_5%@ R895 3 3_0402_5 %@ R3667 33_0402 _5%@

4

T178PAD~D @

PME#

T59PAD ~D @ T60PAD ~D @ T61PAD ~D @ T58PAD ~D @

T63PAD ~D @ T62PAD ~D @

PCH_SPI_ D0

1 2 1 2 1 2

PCH_SPI_ D1 PCH_SPI_ CS#0 PCH_SPI_ CLK PCH_SPI_ CS#1

PCH_SPI_ D2 PCH_SPI_ D3 PCH_SPI_ CS#2

MEDIACARD_ IRQ# FFS_INT2 TPM_PIRQ#

12

@EMC@

33_0402 _5%

1

@EMC@

27P_040 2_50V8J

2

4

PCH_SPI_D1<39>

R7 0_0 402_5%@ R8 33_ 0402_5% R9 33_ 0402_5%

PCH_SPI_ D2_0_RPCH_SPI_ D2_R1

PCH_SPI_ D1_1_RPCH_SPI_ D1_R1 PCH_SPI_ D2_1_R

R3755

C1466

PCH_PLTRST#

UH1A

BD17

GPP_A11/PME#

AG15

RSVD

AG14

RSVD

AF17

RSVD

AE17

RSVD

AR19

TP2

AN17

TP1

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKL-H-PCH_B GA837

PN change to SA0000ACM2L for MP

200 MIL SO8

16MB Flash ROM

U52

1

/CS

2

DO(IO1)

3

/WP(IO2) GND4DI(IO0)

W25Q1 28FVSIQ_SO 8

200 MIL SO8

4MB Flash ROM

U53

@

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q3 2FVSSIQ_SO 8

+3.3V_AL W_PCH +3.3V _RUN

12

RH349

@

0_0402_ 5%

+U638_PW R

5

1

P

IN1

O

2

IN2

G

3

SPT-H_PCH

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

REV = 1.3 1 OF 12 ?

+3.3V_SP I

8

VCC

7

/HOLD(IO3)

PCH_SPI_ CLK_0_R

6

CLK

PCH_SPI_ D0_0_R PCH_SPI_ D0_R1

5

CIS LINK OK

+3.3V_SP I

8

VCC

PCH_SPI_ D3_1_R

7

/HOLD/IO3

6

CLK

PCH_SPI_ D0_1_R

5

DI/IO0

CIS LINK OK

3

12

RH350

@

0_0402_ 5%

U638 SN74AHC1 G08DCKR_SC7 0-5

PCH_PLTRST#_ AND

4

GPP_G14/GSXDIN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

INTRUDER#

C746

1 2

0.1U_040 2_25V6K

C1216

@

1 2

0.1U_040 2_25V6K

3

12

RH196

@

100K_04 02_5%

BB27

TBT_FORCE_PW R

P43

RTD3_CIO_PW R_EN

R39 R36 R42 R41

SIO_EXT_S MI#

AF41

TOUCH_SCREE N_PD#

AE44

TOUCHPAD_INTR#

BC23

TOUCH_SCREE N_DET#

BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

PCH_INTRUDER_ HDR#

BE11

1 2

R3669 33_040 2_5%

1 2

R899 33_0402_5 %EMC@

1 2

R901 33_0402_5 %

1 2

R3670 33_0402 _5%@

1 2

R897 3 3_0402_5 %@EMC@

1 2

R900 3 3_0402_5 %@

1 2 1 2

RH337 0_04 02_5%@

1 2

RH197 0_04 02_5%@ RH212 0_04 02_5%@

1 2

RH346 0_04 02_5%@

PCH_PLTRST#

TBT_FORCE_PWR <46> RTD3_CIO_PWR_EN <46,47>

SIO_EXT_SMI# <48>PCH_SPI_D0<7,39> TOUCH_SCREEN_PD# <30> TOUCHPAD_INTR# <48,50> TOUCH_SCREEN_DET# <30>

+RTC_CELL

PCH_SPI_ D3_R1 PCH_SPI_ CLK_R1PCH_SPI_CLK_ 1_R PCH_SPI_ D0_R1

PLTRST_USH#_EC<47>

12

RH198 1M_0402 _1%

PCH_SPI_ D3_R1PCH_SPI_ D3_0_R PCH_SPI_ CLK_R1

2

PCH_PLTRST#_EC <40,41,47,48> PLTRST_TBT# <46> PLTRST_HDD# <43>

PLTRST_TPM#

RH187 0_0402_ 5%@ RH194 0_0402_ 5%@ RH195 0_0402_ 5%@ RH211 0_0402_ 5%@ RH210 0_0402_ 5%@ RH359 0_0402_ 5%@

+3.3V_SP I

2

1 2 1 2 1 2 1 2 1 2 1 2

1

PLTRST_TPM# <39 > PLTRST_LAN# <37> PLTRST_GPU# <18> PLTRST_MMI# <46> PLTRST_USH# <39>

PCH_SPI_ CLK_0_R

12

@

RE1 33_0402 _5%

1

@

CE1 27P_040 2_50V8J

2

PCH_SPI_ CS#1_R1

12

RH1770_0402_ 5% @

PCH_SPI_ CS#1

PCH_SPI_ D0_R1

12

RH1780_0402_ 5% @

PCH_SPI_ D0 PCH_SPI_ D1_R1

12

RH1790_0402_ 5% @

PCH_SPI_ D1 PCH_SPI_ CLK_R1

12

RH1810_0402_ 5% @

PCH_SPI_ CLK

PCH_SPI_ CS#0_R1

12

RH1820_0402_ 5% @

PCH_SPI_ CS#0 PCH_SPI_ D2_R1

12

RH1830_0402_ 5% @

PCH_SPI_ D2 PCH_SPI_ D3_R1

12

RH1840_0402_ 5% @

PCH_SPI_ D3

+3.3V_AL W_PCH

RH185 0_0 402_5%@

12

RH343 0_ 0402_5%@

12

+3.3V_SP I_PWR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (4/9)

LA-E311P

1

JSPI1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND1

22

GND2

E-T_6712K -Y20N-07L

CONN@

CIS link OK

1.0

22 71Wed nesday, November 23, 2 016

1.0

Dell precision 7520 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual