Dell OPTIPLEX 990 Schematics
5
RepairLap.com
4
3
2
1
1. Index / Block diagram
2. SMBus MAP
3. Clock Distribution
4. Power Delivery Map
D D
5. Power On Sequence
Page 20
CK505 CLOCK Gen
Page 65 ~ 72
VRD12 / VRM / Linear
6. Reset / Power Good Map
7. Strap/IRQ/IDSel Table
8. GPIO Table
XDP
9-14. CPU
15. DDR3 Conn: CHA
16. DDR3 Conn: CHA_DQ_VREF
Katsiki-USFF
Intel PROCESSOR
SANDY BRIDGE
Page 52
LGA1155
Page 9-14
CHANNEL A DDR3 SDRAM (1066/1333)
Page 15
CHANNEL B DDR3 SDRAM (1066/1333)
Page 17
DDR3 DIMM 1
DDR3 DIMM 2
17. DDR3 Conn: CHB
18. DDR3 Conn: CHB_DQ_VREF
19. TBD
20. Clock GEN
DISPLAY PORT
21-30. PCH
31. PCH MISC Conn/BUZ/ID
32-33. SIO:SMSC5544
C C
34-35. LAN: INTEL LEWISVILLE
36-37 AUDIO:ALC269Q
38. TBD
39. TBD
VGA CONN
Mini-PCIe Slot x1
USB 2.0 X1
40. Mini PCIe
41. Display Port
XDP
42. VGA Conn
DP Link
Page 41
VGA
Page 42
PCIe Gen2 1x
Page 40
USB 2.0 Port 12
Page 40
Page 52
FDI
DMI
Intel
Cougar Point
PCIe 1x
Page 34
USB 2.0
Intel
Lewisville
Port 0/1
Port 2 ~ 5
Page 45
Port 6/7
Page 56
Page 35
NIC + USB
Ports X 2
Rear USB Ports X3
Front USB Ports X2
43. SATA Conn
44. eSATA Conn
45. Rear USB
46. TPM & TCM
SATA 3.0 CONN X2
47. Thermal Sensor
48. FAN
49. TBD
B B
50. COM1
51. SPI
eSATA 1.0 CONN X1
(Dummy)
52. XDP
53. Pilot Run Conn
SATA Port 0/1
Page 43
SATA Port 4
Page 44
Page 21-30
LPC
HDA
Page 36
ALC269Q
Page 37
Rear Audio CONN
Line In (MIC In)/Line Out
Front Audio CONN
HP Out/ MIC In
Page 56
54. EMI
55. TBD
56. Front_Panel
57. TBD
58. TBD
59. TBD
60. TBD
61. TBD
62. TBD
SPI ROM
2M+8M
SPI
Page 51
SMSC5544
SERIAL
Ports X1
Page 50
Page 32
TPM/TCM
Page 46
63. Power Conn
64. Power Sequence
A A
65-67. Power: Linear Power
68-69. Power: Vcore PWM
70. Power: VCCIO/VCCSA
71-72. Power: DDR3/5VSB/+3V_DUAL
5
CHECK APPROVEDESIGN
Title
Title
Steven
4
Sam Sdiu
3
2
Title
Index / Block diagram
Index / Block diagram
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Index / Block diagram
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
172Monday, December 06, 2010
172Monday, December 06, 2010
172Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
4
3
2
1
SMBUS DIAGRAM
SMdata2
D D
Intel Lewisvillies
LOM
SMLINK0
R015/RO16RO31/RO32
SMdclk2
5544 SIO
SMdata1
SMdclk1
Clock Generator
IDTCV184-2APAG8
Write : 0 X D2
Read : 0 X D3
SMBus
Controller
SMLINK1
QO4/QO5
BUS Switch
RESUME SMBUS
C C
Main SMBUS
PCH
CPU-XDP
PCH-XDP
RX9/RX10
Mini-PCIe 1x
B B
DDR3 DIMM1 CHA
DDR3 DIMM2 CHB
DIMM SLOTS
Address : 0 X00
Address : 0 X04
A A
Title
Title
5
4
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SMBus MAP
SMBus MAP
SMBus MAP
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
A00
A00
A00
272Monday, December 06, 2010
272Monday, December 06, 2010
272Monday, December 06, 2010
5
RepairLap.com
D D
4
3
2
1
Channel B
DIMM 2
Channel A
DIMM 1
C_PCI_SB
C_PCIEX1_1/C_PCIEX1#_1
MINI PCIe
25 MHZ
C C
PCH
C_SRC1_PCH/C_SRC1_PCH#
PCH XDP
D3_MA_CLK/CLK#[0:3]
D3_MB_CLK/CLK#[0:3]
32.768 KHZ
Buffer Through Mode
C_PE_100M_MCP/MCP#
CPU
B B
C_SATA_PCH/PCH#
25 MHZ
LAN 82579
C_96M_PCH/PCH#
C_PCIE_L1/L1#
C_DMI_PCH/PCH#
C_14M_MCH
C_14M_TPM
C_LPC_TPM
C_LPC_TPM
TPM/TCM
LPC HEADER
CK505
C_LPC_SIO
SUPER IO
A A
5
C_14M_SIO
4
CLOCK CHIP
14.318 MHZ
C_CK505_ITP/ITP#
CPU XDP
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Clock Distribution
Clock Distribution
Clock Distribution
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
372Monday, December 06, 2010
372Monday, December 06, 2010
372Monday, December 06, 2010
A00
A00
A00
5
RepairLap.com
4
3
2
1
RESET / Power Good MAP
Sequence Signal Name:
O_PWRBTN#IN
(1)
S_SLP_S4# S_SLP_S3#
(2)
O_PSON#
(3)
D D
B_ATX_PWROK
(4)
PCH_MEPWRGD
(5)
S_PCH_SYSPWROK P_VR_READY
(6)
PWRGD_3V
(7)
H_DRAMPWRGD
(8)
H_PWRGD
(9)
S_PLTRST#
(10)
X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT
(11)
A_Z_RST#
(12)
D3_RESET#
H_RESET#_R S_PLTRST#_R
CPU-XDP
PCH-XDP
C C
F_TP_XDP_RST
Front Panel
O_PWRBTN#IN
S_SLP_M#
(9)
(1)
(1)
PROCPWRGD
PWROK
> 1ms
UNCOREPWRGOOD
(9)
CPU-Sandy Bridge
SM_DRAMPWROK
RESET*
(10)
Buffer (UH2)
SM_DRAMRST*
Deep Sleep Exit MAP
Sequence Signal Name:
O_PWRBTN#IN
(D1)
S_SLP_SUS#
(D2)
S_RSMRST#
(D3)
S_SUSWARN#
(D4)
S_SUS_PWR_ACK#
(D5)
(8)
(10)
(10)
DDRIII Slots
D3_RESET#
LAN
PE_RST_N
TPM/TCM
LRESET#
(1)
Power On Botton
O_PWRBTN#IN
(1) (1)
(D1)
PWRBTN#
DRAMPWROK
PLTRST# LRESET#
PROCPWRGD
VRD 12
VR_RDY
B B
RESET BUTTON
FP_RST#
HD Audio
RESET#
(12)
(6)
SYS_PWROK
SYS_RESET#
HDA_RST#
AND
PCH
PWROK
SLP_S4# SLP_S4_S5#
SLP_A# IO_SMI#
RSMRST#
(8)
(10)
(2)
(2)
(2)
(7)
PWR_GOOD_3V
SLP_S3#SLP_S3#
PCI_RST_SYS#
PWRBTN#
SIO-5544
PS_ON#
PWRGD_PS
(11)
(4)
(3)
PWR_GOOD_3V
PWRGD_PS
Mini-PCIe
PERST#
ATX Power
PSON
PWROK
100~120ms
(D3)
ME POWER-GOOD
CIRCUIT
PCH_MEPWRGD
PCH_MEPWRGD
+1P05V_ME
A A
> 1ms
5
+5VDUAL
SUSACK#
(5)
APWROK
SLP_SUS#
SUSWARN#
SUSACK#
(D2)
(D4)(D5)
Sequence
Logic
Circuit
Page.64
4
+5V_S5/+3V_S5
SLP_SUS#
Sequence
Logic
Circuit
Page.64
3
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Reset / Power Good Map
Reset / Power Good Map
Reset / Power Good Map
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
672Monday, December 06, 2010
672Monday, December 06, 2010
672Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
POWER ON Timing Diagram
4
3
2
1
G3 to S4/S5 Timing Diagram
VccRTC
RTCRST#
D D
t200
VCCSUS
RSMRST#
SUSCLK
SLP_S5#
C C
Deep Sleep Entry
DPWROK
SUSWARN#
SUS_PWR_ACK
SLP_SUS#
RSMRST#
+5VDUAL
+5V_S5/+3V_S5
B B
t226
t225
t201
t202
1.05V
Deep Sleep Exit
DPWROK
SLP_SUS#
RSMRST#
+5V_S5/+3V_S5
SUSWARN#
A A
SUS_PWR_ACK
O_PS_ON#
S_SLP_S3#
+12V/+5V
+1P5V_SM
+1P05V_VCCIO
+1P8V_SFR
H_VCCSA_VID
+V_VCCSA
SVIDs
(VIDSOUT/VIDCLK)
+VCORE
SAlert#I
VIDALERT#
VR_Ready
Feed into PCH
SYS_PWROK
+1P1V_AXG
Srtaps=CFG[x}
S_Thermtrip#
H_SM_DRAMPWRGD
(xxDRAM_PWROK)
D3_RESET#
PWRGD_3V
Feeds into PCH_PWROK
BCLK, PCIe
CLKs
UNCOREPWRGOOD
(PROCPWRGD)
S_RLTRST#
DMI
Power rails rise
0.2 – 20ms
Power rails rise
+3V
0.2 – 20ms
=50ms
=50ms
=50ms
EN
Note4:Uncorepwergood must be at
a valid level during all power states
PCI/PCIe:100ms min
PSU: <=20ms
=500ms
T
VCCSA VID[0] Buffers Output is
stable after VccIO Ramp
Uncorepwrgd must be stable (low) at this time
Recommended that VccSA ramp after VCCIO has
remped to ensure VCCSA_VID[0] is stable
VSABOOT=SNB Vmax
V
RC
Note5: Core and GT power supplies should not source current during this time.
Note5: Core and GT power supplies should not source current during this time.
Note:DDR spec reuqires that DDR_RESET# be
asserted during power ramp cycle
IH
T
A
VR:5ms max
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood=0
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood=0
Min 10 PCIe bclks
T
10
CPU:1ms min
PSU
100ms~500ms
T
2
CPU:5ms min, 650ms max
17
T
11
CPU:[x]ms min
PCH t34
(1ms)
Min 10 PCIe bclks
PCH t573
(1, 5, 50, or 100ms)
T
1
CPU:
500us max
T
Uncorepwrgood assertion
MAX TBDns
VCCUSA VID[0] FINAL
Ramp not to exceed 50mV/us
VSAFINAL
Typ 60us
Depends on exact SVID
transactions between CPU
and VR
MISC
13
Note: PCH THERMAL WATCHDOG TIMER WILL BE DISABLED WITH SNB.
SNB WILL NOT EXCEED VR IMAX UNTIL THERMTRIP# IS ENABLED
T
A
C
K
0
B
A
Set VID
A
SLOW
Packet
VR:5us max
A
C
C
K
K
T
0
1
VR:2ms max
T
C
VR:1us max
C
K
1
GT Ramp will occur after PLTRST#
Strapping option
Inactive / Disable
T
6
CPU:1ms min, 100ms max
D
T
E
GETReg
status
Packet
T
F
VR:min=Te,5ms max
T
12
CPUPWRGOOD
SYS_PWROK(VR_READY)
T
8
CPU:
400us min
A
A
C
C
Pay
K
K
load
0
1
=5ms
PCH(t1001)
T
14
Min 10 PCIe bclks
Set VID
Packet
T
VR:5us max
Satus
Packet
CPU
Packet
GT
Packet
C
Enable
CPU:[x]ms min
BIOS will deassert DDR_RESET#
PCH: No min/max requirement
AND
PCH t1001
30us, 1, 2or 5ms
=PCH_PWROK & SYS_PWROK &
t1001 Timer expired & internal_ready
T
?
DMI training CPU_RESET_DONE
CPU_RESET_DONE_ACK
+5VDUAL
5
4
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Power On Sequence
Power On Sequence
Power On Sequence
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
572Monday, December 06, 2010
572Monday, December 06, 2010
572Monday, December 06, 2010
A00
A00
A00
5
RepairLap.com
4
3
2
1
PCH
On-Die PLL Voltage Regulator Voltage Select
HDA_SYNC
High
STRAPPING Table
D D
CPU side
CFG[17:0] Description
[2]
[6:5]
PCI Express static x16
lane numbering reversal
PCI Express Bifurcation
1: normal
0: lane numbers reversed
00: 1x8, 2x4 PCI Express
01: reserved
10: 2x8 PCI Express
11: 1x16 PCI Express
Default
Default
Clock Gen.
FREQ
C C
133
PIN NAME
PCI2/TME
(PIN4)
PCI4/SRC5_EN
(PIN6)
PCIF5/ITP_EN
(PIN7)
PCI3/CFGP
(PIN5)
B B
C_CK_BSEL0 C_CK_BSEL1 C_CK_BSEL2
1100
100
NET
C_CK505_33M_PCI2
C_CK505_33M_PCI4
C_CK505_33M_PCI5
C_CK505_33M_PCI3
01
Strapping description
Overclocking DISABLED
1
Overclocking ENABLED
0
SRC5
1
CPU_STOP# and PCI_STOP#
0
CPU_ITP
1
SRC8
0
See CFG Table
(Set SATA and SRC come from PLL4)
Low
See CFG Table
Mid
See CFG Table
High
Default
DEFAULT
DEFAULT
DEFAULT
DEFAULT
SIO SMSC5544
PIN NAME
GP070 / PWM4
(PIN127)
DTR1# [TEST_EN]
/GP051
(PIN104)
A A
NET
O_SPEAKER
O_DTR1#_R
Strapping description
Disable
Diag_En
1
0
1
0
Enable
Diag_En
PE BOOT Loader Strap (DTR1#)= Load from SPI
PE BOOT Loader Strap (DTR1#)= No Load from SPI
DEFAULT
DEFAULT
Low
On-Die PLL Voltage Regulator
GPIO28
(IN-PU)
High
Low
Topblock Swap Mode
GNT3#/GPIO55
(IN-PU)
High
Low
No Reboot Mode
SPKR
(IN-PD)
High
Low
Integrated 1.05V VRM
INTVRMEN
High
Low
TLS Confidentiality
GPIO15
(IN-PD)
High
Low
Flash Descriptor Override Strap
HDA_SDO
High
Low
DMI Rx Termination Voltage
SPI_MOSI
(IN-PD)
Low
DMI Termination Voltage
NV_CLE
(IN-PU)
High
Description
1.5V
1.8V
Description
Regulator is enabled.
Regulator is disabled.
Description
Topblock swap mode: Disable
Topblock swap mode: Enable
Description
No reboot mode: Enable
No reboot mode: Disable
Description
Integrated 1.05V VRM: Enable
Integrated 1.05V VRM: Disable
Description
ME Crypto TLS cipher suite
with confidentiality
ME Crypto TLS cipher suite
with no confidentiality
Description
Flash descriptor security
will be override
Disable ME in Manufacturing Mode
Description
DMI Rx Termination Voltage
Description
DMI and FDI Tx/Rx
Termination Voltage
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
Boot BIOS Destination Selection
GNT1#
(IN-PU)
Low
High
Low
High
Integrated Clocking Strap
GPIO8
(IN-PU)
High
Low
Deep S4/S5 Well on-die Voltage Regulator Enable
DSWVRMEN
High
Low
Digital Port C Strap
DDPC_CTRLDATA
High
Low
SATA1GP/GP19
(IN-PU)
Low
Low
High
High
Description
Buffer Through Mode
Enable Integrated Clock Chip
Description
Enable
Disable
Description
Configure Port C
Disable
Description
Flash cycle routed to LPC
Flash cycle routed to PCI
Flash cycle routed to NAND
Flash cycle routed to SPI
DEFAULT
DEFAULT
DEFAULT
DEFAULT
5
4
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
GPIO/IRQ/IDSEL Table
GPIO/IRQ/IDSEL Table
GPIO/IRQ/IDSEL Table
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
772Monday, December 06, 2010
772Monday, December 06, 2010
772Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
D D
C C
4
3
2
1
B B
A A
Title
Title
5
4
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
GPIO Table
GPIO Table
GPIO Table
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
A00
A00
A00
870Monday, December 06, 2010
870Monday, December 06, 2010
870Monday, December 06, 2010
5
RepairLap.com
C_PE_100M_MCP(27)
C_PE_100M_MCP#(27)
H_VIDSCLK
RH2 change to 44.2 ;
D D
Change net name to
H_RESET#-12/28/09
Add off-page toXDP; CRB 0.7
12/27/09
C C
CRB0.7 12/07/09
H_CFG0(52)
H_CPU_DIMM_VREF_B(18)
H_CPU_DIMM_VREF_A(16)
H_VIDSOUT
H_VIDALERT#
+1P05V_VCCIO
H_PWRGD(24,52,64)
H_PM_SYNC(23)
H_PECI(23,32)
H_PROCHOT#(32,68)
H_THERMTRIP#(23)
H_SKTOCC#(23,24)
RH10 1.5KDummy
RH10 1.5KDummy
*
*
RH11 1.5KDummy
RH11 1.5KDummy
*
*
RH12 1.5KDummy
RH12 1.5KDummy
*
*
RH13 1.5KDummy
RH13 1.5KDummy
*
*
RH14 1.5KDummy
RH14 1.5KDummy
*
*
RH15 1.5KDummy
RH15 1.5KDummy
*
*
RH16 1.5KDummy
RH16 1.5KDummy
*
*
RH19 1.5KDummy
RH19 1.5KDummy
*
*
RH20 1.5KDummy
RH20 1.5KDummy
*
*
RH22 1.5KDummy
RH22 1.5KDummy
*
*
RH24 1.5KDummy
RH24 1.5KDummy
*
*
RH26 1.5KDummy
RH26 1.5KDummy
*
*
RH28 1.5KDummy
RH28 1.5KDummy
*
*
RH29 1.5KDummy
RH29 1.5KDummy
*
*
RH30 1.5KDummy
RH30 1.5KDummy
*
*
RH31 1.5KDummy
RH31 1.5KDummy
*
*
RH32 1.5KDummy
RH32 1.5KDummy
*
*
RH33 1.5KDummy
RH33 1.5KDummy
*
*
RH2 44.2Ohm
RH2 44.2Ohm
RH1 49.9
RH1 49.9
20100308: Remove RH51,RH58
H_PWRGD
*
*
RH58
RH58
1K
B B
20100709: Reserve RH58 connect H_PWRGD to GND
20100721: Mount RH58
A A
1K
H_VIDSCLK(68)
H_VIDSOUT(68)
H_VIDALERT#(68)
Remove CH1,CH2-12/29/09
RH39 change to 110 ohm; CRB 0.7-11/30/09
5
*
*
+/-1%
+/-1%
*
*
+/-1%Dummy
+/-1%Dummy
H_RESET#_R
H_CATERR
H_PROC_SEL
H_CFG0
H_CFG1
H_CFG2
H_CFG3
H_CFG4
H_CFG5
H_CFG6
H_CFG7
H_CFG8
H_CFG9
H_CFG10
H_CFG11
H_CFG12
H_CFG13
H_CFG14
H_CFG15
H_CFG16
H_CFG17
RH38
RH38
91 Ohm
91 Ohm
+/-1%
+/-1%
Dummy
Dummy
*
*
4
RH39
RH39
110Ohm
110Ohm
4
20100913: update CPU socket PN from M disk
UH1E
UH1E
W2
BCLK0
W1
BCLK0*
C37
VIDSCLK
B37
VIDSOUT
A37
VIDALERT*
J40
UNCOREPWRGOOD
F36
RESET*
E38
PM_SYNC
J35
PECI
E37
CATERR*
H34
PROCHOT*
G35
THERMTRIP*
AJ33
SKTOCC*
K32
PROC_SEL
H36
CFG0
J36
CFG1
J37
CFG2
K36
CFG3
L36
CFG4
N35
CFG5
L37
CFG6
M36
CFG7
J38
CFG8
L35
CFG9
M38
CFG10
N36
CFG11
N38
CFG12
N39
CFG13
N37
CFG14
N40
CFG15
G37
CFG16
G36
CFG17
A38
NCTF0
AU40
NCTF1
AW38
NCTF2
C2
NCTF3
D1
NCTF4
AH1
FC_AH1
AH4
FC_AH4
AV1
RSVD_NCTF0
AW2
RSVD_NCTF1
AY3
RSVD_NCTF2
R34
RSVD40
R36
RSVD41
R38
RSVD42
R40
RSVD43
J31
RSVD44
AD34
RSVD45
AD35
RSVD46
K31
RSVD47
PE115527-4041-0DF
PE115527-4041-0DF
+1P05V_VCCIO
*
*
RH40
RH40
75
75
+/-1%
+/-1%
+/-1%
+/-1%
5/10
5/10
*
*
VCCSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
VCCAXG_SENSE
VSSAXG_SENSE
MISC
MISC
VCCP_SELECT
VCCSA_VID
VCC_SENSE
VSS_SENSE
3
TDO
TCK
TMS
TRST*
PRDY*
PREQ*
DBR*
RSVD36
RSVD0
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
P34
T2
A36
B36
AB4
AB3
L32
M32
L39
L40
TDI
M40
L38
J39
K38
K40
E39
C40
D40
H40
H38
G38
G40
G39
F38
E40
F40
AB6
AB7
AD37
AE6
AF4
20100107:
AG4
Remove test points
AJ11
AJ29
AJ30
AJ31
AN20
AP20
AT11
AT14
AU10
AV34
AW34
AY10
C38
C39
D38
H7
H8
J33
J34
J9
K34
K9
L31
L33
L34
L9
M34
N33
N34
P33
H_VCCIO_SEL
P35
P37
P39
+5V
*
*
RH37
RH37
10K
10K
*
*
RH34
RH34
4.7K
4.7K
H_VCCSA_VID (70)
H_VCCSA_SENSE (70)
H_VCC_SENSE (68)
H_VSS_SENSE (68)
H_VCCTT_SENSE (70)
H_VSSTT_SENSE (70)
H_VCCAGX_SENSE (68)
H_VSSAGX_SENSE (68)
H_TDO (52)
H_TDI (52)
H_TCK (52)
H_TMS (52)
H_TRST# (52)
H_PRDY# (52)
H_PREQ# (52)
H_ITPCLK (52)
H_ITPCLK# (52)
H_BPM#0 (52)
H_BPM#1 (52)
H_BPM#2 (52)
H_BPM#3 (52)
H_BPM#4 (52)
H_BPM#5 (52)
H_BPM#6 (52)
H_BPM#7 (52)
H_VCCIO_SEL (70)
Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09
3
RH9 0
RH9 0
*
*
2
+1P05V_VCCIO
RO40change reference to
RH7 and move from SIO to
CPU side ; CRB
0.7-12/29/09
+3V_S5
RH66
RH66
*
*
220
220
+/-5%
+/-5%
Dummy
Dummy
Add RH66 pull-up to +3V_DUAL;
CRB 0.7-12/10/09
H_RESET#(32)
S_PLTRST#(24,32,34,46,52,53)
FP_RST# (24,52,53)
RH35 0
RH35 0
*
*
Dummy
Dummy
+3V_DUAL
CH2 0.1uFCH2 0.1uF
53
UH2
UH2
1
2
74AHCT1G08GW
74AHCT1G08GW
M_NVR_CLE(25)
RH17 change to 4.7k; CRB 0.7-11/30/09
20100709: Reserve CH11 connect H_PROC_SEL to GND
2
1
RH4 usage 1kOhm ; CRB 0.7-12/10/09
Removed RH3; CRB 0.7-12/29/09
Dummy RH6 ; CRB 0.7-12/28/09
Removed RH7; CRB 0.7-12/10/09
20100203: Dummy RH5; Intel update
*
*
*
*
*
*
*
RH4
RH4
RH7
RH7
51 Ohm
51 Ohm
1K
1K
Dummy
Dummy
Close to XDP
Conn
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
RH61 178 Ohm
RH61 178 Ohm
4
RH17
RH17
4.7K
4.7K
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Close to
CPU
*
*
+/-1%
+/-1%
+V_NAND_IO
*
*
*
*
RH18 51 Ohm
RH18 51 Ohm
RH21 51 Ohm
RH21 51 Ohm
RH23 51 Ohm
RH23 51 Ohm
RH25 51 Ohm
RH25 51 Ohm
RH27 51 Ohm
RH27 51 Ohm
RH60
RH60
2.2K
2.2K
*
RH5
RH5
RH6
RH6
51 Ohm
51 Ohm
51 Ohm
51 Ohm
Dummy
Dummy
Dummy
Dummy
+1P05V_VCCIO
*
*
*
*
*
*
*
*
*
*
RH62
RH62
*
*
75
75
+/-1%
+/-1%
20100104: add UH2 to prevent SIO
can't use
CPU-1: MISC
CPU-1: MISC
CPU-1: MISC
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
H_RESET#_R (52)
H_PROC_SEL
CH11
CH11
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
1
972Monday, December 06, 2010
972Monday, December 06, 2010
972Monday, December 06, 2010
H_PROCHOT#
H_PECI
H_THERMTRIP#
H_CATERR
A00
A00
A00
5
RepairLap.com
D D
H_FDI_FSYNC0(25)
H_FDI_LSYNC0(25)
H_FDI_FSYNC1(25)
H_FDI_LSYNC1(25)
H_FDI_INT(25)
RH41 24.9
RH41 24.9
*
+1P05V_VCCIO
C C
*
+/-1%
+/-1%
UH1D
UH1D
AC5
FDI_FSYNC0
AC4
FDI_LSYNC0
AE5
FDI_FSYNC1
AE4
FDI_LSYNC1
AG3
FDI_INT
AE2
FDI_COMPIO
AE1
FDI_ICOMPO
PE115527-4041-0DF
PE115527-4041-0DF
4/10
4/10
FDI
FDI
FDI_TX0
FDI_TX0*
FDI_TX1
FDI_TX1*
FDI_TX2
FDI_TX2*
FDI_TX3
FDI_TX3*
FDI_TX4
FDI_TX4*
FDI_TX5
FDI_TX5*
FDI_TX6
FDI_TX6*
FDI_TX7
FDI_TX7*
AC8
AC7
AC2
AC3
AD2
AD1
AD4
AD3
AD7
AD6
AE7
AE8
AF3
AF2
AG2
AG1
4
H_FDI_TXP0 (25)
H_FDI_TXN0 (25)
H_FDI_TXP1 (25)
H_FDI_TXN1 (25)
H_FDI_TXP2 (25)
H_FDI_TXN2 (25)
H_FDI_TXP3 (25)
H_FDI_TXN3 (25)
H_FDI_TXP4 (25)
H_FDI_TXN4 (25)
H_FDI_TXP5 (25)
H_FDI_TXN5 (25)
H_FDI_TXP6 (25)
H_FDI_TXN6 (25)
H_FDI_TXP7 (25)
H_FDI_TXN7 (25)
3
UH1C
UH1C
B11
B12
D12
D11
C10
E10
C9
E9
B8
B7
C6
C5
A5
A6
E2
E1
F4
F3
G2
G1
H3
H4
J1
J2
K3
K4
L1
L2
M3
M4
N1
N2
PEG_RX0
PEG_RX0*
PEG_RX1
PEG_RX1*
PEG_RX2
PEG_RX2*
PEG_RX3
PEG_RX3*
PEG_RX4
PEG_RX4*
PEG_RX5
PEG_RX5*
PEG_RX6
PEG_RX6*
PEG_RX7
PEG_RX7*
PEG_RX8
PEG_RX8*
PEG_RX9
PEG_RX9*
PEG_RX10
PEG_RX10*
PEG_RX11
PEG_RX11*
PEG_RX12
PEG_RX12*
PEG_RX13
PEG_RX13*
PEG_RX14
PEG_RX14*
PEG_RX15
PEG_RX15*
PEG
PEG
PEG_TX0
PEG_TX0*
PEG_TX1
PEG_TX1*
PEG_TX2
PEG_TX2*
PEG_TX3
PEG_TX3*
PEG_TX4
PEG_TX4*
PEG_TX5
PEG_TX5*
PEG_TX6
PEG_TX6*
PEG_TX7
PEG_TX7*
PEG_TX8
PEG_TX8*
PEG_TX9
PEG_TX9*
PEG_TX10
PEG_TX10*
PEG_TX11
PEG_TX011
PEG_TX12
PEG_TX12*
PEG_TX13
PEG_TX13*
PEG_TX14
PEG_TX14*
PEG_TX15
PEG_TX15*
C13
C14
E14
E13
G14
G13
F12
F11
J14
J13
D8
D7
D3
C3
E6
E5
F8
F7
G10
G9
G5
G6
K7
K8
J5
J6
M8
M7
L6
L5
N5
N6
2
1
H_DMI_RXP0(22)
H_DMI_RXN0(22)
H_DMI_RXP1(22)
H_DMI_RXN1(22)
H_DMI_RXP2(22)
H_DMI_RXN2(22)
H_DMI_RXP3(22)
H_DMI_RXN3(22)
B B
A A
W5
DMI_RX0
W4
DMI_RX0*
V3
DMI_RX1
V4
DMI_RX1*
Y3
DMI_RX2
Y4
DMI_RX2*
AA4
DMI_RX3
AA5
DMI_RX3*
P3
PE_RX0
P4
PE_RX0*
R2
PE_RX1
R1
PE_RX1*
T4
PE_RX2
T3
PE_RX2*
U2
PE_RX3
U1
PE_RX3*
PE115527-4041-0DF
PE115527-4041-0DF
3/10
3/10
DMI
DMI
GEN
GEN
PEG_COMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_TX0
DMI_TX0*
DMI_TX1
DMI_TX1*
DMI_TX2
DMI_TX2*
DMI_TX3
DMI_TX3*
PE_TX0
PE_TX0*
PE_TX1
PE_TX1*
PE_TX2
PE_TX2*
PE_TX3
PE_TX3*
V7
V6
W7
W8
Y6
Y7
AA7
AA8
P8
P7
T7
T8
R6
R5
U5
U6
B4
B5
C4
RH42 24.9
RH42 24.9
*
*
+/-1%
+/-1%
H_DMI_TXP0 (22)
H_DMI_TXN0 (22)
H_DMI_TXP1 (22)
H_DMI_TXN1 (22)
H_DMI_TXP2 (22)
H_DMI_TXN2 (22)
H_DMI_TXP3 (22)
H_DMI_TXN3 (22)
+1P05V_VCCIO
5
4
Title
Title
Title
CPU-2: FDI/PCIe/DMI
CPU-2: FDI/PCIe/DMI
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU-2: FDI/PCIe/DMI
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
10 72Monday, December 06, 2010
10 72Monday, December 06, 2010
10 72Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
D D
C C
1 2
RH8
D3_RESET#(15,17)
Add RC
filter;CRB
0.7-11/30/09
B B
A A
5
RH8
Dummy
Dummy
CH47
CH47
*
*
0.1uF
0.1uF
Dummy
Dummy
4
D3_MAA[15..0](15)
D3_WEA#(15)
D3_CASA#(15)
D3_RASA#(15)
D3_BAA[2..0](15)
D3_SCS_A#0(15)
D3_SCS_A#1(15)
D3_CKE_A0(15)
D3_CKE_A1(15)
D3_ODT_A0(15)
D3_ODT_A1(15)
D3_MA_CLK0(15)
D3_MA_CLK#0(15)
D3_MA_CLK1(15)
D3_MA_CLK#1(15)
RH51 120Ohm
H_DRAMPWRGD(24)
RH51 120Ohm
20100503: Add RH51 ,for PDG1.01
4
D3_MAA0
D3_MAA1
D3_MAA2
D3_MAA3
D3_MAA4
D3_MAA5
D3_MAA6
D3_MAA7
D3_MAA8
D3_MAA9
D3_MAA10
D3_MAA11
D3_MAA12
D3_MAA13
D3_MAA14
D3_MAA15
D3_BAA0
D3_BAA1
D3_BAA2
*
*
+/-5%
+/-5%
H_SM_VREF
UH1A
UH1A
AV27
AY24
AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22
AV28
AU21
AT21
AW32
AU20
AT20
AW29
AV30
AU28
AY29
AW28
AV20
AU29
AV32
AW30
AU33
AV19
AT19
AU18
AV18
AV31
AU32
AU30
AW33
AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26
AW18
AJ19
AJ22
AV13
AV12
AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12
PE115527-4041-0DF
PE115527-4041-0DF
3
20100913: update CPU socket PN from M disk
AK3
DDR_A
DDR_A
1/10
1/10
SA_DQS0
SA_DQS0*
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQS1
SA_DQS1*
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQS2
SA_DQS2*
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQS3
SA_DQS3*
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQS4
SA_DQS4*
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQS5
SA_DQS5*
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQS6
SA_DQS6*
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQS7
SA_DQS7*
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AK2
AJ3
AJ4
AL3
AL4
AJ2
AJ1
AL2
AL1
AP3
AP2
AN1
AN4
AR3
AR4
AN2
AN3
AR2
AR1
AW4
AV4
AV2
AW3
AV5
AW5
AU2
AU3
AU5
AY5
AV8
AW8
AY7
AU7
AV9
AU9
AV7
AW7
AW9
AY9
AV37
AV36
AU35
AW37
AU39
AU36
AW35
AY36
AU38
AU37
AP38
AP39
AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AK38
AK39
AL40
AL37
AJ38
AJ37
AL39
AL38
AJ39
AJ40
AF38
AF39
AG40
AG37
AE38
AE37
AG39
AG38
AE39
AE40
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_WE*
SA_CAS*
SA_RAS*
SA_BS0
SA_BS1
SA_BS2
SA_CS0*
SA_CS1*
SA_CS2*
SA_CS3*
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_CK0
SA_CK0*
SA_CK1
SA_CK1*
SA_CK2
SA_CK2*
SA_CK3
SA_CK3*
SM_DRAMRST*
SM_DRAMPWROK
SM_VREF
SA_DQS8
SA_DQS8*
SA_ECC_CB0
SA_ECC_CB1
SA_ECC_CB2
SA_ECC_CB3
SA_ECC_CB4
SA_ECC_CB5
SA_ECC_CB6
SA_ECC_CB7
3
D3_DQ_A0
D3_DQ_A1
D3_DQ_A2
D3_DQ_A3
D3_DQ_A4
D3_DQ_A5
D3_DQ_A6
D3_DQ_A7
D3_DQ_A8
D3_DQ_A9
D3_DQ_A10
D3_DQ_A11
D3_DQ_A12
D3_DQ_A13
D3_DQ_A14
D3_DQ_A15
D3_DQ_A16
D3_DQ_A17
D3_DQ_A18
D3_DQ_A19
D3_DQ_A20
D3_DQ_A21
D3_DQ_A22
D3_DQ_A23
D3_DQ_A24
D3_DQ_A25
D3_DQ_A26
D3_DQ_A27
D3_DQ_A28
D3_DQ_A29
D3_DQ_A30
D3_DQ_A31
D3_DQ_A32
D3_DQ_A33
D3_DQ_A34
D3_DQ_A35
D3_DQ_A36
D3_DQ_A37
D3_DQ_A38
D3_DQ_A39
D3_DQ_A40
D3_DQ_A41
D3_DQ_A42
D3_DQ_A43
D3_DQ_A44
D3_DQ_A45
D3_DQ_A46
D3_DQ_A47
D3_DQ_A48
D3_DQ_A49
D3_DQ_A50
D3_DQ_A51
D3_DQ_A52
D3_DQ_A53
D3_DQ_A54
D3_DQ_A55
D3_DQ_A56
D3_DQ_A57
D3_DQ_A58
D3_DQ_A59
D3_DQ_A60
D3_DQ_A61
D3_DQ_A62
D3_DQ_A63
2
D3_DQS_A0 (15)
D3_DQS_A#0 (15)
D3_DQ_A[63..0] (15)
D3_DQS_A1 (15)
D3_DQS_A#1 (15)
D3_DQS_A2 (15)
D3_DQS_A#2 (15)
D3_DQS_A3 (15)
D3_DQS_A#3 (15)
D3_DQS_A4 (15)
D3_DQS_A#4 (15)
D3_DQS_A5 (15)
D3_DQS_A#5 (15)
D3_DQS_A6 (15)
D3_DQS_A#6 (15)
D3_DQS_A7 (15)
D3_DQS_A#7 (15)
2
1
+1P5V_SM
RH43
RH43
*
*
100 Ohm
100 Ohm
+/-1%
+/-1%
H_SM_VREF(13)
RH44
RH44
CH3
CH3
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
RH43,RH44 usage 100 Ohm follow CRB;
CRB 0.7-12/10/09
Title
Title
Title
CPU-3: DDR3_CHA
CPU-3: DDR3_CHA
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU-3: DDR3_CHA
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
0.1uF
0.1uF
*
*
100 Ohm
100 Ohm
+/-1%
+/-1%
RH43,RH44 is 1k
in PDG; 100 in
CRB
11 72Monday, December 06, 2010
11 72Monday, December 06, 2010
11 72Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
D3_MAB[15..0](17)
D D
D3_WEB#(17)
D3_CASB#(17)
D3_RASB#(17)
D3_BAB[2..0](17)
D3_SCS_B#0(17)
D3_SCS_B#1(17)
D3_CKE_B0(17)
D3_CKE_B1(17)
C C
B B
A A
D3_ODT_B0(17)
D3_ODT_B1(17)
D3_MB_CLK0(17)
D3_MB_CLK#0(17)
D3_MB_CLK1(17)
D3_MB_CLK#1(17)
5
D3_MAB0
D3_MAB1
D3_MAB2
D3_MAB3
D3_MAB4
D3_MAB5
D3_MAB6
D3_MAB7
D3_MAB8
D3_MAB9
D3_MAB10
D3_MAB11
D3_MAB12
D3_MAB13
D3_MAB14
D3_MAB15
D3_BAB0
D3_BAB1
D3_BAB2
AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16
AR25
AK25
AP24
AP23
AM24
AW17
AN25
AN26
AL25
AT26
AU16
AY15
AW15
AV15
AL26
AP26
AM26
AK26
AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21
AN16
AN15
AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15
4
UH1B
UH1B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_WE*
SB_CAS*
SB_RAS*
SB_BS0
SB_BS1
SB_BS2
SB_CS0*
SB_CS1*
SB_CS2*
SB_CS3*
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_CK0
SB_CK0*
SB_CK1
SB_CK1*
SB_CK2
SB_CK2*
SB_CK3
SB_CK3*
SB_DQS8
SB_DQS8*
SB_ECC_CB0
SB_ECC_CB1
SB_ECC_CB2
SB_ECC_CB3
SB_ECC_CB4
SB_ECC_CB5
SB_ECC_CB6
SB_ECC_CB7
PE115527-4041-0DF
PE115527-4041-0DF
4
DDR_B
DDR_B
2/10
2/10
SB_DQS0
SB_DQS0*
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQS1
SB_DQS1*
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQS2
SB_DQS2*
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQS3
SB_DQS3*
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQS4
SB_DQS4*
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQS5
SB_DQS5*
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQS6
SB_DQS6*
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQS7
SB_DQS7*
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AH7
AH6
AG7
AG8
AJ9
AJ8
AG5
AG6
AJ6
AJ7
AM8
AL8
AL7
AM7
AM10
AL10
AL6
AM6
AL9
AM9
AR8
AP8
AP7
AR7
AP10
AR10
AP6
AR6
AP9
AR9
AN13
AN12
AM12
AM13
AR13
AP13
AL12
AL13
AR12
AP12
AN29
AN28
AR28
AR29
AL28
AL29
AP28
AP29
AM28
AM29
AP33
AR33
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AL33
AM33
AM32
AM31
AL35
AL32
AM34
AL31
AM35
AL34
AG35
AG34
AH35
AH34
AE34
AE35
AJ35
AJ34
AF33
AF35
D3_DQ_B0
D3_DQ_B1
D3_DQ_B2
D3_DQ_B3
D3_DQ_B4
D3_DQ_B5
D3_DQ_B6
D3_DQ_B7
D3_DQ_B8
D3_DQ_B9
D3_DQ_B10
D3_DQ_B11
D3_DQ_B12
D3_DQ_B13
D3_DQ_B14
D3_DQ_B15
D3_DQ_B16
D3_DQ_B17
D3_DQ_B18
D3_DQ_B19
D3_DQ_B20
D3_DQ_B21
D3_DQ_B22
D3_DQ_B23
D3_DQ_B24
D3_DQ_B25
D3_DQ_B26
D3_DQ_B27
D3_DQ_B28
D3_DQ_B29
D3_DQ_B30
D3_DQ_B31
D3_DQ_B32
D3_DQ_B33
D3_DQ_B34
D3_DQ_B35
D3_DQ_B36
D3_DQ_B37
D3_DQ_B38
D3_DQ_B39
D3_DQ_B40
D3_DQ_B41
D3_DQ_B42
D3_DQ_B43
D3_DQ_B44
D3_DQ_B45
D3_DQ_B46
D3_DQ_B47
D3_DQ_B48
D3_DQ_B49
D3_DQ_B50
D3_DQ_B51
D3_DQ_B52
D3_DQ_B53
D3_DQ_B54
D3_DQ_B55
D3_DQ_B56
D3_DQ_B57
D3_DQ_B58
D3_DQ_B59
D3_DQ_B60
D3_DQ_B61
D3_DQ_B62
D3_DQ_B63
3
D3_DQS_B0 (17)
D3_DQS_B#0 (17)
D3_DQ_B[63..0] (17)
D3_DQS_B1 (17)
D3_DQS_B#1 (17)
D3_DQS_B2 (17)
D3_DQS_B#2 (17)
D3_DQS_B3 (17)
D3_DQS_B#3 (17)
D3_DQS_B4 (17)
D3_DQS_B#4 (17)
D3_DQS_B5 (17)
D3_DQS_B#5 (17)
D3_DQS_B6 (17)
D3_DQS_B#6 (17)
D3_DQS_B7 (17)
D3_DQS_B#7 (17)
3
2
Title
Title
Title
CPU-4: DDR3_CHB
CPU-4: DDR3_CHB
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU-4: DDR3_CHB
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
A00
A00
A00
12 72Monday, December 06, 2010
12 72Monday, December 06, 2010
12 72Monday, December 06, 2010
1
5
RepairLap.com
+VCORE +1P05V_VCCIO +1P5V_SM
UH1F
UH1F
A12
VCC_1
A13
VCC_2
A14
VCC_3
A15
VCC_4
D D
C C
B B
A A
S_SMBDATA_PCI(16,18,24,32,40)
S_SMBCLK_PCI(16,18,24,32,40)
5
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
CD50
CD50
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
PE115527-4041-0DF
PE115527-4041-0DF
CPU POWER
CPU POWER
6/10
6/10
+3V_S5
1
4
3
F31
VCC_81
F32
VCC_82
F33
VCC_83
F34
VCC_84
G15
VCC_85
G16
VCC_86
G18
VCC_87
G19
VCC_88
G21
VCC_89
G22
VCC_90
G24
VCC_91
G25
VCC_92
G27
VCC_93
G28
VCC_94
G30
VCC_95
G31
VCC_96
G32
VCC_97
G33
VCC_98
H13
VCC_99
H14
VCC_100
H15
VCC_101
H16
VCC_102
H18
VCC_103
H19
VCC_104
H21
VCC_105
H22
VCC_106
H24
VCC_107
H25
VCC_108
H27
VCC_109
H28
VCC_110
H30
VCC_111
H31
VCC_112
H32
VCC_113
J12
VCC_114
J15
VCC_115
J16
VCC_116
J18
VCC_117
J19
VCC_118
J21
VCC_119
J22
VCC_120
J24
VCC_121
J25
VCC_122
J27
VCC_123
J28
VCC_124
J30
VCC_125
K15
VCC_126
K16
VCC_127
K18
VCC_128
K19
VCC_129
K21
VCC_130
K22
VCC_131
K24
VCC_132
K25
VCC_133
K27
VCC_134
K28
VCC_135
K30
VCC_136
L13
VCC_137
L14
VCC_138
L15
VCC_139
L16
VCC_140
L18
VCC_141
L19
VCC_142
L21
VCC_143
L22
VCC_144
L24
VCC_145
L25
VCC_146
L27
VCC_147
L28
VCC_148
L30
VCC_149
M14
VCC_150
M15
VCC_151
M16
VCC_152
M18
VCC_153
M19
VCC_154
M21
VCC_155
M22
VCC_156
M24
VCC_157
M25
VCC_158
M27
VCC_159
M28
VCC_160
M30
VCC_161
UD5
UD5
Dummy
Dummy
VDD
SDA
SCL
ISL90727WIE627Z-TK
ISL90727WIE627Z-TK
RW
RH
GND
5
6
2
4
20100115: Add DDR3 adjustable DQ
VREF for CPU and DIMMs
+1P5V_SM
RD30 12.1K
RD30 12.1K
*
*
+/-1%
+/-1%
Dummy
Dummy
4
*
*
RD31
RD31
12.1K
12.1K
+/-1%
+/-1%
Dummy
Dummy
3
+V_VCCSA
UH1G
UH1G
A11
VCCIO_1
A7
VCCIO_2
AA3
VCCIO_3
AB8
VCCIO_4
AF8
VCCIO_5
AG33
VCCIO_6
AJ16
VCCIO_7
AJ17
VCCIO_8
AJ26
VCCIO_9
AJ28
VCCIO_10
AJ32
VCCIO_11
AK15
VCCIO_12
AK17
VCCIO_13
AK19
VCCIO_14
AK21
VCCIO_15
AK23
VCCIO_16
AK27
VCCIO_17
AK29
VCCIO_18
AK30
VCCIO_19
B9
VCCIO_20
D10
VCCIO_21
D6
VCCIO_22
E3
VCCIO_23
E4
VCCIO_24
G3
VCCIO_25
G4
VCCIO_26
J3
VCCIO_27
J4
VCCIO_28
J7
VCCIO_29
J8
VCCIO_30
L3
VCCIO_31
L4
VCCIO_32
L7
VCCIO_33
M13
VCCIO_34
N3
VCCIO_35
N4
VCCIO_36
N7
VCCIO_37
R3
VCCIO_38
R4
VCCIO_39
R7
VCCIO_40
U3
VCCIO_41
U4
VCCIO_42
U7
VCCIO_43
V8
VCCIO_44
W3
VCCIO_45
7/10
7/10
PE115527-4041-0DF
PE115527-4041-0DF
+5V_S5
84
5
+
+
7
6
-
-
UD6B
UD6B
LM358
LM358
20100118: Add UD6B
Dummy
Dummy
+5V_S5
*
*
84
3
+
+
1
2
-
-
UD6A
UD6A
LM358
LM358
Dummy
CD47
CD47
*
*
100pF
100pF
Dummy
Dummy
Dummy
H10
VCCSA_1
H11
VCCSA_2
H12
VCCSA_3
J10
VCCSA_4
K10
VCCSA_5
K11
VCCSA_6
L11
VCCSA_7
L12
VCCSA_8
M10
VCCSA_9
M11
VCCSA_10
M12
VCCSA_11
CPU POWER
CPU POWER
AK11
VCCPLL_1
AK12
VCCPLL_2
CD48
CD48
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
RD32 2.2
RD32 2.2
RD26
RD26
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
3
+1P8V_SFR
CH4
CH4
*
*
1uF
1uF
+/-10%
+/-10%
*
*
Dummy
Dummy
20100317: add CH10 connect
to +1P8V_SFR
CH10
CH10
*
*
1uF
1uF
+/-10%
+/-10%
Dummy
Dummy
CH5
CH5
*
*
4.7uF
4.7uF
+/-10%
+/-10%
CLOSE TO CPU CLOSE TO CPU
RD33 0
RD33 0
*
*
Dummy
CD49
CD49
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
Dummy
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
+1P1V_AXG
CH6
CH6
*
*
0.1uF
0.1uF
H_SM_VREF (11)
2
AB33
VAXG_1
AB34
VAXG_2
AB35
VAXG_3
AB36
VAXG_4
AB37
VAXG_5
AB38
VAXG_6
AB39
VAXG_7
AB40
VAXG_8
AC33
VAXG_9
AC34
VAXG_10
AC35
VAXG_11
AC36
VAXG_12
AC37
VAXG_13
AC38
VAXG_14
AC39
VAXG_15
AC40
VAXG_16
T33
VAXG_17
T34
VAXG_18
T35
VAXG_19
T36
VAXG_20
T37
VAXG_21
T38
VAXG_22
T39
VAXG_23
T40
VAXG_24
U33
VAXG_25
U34
VAXG_26
U35
VAXG_27
U36
VAXG_28
U37
VAXG_29
U38
VAXG_30
U39
VAXG_31
U40
VAXG_32
W33
VAXG_33
W34
VAXG_34
W35
VAXG_35
W36
VAXG_36
W37
VAXG_37
W38
VAXG_38
Y33
VAXG_39
Y34
VAXG_40
Y35
VAXG_41
Y36
VAXG_42
Y37
VAXG_43
Y38
VAXG_44
CH7
CH7
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
2
UH1H
UH1H
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
MCH POWER
MCH POWER
VDDQ_21
VDDQ_22
VDDQ_23
8/10
8/10
PE115527-4041-0DF
PE115527-4041-0DF
1
AJ13
VDDQ_1
AJ14
VDDQ_2
AJ20
VDDQ_3
AJ23
VDDQ_6
AJ24
VDDQ_4
AR20
VDDQ_5
AR21
VDDQ_7
AR22
VDDQ_8
AR23
VDDQ_9
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28
+1P5V_SM+1P05V_VCCIO
CH9
CH8
CH8
*
*
22uF
22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
Title
Title
Title
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CH9
*
*
22uF
22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CPU-5: Power
CPU-5: Power
CPU-5: Power
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
13 72Monday, December 06, 2010
13 72Monday, December 06, 2010
13 72Monday, December 06, 2010
A00
A00
A00
5
RepairLap.com
UH1I
UH1I
A17
VSS_1
A23
VSS_2
A26
VSS_3
A29
VSS_4
A35
VSS_5
AA33
VSS_6
AA34
VSS_7
D D
C C
B B
A A
AA35
AA36
AA37
AA38
AA6
AB5
AC1
AC6
AD33
AD36
AD38
AD39
AD40
AD5
AD8
AE3
AE33
AE36
AF1
AF34
AF36
AF37
AF40
AF5
AF6
AF7
AG36
AH2
AH3
AH33
AH36
AH37
AH38
AH39
AH40
AH5
AH8
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36
AJ5
AK1
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK4
AK40
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36
AL5
AM1
AM11
AM14
AM17
AM2
AM21
AM23
AM25
5
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
9/10
9/10
PE115527-4041-0DF
PE115527-4041-0DF
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
GND
GND
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
AM27
AM3
AM30
AM36
AM37
AM38
AM39
AM4
AM40
AM5
AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
4
B39 update to RSVD48;
PDG 0.7-12/07/09
EDS: B39 defined "VSS_NCTF"
CRB: B39 defined "RSVD"
Pin_B39 follow CRB pin define;
CRB 0.7-12/10/09
4
TPH99TPH99
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10
AV11
AV14
AV17
AV3
AV35
AV38
AV6
AW10
AW11
AW14
AW16
AW36
AW6
AY11
AY14
AY18
AY35
AY4
AY6
AY8
C11
C12
C17
C20
C23
C26
C29
C32
C35
D17
D20
D23
D26
D29
D32
D37
D39
AV39
AY37
B10
B13
B14
B17
B23
B26
B29
B32
B35
B38
E11
E12
E17
E20
E23
E26
E29
E32
E36
F10
F13
F14
F17
F20
F23
F26
F29
F35
B39
B6
C7
C8
D2
D4
D5
D9
E7
E8
F1
F2
A4
B3
3
UH1J
UH1J
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
RSVD48
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
10/10
10/10
PE115527-4041-0DF
PE115527-4041-0DF
3
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
GND
GND
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
F37
F39
F5
F6
F9
G11
G12
G17
G20
G23
G26
G29
G34
G7
G8
H1
H17
H2
H20
H23
H26
H29
H33
H35
H37
H39
H5
H6
H9
J11
J17
J20
J23
J26
J29
J32
K1
K12
K13
K14
K17
K2
K20
K23
K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8
2
UH1_1
UH1_1
Backplate
Backplate
20100310: UH1_1 CPU Socket update Dell P/N to PT44A11-640D
20101103: UH1_1 CPU Socket update P/N to PT44A69-640D
Title
Title
Title
CPU-6: GND
CPU-6: GND
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU-6: GND
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
A00
A00
A00
14 72Monday, December 06, 2010
14 72Monday, December 06, 2010
14 72Monday, December 06, 2010
1
5
RepairLap.com
CHANNEL A BANK 1
SMB ADDRESS:000
4
3
2
1
143
144
DQS10
DM2/DQS11
D3_DQS_A[7..0] (11)
D3_DQS_A#[7..0] (11)
203
204
152
153
DQS12
DQS11
DM4/DQS13
DM3/DQS12
+1P5V_SM
D3_DQ_A[63..0] (11)
D3_DQ_A63
D3_DQ_A62
D3_DQ_A61
D3_DQ_A60
D3_DQ_A59
D3_DQ_A58
D3_DQ_A57
D3_DQ_A56
D3_DQ_A55
D3_DQ_A54
D3_DQ_A53
D3_DQ_A52
D3_DQ_A51
D3_DQ_A50
D3_DQ_A49
D3_DQ_A48
D3_DQ_A47
D3_DQ_A46
D3_DQ_A45
D3_DQ_A44
D3_DQ_A43
D3_DQ_A42
D3_DQ_A41
D3_DQ_A40
D3_DQ_A39
D3_DQ_A38
D3_DQ_A37
D3_DQ_A36
D3_DQ_A35
D3_DQ_A34
D3_DQ_A33
D3_DQ_A32
D3_DQ_A31
D3_DQ_A30
D3_DQ_A29
D3_DQ_A28
D3_DQ_A27
D3_DQ_A26
D3_DQ_A25
D3_DQ_A24
D3_DQ_A23
D3_DQ_A22
D3_DQ_A21
D3_DQ_A20
D3_DQ_A19
D3_DQ_A18
D3_DQ_A17
D3_DQ_A16
D3_DQ_A15
D3_DQ_A14
D3_DQ_A13
D3_DQ_A12
D3_DQ_A11
D3_DQ_A10
D3_DQ_A9
D3_DQ_A8
D3_DQ_A7
D3_DQ_A6
D3_DQ_A5
D3_DQ_A4
D3_DQ_A3
D3_DQ_A2
D3_DQ_A1
D3_DQ_A0
131
132
137
138
140
141
146
147
149
150
155
156
200
201
206
207
209
210
215
216
100
105
106
218
219
224
225
108
109
114
115
227
228
233
DQ57
A14
171
DQ58
A15
DQ59
168
DQ60
RESET
DQ61
CAS74RAS
192
234
DQ62
73
DQ63
WE
DIMM1
DIMM1
DDRIII
DDRIII
D3_WEA# (11)
D3_RASA# (11)
D3_CASA# (11)
D3_RESET# (11,17)
122
123
128
129
161
162
230
231
221
222
212
213
DQ03DQ14DQ29DQ310DQ4
DQS17
DQS15
DQS14
DQS13
DM5/DQS14
NC/DQS16
DM8/DQS17
DM7/DQS16
DM6/DQS15
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
197
194
191
189
186
183
182
179
176
173
170
S_SMBCLK_MAIN(17,20,32,52)
S_SMBDATA_MAIN(17,20,32,52)
D3_BAA[2..0](11)
D3_CKE_A1(11)
D3_CKE_A0(11)
D3_SCS_A#1(11)
D3_SCS_A#0(11)
D3_MA_CLK#1(11)
D3_MA_CLK1(11)
D3_MA_CLK#0(11)
D3_MA_CLK0(11)
D3_MAA[15..0](11)
13
DQ5
DQ6
DQ7
DQ812DQ9
DQ1018DQ1119DQ12
DQ13
DQ14
DQ15
DQ1621DQ1722DQ1827DQ1928DQ20
DDRIII
DDRIII
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
+3V
D3_CA_VREF_A
D3_DQ_VREF_A
D3_BAA2
D3_BAA1
D3_BAA0
D3_MAA0
D3_MAA1
D3_MAA2
D3_MAA3
D3_MAA4
D3_MAA5
D3_MAA6
D3_MAA7
D3_MAA8
D3_MAA9
D3_MAA10
D3_MAA11
D3_MAA12
D3_MAA13
D3_MAA14
D3_MAA15
VREFDQ1SCL
VREFCA
67
236
118
238
SDA
119
000
DQ21
SA2
237
DQ22
SA1
117
DQ23
DQ2430DQ2531DQ2636DQ2737DQ28
SA0
BA2
52
190
DQ29
BA071BA1
DQ30
DQ31
DQ3281DQ3382DQ3487DQ3588DQ36
CKE050CKE1
169S0193
DQ37
DQ38
DQ39
S176CK1/NU64CK1/NU63CK0*
DQ4090DQ4191DQ4296DQ4397DQ44
CK0
185
184A0188A1181
DQ45
A261A3
180
DQ46
DQ47
DQ4899DQ49
A459A558A6
178
DQ50
DQ51
A756A9
A8
175
177
DQ52
DQ53
A10/AP70A1155A12
DQ54
174
DQ55
196
DQ56
A13
172
D3_ODT_A1 (11)
D3_ODT_A0 (11)
D D
D3_DQS_A#7
D3_DQS_A#6
D3_DQS_A#5
D3_DQS_A#4
D3_DQS_A#3
D3_DQS_A#2
D3_DQS_A#1
D3_DQS_A#0
D3_DQS_A2
D3_DQS_A1
D3_DQS_A0
RSVD
FREE1
187
195
ODT177ODT0
FREE2
FREE349FREE4
48
68
53
167
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VTT
VTT
239
235
232
120
240
229
VSS
VSS
226
223
158
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
VSS
VSS
VSS
VSS
220
217
214
211
159
VSS
208
164
CB<5>
VSS
205
CB<6>
VSS
6
165
DQS07DQS0
CB<7>
VSS
VSS
VSS
VSS
202
199
166
163
160
VSS
24
15
DQS225DQS2
DQS116DQS1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
157
154
151
148
145
142
139
79
C C
198
+1P5V_SM_VTT
D3_DQS_A3
136
DQS334DQS3
VSS
D3_DQS_A5
D3_DQS_A4
84
33
DQS485DQS4
VSS
VSS
VSS
VSS
VSS
133
130
127
124
121
D3_DQS_A7
D3_DQS_A6
112
103
102
93
DQS6
DQS6
DQS594DQS5
VSS
VSS
VSS
VSS
VSS
116
113
110
107
104
101
125
134
135
126
42
111
DQS9
DQS843DQS8
DQS7
DQS7
DM0/DQS9
DM1/DQS10
VSS
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
CLOSE TO DIMM POWER PIN
+1P5V_SM
CD3
CD2
CD1
CD1
*
*
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
B B
+1P5V_SM_VTT
CD8
CD8
*
*
4.7uF
4.7uF
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
CD2
*
*
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
CD9
CD9
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CD3
*
*
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
CD10
CD10
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CD4
CD4
*
*
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
+3V
*
*
20100104: Remove CD5 10uF
SA_BS[0]-->Pin 71 (BA0)
SA_BS[1]-->Pin 190 (BA1)
SA_BS[2]-->Pin 52 (BA2)
; CRB 0.7-12/10/09
CD6
CD6
1uF
1uF
+/-10%
+/-10%
CD7
CD7
*
*
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
PLAECE CLOSE TO CH-A DIMM
+1P5V_SM
RD1 1K
RD1 1K
*
Dummy
Dummy
*
*
CD11
CD11
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
*
+/-1%
+/-1%
CD12
CD12
RD2
RD2
*
*
*
*
0.1uF
0.1uF
1K
1K
16V, X7R, +/-10%
16V, X7R, +/-10%
+/-1%
+/-1%
D3_DQ_VREF_A (16)
Add CD52,CD53; follow CRB 0.7-12/28/09
A A
+1P5V_SM
RD3 1K
RD3 1K
*
*
CD13
CD13
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Change to 0.1uF; PDG 0.7-12/07/09
*
*
+/-1%
+/-1%
RD4
RD4
*
*
*
*
1K
1K
+/-1%
+/-1%
5
CD14
CD14
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Del CD52,CD53-12/29/09
D3_CA_VREF_A
CD51
CD51
*
*
2.2uF
2.2uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
Change to 0.1uF; PDG 0.7-12/07/09
20100317: add CD51, should be near RD4, follow PDG1.0
20100512: CD51 change package size to 0603
20100519: CD51 change to 2.2uf and mount
Add CD47 , CD48, CD49, CD50, CD51 and Dummy;
CRB 0.7-12/10/09
Del CD47 , CD48, CD49, CD50, CD51 and Dummy;
CRB 0.7-12/29/09
4
Add RD25; PDG 0.7-12/07/09
D3_DQ_VREF_A
D3_CA_VREF_A
20100317: add RD27,should be near RD4, follow PDG1.0
20100319: RD27 change to 0402 size
3
RD25 0
RD25 0
RD27 0
RD27 0
*
*
Dummy
Dummy
Dummy
Dummy
D3_DQ_VREF_B (17,18)
D3_DQ_VREF_B_CA (17,18)
2
Title
Title
Title
DDR3 Conn: CHA_1 (DIMM1)
DDR3 Conn: CHA_1 (DIMM1)
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 Conn: CHA_1 (DIMM1)
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
15 72Monday, December 06, 2010
15 72Monday, December 06, 2010
15 72Monday, December 06, 2010
1
A00
A00
A00
5
RepairLap.com
D D
C C
4
3
2
1
B B
RD12
RD12
100pF
100pF
Dummy
Dummy
+5V_S5
3
+
+
2
-
-
84
*
*
UD2A
UD2A
LM358
LM358
Dummy
Dummy
1
RD5
RD5
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
RD7 2.2
RD7 2.2
RD10
RD10
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
20100706: mount RD6
RD6 0
RD6 0
*
*
RD8 0
RD8 0
*
*
*
Dummy
Dummy
*
*
3
Dummy
Dummy
CD24
CD24
1uF
1uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
*
CD52
CD52
*
*
0.1uF
0.1uF
Dummy
Dummy
Add CD52,CD53; follow CRB 0.7-12/28/09
H_CPU_DIMM_VREF_A (9)
D3_DQ_VREF_A (15)
CD53
CD53
*
*
0.1uF
0.1uF
Dummy
Dummy
Title
Title
Title
DDR3 Conn: CHA_DQ_VREF
DDR3 Conn: CHA_DQ_VREF
DDR3 Conn: CHA_DQ_VREF
DWG NO Rev
DWG NO Rev
DWG NO Rev
Katsiki_USFF
Katsiki_USFF
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Katsiki_USFF
1
16 72Monday, December 06, 2010
16 72Monday, December 06, 2010
16 72Monday, December 06, 2010
A00
A00
A00
+3V_S5
GND
+1P5V_SM
5
RW
6
RH
2
CD21
CD21
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
A A
Dummy
S_SMBDATA_PCI(13,18,24,32,40)
S_SMBCLK_PCI(13,18,24,32,40)
5
UD1
UD1
Dummy
Dummy
1
VDD
4
SDA
3
SCL
ISL90728WIE627Z-TK
ISL90728WIE627Z-TK
20100115: Add DDR3 adjustable DQ
VREF for CPU and DIMMs
CD22 12.1K
CD22 12.1K
*
*
+/-1%
+/-1%
CD23
*
*
CD23
12.1K
12.1K
+/-1%
+/-1%
Dummy
Dummy
4
Dummy
Dummy
*
*
5
RepairLap.com
4
3
2
1
CHANNEL B BANK 1
SMB ADDRESS:010
D3_ODT_B1 (12)
D3_ODT_B0 (12)
D D
D3_DQS_B#3
D3_DQS_B#2
D3_DQS_B#1
D3_DQS_B0
D3_DQS_B#0
D3_DQS_B1
D3_DQS_B2
D3_DQS_B3
D3_DQS_B4
D3_DQS_B#4
D3_DQS_B5
D3_DQS_B#5
D3_DQS_B6
D3_DQS_B#6
D3_DQS_B7
D3_DQS_B#7
D3_DQS_B[7..0] (12)
D3_DQS_B#[7..0] (12)
D3_DQ_B[63..0] (12)
D3_DQ_B39
D3_DQ_B38
D3_DQ_B37
D3_DQ_B36
D3_DQ_B35
D3_DQ_B34
D3_DQ_B33
D3_DQ_B32
D3_DQ_B31
D3_DQ_B30
D3_DQ_B29
D3_DQ_B28
D3_DQ_B27
D3_DQ_B26
D3_DQ_B25
D3_DQ_B24
D3_DQ_B23
D3_DQ_B22
D3_DQ_B21
D3_DQ_B20
D3_DQ_B19
D3_DQ_B18
D3_DQ_B17
D3_DQ_B16
D3_DQ_B15
D3_DQ_B14
D3_DQ_B13
D3_DQ_B12
D3_DQ_B11
D3_DQ_B10
D3_DQ_B9
D3_DQ_B8
D3_DQ_B7
D3_DQ_B6
D3_DQ_B5
D3_DQ_B4
D3_DQ_B3
D3_DQ_B2
D3_DQ_B1
D3_DQ_B0
D3_DQ_B40
D3_DQ_B41
D3_DQ_B42
D3_DQ_B43
D3_DQ_B44
D3_DQ_B45
D3_DQ_B46
D3_DQ_B47
D3_DQ_B48
D3_DQ_B49
D3_DQ_B50
D3_DQ_B51
D3_DQ_B52
D3_DQ_B53
D3_DQ_B54
D3_DQ_B55
D3_DQ_B56
D3_DQ_B57
D3_DQ_B58
D3_DQ_B59
D3_DQ_B60
D3_DQ_B61
D3_DQ_B62
D3_DQ_B63
68
53
FREE349FREE4
48
167
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VTT
VTT
239
235
232
229
120
240
VSS
VSS
226
223
158
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
VSS
VSS
VSS
VSS
220
217
214
211
159
VSS
208
CB<5>
VSS
164
165
CB<6>
CB<7>
VSS
VSS
205
202
199
VSS
15
6
DQS225DQS2
DQS116DQS1
DQS07DQS0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
166
163
160
157
154
151
148
145
84
33
24
DQS485DQS4
DQS334DQS3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
142
139
136
133
130
127
124
121
112
103
102
93
DQS6
DQS6
DQS594DQS5
VSS
VSS
VSS
VSS
VSS
116
113
110
107
104
101
195
79
ODT177ODT0
RSVD
FREE1
C C
FREE2
198
187
+1P5V_SM_VTT
CLOSE TO DIMM POWER PIN
+1P5V_SM
CD27
CD25
CD25
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
+1P5V_SM_VTT
B B
CD29
CD29
*
*
4.7uF
4.7uF
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
CD26
CD26
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
CD30
CD30
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CD27
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
CD28
CD28
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
PLAECE CLOSE TO CH-B DIMM
+1P5V_SM
RD13 1K
RD13 1K
*
*
+/-1%
*
*
CD31
CD31
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
+/-1%
RD14
RD14
*
*
*
*
CD32
CD32
1K
1K
0.1uF
0.1uF
+/-1%
+/-1%
16V, X7R, +/-10%
16V, X7R, +/-10%
Change to 0.1uF; PDG 0.7-12/07/09
+1P5V_SM
RD15 1K
RD15 1K
*
A A
*
*
CD33
CD33
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
*
+/-1%
+/-1%
CD34
CD34
RD16
RD16
*
*
*
*
0.1uF
0.1uF
1K
1K
16V, X7R, +/-10%
16V, X7R, +/-10%
+/-1%
+/-1%
5
D3_DQ_VREF_B (15,18)
Add CD54,CD55; follow CRB 0.7-12/28/09
Del CD54,CD5512/29/09
D3_CA_VREF_B
CD56
CD56
*
*
2.2uF
2.2uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
Change to 0.1uF; PDG 0.7-12/07/09
20100317: add CD56, should be near RD16, follow PDG1.0
20100513: CD56 change package size to 0603
20100519: CD56 change to 2.2uf and mount
125
134
126
42
111
DQS9
DQS843DQS8
DQS7
DQS7
DM0/DQS9
VSS
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
SB_BS[0]-->Pin 71 (BA0)
SB_BS[1]-->Pin 190 (BA1)
SB_BS[2]-->Pin 52 (BA2)
; CRB 0.7-12/10/09
4
152
143
144
135
DQS11
DQS10
DM2/DQS11
DM1/DQS10
212
213
203
204
153
DQS14
DQS13
DQS12
DM5/DQS14
DM4/DQS13
DM3/DQS12
+1P5V_SM
122
123
128
129
161
162
230
231
221
222
DQ03DQ14DQ29DQ310DQ4
DQS15
DM6/DQS15
197
S_SMBCLK_MAIN(15,20,32,52)
S_SMBDATA_MAIN(15,20,32,52)
D3_MAB[15..0](12)
DQS17
NC/DQS16
DM8/DQS17
DM7/DQS16
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
194
191
189
186
183
182
179
176
173
170
D3_BAB[2..0](12)
D3_CKE_B1(12)
D3_CKE_B0(12)
D3_SCS_B#1(12)
D3_SCS_B#0(12)
D3_MB_CLK#1(12)
D3_MB_CLK1(12)
D3_MB_CLK#0(12)
D3_MB_CLK0(12)
D3_CA_VREF_B
13
DQ5
DQ6
DQ7
DQ812DQ9
DDRIII
DDRIII
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
D3_CA_VREF_B
D3_DQ_VREF_B
D3_BAB2
D3_BAB1
D3_BAB0
D3_MAB0
D3_MAB1
D3_MAB2
D3_MAB3
D3_MAB4
D3_MAB5
D3_MAB6
D3_MAB7
D3_MAB8
D3_MAB9
D3_MAB10
D3_MAB11
D3_MAB12
D3_MAB13
D3_MAB14
D3_MAB15
RD28 0
RD28 0
20100317: add RD28, should be near RD16
20100319: RD28 change to 0402 size
3
131
DQ1018DQ1119DQ12
+3V
*
*
Dummy
Dummy
132
137
DQ13
236
138
DQ14
DQ15
DQ1621DQ1722DQ1827DQ1928DQ20
VREFCA
67
VREFDQ1SCL
118
140
141
146
147
149
150
155
DQ21
DQ22
DQ23
DQ2430DQ2531DQ2636DQ2737DQ28
DQ29
SA2
SDA
SA1
SA0
BA071BA1
BA2
52
119
238
237
117
190
010
D3_DQ_VREF_B_CA (15,18)
156
DQ30
DQ31
DQ3281DQ3382DQ3487DQ3588DQ36
CKE050CKE1
169S0193
2
200
201
206
207
DQ37
DQ38
DQ39
S176CK1/NU64CK1/NU63CK0*
209
210
215
216
100
105
106
218
219
224
225
108
109
114
115
227
228
DQ4090DQ4191DQ4296DQ4397DQ44
DQ45
DQ46
DQ47
DQ4899DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
CK0
A261A3
A459A558A6
A756A9
A10/AP70A1155A12
A13
A14
A8
185
184A0188A1181
180
178
175
177
Title
Title
Title
DDR3 Conn: CHB_1 (DIMM2)
DDR3 Conn: CHB_1 (DIMM2)
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 Conn: CHB_1 (DIMM2)
A15
CAS74RAS
RESET
174
196
172
171
168
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
233
192
234
DQ62
73
DQ63
WE
DIMM2
DIMM2
DDRIII
DDRIII
1
D3_WEB# (12)
D3_RASB# (12)
D3_CASB# (12)
D3_RESET# (11,15)
17 72Monday, December 06, 2010
17 72Monday, December 06, 2010
17 72Monday, December 06, 2010
A00
A00
A00
5
RepairLap.com
D D
C C
4
3
2
1
B B
D3_DQ_VREF_B_R
20100317: add RD29, should be near RD13 , follow
PDG1.0follow PDG1.0
20100319: RD29 change to 0402 size
+3V_S5
CD43
CD43
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
A A
S_SMBDATA_PCI(13,16,24,32,40)
S_SMBCLK_PCI(13,16,24,32,40)
5
16V, X7R, +/-10%
Dummy
Dummy
UD3
UD3
1
VDD
4
SDA
3
SCL
ISL90727WIE627Z-TK
ISL90727WIE627Z-TK
RD29 0
RD29 0
*
*
Dummy
Dummy
20100115: Add DDR3 adjustable DQ
VREF for CPU and DIMMs
Dummy
Dummy
GND
+1P5V_SM
5
RW
6
RD21 12.1K
RH
RD21 12.1K
2
4
D3_DQ_VREF_B_CA (15,17)
*
*
+/-1%
+/-1%
RD23
Dummy
Dummy
*
*
RD23
12.1K
12.1K
+/-1%
+/-1%
Dummy
Dummy
+5V_S5
CD44
CD44
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
84
5
+
+
6
CD45
CD45
*
*
100pF
100pF
Dummy
Dummy
7
-
-
UD2B
UD2B
LM358
LM358
Dummy
Dummy
*
*
3
RD18
RD18
RD22
RD22
1K
1K
+/-1%
+/-1%
Dummy
Dummy
2.2
2.2
*
*
Dummy
Dummy
D3_DQ_VREF_B_R
CD46
CD46
1uF
1uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
Dummy
20100706: mount RD17
RD17 0
RD17 0
*
*
RD19
RD19
0
0
*
*
Dummy
Dummy
CD55
CD55
*
*
0.1uF
0.1uF
Dummy
Dummy
Add CD54,CD55; follow CRB 0.7-12/28/09
H_CPU_DIMM_VREF_B (9)
D3_DQ_VREF_B (15,17)
CD54
CD54
*
*
0.1uF
0.1uF
Dummy
Dummy
2
Title
Title
Title
DDR3 Conn: CHB_DQ_VREF
DDR3 Conn: CHB_DQ_VREF
DDR3 Conn: CHB_DQ_VREF
DWG NO Rev
DWG NO Rev
DWG NO Rev
Katsiki_USFF
Katsiki_USFF
Date: Sheet of
Date: Sheet of
Date: Sheet of
Katsiki_USFF
1
18 72Monday, December 06, 2010
18 72Monday, December 06, 2010
18 72Monday, December 06, 2010
A00
A00
A00
5
RepairLap.com
4
3
2
1
+3V_CLK
*
*
Dummy
Dummy
CC7
CC7
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN47
+3V_CLK+3V
*
*
Dummy
Dummy
CC8
CC8
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN53
RC32
RC32
15
15
+/-1%
+/-1%
Dummy
Dummy
QC1
QC1
C_V_OUT
RC36 33
RC36 33
*
*
Dummy
D D
Dummy
B
MMBT3904-7-F
MMBT3904-7-F
Dummy
Dummy
Dummy
Dummy
CC26
CC26
100pF
100pF
50V, NPO, +/-5%
50V, NPO, +/-5%
E C
FBC2 FB 100 Ohm
FBC2 FB 100 Ohm
CC27
CC27
*
*
10uF
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
Dummy
Dummy
*
*
*
*
+3V_CLK_IO
Dummy
Dummy
+3V_CLK
+3V_CLK
12
ECC1
ECC1
*
*
120uF
120uF
+/-20%
+/-20%
Dummy
Dummy
20100506: ECC1 removed for layout request
20100517: add ECC1 for Dell request
+3V_CLK_IO
*
*
CC1
CC1
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
FBC1 FB 100 Ohm
FBC1 FB 100 Ohm
*
*
Dummy
CC4
CC4
10uF
10uF
+/-10%
+/-10%
Dummy
Dummy
Dummy
*
*
Dummy
Dummy
CC2
CC2
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
*
*
CLOSE TO PIN2
Dummy
Dummy
CC3
CC3
0.1uF
0.1uF
CLOSE TO PIN9
16V, X7R, +/-10%
16V, X7R, +/-10%
*
*
Dummy
Dummy
CC5
CC5
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN16
*
*
Dummy
Dummy
CC6
CC6
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN31
Dummy CK505 circuit for Cost down
Add CK505 buffer thru mode circuit-20091225
- PCI4/SRC5_EN (Pin6) Output Mode select.
H=SRC5, L=CPU/PCI Stop#. Latch @ Power-On
- PCIF5/ITP_EN (Pin7) Output Mode Select.
H=CPU_ITP, L= SRC8. Latch @ Power-On
+3V +3V
*
*
*
*
RC1
RC1
RC2
RC2
10K
10K
10K
10K
Dummy
Dummy
Dummy
RC5
RC5
10K
10K
Dummy
Dummy
*
*
Dummy
RC6
RC6
10K
10K
Dummy
Dummy
C_CK505_33M_PCI5 C_CK505_33M_PCI2
*
*
Intel requirement stuff CR8
- PCI2/TME (Pin4) Trust Mode Enable.
H= overclocking disabled. Latch @
Power-On
- PCI3/CFGP (Pin5) Clock Config Strapping.
Details refer to CLK-Gen CFG table
Latch @ Power-On
*
*
*
*
C_CK505_33M_PCI3C_CK505_33M_PCI4
*
*
RC3
RC3
10K
10K
Dummy
Dummy
RC7
RC7
10K
10K
Dummy
Dummy
*
*
RC4
RC4
10K
10K
Dummy
Dummy
RC8
RC8
10K
10K
Dummy
Dummy
20100324: Dummy CK505 buffer thru mode circuit
+3V_CLK_IO
C C
+3V
B B
P_VR_READY_R
A A
*
*
*
*
RH3
RH3
7.5K
7.5K
+/-1%
+/-1%
Dummy
Dummy
RH46
RH46
3KOhm
3KOhm
+/-1%
+/-1%
Dummy
Dummy
FREQ
100
133
*
*
+3V_S5
4 3
CC18
CC18
10uF
10uF
+/-10%
+/-10%
Dummy
Dummy
*
*
5
CC19
CC19
*
*
10uF
10uF
+/-10%
+/-10%
Dummy
Dummy
RC94 10K
RC94 10K
Dummy
Dummy
RH36 7.5K
RH36 7.5K
CC38
CC38
1uF
1uF
+/-10%
+/-10%
Dummy
Dummy
RC92 10K
RC92 10K
16
2
BSEL0 BSEL1 BSEL2
1
CC23
CC23
*
*
10uF
10uF
+/-10%
+/-10%
Dummy
Dummy
*
*
4 3
*
*
+/-1%
+/-1%
Dummy
Dummy
*
*
Dummy
Dummy
QH1
QH1
MMDT5551
MMDT5551
Dummy
Dummy
RC91 10K
RC91 10K
01
001
5
CC24
CC24
*
*
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN12
Dummy
Dummy
Dummy
Dummy
16
2
QH2
QH2
MMDT5551
MMDT5551
Dummy
Dummy
5
P_VR_READY_R
S_SLP_S3# (24,32,64,66,67,70)
*
*
Dummy
Dummy
*
*
+3V_S5
+3V
CC20
CC20
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN20
10K
10K
RC86
RC86
Dummy
Dummy
C_CK_BSEL0
*
*
Dummy
Dummy
CC21
CC21
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN26
Dummy
Dummy
20100107: Swap net
name same as IC pin
out.
S_SMBCLK_MAIN(15,17,32,52)
S_SMBDATA_MAIN(15,17,32,52)
C_CK_BSEL1
*
*
RC89
RC89
10K
10K
Dummy
Dummy
CC22
CC22
*
*
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
CLOSE TO PIN37
Dummy
Dummy
XC1 XTAL-14.318MHz
XC1 XTAL-14.318MHz
1 2
Dummy
Dummy
CC28
CC28
*
*
27pF
27pF
+/-5%
+/-5%
Dummy
Dummy
CC25
CC25
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
+3V
*
*
*
*
4
CLOSE TO PIN41
*
*
CC29
CC29
27pF
27pF
+/-5%
+/-5%
Dummy
Dummy
10K
10K
RC87
RC87
Dummy
Dummy
10K
10K
RC95
RC95
Dummy
Dummy
*
*
C_CK_BSEL2
+3V_CLK
+3V_CLK_IO
C_V_OUT
C_XTAL_14M_IN
C_XTAL_14M_OUT
P_VR_READY_R
C_CK_BSEL1
CC34
CC34
CC35
CC35
*
*
22pF
22pF
22pF
22pF
Dummy
Dummy
Dummy
Dummy
UC1
UC1
16
VDD_PLL3
9
VDD_48MHZ
2
VDD_PCI
53
VDD_REF
31
VDD_SRC
47
VDD_CPU
12
VDD_IO
20
VDD_PLL3_IO
26
VDD_SRC_IO_1
37
VDD_SRC_IO_2
41
VDD_CPU_IO
40
IO_VOUT
52
XTAL_IN
51
XTAL_OUT
48
CKPWRGD/PD#
49
FSB/TEST_MODE
56
SCL
55
SDA
15
VSS_IO
19
VSS_PLL3
11
VSS_48MHZ
44
VSS_CPU
8
VSS_PCI
50
VSS_REF
23
VSS_SRC1
34
VSS_SRC2
IDTCV184-2APAG8
IDTCV184-2APAG8
Dummy
Dummy
CPUT0
CPUC0
CPUT1
CPUC1
SRCT8/CPU_ITPT
SRCC8/CPU_ITPC
46
45
43
42
39
C_CK505_ITP_R
38
C_CK505_ITP#_R
20100120: Remove RC9, RC10
TPC14TPC14
TPC17TPC17
and Add TPC14,TPC17
TPC9TPC9
TPC10TPC10
RC17 33Dummy
RC17 33Dummy
*
*
RC20 33Dummy
RC20 33Dummy
*
*
C_CK505_ITP (52)
C_CK505_ITP# (52)
Buffer thru mode
13
DOT96T/SRCT0
DOT96C/SRCC0
SRCT1/SE1
SRCC1/SE2
SATAT/SRCT2
SATAC/SRCC2
SRCT3/CR#_C
SRCC3/CR#_D
SRCT4
SRCC4
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
SRCT6
SRCC6
SRCT7/CR#_F
IDTCV184-2APAG8
IDTCV184-2APAG8
Dummy RC73 and add RC11
pull-up to +3V; CRB 0.7-12/28/09
P_VR_READY(24,33,52,64,68)
SRCC7/CR#_E
PCI4/SRC5_EN
PCI3/CFGP
PCI1/CR#_B
PCI0/CR#_A
PCIF5/ITP_EN
USB_48/FSA
REF/FSC/TEST_SEL
C_CK505_SRC5_DP
C_CK505_SRC5_DN
RC73 0
RC73 0
3
PCI2/TME
*
*
+/-5%Dummy
+/-5%Dummy
C_96M_PCH_R
14
C_96M_PCH#_R
17
18
21
C_SATA_PCH_R
22
C_SATA_PCH#_R
24
25
27
28
30
C_CK505_SRC5_DP
29
C_CK505_SRC5_DN
33
32
36
C_DMI_PCH_R
35
C_DMI_PCH#_R
6
C_CK505_33M_PCI4
5
C_CK505_33M_PCI3
4
C_CK505_33M_PCI2
3
C_CK505_33M_PCI1
1
C_CK505_33M_PCI0
7
C_CK505_33M_PCI5
10
C_CK_BSEL0
54
C_CK_BSEL2
RC90 10K
RC90 10K
*
*
Dummy
Dummy
RC93 10K
RC93 10K
*
*
Dummy
Dummy
+3V
*
*
RC11
RC11
1K
1K
+/-1%
+/-1%
Dummy
Dummy
P_VR_READY_RP_VR_READY_R
TPC1TPC1
TPC2TPC2
TPC5TPC5
TPC6TPC6
TPC3TPC3
TPC4TPC4
TPC15TPC15
TPC16TPC16
+3V_CLK
RC23 33Dummy
RC23 33Dummy
*
*
RC24 33Dummy
RC24 33Dummy
*
*
RC37 33Dummy
RC37 33Dummy
*
*
RC40 33Dummy
RC40 33Dummy
*
*
20100107: Swap pin 21/22 and pin27/28 pin out; PDG 0.8
20100120: Remove RC49, RC52
and Add TPC15,TPC16
20100107: Remove Test Point
RC55 33Dummy
RC55 33Dummy
*
*
RC58 33Dummy
RC58 33Dummy
*
*
C_96M_PCH (22,27)
C_96M_PCH# (22,27)
Buffer thru mode
C_SATA_PCH (23,27)
C_SATA_PCH# (23,27)
20100107: Dummy RC49,RC52; PDG 0.8
C_DMI_PCH (22,27)
C_DMI_PCH# (22,27)
Buffer thru mode
TPC11TPC11
TPC12TPC12
RC84 33
RC84 33
*
*
Dummy
Dummy
20100107: RC84 change to 33ohm; PDG 0.8
+3V
CC30
CC30
CC31
1uF
1uF
+/-10%
+/-10%
Dummy
Dummy
CC31
*
*
1uF
1uF
+/-10%
+/-10%
Dummy
Dummy
*
*
C_14M_MCH (27)
Buffer thru mode
CC32
CC32
*
1uF
1uF
+/-10%
+/-10%
Dummy
Dummy
*
*
*
2
CC33
CC33
Title
Title
Title
0.1uF
0.1uF
Dummy
Dummy
DWG NO Rev
DWG NO Rev
DWG NO Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Clock GEN
Clock GEN
Clock GEN
Katsiki_USFF
Katsiki_USFF
Katsiki_USFF
1
A00
A00
A00
20 72Monday, December 06, 2010
20 72Monday, December 06, 2010
20 72Monday, December 06, 2010
Loading...