Dell N4030-UMA Schematics

5

D D

4

3

2

1

DJ1 Calpella UMA Schematics Document

Arrandale

C C

Intel PCH

2010-04-23

REV : X01

B B

DY : Nopop Component

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

Cover Page

Cover Page

Cover Page

1

190Monday, April 26, 2010

190Monday, April 26, 2010

190Monday, April 26, 2010

of

of

of

X01

X01

X01

5

9

D D

Clock Generator

SLG8SP585

C C

CRT

LCD

55

LVDS(Dual Channel)

54

RGB CRT

CardReader

SD/MMC/MS/
MS Pro/xD

B B

71

Realtek
RTS5138

32

Azalia

Internal Analog MIC

HP1

MIC IN

CODEC

92HD79B1

30

4

3

DJ1 UMA Block Diagram

Project code : 91.4EK01.001
PCB P/N : 48.4EK19.0SB
Revision : 10212-SB

7

USB2.0

AZALIA

Intel CPU

Arrandale

DMIx4

14 USB 2.0/1.1 ports
High Definition Audio

PCI/PCI BRIDGE

20,21,22,23,24,25,26,27,28

SATA

8,9,10,11,12,13,14

Intel

PCH

SATA ports (6)
PCIE ports (8)

LPC I/F
ACPI 1.1

SATA

FDIx4x2(UMA)

PCIE

USB 2.0

SPI

DDRIII 800/1066 Channel A

DDRIII 800/1066 Channel B

PCIE x 1

PCIE x 1

USB 2.0 x 2

LPC Bus

SPI

KBC

NUVOTON

NPCE781BA0DX

DDRIII
800/1066

DDRIII
800/1066

I/O Board

Connector

76

Slot 0

18

Slot 1

19

Left Side:
USB x 1

Mini-Card

802.11a/b/g

USB 2.0 x 1

USB 2.0 x 1

USB 2.0 x 2

37

2

10/100 NIC

ATHEROS

AR8152/AR8151

CAMERA

Bluetooth

Right Side:
USB x 2

RJ45
CONN

54

73

63

1

CPU DC/DC

ISL62882

INPUTS

+PWR_SRC

OUTPUTS

+VCC_CORE

SYSTEM DC/DC

TPS51218

INPUTS

+PWR_SRC

OUTPUTS

+1.05V_VTT

SYSTEM DC/DC

RT8205BGQW

INPUTS

+PWR_SRC

OUTPUTS

+5V_ALW2
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
+15V_ALW

SYSTEM DC/DC

RT8207GQW

INPUTS

+PWR_SRC

OUTPUTS

+1.5V_SUS
+0.75V_DDR_VTT
+V_DDR_REF

SYSTEM DC/DC

TPS51611

INPUTS

+PWR_SRC

OUTPUTS

+CPU_GFX_CORE

MAXIM CHARGER

BQ24745

INPUTS

+DC_IN
+PBATT

26

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

APL5930

INPUTS

+3.3V_ALW

OUTPUTS

+1.8V_RUN

SYSTEM DC/DC

Switches

INPUTS OUTPUTS

26

+1.5V_SUS
+5V_ALW

+1.5V_RUN
+5V_RUN
+3.3V_RUN+3.3V_ALW

PCB LAYER

L1: Top
L2: VCC
L3: Signal
L4: Signal
L5 GND
L6: Bottom

47,48

49

46

50

53

51

42

3

A A

2CH SPEAKER

HDD

5

http://laptop-motherboard-schematic.blogspot.com/

4

ODD

5959

Flash ROM

4MB

62

Flash ROM

256kB

3

Touch
PAD

62

68

Int.
KB

Thermal

EMC2102

Fan

2

58

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

39

2568

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Block Diagram

Block Diagram

Block Diagram

X01

X01

X01

of

290Monday, April 19, 2010

of

290Monday, April 19, 2010

of

290Monday, April 19, 2010

1

5

D D

4

3

2

1

Adapter

AO4407A

Battery

+PWR_SRC TPS51116

TPS51611

22000mA

+CPU_GFX_CORE

Charger

BQ24745

ISL62882

48000mA 24800mA

+VCC_CORE

TPS51218

+1.05V_VTT

+PBATT

1000mA

+0.75V_DDR_VTT+V_DDR_REF

16825mA

+1.5V_SUS

AO4468

3500mA

C C

+1.5V_RUN

TPS51125

11145mA

10330mA82mA

+15V_ALW

B B

+3.3V_RTC_LDO

+5V_ALW2

G547F2P81U-GP

+5V_USB1

+5V_ALW

AO4468

+5V_RUN

G547F2P81U-GP

2000mA2000mA 6330mA

+5V_USB2

SI3456DDV

AO4468

6661mA

+3.3V_RUN

RTS5159

+3.3V_ALW

AO3403

APL5930

300mA 1761mA

+3.3V_LAN

+1.8V_RUN

2000mA 300mA

+LCDVDD

+3.3V_RUN_CARD

Power Shape

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

Regulator LDO Switch

3

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

2

Date: Sheet

Power Block Diagram

Power Block Diagram

Power Block Diagram

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

390Friday, Ap ril 16, 2010

390Friday, Ap ril 16, 2010

390Friday, Ap ril 16, 2010

of

of

1

of

X01

X01

X01

A

B

C

D

E

PCH SMBus Block Diagram

KBC SMBus Block Diagram

+5V_RUN

+3.3V_ALW

ǂ

1 1

SMBCLK

PCH_SMB_CLK

SMBDATA

PCH_SMB_DATA

2 2

PCH

ǂ

ǂ

SRN2K2J-1-GP

+3.3V_ALW

+3.3V_RUN

ǂ

DMN66D0LDW-7-GP

ǂ

SRN2K2J-1-GP

SML0CLK

SML0DATA

SML0_CLK

SML0_DATA

ǂ

ǂ

+3.3V_RUN

ǂ

SRN2K2J-1-GP

LDDC_CLK

L_DDC_CLK

LDDC_DATA

3 3

L_DDC_DATA

ǂ

ǂ

+3.3V_RUN

ǂ

SRN2K2J-1-GP

PCH_SMBCLK

ǂ

PCH_SMBDATA

ǂ

PCH_SMBCLK

ǂ

PCH_SMBDATA

ǂ

PCH_SMBCLK

ǂ

PCH_SMBDATA

ǂ

PCH_SMBCLK

ǂ

PCH_SMBDATA

ǂ

XDP

LCD CONN

DIMM 1

SCL

SDA

SMBus Address:A0

DIMM 2

SCL

SDA

SMBus Address:A4

Clock
Generator

SCLK

SDATA

SMBus address:D2

Minicard
WLAN

SMB_CLK

SMB_DATA

ǂ

SRN10KJ-5-GP

TouchPad Conn.

TPDATA

PSDAT1

TPCLKPSCLK1

18

19

7

76

NPCE781BA0DX

KBC

ǂ

SCL1

SDA1

GPIO61/SCL2

GPIO62/SDA2

BAT_SCL

BAT_SDA

KBC_SCL1

KBC_SDA1

+KBC_PWR

+3.3V_ALW

ǂ

ǂ

ǂ

SRN4K7J-8-GP

SRN4K7J-8-GP

SRN100J-3-GP

TPDATA

TPDATA

TPCLK

TPCLK

PBAT_SMBCLK1

PBAT_SMBDAT1

+3.3V_RUN

DMN66D0LDW-7-GP

Battery Conn.

CLK_SMB

SMBus address:16

DAT_SMB

BQ24745

SCL

SDA

SMBus address:12

+3.3V_RUN

ǂ

SRN4K7J-8-GP

ǂ

THERM_SCL

ǂ

THERM_SDA

ǂ

Thermal

SCL

SMBus address:7A

SDA

PCH

SML1DATA/GPIO75

SML1CLK/GPIO58

23

+3.3V_RUN

ǂ

SRN2K2J-1-GP

23

GMCH_DDCCLK

GMCH_DDCDATA

ǂ

ǂ

CRT_DDC_CLK

CRT_DDC_DATA

4 4

+3.3V_RUN

ǂ

DMN66D0LDW-7-GP

http://laptop-motherboard-schematic.blogspot.com/

A

+5V_CRT_RUN

ǂ

SRN2K2J-1-GP

ǂ

ǂ

B

DDC_CLK_CON

DDC_DATA_CON

CRT CONN

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Date: Sheet of

Date: Sheet of

C

D

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

SMBUS Block Diagram

SMBUS Block Diagram

SMBUS Block Diagram

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

E

490Friday, April 16, 2010

490Friday, April 16, 2010

490Friday, April 16, 2010

X01

X01

X01

A

B

C

D

E

Thermal Block Diagram

1 1

Audio Block Diagram

SPKR_PORT_D_L-

SPKR_PORT_D_R+

SPEAKER

Codec

DP1

EMC2102_DP1

SC470P50V3JN-2GP

2 2

DN1

EMC2102_DN1

SC470P50V3JN-2GP

MMBT3904-3-GP

Place near CPU

Thermal

and PCH.

ALC269Q_VB5

HP1_PORT_B_L

HP1_PORT_B_R

HP

OUT

EMC2102

EMC2102_DP1

DP2

DN2

MMBT3904-3-GP

EMC2102_DN1

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

System Sensor(UMA only)

3 3

MIC

IN

EMC2102_DP3

DP3

EMC2102_DN3

DN3

4 4

A

SC470P50V3JN-2GP

http://laptop-motherboard-schematic.blogspot.com/

B

MMBT3904-3-GP

Put under CPU.

PORTC_L

PORTC_R

VREFOUT_C

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

C

D

Date: Sheet

Analog
MIC

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chih,
Taipei Hsien 221, Taiwan, R. O .C.

Taipei Hsien 221, Taiwan, R. O .C.

Taipei Hsien 221, Taiwan, R. O .C.

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

E

of

of

of

590Friday, Apri l 16, 2010

590Friday, Apri l 16, 2010

590Friday, Apri l 16, 2010

X01

X01

X01

A

B

C

D

E

Calpella Schematic Checklist Rev.0_7

Name Schematics Notes

SPKR

4 4

3 3

INIT3_3V# Weak internal pull-down. Do not pull high.

GNT3#/
GPIO55

INTVRMEN

GNT0#,
GNT1#/GPIO51

GNT2#/
GPIO53

GPIO33

SPI_MOSI

NV_ALE

NC_CLE Weak internal pull-up. Do not pull low.

HAD_DOCK_EN#
/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high.

HDA_SYNC

GPIO15

GPIO8

GPIO27

2 2

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with

No Reboot Mode with TCO Disabled:

8.2-k- 10-k weak pull-up resistor.

Internal pull-up.

Default Mode:

(Connect to ground with 4.7-k weak

Low (0) = Top Block Swap Mode

pull-down resistor).

High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled

Left both GNT0# and GNT1# floating. No pull up

Default (SPI):

required.

Connect GNT1# to ground with 1-k

Boot from PCI:

pull-down resistor. Leave GNT0# Floating.

Connect both GNT0# and GNT1# to ground with

Boot from LPC:

1-k pull-down resistor.

Default - Internal pull-up.

= Configures DMI for ESI compatible operation (for servers

Low (0)

only. Not for mobile/desktops).

Do not pull low.

Default:

Connect to ground with 1-k

Disable ME in Manufacturing Mode:

pull-down resistor.

Connect to Vcc3_3 with 8.2-k weak pull- up resistor.

Enable iTPM:

Left floating, no pull-down required.

Disable iTPM:

Connect to Vcc3_3 with 8.2-k weak pull-up

Enable Danbury:

resistor.
Connect to ground with 4.7-k weak pull-down

Disable Danbury:

resistor.

Flash Descriptor Security will be overridden.

Low (0):

Flash Descriptor Security will be in effect.

High (1) :

Weak internal pull-down. Do not pull high.

Weak internal pull-down. Do not pull high.

Weak internal pull-up. Do not pull low.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.

ǂ

ǂ

ǂ

ǂ

Pin Name

CFG[4] Disabled - No Physical Display Port attached to

CFG[3]

CFG[0]

CFG[7]

Strap Description Configuration (Default value for each bit is

DisplayPort
Presence

PCI-Express Static
Lane Reversal

PCI-Express
Configuration
Select

Reserved ­Temporarily used
for early
Clarksfield
samples.

1 unless specified otherwise)

1:Embedded

Embedded DisplayPort.

Enabled - An external Display Port device is

0:

connected to the Embedded Display Port.

Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphics

1:

Bifurcation enabled

0:

-

Clarksfield (only for early samples pre-ES1)

Connect to GND with 3.01K Ohm/5% resistor

Only temporary for early CFD samples

Note:

(rPGA/BGA) [For details please refer to the WW33
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality.

Calpella Schematic Checklist Rev.0_7

Default
Value

1

1

1

0

Processor StrappingPCH Strapping

USB TablePCIE Routing

Pair

LANE2 MiniCard WLAN

LANE3 LAN

0

1

2

3

4

5

6

7

1 1

8

9

10

11

12

13

http://laptop-motherboard-schematic.blogspot.com/

A

USB

Device

USB0 (I/O Board)

X

USB2

USB3

X

WLAN (I/O Board)

X

X

X

BLUETOOTH

CARD READER

CAMERA

X

X

B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet

C

D

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Table of Content

Table of Content

690Friday, Ap ril 16, 2010

690Friday, Ap ril 16, 2010

690Friday, Ap ril 16, 2010

E

X01

X01

X01

of

of

5

SSID = CLOCK

4

3

2

1

+3.3V_RUN

D D

+3.3V_RUN

C C

CLK_PCIE_SATA#23

CLK_PCIE_SATA23

CLK_CPU_BCLK#23

CLK_CPU_BCLK23

B B

DY

DY

1 2

DREFCLK#23

DREFCLK23

CLKIN_DMI#23

CLKIN_DMI23

1 2

0R0603-PAD-1-GP

0R0603-PAD-1-GP

12

C701

C701

SC1U10V2KX-1GP

SC1U10V2KX-1GP

R701

R701

2K2R2J-2-GP

2K2R2J-2-GP

R708

R708

DY

DY

CPU_STOP#

12

C702

C702

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

0R4P2R-PAD

0R4P2R-PAD
RN701

RN701
0R4P2R-PAD

0R4P2R-PAD
RN702

RN702
0R4P2R-PAD

0R4P2R-PAD
RN703

RN703
0R4P2R-PAD

0R4P2R-PAD
RN704

RN704

12

C703

C703

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

2 3
1

2 3
1

2 3
1

1
2 3

12

C704

C704

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

4

RN

RN

4

RN

RN

RN

RN

4
4

RN

RN

12

C705

C705

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK_MCH_DREFCLK1#
CLK_MCH_DREFCLK1

CLK_IN_DMI#
CLK_IN_DMI

CLK_PCIE_SATA1#
CLK_PCIE_SATA1

CLK_CPU_BCLK1#
CLK_CPU_BCLK1

+3.3V_RUN_SL585

12

C707

C707

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U701

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

SLG8SP585VTR-GP

SLG8SP585VTR-GP

12

C708

C708

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

15

1

17

24

29

5

VDD_27

VDD_REF

VDD_DOT

VDD_SRC

VDD_CPU

GND

26

33

VSS_REF

21

VSS_SRC

VSS_CPU

12

VDD_SRC_IO

VSS_DOT

VSS_278VSS_SATA

2

18

VDD_CPU_IO

27MHZ

27MHZ_SS

CPU_STOP#

CKPWRGD/PD#

REF_0/CPU_SEL

XTAL_IN

XTAL_OUT

9

SDA
SCL

+1.05V_VTT

R709

R709

1 2

0R0603-PAD-1-GP

0R0603-PAD-1-GP

12

C709

C709

SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

DY

6
7

16
25
30

28
27

31
32

CPU_STOP#
CK_PWRGD
FSC

CLK_XTAL_IN
CLK_XTAL_OUT

PCH_SMBDATA

PCH_SMBCLK

12

R703

R703
33R2J-2-GP

33R2J-2-GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

PCH_SMBDATA 18,19,23,76
PCH_SMBCLK 18,19,23,76

12

C710

C710

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

EC701

EC701

DY

DY

12

12

C711

C711

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C712

C712

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK_PCH_14M 23

+1.05V_RUN_SL585_IO

FSC 0 1

X701

X701

1 2

12

X-14D31818M-37GP

5

X-14D31818M-37GP

82.30005.901

82.30005.901

C714

C714

SC12P50V2JN-3GP

SC12P50V2JN-3GP

A A

CLK_XTAL_OUTCLK_XTAL_IN

12

C715

C715
SC12P50V2JN-3GP

SC12P50V2JN-3GP

http://laptop-motherboard-schematic.blogspot.com/

+1.05V_VTT

DY

DY

1 2

1 2

4

R704

R704
4K7R2J-2-GP

4K7R2J-2-GP

R707

R707
10KR2J-3-GP

10KR2J-3-GP

SPEED

FSC

133MHz

(Default)

100MHz

+3.3V_RUN_SL585

<Core Design>

<Core Design>

R705

R705

10KR2J-3-GP

10KR2J-3-GP

CK_PWRGD

3

1 2

2N7002E-1-GP

2N7002E-1-GP

D

Q701

Q701

.....

.....

G

S

VR_CLKEN# 47

2

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Clock Generator SLG8SP585

Clock Generator SLG8SP585

Clock Generator SLG8SP585

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

790Thursday, April 22, 2010

790Thursday, April 22, 2010

790Thursday, April 22, 2010

1

X01

X01

X01

A

SSID = CPU

D D

C C

B B

5

4

3

2

1

Main:62.10053.601
2nd :62.10040.611
3rd :62.10055.321

1 OF 9

CPU1A

CPU1A

DMI_PTX_CRXN022
DMI_PTX_CRXN122
DMI_PTX_CRXN222
DMI_PTX_CRXN322

DMI_PTX_CRXP022
DMI_PTX_CRXP122
DMI_PTX_CRXP222
DMI_PTX_CRXP322

DMI_CTX_PRXN022
DMI_CTX_PRXN122
DMI_CTX_PRXN222
DMI_CTX_PRXN322

DMI_CTX_PRXP022
DMI_CTX_PRXP122
DMI_CTX_PRXP222
DMI_CTX_PRXP322

FDI_TXN022
FDI_TXN122
FDI_TXN222
FDI_TXN322
FDI_TXN422
FDI_TXN522
FDI_TXN622
FDI_TXN722

FDI_TXP022
FDI_TXP122
FDI_TXP222
FDI_TXP322
FDI_TXP422
FDI_TXP522
FDI_TXP622
FDI_TXP722

FDI_FSYNC022
FDI_FSYNC122

FDI_INT22

FDI_LSYNC022
FDI_LSYNC122

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17
F18

D17

DMI_RX0#
DMI_RX1#
DMI_RX2#
DMI_RX3#

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_TX0#
DMI_TX1#
DMI_TX2#
DMI_TX3#

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI_TX0#
FDI_TX1#
FDI_TX2#
FDI_TX3#
FDI_TX4#
FDI_TX5#
FDI_TX6#
FDI_TX7#

FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

AUBURNDALE

AUBURNDALE

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX0#
PEG_RX1#
PEG_RX2#

DMI

DMI

PEG_RX3#
PEG_RX4#
PEG_RX5#
PEG_RX6#
PEG_RX7#
PEG_RX8#

PEG_RX9#
PEG_RX10#
PEG_RX11#
PEG_RX12#
PEG_RX13#
PEG_RX14#
PEG_RX15#

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5

Intel(R) FDI

Intel(R) FDI

PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX0#
PEG_TX1#
PEG_TX2#
PEG_TX3#
PEG_TX4#
PEG_TX5#
PEG_TX6#
PEG_TX7#
PEG_TX8#
PEG_TX9#

PEG_TX10#
PEG_TX11#
PEG_TX12#
PEG_TX13#
PEG_TX14#
PEG_TX15#

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_IRCOMP_R

EXP_RBIAS

R801 49D9R2F-GPR801 49D9R2F-GP

1 2

R802 750R2F-GPR802 750R2F-GP

1 2

<Core Design>

<Core Design>

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

CPU (PCIE/DMI/FDI)

CPU (PCIE/DMI/FDI)

CPU (PCIE/DMI/FDI)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221, Taiwan, R.O.C.

of

890Thursday, April 22, 2010

890Thursday, April 22, 2010

890Thursday, April 22, 2010

1

X01

X01

X01

A

A

+1.05V_VTT

R902 49D9R2F-GPR902 49D9R2F-GP

R933 68R2-GPR933 68R2-GP

R904 68R2-GP

R904 68R2-GP

D D

C C

1119

B B

VDDPWRGOOD_R

+1.05V_VTT

12

C902

C902
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

DY

Processor Pullups

1 2

1 2

1 2

DY

DY

+1.5V_RUN

12

DY

DY

12

R937

R937
750R2F-GP

750R2F-GP

H_PWRGD

PM_PWRBTN#_R22

H_PWRGD_XDP

5

H_CATERR#

H_PROCHOT#

H_CPURST#

H_PECI25

H_THERMTRIP#25,37,42

H_PM_SYNC22

H_PWRGD25,42

PM_DRAM_PWRGD22

H_VTTPWRGD49

PLT_RST#21,37,70,76

S3 circuit

Normal

R919

R919
1K1R2F-GP

1K1R2F-GP

1 2

DY

DY

R927 1KR2J-1-GP

R927 1KR2J-1-GP

1 2

DY

DY

R929 0R2J-2-GP

R929 0R2J-2-GP

1 2

DY

DY

R930 0R2J-2-GP

R930 0R2J-2-GP

SML0_DATA23

SML0_CLK23

5

4

Processor Compensation Signals

1 2

R901 20R2F-GPR901 20R2F-GP

1 2

R903 20R2F-GPR903 20R2F-GP

1 2

R905 49D9R2F-GPR905 49D9R2F-GP

1 2

R906 49D9R2F-GPR906 49D9R2F-GP

TP901TPAD14-GP TP901TPAD14-GP

1

H_PROCHOT#47

H_CPURST#

R908

R908

1 2

0R0402-PAD

0R0402-PAD

H_PWRGD_XDP

R912

R912

1 2

0R0402-PAD

0R0402-PAD

R913

R913

1 2

1K6R2F-GP

1K6R2F-GP

H_COMP3
H_COMP2
H_COMP1
H_COMP0

SKTOCC#_R

H_CATERR#

VCCPWRGOOD

VDDPWRGOOD_R

PLT_RST#_R

12

R915

R915
750R2F-GP

750R2F-GP

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

CPU1B

CPU1B

COMP3
COMP2
COMP1
COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

SSID = CPU

R920R919

1.1k

1.27k 3k

XDP_PREQ#
XDP_PRDY#

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

XDP_OBS4
XDP_OBS5

XDP_OBS6
XDP_OBS7

H_CPUPWRGD_XDP
PM_PWRBTN#_XDP

PCIE_CLK_XDP_P

XDP_TCLK

0.75k

XDP1

XDP1

1 2
3 4

5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28

DY

DY

29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

PAD-60P-GP

PAD-60P-GP

NP1
61

62

63
64
NP2

U927

U927

1

B

VTT_PWRGD37,42,49

BCLK_ITP_P
BCLK_ITP_N

XDP_TRST#
XDP_TDI
XDP_TMS

2

A

3

GND

74LVC1G08GW -1-GP

74LVC1G08GW -1-GP

VDDPWRGOOD_KBC37

1 2

DY

DY

R931 1KR2J-1-GP

R931 1KR2J-1-GP

XDP_RST#_R

No Stuff

http://laptop-motherboard-schematic.blogspot.com/

4

3

2 OF 9

2 OF 9

A16

BCLK

B16

MISC

MISC

CLOCKS

CLOCKS

AUBURNDALE

AUBURNDALE

THERMAL PWR MANAGEMENT

THERMAL PWR MANAGEMENT

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

5

VCC

VTT_PWRGD_R3 VDDPWRGOOD_R

4

Y

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXT_TS0#
PM_EXT_TS1#

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPM6#
BPM7#

+3.3V_RUN

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

H_CPURST#XDP_RST#_R

1 2

DY

DY

R932 0R2J-2-GP

R932 0R2J-2-GP

TCK
TMS

TDI

TDO

R977

R977

1 2

1K6R2F-GP

1K6R2F-GP

R978

R978

1 2

DY

DY

1K6R2F-GP

1K6R2F-GP

C901

C901

AR30
AT30

E16
D16

A18
A17

F6
AL1

AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29
AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

+1.05V_VTT

12

DY

DY

3

BCLK_CPU_P_R
BCLK_CPU_N_R

BCLK_ITP_P
BCLK_ITP_N

PEG_CLK_R
PEG_CLK#_R

SM_DRAMRST#
SM_RCOMP_0

SM_RCOMP_1
SM_RCOMP_2

PM_EXTTS#0_C
PM_EXTTS#1_C

XDP_PRDY#
XDP_PREQ#

XDP_TCLK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

H_DBR#_R

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

12

R928

R928
51R2J-2-GP

51R2J-2-GP

XDP_TDO

PLT_RST# 21,37,70,76

1
2 3

1
2 3

R909

R909

1 2

0R0402-PAD

0R0402-PAD

2

RN

RN

RN901

RN901

4

0R4P2R-PAD

0R4P2R-PAD

RN

RN

RN903

RN903

4

0R4P2R-PAD

0R4P2R-PAD

0R4P2R-PAD

0R4P2R-PAD
RN906

RN906

XDP_DBRESET# 22

2

+1.05V_VTT

RN905

RN905

4

RN

RN

SRN10KJ-5-GP

SRN10KJ-5-GP

1
2 3

PM_EXTTS#0_C 53

XDP_DBRESET#

XDP_TDI_R

XDP_TDO_M

XDP_TDI_M

XDP_TDO_R

Scan Chain
(Default)
CPU Only

GMCH Only

1

DDR_RST_GATE 25

C915

C915

12

SCD047U16V2ZY-1GP

BCLK_CPU_P 25
BCLK_CPU_N 25

CLK_EXP_P 23
CLK_EXP_N 23

1
23

4

R921 0R2J-2-GP

R921 0R2J-2-GP

R922 0R2J-2-GP

R922 0R2J-2-GP

12

R924

R924
0R0402-PAD

0R0402-PAD

R925 0R2J-2-GP

R925 0R2J-2-GP

Stuff --> R921, R924, R926
No Stuff --> R922, R925
Stuff --> R921, R922
No Stuff --> R924, R926, R925
Stuff --> R926, R925
No Stuff --> R921, R922, R924

G

S

R935 0R2J-2-G P

R935 0R2J-2-G P

PM_EXTTS#0 18
PM_EXTTS#1 19

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

1 2

DY

DY

1 2

DY

DY

1 2

DY

DY

R926

R926

1 2

0R0402-PAD

0R0402-PAD

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

CPU (THERMAL/CLOCK/PM )

CPU (THERMAL/CLOCK/PM )

CPU (THERMAL/CLOCK/PM )

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

SCD047U16V2ZY-1GP

+1.5V_SUS

Q901

Q901

.....

.....

2N7002E-1-GP

2N7002E-1-GP

1 2

DY

DY

DDR3 Compensation Signal s

XDP_TMS
XDP_TDI_R
XDP_PREQ#

XDP_TCLK

12

D

12

SM_DRAMRST#

R907 100R2F-L1-GP-UR907 100R2F-L1-GP-U

1 2

R910 24D9R2F-L-GPR910 24D9R2F-L-GP

1 2

R911 130R2F-1-GPR911 130R2F-1-GP

1 2

1 2

R914 51R2J-2-GP

R914 51R2J-2-GP

1 2

R916 51R2J-2-GP

R916 51R2J-2-GP

1 2

R917 51R2J-2-GP

R917 51R2J-2-GP

1 2

R918 51R2J-2-GP

R918 51R2J-2-GP

XDP_TDI

XDP_TDO

JTAG MAPPING

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

R934

R934
1KR2J-1-GP

1KR2J-1-GP

DDR3_DRAMRST# 18,19

C903

C903
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

R988

R988
100KR2J-1-GP

100KR2J-1-GP

DY

DY
DY

DY
DY

DY
DY

DY

XDP_TRST#

990Thursday, April 22, 2010

990Thursday, April 22, 2010

990Thursday, April 22, 2010

1

of

+1.05V_VTT

12

R923

R923
51R2J-2-GP

51R2J-2-GP

X01

X01

X01

A

5

SSID = CPU

CPU1C

CPU1C

4

3 OF 9

3 OF 9

3

CPU1D

CPU1D

2

4 OF 9

4 OF 9

1

W8

AA6

SA_CK0

AA7

M_A_DQ[63..0]18

D D

C C

B B

M_A_DQ[63..0]

M_A_BS018
M_A_BS118
M_A_BS218

M_A_CAS#18
M_A_RAS#18
M_A_WE#18

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AG5

AJ10
AL10

AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11
AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14
AP14

A10
C10

B10
D10
E10

F10

H10

G10

AH5
AF5
AK6
AK7
AF6

AJ7
AJ6

AJ9

AL7
AL8

AC3
AB2

AE1
AB3
AE9

SA_DQ0
SA_DQ1

C7

SA_DQ2

A7

SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6

A8

SA_DQ7

D8

SA_DQ8
SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15
SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20
SA_DQ21

J7

SA_DQ22

J10

SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS0
SA_BS1

U7

SA_BS2

SA_CAS#
SA_RAS#
SA_WE#

SA_CK0#

P7

SA_CKE0

AUBURNDALE

AUBURNDALE

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK1
SA_CK1#
SA_CKE1

SA_CS0#
SA_CS1#

SA_ODT0
SA_ODT1

SA_DM0

SA_DM1

SA_DM2

SA_DM3

SA_DM4

SA_DM5

SA_DM6

SA_DM7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_MA0

SA_MA1

SA_MA2

SA_MA3

SA_MA4

SA_MA5

SA_MA6

SA_MA7

SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_CLK_DDR0 18
M_CLK_DDR#0 18
M_CKE0 18

M_CLK_DDR1 18
M_CLK_DDR#1 18
M_CKE1 18

M_CS#0 18
M_CS#1 18

M_ODT0 18
M_ODT1 18

M_B_DQ[63..0]19

M_A_DM[7..0] 18
M_A_DQS#[7..0] 18

M_A_DQS[7..0] 18
M_A_A[15..0] 18

M_B_DQ[63..0]

M_B_BS019
M_B_BS119
M_B_BS219

M_B_CAS#19
M_B_RAS#19
M_B_WE#19

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AF3
AG1

AK1
AG4
AG3

AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7

AP9
AR10
AT10

AB1

AC5

AC6

B5

SB_DQ0

A5

SB_DQ1

C3

SB_DQ2

B3

SB_DQ3

E4

SB_DQ4

A6

SB_DQ5

A4

SB_DQ6

C4

SB_DQ7

D1

SB_DQ8

D2

SB_DQ9

F2

SB_DQ10

F1

SB_DQ11

C2

SB_DQ12

F5

SB_DQ13

F3

SB_DQ14

G4

SB_DQ15

H6

SB_DQ16

G2

SB_DQ17

J6

SB_DQ18

J3

SB_DQ19

G1

SB_DQ20

G5

SB_DQ21

J2

SB_DQ22

J1

SB_DQ23

J5

SB_DQ24

K2

SB_DQ25

L3

SB_DQ26

M1

SB_DQ27

K5

SB_DQ28

K4

SB_DQ29

M4

SB_DQ30

N5

SB_DQ31
SB_DQ32
SB_DQ33

AJ3

SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37

AJ4

SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS0

W5

SB_BS1

R7

SB_BS2

SB_CAS#

Y7

SB_RAS#
SB_WE#

AUBURNDALE

AUBURNDALE

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK0
SB_CK0#
SB_CKE0

SB_CK1
SB_CK1#
SB_CKE1

SB_CS0#
SB_CS1#

SB_ODT0
SB_ODT1

SB_DM0

SB_DM1

SB_DM2

SB_DM3

SB_DM4

SB_DM5

SB_DM6

SB_DM7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_CLK_DDR2 19
M_CLK_DDR#2 19
M_CKE2 19

M_CLK_DDR3 19
M_CLK_DDR#3 19
M_CKE3 19

M_CS#2 19
M_CS#3 19

M_ODT2 19
M_ODT3 19

M_B_DM[7..0] 19
M_B_DQS#[7..0] 19

M_B_DQS[7..0] 19
M_B_A[15..0] 19

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

CPU (DDR)

CPU (DDR)

CPU (DDR)

1

of

10 90Thursday, April 22, 2010

10 90Thursday, April 22, 2010

10 90Thursday, April 22, 2010

X01

X01

X01

5

4

3

2

1

SSID = CPU

5 OF 9

CPU1E

CPU1E

D D

CFG0

CFG3

C C

CFG4

CFG7

B B

DY

DY

DY

DY

DY

DY

DY

DY

12

12

12

12

R1101

R1101
3KR2F-GP

3KR2F-GP

R1102

R1102
3KR2J-2-GP

3KR2J-2-GP

R1103

R1103
3KR2F-GP

3KR2F-GP

R1104

R1104
3KR2F-GP

3KR2F-GP

PCI-Expres s Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

CFG4 - Display Port P resence

1:Disabled; No Phys ical Display Port

CFG4

attached to Embedded Display Port
0:Enabled; An external Di splay Port
device is connected to t he E mbedded
Display Port

CFG7(Reserved) - Temporarily used for early
Clarksfield samples.

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample

(rPGA/BGA) [For detai ls please refer to t he
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.

TP1116TP1116
TP1117TP1117

1
1

SA_DIMM_VREF#
SB_DIMM_VREF#

CFG0

CFG3
CFG4

CFG7

AP25
AL25
AL24
AL22
AJ33

AM30
AM28

AP31
AL32
AL30

AM31

AN29

AM32

AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30

AG9
M27

L28

J17
H17
G25
G17
E31
E30

H16

B19
A19

A20
B20

U9
T9

AC9
AB9

J29

J28

RSVD#AP25
RSVD#AL25
RSVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF#
SB_DIMM_VREF#
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP#H16

RSVD#B19
RSVD#A19

RSVD#A20
RSVD#B20

RSVD#U9
RSVD#T9

RSVD#AC9
RSVD#AB9

RSVD#J29
RSVD#J28

AUBURNDALE

AUBURNDALE

5 OF 9

RSVD#AJ13
RSVD#AJ12

RSVD#AH25
RSVD#AK26

RSVD#AL26

RSVD_NCTF#AR2

RSVD#AJ26
RSVD#AJ27

RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33

RSVD#AR32

RSVD_TP#E15
RSVD_TP#F15

RESERVED

RESERVED

RSVD#D15

RSVD#C15
RSVD#AJ15
RSVD#AH15

RSVD_TP#AA5
RSVD_TP#AA4

RSVD_TP#R8
RSVD_TP#AD3
RSVD_TP#AD2
RSVD_TP#AA2
RSVD_TP#AA1

RSVD_TP#R9
RSVD_TP#AG7
RSVD_TP#AE3

RSVD_TP#V4

RSVD_TP#V5

RSVD_TP#N2
RSVD_TP#AD5
RSVD_TP#AD7

RSVD_TP#W3
RSVD_TP#W2

RSVD_TP#N3
RSVD_TP#AE5
RSVD_TP#AD9

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33

AR32

E15
F15
A2

KEY

D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

VSS (AP34) can be left NC is
CRB implementation; EDS/DG
recommendation to GND.

A A

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

CPU (RESERVED)

CPU (RESERVED)

11 90Friday, April 16, 2010

11 90Friday, April 16, 2010

11 90Friday, April 16, 2010

1

of

of

of

X01

X01

X01

SSID = CPU

5

4

CPU1F

CPU1F

3

6 OF 9

6 OF 9

2

1

+VCC_CORE

PROCESSOR CORE POWER

+VCC_CORE

D D

C C

B B

C1206

C1206

C1207

C1207

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

DY

DY

C1212

C1212

C1213

C1213

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1226

C1226

C1225

C1225

12

12

12

C1243

C1243

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1235

C1235

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1236

C1236

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1209

C1209

C1208

C1208

12

12

12

12

12

C1214

C1214

C1227

C1227

C1237

C1237

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1215

C1215

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1229

C1229

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1238

C1238

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1220

C1220

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1223

C1223

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1230

C1230

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1240

C1240

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

2010/04/19
X01

C1210

C1210

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1224

C1224

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1231

C1231

C1232

C1232

12

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1241

C1241

C1242

C1242

12

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

48A

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

AUBURNDALE

AUBURNDALE

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

POWER

POWER

VTT_SELECT

VCC_SENSE

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

PSI#

VID0
VID1
VID2
VID3
VID4
VID5
VID6

ISENSE

VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

H_VID0

AK35

H_VID1

AK33

H_VID2

AK34

H_VID3

AL35

H_VID4

AL33

H_VID5

AM33

H_VID6

AM35
AM34

G15

AN35

AJ34
AJ35

B15

TP_VSS_SENSE_VTT

A15

12

C1201

C1201

C1216

C1216

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1233

C1233

H_VTTVID1

1

H_VTTVID1 = Low, 1.1V
H_VTTVID1 = High, 1.05V

1

12

C1202

C1202

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

PSI# 47
H_VID[6..0] 47

PM_DPRSLPVR 47

TP1201TPAD14-GPTP1201TPAD14-GP

IMVP_IMON 47

VTT_SENSE 49

TP1202TPAD14-GPTP1202TPAD14-GP

12

C1211

C1211

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1234

C1234

C1217

C1217

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

C1218

C1218

12

C1221

C1221

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

+VCC_CORE

12

12

12

C1203

C1203

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

DY

DY

+1.05V_VTT

R1201

R1201
100R2F-L1-GP-U

100R2F-L1-GP-U

R1204

R1204
100R2F-L1-GP-U

100R2F-L1-GP-U

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

DY

DY

C1222

C1222

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1219

C1219

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

+1.05V_VTT

12

+1.05V_VTT

12

12

C1205

C1205

C1204

C1204

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to t he CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.

Please note that the VT T Rail
Values are Auburndale
VTT=1.05V; Clarksfield
VTT=1.1V

VCC_SENSE 47
VSS_SENSE 47

A A

<Core Design>

<Core Design>

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

<Core Design>

Wistron Corporati on

Wistron Corporati on

Wistron Corporati on

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

CPU (VCC_CORE)

CPU (VCC_CORE)

CPU (VCC_CORE)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221, Taiwan, R.O.C.

of

12 90Thursday, April 22, 2010

of

12 90Thursday, April 22, 2010

of

12 90Thursday, April 22, 2010

1

X01

X01

X01

5

SSID = CPU

+CPU_GFX_CORE

22A

D D

2010/04/19
X01

C C

B B

C1325

C1325

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VTT

+1.05V_VTT

C1323

C1323

C1326

C1328

C1328

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1326

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Please note that the VTT Rail
Values are: Auburndale VTT=1.05V

Clarksfield VTT=1.1V

18A

4

CPU1G

CPU1G

AT21

VAXG1

AT19

C1309

C1309

C1312

12

DY

DY

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1308

C1308

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1314

C1314

C1312

12

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1315

C1315

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

C1324

C1324

12

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1313

C1313

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

AT18

AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16

AL21

AL19

AL18

AL16
AK21
AK19
AK18
AK16

AJ21

AJ19

AJ18

AJ16
AH21
AH19
AH18
AH16

H25

K26

H27
G28
G27
G26

F26

E26

E25

VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

J24

VTT1

J23

VTT1
VTT1

VTT1

J27

VTT1

J26

VTT1

J25

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

3

AUBURNDALE

AUBURNDALE

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

7 OF 9

7 OF 9

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6

GFX_IMON

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VTT1
VTT1
VTT1
VTT1

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

VTT1
VTT1
VTT1

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

+1.5V_RUN

12

DY

DY

+1.5V_SUS

VCC_AXG_SENSE 53
VSS_AXG_SENSE 53

R1305 4K7R2J-2-GPR1305 4K7R2J-2-GP

GFX_IMON_C

12

1 2

DY

DY

R1304 0R2J-2-GP

R1304 0R2J-2-GP

12

12

C1301

C1301

C1302

C1302

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C1310

C1310

12

C1316

C1316

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

C1318

C1318

C1319

C1319

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2

C1376

C1376
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C1304

C1304

C1303

C1303

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C1311

C1311

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

C1317

C1317

DY

DY

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.5V_RUN

12

DY

DY

+1.5V_SUS

C1377

C1377
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_RUN

12

DY

DY

+1.5V_SUS

C1378

C1378
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

425302_425302_Calpella_S3PowerReduction_WhitePape

GFX_VID0 53
GFX_VID1 53
GFX_VID2 53
GFX_VID3 53
GFX_VID4 53
GFX_VID5 53
GFX_VID6 53

GFX_VR_EN 53
GFX_DPRSLPVR 53
GFX_IMON 53

12

TC1301

TC1301
SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

+1.8V_RUN

+1.5V_RUN

C1320

C1320

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

12

C1305

C1305

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C1321

C1321

12

C1306

C1306

+1.05V_VTT

+1.05V_VTT

1.35A

12

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

3A

12

C1307

C1307

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

C1322

C1322
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1

+1.5V_RUN

12

DY

DY

C1379

C1379
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_SUS

Revision 0.7

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

CPU (VCC_GFXCORE)

CPU (VCC_GFXCORE)

CPU (VCC_GFXCORE)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

13 90Thursday, April 22, 2010

13 90Thursday, April 22, 2010

13 90Thursday, April 22, 2010

1

X01

X01

X01

5

4

3

2

1

SSID = CPU

8 OF 9

CPU1H

CPU1H

AT20

VSS

AT17

VSS

AR31

VSS

AR28

VSS

AR26

VSS

AR24

VSS

D D

C C

B B

AR23
AR20
AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2

AL34
AL31
AL23
AL20
AL17
AL12

AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9

AH6

AH3
AG10

AF8

AF4

AF2
AE35

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL9

VSS

AL6

VSS

AL3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ8

VSS

AJ5

VSS

AJ2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AUBURNDALE

AUBURNDALE

VSS

VSS

8 OF 9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27

H35
H32
H28
H26
H24
H22
H18
H15
H13
H11

G34
G31
G20

F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11

D33
D30
D26

C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11

A29
A27
A23

CPU1I

CPU1I

VSS

K9

VSS

K6

VSS

K3

VSS

J32

VSS

J30

VSS

J21

VSS

J19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H8

VSS

H5

VSS

H2

VSS
VSS
VSS
VSS

G9

VSS

G6

VSS

G3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E8

VSS

E5

VSS

E2

VSS
VSS
VSS
VSS

D9

VSS

D6

VSS

D3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B8

VSS

B6

VSS

B4

VSS
VSS
VSS
VSS

A9

VSS

AUBURNDALE

AUBURNDALE

VSS

VSS

NCTF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,

AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35

NCTF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,

AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35

9 OF 9

9 OF 9

VSS_NCTF#AR34

VSS_NCTF#B34

VSS_NCTF#B2

VSS_NCTF#B1
VSS_NCTF#A35
VSS_NCTF#AT1

VSS_NCTF#AT35
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#AP35

RSVD_NCTF#AR35

RSVD_NCTF#AT3
RSVD_NCTF#AR1
RSVD_NCTF#AP1
RSVD_NCTF#AT2

RSVD_NCTF#C1

RSVD_NCTF#A3
RSVD_NCTF#C35
RSVD_NCTF#B35

RSVD_NCTF#A34
RSVD_NCTF#A33

AR34
B34
B2

B1
A35
AT1
AT35
AT33
AT34
AP35
AR35
AT3
AR1
AP1
AT2
C1
A3
C35
B35
A34
A33

TP_MCP_VSS_NCTF1
TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF3
TP_MCP_VSS_NCTF4

TP1403TP1403

1

TP1404TP1404

1

TP1406TP1406

1

TP1405TP1405

1

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

CPU (VSS)

CPU (VSS)

CPU (VSS)

1

of

14 90Friday, Ap ril 16, 2010

14 90Friday, Ap ril 16, 2010

14 90Friday, Ap ril 16, 2010

X01

X01

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

15 90Friday, Ap ril 16, 2010

15 90Friday, Ap ril 16, 2010

15 90Friday, Ap ril 16, 2010

of

of

of

X01

X01

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

16 90Friday, Ap ril 16, 2010

16 90Friday, Ap ril 16, 2010

16 90Friday, Ap ril 16, 2010

of

of

of

X01

X01

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

17 90Friday, Ap ril 16, 2010

17 90Friday, Ap ril 16, 2010

17 90Friday, Ap ril 16, 2010

of

of

of

X01

X01

X01

5

SSID = MEMORY

D D

M_A_BS210
M_A_BS010

M_A_BS110

M_A_DQ[63..0]10

C C

+V_DDR_REF

12

12

C1818

C1817

C1817

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

B B

12

C1820

C1820

Place these caps
close to VTT1 and
VTT2.

12

C1821

C1821

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+0.75V_DDR_VTT

C1818
SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

DY

DY

12

12

C1823

C1823

C1822

C1822

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C1826

C1826
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DDR3_DRAMRST#9,19

M_ODT010
M_ODT110

+0.75V_DDR_VTT

+V_DDR_REF

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

H =5.2mm

4

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78
79

109
108

5

7
15
17

4

6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70

129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

10
27
45
62

135
152
169
186

12
29
47
64

137
154
171
188

116
120

126

1
30

203
204

DM1

DM1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

ODT0
ODT1

VREF_CA
VREF_DQ

RESET#

VTT1
VTT2

DDR3-204P-46-GP

DDR3-204P-46-GP

RAS#
CAS#
CS0#

CS1#
CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1
NC#2

NC#/TEST

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

NP1
NP2

WE#

CK0

CK1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA
SCL

SA0
SA1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NP1
NP2

110
113
115

114
121

73
74

101
103

102
104

11
28
46
63
136
153
170
187

200
202

198
199
197

201
77

122
125

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SODIMM0_1_SMB_DATA_R
SODIMM0_1_SMB_CLK_R

SA0_DIM0
SA1_DIM0

+1.5V_SUS

M_A_DM[7..0] 10
M_A_DQS#[7..0] 10

M_A_DQS[7..0] 10
M_A_A[15..0] 10

M_A_RAS# 10
M_A_WE# 10
M_A_CAS# 10

M_CS#0 10
M_CS#1 10

M_CKE0 10
M_CKE1 10

M_CLK_DDR0 10
M_CLK_DDR#0 10

M_CLK_DDR1 10
M_CLK_DDR#1 10

R1804 0R0402-PADR1804 0R0402-PAD

1 2

R1805 0R0402-PADR1805 0R0402-PAD

1 2

PM_EXTTS#0 9

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1801

C1801

3

Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

4

If SA0 DIM0 = 1, SA1_DIM0 = 0

RN1801

RN1801

SO-DIMMA SPD Address is 0xA2

SRN10KJ-5-GP

SRN10KJ-5-GP

SO-DIMMA TS Address is 0x32

1

SODIMM A DECOUPLING

C1804

C1804

TC1801

TC1801

C1803

C1803

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

12

DY

DY

DY

DY

12

12

C1813

C1813

C1814

C1814

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1805

C1805

12

DY

DY

12

C1815

C1815

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

12

C1802

C1802

DY

DY

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

+1.5V_SUS

SA0_DIM0
SA1_DIM0

PCH_SMBDATA 7,19,23,76
PCH_SMBCLK 7,19,23,76

+3.3V_RUN

Layout Note:
Place these Caps near
SO-DIMMA.

2 3

2

C1810

C1810

C1808

C1808

C1807

C1807

C1806

C1806

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

12

DY

DY

12

C1816

C1816

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1809

C1809

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

12

DY

DY

DY

DY

1

62.10017.P11

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM1

DDR3-SODIMM1

DDR3-SODIMM1

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

1

X01

X01

18 90Thursday, April 22, 2010

18 90Thursday, April 22, 2010

18 90Thursday, April 22, 2010

X01

5

SSID = MEMORY

D D

+V_DDR_REF

12

12

C1924

C1923

C1923

SCD1U10V2KX-5GP

C C

B B

SCD1U10V2KX-5GP

Place these caps
close to VTT1 and
VTT2.

C1924
SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

DY

DY

+0.75V_DDR_VTT

12

12

DY

DY

12

C1920

C1920

C1919

C1919

C1921

C1921

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

12

C1925

C1925
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1922

C1922

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_B_BS210
M_B_BS010

M_B_BS110

M_B_DQ[63..0]10

M_ODT210
M_ODT310

+V_DDR_REF

DDR3_DRAMRST#9,18

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

4

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

H = 9.2mm

62.10017.N71

DM2

DM2

DDR3-204P-43-GP

DDR3-204P-43-GP

RAS#
CAS#

CKE0
CKE1

EVENT#

VDDSPD

NC#/TEST

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

NP1
NP2

WE#

CS0#
CS1#

CK0

CK0#

CK1

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA
SCL

SA0
SA1

NC#1
NC#2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NP1
NP2

110
113
115

114
121

73
74

101
103

102
104

M_B_DM0

11

M_B_DM1

28

M_B_DM2

46

M_B_DM3

63

M_B_DM4

136

M_B_DM5

153

M_B_DM6

170

M_B_DM7

187

SODIMM1_1_SMB_DATA_R

200

SODIMM1_1_SMB_CLK_R

202
198
199

SA0_DIM1

197

SA1_DIM1

201
77

122
125

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

+1.5V_SUS

3

M_B_RAS# 10
M_B_WE# 10
M_B_CAS# 10

M_CS#2 10
M_CS#3 10

M_CKE2 10
M_CKE3 10

M_CLK_DDR2 10
M_CLK_DDR#2 10

M_CLK_DDR3 10
M_CLK_DDR#3 10

R1904 0R0402-PADR1904 0R0402-PAD

1 2

R1905 0R0402-PADR1905 0R0402-PAD

1 2

PM_EXTTS#1 9

C1901

C1901

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

12

C1902

C1902

DY

DY

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

+1.5V_SUS

Layout Note:
Place these Caps near
SO-DIMMB.

M_B_DM[7..0] 10
M_B_DQS#[7..0] 10

M_B_DQS[7..0] 10
M_B_A[15..0] 10

PCH_SMBDATA 7,18,23,76
PCH_SMBCLK 7,18,23,76

+3.3V_RUN

SODIMM B DECOUPLING

2

+3.3V_RUN

SA0_DIM1

4

RN1901

RN1901
SRN10KJ-5-GP

SRN10KJ-5-GP

1

C1909

C1909

2 3

C1912

C1912

C1910

C1910

C1911

C1911

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

DY

DY

DY

DY

SA1_DIM1

C1906

C1906

C1907

C1907

C1905

C1905

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

DY

DY

12

12

C1915

C1915

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1908

C1908

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

12

12

C1916

C1916

C1917

C1917

C1918

C1918

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34

A A

http://laptop-motherboard-schematic.blogspot.com/

5

4

SO-DIMMB is placed farther from
the Processor than SO-DIMMA

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM2

DDR3-SODIMM2

DDR3-SODIMM2

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

1

X01

X01

19 90Thursday, April 22, 2010

19 90Thursday, April 22, 2010

19 90Thursday, April 22, 2010

X01

5

4

3

2

1

SSID = PCH

D D

4 OF 10

U2001D

U2001D

LIBG

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

LVDS

LVDS

Digital Display Interface

Digital Display Interface

CRT

CRT

PCH_VGA_BLEN37

PCH_LCDVDD_EN54

12

R2002

R2002
2K37R2F-GP

2K37R2F-GP

PCH_LBKLT_CTL54

LDDC_CLK_PCH54
LDDC_DATA_PCH54

R2003

R2003

PCH_LCDVDD_EN

12

DY

DY

100KR2J-1-GP

100KR2J-1-GP

C C

+3.3V_RUN

45

678

123

RN2002

RN2002
SRN2K2J-4-GP

SRN2K2J-4-GP

LCTRL_DATA

LDDC_CLK_PCH

LCTRL_CLK

LDDC_DATA_PCH

Place near PCH

Impedance:85 ohm

LDDC_CLK_PCH
LDDC_DATA_PCH

LCTRL_CLK
LCTRL_DATA

LVDS_VBG

TP2001TPAD14-GP TP2001TPAD14-GP

1

PCH_LVDSA_TXC#54
PCH_LVDSA_TXC54

PCH_LVDSA_TX0#54
PCH_LVDSA_TX1#54
PCH_LVDSA_TX2#54

PCH_LVDSA_TX054
PCH_LVDSA_TX154
PCH_LVDSA_TX254

Close to ball <600mil

PCH_CRT_BLUE55
PCH_CRT_GREEN55
PCH_CRT_RED55

B B

SRN150F-1-GP

SRN150F-1-GP

CRT SMBUS
Close PCH

+3.3V_RUN

1

23

RN2003

RN2003

SRN2K2J-1-GP

SRN2K2J-1-GP

4

PCH_CRT_DDCCLK

PCH_CRT_DDCDATA

RN2005

RN2005

678

123

4 5

Need Level Shift

PCH_CRT_DDCCLK55
PCH_CRT_DDCDATA55

PCH_CRT_HSYNC55
PCH_CRT_VSYNC55

2.5V Tolerance

1 2

R2001 1KR2J-1-GPR2001 1KR2J-1-GP

CRT_IREF

4 OF 10

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

PCH (LVDS/CRT/DDI)

PCH (LVDS/CRT/DDI)

PCH (LVDS/CRT/DDI)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

20 90Thursday, April 22, 2010

20 90Thursday, April 22, 2010

20 90Thursday, April 22, 2010

1

X01

X01

X01

5

RN2101

PCI_DEVSEL#
PCI_IRDY#
PCI_SERR#

+3.3V_RUN

PCI_PERR#

D D

+3.3V_RUN

C C

PCI_REQ0#
PCI_REQ3#
PCI_FRAME#

+3.3V_RUN

RN2101

1
2
3
4
5 6

SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

RN2102

RN2102

1
2
3
4
5 6

SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

RN2103

RN2103

1
2
3
4 5

SRN10KJ-7GP

SRN10KJ-7GP

INT_PIRQF#

8

INT_PIRQH#

7

INT_PIRQG#

6

INT_PIRQE#

10
9
8
7

10
9
8
7

PCI_REQ2#
INT_PIRQD#
PCI_STOP#INT_PIRQC#
INT_PIRQA#

INT_PIRQB#
PCI_PLOCK#
PCI_REQ1#
PCI_TRDY#

+3.3V_RUN

+3.3V_RUN

PLT_RST#9,37,70,76

BOOT BIOS Strap

PCI_GNT#1 BOOT BIOS LocationPCI_GNT#0

0 0 LPC

0 1 Reserved

PCI

01

SPI(Default)

11

B B

PCLK_FWH70
CLK_PCI_FB23
PCLK_KBC37

A16 swap override Strap/Top-Block
Swap Override jumper

PCI_GNT#3 Low = A16 swap

A A

PCI_GNT3#

override/Top-Block
Swap Override enabled
High = Default

R2109

R2109

1 2

DY

DY

4K7R2J-2-GP

4K7R2J-2-GP

5

http://laptop-motherboard-schematic.blogspot.com/

4

SSID = PCH

+3.3V_RUN

U2101

U2101

5
4

74LVC1G08GW-1-GP

74LVC1G08GW-1-GP

R2104 0R0402-PADR2104 0R0402-PAD

12

C2101

C2101

DY

DY

SC220P50V2KX-3GP

SC220P50V2KX-3GP

R2110 22R2J-2-GP

R2110 22R2J-2-GP

12

DY

DY

R2108 22R2J-2-GPR2108 22R2J-2-GP

4

VCC

DY

DY

Y

GND

1 2

1

B

PCI_PLTRST#

2

A

3

12

R2111 22R2J-2-GPR2111 22R2J-2-GP

3

5 OF 10

U2001E

U2001E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

TP2116TPAD14-GPTP2116TPAD14-GP
TP2117TPAD14-GPTP2117TPAD14-GP
TP2103TPAD14-GPTP2103TPAD14-GP

TP2108TPAD14-GPTP2108TPAD14-GP

TP2115TPAD14-GPTP2115TPAD14-GP

PCI_GNT0#

1

PCI_GNT1#

1

PCI_GNT2#

1

PCI_GNT3#
INT_PIRQE#

INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

PCIRST#

1

PCI_SERR#
PCI_PERR#

PCI_IRDY#
PCI_DEVSEL#

PCI_FRAME#
PCI_PLOCK#
PCI_STOP#

PCI_TRDY#
PCH_PME#

1

PCI_PLTRST#

PCLK_FWH_R
CLK_PCI_FB_R
PCLK_KBC_R

12

+3.3V_ALW

3

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

USB_OC#10_11
USB_OC#12_13 USB_OC#4_5

USB_OC#0_1

PCI

PCI

RN2104

RN2104

1
2
3
4
5 6

SRN10KJ-L3-GP

SRN10KJ-L3-GP

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8

NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11

NVRAM

NVRAM

NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USB

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

10
9

USB_OC#6_7USB_OC#8_9

8

USB_OC#2_3

7

SMC_WAKE_SCI#_R

5 OF 10

NV_ALE
NV_CLE

NV_RB#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

2

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

+3.3V_ALW

2

NV_ALE
NV_CLE

NV_RCOMP

USB_RBIAS_PN

USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
SMC_WAKE_SCI#_R

1

Danbury Technology:
Disabled when Low.
Enable when High.

TP2100TP2100
TP2101TP2101

1
1

TP2102TP2102

1

USB

Pair

USB_PN0 76
USB_PP0 76

USB_PN2 63
USB_PP2 63
USB_PN3 63
USB_PP3 63

USB_PN5 76
USB_PP5 76

0

1

2

3

4

5

6

7

8

USB_PN9 73
USB_PP9 73
USB_PN10 32
USB_PP10 32
USB_PN11 54
USB_PP11 54

9

10

11

12

13

1 2

R2106

R2106
22D6R2F-L1-GP

22D6R2F-L1-GP

USB_OC#0_1 63
USB_OC#2_3 63

<Core Des ign>

<Core Des ign>

<Core Des ign>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

PCH (PCI/USB/NVRAM)

PCH (PCI/USB/NVRAM)

PCH (PCI/USB/NVRAM)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Device

USB0 (I/O Board)

X

USB2

USB3

X

WLAN (I/O Board)

X

X

X

BLUETOOTH

CARD READER

CAMERA

X

X

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

of

21 90Thursday, April 22, 2010

21 90Thursday, April 22, 2010

21 90Thursday, April 22, 2010

1

X01

X01

X01

5

4

3

2

1

SSID = PCH

3 OF 10

U2001C

U2001C

DMI_CTX_PRXN08
DMI_CTX_PRXN18
DMI_CTX_PRXN28
DMI_CTX_PRXN38

DMI_CTX_PRXP08

D D

+1.05V_VTT

C C

B B

XDP_DBRESET#9

PM_PWROK37

PM_DRAM_PWRGD9

PCH_RSMRST#37 PM_SLP_S4# 37,50

SUS_PWR_DN_ACK37

PM_PWRBTN#_R9

PM_PWRBTN#37

AC_PRESENT_EC37

R2207 0R0402-PADR2207 0R0402-PAD

R2208

R2208

R2209 10KR2J-3-GPR2209 10KR2J-3-GP

PM_DRAM_PWRGD

R2213 0R0402-PADR2213 0R0402-PAD

PM_BATLOW#_R

PM_RI#

DMI_CTX_PRXP18
DMI_CTX_PRXP28
DMI_CTX_PRXP38

DMI_PTX_CRXN08
DMI_PTX_CRXN18
DMI_PTX_CRXN28
DMI_PTX_CRXN38

DMI_PTX_CRXP08
DMI_PTX_CRXP18
DMI_PTX_CRXP28
DMI_PTX_CRXP38

R2204

R2204

1 2

49D9R2F-GP

49D9R2F-GP

1 2
1 2

1 2

R2210 0R0402-PADR2210 0R0402-PAD

R2218 0R0402-PADR2218 0R0402-PAD

1 2

R2216 0R0402-PADR2216 0R0402-PAD

DMI_IRCOMP_R

10KR2J-3-GP

10KR2J-3-GP

1 2

1 2

1 2

+3.3V_RUN

12

R2205

R2205
10KR2J-3-GP

10KR2J-3-GP

PM_PWRGD

LAN_RST#1

PM_RSMRST#_R

SUS_PWR_ACK

PM_PWRBTN#_R

AC_PRESENT

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

DMI

DMI

System Power Management

System Power Management

3 OF 10

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI

FDI

FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

SLP_LAN#/GPIO29

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PM_CLKRUN#

PM_SUS_STAT#

PCH_SUSCLK

PCH_SLP_S5#

PM_SLP_S4#_R

PM_SLP_S3#_R

SIO_SLP_M#_R

PM_SLP_DSW#

H_PM_SYNC

PM_SLP_LAN#

FDI_TXN0 8
FDI_TXN1 8
FDI_TXN2 8
FDI_TXN3 8
FDI_TXN4 8
FDI_TXN5 8
FDI_TXN6 8
FDI_TXN7 8

FDI_TXP0 8
FDI_TXP1 8
FDI_TXP2 8
FDI_TXP3 8
FDI_TXP4 8
FDI_TXP5 8
FDI_TXP6 8
FDI_TXP7 8

FDI_INT 8
FDI_FSYNC0 8
FDI_FSYNC1 8
FDI_LSYNC0 8
FDI_LSYNC1 8

PCIE_WAKE# 76

PM_CLKRUN# 37

1

TP2201TPAD14-GPTP2201TPAD14-GP

1

TP2202

TP2202
TPAD14-GP

TPAD14-GP

R2211 0R0402-PADR2211 0R0402-PAD

1 2

R2212 0R0402-PADR2212 0R0402-PAD

1 2

1

TP2203TPAD14-GPTP2203TPAD14-GP

1

TP2204TPAD14-GPTP2204TPAD14-GP

1

TP2205TPAD14-GPTP2205TPAD14-GP

R2219 0R2J-2-GPR2219 0R2J-2-GP

1 2

R2220 10R2J-2-GPR2220 10R2J-2-GP

1 2

PM_SLP_S3# 37,42,50,51

H_PM_SYNC 9

PM_RI#
SUS_PWR_ACK
PM_BATLOW#_R
AC_PRESENT_EC

PCIE_WAKE#

PCH_RSMRST#

PCH_SUSCLK_2102 39
PCH_SUSCLK_KBC 37

R2202 1KR2J-1-GPR2202 1KR2J-1-GP

RN2201

RN2201

1
2
3
4 5

SRN10KJ-6-GP

SRN10KJ-6-GP

1 2

R2203

R2203

1 2

10KR2J-3-GP

10KR2J-3-GP

+3.3V_ALW

8
7
6

+3.3V_RUN

PM_CLKRUN#

12

R2215

A A

Option to " Disable " clkrun.
Pulling it down will keep the clks running.

5

http://laptop-motherboard-schematic.blogspot.com/

R2215

10KR2J-3-GP

10KR2J-3-GP

DY

DY

4

1 2

R2214

R2214
10KR2J-3-GP

10KR2J-3-GP

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

PCH (DM I/FDI/PM)

PCH (DM I/FDI/PM)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

22 90Thursday, April 22, 2010

22 90Thursday, April 22, 2010

22 90Thursday, April 22, 2010

1

X01

X01

X01

5

SSID = PCH

D D

C C

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

B B

PCIE_RXN276

PCIE_RXP276
PCIE_TXN276
PCIE_TXP276

PCIE_RXN376

PCIE_RXP376
PCIE_TXN376
PCIE_TXP376

CLK_PCIE_MINI1#76
CLK_PCIE_MINI176

MINI1_CLK_REQ#76

CLK_PCIE_LAN#76
CLK_PCIE_LAN76

C2305 SCD1U10V2KX-5GPC2305 SCD1U10V2KX-5GP
C2306 SCD1U10V2KX-5GPC2306 SCD1U10V2KX-5GP

C2303 SCD1U10V2KX-5GPC2303 SCD1U10V2KX-5GP
C2304 SCD1U10V2KX-5GPC2304 SCD1U10V2KX-5GP

RN2309

RN2309

0R4P2R-PAD

0R4P2R-PAD

0R4P2R-PAD

0R4P2R-PAD

1
2 3

RN2304

RN2304

1
2 3

R2305 10KR2J-3-GPR2305 10KR2J-3-GP

1 2
1 2

1 2
1 2

RN

RN

RN

RN

4

4

12

PCIE_C_TXN2
PCIE_C_TXP2

PCIE_C_TXN3
PCIE_C_TXP3

PCIE_CLK_RQ1#

CLK_PCIE_MINI1R#
CLK_PCIE_MINI1R

MINI1_CLK_REQ#

CLK_PCIE_LAN1#
CLK_PCIE_LAN1

PCIE_CLK_RQ3#

PCIE_CLKRQ4#

PCIE_CLK_RQ5#

PEG_B_CLKRQ#

4

U2001B

U2001B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

WLAN

LAN

SMBus

SMBus

PCI-E*

PCI-E*

Link

Link

Controller

Controller

PEG_A_CLKRQ#/GPIO47

PEG

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

CLKIN_SATA_N/CKSSCD_N

CLKIN_SATA_P/CKSSCD_P

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

Clock Flex

Clock Flex

CLKOUTFLEX3/GPIO67

2 OF 10

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1
CL_DATA1
CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9
H14
C8

J14
C6
G8

M14
E10
G12

T13
T11
T9

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

AH51
AH53

AF38

T45

P43

T42

N50

3

PCH_GPIO11
PCH_SMB_CLK
PCH_SMB_DATA

TPM_ID1
SML0_CLK
SML0_DATA

LPD_SPI_INTR#
KBC_SCL1
KBC_SDA1

CL_CLK

1

CL_DATA

1

CL_RST#

1

PEG_CLKREQ#

CLK_EXP_N
CLK_EXP_P

CLKIN_DMI#
CLKIN_DMIPCIE_CLK_RQ0#

CLK_CPU_BCLK#
CLK_CPU_BCLK

DREFCLK#
DREFCLK

CLK_PCIE_SATA#
CLK_PCIE_SATA

CLK_PCH_14M

CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

CLK_PCH_GPIO64

CLK48_GPIO

R2301

R2301
10KR2J-3-GP

10KR2J-3-GP

12

+3.3V_ALW

R2302

R2302

12

10KR2J-3-GP

10KR2J-3-GP

R2303

R2303

10KR2J-3-GP

10KR2J-3-GP

TP2301TPAD14-GPTP2301TPAD14-GP
TP2302TPAD14-GPTP2302TPAD14-GP
TP2303TPAD14-GPTP2303TPAD14-GP

R2304

R2304

10KR2J-3-GP

10KR2J-3-GP

1

R2306 90D9R2F-1-GPR2306 90D9R2F-1-GP

1

R2307 33R2J-2-GPR2307 33R2J-2-GP

+3.3V_ALW

12

+3.3V_ALW

12

TP2305TPAD14-GPTP2305TPAD14-GP

1 2

TP2304TPAD14-GPTP2304TPAD14-GP

12

+3.3V_ALW

CLK_EXP_N 9
CLK_EXP_P 9

CLKIN_DMI# 7
CLKIN_DMI 7

CLK_CPU_BCLK# 7
CLK_CPU_BCLK 7

DREFCLK# 7
DREFCLK 7

CLK_PCIE_SATA# 7
CLK_PCIE_SATA 7

CLK_PCH_14M 7

CLK_PCI_FB 21

SML0_CLK 9
SML0_DATA 9

KBC_SCL1 37
KBC_SDA1 37

2

PCH_SMB_DATA

PCH_SMB_CLK

+1.05V_VTT

CLK_48M_CARD 32

123

RN2301

RN2301

SRN2K2J-2-GP

SRN2K2J-2-GP

SML0_CLK
SML0_DATA

+3.3V_RUN

1 2

R2309 0R2J-2-GPR2309 0R2J-2-GP

45

678

KBC_SCL1
KBC_SDA1

RN2303

RN2303

2 3
1

4

SRN2K2J-1-GP

SRN2K2J-1-GP

Q2301

Q2301

1

6

2

5

34

DMN66D0LDW-7-GP

DMN66D0LDW-7-GP

1

+3.3V_ALW+3.3V_ALW

PCH_SMB_CLK
PCH_SMB_DATA

PCH_SMBDATA 7,18,19,76

PCH_SMBCLK 7,18,19,76

1

23

4

RN2302

RN2302
SRN2K2J-1-GP

SRN2K2J-1-GP

+3.3V_ALW

A A

RN2307

RN2307

8
7
6

SRN10KJ-7GP

SRN10KJ-7GP

5

1
2
3
45

PCIE_CLK_RQ0#
PEG_B_CLKRQ#
PCIE_CLKRQ4#
PCIE_CLK_RQ5#

+3.3V_RUN

4

PCIE_CLK_RQ1#
MINI1_CLK_REQ#

3

2

1
2 3

RN2308

RN2308

SRN10KJ-5-GP

SRN10KJ-5-GP

http://laptop-motherboard-schematic.blogspot.com/

4

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

PCH (PCI-E/SMBUS/CLOCK/CL)

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

23 90Thursday, April 22, 2010

23 90Thursday, April 22, 2010

23 90Thursday, April 22, 2010

1

X01

X01

X01

5

4

3

2

1

R2401

R2401

1 2

10MR2J-L-GP

10MR2J-L-GP

X2401

X2401

1

4

D D

C C

B B

12

C2402

C2402

+3.3V_RUN

+3.3V_RUN

2 3

SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

NO REBOOT STRAP

1 2

DY

DY

R2410 1KR2J-1-GP

R2410 1KR2J-1-GP

1 2

R2411 10KR2J-3-GPR2411 10KR2J-3-GP

X-32D768KHZ-40GPU

X-32D768KHZ-40GPU

82.30001.841

PCH_AZ_CODEC_RST#30
PCH_AZ_CODEC_BITCLK30
PCH_AZ_CODEC_SYNC30

PCH_SDOUT_CODEC30

ACZ_SPKR

INT_SERIRQ

PCH_RTCX1
PCH_RTCX2

12

C2403

C2403
SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

No Reboot Strap R23

HDA_SPKR

+RTC_CELL

SRN20KJ-GP-U

SRN20KJ-GP-U

RN2402

RN2402

1
2
3
4 5

SRN33J-7-GP

SRN33J-7-GP

Low = Default
High = No Reboot

RN2401

RN2401

1
2 3

8
7
6

4

C2401

C2401

ME_UNLOCK#37

PCH_SPI_CLK62
PCH_SPI_CS0#62

PCH_SPI_DO62
PCH_SPI_DI62

C2404

C2404

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

ACZ_SPKR30

PCH_SDIN_CODEC30

PCH_SPI_CLK
PCH_SPI_CS0#

PCH_SPI_DO
PCH_SPI_DI

21

ACZ_SDATAOUT_R

INTVRMEN- Integrated SUS

1.1V VRM Enable

G2401

G2401

High - Enable internal VRs

GAP-OPEN

GAP-OPEN

+RTC_CELL

TP2404TPAD14-GP TP2404TPAD14-GP
TP2405TPAD14-GP TP2405TPAD14-GP
TP2406TPAD14-GP TP2406TPAD14-GP
TP2407TPAD14-GP TP2407TPAD14-GP
TP2408TPAD14-GP TP2408TPAD14-GP

SRN15J-2-GP

SRN15J-2-GP

2 3
1

RN2403

RN2403

R2415 15R2J-GPR2415 15R2J-GP

1 2

PCH_RTCX1
PCH_RTCX2

PCH_RTCRST#

SRTCRST#

1 2

R2406 1MR2J-1-GPR2406 1MR2J-1-GP

1 2

R2404 330KR2F-L-GPR2404 330KR2F-L-GP

1
1
1
1
1

4

SM_INTRUDER#
PCH_INTVRMEN

ACZ_BIT_CLK
ACZ_SYNC_R
ACZ_SPKR
ACZ_RST#_R

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

SPI_CLK_R
SPI_CS#0_R

SPI_MOSI_R

SSID = PCH

U2001A

U2001A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

LPC

SATA0RXN

SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN

SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN

SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN

SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA0GP/GPIO21
SATA1GP/GPIO19

1 OF 10

1 OF 10

LDRQ0#

SERIRQ

SATALED#

D33
B33
C32
A32

C34
A34

F34
AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16
AF15

T3

Y9
V1

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

SATA_TXN0_C
SATA_TXP0_C

SATA_TXN1_C
SATA_TXP1_C

SATA_DET#0_R
SATA_DET#1_R

LPC_LAD[0..3]

LPC_LFRAME# 37,70

INT_SERIRQ 37

C2405 SCD01U16V2KX-3GPC2405 SCD01U16V2KX-3GP

1 2

C2406 SCD01U16V2KX-3GPC2406 SCD01U16V2KX-3GP

1 2

C2407 SCD01U16V2KX-3GPC2407 SCD01U16V2KX-3GP

1 2

C2408 SCD01U16V2KX-3GPC2408 SCD01U16V2KX-3GP

1 2

R2412

SATAICOMP

R2412

1 2

37D4R2F-GP

37D4R2F-GP

SATA_LED# 66

LPC_LAD[0..3] 37,70

+1.05V_VTT

10KR2J-3-GP

10KR2J-3-GP

R2416

R2416

SATA_RXN0_C 59
SATA_RXP0_C 59
SATA_TXN0 59
SATA_TXP0 59

SATA_RXN1_C 59
SATA_RXP1_C 59
SATA_TXN1 59
SATA_TXP1 59

+3.3V_RUN

R2417

R2417
10KR2J-3-GP

10KR2J-3-GP

1 2

1 2

HDD

ODD

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

PCH (SPI/RTC/LPC/SATA/IHDA)

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

of

24 90Thursday, April 22, 2010

24 90Thursday, April 22, 2010

24 90Thursday, April 22, 2010

1

X01

X01

X01

+3.3V_RUN

12

R2503

R2503
10KR2J-3-GP

10KR2J-3-GP

S_GPIO

D D

+3.3V_RUN

R2510

R2510

1 2

10KR2J-3-GP

10KR2J-3-GP

RN2506

RN2506

1
2 3

C C

SRN10KJ-5-GP

SRN10KJ-5-GP

+3.3V_ALW

12

PCH_GPIO28

B B

SIO_EXT_WAKE#
PCH_GPIO6

DGPU_HOLD_RST#
PCH_TEMP_ALERT#_C

A A

PCH_GPIO37
PCH_GPIO48

PCH_GPIO38
PCH_GPIO36

5

SIO_EXT_WAKE#37

SC47P50V2JN-3GP

SC47P50V2JN-3GP

PCH_GPIO22

SIO_EXT_SCI#

4

PCH_GPIO17

R2525

R2525
10KR2J-3-GP

10KR2J-3-GP

PCH_GPIO57

HOST_ALTERT#1

PCH_GPIO45
DDR_RST_GATE

PCH_GPIO24

PCH_GPIO12
SIO_EXT_SMI#

SRN10KJ-5-GP

SRN10KJ-5-GP

SRN10KJ-5-GP

SRN10KJ-5-GP

R2519 10KR2J-3-GPR2519 10KR2J-3-GP
R2515 10KR2J-3-GPR2515 10KR2J-3-GP

SRN10KJ-5-GP

SRN10KJ-5-GP

5

C2501

C2501

DY

DY

R2524 10KR2J-3-GPR2524 10KR2J-3-GP

R2513 1KR2J-1-GPR2513 1KR2J-1-GP

1
2 3

RN2509

RN2509

SRN10KJ-5-GP

SRN10KJ-5-GP

R2514 100KR2J-1-GP

R2514 100KR2J-1-GP

1
2 3

RN2501

RN2501

SRN10KJ-5-GP

SRN10KJ-5-GP

RN2503

RN2503

4

RN2507

RN2507

4

1 2
1 2

RN2502

RN2502

4

12

C2502

C2502

SC47P50V2JN-3GP

SC47P50V2JN-3GP

PCH_TEMP_ALERT#37

1 2

1 2

DY

DY

+3.3V_RUN

1
23

1
23

1
23

SSID = PCH

SIO_EXT_SCI#37

SIO_EXT_SMI#37

12

DY

DY

R2508

R2508
10KR2J-3-GP

10KR2J-3-GP

1 2

DDR_RST_GATE9

1 2

R2518 0R0402-PADR2518 0R0402-PAD

+3.3V_ALW

4

12

4

STP_PCI#
PCH_GPIO39

http://laptop-motherboard-schematic.blogspot.com/

TP2507TPAD14-GP TP2507TPAD14-GP

TP2510TPAD14-GP TP2510TPAD14-GP

TP2511TPAD14-GP TP2511TPAD14-GP
TP2512TPAD14-GP TP2512TPAD14-GP

TP2509TPAD14-GP TP2509TPAD14-GP

SRN100KJ-6-GP

SRN100KJ-6-GP

4

4

1

PCH_NCTF_1

1

PCH_NCTF_2

1

PCH_NCTF_3

1

PCH_NCTF_4

1

S_GPIO
SIO_EXT_SCI#
PCH_GPIO6
SIO_EXT_WAKE#
SIO_EXT_SMI#
PCH_GPIO12
HOST_ALTERT#1
DGPU_HOLD_RST#
PCH_GPIO17
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
STP_PCI#
CLK_SATA_OE#
PCH_GPIO36
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO45
DDR_RST_GATE
PCH_GPIO48
PCH_TEMP_ALERT#_C
PCH_GPIO57

RN2504

RN2504

1

4

23

U2001F

U2001F

Y3

BMBUSY#/GPIO0

C38

TACH1/GPIO1

D37

TACH2/GPIO6

J32

TACH3/GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL/GPIO12

T7

GPIO15

AA2

SATA4GP/GPIO16

F38

TACH0/GPIO17

Y7

SCLOCK/GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI#/GPIO34

V6

SATACLKREQ#/GPIO35

AB7

SATA2GP/GPIO36

AB13

SATA3GP/GPIO37

V3

SLOAD/GPIO38

P3

SDATAOUT0/GPIO39

H3

PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46

AB6

SDATAOUT1/GPIO48

AA4

SATA5GP/GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

+3.3V_RUN

3

MISC

MISC

CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

3

6 OF 10

6 OF 10

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

TP19
NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

2

AH45
AH46

AF48
AF47

U2

AM3
AM1
BG10
T1
BE10
BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

INIT3_3V#

P6
C10

BCLK_CPU_N 9
BCLK_CPU_P 9

H_PECI 9

SIO_RCIN# 37

H_PWRGD 9,42

PCH_THERMTRIP_R

TP2506TPAD14-GPTP2506TPAD14-GP

1

2

SIO_A20GATE 37

+1.05V_VTT

RN2505

RN2505

23
1

4

SRN56J-4-GP

SRN56J-4-GP

<Core Des ign>

<Core Des ign>

<Core Des ign>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

PCH (GPIO/CPU)

PCH (GPIO/CPU)

PCH (GPIO/CPU)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

1

H_THERMTRIP# 9,37,42

Placed Within 2" from PCH

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

of

25 90Thursday, April 22, 2010

25 90Thursday, April 22, 2010

25 90Thursday, April 22, 2010

1

X01

X01

X01

5

SSID = PCH

4

3

2

1

+1.05V_VTT

1.524A

C2601

C2601

SC10U6D3V5KX-1GP

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

TP2601TPAD14-GPTP2601TPAD14-GP

1

12

C2609

C2609

SC1U10V3KX-3GP

SC1U10V3KX-3GP

DY

DY

+1.05V_VTT

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

D D

C C

B B

+1.05V_VTT

3.208A

C2608

C2608

+1.05V_VTT

C2610

C2610

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

C2614

C2614

TP2602TPAD14-GP TP2602TPAD14-GP

12

C2602

C2602
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

+1.05VS_VCCAPLL_EXP

12

12

C2611

C2611

C2612

C2612

SC1U10V3KX-3GP

SC1U10V3KX-3GP

+3.3V_RUN

12

357mA

VCCAFDI_VRM
VCCAFDIPLL

1

VCCAFDI_VRM

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

U2001G

U2001G

AB24

VCCCORE

AB26

VCCCORE

AB28

VCCCORE

AD26

VCCCORE

AD28

VCCCORE

AF26

VCCCORE

AF28

VCCCORE

AF30

VCCCORE

AF31

VCCCORE

AH26

VCCCORE

AH28

VCCCORE

AH30

VCCCORE

AH31

VCCCORE

AJ30

VCCCORE

AJ31

VCCCORE

AK24

VCCIO

BJ24

VCCAPLLEXP

AN20

VCCIO

AN22

VCCIO

AN23

VCCIO

AN24

VCCIO

AN26

VCCIO

AN28

VCCIO

BJ26

VCCIO

BJ28

VCCIO

AT26

VCCIO

AT28

VCCIO

AU26

VCCIO

AU28

VCCIO

AV26

VCCIO

AV28

VCCIO

AW26

VCCIO

AW28

VCCIO

BA26

VCCIO

BA28

VCCIO

BB26

VCCIO

BB28

VCCIO

BC26

VCCIO

BC28

VCCIO

BD26

VCCIO

BD28

VCCIO

BE26

VCCIO

BE28

VCCIO

BG26

VCCIO

BG28

VCCIO

BH27

VCCIO

AN30

VCCIO

AN31

VCCIO

AN35

VCC3_3

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

1 2

R2606 0R0402-PADR2606 0R0402-PAD

POWER

POWER

VCC CORE

VCC CORE

DMI

DMI

PCI E*

PCI E*

NAND / SPI

NAND / SPI

FDI

FDI

+1.8V_RUN

CRTLVDS

CRTLVDS

HVCMOS

HVCMOS

7 OF 10

7 OF 10

VCCADAC

VCCADAC
VSSA_DAC
VSSA_DAC

VCCALVDS

VSSA_LVDS

VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS

VCC3_3
VCC3_3
VCC3_3

VCCVRM

VCCDMI
VCCDMI

VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND

VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3

+VCCA_DAC_1_2

AE50
AE52
AF53
AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

12

C2603

C2603

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

+3VS_VCCA_LVD +3.3V_RUN

C2616

C2616

1 2

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+1.8VS_VCCTX_LVDS

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

357mA

12

C2607

C2607
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2618

C2618

12

12

C2606

C2606

C2605

C2605

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

+1.8V_RUN

12

C2619

C2619

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

0R0603-PAD-1-GP

0R0603-PAD-1-GP

12

C2617

C2617

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+3.3V_RUN

R2603

R2603

12

R2611

R2611

1 2

0R0805-PAD-2-GP

0R0805-PAD-2-GP

35mA

+1.05VS_VCC_DMI

12

C2613

C2613
SC1U10V3KX-3GP

SC1U10V3KX-3GP

156mA

12

C2615

C2615
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

85mA

PCH_VCCME3_3

12

C2622

C2622
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

R2601 0R0402-PADR2601 0R0402-PAD

+3.3V_RUN

12

R2605

R2605
0R0402-PAD

0R0402-PAD

61mA

+1.05V_VTT

+5V_RUN +3.3V_CRT_LDO

C2621

C2621

SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

L2602 HCB1608KF-181-GPL2602 HCB1608KF-181-GP

1 2

DY

DY

L2603 HCB1608KF-181-GP

L2603 HCB1608KF-181-GP

+1.8V_RUN

2010/04/21
X01

3.3V CRT LDO

2

12

DY

DY

1

Second 74.09091.H3F

+3.3V_RUN

+3.3V_CRT_LDO

+3.3V_RUN

U2601

U2601

VIN3VOUT
GND

DY

DY

EN

NC#5

RT9198-33PBG-GP

RT9198-33PBG-GP

4
5

12

C2620

C2620
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

3

2

<Core Des ign>

<Core Des ign>

<Core Des ign>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

Taipei Hsien 221 , Taiwan, R.O.C.

PCH (POWER1)

PCH (POWER1)

PCH (POWER1)

1

of

26 90Wednesday, April 21, 2010

26 90Wednesday, April 21, 2010

26 90Wednesday, April 21, 2010

X01

X01

X01

5

D D

+1.05V_VTT

1.998A

C2704

C2704

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

+1.05V_VTT

C2734

C2734

C2735

C2735

DY

DY

DY

DY

+1.05VS_VCCA_A_DPL

12

12

C2711

C2711
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05VS_VCCA_B_DPL

12

12

C2714

C2714
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

C C

L2702 0R0805-PADL2702 0R0805-PAD

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1 2

L2703 0R0805-PADL2703 0R0805-PAD

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

C2705

C2705

DY

DY

72mA
73mA

+1.05V_VTT

12

C2718

C2718

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

163mA

12

SCD1U10V2KX-5GP

B B

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3.3V_ALW

C2726

C2726

+1.05V_VTT

1mA

C2728

C2728

SC4D7U10V5KX-4GP

SC4D7U10V5KX-4GP

A A

+RTC_CELL

C2719

C2719

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2723

C2723

12

+3.3V_RUN

12

2mA

5

http://laptop-motherboard-schematic.blogspot.com/

TP2515TPAD14-GP TP2515TPAD14-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2713

C2713

12

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+VCCSST

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+1.05VALW_INT_VCCSUS

C2724

C2724

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2729

C2729

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2732

C2732

4

VCCACLK

1

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2707

C2707

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

+1.8V_RUN

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2727

C2727

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

4

DCPSUSBYP

12

12

C2708

C2708

12

C2710

C2710

+VCCRTCEXT

12

C2720

C2720

12

12

C2730

C2730

12

C2733

C2733

U2001J

U2001J

AP51

VCCACLK

AP53

VCCACLK

AF23

VCCLAN

AF24

VCCLAN

Y20

DCPSUSBYP

AD38

VCCME

AD39

VCCME

AD41

VCCME

AF43

VCCME

AF41

VCCME

AF42

VCCME

V39

VCCME

V41

VCCME

V42

VCCME

Y39

VCCME

Y41

VCCME

Y42

VCCME

V9

DCPRTC

AU24

VCCVRM

BB51

VCCADPLLA

BB53

VCCADPLLA

BD51

VCCADPLLB

BD53

VCCADPLLB

AH23

VCCIO

AJ35

VCCIO

AH35

VCCIO

AF34

VCCIO

AH34

VCCIO

AF32

VCCIO

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

AT18

V_CPU_IO

AU18

V_CPU_IO

A12

VCCRTC

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

3

POWER

POWER

USB

USB

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPC

PCI/GPIO/LPC

SATA

SATA

PCI/GPIO/LPC

PCI/GPIO/LPC

CPU

CPU

RTC

RTC

HDA

HDA

10 OF 10

10 OF 10

VCCIO
VCCIO
VCCIO
VCCIO

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

VCCSUS3_3

VCCIO

V5REF_SUS

V5REF

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCCSATAPLL
VCCSATAPLL

VCCIO

VCCVRM

VCCIO
VCCIO
VCCIO
VCCIO

VCCIO
VCCIO
VCCIO

VCCIO
VCCIO
VCCIO
VCCIO

VCCME
VCCME
VCCME
VCCME

VCCSUSHDA

3

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+3VS_+1.5VS_HDA_IO

12

C2706

C2706
SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

DY

+5VALW_PCH_VCC5REFSUS

+5VS_PCH_VCC5REF

VCCSATAPLL

R2707 0R0402-PADR2707 0R0402-PAD

6mA

12

C2731

C2731
SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2703

C2703
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

12

C2716

C2716
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

+1.8V_RUN

1 2

2

+3.3V_ALW +3.3V_ALW

C2709

C2709
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+1.05V_VTT

+3.3V_RUN

TP2514 TPAD14-GPTP2514 TPAD14-GP

+1.05V_VTT

2

12

C2712

C2712
SC1U10V2KX-1GP

SC1U10V2KX-1GP

C2717

C2717

1 2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3.3V_ALW

1

+1.05V_VTT

+3.3V_ALW

21

D2701

D2701
CH751H-40PT-GP

CH751H-40PT-GP

+5V_ALW

1 2

R2701 100R2F-L1-GP-UR2701 100R2F-L1-GP-U

12

C2715

C2715
SC1U10V2KX-1GP

SC1U10V2KX-1GP

+3.3V_RUN

+1.05V_VTT

12

C2725

C2725
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

<Core Des ign>

<Core Des ign>

<Core Des ign>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

PCH (POWER2)

PCH (POWER2)

PCH (POWER2)

DJ1 Calpella UMA

DJ1 Calpella UMA

DJ1 Calpella UMA

SSID = PCH

+3.3V_RUN

21

D2702

D2702
CH751H-40PT-GP

CH751H-40PT-GP

1 2

R2702 100R2F-L1-GP-UR2702 100R2F-L1-GP-U

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

Taipei Hsien 221 , Taiwan, R.O.C.

1

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27 90Friday, Ap ril 16, 2010

27 90Friday, Ap ril 16, 2010

27 90Friday, Ap ril 16, 2010