Dell Mini 10, Mini 1012 Schematics

A

B

C

D

E

MODEL NAME :
PCB NO :
BOM P/N :

1 1

LA-5732P (DA60000EI00)

43178431L01

NIM10

Compal Confidential

2 2

SAMOS Schematics Document

Intel Pineview-M Processor with TigerPoint

2009-8-21

REV: 0.2

3 3

@ : Nopop Component

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

133Wednesday, September 16, 2009

133Wednesday, September 16, 2009

133Wednesday, September 16, 2009

E

A

A

A

of

of

of

A

B

C

D

E

Compal Confidential

Model Name : NIM10
Project Code:
Project Name : LA-5732P

1 1

LVDS

RGB

Pineview-M

DMI
X2 mode

Processor

22x22mm

page 4,5,6

Memory BUS(DDRII)

1.8V/667MHz

DDRII-DIMM X1

P 07

Daughter board

LS-5731P

USB Port X1

page 21

LCD Conn.

page 09

CRT Conn

page 21

Port 1

Thermal Sensor

W83L771AWG

page 5

Clock Generator
CK505

page 08

SIM card

USB Port X1

2 2

page 21

Card Reader
RTS5159
SD/MMC/MS

page 21

MINI Card

3 3

4 4

WLAN

page 14

USB Port 6

Power ON/OFF

DC IN

BATT CONN/OTP

CHARGER

Port 2

Port 7

MINI Card

WWAN

page 14

PCIE-Port 3

MINI Card

Broadcom MCP

page 14

PCIE-Port 4PCIE-Port 2 PCIE-Port 1

USB Port 4

page 24 page 22

page 24

page 30

page 25

A

DC/DC Interface

3VALW/5VALW

page 26

1.5VS/0.9VS/

0.89VS

page 28

1.8V/VCCP

page 27

CPU CORE

page 29

USB

PCI-Express

10/100 Ethernet

RTL8103EL

page 18

RJ45

page 18

B

Int.KBD

page 19

USB

Tiger Pointer
Chipset

17x17mm

page 10,11,12,13

LPC BUS

ENE KBC
KB926

Touch Pad

page 20

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPI

page 19

SPI ROM

C

SATA

HDA

Audio Codec

ALC272-VB-GR

page 15

Through power buttom cable

page 20

Compal Secret Data

Compal Secret Data

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PWR buttom board

LS-5732P

2.5" HDD

AMP & Speaker

HeadPhone &
MIC Jack

D

page 17

page 16

page 16

Port 4

Port 0

WWAN

page 14

USB Port X1
(R)

page 21

Through BT cable

Port 5

BlueTooth

page 14

Through LVDS cable

Port 3

CMOS CAM

page 09

Through LED cable

LED/B

LS-5733P

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

233Wednesday, September 16, 2009

233Wednesday, September 16, 2009

233Wednesday, September 16, 2009

E

of

of

of

A

A

A

A

ZZZ

ZZZ

PCB

PCB

DA60000EI00

1 1

DA60000EI00

B

C

D

E

Voltage Rails

S5

Power Plane
VIN
B+
+CPU_CORE
+0.9VS
+VCCP
+1.5VS
+1.8V
+0.89VS
+3VALW
+3VS
+5VALW

2 2

+5VS
+VS
+RTCBATT

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

0.9V switched power rail for DDR terminator
VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR
CORE VOLTAGE FOR CPU VGA

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail
VS always on power rail
RTC power

SIGNAL

SLP_S3#

SLP_S4#

SLP_S5#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

S3S1

N/A N/A N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

N/AN/AN/A

OFF

OFF
OFF

OFF
OFFOFF
OFFOFF

ON

OFF
OFF

OFF
ON ON*
OFF

OFF
ON ON*
OFF

OFF
ON ON*
ON

ON

+V +VS Clock

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

External PCI Devices

No PCI Device

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

IDSEL #DEVICE REQ/GNT #

EC SM Bus2 address

Address

1010 000X b

Device

W83L771AWG
EMC1402

PIRQ

Address

1001_100X b0001 011X b
100_1100X b

3 3

4 4

BOARD ID Table(Page 19)

VCC 3.3V +/-5%

*

ID

0
1
2
3
4
5
6
7MP

BRD ID

R01 (SSI)
R02 (ST)
R10 (X build)
Reserved
Reserved
Reserved
Reserved

A

Ra

NC

100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%

Rb Vab (Min)

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

0.168V

0.375V

0.634V

0.958V

1.372V

1.851V

2.433V

0V

Tiger Point SM Bus address

Vab (Type) Vab (Max)

0V

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.300V

B

0.155V

0.362V

0.621V

0.945V

1.359V

1.838V

2.420V

3.300V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

Compal Secret Data

Compal Secret Data

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

C

Compal Secret Data

Address

1101 001Xb

1010 000Xb

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

333Wednesday, September 16, 2009

333Wednesday, September 16, 2009

333Wednesday, September 16, 2009

E

A

A

A

of

of

of

5

PINEVIEW_M

U31A

U31A

DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R

D D

C C

CLK_CPU_EXP#<8>
CLK_CPU_EXP<8>

C906

C906

DMI_RX0<12>

DMI_RX#0<12>

DMI_RX1<12>

DMI_RX#1<12>

C907

C907

C908

C908

C909

C909

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

F3
F2
H4

G3

N7
N6

R10

R9

N10

N9

K2

J1

M4

L3

DMI_RX0_R

DMI_RX#0_R

DMI_RX1_R

DMI_RX#1_R

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

EXP_CLKINN
EXP_CLKINP

EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

DMI

DMI

Close to CPU

B B

Differential Clock Signal Table
Signal Name Description

BCLKP[0]
BCLKN[0]

HPL_CLKINP
HPL_CLKINN

EXP_CLKINP
EXP_CLKINN

REFCLKINP
REFCLKINN

REFSSCLKINP
REFSSCLKINN

A A

Differential Core Clock In

Differential Host Clock In

Differential DMI Clock In

Differential PLL Clock In

Differential Spread Spectrum Clock In

XDP_TDO

XDP_PREQ#

PSOT24C_SOT23-3

PSOT24C_SOT23-3

2

3

@

@

1

XDP_TCK

5

XDP_TRST#

D8

D8

PSOT24C_SOT23-3

PSOT24C_SOT23-3

XDP_TDI
XDP_TMS

@

@

D5

D5

3

1

Direction

2

I

I

I

I

I

3

@

@

D7

D7

PSOT24C_SOT23-3

PSOT24C_SOT23-3

2009-4-27-MODIFY

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

EXP_RCOMPO

EXP_ICOMPI

EXP_RBIAS

1 OF 6

1 OF 6

H_PWRGD<5,12>

CPU_ITP<8>
CPU_ITP#<8>

+VCCP

Type

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

2

1

4

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD
RSVD

SLPIOVR#<12>

PLTRST#<5,12,14,18,19>

4

G2
G1
H3
J2

L10

R1172

R1172

L9

R1171

R1171

49.9_0402_1%

L8
N11

P11

K3
L2
M2
N2

XDP_PREQ#<5>
XDP_PRDY#<5>

XDP_BPM#3<5>
XDP_BPM#2<5>

XDP_BPM#1<5>
XDP_BPM#0<5>

XDP_TDO<5>
XDP_TRST#<5>

49.9_0402_1%
750_0402_1%

750_0402_1%

T1T1
T2T2

R1173 1K_0402_1%R1173 1K_0402_1%

1 2

R1174 1K_0402_1%@R1174 1K_0402_1%@

1 2

CPU_ITP
CPU_ITP#

R1175

R1175

PLTRST#

1 2

XDP_TDI<5>
XDP_TMS<5>

XDP_TCK<5>

XDP Reserve

XDP_PREQ#
XDP_PRDY#

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

T44T44

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

XDP_TDI
XDP_TMS
XDP_TDO
XDP_PREQ#

XDP_TRST#
XDP_TCK

3

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>

3

DDR_A_DQS[0..7]<7>

+VCCP

DDR_A_MA[0..14]<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_A_RAS#<7>

DDR_A_BS0<7>
DDR_A_BS1<7>
DDR_A_BS2<7>

DDR_CS#0<7>
DDR_CS#1<7>

DDR_CKE0<7>
DDR_CKE1<7>

M_ODT0<7>
M_ODT1<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>
M_CLK_DDR1<7>
M_CLK_DDR#1<7>

+1.8V +1.8V

12

R1177

R1177

1K_0402_1%

1K_0402_1%

12

R1180

R1180

1K_0402_1%

1K_0402_1%

Compal Secret Data

Compal Secret Data

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Compal Secret Data

DMI_TX0 <12>
DMI_TX#0 <12>
DMI_TX1 <12>
DMI_TX#1 <12>

JP80

JP80

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

1K_0402_1%

1K_0402_1%

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_87151-24051

ACES_87151-24051

R1182 51_0402_5%~DR1182 51_0402_5%~D

1 2

R1183 51_0402_5%~DR1183 51_0402_5%~D

1 2

R1184 51_0402_5%~DR1184 51_0402_5%~D

1 2

R1185 51_0402_5%~DR1185 51_0402_5%~D

1 2

R1186 51_0402_5%~DR1186 51_0402_5%~D

1 2

R1187 51_0402_5%~DR1187 51_0402_5%~D

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS#0
DDR_CS#1

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

R1179

R1179
R1181

R1181

Deciphered Date

Deciphered Date

Deciphered Date

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_MA14

+1.8V

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

2

R1176

R1176
10K_0402_5%

10K_0402_5%

R1178

R1178
10K_0402_5%

10K_0402_5%

@

@

T6T6
T7T7

2

AH19

AJ18
AK18
AK16

AJ14
AH14
AK14

AJ12
AH13
AK12
AK20
AH12

AJ11

AJ24

AJ10

AK22

AJ22
AK21

AJ20
AH20
AK11

AH22
AK25

AJ21

AJ25
AH10

AH9

AK10

AK24
AH26
AH24
AK27

AG15
AF15
AD13
AC13

AC15
AD15
AF13
AG13

AD17
AC17
AB15
AB17

AB4
AK8

AB11
AB13

AL28
AK28

AJ26
AK29

AJ8

U31B

U31B

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#

DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

RSVD_TP
RSVD_TP

DDR_VREF
DDR_RPD
DDR_RPU

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0
DDR_A_DQ_0

DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1
DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2
DDR_A_DQ_16

DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3
DDR_A_DQ_24

DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4
DDR_A_DQ_32

DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5
DDR_A_DQ_40

DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A

DDR_A

2 OF 6

2 OF 6

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

DDR_A_DM_6
DDR_A_DQ_48

DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7
DDR_A_DQ_56

DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

1

AD3
AD2
AD4

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AB8
AD7
AA9

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AD8
AD10
AE8

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

AK5
AK3
AJ3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AG22
AG21
AD19

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

AE26
AG27
AJ27

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

AE30
AF29
AF30

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

AB27
AA27
AB26

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

433Wednesday, September 16, 2009

433Wednesday, September 16, 2009

433Wednesday, September 16, 2009

A

A

A

of

of

of

5

PINEVIEW_M

U31C

U31C

D12

T18T18
T8T8
T9T9
T10T10
T19T19
T20T20
T11T11

D D

C C

B B

T21T21
T12T12

T22T22
T16T16
T13T13
T23T23
T17T17
T14T14
T15T15
T24T24

R1198

R1198
1K_0402_1%

1K_0402_1%

T25T25

T26T26
T27T27
T28T28
T29T29

T30T30
T31T31
T32T32
T33T33

C10
D10
B11
B10
B12
C11

AA7
AA6

AA21

W21

V21

A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8

L11

R5
R6

T21

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

RSVD

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

VGA

VGA

PM_EXTTS#_1/DPRSLPVR

MISC

MISC

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

REFCLKINP

REFCLKINN
REFSSCLKINP
REFSSCLKINN

PM_EXTTS#_0

PWROK

RSTIN#

HPL_CLKINN
HPL_CLKINP

3 OF 6

3 OF 6

M30
M29

N31
P30
P29
N30

L31
L30

P28
Y30

Y29
AA30
AA31

K29
J30
L5
AA3

W8
W9

PM_EXTTS#1

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

PM_EXTTS#0
H_PWROK
PLTRST#

CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK

Close to Processor

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

+3VS

1

C914

C914

2

H_THERMDA

0.1U_0402_16V4Z~D

A A

C915

C915

1 2

0.1U_0402_16V4Z~D

H_THERMDC

2200P_0402_50V7K

2200P_0402_50V7K

5

CPU THERMAL SENSOR

U33

U33

1

VDD

2

D+

3

D-

4

T_CRIT_A#

W83L771AWG_TSSOP8

W83L771AWG_TSSOP8

Address:1001_100

2009-5-05

ALERT#

SDA

GND

SCL

pin

8
7
6
5

0_0402_5%

0_0402_5%

H_PWROK

PM_EXTTS#0

EC_SMB_CK2
EC_SMB_DA2

10K_0402_5%

10K_0402_5%

4

GMCH_CRT_HSYNC <21>
GMCH_CRT_VSYNC <21>

GMCH_CRT_R <21>
GMCH_CRT_G <21>
GMCH_CRT_B <21>

GMCH_CRT_DATA <21>
GMCH_CRT_CLK <21>

R1189 665_0402_1%R1189 665_0402_1%

CPU_DREFCLK <8>
CPU_DREFCLK# <8>
CPU_SSCDREFCLK <8>
CPU_SSCDREFCLK# <8>

R1252

R1252

PM_EXTTS#0 <7>
PLTRST# <4,12,14,18,19>

CLK_CPU_HPLCLK# <8>
CLK_CPU_HPLCLK <8>

1 2

1 2

+3VS

12

R1195

R1195
10K_0402_5%

10K_0402_5%

EC_SMB_CK2 <19>

4

EC_SMB_DA2 <19>

12

+3VS

R1206

R1206

PM_DPRSLPVR <12>

R1193

@R1193

@

0_0402_5%

0_0402_5%

R1194

R1194

0_0402_5%

0_0402_5%

H_PROCHOT#

Close to Processor
pin

3

VGATE <8,12,19,29>

PCH_POK <12,19>

+VCCP

R1196

R1196
68_0402_5%

68_0402_5%

Place closed to chipset

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_ENBKL

1 2
1 2
1 2

100K_0402_5%

100K_0402_5%

LVDSAC-<9>
LVDSAC+<9>
LVDSA0-<9>
LVDSA0+<9>
LVDSA1-<9>
LVDSA1+<9>
LVDSA2-<9>
LVDSA2+<9>

GMCH_ENBKL<19>

EDID_CLK_LCD<9>

EDID_DAT_LCD<9>

GMCH_LVDDEN<9>

XDP_BPM#0<4>
XDP_BPM#1<4>
XDP_BPM#2<4>
XDP_BPM#3<4>

R1203

R1203
150_0402_1%

150_0402_1%
R1200

R1200
150_0402_1%

150_0402_1%
R1204

R1204
150_0402_1%

150_0402_1%
R1205

R1205

U31D

U31D

U25

LA_CLKN

U26

LA_CLKP

R23

LA_DATAN_0

R24

LA_DATAP_0

N26

LA_DATAN_1

N27

LA_DATAP_1

R26

LA_DATAN_2

R27

LA_DATAP_2

R1190

R1190

2.37K_0402_1%

2.37K_0402_1%

GMCH_ENBKL

R1192

R1192
100K_0402_5%

100K_0402_5%

1 2
1 2
1 2
1 2

R1209

R1209
R1211

R1211
R1214

R1214
R1253

R1253

H_THERMDA
H_THERMDC

H_GTLREF

XDP_TDI
XDP_TDO
XDP_TCK

C939

@ C939

@

XDP_TDI<4>
XDP_TDO<4>
XDP_TCK<4>
XDP_TMS<4>
XDP_TRST#<4>

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

T34T34
T35T35
T36T36
T37T37

T38T38

XDP_TMS
XDP_TRST#

1

2

1U_0603_10V4Z

1U_0603_10V4Z

G11
G13

R22
N22

N23

K25
K23
K24
H26

E15
F13
B18

B20
C20
B21

D14
D13
B14
C14
C16

D30
E30

C30
D31

J28

L27
L26
L23

G5

LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN

BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

RSVD
TDI
TDO
TCK
TMS
TRST#

THRMDA_1
THRMDC_1

THRMDA_2/RSVD
THRMDC_2/RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

R1197

R1197
1K_0402_1%

1K_0402_1%

R1201

R1201
2K_0402_1%

2K_0402_1%

2

PINEVIEW_M

PINEVIEW_M

LVDS

LVDS

4 OF 6

4 OF 6

REV = 1.1

REV = 1.1

ICH

ICH

CPU

CPU

placed within 0.5"
of processor pin.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

H_SMI#

SMI#
A20M#
FERR#

LINT0
LINT1

IGNNE#

STPCLK#

DPRSTP#

DPSLP#

INIT#
PRDY#
PREQ#

THERMTRIP#

PROCHOT#

CPUPWRGOOD

GTLREF

RSVD
RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

EXTBGREF

VSS

E7
H7
H6
F10
F11
E5
F8

G6
G10
G8

R1254 0_0402_5%R1254 0_0402_5%

E11
F15

H_THERMTRIP#

E13

H_PROCHOT#

C18
W1

A13
H27

L6
E17

H10
J10

CPU_BSEL0

K5

CPU_BSEL1

H5

CPU_BSEL2

K6

CPU_VID0

H30

CPU_VID1

H29

CPU_VID2

H28

CPU_VID3

G30

CPU_VID4

G29

CPU_VID5

F29

CPU_VID6

E29
L7

D20
H13
D18

K9
D19

H_EXTBGREF

K7

H_EXTBGREF

H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#

H_DPRSTP#
H_DPSLP#
H_INIT#

1 2

1 2

R1255 0_0402_5%R1255 0_0402_5%

H_PWRGD

H_GTLREF

CLK_CPU_BCLK#
CLK_CPU_BCLK

T39T39
T40T40

H_SMI# <11>
H_A20M# <11>
H_FERR# <11>
H_INTR <11>
H_NMI <11>
H_IGNNE# <11>
H_STPCLK# <11>

H_DPRSTP# <12>
H_DPSLP# <12>
H_INIT# <11>

H_THERMTRIP# <11>

H_PWRGD <4,12>

CPU_BSEL0 <8>
CPU_BSEL1 <8>
CPU_BSEL2 <8>

CPU_VID0 <29>
CPU_VID1 <29>
CPU_VID2 <29>
CPU_VID3 <29>
CPU_VID4 <29>
CPU_VID5 <29>
CPU_VID6 <29>

1

C940

C940

2

@

@

1U_0603_10V4Z

1U_0603_10V4Z

XDP_PRDY# <4>
XDP_PREQ# <4>

CLK_CPU_BCLK# <8>
CLK_CPU_BCLK <8>

+VCCP+VCCP

R1199

R1199
976_0402_1%

976_0402_1%

R1202

R1202

3.3K_0402_1%

3.3K_0402_1%

placed within 0.5"
of processor pin.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

533Wednesday, September 16, 2009

533Wednesday, September 16, 2009

533Wednesday, September 16, 2009

1

of

of

of

A

A

A

5

U31E

1

2

T13
T14
T16
T18
T19
V13

V19
W14
W16
W18
W19

AK13
AK19

AK9

AL11
AL16
AL21
AL25

AK7

AL7

U10

U5
U6
U7
U8
U9

V2
V3

V4
W10
W11

AA10
AA11

AA19

V11

AC31

T30

T31
J31

C3

B2

C2

A21

1

C952

C952

2

1U_0402_6.3V6K

1U_0402_6.3V6K

U31E

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

VCCACRTDAC

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

C954

C954

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

5 OF 6

5 OF 6

C927

C927

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

GFX/MCH

GFX/MCH

DDR

DDR

POWER

POWER

EXP\CRT\PLL

EXP\CRT\PLL

DMI

DMI

1

1

+

+

C995

C995

330U 2.5V Y

330U 2.5V Y

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

GFX supply current: 1.38A
Sustained GFX supply current: 1.05A

2.2U_0603_10V6K

2.2U_0603_10V6K

2

C930

C930

C929

C929

1

2.2U_0603_10V6K

2.2U_0603_10V6K

+0.89VS

2

C931

C931

1

D D

DDR supply current: 2.27A

+1.8V

2.2U_0603_10V6K

2.2U_0603_10V6K

2

2

C928

C928

1

1

2.2U_0603_10V6K

+1.8V

C C

2.2U_0603_10V6K

07/17

+VCCP

1

DDR analog supply current: 1.32A

C933

C933

2

22U_0805_6.3V6M

22U_0805_6.3V6M

Display PLL SFR and CRT DAC supply
current: 0.154A

B B

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL
supply current: 0.33A

A A

+VCCP

+1.8VS

R1212

R1212
0_0603_5%

0_0603_5%

1 2

+3VS

GIO supply current:0.006A

+RING_EAST
+RING_WEST

+0.89VS

2

C946

C946

1

2.2U_0603_10V6K

2.2U_0603_10V6K

C941

C941

1U_0603_10V4Z

1U_0603_10V4Z

C947

C947

1

1

C942

C942

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C949

C949

C948

C948

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_CRT_DAC

1

1

C950

C950

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C951

C951

1U_0402_6.3V6K

1U_0402_6.3V6K

Close Chipset pin

5

CPU

CPU

LVDS

LVDS

VCCSFR_DMIHMPLL

1

C1000

C1000

2

10U_0805_10V6K~D

10U_0805_10V6K~D

4

VCCSENSE
VSSSENSE

VCCA

VCCP
VCCP

VCCP

VCCALVDS
VCCDLVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

RSVD

VCCP

4

1U_0402_6.3V6K

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

C29
B29
Y2

D4
B4

B3

V30
W31

T1
T2
T3

P2
AA1

E2

1U_0402_6.3V6K

VCCSENSE
VSSSENSE

Processor Core analog supply current: 0.08A

+VCCP

+VCC_ALVD
+VCC_DLVD

LVDS supply current: 0.06A

+VCC_DMI

DMI analog supply current: 0.48A

+DMI_HMPLL

SFR & DMIHMPLL supply current: 0.104A

VCCSENSE

VSSSENSE

1

C919

C919

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+CPU_CORE

330U 2.5V Y

330U 2.5V Y

VSSSENSE <29>

1

C391

C391

0.01U_0402_16V7K

0.01U_0402_16V7K

2

T41T41

+VCCP

R1218

R1218

1 2

100_0402_1%

100_0402_1%
R1219

R1219

1 2

100_0402_1%

100_0402_1%

1

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C916

C916

2 x 330uF(9mohm/2)

+

+

C921

C921

3

22U_0805_6.3V6M

22U_0805_6.3V6M

@

1

C920

C920

2

1U_0402_6.3V6K

1U_0402_6.3V6K

PLACE IN CAVITY

330U 2.5V Y

330U 2.5V Y

+1.5VS

+CPU_CORE

@

1

1

C922

C922

C917

C917

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

+

+

C918

C918

330U 2.5V Y

330U 2.5V Y

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

1

C269

C269

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

+

+

C923

C923

2

+CPU_CORE

Add 22U x3

1

C271

C271

C272

C272

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

07/17

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

1

C924

C924

1

C925

C925

2

22U_0805_6.3V6M

22U_0805_6.3V6M

Close to U71.E2

Close to U71.D4

R1207

R1207

1 2

0_0603_5%

0_0603_5%

R1208

R1208

1 2

0_0603_5%

0_0603_5%

1U_0603_10V4Z

1U_0603_10V4Z

R1210

R1210

1 2

0_0805_5%

0_0805_5%

C937

C937

1U_0603_10V4Z

1U_0603_10V4Z

+1.8VS

R1213

R1213

1 2

MBK2012601_YZF

MBK2012601_YZF

R1215

R1215

1 2

0_0603_5%

0_0603_5%

R1216

R1216

1 2

0.1UH_MLF1608DR10KT_10%~D

0.1UH_MLF1608DR10KT_10%~D

R1217

R1217

1 2

0_0805_5%

0_0805_5%

Compal Secret Data

Compal Secret Data

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Compal Secret Data

2

Close to U31.U10

1

C934

C934

2

1

1U_0603_10V4Z

1U_0603_10V4Z

2

Close to Pin T1

+VCC_CRT_DAC

1

C943

C943
1U_0603_10V4Z

1U_0603_10V4Z

2

+DMI_HMPLL

1

C944

C944
1U_0603_10V4Z

1U_0603_10V4Z

2

+VCC_ALVD

1

C56

C56
22U_0805_6.3V6M

22U_0805_6.3V6M

2

+VCC_DLVD

1

C953

C953
1U_0603_10V4Z

1U_0603_10V4Z

2

Deciphered Date

Deciphered Date

Deciphered Date

1

2

C926

C926

1U_0603_10V4Z

1U_0603_10V4Z

+RING_EAST

1

C932

C932
1U_0603_10V4Z

1U_0603_10V4Z

2

+RING_WEST

1

C935

C935
1U_0603_10V4Z

1U_0603_10V4Z

2

C938

C938

2

1

2

+VCC_DMIVCCSENSE <29>

07/17

2

1

PINEVIEW_M

PINEVIEW_M

U31F

U31F

REV = 1.1

REV = 1.1

A11

VSS

A16

VSS

A19

VSS

A29

RSVD_NCTF

A3

RSVD_NCTF

A30

RSVD_NCTF

A4

RSVD_NCTF

AA13

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA2

VSS

AA22

VSS

AA25

VSS

AA26

VSS

AA29

VSS

AA8

VSS

AB19

VSS

AB21

VSS

AB28

VSS

AB29

VSS

AB30

VSS

AC10

VSS

AC11

VSS

AC19

VSS

AC2

VSS

AC21
AC28
AC30
AD26

AD5

AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10

AG3
AH18
AH23
AH28

AH4
AH6
AH8

AJ1
AJ16
AJ31

AK1

AK2
AK23
AK30
AK31
AL13
AL19

AL2
AL23
AL29

AL3
AL30

AL9

B13

B16

B19

B22

B30

B31

B5
B9

C1
C12
C21
C22
C25
C31
D22

E1
E10
E19
E21
E25

E8
F17
F19

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

GND

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 6

6 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

T29

of

of

of

633Wednesday, September 16, 2009

633Wednesday, September 16, 2009

1

633Wednesday, September 16, 2009

A

A

A

5

DDR_A_DQS#[0..7]<4>

DDR_A_D[0..63]<4>

DDR_A_DM[0..7]<4>

DDR_A_DQS[0..7]<4>

DDR_A_MA[0..14]<4>

D D

+1.8V

1

1

2

2

C1021

C1021

C1020

C1020

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

+

+

@

@

2

C1030

C1030

C1031

C1042

C1042

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1031

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

1

2

C1043

C1043

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

RP1

RP1

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP3

RP3

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP5

RP5

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

R168

R168

1 2

47_0402_5%

47_0402_5%
R64

R64

1 2

47_0402_5%

47_0402_5%
R59

R59

1 2

47_0402_5%

47_0402_5%

5

C C

+0.9VS

1

C1040

C1040

1

2

2

C1041

C1041

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

DDR_A_RAS#
DDR_CS#0
DDR_A_MA13
M_ODT0

DDR_A_BS0
DDR_A_MA10

DDR_A_MA1

DDR_A_MA3

M_ODT1
DDR_CS#1
DDR_A_CAS#
DDR_A_WE#

DDR_CKE1
DDR_A_BS2
DDR_CKE0

B B

A A

C1022

C1022

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

C1032

C1032

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Layout Note:
Place one cap close to every 2 pull-up
resistors terminated to +0.9VS.
(check list page 18)

1

2

C1044

C1044

C1045

C1045

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+0.9VS

1

2

C1023

C1023

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

1

2

2

C1033

C1033

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C1047

C1047

C1046

C1046

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

RP2

RP2

18
27
36
45

47_0804_8P4R_5%

47_0804_8P4R_5%

RP4

RP4

18
27
36
45

47_0804_8P4R_5%

47_0804_8P4R_5%

RP6

RP6

18
27
36
45

47_0804_8P4R_5%

47_0804_8P4R_5%

1

2

C1034

C1034

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

DDR_A_MA5
DDR_A_MA9
DDR_A_MA8

DDR_A_MA12

Share +DIMM_VREF for

1.DDRII VREF

2.GMCH SM_VREF_0
SM_VREF_1

Layout Note:
Place near JDIM1

1

2

C1024

C1024

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C1049

C1049

C1048

C1048

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

DDR_A_BS1

DDR_A_MA0
DDR_A_MA2
DDR_A_MA4

DDR_A_MA6
DDR_A_MA7

DDR_A_MA11

DDR_A_MA14

1

2

C1050

C1050

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4

1

1

2

2

C1052

C1052

C1051

C1051

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Layout Note:
Place these resistor
closely DIMMA,all
trace length Max=1.0"

4

+1.8V

12

R1343

R1343

1K_0402_1%

1K_0402_1%

12

R1345

R1345

1K_0402_1%

1K_0402_1%

Schematic Note:
Follow Intel check list recommand, we add
8 CAP.

1

2

C1053

C1053

1

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1054

C1054

1

2

2

C1055

C1055

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+DIMM_VREF

Layout Note:
Place near JDIM1

+DIMM_VREF

1

C1056

C1056

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1057

C1057

1

2

2

C1058

C1058

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2009-5-27 modify

C1062

C1062

20mils

1

C1016

C1016

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2009-5-27 modify

1

1

2

2

C1059

C1059

C1060

C1060

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3VS

1

C1061

C1061

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

3

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C1018

C1018

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2

DDR_CKE0<4>

DDR_A_BS2<4>

DDR_A_BS0<4>
DDR_A_WE#<4>

DDR_A_CAS#<4>

DDR_CS#1<4>

M_ODT1<4>

CLK_SMBDATA<8>

CLK_SMBCLK<8>

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS#1

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SMBDATA

CLK_SMBCLK

2

+1.8V +1.8V

JDIM1

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

G1

TYCO_292525-4

TYCO_292525-4

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

201

DIMM_A(REV)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3
DQ30

DQ31

RAS#

ODT0

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SA0
SA1

1

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D14

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

G2

DDR_A_DM2

52
54

DDR_A_D22

56

DDR_A_D23

58
60

DDR_A_D28

62

DDR_A_D29

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D30

74

DDR_A_D31

76
78

DDR_CKE1

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90

DDR_A_MA7

92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS#0

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D38

134

DDR_A_D39

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D46

152

DDR_A_D47

154
156

DDR_A_D52

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

R1347 10K_0402_5%R1347 10K_0402_5%

198

R1349 10K_0402_5%R1349 10K_0402_5%

200

202

1 2
1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

M_CLK_DDR0 <4>
M_CLK_DDR#0 <4>

R1344

R1344

1 2

0_0402_5%

0_0402_5%

DDR_CKE1 <4>

DDR_A_BS1 <4>
DDR_A_RAS# <4>
DDR_CS#0 <4>

M_ODT0 <4>

M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

1

PM_EXTTS#0 <5>

733Wednesday, September 16, 2009

733Wednesday, September 16, 2009

733Wednesday, September 16, 2009

A

A

A

of

of

of

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

*

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

111

+VCCP

2009-5-27 modify

R138

R138

2.2K_0402_5%

2.2K_0402_5%

1 2

R147

R147
0_0402_5%

0_0402_5%

12

1 2

12

+VCCP

FSA

C C

CPU_BSEL0<5>

2009-5-27 modify

R86

R86
1K_0402_1%

1K_0402_1%

FSB

CPU_BSEL1<5>

B B

2009-5-27 modify

10K_0402_5%

10K_0402_5%

FSC

CPU_BSEL2<5>

1 2

R91

R91
0_0402_5%

0_0402_5%

R100

R100

1 2

R95

R95
0_0402_5%

0_0402_5%

1 2

12

12

+VCCP

1 2

12

12

2009-5-27 modify

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

A A

C169 22P_0402_50V8JC169 22P_0402_50V8J

14.31818MHZ_16PF_DSX840GA

14.31818MHZ_16PF_DSX840GA

C162 22P_0402_50V8JC162 22P_0402_50V8J

12

Y6

Y6

Routing the trace at least 10mil

5

Reserved

R140

R140
470_0402_5%~D

470_0402_5%~D

R141

@R141

@

1K_0402_1%

1K_0402_1%

2009-08-04 modify

CLK_ENABLE#<29>

2009-08-04 modify

10K_0402_5%

10K_0402_5%

2

2009-08-04 modify

R81

R81
470_0402_5%~D

470_0402_5%~D

R82

@R82

@

0_0402_5%

0_0402_5%

R97

@R97

@

470_0402_5%~D

470_0402_5%~D

R98

@R98

@

0_0402_5%

0_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

CLK_XTAL_IN

CLK_XTAL_OUT

2009-08-04 modify

Schematic Note:
33 ohm series-resistor need add for singal end clock.

CLK_PCI_LPC<19>
CLK_PCI_ICH<10>

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

+3VS+3VS +3VS

R129

R129
10K_0402_5%

10K_0402_5%

1 2

ITP_EN PCI4_SEL PCI2_TME

@R132

@

10K_0402_5%

10K_0402_5%

1 2

1 2

R132

1 2

+3VS

+VCCP

+3VS

R435

R435

R119

@R119

@

10K_0402_5%

10K_0402_5%

R117

R117

10K_0402_5%

10K_0402_5%

4

1 2
13

DTC124EK_SC59

DTC124EK_SC59

CLK_ICH_48M<12>

CLK_ICH_14M<12>

CLK_EN

H_STP_CPU#<12>

H_STP_PCI#<12>

4

1 2

R78 0_0805_5%R78 0_0805_5%

1 2

R131 0_0805_5%R131 0_0805_5%

CLK_EN

Q32

Q32

VGATE<5,12,19,29>

1

C1012

C1012

@

@

2

10P_0402_50V8J~D

10P_0402_50V8J~D

R109

R109
10K_0402_5%

10K_0402_5%

1 2

R110

@R110

@

10K_0402_5%

10K_0402_5%

1 2

+3VM_CK505

10U_0805_10V6K~D

10U_0805_10V6K~D

1

C151

C151

2

+1.05VM_CK505

1

2

2009-8-10 modify

+1.5VM_CK505

+1.05VM_CK505

1 2

12

C8325P_0402_50V8C @C8325P_0402_50V8C @

1 2

1 2

C392 10P_0402_50V8J~D

C392 10P_0402_50V8J~D

@

@

1 2

1 2
1 2

1

C1013

C1013

@

@

2

10P_0402_50V8J~D

10P_0402_50V8J~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C181

C181

2

C163

C163
10U_0805_10V6K~D

10U_0805_10V6K~D

2009-8-10 modify

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C197

C197

2

C198

C198

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C175

C175

1

2

1

C936

@C936

@

2

1

C152

C152

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

3

R94 0_0805_5%R94 0_0805_5%

1 2

47P_0402_50V8J

47P_0402_50V8J

C199

C199

1

C153

C153

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C155

C155

1

C167

C167

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

R137

R137

33_0402_5%

33_0402_5%

R101

R101

33_0402_5%

33_0402_5%

R13270_0402_5% @R13270_0402_5% @

R1334 33_0402_5%R1334 33_0402_5%

R1335

R1335

33_0402_5%

33_0402_5%

+3VM_CK505

FSA
FSB

FSC

H_STP_CPU#
H_STP_PCI#

CLK_XTAL_IN
CLK_XTAL_OUT

PCI2_TME

PCI4_SEL
ITP_EN

U11

U11

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VTR_QFN72_10X10

SLG8SP556VTR_QFN72_10X10

3

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SLKREQ_10#
CLKREQ_11#

USB_1/CLKREQ_A#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#
CLKREQ_9#

2

+1.5VM_CK505

SDA
SCL

R102 0_0805_5%@ R102 0_0805_5%@

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C154

C154

2

1

C189

C189

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

CLK_SMBDATA

9

CLK_SMBCLK

10

CLK_CPU_BCLK

71

CLK_CPU_BCLK#

70

CLK_CPU_HPLCLK

68

CLK_CPU_HPLCLK#

67

CPU_DREFCLK

24

CPU_DREFCLK#

25

CPU_SSCDREFCLK

28

CPU_SSCDREFCLK#

29

CLK_CPU_EXP

32

CLK_CPU_EXP#

33

35
36

CLK_PCIE_SATA

39

CLK_PCIE_SATA#

40

CLK_PCIE_WLAN

57

CLK_PCIE_WLAN#

56

CLK_PCIE_MCP

61

CLK_PCIE_MCP#

60

CPU_ITP

64

CPU_ITP#

63

CLK_PCIE_LAN

44

CLK_PCIE_LAN#

45

CLK_PCIE_ICH

50

CLK_PCIE_ICH#

51

CLK_PCIE_WWAN

48

CLK_PCIE_WWAN#

47

37
41

WLAN_CLKREQ#

58

MCP_CLKREQ#

65

CLKREQ_LAN#

43
49

WWAN_REQ#11

46
21

2007/10/15 2009/06/22

2007/10/15 2009/06/22

2007/10/15 2009/06/22

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

@C156

@

C182

@C182

@

2

1

C200

C200

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2009-08-17 modify

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

C156

2

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.5VS

10U_0805_10V6K~D

10U_0805_10V6K~D

1

@

@

C945

C945
47P_0402_50V8J

47P_0402_50V8J

2

CLK_SMBDATA <7>
CLK_SMBCLK <7>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>
CLK_CPU_HPLCLK <5>
CLK_CPU_HPLCLK# <5>

CPU_DREFCLK <5>
CPU_DREFCLK# <5>

CPU_SSCDREFCLK <5>
CPU_SSCDREFCLK# <5>

CLK_CPU_EXP <4>
CLK_CPU_EXP# <4>

CLK_PCIE_SATA <11>
CLK_PCIE_SATA# <11>

CLK_PCIE_WLAN <14>
CLK_PCIE_WLAN# <14>

CLK_PCIE_MCP <14>
CLK_PCIE_MCP# <14>

CPU_ITP <4>
CPU_ITP# <4>

CLK_PCIE_LAN <18>
CLK_PCIE_LAN# <18>

CLK_PCIE_ICH <12>
CLK_PCIE_ICH# <12>

CLK_PCIE_WWAN <14>
CLK_PCIE_WWAN# <14>

WLAN_CLKREQ# <14>
MCP_CLKREQ# <14>
CLKREQ_LAN# <18>

WWAN_REQ#11 <14>

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

ICH_SMBDATA<12>

+3VS

ICH_SMBCLK<12>

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Co-Layout circuit

Silego,ICS +3VS
Realtek

+3VS,+1.5VS

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

+3VS

R112

R112

2.2K_0402_5%

2.2K_0402_5%
Q10A

Q10A

6 1

2
5

3

4

Q10B

Q10B

De-pop R102,pop R94
De-pop R94,pop R102

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

WWAN_REQ#11
WLAN_CLKREQ#
CLKREQ_LAN#
MCP_CLKREQ#
H_STP_CPU#
H_STP_PCI#

07/17

DEVICE

CPU_VGA
DMI

PCIE_SATA
PCIE_WLAN
PCIE_MCP
CPU_XDP
PCIE_LAN
PCIE_TigerPoint
PCIE_WWAN

R139

R139
R84

R84
R111

R111
R113

R113
R121

R121
R124

R124

REQ PORT LIST

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

PCIE_WLAN
PCIE_MCP
PCIE_LAN

PCIE_WWAN

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

1

R108

R108

2.2K_0402_5%

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

10K_0402_5%

10K_0402_5%

12

10K_0402_5%

10K_0402_5%

12

10K_0402_5%

10K_0402_5%

12

10K_0402_5%

10K_0402_5%

12

10K_0402_5%

10K_0402_5%

12

10K_0402_5%

10K_0402_5%

12

+3VS

A

A

A

of

833Wednesday, September 16, 2009

of

833Wednesday, September 16, 2009

of

833Wednesday, September 16, 2009

5

4

3

2

1

+LCDVDD

R70

R70

470_0805_5%

D D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

C C

470_0805_5%

GMCH_LVDDEN<5>

100K_0402_5%

100K_0402_5%

08/04
(TouchScreen)

USB20_P6_TS<12>

USB20_N6_TS<12>

Q29A

Q29A

R72

R72

+5VALW

12

61

2

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1 2

WCM2012F2S-900T04_0805@

WCM2012F2S-900T04_0805@

3

3

2

2

R63

R63
1M_0402_5%

1M_0402_5%

1 2

1 2

100K_0402_5%

100K_0402_5%

3

Q29B

Q29B

4

R1168

@ R1168

@

0_0402_5%

0_0402_5%

R1169

@ R1169

@

0_0402_5%

0_0402_5%

R73

R73

L65

L65

12

4

1

12

2

1

1000P_0402_50V7K

1000P_0402_50V7K

4

1

MIC_DATA<15>

MIC_CLK<15>

BKOFF#<19>

C395

C395

+3VS

W=60mils

Q3

Q3

S

S

G

G

AO3413_SOT23

AO3413_SOT23

2

D

D

W=60mils

1 3

C396

@C396

@

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

LVDSA0+<5>
LVDSA0-<5>

LVDSA2+<5>
LVDSA2-<5>

L25

L25

1 2

FBMA-L10-160808 301LMT_0603

FBMA-L10-160808 301LMT_0603

BKOFF#

100P_0402_50V8J

100P_0402_50V8J

C229

C229

@

@

+LCDVDD

1

C394

C394

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

R60

R60

4.7K_0402_5%

4.7K_0402_5%

1

2

+3VS

(TouchScreen)

12

USB20_TS_P
USB20_TS_N

@

@

1

C230

C230

2

100P_0402_50V8J

100P_0402_50V8J

LCD POWER CIRCUIT

+LCDVDD +LCDVDD_R +3VS +3VS_LCD +3VS +VMIC

L21

L21

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 2

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

LCD/PANEL BD. Conn.

+CAM_VDD

+LCDVDD_R

JP24

JP24

42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

8
6
4
2

ACES_87242-4001-09

ACES_87242-4001-09

GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

C398

C398

GMD

1

C397

C397

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

INVPWR_B+ +3VS_LCD +VMIC

41
39

39

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

1 2

LCD_TST

Change to SP02000MD00

+CAM_VDD+5VALW

R35

R35

0_0603_5%

0_0603_5%

LVDC+
LVDC-

1
C600

2

1

2

R69

R69

2.2K_0402_5%

2.2K_0402_5%

R1027 0_0402_5%R1027 0_0402_5%

1 2

R1026 0_0402_5%R1026 0_0402_5%

LCD_TST <19>

C600
100P_0402_50V8J

100P_0402_50V8J

W=20mils

C45

C45

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3VS

12

12

12

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

2009-4-15

R65

R65

2.2K_0402_5%

2.2K_0402_5%

1

C231

C231

2

100P_0402_50V8J

100P_0402_50V8J

1 2

EDID_CLK_LCD <5>
EDID_DAT_LCD <5>

LVDSA1+ <5>
LVDSA1- <5>

LVDSAC+ <5>
LVDSAC- <5>

INVT_PWM <19>

L22

L22

FBMA-L11-201209-221LMA30T_0805

1

2

USBP3

USBN3

FBMA-L11-201209-221LMA30T_0805

C399

C399

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R44

R44

1 2

0_0402_5%

0_0402_5%

@

@

WCM2012F2S-900T04_0805

WCM2012F2S-900T04_0805

4

4

1

1

L64

L64

R46

R46

1 2

0_0402_5%

0_0402_5%

3

2

1 2

3

2

L37

L37

1

C647

C647

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2009-08-13 modify

USB20_P3 <12>

USB20_N3 <12>

07/17 BITS

B B

L18

L18
FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

1

C85

C85

68P_0402_50V8J~D

68P_0402_50V8J~D

40mil

1

C829

@C829

@

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2

A A

5

12

@R1158

@

100K_0402_5%

100K_0402_5%

R1159 100K_0402_5%@R1159 100K_0402_5%@

BKOFF#

R1158

1 2

2

@

@

SI3457BDV-T1-E3_TSOP6~D

SI3457BDV-T1-E3_TSOP6~D

S

S

4 5

G

G

3

PWR_SRC_ON

INVPWR_B+B+

1

C393

C393

0.1U_0603_25V7K

0.1U_0603_25V7K

2

Q80

Q80

D

D

6
2

1

Q81

@

Q81

@

RHU002N06_SOT323-3~D

RHU002N06_SOT323-3~D

D

S

D

S

1 3

G

G

2

4

40mil

1

C830

@C830

@

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

2

2009-08-17 modify

LVDSAC+
LVDSAC-

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/03/25 2009/06/22

2009/03/25 2009/06/22

2009/03/25 2009/06/22

100P_0402_50V8J

@C233

100P_0402_50V8J

@

100P_0402_50V8J

@C232

100P_0402_50V8J

@

C233

C232

1

1

2

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

933Wednesday, September 16, 2009

933Wednesday, September 16, 2009

933Wednesday, September 16, 2009

1

of

of

of

A

A

A

5

D D

4

3

2

1

+3VS

R1220

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

10K_0402_5%

10K_0402_5%

CLK_PCI_ICH<8>

R1233

R1233

@

@

R1234

R1234
10K_0402_5%

10K_0402_5%

@

@

10K_0402_5%

10K_0402_5%

R1243

@

@

R1322

R1322

PCI_RST#<19>

C C

CLK_PCI_ICH

12

R1232

R1232

@

@

33_0402_5%

33_0402_5%

1

C955

C955

@

@

22P_0402_50V8J

22P_0402_50V8J

2

For EMI, close to TigerPoint

B B

R1154

R1154
100K_0402_5%

100K_0402_5%

1 2

1 2

0_0402_5%

0_0402_5%

R1220

R12218.2K_0402_5% R12218.2K_0402_5%
R1222

R1222
R12248.2K_0402_5% R12248.2K_0402_5%
R12238.2K_0402_5% R12238.2K_0402_5%
R12258.2K_0402_5% R12258.2K_0402_5%
R12268.2K_0402_5% R12268.2K_0402_5%
R12278.2K_0402_5% R12278.2K_0402_5%

R12288.2K_0402_5% R12288.2K_0402_5%
R12298.2K_0402_5% R12298.2K_0402_5%

R123010K_0402_5% R123010K_0402_5%
R123110K_0402_5% R123110K_0402_5%

R12358.2K_0402_5% R12358.2K_0402_5%
R12368.2K_0402_5% R12368.2K_0402_5%
R12378.2K_0402_5% R12378.2K_0402_5%
R12388.2K_0402_5% R12388.2K_0402_5%
R12398.2K_0402_5% R12398.2K_0402_5%
R12408.2K_0402_5% R12408.2K_0402_5%
R12418.2K_0402_5% R12418.2K_0402_5%
R12428.2K_0402_5% R12428.2K_0402_5%

R12448.2K_0402_5% R12448.2K_0402_5%R1243

R12458.2K_0402_5% R12458.2K_0402_5%

PCI_DEVSEL#
CLK_PCI_ICH

PCI_IRDY#
PCI_SERR#

PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

PCI_REQ1#
PCI_REQ2#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

U34A

U34A

A5

PAR

B15

DEVSEL#

J12

PCICLK

A23

PCIRST#

B7

IRDY#

C22

PME#

B11

SERR#

F14

STOP#

A8

PLOCK#

A10

TRDY#

D10

PERR#

A16

FRAME#

A18

GNT1#

E16

GNT2#

G16

REQ1#

A20

REQ2#

G14

GPIO48/STRAP1#

A2

GPIO17/STRAP2#

C15

GPIO22

C9

GPIO1

B2

PIRQA#

D7

PIRQB#

B3

PIRQC#

H10

PIRQD#

E8

PIRQE#/GPIO2

D6

PIRQF#/GPIO3

H8

PIRQG#/GPIO4

F8

PIRQH#/GPIO5

D11

STRAP0#

K9

RSVD01

M13

RSVD02

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

TGP

TGP

PCI

PCI

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1

1

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

H16
M15
C13
L16

A A

Security Classification

Security Classification

Security Classification

2009/03/25 2009/06/22

2009/03/25 2009/06/22

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/03/25 2009/06/22

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

SCHEMATIC, MB A5732

401784

401784

401784

10 33Wednesday, September 16, 2009

10 33Wednesday, September 16, 2009

10 33Wednesday, September 16, 2009

1

A

A

A

of

of

of