Dell Latitude G3 3579 Schematics

A

B

C

D

E

ZZZ

COMPAL CONFIDENTIAL

1 1

MODEL NAME : Loki-G 15/17

UC1

MB PCB PN : DAA000FC010 PWR/B PCB PN : DA4002L3010 IO/B PCB PN : DA6001XF010

2 2

UC1

PCB R1

DAA000FC010

PCB@

CPU R1

SA0000BPJ1L

i5@

SA0000BPZ1L

i7@

UC1

CPU R3

SA0000BPJ2L

i5@

SA0000BPZ2L

i7@

Dell/Compal Confidential

Schematic Document

COFFEE LAKE H

3 3

N17P-G0/G1

Loki-G 15/17

2018-03-22

REV : 1.0 (A00)

Layout Dell logo

4 4

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

Cover Page

LA-F611P

0.3

1 7 8Thursday, March 22, 2018

E

A

B

C

D

E

VRAM * 4 GDDR5

GPU N17P-G0/G1

GB4-128

PEG 3.0 x8

DDR4 ChannelA DDR4 ChannelB

Intel

1 1

HDMI 2.0

Conn.

HDMI2.0

Re-Timer

PS8409A

IFPx

DDI1 x4

USB3.1 TypeC

3

USB2.0/C C

TPS65982DC

I2C/USB2. 0

RJ45

2 2

USB3.1 Gen1

Thunderbolt Alpine Ridge-SP

M.2 Slot A Key-E

(WLAN+BT4.0 )

LOM RTL8111H

M.2 Slot C Key-M

(SATA/PCIe SSD)

PCI-E x4

Port 7-Port 10

PCI-E x1

CNVi

3

3 3

3

Port 15

PCI-E x1

Port 14

PCI-E x4

Port 9-Port 12

SATA 1A

CFL-Lake-H

Processor

45W

BGA

DMI x4

100MH z 5GB/s

Intel

CNL-H-PCH

BGA 874 Balls

eDP1.2 x4

USB2 .0 USB3 .0

USB2 .0

HM370

HDD Conn.

3

Main SPKR *2

Universal Audio Jack

3 3

3

HDA Codec ALC3204

SPI Flash (BIOS 32MB)

TPM NPCT650

Reserved

3

3

3

SATA 0B

HD Audio

SPI

SMBus

I2C

3

USB2 .0

USB2 .0 SD3.0

Port 6

Card Reader 2 in 1 RTS5170 SD / MS

USB2 .0

Port 9

DDRIV-DIMM X2

1.2V DDR4 2400 MHz

32GB Max

15.6'' and 17.3"

HD / FHD

Port 1 Port 1

Port 3 Port 3

Port 2

Port 4

Port 5

Port 8

33

USB 3.0 Type-A

USB 2.0 Type-A

TPS65982D C

Digital Camera Conn.

Touch Panel Conn.

Finger Print

M.2 Slot A Key-E

(WLAN+BT4.0 )

3

3

3

3

Left

Right

I/O Board

FFS LNG2D MT R

Reserved

3

Touch Pad

LED

PS2

3

3

SMBus

4 4

Power Button

3

eSPI

MEC 1416

KBC

Charger & Battery

PWM

FAN

3

I2C

3

333

Thermal Sensor NCT7718W

KB Conn.

3

AC Adaptor

3

Power Button Board

128M*32 x4 =2G 256M*32 x4 =4G

A

B

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Block Diagram

Size

Document Number R ev

LA-F611P

Date : Sheet of

E

2 78Thursday, March 22, 2018

0.3

5

Refer Page 26

Board ID

X00

X01

X02

D D

X03

A00

Resistor

10K

17.8K

27K

37.4K

49.9K

HSIO port Alloction

USB3

DESTINATION

1

USB JUSB1 (Left Side)

2

None

3

USB JUSB3 (Left Side)

4

None

5

None

6

None

4

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

DESTINATION

None

USB3

10

3

7

8

9

DESTINATION

None

2

1

Lane 9

USB2

C C

DESTINATION

1

USB JUSB1 (Left Side)

2

USB JUSB2 (I/O)

3

USB JUSB3 (Left Side)

4

TYPEC PD

CAMERA

5

6

Card Reader (I/O)

7

BT & CNVi BRI

8

Touch Screen

9

Finger Print

10

None

11

12

None

13

14

None

Lane 10

Lane 11

Lane 12

Lane 13

Lane 14

Lane 15

Lane 16

Lane 17

Lane 18

Lane 19

Lane 20

Lane 21

Lane 22

Lane 23

Lane 24

NGFF - NVMe SSD

None (HDD)

LAN

NGFF - WLAN

None

Alpine Ridge - SP

SATA

DESTINATION

0a

1a

0b

1b

2

3None

4

5 None

6 None

7 None

None (NVMe)

NGFF - SSD

HDD

None (LAM)

None (WLAN)

None

DDI

B B

A A

1

2

3

DESTINATION

Alpine Ridge

HDMI2.0 LSPCON PS175

5

CLK_PCIE

4

DESTINATION

0

TBT-AR

1

None

2

None

3

None

4

None

5

None

6

None

7

GPU

None

8

9

NGFF - SSD

10

11

12

13

14

15

None

None None

None

LAN

WLAN

CLK_REQ

10

11

12

13

14

15

0

1

2

3

4

5

6

7

8

9

DESTINATION

TBT-AR

None

GPU

None

NVMe

None

LAN

WLAN

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/01/06

Compal Secret Data

Deciphered Date

2

2018/01/06

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Title

Size

Date : Sheet of

Compal Electronics, Inc.

Notes List

Document Number R ev

Thursday, March 22, 2018

LA-F611P

1

3 78

0.3

5

4

3

2

1

PJP901

SY8286RAC (PU901)

PJPM01

RT8207PGQW

PJPH01

PJPW01

PJP501

PJP301

(PUM01)

TPS51212DS CR

(PUH01)

FUSE 1.5A_2 4V (F1)

RT8816AGQW (PUW01)

SY8180CRAC (PU501)

SY8288BRAC (PU301)

D D

CPU PWR

GPU PWR

C C

Peripheral Device PWR

ADAPTER

CHARGE R ISL9538HRTZ-T (PUB01)

+PWR_ SRC (+19VB )

BATTERY

B B

A A

5

VCCIO_ EN

1.2V_VDDQ _EN

SM_PG_CTRL

EN_5V

EN_3V

NCP302045MNTXG

(PUI01)

NCP302045MN

(PUG01)

NCP302035MNTXG (PUA01)

NCP302045MNTXG (PUV01)

NCP302045MNTXG (PUV02)

NCP302045MNTXG (PUV03)

+VCCIOP

+1.2VP +1.2V_DD R

+0.6VSP

+1.05VP

+DCBAT_LC D

DGPU_PWR OK

1.35VGPUP

+5VALWP

+3VLP

+3VALWP

NCP302045MNTXG

(PUI02)

DRVON PWM1_2PH/ICCMAX 2

DRVON PWM1_1PH/ICCMAX 1

PJP902

PJPM04 PJPM02

PJPM03

PJPH03 PJPH02FBVDD_ EN

PJPW03 PJPW02

PJP502 PJP503

PJP303 PJP302

DRVON PWM2_4PH/A DDR PWM1_4PH/ICCMA X4

+VCC_GT

+VCC_S A

+GPU_CO RE

+VCCIO

EN_VCCSTG_VCCP LL_O C RZ67

+0.6V_DDR _VTT

+1.05VALW

+1.35VS_VGA

+5VALW

BAS40 C (D1)

+RTC_CELL

+RTC_VCC

+3VALW

+VCC_CORE

4

APE8937GN 2

(UZ16)

+1.2V_VCCPL L_OC

JDIMM1/JDIM M2

EN_VCCSTG_VCCP LL_O C

TPS22961

(UZ9)

TPS22961

(UZ15)

SIO_SLP _S4 # SIO_SLP _S3 #

+VCCSTG_O UT

+VCCST_O UT

RC251 +1.05V_XD P

SY6288D20AA C

(UU1)

SY6288D20AA C

(UU3)

EM5209VF

(UZ1)

SN1610042 ZQZR

(UT4)

EM5209VF

(UZ1)

0ohm 0603

(RE2)

SY6288C20AA C

(UL2)

0ohm 0402

(RT97)

0ohm 0805

(RT95)

RB551V-30

(DT18)

EM5209VF

(UZ7)

PJP180 1

RT8061AZQW (PU1801 )

PJP250 1 S IO_SL P_S4 # PJP250 2

RT9059GSP (PU2501)

PJP100 1

RT8061AZQW (PU1001 )

USB_EN#

SIO_SLP _S3 #

JPZ2

AUX_ON

PEX_VDD_EN

POK

RT9058-33GX (PUS04)

RZ48

3.44A

2.8A

+VCCSTG

RZ66

+VCCST

0.24A

0ohm 0603

(R13)

0ohm 0805

(RA1)

0ohm 0603

PLS11, PLS12

3

RH162

PJP180 2

PJP100 2

(RA4)

JP5

AP2330W-7 (UV17)

FUSE 0.5A_1 3.2V (F3)

+TBTA_VBUS_1

+3.3V_VBU S_IN

SY6288C20AA C

(U1)

RT9041E-15G QW (UP1)

+3VALW_DSW

USB30_VC CA

USB20_VC CB

+5VS

+TBTA_VBUS

+3VS

+3VALW_E C

+LAN_VDD 33

+3.3V_TBT_SX

+3VS_TB T

+3VALW_P D

+3V_PCH _PRIM

+1.8VALWP

+2.5VP +2.5V_MEM

+1.0VS_VGA P +1VS_GFX

3.4A

PLS11, PLS12

LCD_VCC_TEST_ EN_R

or

EDP_VDD_ EN

+1.8V_PRI M

+TPAN_VDD

+5V_PVD D

+5V_AVD D

+5V_HDD

+VDISPLAY_VCC

+5V_KB_B L

AON7409 (PQS17,PAS18 )

RB551V-30

(DT17)

+LCDVD D

+1.2V_RTM_IN

+VBUS_DC _TRIP

+3VALW_P D

AOZ1331

(UG12)

LN2306LT1G (QA1)

0ohm 0603 (RE66)

1V8_AON_O N

1V8_MAIN_E N

AON7409 (PQS1,PAS15 )

+1V8_AON

+1V8_MAIN

+VBUS_DC _SS

AON7409 (PQS2,PAS16 )

+1.8V_AVD D

+1.8VALW_E C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2016/01/06 2017/01/06

Deciphered Date

CHARGE R

+SDC_IN

Title

Size

Date: Sheet of

ISL9538HRTZ-T (PUB01)

Compal Electronics, Inc.

Power Rail

Document Number Rev

LA-F611P

1

4 78Thursday, March 22 , 2018

0.3

5

4

3

2

1

D D

PCH

Host

BE26

BF26

SMBCLK SMBDATA

1K

+3V ALW

+3V S

DMN65D8L

499

+3V ALW

BF25

BE24

499

SML0_SMBCL K SML0_S MBDATA

4.7K

Host

C C

BE21

BF21

Slave

BF27

BE27

Address: 0x88/0x89

B B

I2C1_SCL_TCH_PAD I2C1_SDA_TCH_PAD

GPU_THM_SMBCLK GPU_TH M_SMBDAT

+3V S

DMN66D0L

Host

MEC1416

Host

1K

+3V S

PCH_SMBCLK PCH_SMBDATA

499@

@

499

+3V S

Slave

253

254

Slave

253

254

Slave

1

4

Slave

DIMM1

DIMM2

FFS

Address: 0xA0/ 0xA1

Address: 0xA4/ 0xA5

Address: 0x52/0x53

2.2K

@

2.2K

@

1211

9

8

9189

I2C_SCL_TP I2C_SDA_TP

GPU_THM_SMBCLK GPU_TH M_SMBDAT

Host

+TP_VD D

+3VALW_ EC

PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT

+3V S

DMN66D0L

ALL_GPW RGD

DMN53D0L

4.7K

10K

@

10K

@

Slave

8

7

Touch Pad

2.2K

1.8K

+3VALW_ EC

+3V S

Address: 0x2C/0 x2D

+3V S

THM_SML1_CLK THM_SML1_DATA

+1V8_AO N

VGA_SMB_CK2 VGA_SMB_DA 2

Slave

7

BATT

6

Slave

22

CHAGER

21

Slave

8

Thermal

7

Sensor

Address: 0x98/0x99

Slave

T4

GPU

T3

Address: 0x9E/0x9F

Address: 0x16/0x17

Address: 0x12/0x13

TYPEC_SMBCLK TYPEC_SMBDA

0 Ohm

PD_I2C_SCL_R PD_I2C_SDA_R

0 Ohm

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/01/06 2018/01/06

Compal Secret Data

Deciphered Date

2

Slave

B5

TPS65982D

A5

Address: 0x70/0x71

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Numb er Re v

Custom

Dat e: Sheet of

LA-F611P

1

5 78Thursday, March 22, 2018

0.3

A

Main Func = CPU

B

UC1

CFL_H@

C

D

E

1 1

CPU_DP 1_P041 CPU_DP 1_N041 CPU_DP 1_P141 CPU_DP 1_N141 CPU_DP 1_P241

TBT-AR

2 2

3 3

CPU_DP 1_N241 CPU_DP 1_P341 CPU_DP 1_N341

CPU_DP 1_AUXP41

CPU_DP 1_AUXN41

CPU_DP 1_P0 CPU_DP 1_N0 CPU_DP 1_P1 CPU_DP 1_N1 CPU_DP 1_P2 CPU_DP 1_N2 CPU_DP 1_P3 CPU_DP 1_N3

CPU_DP 1_AUXP CPU_DP 1_AUXN

CFL-H_BG A1440

SA011703151

UC1D

K36

DDI1_TXP_0

K37

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_B GA1440

@

CFL_H_SOC

EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29 E29 F28 E28 A29 B29 C28 B28

C26 B26

A33

D37

EDP_TX P0 EDP_TX N0 EDP_TX P1 EDP_TX N1

EDP_AU XP EDP_AU XN

EDP_DISP _UTIL

DP_RCO MP

TC1 TP@

1 2

RC1 24.9_04 02_1%

DP_RCOMP Trace width=5 mils Spacing=20 mils Max length= 600 mils

G27 G25

CPU_DISP A_SDI_C

G29

RC2 20_040 2_5%

12

EDP_TX P0 29 EDP_TX N0 29 EDP_TX P1 29 EDP_TX N1 29

EDP_AU XP 2 9 EDP_AU XN 29

CPU_DISP A_BCLK CPU_DISP A_SDO CPU_DISP A_SDI

eDP

+VCCIO

Check OK

CPU_DISP A_BCLK 1 8 CPU_DISP A_SDO 1 8

CPU_DISP A_SDI 18

4 4

Security Classification

2016/01 /06 2017/01 /06

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(1/8)DDI/eDP

LA-F611P

E

0.3

6 7 8Thursday, March 22, 2018

A

Main Func = CPU

B

C

D

E

DDR_A_ D[0..63]14

1 1

2 2

3 3

For ECC DIMM

DDR_A_ D0 DDR_A_ D1 DDR_A_ D2 DDR_A_ D3 DDR_A_ D4 DDR_A_ D5 DDR_A_ D6 DDR_A_ D7 DDR_A_ D8 DDR_A_ D9 DDR_A_ D10 DDR_A_ D11 DDR_A_ D12 DDR_A_ D13 DDR_A_ D14 DDR_A_ D15 DDR_A_ D16 DDR_A_ D17 DDR_A_ D18 DDR_A_ D19 DDR_A_ D20 DDR_A_ D21 DDR_A_ D22 DDR_A_ D23 DDR_A_ D24 DDR_A_ D25 DDR_A_ D26 DDR_A_ D27 DDR_A_ D28 DDR_A_ D29 DDR_A_ D30 DDR_A_ D31 DDR_A_ D32 DDR_A_ D33 DDR_A_ D34 DDR_A_ D35 DDR_A_ D36 DDR_A_ D37 DDR_A_ D38 DDR_A_ D39 DDR_A_ D40 DDR_A_ D41 DDR_A_ D42 DDR_A_ D43 DDR_A_ D44 DDR_A_ D45 DDR_A_ D46 DDR_A_ D47 DDR_A_ D48 DDR_A_ D49 DDR_A_ D50 DDR_A_ D51 DDR_A_ D52 DDR_A_ D53 DDR_A_ D54 DDR_A_ D55 DDR_A_ D56 DDR_A_ D57 DDR_A_ D58 DDR_A_ D59 DDR_A_ D60 DDR_A_ D61 DDR_A_ D62 DDR_A_ D63

TC4TP@ TC5TP@ TC6TP@ TC7TP@ TC8TP@ TC9TP@ TC10T P@ TC12T P@

UC1A

DDR4(IL)/LP3-DDR4(N IL)

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_B GA1440

CFL_H_SOC

DDRCHANNELA

DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_1/DDR0_CKP_1 DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2 NC/DDR0_CKN_2 NC/DDR0_CKP_3 NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1 DDR0_CKE_2/DDR0_CKE_2 DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2 NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1 NC/DDR0_ODT_2 NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16 DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1 DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

1OF13

DDR0_DQSN_8/DDR0_DQSN_8

LP3/DDR4

AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AA3 U3 P3 L3

BP5 BK3 BF3 BC3 AB3 V3 R3 M3

AY3 BA3

DDR_A_ CLK0 DDR_A_ CLK#0 DDR_A_ CLK1 DDR_A_ CLK#1

DDR_A_ CKE0 DDR_A_ CKE1

DDR_A_ CS#0 DDR_A_ CS#1

DDR_A_ ODT0 DDR_A_ ODT1

DDR_A_ BA0 DDR_A_ BA1 DDR_A_ BG0

DDR_A_ MA16_RAS# DDR_A_ MA14_WE # DDR_A_ MA15_CAS#

DDR_A_ MA0 DDR_A_ MA1 DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13 DDR_A_ BG1 DDR_A_ ACT#

DDR_A_ PAR DDR_A_ ALERT#

DDR_A_ DQS#0 DDR_A_ DQS#1 DDR_A_ DQS#2 DDR_A_ DQS#3 DDR_A_ DQS#4 DDR_A_ DQS#5 DDR_A_ DQS#6 DDR_A_ DQS#7

DDR_A_ DQS0 DDR_A_ DQS1 DDR_A_ DQS2 DDR_A_ DQS3 DDR_A_ DQS4 DDR_A_ DQS5 DDR_A_ DQS6 DDR_A_ DQS7

TC11 TP@ TC13 TP@

DDR_A_ CLK0 14 DDR_A_ CLK#0 14 DDR_A_ CLK1 14 DDR_A_ CLK#1 14

DDR_A_ CKE0 14 DDR_A_ CKE1 14

DDR_A_ CS#0 14 DDR_A_ CS#1 14

DDR_A_ ODT0 14 DDR_A_ ODT1 14

DDR_A_ BA0 14 DDR_A_ BA1 14 DDR_A_ BG0 14

DDR_A_ MA16_RAS# 14 DDR_A_ MA14_WE # 14 DDR_A_ MA15_CAS# 14

DDR_A_ MA0 14 DDR_A_ MA1 14 DDR_A_ MA2 14 DDR_A_ MA3 14 DDR_A_ MA4 14 DDR_A_ MA5 14 DDR_A_ MA6 14 DDR_A_ MA7 14 DDR_A_ MA8 14 DDR_A_ MA9 14 DDR_A_ MA10 1 4 DDR_A_ MA11 1 4 DDR_A_ MA12 1 4 DDR_A_ MA13 1 4 DDR_A_ BG1 14 DDR_A_ ACT# 14

DDR_A_ PAR 14 DDR_A_ ALERT# 14

DDR_A_ DQS#0 14 DDR_A_ DQS#1 14 DDR_A_ DQS#2 14 DDR_A_ DQS#3 14 DDR_A_ DQS#4 14 DDR_A_ DQS#5 14 DDR_A_ DQS#6 14 DDR_A_ DQS#7 14

DDR_A_ DQS0 14 DDR_A_ DQS1 14 DDR_A_ DQS2 14 DDR_A_ DQS3 14 DDR_A_ DQS4 14 DDR_A_ DQS5 14 DDR_A_ DQS6 14 DDR_A_ DQS7 14

For ECC DIMM

4 4

Security Classification

2016/01 /06 2017/01 /06

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(2/8)DIMMA

LA-F611P

0.3

7 7 8Thursday, March 22, 2018

E

A

Main Func = CPU

B

C

D

E

DDR_B_ D[0..63]15

DDR_B_ D0 DDR_B_ D1 DDR_B_ D2 DDR_B_ D3 DDR_B_ D4 DDR_B_ D5

TC14T P@ TC15T P@ TC16T P@ TC17T P@ TC18T P@ TC19T P@ TC20T P@ TC22T P@

DDR_B_ D6 DDR_B_ D7 DDR_B_ D8 DDR_B_ D9 DDR_B_ D10 DDR_B_ D11 DDR_B_ D12 DDR_B_ D13 DDR_B_ D14 DDR_B_ D15 DDR_B_ D16 DDR_B_ D17 DDR_B_ D18 DDR_B_ D19 DDR_B_ D20 DDR_B_ D21 DDR_B_ D22 DDR_B_ D23 DDR_B_ D24 DDR_B_ D25 DDR_B_ D26 DDR_B_ D27 DDR_B_ D28 DDR_B_ D29 DDR_B_ D30 DDR_B_ D31 DDR_B_ D32 DDR_B_ D33 DDR_B_ D34 DDR_B_ D35 DDR_B_ D36 DDR_B_ D37 DDR_B_ D38 DDR_B_ D39

DDR_B_ D40 DDR_B_ D41 DDR_B_ D42 DDR_B_ D43 DDR_B_ D44 DDR_B_ D45 DDR_B_ D46 DDR_B_ D47 DDR_B_ D48 DDR_B_ D49 DDR_B_ D50 DDR_B_ D51 DDR_B_ D52 DDR_B_ D53 DDR_B_ D54 DDR_B_ D55 DDR_B_ D56 DDR_B_ D57 DDR_B_ D58 DDR_B_ D59 DDR_B_ D60 DDR_B_ D61 DDR_B_ D62 DDR_B_ D63

1 1

2 2

3 3

For ECC DIMM

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL_H_SOC

DDRCHANNE LB

DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKN_1/DDR1_CKN_1

NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

NC/DDR1_CS#_2 NC/DDR1_CS#_3

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3

DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

NC/DDR1_PAR

NC/DDR1_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8 DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10

AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BN9 BL9 BG9 BC9 AC9 W9 R9 M9

BP9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

DDR_B_ CLK0 DDR_B_ CLK#0 DDR_B_ CLK1 DDR_B_ CLK#1

DDR_B_ CKE0 DDR_B_ CKE1

DDR_B_ CS#0 DDR_B_ CS#1

DDR_B_ ODT0 DDR_B_ ODT1

DDR_B_ MA16_RAS# DDR_B_ MA14_WE # DDR_B_ MA15_CAS#

DDR_B_ BA0 DDR_B_ BA1 DDR_B_ BG0

DDR_B_ MA0 DDR_B_ MA1 DDR_B_ MA2 DDR_B_ MA3 DDR_B_ MA4 DDR_B_ MA5 DDR_B_ MA6 DDR_B_ MA7

DDR_B_ MA8 DDR_B_ MA9 DDR_B_ MA10 DDR_B_ MA11 DDR_B_ MA12 DDR_B_ MA13 DDR_B_ BG1 DDR_B_ ACT#

DDR_B_ PAR DDR_B_ ALERT#

DDR_B_ DQS#0 DDR_B_ DQS#1 DDR_B_ DQS#2 DDR_B_ DQS#3 DDR_B_ DQS#4 DDR_B_ DQS#5 DDR_B_ DQS#6 DDR_B_ DQS#7

DDR_B_ DQS0 DDR_B_ DQS1 DDR_B_ DQS2 DDR_B_ DQS3 DDR_B_ DQS4 DDR_B_ DQS5 DDR_B_ DQS6 DDR_B_ DQS7

TC21 TP@ TC23 TP@

DDR_B_ CLK0 15 DDR_B_ CLK#0 15 DDR_B_ CLK1 15 DDR_B_ CLK#1 15

DDR_B_ CKE0 15 DDR_B_ CKE1 15

DDR_B_ CS#0 15 DDR_B_ CS#1 15

DDR_B_ ODT0 15 DDR_B_ ODT1 15

DDR_B_ MA16_RAS# 15 DDR_B_ MA14_WE # 15 DDR_B_ MA15_CAS# 15

DDR_B_ BA0 15 DDR_B_ BA1 15 DDR_B_ BG0 15

DDR_B_ MA0 15 DDR_B_ MA1 15 DDR_B_ MA2 15 DDR_B_ MA3 15 DDR_B_ MA4 15 DDR_B_ MA5 15 DDR_B_ MA6 15 DDR_B_ MA7 15

DDR_B_ MA8 15 DDR_B_ MA9 15 DDR_B_ MA10 1 5 DDR_B_ MA11 1 5 DDR_B_ MA12 1 5 DDR_B_ MA13 1 5 DDR_B_ BG1 15 DDR_B_ ACT# 15

DDR_B_ PAR 15 DDR_B_ ALERT# 15

DDR_B_ DQS#0 15 DDR_B_ DQS#1 15 DDR_B_ DQS#2 15 DDR_B_ DQS#3 15 DDR_B_ DQS#4 15 DDR_B_ DQS#5 15 DDR_B_ DQS#6 15 DDR_B_ DQS#7 15

DDR_B_ DQS0 15 DDR_B_ DQS1 15 DDR_B_ DQS2 15 DDR_B_ DQS3 15 DDR_B_ DQS4 15 DDR_B_ DQS5 15 DDR_B_ DQS6 15 DDR_B_ DQS7 15

For ECC DIMM

1 2

RC3 1 21_0402_1%

1 2

RC4 75_040 2_1%

1 2

RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil Max Trace Length: 500 mil

4 4

A

B

SM_RCO MP0 SM_RCO MP1 SM_RCO MP2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_B GA1440

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2OF13

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

2016/01 /06 2017/01 /06

C

+V_DDR _REFA_R

BN13 BP13

+V_DDR _REFB_R

BR13

Compal Secret Data

Deciphered Date

TC111TP@

+V_DDR _REFA_R

+V_DDR _REFB_R

D

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(3/8)DIMMB

LA-F611P

8 7 8Thursday, March 22, 2018

E

0.3

A

Main Func = CPU

B

C

D

E

1 1

PEG_CT X_C_GRX_P[0 ..7]48

PEG_CT X_C_GRX_N[0 ..7]48

PEG_CR X_GTX_P[0..7]48

PEG_CR X_GTX_N[0..7]48

2 2

+VCCIO

3 3

)URP3&+7R3&+

PEG_CT X_C_GRX_P[0 ..7]

PEG_CT X_C_GRX_N[0 ..7]

PEG_CR X_GTX_P[0..7]

PEG_CR X_GTX_N[0..7]

1 2

RC9 24.9_04 02_1%

DMI_CRX_ PTX_P019 DMI_CRX_ PTX_N019

DMI_CRX_ PTX_P119 DMI_CRX_ PTX_N119

DMI_CRX_ PTX_P219 DMI_CRX_ PTX_N219

DMI_CRX_ PTX_P319 DMI_CRX_ PTX_N319

PEG_CR X_GTX_P7 PEG_CR X_GTX_N7

PEG_CR X_GTX_P6 PEG_CR X_GTX_N6

PEG_CR X_GTX_P5 PEG_CR X_GTX_N5

PEG_CR X_GTX_P4 PEG_CR X_GTX_N4

PEG_CR X_GTX_P3 PEG_CR X_GTX_N3

PEG_CR X_GTX_P2 PEG_CR X_GTX_N2

PEG_CR X_GTX_P1 PEG_CR X_GTX_N1

PEG_CR X_GTX_P0 PEG_CR X_GTX_N0

PEG_RC OMP

Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil

DMI_CRX_ PTX_P0 DMI_CRX_ PTX_N0

DMI_CRX_ PTX_P1 DMI_CRX_ PTX_N1

DMI_CRX_ PTX_P2 DMI_CRX_ PTX_N2

DMI_CRX_ PTX_P3 DMI_CRX_ PTX_N3

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18 F18

D17 E17

F16 E16

D15 E15

F14 E14

D13 E13

F12 E12

D11 E11

F10 E10

G2

D8 E8

E6 F6

D5 E5

J8 J9

PEG_RCOMP

CFL_H_SOC

UC1C

PEG_RXP_0 PEG_RXN_0

PEG_RXP_1 PEG_RXN_1

PEG_RXP_2 PEG_RXN_2

PEG_RXP_3 PEG_RXN_3

PEG_RXP_4 PEG_RXN_4

PEG_RXP_5 PEG_RXN_5

PEG_RXP_6 PEG_RXN_6

PEG_RXP_7 PEG_RXN_7

PEG_RXP_8 PEG_RXN_8

PEG_RXP_9 PEG_RXN_9

PEG_RXP_10 PEG_RXN_10

PEG_RXP_11 PEG_RXN_11

PEG_RXP_12 PEG_RXN_12

PEG_RXP_13 PEG_RXN_13

PEG_RXP_14 PEG_RXN_14

PEG_RXP_15 PEG_RXN_15

PEG_RCOMP

DMI_RXP_0 DMI_RXN_0

DMI_RXP_1 DMI_RXN_1

DMI_RXP_2 DMI_RXN_2

DMI_RXP_3 DMI_RXN_3

CFL-H_B GA1440

@

PEG_TXP_10 PEG_TXN_10

PEG_TXP_11 PEG_TXN_11

PEG_TXP_12 PEG_TXN_12

PEG_TXP_13 PEG_TXN_13

PEG_TXP_14 PEG_TXN_14

PEG_TXP_15 PEG_TXN_15

3OF13

PEG_TXP_0 PEG_TXN_0

PEG_TXP_1 PEG_TXN_1

PEG_TXP_2 PEG_TXN_2

PEG_TXP_3 PEG_TXN_3

PEG_TXP_4 PEG_TXN_4

PEG_TXP_5 PEG_TXN_5

PEG_TXP_6 PEG_TXN_6

PEG_TXP_7 PEG_TXN_7

PEG_TXP_8 PEG_TXN_8

PEG_TXP_9 PEG_TXN_9

DMI_TXP_0 DMI_TXN_0

DMI_TXP_1 DMI_TXN_1

DMI_TXP_2 DMI_TXN_2

DMI_TXP_3 DMI_TXN_3

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

PEG_CT X_GRX_P7

A17

PEG_CT X_GRX_N7

B17

PEG_CT X_GRX_P6

C16

PEG_CT X_GRX_N6 PEG_CT X_C_GRX_N6

B16

PEG_CT X_GRX_P5

A15

PEG_CT X_GRX_N5 PEG_CT X_C_GRX_N5

B15

PEG_CT X_GRX_P4 PEG_ CTX_C_GRX_ P4

C14

PEG_CT X_GRX_N4

B14

PEG_CT X_GRX_P3

A13

PEG_CT X_GRX_N3

B13

PEG_CT X_GRX_P2

C12

PEG_CT X_GRX_N2 PEG_CT X_C_GRX_N2

B12

PEG_CT X_GRX_P1

A11

PEG_CT X_GRX_N1

B11

PEG_CT X_GRX_P0

C10

PEG_CT X_GRX_N0 PEG_CT X_C_GRX_N0

B10

B8 A8

C6 B6

B5 A5

D4 B4

DMI_CTX_ PRX_P0 DMI_CTX_ PRX_N0

DMI_CTX_ PRX_P1 DMI_CTX_ PRX_N1

DMI_CTX_ PRX_P2 DMI_CTX_ PRX_N2

DMI_CTX_ PRX_P3 DMI_CTX_ PRX_N3

1 2

CC15 0.22U_0 201_6.3V6M

1 2

CC16 0.22U_0 201_6.3V6M

1 2

CC13 0.22U_0 201_6.3V6M

1 2

CC14 0.22U_0 201_6.3V6M

1 2

CC11 0.22U_0 201_6.3V6M

1 2

CC12 0.22U_0 201_6.3V6M

1 2

CC9 0.22U_0 201_6.3V6M

1 2

CC10 0.22U_0 201_6.3V6M

1 2

CC7 0.22U_0 201_6.3V6M

1 2

CC8 0.22U_0 201_6.3V6M

1 2

CC5 0.22U_0 201_6.3V6M

1 2

CC6 0.22U_0 201_6.3V6M

1 2

CC3 0.22U_0 201_6.3V6M

1 2

CC4 0.22U_0 201_6.3V6M

1 2

CC1 0.22U_0 201_6.3V6M

1 2

CC2 0.22U_0 201_6.3V6M

DMI_CTX_ PRX_P0 19 DMI_CTX_ PRX_N0 19

DMI_CTX_ PRX_P1 19 DMI_CTX_ PRX_N1 19

DMI_CTX_ PRX_P2 19 DMI_CTX_ PRX_N2 19

DMI_CTX_ PRX_P3 19 DMI_CTX_ PRX_N3 19

PEG_CT X_C_GRX_P7 PEG_CT X_C_GRX_N7

PEG_CT X_C_GRX_P6

PEG_CT X_C_GRX_P5

PEG_CT X_C_GRX_N4

PEG_CT X_C_GRX_P3 PEG_CT X_C_GRX_N3

PEG_CT X_C_GRX_P2

PEG_CT X_C_GRX_P1 PEG_CT X_C_GRX_N1

PEG_CT X_C_GRX_P0

Trace width=15 mils Spacing=15 mils Max length= 600 mils

4 4

Security Classification

2016/01 /06 2017/01 /06

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(4/8)PEG

LA-F611P

0.3

9 7 8Thursday, March 22, 2018

E

A

Main Func = CPU

1 1

VR_SVID_ ALERT#67 VR_SVID_ CLK67 VR_SVID_ DATA67 H_PROC HOT#26,59,61 ,67

H_VCCS T_PWRGD18

H_CPUP WRGD18 H_PLTR ST_CPU#16 H_PM_S YNC_R16

H_PM_D OWN16

PECI_EC16,26

H_THER MTRIP#16

PROC_D ETECT#16

2 2

+VCCST

H_VCCS T_PWRGD

H_THER MTRIP#

XDP_PR EQ#

CATERR #

VR_SVID_ DATA

VR_SVID_ ALERT#

1 2

1 2 1 2 1 2

12 12

RC20 1K_040 2_5% RC46 1K_040 2_5%

RC259 51_040 2_5%@

RC263 49.9_04 02_1%@ RC260 100_04 02_1% RC261 56.2_04 02_1%

+VCCSTG

3 3

1 2

RC262 1K_040 2_5%

H_PROC HOT#

VR_SVID_ ALERT# VR_SVID_ ALERT#_R

VR_SVID_ DATA H_PROC HOT#

PROC_D ETECT#

B

PCH_CP U_BCLK_P17 PCH_CP U_BCLK_N17

PCH_CP U_PCIBCLK_P17 PCH_CP U_PCIBCLK_N17

CPU_24 MHZ_P17 CPU_24 MHZ_N17

1 2

RC267 220_04 02_5%

1 2

RC268 499_04 02_1%

1 2

RC269 60.4_ 0402_1%

1 2

RC22 20_040 2_5%

1 2

RC44 0_0201 _5%

1 2

RC45 0_0201 _5%

1 2

RC277 0_04 02_5%@

< VDDQ_VTT_EN >

SM_PG_ CTRL63

+3VS

C

CFL_H_SOC

UC1E

PCH_CP U_BCLK_P PCH_CP U_BCLK_N

PCH_CP U_PCIBCLK_P PCH_CP U_PCIBCLK_N

CPU_24 MHZ_P CPU_24 MHZ_N

DDR_VT T_PG_CTRL

< OUT >

VCCST_ PWRGD_C PUH_VCCS T_PWRGD

H_CPUP WRGD H_PLTR ST_CPU# H_PM_S YNC_R H_PM_D OWN_RH_PM_D OWN PECI_EC_ RPECI_EC H_THER MTRIP#_CH_THER MTRIP#

TC97TP@

TC96TP@

TC94TP@ TC95TP@

PROC_S ELECT#

CATERR #

H_PROC HOT#_R

D35 C36

D31

BH31 BH32 BH29 BR30

BT13

BT31 BP35 BM34 BP31

BT34

BR33

BN1

BM30

AT13

AW13

AU13 AY13

B31 A32

E31

H13

J31

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

ZVM# MSM#

RSVD1 RSVD2

CFL-H_B GA1440

@

5 OF13

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8

CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

CFG_17 CFG_16 CFG_19 CFG_18

BPM#_0 BPM#_1 BPM#_2 BPM#_3

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

+1.2V_DDR

12

CH197 0.1U _0402_10V7 K

1 2

RC270 3 30K_0402_5%

SA00007WE00 (S IC 74AUP1G07SE-7 SOT353 5P LOW PW BUFF) _DIODES SA00005U600 (S IC 74AUP1G07GW TSSOP 5P BUFFER) _NXP

UC10

5

4

74AUP1 G07GW_T SSOP5

MAIN@

VCC

Y

NC

GND

1

2

A

3

BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

BR27 BT27 BM31 BT30

BT28 BL32 BP28 BR28

BP30 BL30 BP27

BT25

< IN >

DDR_VT T_PG_CTRL

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG17 CFG16 CFG19 CFG18

XDP_BP M#0 XDP_BP M#1 XDP_BP M#2 XDP_BP M#3

CPU_XD P_TDO CPU_XD P_TDI CPU_XD P_TMS CPU_XD P_TCK0

CPU_XD P_TRST# XDP_PR EQ# XDP_PR DY#

CFG_RC OMP

Trace Width/Space: 4 mil/ 12 mil Max Trace Length: 600 mil

TC98 TP@ TC99 TP@ TC101TP@ TC100TP@

12

RC19

49.9_04 02_1%

D

CFG0 38 CFG1 38 CFG2 38 CFG3 38 CFG4 38 CFG5 38 CFG6 38 CFG7 38 CFG8 38

CFG9 38 CFG10 38 CFG11 38 CFG12 38 CFG13 38 CFG14 38 CFG15 38

CFG17 38 CFG16 38 CFG19 38 CFG18 38

CPU_XD P_TDO 18 ,38 CPU_XDP_TDI 18,38 CPU_XDP_TMS 18,38 CPU_XDP_TCK 0 18,3 8

CPU_XDP_TRS T# 22,38 XDP_PREQ# 22 ,38 XDP_PR DY# 22,38

The CFG signals have a default valu e of '1' if not terminated on the board.

E

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

*1 = (Default) Normal Operation; 0 = Stall.

CFG[2]: PCI Express* Static x16 Lan e Numbering Reversal.

1 = Normal operation *0 = Lane numbers reversed.

CFG[4]: eDP enable:

1 = Disabled. *0 = Enabled.

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express* 01 = reserved *10 = 2 x8 PCI Express* 11 = 1 x16 PCI Express*

CFG[7]: PEG Training:

*1 = (default) PEG Train immediatel y following RESET# de assertion. 0 = PEG Wait for BIOS for training .

To be confirm

CFG0

CFG2 CFG4

CFG5 CFG6 CFG7

1 2

RC255 1K_0 402_5%@

1 2

RC258 1K_0 402_5%

1 2

RC257 1K_0 402_5%

1 2

RC256 1K_0 402_5%

1 2

RC253 1K_0 402_5%@

1 2

RC254 1K_0 402_5%@

Reserve for ESD

H_VCCS T_PWRGD

H_PROC HOT#_R

4 4

A

CH210

CH211

1 2

100P_0 402_50V8J@ESD@

1 2

100P_0 402_50V8J

Security Classification

2016/01 /06 2017/01 /06

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(5/8)CFG

LA-F611P

0.3

10 78T hursday, March 22, 201 8

E

A

Main Func = CPU

+VCCGT +VCCGT

AT14

A

AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35

AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32

BC35

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BP37

BP38

BR15

BR16

BR17

1 1

2 2

3 3

4 4

CFL_H_SOC

UC1K

VCCGT1 VCCGT2 VCCGT3 VCCGT4 VCCGT5 VCCGT6 VCCGT7 VCCGT8 VCCGT9 VCCGT10 VCCGT11 VCCGT12 VCCGT13 VCCGT14 VCCGT15 VCCGT16 VCCGT17 VCCGT18 VCCGT19 VCCGT20 VCCGT21 VCCGT22 VCCGT23 VCCGT24 VCCGT25 VCCGT26 VCCGT27 VCCGT28 VCCGT29 VCCGT30 VCCGT31 VCCGT32 VCCGT33 VCCGT34 VCCGT35 VCCGT36 VCCGT37 VCCGT38 VCCGT39 VCCGT40 VCCGT41 VCCGT42 VCCGT43 VCCGT44 VCCGT45 VCCGT46 VCCGT47 VCCGT48 VCCGT49 VCCGT50 VCCGT51 VCCGT52 VCCGT53 VCCGT54 VCCGT55 VCCGT56 VCCGT57 VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT62 VCCGT63 VCCGT64 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT159 VCCGT160 VCCGT161 VCCGT162 VCCGT163

11OF13

CFL-H_B GA1440

VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT95 VCCGT96 VCCGT97 VCCGT98

VCCGT99 VCCGT100 VCCGT101 VCCGT102 VCCGT103 VCCGT104 VCCGT105 VCCGT106 VCCGT107 VCCGT108 VCCGT109 VCCGT110 VCCGT111 VCCGT112 VCCGT113 VCCGT114 VCCGT115 VCCGT116 VCCGT117 VCCGT118 VCCGT119 VCCGT120 VCCGT121 VCCGT122 VCCGT123 VCCGT124 VCCGT125 VCCGT126 VCCGT127 VCCGT128 VCCGT129 VCCGT130 VCCGT131 VCCGT132 VCCGT133 VCCGT134 VCCGT135 VCCGT136 VCCGT137 VCCGT138 VCCGT139 VCCGT140 VCCGT141 VCCGT142 VCCGT143 VCCGT144 VCCGT145 VCCGT146 VCCGT147 VCCGT148 VCCGT149 VCCGT150 VCCGT151 VCCGT152 VCCGT153 VCCGT154 VCCGT155 VCCGT156 VCCGT157 VCCGT158 VCCGT164 VCCGT165 VCCGT166 VCCGT167 VCCGT168

VSSGT_SENSE

VCCGT_SENSE

BD35 BD36 BE31 BE32 BE33 BE34 BE35 BE36 BE37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ16 BJ17 BJ19 BJ20 BJ21 BJ23 BJ24 BJ26 BJ27 BJ37 BJ38 BK16 BK17 BK19 BK20 BK21 BK23 BK24 BK26 BK27 BL15 BL16 BL17 BL23 BL24 BL25 BL26 BL27 BL28 BL36 BL37 BM15 BM16 BM17 BM36 BM37 BN15 BN16 BN17 BN36 BN37 BN38 BP15 BP16 BP17 BR37 BT15 BT16 BT17 BT37

AH37 AH38

VSSGT_ SENSE VCCGT_ SENSE

B

C

+VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE

UC1I

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF29 AF30 AF31 AF32 AF33 AF34 AF35 AF36 AF37

AF38 AG14 AG31 AG32 AG33 AG34 AG35 AG36

CFL-H_B GA1440

+VCCGT

RC12 100_04 02_1%

VCCGT_ SENSE VSSGT_ SENSE

1 2

12

RC13 100_04 02_1%

VCCGT_ SENSE 67

1. VccGT_ SENSE / Vss GT_SENSE Tr ace Length Match < 25 mils

2. Mai ntain 25- mil separ ation dist ance away from any other dynamic signals.

3. RC1, RC2 should be pla ced within 2 inch es (50.8 mm) of CP U

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

CFL_H_SOC

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63

9OF13

VSSGT_ SENSE 67

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE VSS_SENSE

AG37 AG38

Compal Secret Data

2016/01 /06 2017/01 /06

C

Compal Secret Data

VCC_SE NSE VSS_SE NSE

Deciphered Date

+VCC_CORE

RC10 100_04 02_1%

1 2

12

RC11 100_04 02_1%

1. Vcc_S ENSE/ Vss_ SENSE Trace Length M atch < 25 mils

2. Mai ntain 25- mil separ ation dist ance away from any other dynamic signals.

3. RC1, RC2 should be pla ced within 2 inch es (50.8 mm) of CP U

D

VCC_SE NSE 67

VSS_SE NSE 67

LA-F611PR01_0531C.DSN VCCSENSE change to VCC_SENSE VSSSENSE change to VSS_SENSE

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

E

UC1J

K14

L13

L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38

T29

T30

T31

T32

T35

T36

T37

T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 V32 V33 V34 V35 V36 V37 V38

W13 W14 W29 W30 W31 W32

CFL-H_B GA1440

CFL-H(6/8)VCC_CORE/GT

LA-F611P

CFL_H_SOC

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62

10OF13

VCC63

Compal Electronics, Inc.

VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75

E

W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36

0.3

11 78T hursday, March 22, 201 8

A

B

C

D

E

Main Func = CPU

570805_CFL_EDS_Vol1_Rev0.5

+VCCSA

UC1L

J30

11.1A

K29 K30 K31 K32

1 1

570805_CFL_EDS_Vol1_Rev0.5 +VCC_IO Max: 6400mA

2 2

+VCCIO

+0.95VS_VCCIO

K33 K34 K35 L31 L32 L35 L36 L37

L38 M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21

H15

H16

H17

H19

H20

H21

H26

H27

J15 J16 J17 J19 J20 J21 J26 J27

CFL-H_B GA1440

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16 VCCSA17 VCCSA18 VCCSA19 VCCSA20 VCCSA21 VCCSA22

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21

CFL_H_SOC

12OF13

VCCPLL_OC1 VCCPLL_OC2 VCCPLL_OC3

VCCSTG2

VCCSTG1

VCCPLL1 VCCPLL2

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

+1.2V_DDR +1.2V_DDR

AA6

VDDQ1

AE12

VDDQ2

AF5

VDDQ3

AF6

VDDQ4

AG5

VDDQ5

AG9

VDDQ6

AJ12

VDDQ7

AL11

VDDQ8

AP6

VDDQ9

AP7

VDDQ10

AR12

VDDQ11

AR6

VDDQ12

AT12

VDDQ13

AW6

VDDQ14

AY6

VDDQ15

J5

VDDQ16

J6

VDDQ17

K12

VDDQ18

K6

VDDQ19

L12

VDDQ20

L6

VDDQ21

R6

VDDQ22

T6

VDDQ23

W6

VDDQ24

Y12

VDDQ25

BH13 BJ13 G11

H30

VCCST

H29

G30

H28 J28

M38 M37

H14 J14

+1.2V_VDDQ_CPU Max: 3300mA

570805_CFL_EDS_Vol1_Rev0.5 +1.2V_VCCPLL_OC Max: 130mA

+1.2V_VCCPLL_OC

1 2

RC14 0_0805 _5%@

+VCCST

Max: 60mA

Max: 20mA

+VCCSTG

+VCCST

Max: 150mA

1 2

RC15 100_04 02_1%

1 2

RC275 0_04 02_5%

1 2

RC276 0_04 02_5%

1 2

RC16 100_04 02_1%

+1.2V_DDR

+VCCSA

VCC_SA _SENSE VSS_SA _SENSE

10U_0402_6.3V6M

1

2

CC18

CC17

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

+VCCIO

10U_0402_6.3V6M

1

CC33

CC34

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +0.95VS_VCCIO: 10uF * 12 22uF * 4

VCC_SA _SENSE 67 VSS_SA _SENSE 67

1. VccGT_ SENSE / Vss GT_SENSE Tr ace Length Match < 25 mils

2. Mai ntain 25- mil separ ation dist ance away from any other dynamic signals.

3. RC1, RC2 should be pla ced within 2 inch es (50.8 mm) of CP U

10U_0402_6.3V6M

1

CC19

2

10U_0402_6.3V6M

1

CC20

CC21

CC22

2

+1.2V_VCCPLL_OC

10U_0402_6.3V6M

1

CC35

2

1

2

10U_0402_6.3V6M

1

CC23

2

1U_0201_6.3V6M

1

CC36

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.2V_VCCPLL_OC: 1uF * 2

10U_0402_6.3V6M

1

CC24

CC25

2

1U_0201_6.3V6M

CC37

10U_0402_6.3V6M

1

2

1

CC27

CC26

2

+VCCSTG +VCCSA

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05VS_VCCSTG: 1uF * 1

10U_0402_6.3V6M

CC28

1

2

22U_0603_6.3V6M

1

CC29

CC30

2

1U_0201_6.3V6M

CC40

22U_0603_6.3V6M

1

2

CC32

CC31

2

1U_0402_6.3V6K

1

CC303

2

+VCCST+VCCST

+VCCIO

1 2

3 3

4 4

A

RC271 100_ 0402_1%

1 2

RC272 0_04 02_5%

1 2

RC273 0_04 02_5%

1 2

RC274 100_ 0402_1%

B

VCCIO_SE NSE VSSIO_SE NSE

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

VCCIO_SE NSE 64 VSSIO_SE NSE 64

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05V_VCCST: 1uF * 1

2016/01 /06 2017/01 /06

C

1U_0201_6.3V6M

1

CC38

2

Compal Secret Data

Deciphered Date

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05V_VCCSFR: 1uF * 1

1U_0201_6.3V6M

1

CC39

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(7/8)VCCSA/VCCIO/VDDQ

LA-F611P

12 78T hursday, March 22, 201 8

E

0.3

A

Main Func = CPU

AW5 AY12 AY33 AY34

BA10 BA11 BA12 BA37 BA38

BA6 BA7 BA8 BA9 BB1

BB12

BB2

BB29

BB3

BB30

BB4 BB5

BB6 BC12 BC13 BC14 BC33 BC34

BC6 BD10 BD11 BD12 BD37

BD6

BD7

BD8

BD9

BE1

BE2 BE29

BE3 BE30

BE4

BE5

BE6 BF12 BF33 BF34

BF6 BG12 BG13 BG14 BG37 BG38

BG6

BH1 BH10 BH11 BH12 BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33 T34

U37

U38

BJ12 BJ14

B9

T2 T3

T4 T5 T7 T8 T9

CFL_H_SOC

UC1G

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CFL-H_B GA1440

CFL_H_SOC

UC1F

A10

VSS

A12

VSS

A16

VSS

A18

VSS

A20

VSS

A22

VSS

A24

VSS

A26

VSS

1 1

2 2

3 3

A28 A30

AA12 AA29 AA30 AB33 AB34

AB6 AC1

AC12

AC2

AC3 AC37 AC38

AC4

AC5

AC6 AD10 AD11 AD12 AD29 AD30

AD6

AD8

AD9 AE33 AE34

AE6

AF1 AF12 AF13 AF14

AF2

AF3

AF4 AG10 AG11 AG13 AG29 AG30

AG6 AG7

AG8 AH12 AH33 AH34 AH35 AH36

AH6

AJ1

AJ13

AJ2

AJ3 AJ37 AJ38

AJ4

AJ5

AJ6

W4

W5 Y10 Y11 Y13 Y14 Y37 Y38

AK29 AK30

A6 A9

Y7 Y8 Y9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6OF13

VSS

CFL-H_B GA1440

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK4 AL10 AL12 AL14 AL33 AL34 AL4 AL7 AL8 AL9 AM1 AM12 AM2 AM3 AM37 AM38 AM4 AM5 AN12 AN29 AN30 AN5 AN6 AP10 AP11 AP12 AP33 AP34 AP8 AP9 AR1 AR13 AR14 AR2 AR29 AR3 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR4 AR5 AT29 AT30 AT6 AU10 AU11 AU12 AU33 AU34 AU6 AU7 AU8 AU9 AV37 AV38 AW1 AW12 AW2 AW29 AW3 AW30 AW4 U6 V12 V29 V30 A14 AD7 V6 W1 W12 W2 W3 W33 W34

7OF13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B

CFL_H_SOC

UC1H

BN4 BJ15 BJ18 BJ22 BJ25 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BK13 BK14 BK15 BK18 BK22 BK25 BK29 BK6 BL13 BL14 BL18 BL19 BL20 BL21 BL22 BL29 BL33 BL35 BL38 BL6 BM11 BM12 BM13 BM14 BM18 BM2 BM21 BM22 BM23 BM24 BM25 BM26 BM27 BM28 BM29 BM3 BM33 BM35 BM38 BM5 BM6 BM7 BM8 BM9 BN12 BN14 BN18 BN19 BN2 BN20 BN21 BN24 BN29 BN30 BN31 BN34 P38 P6 R12 R29 AY14 BD38 R30 T1 T10 T11 T12 T13 T14

BN7

BP12 BP14 BP18 BP21 BP24 BP25 BP26 BP29 BP33 BP34

BP7

BR12 BR14 BR18 BR21 BR24 BR25 BR26 BR29 BR34 BR36

BR7

BT12 BT14 BT18 BT21 BT24 BT26 BT29 BT32

BT5

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C37

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D33

N33

N34

M14

E34 E35 E38

P12 P37

F11 F13

C5 C8 C9

D3

D6 D9

E4 E9 N3

N4 N5 N6 N7 N8 N9

M6

N1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CFL-H_B GA1440

8OF13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F15 F17 F19 F2 F21 F23 F25 F27 F29 F3 F31 F36 F4 F5 F8 F9 G10 G12 G14 G16 G18 G20 G22 G23 G24 G26 G28 G4 G5 G6 G8 G9 H11 H12 H18 H22 H25 H32 H35 J10 J18 J22 J25 J32 J33 J36 J4 J7 K1 K10 K11 K2 K3 K38 K4 K5 K7 K8 K9 L29 L30 L33 L34 M12 M13 N10 N11 N12 N2 BT8 BR9

A3 A34 A4 B3 B37 BR38 BT3 BT35 BT36 BT4 C2 D38

C

1 2

RC6 0_0201 _5%

1 2

RC7 0_0201 _5%

PCH_TR IGOUT_R22 CPU_TR IGOUT_R22

1 2

RC8 30_040 2_5%

D

TC25T P@

TC26T P@ TC24T P@

TC27T P@ TC29T P@

TC31T P@

TC32T P@ TC33T P@ TC34T P@ TC35T P@

TC36T P@ TC37T P@ TC38T P@ TC39T P@ TC40T P@ TC41T P@

PCH_TR IGOUT_R CPU_TR IGOUT

TC42T P@

TC43T P@

TC44T P@ TC46T P@

TC49T P@ TC50T P@

TC54T P@ TC56T P@ TC58T P@

BR1

BT2

BN35

H24

BN33

BL34

N29

R14 AE29 AA14 AP29 AP14

A36

A37

H23

F30

E30

B30

C30

BR35 BR31 BH30

E2 E3 E1 D1

J24

J23

G3

J3

UC1M

RSVD_TP5 IST_TRIG RSVD_TP4 RSVD_TP3

RSVD_TP1 RSVD_TP2

RSVD15

RSVD28 RSVD27 RSVD14 RSVD13

RSVD30 RSVD31 RSVD2 RSVD1 RSVD5 RSVD4 VSS_A36

VSS_A37

PROC_TRIGIN PROC_TRIGOUT

RSVD24

RSVD23

RSVD7 RSVD21

RSVD26 RSVD29

RSVD19 RSVD18 RSVD9

CFL-H_B GA1440

CFL_H_SOC

13OF13

RSVD11 RSVD10

RSVD12

RSVD3

RSVD25

RSVD22 RSVD20 RSVD17 RSVD16

RSVD8 RSVD6

E

BK28 BJ28

BL31 AJ8 G13

C38 C1 BR2 BP1 B38 B2

TC28 TP@ TC30 TP@

TC45 TP@ TC47 TP@ TC48 TP@

TC51 TP@ TC52 TP@ TC53 TP@ TC55 TP@ TC57 TP@ TC59 TP@

4 4

Security Classification

2016/01 /06 2017/01 /06

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2016/01 /06 2017/01 /06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

CFL-H(8/8)GND/RSVD

LA-F611P

E

0.3

13 78T hursday, March 22, 201 8

5

4

3

2

1

Main Func = DDR

DDR_A_D[0..63]7 DDR_A_MA[0..13]7 DDR_A_DQS#[0..7]7

Layout Note: Place near JDIMM1.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM1

10U_0603_6.3V6M~D

1

CD1

2

1U_0402_6.3V6K~D

CD3

1

CD2

2

CD4

1

2

Layout Note: Place near JDIMM1.258

+0.6V_DDR_VTT

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD5

1

2

10U_0603_6.3V6M~D

CD6

1

2

1U_0402_6.3V6K~D

CD7

1U_0402_6.3V6K~D

CD60

CD61

1

2

DDR_A_DQS[0..7]7

Layout Note: Place near JDIMM1.255

+3VS

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

CD10

CD9

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD11

1

2

C C

CD13

CD12

1

2

CD15

CD14

1

2

1U_0402_6.3V6K~D

+1.2V_DDR

10U_0603_6.3V6M~D

1

CD19

2

10U_0603_6.3V6M~D

1

CD20

CD21

2

10U_0603_6.3V6M~D

1

CD23

CD22

2

1U_0402_6.3V6K~D

CD16

1

2

10U_0603_6.3V6M~D

1

CD24

2

1U_0402_6.3V6K~D

CD17

CD18

1

2

DDR_A_CKE07

DDR_A_BG17 DDR_A_BG07

10U_0603_6.3V6M~D

1

CD25

2

1

+

CD27

CD26

330U_D2_2V_Y

MAIN@

2

DDR_A_CLK07 DDR_A_CLK#07

DDR_A_PAR7 DDR_A_BA17

DDR_A_CS#07 DDR_A_MA14_WE#7

DDR_A_ODT07 DDR_A_CS#17

DDR_A_ODT17

+1.2V_DDR

B B

+3VS

12

@

12

+V_DDR_REFA_R

RD1 0_0402_5%

RD4 0_0402_5%

20mil

RD9 2_0402_1%

A A

1

CD30

0.022U_0402_25V7K

2

12

RD11

24.9_0402_1%

5

+3VS +3VS

12

@

12

1 2

RD2 0_0402_5%

RD5 0_0402_5%

+1.2V_DDR

12

RD10

1K_0402_1%~D

+V_DDR_REFA

RD12

1K_0402_1%~D

12

RD3

@

0_0402_5%

DDR_DRAMRST#DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2

12

RD6 0_0402_5%

1

@

2

CD29

0.1U_0402_16V7K~D

RD8 0_0402_5%

12

RD7 470_0402_1%

12

+1.2V_DDR

H_DRAMRST# 18

+1.2V_DDR

+3VS

4

PCH_SMBCLK15,18,32

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.2V_DDR

DDR_A_D1

DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D9

DDR_A_D8

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23

DDR_A_D18

DDR_A_D24

DDR_A_D29

DDR_A_D31 DDR_A_D26

DDR_A_D30

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR DDR_A_BA1

DDR_A_CS#0 DDR_A_MA14_WE#

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

TP41

DDR_A_D36

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D39

DDR_A_D34

DDR_A_D41

DDR_A_D40

DDR_A_D43

DDR_A_D42

DDR_A_D48

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D55

DDR_A_D53

DDR_A_D59

DDR_A_D56

DDR_A_D60

DDR_A_D61

PCH_SMBCLK

Issued Date

JDIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DB I_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DB I3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n /A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_ n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DB I5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DB I7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0206-P001A02~D

DEREN_40-42271-26001RHF

CONN@

2016/01/06 2017/01/06

SP07001CY0L

VSS2

DQ4

VSS4

DQ0

VSS6

DM0_n/DB I0_n

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DB I2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DB I_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

EVENT_n/ NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

RAS_n/A 16

VDD16

CAS_n/A 15

A13

VDD18

C0/CS2_ n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DB I4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DB I6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0 VTT SA1

GND2

Compal Secre t Data

Deciphered Date

2

+1.2V_DDR

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_A_D0

DDR_A_D4

DDR_A_D6

DDR_A_D2

DDR_A_D12

DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_D19

DDR_A_D22

DDR_A_D28

DDR_A_D25

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D27

DDR_DRAMRST# DDR_A_CKE1

DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2

DDR_A_CLK1 DDR_A_CLK#1

DDR_A_MA0 DDR_A_MA10

DDR_A_BA0 DDR_A_MA16_RAS#

DDR_A_MA15_CAS# DDR_A_MA13

DIMM_CHA_SA2

DDR_A_D33

DDR_A_D32

DDR_A_D38

DDR_A_D35

DDR_A_D45

DDR_A_D44

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D47

DDR_A_D46

DDR_A_D50

DDR_A_D49

DDR_A_D54

DDR_A_D51

DDR_A_D58

DDR_A_D57

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62

DDR_A_D63

PCH_SMBDATA DIMM_CHA_SA0

DIMM_CHA_SA1

DDR_DRAMRST# 15 DDR_A_CKE1 7

DDR_A_ACT# 7 DDR_A_ALERT# 7

12

RD23

240_0402_1%

TP40

+1.2V_DDR

DDR_A_CLK1 7 DDR_A_CLK#1 7

DDR_A_BA0 7 DDR_A_MA16_RAS# 7

DDR_A_MA15_CAS# 7

0.1U_0402_16V7K~D

CD28

1

2

All VREF traces should have 10 mil tra ce width

+V_DDR_REFA

+1.2V_DDR

PCH_SMBDATA 15,18,32

Title

Size Document Number Re v

Date: Sheet

+0.6V_DDR_VTT+2.5V_MEM

Compal Electronics, Inc.

DDR4 DIMMA_RVS

LA-F611P

1

0.3

of

14 78Thursday, March 22, 2018

of

14 78Thursday, March 22, 2018

of

14 78Thursday, March 22, 2018

5

4

3

2

1

Main Func = DDR

DDR_B_D[0..63]8 DDR_B_MA[0..13]8 DDR_B_DQS#[0..7]8

Layout Note: Place near JDIMM2.258

+0.6V_DDR_VTT

D D

1U_0402_6.3V6K~D

CD31

1

2

10U_0603_6.3V6M~D

CD32

1

2

10U_0603_6.3V6M~D

1

CD33

2

Layout Note: Place near JDIMM2.257,259

+2.5V_MEM

CD34

1U_0402_6.3V6K~D

CD35

1

2

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD36

1

CD37

2

1U_0402_6.3V6K~D

1

2

CD63

CD62

1

2

Layout Note: Place near JDIMM2.255

DDR_B_DQS[0..7]8

+3VS

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

CD39

CD40

1

2

Layout Note: Place near JDIMM2

1

2

+1.2V_DDR +1.2V_DDR

DDR_B_D5

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D7

DDR_B_D3

DDR_B_D14

DDR_B_D10

DDR_B_D13 DDR_B_D12

DDR_B_D18 DDR_B_D22

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D21

DDR_B_D20

DDR_B_D27

DDR_B_D25

DDR_B_D29

DDR_B_D26

+1.2V_DDR

1U_0402_6.3V6K~D

C C

1U_0402_6.3V6K~D

CD41

CD42

1

2

+1.2V_DDR

10U_0603_6.3V6M~D

1

CD49

CD50

2

B B

12

@

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2

12

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

1

2

RD13 0_0402_5%

RD16 0_0402_5%

1U_0402_6.3V6K~D

CD44

CD43

1

2

10U_0603_6.3V6M~D

1

CD51

CD52

2

1U_0402_6.3V6K~D

CD46

CD45

1

2

10U_0603_6.3V6M~D

1

CD53

CD54

2

12

RD14 0_0402_5%

12

RD17

@

0_0402_5%

1U_0402_6.3V6K~D

CD48

CD47

1

2

10U_0603_6.3V6M~D

1

CD56

CD55

2

DDR_B_CKE08

DDR_B_BG18 DDR_B_BG08

DDR_B_CLK08 DDR_B_CLK#08

DDR_B_PAR8 DDR_B_BA18

DDR_B_CS#08 DDR_B_MA14_WE#8

DDR_B_ODT08 DDR_B_CS#18

DDR_B_ODT18

+3VS+3VS+3VS

12

RD15

@

0_0402_5%

12

RD18 0_0402_5%

+1.2V_DDR

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PAR DDR_B_BA1

DDR_B_CS#0 DDR_B_MA14_WE#

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

TP42

DDR_B_D38 DDR_B_D39

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D37

DDR_B_D36

DDR_B_D44

DDR_B_D45

DDR_B_D43

DDR_B_D42

DDR_B_D51 DDR_B_D54

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D53

DDR_B_D61

DDR_B_D62

+1.2V_DDR

+V_DDR_REFB_R

A A

20mil

1 2

RD19 2_0402_1%

1

CD59

0.022U_0402_25V7K

2

12

RD22

24.9_0402_1%

5

+1.2V_DDR

12

RD20

1K_0402_1%~D

+V_DDR_REFB

RD21

1K_0402_1%~D

+3VS

+2.5V_MEM +0.6V_DDR_VTT

4

PCH_SMBCLK14,18,32

DDR_B_D60 DDR_B_D56

PCH_SMBCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DB I_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DB I3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n /A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_ n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DB I5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DB I7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0205-P001A02~D

DEREN_40-42261-26001RHF

CONN@

2016/01/06 2017/01/06

SP07001HW0L

2

VSS2

4

DQ4

6

VSS4

8

DQ0

10

VSS6

12

DM0_n/DB I0_n

14

VSS7

16

DQ6

18

VSS9

20

DQ2

22

VSS11

24

DQ12

26

VSS13

28

DQ8

30

VSS15

32

DQS1_c

34

DQS1_t

36

VSS18

38

DQ14

40

VSS20

42

DQ11

44

VSS22

46

DQ20

48

VSS24

50

DQ16

52

VSS26

54

DM2_n/DB I2_n

56

VSS27

58

DQ22

60

VSS29

62

DQ18

64

VSS31

66

DQ28

68

VSS33

70

DQ24

72

VSS35

74

DQS3_c

76

DQS3_t

78

VSS38

80

DQ31

82

VSS40

84

DQ27

86

VSS42

88

CB4/NC

90

VSS44

92

CB0/NC

94

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/ NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A 16

VDD16

CAS_n/A 15

VDD18

C0/CS2_ n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DB I4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DB I6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

Deciphered Date

96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

2

DM8_n/DB I_n/NC

Compal Secre t Data

DDR_B_D4

DDR_B_D0

DDR_B_D2

DDR_B_D6

DDR_B_D8

DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D15DDR_B_D11

DDR_B_D16DDR_B_D17

DDR_B_D23

DDR_B_D19

DDR_B_D28

DDR_B_D30

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D24

DDR_DRAMRST# DDR_B_CKE1

DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0 DDR_B_MA10

DDR_B_BA0 DDR_B_MA16_RAS#

DDR_B_MA15_CAS# DDR_B_MA13

DIMM_CHB_SA2

DDR_B_D34DDR_B_D35

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46

DDR_B_D47

DDR_B_D48DDR_B_D52

DDR_B_D49

DDR_B_D50

DDR_B_D59

DDR_B_D57

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D58DDR_B_D63

PCH_SMBDATA

DIMM_CHB_SA0

DIMM_CHB_SA1

RD24

240_0402_1%

TP43

+1.2V_DDR

DDR_DRAMRST# 14 DDR_B_CKE1 8

DDR_B_ACT# 8 DDR_B_ALERT# 8

12

PCH_SMBDATA 14,18,32

+1.2V_DDR

DDR_B_CLK1 8 DDR_B_CLK#1 8

DDR_B_BA0 8 DDR_B_MA16_RAS# 8

DDR_B_MA15_CAS# 8

+V_DDR_REFB

0.1U_0402_16V7K~D

CD58

1

2

Title

DDR4 DIMMB_STD

Size Document Number Re v

LA-F611P

Date: Sheet

All VREF traces should have 10 mil tra ce width

Compal Electronics, Inc.

15 78Thursday, March 22, 2018

1

15 78Thursday, March 22, 2018

0.3

of

Main Func = PCH

5

4

3

2

1

CLIP1 CLIP_15X3_VIUS1

EC0XQ000G00

D D

PCIE SSD M.2 SSD/ NVMe/ Optane

PCIe

LAN

C C

PCIE SSD M.2 SSD/ NVMe/ Optane

PCIe

B B

SATA HDD --->

PCIE_PTX_DRX_P1134 PCIE_PTX_DRX_N1134 PCIE_PRX_DTX_P1134 PCIE_PRX_DTX_N1134

PCIE_PTX_DRX_N1435 PCIE_PTX_DRX_P1435 PCIE_PRX_DTX_N1435 PCIE_PRX_DTX_P1435

SATA3_PTX_DRX_N032

SATA3_PTX_DRX_P032 SATA3_PRX_DTX_N032 SATA3_PRX_DTX_P032

PCIE_PTX_DRX_P1234 PCIE_PTX_DRX_N1234 PCIE_PRX_DTX_P1234 PCIE_PRX_DTX_N1234

CPU_DP1_HPD41

EDP_HPD29

PCIE_PTX_DRX_P11

PCIE_PTX_DRX_N11

PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11

PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14

PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12

PCIE_PRX_DTX_N12

RH656 0_0201_5%

1 2

SATA3_PTX_DRX_N0 SATA3_PTX_DRX_P0 SATA3_PRX_DTX_N0 SATA3_PRX_DTX_P0

CPU_DP1_HPD

EDP_HPD_R

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BGA874

UH1E

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DPPD_HPD2/DISP_MISC2

AL15

GPP_I3/DPPE_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_BGA874

CNP-H

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN

PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

CNP-H

5 OF 13

PLTRST_CPU#

PM_DOWN

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/EXT_PWR_GATE#/PS_ON#

GPP_K23/IMGCLKOUT1 GPP_K22/IMGCLKOUT0

GPP_K21 GPP_K20

GPP_H23/TIME_SYNC0

PCIE_PRX_DTX_N9

G36

PCIE_PRX_DTX_P9

F36

PCIE_PTX_DRX_N9

C34

PCIE_PTX_DRX_P9

D34

PCIE_PRX_DTX_N10

K37

PCIE_PRX_DTX_P10

J37

PCIE_PTX_DRX_N10

C35

PCIE_PTX_DRX_P10

B35

PCIE_PRX_DTX_N15

F44

PCIE_PRX_DTX_P15

E45

PCIE_PTX_DRX_N15

B40

PCIE_PTX_DRX_P15

C40

L41 M40 B41 C41

K43 K44 A42 B42

P41 R40 C42 D42

PCH_SATA_LED#

AK48

AH41

M2_SSD_DETECT

AJ43 AK47 AN47 AM46 AM43 AM47 AM48

L_BKLT_CTRL

AU48

BKLT_IN_EC

AV46

EDP_VDD_EN

AV44

AD3

PECI_PCH

AF2

H_PM_SYNC_PCH H_PM_SYNC_R

AF3

H_PLTRST_CPU#

AG5

H_PM_DOWN

AE2

AL13

CPU_DP1_CTRL_DATA

AR8 AN13 AL10 AL9 AR3 AN40 AT49

PROC_DETECT#

AP41

PROJECT_ID2

M45

PROJECT_ID1

L48 T45 T46 AJ47

PCH_SATA_LED# 30,34

M2_SSD_DETECT 34

L_BKLT_CTRL 29 BKLT_IN_EC 26 EDP_VDD_EN 29

1 2

RH79 620_0402_5%

1 2

RH73 13_0402_5%

1 2

RH13 30_0402_5%

T4942 TP@

T4943 TP@ T4941 TP@

PROC_DETECT# 10

H_THERMTRIP#H_THERMTRIP#_R

PCIE_PRX_DTX_N9 34 PCIE_PRX_DTX_P9 34

PCIE_PTX_DRX_N9 34 PCIE_PTX_DRX_P9 34

PCIE_PRX_DTX_N10 34 PCIE_PRX_DTX_P10 34

PCIE_PTX_DRX_N10 34 PCIE_PTX_DRX_P10 34

PCIE_PRX_DTX_N15 33 PCIE_PRX_DTX_P15 33 PCIE_PTX_DRX_N15 33 PCIE_PTX_DRX_P15 33

H_THERMTRIP# 10 PECI_EC 10,26 H_PM_SYNC_R 10 H_PLTRST_CPU# 10

H_PM_DOWN 10

PCIE SSD M.2 SSD/ NVMe/ Optane PCIe / SATA

WLA N

PCH_SATA_LED#

H_PM_DOWN

@

RH14 13_0402_5%

1 2

#571391_CFL_H_PDG_Rev0p5

12.2.10 PM_DOWN Topology

1 2

RH512 10K_0201_5%

+3VS

eDP_HPD pull down 100K

+3VS

12

TBT@

RH557

10K_0201_5%

12

NON_TBT@

RH681

10K_0201_5%

A A

PROJECT ID

Non-TBT TBT

5

4

NON_TPM@

RH562

10K_0201_5%

PROJECT ID1

(GPP_K22)

0 1

12

TPM@

RH561 10K_0201_5%

12

PROJECT_ID1 PROJECT_ID2

TPM ID

SW TPM HW TPM

PROJECT ID2

(GPP_K23)

0 1

PCH Strap PIN

CPU_DP1_CTRL_DATA

DDP[B..F]CTRLDATA This signal has a weak internal Pull-down. 0 = Port B is not detected. (Default) 1 = Port B is detected. Notes:

1. The internal Pull-down is disabled after PCH_PWROK de-asserts.

2. This signal is in the primary well.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

RH33

Compal Secret Data

1 2

2.2K_0402_5%

Deciphered Date

2

+3VS

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Date: Sheet o f

Compal Electronics, Inc.

PCH (1/7) SATA,DDC,PCIE

Document Number Re v

LA-F611P

1

16 78T hursday, March 22, 2018

0.3

5

4

3

2

1

Main Func = PCH

4

1

CH201

0.1U_02 01_6.3V6 K

2

4

12

PCH_RTCX1

PCH_RTCX2

1

CH46

8.2P_0 402_50V

XTAL_M@

2

XTAL24_ IN_R

XTAL24_ OUT_R

XTAL_M@

1

CH48 15P_04 02_50V

2

RH199 100K_0 201_5%

+3VS

TP_WAK E_KBC# 26,31

+3V_PCH_ PRIM

YH1 CH45 CH46 Main X76 control

X7676731L91

XTAL24_ OUT_R

XTAL24_ IN_R

YH2 CH47 CH48 Main X76 control

X7676731L74

PLTRST# 23,26,33,3 4,35,41,4 8

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

PCH (2/7) CLK,SPI,PLTRST

Document Numb er Rev

LA-F611P

1

0.3

17 7 8Thursday, March 22, 2018

0.3

8SGDWH2.

CNP-H

1 OF 13

RPH5

1 8 2 7 3 6 4 5

33_080 4_8P4R_5 %

1 2

RH104 15_04 02_1%EMI@

CNP-H

CLKOUT_ITP XDP#

CLKOUT_ITP XDP_P

CLKOUT_CP UPCIBCLK#

CLKOUT_CP UPCIBCLK_ P

CLKOUT_P CIE_N0 CLKOUT_P CIE_P0

CLKOUT_P CIE_N1 CLKOUT_P CIE_P1

CLKOUT_P CIE_N2 CLKOUT_P CIE_P2

CLKOUT_P CIE_N3 CLKOUT_P CIE_P3

CLKOUT_P CIE_N4 CLKOUT_P CIE_P4

CLKOUT_P CIE_N5 CLKOUT_P CIE_P5

CLKOUT_P CIE_N6 CLKOUT_P CIE_P6

CLKOUT_P CIE_N7 CLKOUT_P CIE_P7

CLKOUT_P CIE_N8 CLKOUT_P CIE_P8

CLKOUT_P CIE_N9 CLKOUT_P CIE_P9

CLKOUT_P CIE_N10 CLKOUT_P CIE_P10

CLKOUT_P CIE_N11 CLKOUT_P CIE_P11

7 OF 13

CLKIN_X TAL

GPP_B1 3/PLTRST#

GPP_K1 6/GSXCLK

GPP_K1 2/GSXDOUT

GPP_K1 3/GSXSLO AD

GPP_K1 4/GSXDIN

GPP_K1 5/GSXSRE SET#

GPP_E3 /CPU_GP0 GPP_E7 /CPU_GP1 GPP_B3 /CPU_GP2 GPP_B4 /CPU_GP3

GPP_H1 8/SML4ALE RT#

GPP_H1 7/SML4DATA

GPP_H1 6/SML4CLK

GPP_H1 5/SML3ALE RT#

GPP_H1 4/SML3DATA

GPP_H1 3/SML3CLK

GPP_H1 2/SML2ALE RT#

GPP_H1 1/SML2DATA

GPP_H1 0/SML2CLK

INTRUDER#

PCH_SPI _HOLD#_R PCH_SPI _SO_R PCH_SPI _SI_R PCH_SPI _WP#_R

PCH_SPI _CLK_RPCH_SPI _CLK

Y3 Y4

PCH_CPU_ PCIBCLK_N

B6

PCH_CPU_ PCIBCLK_P

A6

AJ6 AJ7

AH9 AH10

AE14 AE15

AE6 AE7

AC2 AC3

AB2 AB3

W4 W3

W7 W6

AC14 AC15

U2 U3

AC9 AC11

AE9 AE11

R6

AV29

Y47 Y46 Y48 W46 AA45

AL47 AM45 BF32 BC33

AE44 AJ46 AE43 AC47 AD48 AF47 AB47 AD47 AE48

BB44

PCH_SPI _CLK_R 23

3

PCH_XDP _CLK_N PCH_XDP _CLK_P

CLK_PCI E_N0 CLK_PCI E_P0

CLK_PCI E_N7 CLK_PCI E_P7

CLK_PCI E_N9 CLK_PCI E_P9

RH698 0_0402 _5%

RH716 10K_020 1_5%

PCH_PLTRS T#

TBT_FORCE_ PWR RTD3_CIO_ PWR_EN RTD3_USB_ PWR_EN

TOUCH_SCRE EN_PD#

TOUCHPAD_ INTR#

GC6_THM_D IS#

GPP_H1 5

GPP_H1 2

INTRUDER#

T4938 TP@ T4939 TP@

PCH_CPU_ PCIBCLK_N 10 PCH_CPU_ PCIBCLK_P 1 0

CLK_PCI E_N0 41 CLK_PCI E_P0 41

CLK_PCI E_N7 48 CLK_PCI E_P7 48

TBT-A R

GPU

TBT

CH45

8.2P_0 402_50V

XTAL_M@

XTAL24_ OUT XTAL24_ IN

GPU

CLK_PCI E_N9 34

CLK_PCI E_P9 34

NGFF - SSD

NVMe

REFCLK_ CNVREFCLK_ CNV_H

12

CNV@

1 2

TBT_FORCE_ PWR 41

RTD3_CIO_ PWR_EN 41 RTD3_USB_ PWR_EN 41

TOUCH_SCRE EN_PD# 29

GC6_THM_D IS# 26

+RTC_CELL_ PCH

1 2

1M_040 2_5%

RH531

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

REFCLK_ CNV 33

2016/01/06 2017/01/06

XTAL_M@

CH47

12P_04 02_50V

PCH_PLTRS T#

12

RH742 100K_0 201_5%

TOUCH_SCRE EN_PD#

TOUCHPAD_ INTR#

GC6_THM_D IS#

TOUCHPAD_ INTR# TP_WAK E_KBC#

RB751S 40T1G_SOD5 23-2

HDD_EN_P CH

GPP_H1 5

GPP_H1 2

PCH_SPI _CLK_R

Reserve for ESD

PCH_PLTRS T#

Compal Secret Data

Deciphered Date

2

UH1G

T92TP@

+3VS

1 2

RH728 100K_0 201_5%

1 2

D D

C C

B B

RH680 100K_0 201_5%

RP3

4 5 3 6 2 7 1 8

10K_08 04_8P4R_ 5%

CFL-H PDG rev0.7 pop 20K for SP I0_IO2/3

CNL- PCH EDS rev0.5 Reserved External pull-up is required. Recommend 100K if pulled up to 3 .3V

+3V_SPI

RH74 4.7K_ 0402_5%@

RH75 100K_ 0402_5%

RH78 100K_ 0402_5%

RH735 100K_0 402_5%

RH455 1K_020 1_5%@

+3V_PCH_ PRIM +3V_SPI

FFS_INT1

FFS_INT2

CLKREQ_ PCIE#7 CLKREQ_ PCIE#14 CLKREQ_ PCIE#15 CLKREQ_ PCIE#9

1 2

12

RSPI1 0_0402 _5%

FFS_INT1 20 ,32

GPU LAN WLAN NVMe

PCH_SPI _CS#

PCH_SPI _WP#_R

PCH_SPI _HOLD#_R

PCH_SPI _SI_R

PCH_SPI _HOLD#_R

+1.05VALW

RH71 2.7K_0402_1 %

XCLK_ BIASREF Trace Width/Space: 15mil /15 mil Max Trace Length: 1000 mil

CPU_24M HZ_P10 CPU_24M HZ_N10

PCH_CPU_ BCLK_P10 PCH_CPU_ BCLK_N10

pop RH71 for K BL-H pop RH20 for CFL-H , PDG 0.5

1 2

@

1 2

RH20 60.4_ 0402_1%

TBT

GPU

NVMe

LAN WLAN

WLAN

CLKREQ_ PCIE#041

CLKREQ_ PCIE#934

CLKREQ_ PCIE#1435

CLKREQ_ PCIE#1533

CLK_PCI E_N1533 CLK_PCI E_P1533

LAN

PCH_SPI _SI_R23,38

PCH_SPI _SO_R23

RH1 close to UH4

PCH_SPI _WP#_R38

PCH_SPI _CS2#23

FFS_INT232

HDD_EN_P CH32

CLKREQ_ PCIE#748

CLK_PCI E_N1435

CLK_PCI E_P1435

TPM_PIRQ#23

CPU_24M HZ_P CPU_24M HZ_N

PCH_CPU_ BCLK_P PCH_CPU_ BCLK_N

XCLK_B IASREF

CLKREQ_ PCIE#0

CLKREQ_ PCIE#7

CLKREQ_ PCIE#9

CLKREQ_ PCIE#14 CLKREQ_ PCIE#15

CLK_PCI E_N15 CLK_PCI E_P15

CLK_PCI E_N14 CLK_PCI E_P14

PCH_SPI _SI_R PCH_SPI _SO_R

PCH_SPI _SI_R PCH_SPI _SO_R PCH_SPI _CS# PCH_SPI _CLK_R

PCH_SPI _WP#_R PCH_SPI _HOLD#_R PCH_SPI _CS2#

HDD_DET#

T4940PAD@

FFS_INT2 TPM_PIRQ#

HDD_EN_P CH_H

HDD_EN_P CH HDD_EN_P CH_H

1 2

@

RH699 0_0201_ 5%

XTAL24_ OUT XTAL24_ IN

XCLK_B IASREF

PCH_RTCX1 PCH_RTCX2

SPI ROM PCH

+3V_SPI

SPI ROM FOR ME ( 32MByte ) PN: SA00009RI10

PCH_SPI _CS# PCH_SPI _SO PCH_SPI _WP#

A A

PCH_SPI _CS# PCH_SPI _SO PCH_SPI _WP# PCH_SPI_ CLK

UH4

1

CS#

2

DO

3

WP#

4

GND1

9

GND2

W25Q 256JVEIQ_ WSON8_ 8X6

SA00009RI10

@

UH15

1

/CS

2

DO(IO1)

3

/WP(IO 2) GND4DI(IO0)

S IC FL 1 28M W25 Q128JVSI Q SOIC8P S PI ROM

SA00005VV20

MAIN@

HOLD#_R ESET#

VCC

/HOLD(IO3 )

CLK

VCC

CLK

DI

+3V_SPI

8 7 6 5

8

PCH_SPI _HOLD#

7

PCH_SPI _CLK

6

PCH_SPI _SI

5

PCH_SPI _HOLD#

PCH_SPI _SI

1

CH49

0.1U_04 02_16V7 K

2

PCH_SPI_CLK

Close UH4

33_0402_5%

RH708

@EMI@

1 2

33P_0402_50V8J

@EMI@

CH224

1 2

BE33

GPP_A1 6/CLKOUT_4 8

D7

CLKOUT_CP UNSSC_P

C6

CLKOUT_CP UNSSC#

B8

CLKOUT_CP UBCLK_P

C8

CLKOUT_CP UBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_B IASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5 /SRCCLKREQ 0#

BE31

GPP_B6 /SRCCLKREQ 1#

AR32

GPP_B7 /SRCCLKREQ 2#

BB30

GPP_B8 /SRCCLKREQ 3#

BA30

GPP_B9 /SRCCLKREQ 4#

AN29

GPP_B1 0/SRCCLKRE Q5#

AE47

GPP_H0 /SRCCLKREQ 6#

AC48

GPP_H1 /SRCCLKREQ 7#

AE41

GPP_H2 /SRCCLKREQ 8#

AF48

GPP_H3 /SRCCLKREQ 9#

AC41

GPP_H4 /SRCCLKREQ 10#

AC39

GPP_H5 /SRCCLKREQ 11#

AE39

GPP_H6 /SRCCLKREQ 12#

AB48

GPP_H7 /SRCCLKREQ 13#

AC44

GPP_H8 /SRCCLKREQ 14#

AC43

GPP_H9 /SRCCLKREQ 15#

V2

CLKOUT_P CIE_N15

V3

CLKOUT_P CIE_P15

T2

CLKOUT_P CIE_N14

T1

CLKOUT_P CIE_P14

AA1

CLKOUT_P CIE_N13

Y2

CLKOUT_P CIE_P13

AC7

CLKOUT_P CIE_N12

AC6

CLKOUT_P CIE_P12

CNP-H_BG A874

UH1A

BE36

GPP_A1 1/PME#/SD _VDD2_PW R_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MO SI

BA45

SPI0_MI SO

AY47

SPI0_CS 0#

AW47

SPI0_CL K

AW48

SPI0_CS 1#

AY48

SPI0_IO 2

BA46

SPI0_IO 3

AT40

SPI0_CS 2#

BE19

GPP_D1 /SPI1_CLK /SBK1_BK 1

BF19

GPP_D0 /SPI1_CS# /SBK0_BK 0

BF18

GPP_D3 /SPI1_MOS I/SBK3_BK 3

BE18

GPP_D2 /SPI1_MISO /SBK2_BK 2

BC17

GPP_D2 2/SPI1_IO 3

BD17

GPP_D2 1/SPI1_IO 2

CNP-H_BG A874

PCH_SPI _HOLD# PCH_SPI _SO PCH_SPI _SI PCH_SPI _WP#

Co-lay with UH4

5

4

RH70 10M_04 02_5%

1 2

YH1

32.768 KHZ_X1A00 0141000 300

1 2

XTAL_M@

1

2

RTC CRYSTAL Max Crystal ESR = 50k Ohm.

Reserve for RF immunity

1 2

RH711 33_ 0201_5%RFI@

1 2

RH712 33_ 0201_5%RFI@

RH72 1M_040 2_5%~D

1 2

YH2

24MHZ 12 PF +-10PPM 7M240900 01

123

1

XTAL_M@

2

Metal Shielding Type

+3VS

UH3

5

TC7SH08FU _SSOP5

1

P

B

Y

2

A

G

MAIN@

3

1 2

RH69 10K_0 201_5%

1 2

RH179 10K _0201_5 %

1 2

RH573 10K _0201_5 %

DH2

12

MAIN@

1 2

RH687 10K _0201_5 %@

1 2

RH726 100 K_0201_ 5%

1 2

RH727 4.7 K_0402_5 %@

1 2

RH738 100 K_0201_ 5%

1 2

CH222 100P_0402_5 0V8J

@ESD@

Main Func = PCH

D D

C C

B B

A A

PCH to DDR, XDP, FFS

+RTC_CELL_PCH

RH83 20K_0402_5%~D

1 2

1U_0603_10V6K~D

RTCRST_ON23,26

RH679

100K_0201_5%

+RTC_CELL_PCH

1 2

RH84 20K_0402_5%~D

1U_0603_10V6K~D

+3V_PCH_PRIM

1 2

RH674 1K_0201_5%

1 2

RH675 1K_0201_5%

1 2

RH62 1K_0201_5%

1 2

RH63 1K_0201_5%

+3VS

1 2

RH501 499_0402_1%@

RH502 499_0402_1%@

1 2

RH463 1K_0201_5%

1 2

RH462 1K_0201_5%

1 2

RH676 10K_0201_5%

RH700 100K_0201_5%

1 2 1 2

RH673 100K_0201_5%

1 2

RH90 100K_0201_5%@

Buffer with Open Drain Output For VTT power contr ol

UC16

1

NC

VR_ON

2

A

3

GND

74AUP1G07SE-7_SOT353

SA00007WE00

MAIN@

Service Mode Switch: Add a swit ch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

ME_FWP26

ME_FWP PC H has internal 20K PD.

FLASH DESC RIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) Enable ME Protect (ME cannot be updated)(Default posit i on)

5

PCH_SRTCRST#

1

CH52

2

PCH_RTCRST#

DVT1.0 Change QH6 to SB00000P U00

13

D

QH7

2

G

1

12

2

SHORT PADS

L2N7002LT1G_SOT23-3

GEN8@

S

PCH_RTCRST#

CLRP1

12

GEN8@

CH53

CLRP1 in DIMM Door

SMBCLK SMBDATA

SML0_SMBCLK SML0_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

PCH_SMBCLK

PCH_SMBDATA

DGPU_PWROK

PCH_RSMRST# SYS_PWROK PCH_DPWROK

+3VALW

CC2980.1U_0402_16V7K

12

5

VCC

H_VCCST_PWRGD

4

Y

RH16 1K_0402_1%

1 2

5

PCH_AZ_CODEC_SDIN024

CPU_DISPA_SDO6

CPU_DISPA_SDI6

CPU_DISPA_BCLK6

PCH_RSMRST#26,38

GPU_TH M_SMBC LK GPU_T HM_SMB DAT

H_VCCST_PWRGD 10

PCH_AZ_SDOUT

SMBCLK

SMBDATA

IMVP_VR_ON26

PCH_AZ_CODEC_SDOUT24 PCH_AZ_CODEC_SYNC24

PCH_AZ_CODEC_BITCLK24

RH39 30_0402_5%

1 2

RH38 30_0402_5%

CLKREQ_CNV#33 CNV_RF_RESET#33

DGPU_PWROK48,56,76

1 2

RH503 0_0201_5%

1 2

RH672 0_0201_5%

GPU_THM_SMBCLK26,31,48

GPU_THM_SMBDAT26,31,48

GPU_THM_ EC

+3VS

QH4A

2

DMN65D8LDW-7_SOT363-6

6 1

5

MAIN@

3 4

QH4B DMN65D8LDW-7_SOT363-6

MAIN@

IMVP_VR_ON

SIO_SLP_S3#

MC74VHC1G08DFT2G_SC70-5

SA00000OH00

1

2

1 8 2 7 3 6 4 5

VSVALW

IN1

IN2

MAIN@

RP50

33_0804_8P4R_5%

GPU_ID2 GPU_ID1

SMBCLK SMBDATA SML0ALERT#

SML0_SMBCLK SML0_SMBDATA

SML1ALERT# GPU_THM_SMBCLK

GPU_THM_SMBDAT

PCH_SMBCLK

PCH_SMBDATA

+3VALW

5

3

PCH_AZ_SDOUT PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_BITCLK

PCH_AZ_BITCLK

PCH_AZ_SDOUT PCH_AZ_SYNC

PCH_AZ_RST#

CPU_DISPA_SDO_R

CPU_DISPA_BCLK_R

CLKREQ_CNV# CNV_RF_RESET#

DGPU_PWROK

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK

PCH_RSMRST#_RPCH_RSMRST#

PCH_DPWROK

SMBALERT#

UZ21

VCC

4

OUT

GND

4

BD11 BE11 BF12

BG13

BE10 BF10 BE12 BD12

AM2 AN3 AM3

AV18

AW18

BA17 BE16 BF15 BD16 AV16

AW15

BE47 BD46

AY42 BA47

AW41

BE25 BE26 BF26 BF24 BF25 BE24 BD33 BF27 BE27

PCH to DDR / FFS

PCH_SMBCLK 14,15,32

PCH_SMBDATA 14,15,32

1

CC302

0.1U_0201_6.3V6K

2

VR_ON

12

RZ71 100K_0201_5%

RH552

10K_0201 _5%

SD043100280

RH554

10K_0201 _5%

SD043100280

4

GPU ID

UMA N17P- G0 N17E-G 1 N17P- G1

UH1D

HDA_BCLK/I2S0_SCLK HDA_SDI0/I2S0_RXD HDA_SDO/I2S0_TXD HDA_SYNC/I2S0_SFRM

HDA_RST#/I2S1_SCLK HDA_SDI1/I2S1_RXD I2S1_TXD/SNDW2_DATA I2S1_SFRM/SNDW2_C LK

HDACPU_SDO HDACPU_SDI HDACPU_SCLK

GPP_D8/I2S2_SCLK GPP_D7/I2S2_RXD GPP_D6/I2S2_TXD/MODEM_CLKREQ GPP_D5/I2S2_SFRM/CNV_RF_RES ET# GPP_D20/DMIC_DATA0/SNDW 4_DATA GPP_D19/DMIC_CLK0/SNDW 4_CLK GPP_D18/DMIC_DATA1/SNDW 3_DATA GPP_D17/DMIC_CLK1/SNDW 3_CLK

RTCRST# SRTCRST#

PCH_PWROK RSMRST#

DSW_PW ROK GPP_C2/SMBALERT# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK GPP_C7/SML1DATA

CNP-H_BGA874

VR_ON 67

UMA@

GPP_A12/BM_BUSY#/ISH_GP6/SX _EXIT_HOLDOFF#

IMVP_VR_PG67

ALL_SYS_PWRGD18,26

GPU I D2 (GPP_D6)

0 0 1 1

RH551

N17P_G0@

10K_0201 _5%

SD043100280

RH554

N17P_G0@

10K_0201 _5%

SD043100280

3

CNP-H

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLA N#

GPP_B2/VRALERT#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

GPP_B12/SLP_S0#

GPP_A15/SUSACK#

GPP_A13/SUSW ARN#/SUSPWRDNA CK

GPD2/LAN_WAK E#

GPD1/ACPRESENT

4 OF 13

+VCCIO_PG64 ALL_SYS_PWRGD 18,26

IMVP_VR_PG

ALL_SYS_PWRGD

MC74VHC1G08DFT2G_SC70-5

GPU I D1 (GPP_D5)

0 1 0 1

N17E_G1@

RH551

10K_0201 _5%

SD043100280

RH553

10K_0201 _5%

SD043100280

RH553

10K_0201 _5%

SD043100280

RH552

10K_0201 _5%

SD043100280

DRAM_RESET#

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

SA00000OH00

MAIN@

N17P_G1@

BF36 AV32

BF41

BD42

BB46 BE32 BF33 BE29 R47 AP29 AU3

BB47 BE40 BF40 BC28 BF42 BE42 BC42

BE45 BF44 BE35 BC37

BG44 BG42 BD39 BE46 AU2 AW29 AE3

AL3 AH4 AJ4 AH3 AH2 AJ3

RH103

1 2

0_0201_5%

1

2

PCH_PCIE_WAKE#

SIO_SLP_S0#_PCH SIO_SLP_S3#_PCH SIO_SLP_S4#_PCH

+3VS

12

RH180 100K_0201_5%

1 2

0_0201_5%

+3VS

5

VCC

IN1

OUT

IN2

GND

3

10K_0201_5%

CLKRUN#

SYS_PWROK

RH4 0_0201_5%

PCH_BATLOW#

ME_SUS_PWR_ACK

LAN_WAKE# AC_PRESENT

SIO_PWRBTN# SYS_RESET#

RH105

UH14

4

+3VS

12

@

RH551

10K_0201_5%

12

@

RH552

10K_0201_5%

3

H_DRAMRST# 14

SYS_PWROK 26

12

1 2

RH682 0_0201_5%

1 2

RH683 0_0201_5% RH684 0_0201_5%

1 2

SUSCLK

PCH_BATLOW# 41

TH148TP@

12

RH11 0_0201_5%

SIO_PWRBTN# 26

SPKR 24 H_CPUPWRGD 10

XDP_ITP_PMODE 38 CPU_XDP_TCK0 10,38 CPU_XDP_TMS 10,38

CPU_XDP_TDO 10,38 CPU_XDP_TDI 10,38 PCH_JTAG_TCK1 38

ALL_SYS_PWRGD+VCCIO_PG

1

CC301

0.1U_0201_6.3V6K

2

PCH_PWROK

12

RH94 10K_0201_5%

12

@

RH553

GPU_ID1 GPU_ID2

12

@

RH554

PCIE_WAKE# 26,33,34,35,41

SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4#

RH713 0_0201_5%

RH714 0_0201_5%

LANWAKE#

12

DH1 RB751V40_SC76-2

2

PCH_PCIE_WAKE#

PCH_BATLOW#

AC_PRESENT

LAN_WAKE#

SIO_PWRBTN#

ME_SUS_PWR_ACK

CLKRUN#

SIO_SLP_S0# 23,26 SIO_SLP_S3# 36,37,41 SIO_SLP_S4# 37,66

12

LANWAKE# 26

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SUSCLK_WLAN 33

SUSCLK_EC 26

HW_ACAV_IN 26,59,60,61

Reserve for ESD

12

CH212 100P_0402_50V8J

12

CH209 100P_0402_50V8J

@ESD@

Reserve for RF please cl ose to UH1

1 2

CH51 10P_0402_25V8J

@RF@

+3VALW

1 2

RH685 150K_0402_5%@

Top Swap Ov erride ( internal PD)

HIGH LOW(DEFAULT)

2016/01/06 201 7/01/06

ESD@

2

Enabl e Dis able

PCH_RSMRST#

SYS_RESET#

PCH_AZ_SDOUT

SPKR

Compal Secret Data

Deciphered Date

+3V_PCH_PRIM

SYS_RESET#

PCH_AZ_RST# PCH_AZ_BITCLK SIO_SLP_S3# SIO_SLP_S4# HW_ACAV_IN

RH66 2.2K_0402_5%@

1 2

TLS CONFIDENTIAL ITY

HIGH LOW(DEFAULT)

1 2

RH64 2.2K_0402_5%

EC interface

HIGH LOW(DEFAULT)

1 2

RH65 150K_0402_5%

PCHHOT#

HIGH LOW(DEFAULT)

1

+3VALW_DSW

1 2

RH453 1K_0201_5%

RH515 8.2K_0402_5%

1 2

RH533 100K_0201_5%

1 2

RH545 10K_0201_5%

RH717 10K_0201_5%

1 2

RH506 1M_0402_5%@

1 2

+3V_1.8V_PGPPA

@

1 2

RH701 8.2K_0402_5%

+3V_PCH_PRIM

RH737 8.2K_0402_5%

1 2

RH571 8.2K_0402_5%@

1 2

RH746 100K_0201_5%@

1 2

RH739 100K_0201_5% RH740 100K_0201_5%

1 2

RH741 100K_0201_5%

1 2 1 2

RH749 1K_0201_5%@

SMBALERT#

Enabl e Dis able

SML0ALERT#

ESPI* LPC

SML1ALERT#

Enabl e Dis able

Title

PCH (3/7) PM,HDA ,SMB,JTAG

Size Documen t Number Rev

LA-F611P

Date : Sheet of

+3VS

Compal Electro nics, Inc.

1

0.3

18 78Thursday, March 22, 2018

5

4

3

2

1

Main Func = PCH

8SGDWH2.

DMI_CTX_PRX_N09 DMI_CTX_PRX_P09

DMI_CRX_PTX_N09 DMI_CRX_PTX_P09

DMI_CTX_PRX_N19

D D

C C

USB3.0 Port1

B B

USB3.0 Port2

DMI_CTX_PRX_P19

DMI_CRX_PTX_N19

DMI_CRX_PTX_P19 DMI_CTX_PRX_N29 DMI_CTX_PRX_P29

DMI_CRX_PTX_N29

DMI_CRX_PTX_P29 DMI_CTX_PRX_N39 DMI_CTX_PRX_P39

DMI_CRX_PTX_N39

DMI_CRX_PTX_P39

USB3_PTX_DRX_N127 USB3_PTX_DRX_P127 USB3_PRX_DTX_N127 USB3_PRX_DTX_P127

USB3_PTX_DRX_P327 USB3_PTX_DRX_N327 USB3_PRX_DTX_P327 USB3_PRX_DTX_N327

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB3_PRX_DTX_P1

USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 USB3_PRX_DTX_N3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

DMI7_TXP

B25

DMI7_TXN

P24

DMI7_RXP

R24

DMI7_RXN

C26

DMI6_TXP

B26

DMI6_TXN

F26

DMI6_RXP

G26

DMI6_RXN

B27

DMI5_TXP

C27

DMI5_TXN

L26

DMI5_RXP

M26

DMI5_RXN

D29

DMI4_TXP

E28

DMI4_TXN

K29

DMI4_RXP

M29

DMI4_RXN

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BGA874

UH1F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CNP-H_BGA874

CNP-H

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3# GPP_F15/USB2_OC4# GPP_F16/USB2_OC5# GPP_F17/USB2_OC6# GPP_F18/USB2_OC7#

USB2_COMP

USB2_VBUSSENSE

RSVD1

USB2_ID

GPD7

PCIE24_TXP PCIE24_TXN PCIE24_RXP PCIE24_RXN PCIE23_TXP PCIE23_TXN PCIE23_RXP PCIE23_RXN PCIE22_TXP PCIE22_TXN PCIE22_RXP PCIE22_RXN PCIE21_TXP PCIE21_TXN PCIE21_RXP PCIE21_RXN

2 OF 13

CNP-H

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2 GPP_E5/SATA_DEVSLP1 GPP_E4/SATA_DEVSLP0 GPP_F9/SATA_DEVSLP7 GPP_F8/SATA_DEVSLP6 GPP_F7/SATA_DEVSLP5 GPP_F6/SATA_DEVSLP4 GPP_F5/SATA_DEVSLP3

6 OF 13

J3 J2 N13 N15 K4 K3 M10 L9 M1 L2 K7 K6 L4 L3 G4 G5 M6 N8 H3 H2 R10 P9 G1 G2 N3 N2 E5 F6

AH36 AL40 AJ44 AL41 AV47 AR35 AR37 AV43

F4 F3 U13 G3

BE41

G45 G46 Y41 Y40 G48 G49 W44 W43 H48 H47 U41 U40 F46 G47 R44 T43

BB39 AW37 AV37 BA38

BE38 AW35 BA36 BE39 BF38

BB36 BB34

T48 T47

AH40 AH35 AL48 AP47 AN37 AN46 AR47 AP48

USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9

USB20_N11 USB20_P11

USB20_N14 USB20_P14

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB2_COMP USB2_VBUSSENSE

USB2_ID

GPD_7

PCIE_PTX_DRX_P24 PCIE_PTX_DRX_N24 PCIE_PRX_DTX_P24 PCIE_PRX_DTX_N24 PCIE_PTX_DRX_P23 PCIE_PTX_DRX_N23 PCIE_PRX_DTX_P23 PCIE_PRX_DTX_N23 PCIE_PTX_DRX_P22 PCIE_PTX_DRX_N22 PCIE_PRX_DTX_P22 PCIE_PRX_DTX_N22 PCIE_PTX_DRX_P21 PCIE_PTX_DRX_N21 PCIE_PRX_DTX_P21 PCIE_PRX_DTX_N21

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

ESPI_CS# ESPI_ALERT#

PIRQA#

ESPI_RESET#

ESPI_CLK

SSD_DEVSLP HDD_DEVSLP

USB20_N1 27 USB20_P1 27 USB20_N2 27 USB20_P2 27 USB20_N3 27 USB20_P3 27 USB20_N4 40 USB20_P4 40 USB20_N5 29 USB20_P5 29 USB20_N6 27 USB20_P6 27 USB20_N7 33 USB20_P7 33 USB20_N8 29 USB20_P8 29 USB20_N9 28 USB20_P9 28

TH145TP@ TH143TP@

TH142TP@ TH141TP@

USB_OC0# 27 USB_OC1# 27

1 2

RH109 113_0402_1%

1 2

RH580 1K_0201_5%

1 2

RH581 1K_0201_5%

PCIE_PTX_DRX_P24 41 PCIE_PTX_DRX_N24 41

PCIE_PRX_DTX_P24 41

PCIE_PRX_DTX_N24 41 PCIE_PTX_DRX_P23 41 PCIE_PTX_DRX_N23 41

PCIE_PRX_DTX_P23 41

PCIE_PRX_DTX_N23 41 PCIE_PTX_DRX_P22 41 PCIE_PTX_DRX_N22 41

PCIE_PRX_DTX_P22 41

PCIE_PRX_DTX_N22 41 PCIE_PTX_DRX_P21 41 PCIE_PTX_DRX_N21 41

PCIE_PRX_DTX_P21 41

PCIE_PRX_DTX_N21 41

RPH7

ESPI_IO0_R

18

ESPI_IO1_R

27

ESPI_IO2_R

36

ESPI_IO3_R

45

15_0804_8P4R_5%

EMI@

SSD_DEVSLP 34 HDD_DEVSLP 32

ESPI_CLK_R

1 2

RH658 15_0402_5%

-----> Port 1, USB3.0 (MB)

-----> Port 3, USB2.0 (IO/B)

-----> Port 2, USB3.0 (MB)

-----> TYPEC PD

-----> CCD

-----> Card Reader (IO/B)

-----> BT & CNVi BRI use

-----> Touch Screen

-----> Finger Printer

TBT-AR

ESPI_IO0_R 26 ESPI_IO1_R 26 ESPI_IO2_R 26 ESPI_IO3_R 26

ESPI_CS# 26 ESPI_ALERT# 26

ESPI_RESET# 26

ESPI_CLK_R 26

+3V_PCH_PRIM

USB_OC0# USB_OC1# USB_OC3# USB_OC2#

10K_8P4R_5%

4 5 3 6 2 7 1 8

RPH6

USB2_COMP 50ohm single-ended and as short as possible Spacing=15 mils Max length= 1000 mils

+3V_PCH_PRIM

12

RH12

PIRQA#

ESPI_ALERT#

USB_OC0#

ESPI_RESET#

GPD_7

X'tal Input: High: Differential Low: Single ended

1 2

RH546 10K_0201_5%

1 2

RH578 8.2K_0402_5%

1 2

CH228 0.1U_0402_10V7K

1 2

RH743 100K_0201_5%

+1.8V_PRIM

12

@

RH705 10K_0201_5%

100K_0201_5%

Reserve for EMI

ESPI_CLK

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

2

12

CC57

@EMI@ 12P_0402_50V8J

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

PCH (4/7) DMI,PCIE,USB,LPC

Document Number Re v

LA-F611P

0.3

19 78T hursday, March 22, 2018

1

19 78T hursday, March 22, 2018

0.3

5

4

3

2

1

Main Func = PCH

NGSYNC@

1 2

1 2 1 2

1 2

+3V_PCH_PRIM

LPC SPI

Enable Disa ble

1

+3VS

+3V_1.8V_PGPPA

BBS_BIT0

NRB_BIT

20 78T hursday, March 22, 2018

0.3

+3VS

GSYNC_ID

CNV_BRI_PTX_DRX

GPP_J9

CNV_BRI_PRX_DTX

CNV_RGI_PRX_DTX

5

WLAN_RADIO_DIS#

SIO_EXT_SCI#

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

BT_RADIO_DIS#

WLAN_RADIO_DIS#

CNV_RGI_PTX_DRX

CPU_VCCIO_PWR_GATE#

RTC_DET#

SIO_EXT_WAKE#

BBS_BIT0

3.3V_TS_EN29

FFS_INT117,32

DBC_PANEL_EN29

GPU_GC6_FB_EN_H48,56

GPU_EVENT#48

BT_RADIO_DIS#33

HDMI_HPD_PCH44

SIO_EXT_WAKE#26

UART_2_CTXD_DRXD33

UART_2_CRXD_DTXD33

I2C1_SCL_TCH_PAD31 I2C1_SDA_TCH_PAD31

TBT_CIO_PLUG_EVENT#41

KB_LED_BL_DET31

CPU_VCCIO_PWR_GATE#36

CNV_BRI_PTX_DRX33

CNV_BRI_PRX_DTX33

CNV_RGI_PTX_DRX33

CNV_RGI_PRX_DTX33

3.3V_TS_EN SIO_EXT_SCI# FFS_INT1

NRB_BIT

GPU_GC6_FB_EN_H

EDP_SW

T4937PADTP@

CPU_ID

BT_RADIO_DIS#

SIO_EXT_WAKE# UART_2_CTXD_DRXD UART_2_CRXD_DTXD

TBT_CIO_PLUG_EVENT#

KB_LED_BL_DET

CPU_VCCIO_PWR_GATE#

CNV_BRI_PTX_DRX

CNV_BRI_PRX_DTX

CNV_RGI_PTX_DRX

CNV_RGI_PRX_DTX

GPP_J9

4

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0_TXD

BE23

GPP_C8/UART0_RXD

AP24

GPP_C11/UART0_CTS#

BA24

GPP_C10/UART0_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BGA874

UH1M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_D0

BF8

GPP_G2/SD_D1

BF9

GPP_G3/SD_D2

BG8

GPP_G4/SD_D3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_VCCIO_PWR_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J_4_CNV_BRI_DT_UART0_RTSB

AY2

GPP_J5/CNV_BRI_RSP/UART0_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CNP-H_BGA874

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

CNP-H

13 OF 13

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1

CNV_WR_CLKN CNV_WR_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WT_CLKN CNV_WT_CLKP

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N CNV_WT_D1P

PCIE_RCOMPN

PCIE_RCOMPP SD_RCOMP_1P8 SD_RCOMP_3P3

RSVD2 RSVD3

RSVD1

GPP_A18/ISH_GP0

BD4 BE3

BB3 BB4 BA3 BA2

BC5 BB6

BE6 BD7 BG6 BF6 BA1

B12 A13 BE5 BE4 BD1 BE1 BE2

Y35 Y36

BC1 AL35

TP

3

CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P

CNV_PRX_DTX_N0 CNV_PRX_DTX_P0 CNV_PRX_DTX_N1 CNV_PRX_DTX_P1

CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P

CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 CNV_PTX_DRX_N1 CNV_PTX_DRX_P1

CNV_WT_RCOMP

PCIE_RCOMPN PCIE_RCOMPP SD_RCOMP_1P8 SD_RCOMP_3P3

GPPJ_RCOMP_1P8

Security Classification

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

CNV_WT_RCOMP

GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P83

BA20

DGPU_HOLD_RST#

BB20

WLAN_RADIO_DIS#

BB16

DGPU_PWR_EN

AN18

BF14 AR18

CNVi_EN#

BF17

GSYNC_ID

BE17

AG45 AH46

AH47 AH48

RTC_DET#

AV34 AW32 BA33

KB_DET#

BE34 BD34 BF35

DGPU_PRSNT#

BD38

RH667

1 2

150_0402_1%

1 2

RH669 100_0402_1%

1 2

RH668 200_0402_1%

1 2

RH670 200_0402_1%

1 2

RH666 200_0402_1%

Issued Date

TH101TP@

2016/01/06 2017/01/06

#571483_CFL_H_RVP_CRB_TDK_Rev0p5 Recommend external test point

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

1 2

RH135 10K_0201_5%

DGPU_HOLD_RST# 48 WLAN_RADIO_DIS# 33 DGPU_PWR_EN 56

CNVi_EN# 33

RTC_DET# 23

KB_DET# 31

CLK_CNV_PRX_DTX_N 33 CLK_CNV_PRX_DTX_P 33

CNV_PRX_DTX_N0 33 CNV_PRX_DTX_P0 33 CNV_PRX_DTX_N1 33 CNV_PRX_DTX_P1 33

CLK_CNV_PTX_DRX_N 33 CLK_CNV_PTX_DRX_P 33

CNV_PTX_DRX_N0 33 CNV_PTX_DRX_P0 33 CNV_PTX_DRX_N1 33 CNV_PTX_DRX_P1 33

Compal Secret Data

Deciphered Date

2

CPU_ID

DGPU_PWR_EN

KB_DET#

+3V_PCH_PRIM

Title

Size

Date: Sheet o f

1 2

RH520 8.2K_0402_5%@

1 2

RH521 10K_0201_5%

RH709 49.9K_0402_1%

D D

RH710 49.9K_0402_1%

+3VALW

RH706 8.2K_0402_5%@

RH707 8.2K_0402_5%@

C C

Follow CRB REV0.9 PU 4.7K

+1.8V_PRIM

RH671 4.7K_0402_5%~D

This signal has a weak internal pull-down. 0 = 38.4/19.2MHz XTAL frequency selected. (Default) 1 = 24MHz XTAL frequency selected. Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well.

B B

+1.8V_PRIM

RH93 10K_0402_5%@

+1.8V_PRIM

RH719 10K_0201_5%@

+1.8V_PRIM

A A

RH614 20K_0402_5%

RH613 20K_0402_5%

CFL PDG rev0.5 To avoid fl oating input at the I/O pin i t is recommended to add a weak pull up resistor to the SOC pin with a recommended value of 20K ohm.

12

1 2

M.2 CNV Mode Select

1 2

CNV@

RH588 20K_0402_5%

RH589 10K_0402_5%@

An external pull-up or pull-down is required. 0 = Integrated CNVi enable. 1 = Integrated CNVi disable.

12

The signal has a weak internal pull-down 0 = VCCPSPI is connected to 3.3V rail 1 = VCCPSPI is connected to 1.8V rail Note: If VCCPSPI is connected to 1.8V rail, this pin strap must be a ‘ 1’ for the proper functionality of the SPI (Flash) I/Os

12

1 2

@

1 2

@

1 2

RH29 10K_0201_5%GSYNC@

1 2

RH30 10K_0201_5%

RH734 10K_0201_5%@

RH721 10K_0201_5%

RH23 10K_0201_5%@ RH24 10K_0201_5%

RH537 10K_0201_5%

RH128 10K_0201_5%

1 2

RH130 2.2K_0402_5%@

Boot BIOS Strap Bit (internal PD )

HIGH LOW(DEFAULT)

+3V_PCH_PRIM

1 2

RH524 2.2K_0402_5%@

NO REBOOT mode (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

PCH (5/7) I2C,GPIO,CNVI

Document Number Re v

LA-F611P

A

B

C

D

E

Main Func = PCH

+RTC_CELL_PCH

+1.05VALW

5.95A

1 1

2 2

+1.05VALW +1.05VALW

22U_0402_6.3V6M

1U_0402_6.3V6K

Close to UC1.AA22 Close to UC1.U26 Close to UC1.BC49

1

CH62

2

PLACE 3-5MM FROM PACKAGE EDGE

1U_0402_6.3V6K

1

CH12

CH13

2

Deep Sx Well: 1.05V. This rail is generated by on die DSW low dropout (L DO) linear regulator to supply DSW core log ic. Board needs t o connect a 1uF capacitor to this rail and power should NOT be drive n from the board.

+1.05V_LDO

1U_0402_6.3V6K

1

CH16

2

+1.05VALW

RH732

RH731

+1.05VALW

+1.05V_LDO

0_0603_5 %

+1.05VALW

+1.05V_LDO

+1.05V_VCCAMPH YPLL

12

+1.05V_XTAL

12

+1.05VALW

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA87 4

CNP-H

8 OF 13

VCCPRIM_3P32

DCPRTC1 DCPRTC2

VCCPRIM_3P35

VCCSPI

VCCRTC1 VCCRTC2

VCCPGPPG_3P3

VCCPRIM_3P33 VCCPRIM_3P34

VCCPGPPHK1 VCCPGPPHK2 VCCPGPPEF1 VCCPGPPEF2

VCCPGPPD VCCPGPPBC1 VCCPGPPBC2

VCCPGPPA

VCCPRIM_3P31 VCCDSW_3P31 VCCDSW_3P32

VCCHDA VCCPRIM_1P83 VCCPRIM_1P84 VCCPRIM_1P85 VCCPRIM_1P86 VCCPRIM_1P87

VCCPRIM_1P81 VCCPRIM_1P82

VCCPRIM_1P0520 VCCPRIM_1P0519

VCCPRIM_1P241 VCCPRIM_1P242

VCCDPHY_1P241 VCCDPHY_1P242 VCCDPHY_1P243

VCCMPHY_SENSE VSSMPHY_SENSE

AW9

BF47 BG47

V23

AN44

BC49 BD49

AN21 AY8 BB7

AC35 AC36 AE35 AE36

AN24 AN26 AP26

AN32

AT44 BE48 BE49

BB14 AG19 AG20 AN15 AR15 BB11

AF19 AF20

AG31 AF31 AK22 AK23

AJ22 AJ23 BG5

K47 K46

0.182A

+VCCRTCE XT

0.095A

+RTC_C ELL_PCH

0.195A

0.97A

0.262A

0.174A

0.14A

0.334A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

0.193A

0.0895A

VCCMPHY_SEN SE VSSMPHY_SENSE

+3V_PCH_PRIM

+3V_1.8V_PGPPA

+1.8V_PRIM

+1.8V_PHVLDO

+1.05VALW +1.05VALW

+1.24V_VCCLDOSRAM_IN

+1.24V_PRIM_DPHY

+1.24V_PRIM_MAR

+3V_PCH_PRIM

+3VALW_DSW

1

close UC1.BB14 and <120mil

CC43

0.5P_0402 _50V8

2

RF@

1.24V for CNVi logic.

TH139T P@ TH138T P@

Can be NC if project do not use CNVI ?

+1.24V_VCCLDOSRAM_IN +1.24V_PR IM_DPHY

1 2

RH174 0_0402_5 %

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

0.1U_0402_10V6K

1

CH225

2

1 2

RH697 0_04 02_5%

1U_0402_6.3V6K

1

CH226

2

For DDX30 R02

+1.24V_PRIM_MAR

+RTC_CELL

GEN8@

+VCCRTCE XT

+1.8V_PRIM

4.7U_0402_6.3V6M

1

CH35

2

Close to AG20,AN15

4.7U_0402_6.3V6M

1

CH36

2

0.1U_0402_10V6K

1

CH25

2

1U_0402_6.3V6K

CH29

+1.8V_PRIM +1.8V_PHV LDO

1 2

+1.05VALW

3 3

+1.05VALW

+1.05V_VCCAMPHYPLL

4 4

+1.05VALW

1P_0402_50V8

1

CH24

2

@

1P_0402_50V8

1U_0402_6.3V6K

1

CH17

CH223

Close to UC1.D1

2

@

+1.05VALW

0.1U_0402_10V6K

1

CH15

2

0.1U_0402_10V6K

Close to UC1.W22Close to UC1.W31

1

CH14

2

@

+1.05V_XTAL

1U_0402_6.3V6K

22U_0402_6.3V6M

1

CH19

CH18

2

@

22U_0402_6.3V6M

1

CH20

2

@

Close to UC1.C49 Close to UC1.P2

A

+1.05VALW +1.05VALW

0.1U_0402_10V6K

1

CH22

Check OK

2

Close to UC1.C1

@

+1.05VALW

1U_0402_6.3V6K

1

Check OK

CH21

2

+1.05VALW Discharge

PCH_PRIM_EN26,37 ,65,66

B

1U_0402_6.3V6K

1

2

CH23

close UC1.C1 and <120mil

1

2

close UC1.C1 and <120mil

1

CC41

0.5P_0402 _50V8

2

RF@

10K_0402 _5%

PCH_PRIM_EN

CC42

0.5P_0402 _50V8

RF@

+5VALW

12

RH747

@

61

2

+1.05VALW

12

RH748

51_0402_ 5%@

3

QH10B

@

5

DMN53D0 LDW-7_SOT3 63-6

SB000018X00

4

QH10A

@

DMN53D0 LDW-7_SOT3 63-6

SB000018X00

+3VALW +3V_PCH_PRIM

1 2

RH89

@

0_1206_5 %

+3V_PCH_PRIM

1 2

@

RH162 0_ 0402_5%

+3VALW_DSW

+3VALW_DSW +3V_PCH_P RIM

0.1U_0402_10V6K

1

CH34

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

0.1U_0402_10V6K

1U_0402_6.3V6K

1

CH30

CH31

Close to UC1.AY8

2

2016/01/06 2017/01/06

RH736 0_0402_5 %@

8/17 separate +1.8V_PRIM and +1.8V_PHVLDO

1 2

RH143 0_0402_5 %@

RH150 0_0402_5 %@

1

0.1U_0402 _10V6K CH33

2

Close to UC1.AE35

Compal Secret Data

Deciphered Date

+3V_PCH_PRIM

+1.8V_PRIM

D

+3V_1.8V_PGPPA

12

@

1 2

CH63 1P_04 02_50V8

+3V_PCH_PRIM+3V_PCH_PRIM

1

0.1U_0402 _10V6K

@

CH32

2

Close to UC1.AC35

Compal Electronics, Inc.

Title

Size Document Numb er Re v

Dat e: Sheet of

Compal Electronics, Inc.

PCH (6/7) POWER

LA-F611P

E

21 78Thursday, March 22, 20 18

0.3

5

Main Func = PCH

4

3

2

1

D D

CNP-H

UH1I

A2

VSS

A28

VSS

A3

VSS

A33

VSS

A37

VSS

A4

VSS

A45

VSS

A46

VSS

A47

VSS

A48

VSS

A5

VSS

A8

VSS

AA19

VSS

AA20

VSS

AA25

VSS

AA27

VSS

AA28

VSS

AA30

VSS

AA31

VSS

AA49

VSS

AA5

VSS

AB19

VSS

AB25

VSS

AB31

VSS

AC12

VSS

AC17

VSS

AC33

C C

B B

AC38

AC46

AD19

AD22 AD25 AD49 AE12 AE33 AE38

AE46

AF22 AF25 AF28

AG22 AG23 AG25 AG27 AG28 AG30 AG49 AH12 AH17 AH33 AH38

AJ19 AJ20 AJ25 AJ27 AJ28 AJ30

AJ31 AK19 AK20 AK25 AK27 AK28 AK30 AK31

AK46

AC4

AD1

AD2

AE4

AG1

AK4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

9 OF 13

VSS

CNP-H_BGA874

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL12 AL17 AL21 AL24 AL26 AL29 AL33 AL38 AM1 AM18 AM32 AM49 AN12 AN16 AN34 AN38 AP4 AP46 AR12 AR16 AR34 AR38 AT1 AT16 AT18 AT21 AT24 AT26 AT29 AT32 AT34 AT45 AV11 AV39 AW10 AW4 AW40 AW46 B47 B48 B49 BA12 BA14 BA44 BA5 BA6 BB41 BB43 BB9 BC10 BC13 BC15 BC19 BC24 BC26 BC31 BC35 BC40 BC45 BC8 BD43 BE44 BF1 BF2 BF3 BF48 BF49 BG17 BG2 BG22 BG25 BG28

BG33 BG37

BG48

BG3

BG4

M16 M18 M21

C12 C25 C30

C4

C48

C5 D12 D16 D17 D30 D33

D8 E10 E13 E15 E17 E19 E22 E24 E26 E31 E33 E35 E40 E42

E8

F41 F43 F47

G44

G6

H8

J10 J26 J29

J4

J40 J46 J47 J48

J9 K11 K39

CNP-H

UH1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

12 OF 13

VSS

CNP-H_BGA874

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M24 M32 M34 M49 M5 N12 N16 N34 N35 N37 N38 P26 P29 P4 P46 R12 R16 R26 R29 R3 R34 R38 R4 T17 T18 T32 T4 T49 T5 T7 U12 U15 U17 U21 U24 U33 U38 V20 V22 V4 V46 W25 W27 W28 W30 Y10 Y12 Y17 Y33 Y38 Y9

CNP-H

UH1J

RSVD7 RSVD8 RSVD6 RSVD5

RSVD3 RSVD4

RSVD2 RSVD1

PREQ#

PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BGA874

Y14 Y15 U37 U35

N32 R32

AH15 AH14

To b e confirm

XDP_PREQ#

AL2

XDP_PRDY#

AM5

CPU_XDP_TRS T#

AM4

PCH_TRIGOUT PCH_TRIGOUT_R

AK3

CPU_TRIGOUT_R

AK2

TH1TP@ TH2TP@ TH3TP@ TH4TP@

TH5TP@ TH6TP@

TH7TP@ TH8TP@

1 2

RH665 30_0402_5%

XDP_PREQ# 10,38 XDP_PRDY# 10,38 CPU_XDP_TRS T# 10,38

PCH_TRIGOUT_R 13 CPU_TRIGOUT_R 13

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date : Sh eet of

2

Date : Sh eet of

Compal Electronics, Inc.

PCH (7/7) VSS

LA-F611P

1

0.3

22 78Thursday, March 22, 2018

0.3

5

Main Func = TPM

D D

C C

TPM@, cTPM@

+3V_PCH_PRIM

1 2

TPM@

RTPM9 10K_0402_5%

SIO_SLP_S0#18,26

PCH_SPI_SO_R17

PCH_SPI_SI_R17,38

PCH_SPI_CLK_R17

PCH_SPI_CS2#17

PLTRST#17,26,33,34,35,41,48

4

UTPM1

S IC NPCT750JAAYX QFN 32P TPM

TPM_PIRQ#

750@

RTPM11 0_0402_5%

650@

RTPM12 0_0402_5%

1 2

RTPM1 33_0402_5%

TPM@

1 2

RTPM2 33_0402_5%

TPM@

TPM_PIRQ#17

1 2

RTPM3 33_0402_5%

TPM@

10K_0402_5%

SA0000AQ200

750@

12

PCH_SPI_SO_TPM PCH_SPI_SI_TPM TPM_PIRQ#

PCH_SPI_CLK_TPM

12

RTPM4

650@

3

UTPM1

SA00008EL90

650@

S IC NPCT650VBBYX QFN 32P TPM

UTPM1

29

GPIO0/SDA

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCLK/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET #

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT650VB2YX_QFN32_5X5

@

VSB

VDD1 VHIO1 VHIO2

NC1 NC2 NC3 NC4 NC5 NC6 NC7

GND1 GND2 GND3 GND4 PGND

Reserved

1

8 14 22

2 7 10 11 25 26 31

9 16 23 32 33 12

CTPM1

0.1U_0402_16V7K

TPM@

Place CTPM1,CTPM2 as close as UTPM.1

1

CTPM2 10U_0402_6.3V6M

TPM@

2

RTPM8 0_0402_5%

RTPM10 0_0402_5%

0.1U_0402_10V7K

CTPM7

1

2

CTPM6

1

2

TPM@

2

1 2

RTPM7 0_0402_5%@

1 2

RTPM6 0_0402_5%

TPM@

12

+3VS

12

@

1

2

10U_0402_6.3V6M

+3V_PCH_PRIM

CTPM5

CTPM3, CTPM4: colse to Pin8

TPM@

1

+3VALW+3VS

+3VS

10U_0402_6.3V6M

0.1U_0402_10V7K CTPM4

CTPM3

1

2

TPM@

UTPM1 place colse to UH4

NPCT650:TPM@/650@/650@750@ NPCT750:TPM@/750@/650@750@ ChinaTPM:TPM@/cTPM@

CTPM5, CTPM6: colse to Pin14 CTPM7: colse to Pin22

SW TPM:fTPM@

Main Func = RTC

B B

A A

5

GEN9@

+RTC_VCC +3VLP

R1

12

R2 10M_0402_5%

1K_0402_5%

RTC_PWR

12

2

G

D

S

Q1 2N7002K_SOT23-3

MAIN@

13

4

D1

2

anode

cathode

3

anode

BAS40C_SOT23-3

MAIN@

0.47U_0402_6.3V6K

+RTC_CELL

1

C1

@

RTC_DET# 20

1

2

1U_0402_6.3V6K

12

C59

GEN9@

L2N7002WT1G_SC-70-3

Q25

GEN9_M@

10K_0402_5%

12

R73

GEN9@

D7

2 1

2

G

12

RB751S40T1G_SOD523-2

R78

1 2

1M_0402_5%

22P_0402_50V8J

C60

13

D

S

GEN9@

Security Classification

2016/01/06 2017/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Q26

LP2301ALT1G_SOT23-3

123

D

G

GEN9_M@

GEN9@

100K_0402_5%

1 2

2

GEN9_M@

S

+RTC_CELL+RTC_CELL_PCH

RTCRST_ON

0.1U_0402_25V6

R79

GEN9@

C61

12

@

Compal Electronics, Inc.

Title

Size

Document Number R ev

Date : Sheet o f

Compal Electronics, Inc.

TPM/RTC/Screw Holes

LA-F611P

RTCRST_ON 18,26

1

0.3

23 78Thursday, March 22, 2018

+5V_PVDD

@

PCH_AZ_CODEC_BITCLK

RA43

@EMI@

33P_0402_50V8J

CA38

@EMI@

5

CA1

12

10U_0603_10V6M

Layout Note:

Close pin39

+3V_DVDD

2

CA5

1

10U_0603_6.3V6M

EMI@, RF@, @EMI@, @ESD@, @RF@

CA2

CA3

12

.1U_0402_16V7K

10U_0603_10V6M

Layout Note:

Close pin34

CA6

Close pin8

.1U_0402_16V7K

CA4

1

2

.1U_0402_16V7K

1

2

1

2

Main Func = Audio

+5VS

2A

1 2

RA1 0_0805_5%

change to shortpad 11/23

D D

+3VS

25mA

1 2

RA2 0_0402_5%

change to shortpad 11/23

C C

33_0402_5%

1 2

RA43,CA38: close to UA1.6

+3V_DVDD

RA3 100K_0402_5%

12

moa t

B B

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

AUD_SPK_R+ AUD_SPK_RAUD_SPK_L+ AUD_SPK_L-

A A

AUD_SENSE_A

1

CA7

@

.1U_0402_16V7K

2

AUD_AGND

1 2

RA13 BLM15PD800SN1D_2PEMI_M@

1 2

RA14 BLM15PD800SN1D_2PEMI_M@

1 2

RA15 BLM15PD800SN1D_2PEMI_M@

1 2

RA16 BLM15PD800SN1D_2PEMI_M@

1

CA28

CA27

2

EMI@

1000P_0402_50V7K

1

CA30

CA29

2

EMI@

1000P_0402_50V7K

4

DMIC_DATA_EDP29

DMIC_CLK_EDP29

1

CA40 10P_0402_50V8J

@RF@

2

10U_0603_6.3V6M

PCH_AZ_CODEC_SYNC18 PCH_AZ_CODEC_BITCLK18 PCH_AZ_CODEC_SDOUT18

PCH_AZ_CODEC_SDIN018

+3V_DVDD

EC_MUTE#26

AUD_AGND

Layout Note: Speaker trace width >40mil @ 2W4ohm speaker power

JACK_PLUG25

1 2

RA7 33_0402_5%

1 2

@

RA9 0_0402_5%

1 2

@

RA8 100K_0402_5%

1 2

RA41 100K_0402_5%

1 2

CA20 10U _0603_6.3V6M

1 2

CA21 10U _0603_6.3V6M

1 2

CA22 10U _0603_6.3V6M

1 2

RA10 200K_0402_1%

Layout Note: Place close t o Pin 12

Speaker

AUD_SPK_R+_C AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C

DA1

1000P_0402_50V7K

2

3

1

@ESD@

2

3

DA2

1

@ESD@

L03ESDL5V0CC3-2_SOT23-3

1 2 3 4 5 6

L03ESDL5V0CC3-2_SOT23-3

1 2

RA42 33_0402_5%

1 2

L5 BLM15PX221SN1D_2P

CA9,L5 place colse to UA1.3

1

CA9

6.8P_0402_50V

@RF@

2

+3V_DVDD

1

CA15

2

HDA_CODEC_SDIN0

DMIC_DATA DMIC_CLK

LDO1_CAP LDO2_CAP LDO3_CAP

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

AUD_SENSE_A

JSPK1

1 2 3 4 G1 G2

ACES_50224-00401-001

CONN@ SP02000GC10

EMI_M@

1

CA16 .1U_0402_16V7K

2

3

UA1

9

SYNC

5

BIT-CLK

4

SDATA-OUT

7

SDATA-IN

10

DC_DET

2

GPIO0/DMIC-DATA12

3

GPIO1/DMIC-CLK

40

PDB

21

LDO1-CAP

32

LDO2-CAP

6

LDO3-CAP

35

SPK-OUT-LP

36

SPK-OUT-LN

37

SPK-OUT-RN

38

SPK-OUT-RP

12

HP/LINE1_JD1

ALC3204-CG_MQFN40_5X5

CONN Pin

Pin1

Pin2

Pin3

Pin4

+5V_PVDD

1

8

DVDD

DVDD-IO

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

DMIC_DATA

DMIC_CLK

34

PVDD1

+5V_AVDD

39

PVDD2

20

AVDD1

29

33

AVDD2

CPVDD

LINE1-VREFO-L

MIC2-VREFO

MIC2-L/RING2

MIC2-R/SLEEVE

HP-OUT-R

THERMAL_PAD

SPKR18

BEEP26

+1.8V_AVDD

VREF

VD33STB

CPVEE

MIC2-CAP

LINE1-L LINE1-R PCBEEP

HP-OUT-L

AVSS1 AVSS2

2

moa t

+1.8V_PRIM

RA4 0_0603_1%

1

12

CA10

CA11

2

+1.8V_CPVDD

+LINE1_VREFO_L

24

23

AUD_VREF

22 28

CBN

30

CBP

V3D3_STB

16

27

CPVEE

13 14

MIC_CAP

15

18 17

AUD_PC_BEEP

11 25 26

19 31 41

Place close to Pin 26

10U_0603_10V6M

.1U_0402_16V7K

AUD_AGND

CLOSE TO UA1

+5V_PVDD +3V_DVDD +5V_AVDD + 1.8V_CPVDD

68P_0201_50V8J

CA43

1

RF@

2

+MIC2-VREFO

1 2

CA23 2.2U_0603_6.3V6K

1 2

CA24 2.2U_0603_6.3V6K

1 2

CA25 1U_0603_16V7

1 2

CA26 10U_0603_6.3V6M

AUD_AGND

+5VS+5V_AVDD

12

@

change to shortpad 11/23 change to shortpad 11/23

10P_0201_50V8J

1

2

10 mils 10 mils

RING2 25 SLEEVE 25

LINE1_L 25 LINE1_R 25

AUD_HP1_JACK_L 25 AUD_HP1_JACK_R 25

10P_0201_50V8J

68P_0201_50V8J

CA44

1

CA47

RF@

CA48

RF@

2

RF@

AUD_AGND

moa t

1 2

RA11 0_0402_5%@

1 2

@

RA12 0_0402_5%

change to shortpad 11/23

Layout Note: Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp w ill be better. Add 2 vias (>0 .5A) when trace layer change .

AUD_AGND

0.1U_0402_25V6

1

CA52

CA53

2

EMI@

+3VS

68P_0201_50V8J

CA45

1

RF@

2

0.1U_0402_25V6

1

CA51

2

EMI@

QA1

LN2306LT1G_SOT23-3

MAIN@

D

1 3

2

68P_0201_50V8J

10P_0201_50V8J

1

CA49

2

RF@

+RTC_CELL

+3VALW

S

G

10P_0201_50V8J

CA46

1

RF@

2

RA17 0_0402_5%@ RA18 0_0402_5%@

AUD_AGND

RA22 0_0805_5%

AUD_AGND

1

2

1

moa t

+1.8V_AVDD

1 2

@

RA5 0_0402_5%

1 2

RA6 0_0402_5%

change to shortpad 11/23

CA50

RF@

@

AUD_AGND

+1.8V_CPVDD

2

CA12

1

2

CA13

1

moa t

change to shortpad 11/23

1 2 1 2

change to shortpad 11/23

@

1 2

Layout Note:

Tied at point only under Codec or near the Codec

Close pin33

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

CA14

Close pin29

.1U_0402_16V7K

Place on the moat between GND & GNDA.

DA3

2

3

BAT54CW_SOT323-3

1

1 2

RA23 1K_0402_5%

1 2

CA31 0.1U_0402_16V7K

12

RA24 10K_0402_5%

AUD_PC_BEEPAUD_PC_BEEP_C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

Audio Codec ALC3204

Document Number Re v

LA-F611P

1

24 78T hursday, March 22, 2018

0.3

Dell Latitude G3 3579 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual