Dell Latitude E7470 Schematic
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : AAZ60
PCB NO : DAA0009Y000
BOM P/N :
GPIO MAP: Gen7 GPIO Master_1127
Beaver Creek 14" UMA
Skylake U
2 2
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
3 3
TCM@ : TPM & China TPM select
2015-09-25
REV : 1.0 (A00)
CT3@ : For 2+3 CPU HW Part
U23E@ : For 2+3 CPU Power Part
MB PCB
Part Number
DAZ1DL00100
4 4
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: A00
PWB:
Description
PCB AAZ60 LA-C461P LS-C461P 02
Layout Dell logo
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-C461P
LA-C461P
LA-C461P
161Tuesday, October 13, 2015
161Tuesday, October 13, 2015
161Tuesday, October 13, 2015
E
1.0
1.0
1.0
A
www.vinafix.com
B
C
D
E
Reverse Type
Beaver Creek 14 Block Diagram
Memory BUS (DDR4)
1.2V DDR4 1866 MHz
1 1
EDP CONN
VGA
DP
DOCKING
CONN
2 2
DP
P38
DAI
LAN
P26
SYNATICS
VMM3320
mDP CONN
P25
DP DeMUX
PS8338
WIGIG DP
To M 2 W iG ig c ar d
P22
SATA1
DOCK_USB2.0[5]
DOCK_USB2.0[6]
DOCK_USB3.0[2]
PCIE[9] PCIE[5]
3 3
Intel Jacksonville
I219LM
Transf orm er
RJ45
P27
P27
P27
SD4.0
PCIE[3]
M.2,3042 Key B M.2,3030 Key A
WWAN/LTE/HCA
P29
USB2.0[10]
USB3.0[5]
eDP Lane x 4
HDMI 1.4b
CONN
P24
DP
Card reader
RTS5250
WLAN+BT/WIGIG
WIGIG_DP
DDI[1]
P22
DP DeMUX
PS8338
DDI[2]
P23
PCIE[10]
P28P28
PCIE[6]
SMSC SIO
P29 P31
USB2.0[8]
ECE5048
INTEL
SKYLAKE_U MCP
LPC
BC BUS
SMSC KBC
MEC5085
P32
PAG E 6 ~1 9
SPI
USB
HD Audio I/F
SATA[2]/PCIE[11],[12]
W25Q128FVSIQ
128M 4K sector
W25Q64CVSSIQ
(Reserve)
64M 4K sector
TPM1.2
NPCT650JA0YX
KB/TP CONN
FAN CONN
P39
P32
USB2.0[1]
P8
P8
P33
PI5USB2544
USB POWER SHARE
SATA/PCIE REPEATER X2
PS8558B
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
USB2.0[1]_PS
P36
HDA Codec
ALC3235
USB2.0[9]
USB2.0[2]
USB3.0[1]
USB2.0[4]
USB3.0[4]
USB2.0[3]
USB3.0[3]
LCD Touch
Camera
USB3.0 Conn
PS(RIGHT)
USB3.0 Conn
(REAR Right)
USB3.0 Conn
(Rear LEFT)
INT.Speaker
Universal Jack
P30
Dig. MIC
M.2 2280 Key M
P34 P35
HDD Conn
P26
P26
Tro ugh e DP Ca ble
P36
P37
P37
P30
P30
Tro ugh e DP Ca ble
LID SWITCH
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
P40
P33
P14
P11
DC/DC Interface
Smart Card
4 4
A
TDA8034HN
RFID/NFC
Fingerprint
CONN
SPI
SPI
USH TPM1.2
BCM58102
B
USB2.0[7]
USH board
P33
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
POWER ON/OFF
SW & LED
Block diagram
Block diagram
Block diagram
LA-C461P
LA-C461P
LA-C461P
E
261Tuesday, October 13, 2015
261Tuesday, October 13, 2015
261Tuesday, October 13, 2015
P41
P40
1.0
1.0
1.0
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M3
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW
LOW
LOW LOW LOW
LOW LOW LOW LOW
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH
HIGH HIGH
LOW
LOW
LOW
HIGH HIGH
HIGH
ALWAYS
SLP
PLANE
A#
HIGH
ON
HIGH
ON ON ON
ON ON
HIGH
ON ON
ON ON
LOW
ON
ON
M
PLANE
ON
OFF OFF OFF
OFF OFF OFF OFF
OFF OFF OFF OFF
RUN
SUS
PLANE
PLANE
ON ON ON
OFF
OFF
OFF
OFF
OFFLOW
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-6
PM TABLE
C C
power
plane
State
S0
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
+3.3V_CV2
+2.5V_MEM
+1.0V_VCC ST
ON ON
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.5V_RUN
(M-OFF)
+3.3V_M +3.3V_M
ON
+VCC_CORE
+VCC_GT
+1.0VS_VCCIO
+VCC_SA
ON
SSIC
SSIC-1
SSIC-2
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
SATA-0
SATA-1
SATA-1*
SATA-2
JUSB1-->Right
EDOCK PORT1
JUSB2-->Rear Lef t
JUSB3-->Rear Right
M2 3042(WWAN)USB3.0-5
NA
M.2 3042(HCA or QCA LTE)
NA
M.2 3030(WLAN)
M.2 3030(WIGIG)
NA
EDOCK E-SATA
LOM
Card Reader
M.2 2280 SSD(Reverse)
(PCIex2 or SATA)
USB PORT#DESTINATION
USH
DESTINATION
1
2
3
4
5
6
7
8
9
10
JUSB1-->Right
Camera
JUSB2-->Rear Lef t
JUSB3-->Rear Right
EDOCK PORT1
EDOCK PORT2
USH
M.2 3030(BT)
Tou c h S c re en
M2 3042(WWAN)
H
BIO
B B
A A
S3
S5 S4/AC
S5 S4/AC doesn't exist
ON
ON
ON
OFF
OFFOFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFFOFF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DIS CLOSE D TO ANY THI RD
PART Y W ITH OU T D ELL 'S EXP RE SS WR ITT EN CO NSE NT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-C461P
LA-C461P
LA-C461P
361Tuesday, October 1 3, 2015
361Tuesday, October 1 3, 2015
361Tuesday, October 1 3, 2015
1
1.0
1.0
1.0
5
RT8207M
(PU201)
ADAPTER
D D
SYX198D
(PU301)
4
SIO_SLP_S4#
SIO_SLP_SUS#
+1.2V_MEM
TPS22961
(UZ26)
+1.0V_PRIM
LDOIN
SIO_SLP_SUS#
SIO_SLP_S4#
3
RT8207
(PU201)
0.6V_DDR_VTT_ON
+VCC_SFR_OC
+0.6V_DDR_VTT
2
TPS22961
@(UZ20)
TPS22961
(UZ19)
TPS22961
(UZ21)
MPHYP_PWR_EN
SIO_SLP_S3#
SIO_SLP_S0#
SIO_SLP_S4#
+1.0V_MPHYGT
+1.0V_VCCSTG
+1.0V_VCCST
1
CPU PWR
PCH PWR
GT3 PWR
Peripheral Device PWR
TPS62134A
CHARGER
BQ24777
(PU801)
+PWR_SRC
SYX198C
(PU100)
ALWON
+5V_ALW
+5V_ALW2
BATTERY
C C
SYX198B
(PU100)
ALWON
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
ISL95857
(PU602)
IMVP_V R_ON
B B
IMVP_V R_ON
+VCC_GT+VCC_SA
IMVP_V R_ON
+VCC_CORE
AO6405
(QV1)
EN_INVPW R
+BL_PWR_SRC
TPS62134CRGT
(PU1200)
RUN_ON
+VCC_EDRAM
TPS62134CRGT
(PU1201)
SIO_SLP_SUS#
+VCC_EOPIO
(PU401)
TPS62134B
(PU402)
EM5209
(UZ4)
EM5209
(UZ5)
PI5USB2544
(UI3)
SY6288
(UI1)
SY6288
(UI2)
SY8032A
(PU501)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
EM5209
(UZ5)
AOZ1336
@(UZ8)
TPS22967
(UZ22)
RUN_ON
SIO_SLP_SUS#
RUN_ON
AUD_PWR_EN
USB_PWR_SHR_EN#
USB_PWR_EN1#
USB_PWR_EN2#
SIO_SLP_SUS#
SIO_SLP_LAN#
AUX_EN_W OWL
@SIO_SLP_WLAN#
SIO_SLP_SUS#
@PCH_ALW_ON
RUN_ON
3.3V_WWAN_ EN
AUD_PWR_EN
A_ON
3.3V_HDD _EN
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+5V_RUN
+5V_RUN_AUDIO
+5V_USB_CHG_PWR
+USB_LEFT_PW R
+USB_REAR_PWR
+1.8V_PRIM
+3.3V_LAN
+3.3V_W LAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_W WAN
+3.3V_RUN_AUDIO
+3.3V_M
+3.3V_HDD
TPS22961
@(UV28)
LP2301
(QV8)
EM5106VT
(UV29)
HUB_LP_EN
AP7175SP
(PU503)
APL5930
(PU502)
LP2301A
(QZ1)
3.3V_TS_EN
HUB_LP_EN
SIO_SLP_S4#
SIO_SLP_S3#
3.3V_CAM_EN#
+1.0V_RUN_VMM
+5V_TSP
+1.0V_RUN_VMM
+2.5V_MEM
+1.5V_RUN
+3.3V_CAM
TPS22967
3
(UZ18)
G524B1T11U
(UV24)
A A
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
CV2_ON
ENVCC_PC H
+3.3V_CV2
+LCDVDD
USH/B
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-C461P
LA-C461P
LA-C461P
461Tuesday, October 13, 2015
461Tuesday, October 13, 2015
461Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
R7
R8
D D
SKL-U
R9
W2
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
V3W3
B4
A3
B5
A4
1K
1K
DOCK_SMB _CLK
DOCK_SMB_DAT
+3.3V_ALW_PCH
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
499
499
4
1K
1K
+3.3V_ALW_PCH
2N7002
2N7002
+3.3V_ALW_PCH
28
31
LOM
3
2
1
2.2K
2.2K
+3.3V_RUN
202
200
202
200
DIMMA
DIMMB
53
51
XDP
2.2K
2.2K
+3.3V_ALW
127
129
Dock
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
@2.2K
@2.2K
A50
B53
USH_SMBCL K
USH_SMBDAT
B B
MEC 5085
1E
1E
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
7
6
BATTERY
CONN
2.2K
2.2K
+3.3V_CV2
M9
L9
USH
USH/B
A49
2B
B52
2B
B50
A47
B7
A7
B48
B49
CHARGER_SMB CLK
CHARGE R_SMBDAT
GPU_SMBDAT
GPU_SMBCLK
1G
1G
A A
2D
2D
2A
2A
5
2.2K
2.2K
2.2K
2.2K
4
+3.3V_ALW
+3.3V_RUN
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-C461P
LA-C461P
LA-C461P
561Tuesday, October 13, 2015
561Tuesday, October 13, 2015
561Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
C C
B B
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
+1.0VS_VCCIO
CPU_DP1_N0<22>
CPU_DP1_P0<22>
CPU_DP1_N1<22>
CPU_DP1_P1<22>
CPU_DP1_N2<22>
CPU_DP1_P2<22>
CPU_DP1_N3<22>
CPU_DP1_P3<22>
CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>
CPU_DP1_CTRL_CLK<22>
CPU_DP1_CTRL_DATA<22> CPU_DP1_HPD <22>
CPU_DP2_CTRL_CLK<23>
CPU_DP2_CTRL_DATA<23>
@
T120
PAD~D
1 2
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23 CPU_DP1_HPD
EDP_COMP
UC1A
CPU@
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DD PB_CTRLCLK
L12
GPP_E19/DD PB_CTRLDATA
N7
GPP_E20/DD PC_CTRLCLK
N8
GPP_E21/DD PC_CTRLDATA
N11
GPP_E22/DD PD_CTRLCLK
N12
GPP_E23/DD PD_CTRLDATA
E52
EDP_RCOMP
SKL-U_BGA1356
SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
UC1I
CPU@
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL-U_BGA1356
SKL-U
DDI
DISPLAY SIDEBANDS
SKL_ULT
EDP
1 OF 20
GPP_F13/EM MC_DATA0
GPP_F14/EM MC_DATA1
GPP_F15/EM MC_DATA2
GPP_F16/EM MC_DATA3
GPP_F17/EM MC_DATA4
GPP_F18/EM MC_DATA5
GPP_F19/EM MC_DATA6
GPP_F20/EM MC_DATA7
GPP_F21/EM MC_RCLK
EDP_DISP_UTIL
GPP_E13/DD PB_HPD0
GPP_E14/DD PC_HPD1
GPP_E15/DD PD_HPD2
GPP_E16/DD PE_HPD3
GPP_E17/ED P_HPD
EDP_BKLTEN
EDP_BKLTCTL
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLA SHTRIG
EMMC
GPP_F22/EM MC_CLK
GPP_F12/EM MC_CMD
EMMC_RCOMP
9 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_VDDEN
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
CSI2_COMP
RC3
EMMC_RCOMP
EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>
EDP_TXN2 <26>
EDP_TXP2 <26>
EDP_TXN3 <26>
EDP_TXP3 <26>
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
CPU_DP2_HPD <23>
EDP_HPD <26>
PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26,32>
1 2
100_0402_1%
1 2
RC4 200_0402_1%
Support QHD
EDP_AUXN <26>
EDP_AUXP <26>
CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>
@
T1
PAD~D
@
T2
PAD~D
CPU_DP1_AUXN
CPU_DP2_AUXN
CPU_DP2_AUXP
CPU_DP1_AUXP
EDP_HPD
CPU_DP2_HPD
+3.3V_RUN
12
RC179100K_0402_5%
12
RC181100K_0402_5%
12
RC182100K_0402_5%
12
RC180100K_0402_5%
12
RC1100K_0402_5%
12
RC312100K_0402_5%
12
@
RC242100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-C461P
LA-C461P
LA-C461P
661Tuesday, October 13, 2015
661Tuesday, October 13, 2015
661Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
DDR4, Ballout for side by side(Non-Interleave)
UC1B
CPU@
DDR_A_D0
AL71
DDR_A_D1
DDR_A_D2
D D
C C
B B
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
SKL-U
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2 OF 20
3
DDR_A_DQS#[0..7]<20>
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
DDR_A_CLK#0
AU53
DDR_A_CLK0
AT53
DDR_A_CLK#1
AU55
DDR_A_CLK1
AT55
DDR_A_CKE0
BA56
DDR_A_CKE1
BB56
DDR_A_CKE2
AW56
DDR_A_CKE3
AY56
DDR_A_CS#0
AU45
DDR_A_CS#1
AU43
DDR_A_ODT0
AT45
DDR_A_ODT1 DDR_B_ODT0
AT43
DDR_A_MA5
BA51
DDR_A_MA9
BB54
DDR_A_MA6
BA52
DDR_A_MA8
AY52
DDR_A_MA7
AW52
DDR_A_BG0
AY55
DDR_A_MA12
AW54
DDR_A_MA11
BA54
DDR_A_ACT#
BA55
DDR_A_BG1
AY54
DDR_A_MA13
AU46
DDR_A_MA15
AU48
DDR_A_MA14 DDR_B_MA15
AT46
DDR_A_MA16
AU50
DDR_A_BA0
AU52
DDR_A_MA2
AY51
DDR_A_BA1
AT48
DDR_A_MA10
AT50
DDR_A_MA1
BB50
DDR_A_MA0
AY50
DDR_A_MA3
BA50
DDR_A_MA4
BB52
DDR_A_DQS#0
AM70
DDR_A_DQS0
AM69
DDR_A_DQS#1
AT69
DDR_A_DQS1
AT70
DDR_A_DQS#4
BA64
DDR_A_DQS4
AY64
DDR_A_DQS#5
AY60
DDR_A_DQS5
BA60
DDR_B_DQS#0
BA38
DDR_B_DQS0
AY38
DDR_B_DQS#1
AY34
DDR_B_DQS1
BA34
DDR_B_DQS#4
BA30
DDR_B_DQS4
AY30
DDR_B_DQS#5
AY26
DDR_B_DQS5
BA26
DDR_A_ALERT#
AW50
DDR_A_PARITY
AT52
AY67
+DDR_VREF_A_DQ
AY68
BA67
AW67
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
PAD~D
@
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20>
+DDR_VREF_CA
@
PAD~D
+DDR_VREF_B_DQ
DDR_VTT_CTRL <20>
T3
T4
Check ODT schematic 0918
T132
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL-U_BGA1356
CPU@
2
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
3 OF 20
DDR_B_DQS#[0..7]<21>
DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_MA[0..16]<21>
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
1
DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>
DDR_B_CKE0 <21>
DDR_B_CKE1 <21>
@
T5
PAD~D
@
T6
PAD~D
DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>
Check ODT schematic 0918
DDR_B_BG0 <21>
DDR_B_ACT# <21>
DDR_B_BG1 <21>
DDR_B_BA0 <21>
DDR_B_BA1 <21>
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-C461P
LA-C461P
LA-C461P
761Tuesday, October 13, 2015
761Tuesday, October 13, 2015
761Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
1 2
PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>
D D
+3.3V_RUN
10K_0402_5%
12
RC267@
10K_0402_5%
12
RC268
DIMM Detect
HIGH
LOW
C C
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
1 2
1 2
B B
A A
RC10 1K_0402_1%
RC11 1K_0402_1%
ONE_DIMM#
1 DIMM
2 DIMM
RC28
@EMC@
33P_0402_50V8J
CC7
@EMC@
1 2
PCH_SPI_CS#2<33>
+3.3V_RUN
12
SIO_RCIN#<32>
+3.3V_RUN
33_0402_5%
RC29
@EMC@
1 2
33P_0402_50V8J
CC8
@EMC@
1 2
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
MEDIACARD_IRQ#<28>
PCH_CL_DATA1<29>
RC13
10K_0402_5%
IRQ_SERIRQ<31,32>
RC21 10K_0402_1%
+3.3V_SPI
@
@
@
RC37 0_0402_5%
@
RC39 33_0402_5%
RC42 0_0402_5%
@
RC43 33_0402_5%
@
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
TPM_PIRQ#<33>
PCH_CL_CLK1<29>
PCH_CL_RST1#<29>
1 2
RC30 1K_0402_5%
RC31 1K_0402_5%
RC316 1K_0402_5%
1 2
1 2
1 2
1 2
ONE_DIMM#
PCH_SPI_D2_R1
1 2
PCH_SPI_D3_R1
1 2
PCH_SPI_D3_R1
1 2
03/02:follow Intel MOW_2015WW 06
4
UC1E
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1 _CLK
M3
GPP_D2/SPI1 _MISO
J4
GPP_D3/SPI1 _MOSI
V1
GPP_D21/SP I1_IO2
V2
GPP_D22/SP I1_IO3
M1
GPP_D0/SPI1 _CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN #
AY11
GPP_A6/SER IRQ
SKL-U_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
CPU@
SPI - FLASH
SPI - TOUCH
C LINK
PCH_SPI_D1_R1<33>
PCH_SPI_D0_R1<33>
PCH_SPI_CLK_R1<33>
128Mb Flash ROM
1
/CS
2
IO1
3
IO2
4
GND
W25Q128FVSIQ_SO8
64Mb Flash ROM
@
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
UC5
UC6
SKL-U
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
VCC
IO3
CLK
IO0
VCC
/HOLD(IO3)
CLK
DI(IO0)
SMBUS, SMLINK
GPP_B23/SM L1ALERT#/PCHH OT#
LPC
GPP_A14/SU S_STAT#/ESPI_RE SET#
GPP_A9/CLK OUT_LPC0/ESPI_CL K
SOFTWARE TAA
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
RPC2
@
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
+3.3V_SPI
1 2
0.1U_0201_10V6K
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
@
1 2
0.1U_0201_10V6K
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
3
GPP_C0/SMB CLK
GPP_C1/SMB DATA
GPP_C2/SMB ALERT#
GPP_C3/SML 0CLK
GPP_C4/SML 0DATA
GPP_C5/SML 0ALERT#
GPP_C6/SML 1CLK
GPP_C7/SML 1DATA
GPP_A1/LAD 0/ESPI_IO0
GPP_A2/LAD 1/ESPI_IO1
GPP_A3/LAD 2/ESPI_IO2
GPP_A4/LAD 3/ESPI_IO3
GPP_A5/LFR AME#/ESPI_CS#
GPP_A10/CLK OUT_LPC1
GPP_A8/CLK RUN#
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
CC9
CC10
5 OF 20
+3.3V_SPI
MEM_SMBCLK
R7
MEM_SMBDATA
R8
PCH_SMB_ALERT#
R10
SML0_SMBCLK
R9
SML0_SMBDATA
W2
GPP_C5
W1
SML1_SMBCLK
W3
SML1_SMBDATA
V3
GPP_B23
AM7
LPC_AD0
AY13
LPC_AD1
BA13
LPC_AD2
BB13
LPC_AD3
AY12
LPC_FRAME#
BA12
SUS_STAT#
BA11
PCI_CLK_LPC0
AW9
PCI_CLK_LPC1
AY9
AW11
CLKRUN# <31,32>
RC32 0_0402_5%
@
RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%
+3.3V_ALW_PCH
RC41 0_0402_5%
Reserve
12
12
12
12
12
12
12
RC289 0_0402_5%
@
+3.3V_M
RC276 0_0402_5%
@
12
SML0_SMBCLK <27>
SML0_SMBDATA <27>
SML1_SMBCLK <32>
SML1_SMBDATA <32>
LPC_AD0 <31,32>
LPC_AD1 <31,32>
LPC_AD2 <31,32>
LPC_AD3 <31,32>
LPC_FRAME# <31,32>
1 2
RC16EMC@ 22_0402_5%
1 2
RC18EMC@ 22_0402_5%
1 2
RC22EMC@ 22_0402_5%
1 2
RC24EMC@ 22_0402_5%
CLK_PCI_5048
CLK_PCI_MEC
CLK_PCI_LPDEBUG
CLK_PCI_DOCK
Reserve for RF
PCH_SPI_CS#1_R1
PCH_SPI_CS#1
PCH_SPI_D0_R1
PCH_SPI_D0
PCH_SPI_D1_R1
PCH_SPI_D1
PCH_SPI_CLK_R1
PCH_SPI_CLK
PCH_SPI_CS#0_R1
PCH_SPI_CS#0
PCH_SPI_D2_R1
PCH_SPI_D2
PCH_SPI_D3_R1
PCH_SPI_D3
12
8/27 sch review
12
+3.3V_SPI_R
2
12
EMC@27P_0402_50V8J
CC3
12
@EMC@27P_0402_50V8J
CC4
12
EMC@27P_0402_50V8J
CC5
12
EMC@27P_0402_50V8J
CC6
E-T_6705K-Y20N-00L
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSPI1
CONN@
MEM_SMBCLK
MEM_SMBDATA
3 4
DMN65D8LDW-7_SOT363-6
CLK_PCI_5048 <31>
CLK_PCI_MEC <32>
CLK_PCI_LPDEBUG <32>
CLK_PCI_DOCK <38>
GPP_B23 GPP_B23_Q
SIO_SLP_A#<11,32>
SIO_SLP_SUS#<11,17,18,32,41,45,46,47,53>
1
+3.3V_RUN
2
1
6
5
DMN65D8LDW-7_SOT363-6
QC2B
DDR_XDP_WAN_SMBCLK <14,20,21>
QC2A
DDR_XDP_WAN_SMBDAT <14,20,21>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SUS_STAT#
Reserve
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
1 2
RC26@ 10K_0402_5%
11/2 0 IN TE L R EV IE W
1 2
RC19 499_0402_1%
@
1 2
RC20 499_0402_1%
@
8/5 CKLT0.9
1 2
RC27 8.2K_0402_5%
1 2
RC23 2.2K_0402_5%
TLS C ONFIDENTIALITY
RC25 10K_0402_5%@
ENABLE
DISABLE
1 2
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
GPP_C5
EC interfac e
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
+3.3V_RUN +3.3V_ALW_PCH
11/2 9 ,M OW f or D CI
1 2
@
RC339
0_0402_5%
@
RC340
0_0402_5%
150K_0402_5%
@
RC326
12
12
RC327
@
0_0402_5%
S
G
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
ESPI
LPC
12
D
13
QC3
@
L2N7002WT1G_SC-70-3
2
ENABLE D
DIABLED
+3.3V_RUN
12
RC3182.2K_0402_5%
12
RC3192.2K_0402_5%
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
02/25 ,INTEL mail for DCI
150K_0402_5%
RC317
1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-C461P
LA-C461P
LA-C461P
861Tuesday, October 13, 2015
861Tuesday, October 13, 2015
861Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
+3.3V_ALW_PCH
+3.3V_RUN
UC1F
CPU@
LPSS ISH
AN8
D D
C C
RC270 10K_0402_5%
RC282 100K_0402_5%
RC279 10K_0402_5%
RC292 10K_0402_5%
RC237 10K_0402_5%
+3.3V_ALW_PCH
RC283 10K_0402_5%
1 2
RC330 49.9K_0402_1%@
1 2
RC331 49.9K_0402_1%@
+3.3V_ALW_PCH
1 2
1 2
1 2
1 2
12
1 2
1 2
RC186 4.7K_0402_5%
@
3.3V_TS_EN
AUD_PWR_EN
HOST_SD_WP#
SIO_EXT_SCI#
SIO_EXT_WAKE#
UART2_RXD
UART2_TXD
NRB_BIT
Reserve
8/20
NRB_BIT
3.3V_TP_EN
Reserve
SIO_EXT_SCI#<32>
3.3V_TS_EN<26>
3.3V_HDD_EN<41>
UART0_TXD<32>
HOST_SD_WP#<28>
SIO_EXT_WAKE#<32>
I2C_1_SDA<39>
3.3V_HDD_EN
UART2_RXD
UART2_TXD
Reserve
I2C_1_SCL<39>
3.3V_TP_EN
GPP_B15/GSPI0 _CS#
AP7
GPP_B16/GSPI0 _CLK
AP8
GPP_B17/GSPI0 _MISO
AR7
GPP_B18/GSPI0 _MOSI
AM5
GPP_B19/GSPI1 _CS#
AN7
GPP_B20/GSPI1 _CLK
AP5
GPP_B21/GSPI1 _MISO
AN5
GPP_B22/GSPI1 _MOSI
AB1
GPP_C8/UAR T0_RXD
AB2
GPP_C9/UAR T0_TXD
W4
GPP_C10/UA RT0_RTS#
AB3
GPP_C11/UA RT0_CTS#
AD1
GPP_C20/UA RT2_RXD
AD2
GPP_C21/UA RT2_TXD
AD3
GPP_C22/UA RT2_RTS#
AD4
GPP_C23/UA RT2_CTS#
U7
GPP_C16/I2C 0_SDA
U6
GPP_C17/I2C 0_SCL
U8
GPP_C18/I2C 1_SDA
U9
GPP_C19/I2C 1_SCL
AH9
GPP_F4/I2C2_ SDA
AH10
GPP_F5/I2C2_ SCL
AH11
GPP_F6/I2C3_ SDA
AH12
GPP_F7/I2C3_ SCL
AF11
GPP_F8/I2C4_ SDA
AF12
GPP_F9/I2C4_ SCL
SKL-U_BGA1356
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
No REBOOT
REBOOT ENABLE
SKL-U
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_ I2C0_SDA
GPP_D6/ISH_ I2C0_SCL
GPP_D7/ISH_ I2C1_SDA
GPP_D8/ISH_ I2C1_SCL
GPP_F10/I2C5 _SDA/ISH_I2C2_SD A
GPP_F11/I2C5 _SCL/ISH_I2C2_SC L
GPP_D13/ISH _UART0_RXD/SM L0BDATA/I2C4B_ SDA
GPP_D14/ISH _UART0_TXD/SM L0BCLK/I2C4B_SC L
GPP_D15/ISH _UART0_RTS#
GPP_D16/ISH _UART0_CTS#/SM L0BALERT#
GPP_C12/UA RT1_RXD/ISH_UA RT1_RXD
GPP_C13/UA RT1_TXD/ISH_UA RT1_TXD
GPP_C14/UA RT1_RTS#/ISH_U ART1_RTS#
GPP_C15/UA RT1_CTS#/ISH_U ART1_CTS#
GPP_A18/ISH _GP0
GPP_A19/ISH _GP1
GPP_A20/ISH _GP2
GPP_A21/ISH _GP3
GPP_A22/ISH _GP4
GPP_A23/ISH _GP5
GPP_A12/BM _BUSY#/ISH_GP6
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
DIMM_TYPE
CLKDET#
TPM_TYPE
DIMM_TYPE
9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0 . 9
ISH_I2C2_SD A <29>
ISH_I2C2_SC L < 29>
ISH_UART0 _RXD <29>
ISH_UART0 _TXD < 29>
ISH_UART0 _RTS# <29>
ISH_UART0 _CTS# <29>
LCD_CBL_DET# <26>
@
T121
PAD~D
VMM3320_LPM_DIS <25>
KB_DET# <39>
AUD_PWR_EN <30>
IR_CAM_D ET# <26>
+3.3V_ALW_PCH
RC341
@
10K_0402_5%
1 2
WWAN
WLAN
8/21
KB_DET#
LCD_CBL_DET#
IR_CAM_D ET#
TPM_TYPE
1 2
RC288 10K_0402_5%
1 2
RC287 100K_0402_5%
1 2
RC345 100K_0402_5%
1 2
RC349 100_0402_1%TCM@
RC349
POP
DEPOP
+3.3V_RUN
China TPM
TPM
B B
+3.3V_ALW_PCH
12
RC184
@
8.2K_0402_5%
3.3V_HDD_EN
RC342
10K_0402_5%
1 2
DIMM TYPE
HIGH
DDR3L
LOW DDR4
BOOT BIOS Dest i nat i on(Bi t 10)
HIGH
LOW(DEFAULT)
A A
LPC
SPI
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-C461P
LA-C461P
LA-C461P
961Tuesday, October 13, 2015
961Tuesday, October 13, 2015
961Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
UC1H
CPU@
PCIE/USB3/SATA
D D
WWAN ----->
WWAN --->
WIGIG--->
C C
E DOCK ESATA--->
10/100/1G LAN --->
Card Reader --->
+3.3V_RUN
8/5 CKLT0.9
RC245 10K_0402_5%
M2 2280 SSD(Reverse) --->
B B
USB3_PRX_DTX_N5<29>
USB3_PRX_DTX_P5<29>
USB3_PTX_DRX_N5<29>
USB3_PTX_DRX_P5<29>
PCIE_PRX_DTX_N3<29>
PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>
PCIE_PRX_DTX_N5<29>
PCIE_PRX_DTX_P5<29>
PCIE_PTX_DRX_N5<29>
PCIE_PTX_DRX_P5<29>
PCIE_PRX_DTX_N6<29>
PCIE_PRX_DTX_P6<29>
PCIE_PTX_DRX_N6<29>
PCIE_PTX_DRX_P6<29>
SATA_PRX_DTX_N1<38>
SATA_PRX_DTX_P1<38>
SATA_PTX_DRX_N1<38>
SATA_PTX_DRX_P1<38>
PCIE_PRX_DTX_N9<27>
PCIE_PRX_DTX_P9<27>
PCIE_PTX_DRX_N9<27>
PCIE_PTX_DRX_P9<27>
PCIE_PRX_DTX_N10<28>
PCIE_PRX_DTX_P10<28>
PCIE_PTX_DRX_N10<28>
PCIE_PTX_DRX_P10<28>
1 2
RC45 100_0402_1%
1 2
PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>
PCIE_RCOMPN
PCIE_RCOMPP
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA #
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL-U_BGA1356
SKL-U
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB 2_OC0#
GPP_E10/US B2_OC1#
GPP_E11/US B2_OC2#
GPP_E12/US B2_OC3#
GPP_E4/DEV SLP0
GPP_E5/DEV SLP1
GPP_E6/DEV SLP2
GPP_E0/SAT AXPCIE0/SATAGP0
GPP_E1/SAT AXPCIE1/SATAGP1
GPP_E2/SAT AXPCIE2/SATAGP2
GPP_E8/SAT ALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
USB2_VBUSSENSE
AG4
A9
C9
D9
USB_OC3#
B9
J1
J2
J3
H2
SATAGP0
H3
SATAGP1
G4
H1
USBCOMP
USB2_ID
USB3_PRX_DTX_N1 <36>
USB3_PRX_DTX_P1 <36>
USB3_PTX_DRX_N1 <36>
USB3_PTX_DRX_P1 <36>
USB3_PRX_DTX_N2 <38>
USB3_PRX_DTX_P2 <38>
USB3_PTX_DRX_N2 <38>
USB3_PTX_DRX_P2 <38>
USB3_PRX_DTX_N3 <37>
USB3_PRX_DTX_P3 <37>
USB3_PTX_DRX_N3 <37>
USB3_PTX_DRX_P3 <37>
USB3_PRX_DTX_N4 <37>
USB3_PRX_DTX_P4 <37>
USB3_PTX_DRX_N4 <37>
USB3_PTX_DRX_P4 <37>
USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <26>
USB20_P2 <26>
USB20_N3 <37>
USB20_P3 <37>
USB20_N4 <37>
USB20_P4 <37>
USB20_N5 <38>
USB20_P5 <38>
USB20_N6 <38>
USB20_P6 <38>
USB20_N7 <33>
USB20_P7 <33>
USB20_N8 <29>
USB20_P8 <29>
USB20_N9 <26>
USB20_P9 <26>
USB20_N10 <29>
USB20_P10 <29>
1 2
RC44 113_0402_1%
1 2
RC337 0_0402_5%
@
1 2
RC338 1K_0402_5%
USB_OC0# <36>
USB_OC1# <37>
USB_OC2# <37>
Reserve
M2_DEVSLP <35>
Reserve
Reserve
IFDET_SAT A#_PCIE <12,34,3 5>
PCH_SATA_LED# <40>
-----> Ext USB3 Port 1 Charge(RIGHT)
-----> EDOCK
-----> Ext USB3 Port 2(REAR LEFT)
-----> Ext USB3 Port 3(REAR RIGHT)
-----> Ext USB Port 1 Charge(RIGHT)
-----> CameraWLAN --->
-----> Ext USB Port 2(REAR LEFT)
-----> Ext USB Port 3(REAR RIGHT)
-----> EDOCK PORT1
-----> EDOCK PORT2
-----> USH
-----> BT
-----> LCD Touch
-----> M2 3042(WWAN)
2/5 for DCI,#545659 SKL_PCH-LP EDS Rev1.2.
(Rev1.0 doesn’ t wit h bel ow not es)
8/19 for layout routing change
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
RPC3
4 5
3
2
1
10K_8P4R_5%
6
7
8
+3.3V_ALW_PCH
+3.3V_RUN
CAM_MIC_CBL_DET#<12,26>
A A
CAM_MIC_CBL_DET#
PCH_SATA_LED#
SATAGP0
SATAGP1
RPC4
4 5
3
2
1
10K_8P4R_5%
6
7
8
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-C461P
LA-C461P
LA-C461P
10 61Tuesday, October 13, 2015
10 61Tuesday, October 13, 2015
10 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
CLK_PCIE_N0<29>
WWAN
D D
WLAN--- >
WIGIG--->
SATA EXPRESS HDD--->
LAN--->
MMI --->
C C
11/2 0 IN TE L R EV IE W
+3.3V_LAN
1 2
RL70 10K_0402_5%
@
+3.3V_ALW_DSW
+1.0V_VCCST
+3.3V_ALW_PCH
B B
1 2
RC323 10K_0402_5%
1 2
RC71 1K_0402_5%
1 2
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
@
T9
PAD~D
H_CPUPWRGD H_VCCST_PWRGD
100P_0402_50V8J
12
12
CC300EMC@
ESD Request:place near CPU side
CLK_PCIE_P0<29>
CLKREQ_PCIE#0<29>
CLK_PCIE_N1<29>
CLK_PCIE_P1<29>
CLKREQ_PCIE#1<29>
CLK_PCIE_N2<29>
CLK_PCIE_P2<29>
CLKREQ_PCIE#2<29>
CLK_PCIE_N3<35>
CLK_PCIE_P3<35>
CLKREQ_PCIE#3<35>
CLK_PCIE_N4<27>
CLK_PCIE_P4<27>
CLKREQ_PCIE#4<27>
CLK_PCIE_N5<28>
CLK_PCIE_P5<28>
CLKREQ_PCIE#5<28>
LAN_WAKE#
H_VCCST_PWRGD
ME_SUS_PWR_ACK
H_VCCST_PWRGD<14,32>
100P_0402_50V8J
CC301EMC@
1 2
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_DSW
+3.3V_RUN
RC75 10K_0402_5%
RC189 10K_0402_5%
1 2
RC47 10K_0402_5%
1 2
RC50 10K_0402_5%
1 2
RC59 10K_0402_5%
1 2
RC51 10K_0402_5%
1 2
RC190 10K_0402_5%
PCH_PLTRST#
1 2
RC67 1K_0402_5%
1 2
RC225@ 8.2K_0402_5%
PCH_RSMRST#_Q<14,39>
1 2
1 2
RC77 1K_0402_5%@
1 2
RC78 60.4_0402_1%
RESET_OUT#<14,32>
PCH_PWROK<48>
PCH_DPWROK<32> POWER_SW#_MB<32,40>
ME_SUS_PWR_ACK<32>
PCH_PCIE_WAKE#<31,32>
PM_LANPHY_ENABLE<27>
3.3V_CAM_EN#<26>
UC7
TC7SH08FU_SSOP5~D
PCH_PCIE_WAKE#
ME_RESET#
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_Q
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD
SUSACK#<32>
LAN_WAKE#<27,32>
1 2
RC311 10K_0402_5%
8/28 schematic review
1
2
RC215
POP
NO Support Deep sleep
DE-POP
0.01UF_0402_25V7K
12
CC266
Support Deep sleep
1 2
RC215 0_0402_5%@
100K_0402_1%
RC220
XDP_DBRESET#<14>
XDP_DBRESET#
RC227@ 8.2K_0402_5%
PCH_DPWROK PCH_RSMRST#_Q
A A
1
2
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
5
4
UC1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRC CLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRC CLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRC CLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRC CLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRC CLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SR CCLKREQ5#
SKL-U_BGA1356
12
RC610_0402_5%
12
RC62 @0_0402_5%
12
RC64 @0_0402_5%
12
RC244 @0_0402_5%
+3.3V_ALW_PCH
5
P
B
PCH_PLTRST#_AND
4
O
A
G
3
UC1K
AN10
GPP_B13/PLT RST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SU SWARN#/SUSP WRDNACK
AP11
GPP_A15/SU SACK#
BB15
WAKE#
AM15
GPD2/LAN_W AKE#
AW17
GPD11/LANP HYPC
AT15
GPD7/RSVD
SKL-U_BGA1356
RC290 0_0402_5%
@
ME_RESET#
12
4
CPU@
@
12
RC65
@
100K_0402_5%
CPU@
1 2
+3.3V_RUN
5
1
P
B
2
A
G
74AHC1G09GW_TSSOP5
3
SKL_ULT
CLOCK SIGNALS
PLTRST_VMM2320# <25>
PLTRST_LAN# <27>
PLTRST_5048# <31>
PCH_PLTRST#_EC <32>
PCH_PLTRST#_AND <28,29,33,35>
SYSTEM POWER MANAGEMENT
SYS_RESET#_R
4
O
UC12@
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
SKL-U
GPP_B11/EXT _PWR_GATE#
1 2
RC224 1K_0402_5%
3
1 2
SUSCLK
RC48 1K_0402_5%@
CLK_ITPXDP_N
F43
CLK_ITPXDP_P
E43
XTAL24_IN
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST#
GPD8/SUSC LK
XTAL24_OUT
XCLK_BIASREF
CMOS1 must take care sh ort & touch risk on layout placement
PCH_PLTRST#
PCH_PLTRST#_AND
8/21 can change to 10K for merge to RP
GPP_B12/SLP _S0#
GPD4/SLP_S 3#
GPD5/SLP_S 4#
GPD10/SLP_S 5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_W LAN#
GPD6/SLP_A #
GPD3/PWR BTN#
GPD1/ACPR ESENT
GPD0/BATLOW #
GPP_A11/PM E#
INTRUDER #
GPP_B2/VRA LERT#
11 OF 20
+3.3V_RUN
12
RC291
10K_0402_5%
@
SYS_RESET#
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
RC60 0_0402_5%
@
@
SIO_SLP_LAN#
PCH_BATLOW#
AC_PRESENT
SIO_SLP_S0#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER #
AM10
AM11
VRALERT#
3
RC325 0_0402_5%
1 2
RC297 0_0402_5%
@
1 2
RC298 0_0402_5%
@
SUSCLK <29,35>
1 2
RC52 2.7K_0402_1%
1 2
@
RC324 59_0402_1%
546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0
1 2
RC56 20K_0402_5%
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5%
1 2
CC25 1U_0402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
12
12
1 2
RC344 10K_0402_5%
@
1 2
RC68 10K_0402_5%
@
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
SIO_SLP_S0# <17,33,46>
SIO_SLP_S3# <17,32,47>
SIO_SLP_S4# <17,32,44,54>
SIO_SLP_S5# <32>
SIO_SLP_SUS# <8,17,18,32,41,45,46,47,53>
SIO_SLP_LAN# <32,41>
SIO_SLP_WLAN# <31,41>
SIO_SLP_A# <8,32>
SIO_PWRBTN# <14,32>
AC_PRESENT <32>
PAD~D
MPHYP_PWR_EN <18,45>
connect to VCCMPHYGTAON_1P0 enable pin
+3.3V_ALW
+3.3V_ALW_DSW
SLP_S0# for support connect stand by mode
@
T115
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52
2
PLTRST_TPM# <33>
+3.3V_ALW_PCH
8/21 CRB1.0 change to 0603 1/10W
10/30 move to EC side
2
1M_0402_1%
RC46
XTAL24_IN
XTAL24_OUT XTAL24_OUT_R
PCH_RTCX1
PCH_RTCX2
+RTC_CELL
INTRUDER #
VRALERT#
1 2
RC69 1M_0402_5%
1 2
RC73 10K_0402_5%
SYS_RESET#
0.1U_0402_25V6
12
ESD Request:place near CPU side
1 2
1 2
RC295 0_0402_5%
@
For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MH z (30 Ohm ESR)
546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0
RC54
10M_0402_5%
1 2
1 2
RC296 0_0402_5%
@
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_DSW
+3.3V_ALW_DSW
@EMC@
CC302
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
CC21
1 2
3
1
PCH_RTCX2_R
YC2 c hange SJ1 0000LV 00 as main
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-C461P
LA-C461P
LA-C461P
15P_0402_50V8J
4
YC1
24MHZ_12PF_X3G024000DC1H
2
12
CC22
1 2
15P_0402_50V8J
CC23
1 2
15P_0402_50V8J
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_50506-01841-P01
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
CONN@
11 61Tuesday, October 13, 2015
11 61Tuesday, October 13, 2015
11 61Tuesday, October 13, 2015
JAPS1
1.0
1.0
1.0
5
+1.0V_VCCST
11/2 7 D G1 .0
1 2
RC79 49.9_0402_1%
@
1 2
RC80 1K_0402_5%
+1.0V_VCCSTG
8/19 DG0.9
1 2
RC83 1K_0402_5%
+3.3V_RUN
D D
+3.3V_RUN
+3.3V_ALW_PCH
C C
+3.3V_RUN
B B
+3.3V_ALW_PCH +3.3V_ALW_PCH
1 2
RC272 10K_0402_5%
RPC5
4 5
3
2
1
10K_8P4R_5%
1 2
RC346 10K_0402_5%
1 2
RC278 10K_0402_5%
1 2
RC183 8.2K_0402_5%@
H_CATERR#
H_THERMTRIP#
H_PROCHOT#
TOUCHPAD_INTR#
IFDET_SAT A#_PCIE
6
TOUCH_SCREEN_PD#
7
8
SIO_EXT_SMI#
CONTACTLESS_DET#
SPKR
HDA_SYNC_R<30>
HDA_BIT_CLK_R<30>
HDA_SDOUT_R<30>
22P_0402_50V8J
Close to RC93
H_PROCHOT#<32,48,50>
H_THERMTRIP#<20,21,32>
IFDET_SAT A#_PCIE <10,34,3 5>
RC92 33_0402_5%
RC93 33_0402_5%EMC@
RC94 33_0402_5%
ME_FWP
RC223 1K_0402_5%
HDA_RST#_R<30>
HDA_BIT_CLK_R
1
CC27
2
RC187 4.7K_0402_5%@
PECI_EC<32>
8/19 DG0.9
1 2
RC84 499_0402_1%
SIO_EXT_SMI#<32>
TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<39>
TOUCH_SCREEN_DET#<26>
12
RC88
1 2
1 2
1 2
1 2
1 2
RC95 33_0402_5%
SPKR<30>
HDA_SDOUT
1 2
XDP_OBS0_R<14>
XDP_OBS1_R<14>
@
T10
@
T11
12
RC89
49.9_0402_1%
HDA_SDIN0<30>
4
H_PROCHOT#_R
H_THERMTRIP#
PAD~D
PAD~D
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
12
RC90
49.9_0402_1%
49.9_0402_1%
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_RST#
H_CATERR#
XDP_OBS2_R
XDP_OBS3_R
EOPIO_RCOMP
12
RC91
49.9_0402_1%
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK10
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_ MCLK
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_ SFRM
AK6
GPP_F0/I2S2_ SCLK
AK9
GPP_F2/I2S2_ TXD
GPP_F3/I2S2_ RXD
H5
GPP_D19/DM IC_CLK0
D7
GPP_D20/DM IC_DATA0
D8
GPP_D17/DM IC_CLK1
C8
GPP_D18/DM IC_DATA1
AW5
GPP_B14/SPK R
SKL-U_BGA1356
UC1D
CPU@
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU _GP0
GPP_E7/CPU _GP1
GPP_B3/CPU _GP2
GPP_B4/CPU _GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOM P
OPC_RCOMP
SKL-U_BGA1356
CPU@
AUDIO
CPU MISC
SKL-U
SKL-U
3
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
SDIO/SDXC
GPP_A17/SD _PWR_EN#/ISH _GP7
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
RC87 1K_0402_5%@
GPP_G0/SD_C MD
GPP_G1/SD_D ATA0
GPP_G2/SD_D ATA1
GPP_G3/SD_D ATA2
GPP_G4/SD_D ATA3
GPP_G5/SD_C D#
GPP_G6/SD_C LK
GPP_G7/SD_W P
GPP_A16/SD _1P8_SEL
SD_RCOMP
GPP_F23
CPU_XDP_TCLK XDP_JTAGX
RC328 0_0402_5%
@
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
1 2
AB11
AB13
AB12
W12
CONTACTLESS_DET#
W11
W10
W8
W7
BA9
BB9
SD_RCOMP
AB7
AF13
7 OF 20
12
2/5 for DCI
RC86 51_0402_5%@
+1.0V_VCCSTG
CAM_MIC_CBL_DET# <10,26>
1 2
RC96 200_0402_1%
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
0.1U_0402_25V6
@EMC@
12
CC303
2
PCH_JTAG_TDI
51_0402_5%
PCH_JTAG_TDO
100_0402_1%
PCH_JTAG_TMS
51_0402_5%
12
Service Mode Switch:
Add a switch to ME_FWP sign al to unlo ck the ME region and
allow the ent i re r egi on of t he SPI f l ash to be updated using FPT.
+3.3V_ALW_PCH
12
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENAB LE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CONTACTLESS_DET# <33>
0.1U_0402_25V6
@EMC@
12
CC304
ESD request,Place near CPU side.
12
RC81
12
RC82
12
RC130
RC221 0_0402_5%
@
PT,ST pop RC222 and SW1; MP pop RC221
RC222
@
1K_0402_5%
ME_FWP_EC<31>
0.1U_0402_25V6
@EMC@
12
CC305
+1.0V_VCCSTG
ME_FWPME_FWP_EC
12
SW1
@
1
A
2
ME_FWP
12
B
3
C
4
G1
5
G2
SS3-CMFTQR9_3P
H_THERMTRIP# H_PROCHOT#
0.1U_0402_25V6
@EMC@
12
CC312
1
0.1U_0402_25V6
@EMC@
CC310
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
DISABLE
ENABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-C461P
LA-C461P
LA-C461P
12 61Tuesday, October 13, 2015
12 61Tuesday, October 13, 2015
12 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
1 2
RC113 10K_0402_1%@
Stall reset sequence
HIGH(DEFAULT)
LOW
C C
1 2
RC109 1K_0402_5%
eDP enable
HIGH(DEFAULT)
LOW
B B
CFG0
No stall(Normal Operat i on)
stall
CFG4
Disabled
Enabled
+1.0V_PRIM_XDP
1 2
RC112 10K_0402_1%@
1 2
RC110 10K_0402_1%@
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
UC1S
CPU@
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL-U_BGA1356
RESERVED SIGNALS -1
SKL-U
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20
SPARE
SKL-U
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
E3
C11
B11
A11
D12
C12
F52
UC1T
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
@
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T128
PAD~D
@
T129
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
LPM_ZVM_N <53>
@
T113
PAD~D
@
T114
PAD~D
MSM_N <53>
1 2
RC120 100K_0402_5%
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0
1/5 2014W W52 M OW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%
@
+VCC_1P8+1.8V_PRIM
ZVM# for SKYLA KE-U 2+3e
MSM# for SKYLAKE-U 2+3e
+1.0V_VCCST
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
1
2
@
RSVD_H11
SKL-U_BGA1356
CC222
1U_0402_6.3V6K
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-C461P
LA-C461P
LA-C461P
13 61Tuesday, October 13, 2015
13 61Tuesday, October 13, 2015
13 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
CC29
5
+1.0V_PRIM_XDP
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124
CXDP@ 1K_0402_5%
PCH_SPI_DO_XDP<8>
RESET_OUT#<11,32>
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 n eed to close to JCPU1
1 2
1 2
FIVR_EN
CFG0
CXDP@
1 2
RC217 0_0402_5%
@
1 2
RC126 1K_0402_5%
@
1 2
RC128 0_0402_5%
1 2
RC129 0_0402_5%
@
DDR_XDP_WAN_SMBDAT<8,20,21>
DDR_XDP_WAN_SMBCLK<8,20,21>
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,32>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM
1 2
RC216 0_0603_1%
@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
@
CC28
1
1
2
2
D D
Place near
JXDP1
H_VCCST_PWRGD<11,32>
PCH_RSMRST#_Q<11,39>
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
4
XDP_PRSNT_PIN1
1 2
RC121 1K_0402_5%
1 2
RC122 0_0402_5%@
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A 0
11
OBSDATA_A 1
13
GND4
15
OBSDATA_A 2
17
OBSDATA_A 3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B 0
29
OBSDATA_B 1
31
GND10
33
OBSDATA_B 2
35
OBSDATA_B 3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
CXDP@
CFG3
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C 0
OBSDATA_C 1
GND5
OBSDATA_C 2
OBSDATA_C 3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D 0
OBSDATA_D 1
GND11
OBSDATA_D 2
OBSDATA_D 3
GND13
ITPCLK#/HOOK 5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
TD0
TDI
+1.0V_PRIM_XDP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
3
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13 >
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
2
+3.3V_RUN
CC30
1 2
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<31,32>
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
GND
GND PAD
1
3
1B
6
2B
8
3B
11
4B
7
15
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
+1.0VS_VCCIO
C C
B B
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
1 2
RC132 150_0402_5%
1 2
RC218 150_0402_5%
@
1 2
RC219 10K_0402_5%
@
1 2
RC137
1 2
RC138
@
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
1K_0402_5%
CPU_XDP_PREQ#
51_0402_5%
11/0 6: CR B is NC
CKLT0.9
+3.3V_ALW_PCH
0.1U_0402_25V6
CC33@
Place near JXDP1.47
12
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
12
9/1 follow SPI PWR rail
Place near JXDP1.48
XDP_DBRESET#
CPU_XDP_TMS
51_0402_5%
+3.3V_ALW_DSW
0.1U_0402_25V6
CC32
CXDP@
12
SIO_PWRBTN#
12
12
1.5K_0402_5%
RC241
@
0.1U_0402_25V6
CC269
@
EDS0.7
Place near JXDP1.41
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
0.1U_0402_25V6
@EMC@
12
CC306
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
12
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TRST#
CPU_XDP_TCLK
XDP_TMS
TDI_XDP
TDO_XDP
9/1 correct typo netname
0.1U_0402_25V6
@EMC@
CC307
51_0402_5%
100_0402_1%
51_0402_5%
51_0402_5%
1 2
RC228 0_0402_5%
@
1 2
RC229 0_0402_5%
@
1 2
RC230 0_0402_5%
@
0.1U_0402_25V6
@EMC@
12
CC308
12
RC131
12
RC134
12
RC135
12
RC136@
12
RC139
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-C461P
LA-C461P
LA-C461P
14 61Tuesday, October 13, 2015
14 61Tuesday, October 13, 2015
14 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
+VCC_EDRAM
+1.8V_PRIM
+VCC_EOPIO
C C
VCCOPC,VCC OPC_1P8,VCCEOP IO f or SKYLAKE-U 2+3 e
(w/ on package cache)
PAD~D
1 2
RC232 0_0603_5%@
VCC_EDRAM_SENSE<53>
VSS_EDRAM_SENSE<53>
VCCEOPIO_SENSE<53>
VSSEOPIO_SENSE<53>
+VCC_EDRAM +VCC_EOPIO
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
+1.8V_PRIM_R
1
1
CC180
2
CC183
2
GT3@
GT3@
10U_0402_6.3V6M
1U_0402_6.3V6K
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
SKL-U_BGA1356
1
CC289
2
GT3@
1U_0402_6.3V6K
UC1L
CPU@
1
CC290
2
GT3@
CPU POW ER 1 OF 4
1
CC291
2
GT3@
1U_0402_6.3V6K
SKL-U
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
1
1
CC292
CC293
2
2
GT3@
1U_0402_6.3V6K
GT3@
1U_0402_6.3V6K
1U_0402_6.3V6K
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
VCCSENSE
E33
VSSSENSE
H_CPU_SVIDALRT#
B63
A63
VIDSCLK
D64
VIDSOUT
G20
+1.0V_VCCSTG_R
1
2
CC184
GT3@
10U_0402_6.3V6M
+VCC_CORE
VIDSCLK <48>
1 2
RC143 0_0603_5%@
1
CC187
2
GT3@
10U_0402_6.3V6M
12
12
RC140
100_0402_1%
RC141
100_0402_1%
VCCSENSE <48>
VSSSENSE <48>
+1.0V_VCCSTG
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on seco ndary side, underneath the package
Component placement order:
Package edge > 040 2 caps > 0805 ca ps > Bul k caps >Power source
ESD Request
+VCC_CORE +1.2V_MEM
+1.0V_PRIM +VCC_CORE
CC282
CC283
CC284
CC285
CC286
CC287
1 2
1 2
1 2
1 2
1 2
1 2
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
+3.3V_RUN+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+1.2V_MEM+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+3.3V_RUN+VCC_CORE
22U_0603_6.3V6M@EMC@
INTEL PDG 1.0
B B
8/21 CR B1.0 , DG0.9
SVID ALERT
VIDALERT_N<48>
SVID DATA
A A
VIDSOUT<48>
+1.0V_VCCST
12
+1.0V_VCCST
12
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-C461P
LA-C461P
LA-C461P
15 61Tuesday, October 13, 2015
15 61Tuesday, October 13, 2015
15 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
D D
C C
+VCC_GT
12
RC161
100_0402_1%
VCC_GT_SENSE<48>
VSS_GT_SENSE<48>
B B
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
A48
A53
A58
A62
A66
K48
K50
K52
K53
K55
K56
K58
K60
M62
N63
N64
N66
N67
N69
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKL-U_BGA1356
CPU@
CPU POW ER 2 OF 4
SKL-U
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
VCCGTX for SKYLAKE-U 2+3e
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GT
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-C461P
LA-C461P
LA-C461P
16 61Tuesday, October 13, 2015
16 61Tuesday, October 13, 2015
16 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
4
3
2
1
+5V_ALW
CZ115
@
1 2
4
O
CC182
@
CC253
+1.2V_MEM
1 2
@
RZ119 0_0402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
UC14
INTEL PDG 1.0
1
1
2
2
CC185
CC186
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
CC250
1U_0402_6.3V6K
SIO_SLP_S0#
CC251
SIO_SLP_S3#
1U_0402_6.3V6K
AND
+VCCPLL_OC source
8/14 CRB1.0
1 2
RC231 0_0402_5%
@
D D
BSC
1
2
BSC
1
2
CC256
@
1U_0402_6.3V6K
C C
B B
PSC
1
CC174
2
@
@
10U_0402_6.3V6M
1
1
2
2
CC257
@
1U_0402_6.3V6K
1
1
2
1
2
1U_0402_6.3V6K
CC176
2
10U_0402_6.3V6M
1
2
CC255
@
1U_0402_6.3V6K
+1.0V_VCCST
CC177
22U_0603_6.3V6M
1
2
CC175
10U_0402_6.3V6M
CC254
@
+1.2V_MEM+1.2V_MEM_CPUCLK
VDDQ: 8.45A
DG0.9
1
1
CC179
CC178
2
2
10U_0402_6.3V6M
22U_0603_6.3V6M
1
2
1U_0402_6.3V6K
10U_0402_6.3V6M
22U_0603_6.3V6M
CC296
CC295
1
2
PSC
+1.0V_VCCSTG
BSC
1
CC199
2
@
1
CC297
2
1U_0402_6.3V6K
10U_0402_6.3V6M
+VCC_SFR_OC
+1.2V_MEM_CPUCLK
BSC
1
CC194
2
@
1
2
10U_0402_6.3V6M
CC294
PSC
PSC
DG1.0
CC195
+1.0V_VCCST source
+1.2V_MEM
1U_0402_6.3V6K
CC288
1U_0402_6.3V6K
1.35V in DDR3L,
1.2V in LPDDR3 and DDR4
UC1N
CPU@
CPU POW ER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
SKL-U_BGA1356
+1.0V_VCCST
PSC
1
2
CC202
1U_0402_6.3V6K
SKL-U
+VCC_SA
DG0.9
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
1 2
RC168 100_0402_1%
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+1.0VS_VCCIO
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
12
12
RC166
100_0402_1%
VSA_SEN- <48>
VSA_SEN+ <48>
8/14 PWR request
RC165
100_0402_1%
VCCIO_SENSE <46>
VSSIO_SENSE <46>
RC167
100_0402_1%
12
CZ113 1U_0402_6.3V6K
SIO_SLP_S3#<11,17,32,47>
SIO_SLP_SUS#<8,11,18,32,41,45,46,47,53>
SIO_SLP_S4#<11,17,32,44,54>
1 2
RZ120 0_0402_5%
@
+3.3V_ALW
1
2
+1.0VS_VCCIO
1
2
@
5
0.1U_0402_10V7K
P
B
A
G
3
TC7SH08FU_SSOP5~D
1
2
CC181
1U_0402_6.3V6K
PSC
1
1
2
2
CC252
1U_0402_6.3V6K
+1.0V_VCCSTG source
+VCC_SFR_OC
6
VOUT
5
GND
BSCBSC
1
2
@
S0
HIGH
HIGH
HIGH LOW LOW
S0Ix
LOW
HIGH
S3
LOW
LOW
@
CZ114 0.1U_0201_10V6K
1
CC248
CC249
2
@
10U_0402_6.3V6M
10U_0402_6.3V6M
1 2
+1.0V_VCCST+1.0V_VCCSTG
1 2
RC238 0_0603_5%@
+1.0V_PRIM
12
CZ95 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,32,44,54>
A A
5
+1.0V_PRIM
+5V_ALW
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6 A
TR=12.5us@Vin=1.05 V
VOUT
GND
6
5
4
+1.0V_VCCST_C
PJP27
12
PAD-OPEN1x1m
1 2
@
CZ78 0.1U_0201_10V6K
+1.0V_VCCST
SIO_SLP_S0#<11,33,46>
SIO_SLP_S3#<11,17,32,47>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
3
12
CZ87 1U_0402_6.3V6K
@
+5V_ALW
+3.3V_ALW
5
1
P
B
O
2
A
G
UC13
3
1 2
RC320 0_0402_5%
4
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6 A
TR=12.5us@Vin=1.05 V
2
VOUT
GND
12
PJP32
PAD-OPEN1x1m
+1.0V_VCCSTG_C
6
5
DELL CONFIDENTIAL/PROPRIETARY
pop option with UZ19
1 2
@
CZ82 0.1U_0201_10V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-C461P
LA-C461P
LA-C461P
17 61Tuesday, October 13, 2015
17 61Tuesday, October 13, 2015
17 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
5
+1.0V_PRIM
1 2
RC194 0_0805_5%
@
Imax : 2.57A
1 2
D D
C C
B B
RC299 0_0603_5%@
1 2
@
RC300 0_0402_5%
1 2
RC301 0_0402_5%
@
1 2
RC302 0_0402_5%
@
1 2
RC303 0_0402_5%
@
+1.8V_PRIM
+3.3V_ALW_PCH
+1.8V_PRIM
1 2
RC304 0_0402_5%
@
1 2
@
RC234 0_0402_5%
1 2
RC235 0_0402_5%
@
1 2
RC211 0_0402_5%
@
1 2
@
RC212 0_0402_5%
1 2
RC305 0_0402_5%
@
1 2
RC306 0_0402_5%
@
1 2
RC307 0_0402_5%
@
1 2
RC308 0_0402_5%
@
+3.3V_ALW_PCH +3.3V_VCCHDA
1 2
LC1 BLM15HG601SN1D_2P
1
CC215
2
@
1U_0402_6.3V6K
+1.0V_PRIM_CORE
+1.0V_MPHYAON
8/28 schematic review
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
close UC1.AF20 and <40 0mil
+3.3V_1.8V_PGPPA
+3.3V_PGPPB+3.3V_ALW_PCH
+3.3V_PGPPC
+3.3V_PGPPD
+3.3V_PGPPE
8/28 schematic review Pop PJP35 & Depop UZ20/RZ83/CZ84
close UC1.V15 and <100mil
1
CC313
2
0.1U_0402_25V6
8/26 vender suggest depop
LC2 BLM15HG601SN1D_2P
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
+1.0V_MPHYGT
close UC1.N15 and CC210 <400m il, CC 211 <120mil
1
2
+1.0V_SRAM
close UC1.K15, UC1.L15 and <100mil
1 2
RC169 0_0603_5%@
1
2
CC281
@
0.1U_0201_10V6K
1 2
CC210
@
1
2
close UC1.AJ19 an d <400mil
+3.3V_ALW +3.3V_ALW_DSW
A A
1 2
RC214 0_0402_5%
@
22U_0603_6.3V6M
@
CC279
1
2
5
22U_0603_6.3V6M
@
CC280
1
2
8/26 vender suggest depop
+3.3V_ALW +1.8V_PRIM +1.0V_PRIM
1
CC271
2
47U_0805_6.3V6M
4
close UC1.AL1 and <12 0mil
1
2
CC204
1U_0402_6.3V6K
close UC1.AF18 and <40 0mil
1
2
CC211
1U_0402_6.3V6K
47U_0805_6.3V6M
CC217
+1.0V_APLLEBB
@
1U_0402_6.3V6K
1
2
CC218
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
CC219
2
@
47U_0805_6.3V6M
+1.0V_APLL+1.0V_PRIM
1
2
1
CC225
@
1
2
CC314
2
47U_0805_6.3V6M
1
CC273
2
4
0.1U_0402_25V6
+1.0V_PRIM_CORE
47U_0805_6.3V6M
47U_0805_6.3V6M
CC272
+1.0V_PRIM_CORE+1.0VO_DSW
1
2
+1.0V_PRIM
close UC1.AB19 and <4 00milclose UC1.K17 an d <120mil
CC205
@
1U_0402_6.3V6K
+1.0V_AMPHYPLL
+1.0V_APLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
1
2
close UC1.N18 and <120mil
1U_0402_6.3V6K
close UC1.K15 an d <120mil
1
2
CC264
@
1U_0402_6.3V6K
close UC1.N20 and <100mil
1
2
8/26 vender suggestion
CC274
47U_0805_6.3V6M
+1.0V_PRIM
CC206
@
AB19
1U_0402_6.3V6K
AB20
P18
AF18
AF19
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
T19
T20
AJ21
AK20
N18
1 2
RC170 0_0402_5%
@
close UC1.K19 an d <100mil
RC173 0_0402_5%
@
3
PCH PWR
close UC1.AG15 and <120mil
UC1O
CPU@
CPU POW ER 4 OF 4
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB
SKL-U_BGA1356
1 2
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
SKL-U
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE _VID0
GPP_B1/CORE _VID1
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.AK19 and <120mil
+DCPRTC
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
CORE_VID0 <46>
CORE_VID1 <46>
Tak e c ar e! !! N ot e1 on P ag e 1 9
15 OF 20
+1.0V_CLK2+1.0V_PRIM
1 2
RC171 0_0402_5%
@
1
CC220
2
@
47U_0805_6.3V6M
+1.0V_CLK4+1.0V_PRIM
1
CC226
2
@
47U_0805_6.3V6M
3
close UC1.L19 an d <100mil
SIO_SLP_SUS#<8,11,17,32,41,45,46,47,53>
MPHYP_PWR_EN<11,45>
2
close UC1.Y16 and <4 00mil
+3.3V_PGPPB
1
CC265
2
@
close UC1.AA1 and <400mil
1
2
+1.0V_CLK6
1
CC221
2
@
47U_0805_6.3V6M
+3.3V_PGPPC
1U_0402_6.3V6K
CC214
0.1U_0201_10V6K
1
2
+3.3V_PGPPE
close UC1.T16 and <4 00mil
1
2
+RTC_CELL
1
2
DG0.9
1
CC207
2
@
1U_0402_6.3V6K
1
2
CC270
CC213
1U_0402_6.3V6K
0.1U_0201_10V6K
close UC1.A10 and <1 20mil
CC216
@
1U_0402_6.3V6K
DG0.9
CC208
@
1U_0402_6.3V6K
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
+1.0V_MPHYGT source
11/0 c ha nge p ower s ou rce
CZ84 1U_0402_6.3V6K@
RZ82 0_0402_5%
@
RZ83 0_0402_5%
@
+1.0V_PRIM
12
+5V_ALW
12
12
UZ20 @
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6 A
TR=12.5us@Vin=1.05 V
DELL CONFIDENTIAL/PROPRIETARY
2
1
+1.0V_MPHYGT
+1.0V_SRAM
+1.0V_APLLEBB
+1.8V_PRIM
1
2
+3.3V_ALW_PCH
1
2
CC212
1U_0402_6.3V6K
1 2
RC309 0_0603_5%@
1 2
RC310 0_0603_5%@
8/28 schematic review
close UC1.V19 and <120mil
CC209
@
1U_0402_6.3V6K
close UC1.AK17 and <120mil
1
1
CC223
2
2
CC224
1U_0402_6.3V6K
0.1U_0201_10V6K
+1.0V_MPHYGT+1.0V_PRIM
PJP35
1 2
PAD-OPEN1x3m
+1.0V_MPHYGT
6
VOUT
5
GND
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
1
2
@
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-C461P
LA-C461P
LA-C461P
1
CZ85
0.1U_0201_10V6K
18 61Tuesday, October 13, 2015
18 61Tuesday, October 13, 2015
18 61Tuesday, October 13, 2015
1.0
1.0
1.0
5
4
3
2
1
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D R e c o m me n d a t i on
CPU@
SKL-U
UC1P
GND 1 OF 3
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
D D
C C
B B
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
CPU@
UC1Q
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17 OF 20
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
SKL-U_BGA1356
CPU@
UC1R
GND 3 OF 3
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
18 OF 20
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (14/14)
CPU (14/14)
CPU (14/14)
LA-C461P
LA-C461P
LA-C461P
19 61Tuesday, October 13, 2015
19 61Tuesday, October 13, 2015
19 61Tuesday, October 13, 2015
1
1.0
1.0
1.0
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