Dell Latitude 300 Schematic

5

D D

4

3

2

1

Latitude3000 Schematic

Haswell-ULT

C C

2013-4-19

REV : X01

B B

A A

DY : None Installed UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, April 19, 2013

Date: Sheet of

Date: Sheet

Cover Page

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

1104

of

1104

of

1104

1

X00

5

Project code: 91.46O01.001 PCB P/N : 13221-SB Revision: X01

D D

VRAM(GDDR5) *8

128M x 16b x 4(1GB) 256M x 16b x 4(2GB)

78,79,80,81

DDR3L

Switchable Graphic only

eDP/CRT Converter

C C

CRT

R G B

55

14.0" LCD (16:9)

52

Touch Panel

MIC_IN/GND

B B

29

Combo Jack

HP_R/L

2CH SPEAKER (2CH 2W/4ohm)

NXP PTN3393

eDP/LVDS Converter

Realtek RTD2136R

Digital MIC

HDA CODEC

Camera

Realtek ALC3223

4

3

Latitude3000 Block Diagram

GPU

Nvidia N14P-GV2

73,74,75,76,77

55

53

52

27

PCIE x 4

eDP

USB2.0 x 1

HDA

Intel CPU

Haswell ULT

15W

Lynx Point

8 USB 2.0/1.1 ports

4 USB 3.0 port s

High Definition A udio

4 SATA ports

8 PCIE ports

LPC I/F

ACPI 4.0a

DDR3L 1333/1600MHz Channel A

DDR3L 1333/1600MHz Channel B

PCIE x 1

USB2.0 x 1

USB3.0 x 2

USB2.0 x 2

USB2.0 x 1

2

Giga LAN

RealTek 8111GUS

Mini-Card

802.11 b/g/n BT V4.0 combo

Left side

USB3.0 Port x 2

Right side

USB2.0 Port x 1

CardReader

RealTek RTS5176E

32

58

34,35

USB Board

DDR3L 1333/1600

SODIMM A

DDR3L 1333/1600

SODIMM B

30

SD/SDHC/MS/MS Pro Slot

12

13

RJ45 Conn.

1

CHARGER

BQ24717

INPUTS

AD+

BT+

SYSTEM DC/DC

TPS51225

INPUTS

DCBATOUT

CPU Core Power

ISL95813

INPUTS

DCBATOUT

DDR3L SUS

TPS51216

INPUTS OUTPUTS

DCBATOUT 1D35V_S3

CPU 1.05V

RT8237

DCBATOUT

31

CPU 1D5V_S0

TLV70215

3D3V_S5

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE

0D65V_S0

OUTPUTSINPUTS

1D05V_S0

OUTPUTSINPUTS

1D5V_S0

Switches

46,47

33

36 83

44

45

49

48

51

INPUTS OUTPUTS

1D35V_S3 1D35V_S0

5V_S5 5V_S0

3D3V_S5

VCCP_CPU 3D3V_S0

3D3V_S0

0D675V_S0

1D05V_VGA_S0

3D3V_VGA_S0

1D35V_VGA_S0

PCB LAYER

L1:Top L2:GND L3:Signal L4:Signal

33

L5:VCC L6:Signal L7:GND L8:Bottom

29

Thermal

NUVOTON NCT7718W

Fan Control

NUVOTON NCT3940S-A

A A

5

FAN

SMBUS

26

LPC debug port

KBC

NUVOTON

NPCE985P

Int.

62

KB

65

Touch PAD

Image sensor

4

PS2

LPC BUS

24

62

SPI

Flash ROM

8MB Quad Read

SMBUS

SATA(Gen3) x 1

25

3

SATA(Gen1) x 1

HDD

ODD

56

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Latitude300 Haswell

2104Friday, April 19, 2013

1

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)

Size Document Number Rev

A3

Date: Sheet of

(Reserved)

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

3104Tuesday, March 26, 2013

1

X00

5

4

3

2

1

SSID = CPU

1D05S_VCCST

RN401

XDP_TMS

D D

XDP_TDI

XDP_TDO

XDP_TRST# XDP_TCLK

R402 51R2J-2-GP

R402 51R2J-2-GP R406 51R2J-2-GPR406 51R2J-2-GP

Check TCLK Pull down Res.

1D05S_VCCST

12

SKTOCC#

1

H_CATERR#

1

H_PROCHOT#_R XDP_TRST#

H_CPUPWRGD

1

R405

12

10KR2J-3-GP

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST# DDR_PG_CTRL

H_PECI24

TP401TP401 TP402TP402

TP403TP403

1 2

R403

56R2J-4-GP

R401

62R2J-GP

C C

H_PROCHOT#24,42,44,46

Layout Note:

Impedance control:50 ohm

DDR_PG_CTRL12

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

CPU1B

PROC_DETECT# CATERR# PECI

PROCHOT#

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# SM_PG_CNTL1

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

JTAG

2 OF 19

PRDY#

PREQ# PROC_TCK PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS

XDP_TDI XDP_TDO

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

XDP_PRDY# 96 XDP_PREQ# 96 XDP_TCLK 96 XDP_TMS 96 XDP_TRST# 96 XDP_TDI 96 XDP_TDO 96

XDP_BPM[7:0]

RN401

1 2 3

XDP

4 5

SRN51J-1-GP

XDP

1 2 1 2

8 7 6

XDP_BPM[7:0] 96

B B

R407 200R2F-L-GPR407 200R2F-L-GP

1 2

R408 120R2F-GPR408 120R2F-GP

1 2

R409 100R2F-L1-GP-UR409 100R2F-L1-GP-U

1 2

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

Layout Note:

Design Guideline:

HASWELL-6-GP

SM_DRAMRST#

1D35V_S3

12

R410

R410 470R2J-2-GP

470R2J-2-GP

R404

1 2

0R2J-2-GP

Layout Note:

Place close to DIMM

DDR3_DRAMRST# 12,13

SM_RCOMP keep routing length less than 500 mils.

Wistron Corporation

A A

Title

CPU (THERMAL/MISC/PM)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU (THERMAL/MISC/PM)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

4104Friday, April 19, 2013

1

X00

SSID = CPU

5

4

3

2

1

D D

M_A_DQ[63:0]12

C C

B B

M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AW58

AW56

AW54

AW52

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58

AY56

AV58 AU58 AV56 AU56 AY54

AY52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HASWELL-6-GP

HSW_ULT _DD R3L

DDR CHANNEL A

3 OF 19

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

+V_SM_VREF_CNT

M_A_DIMA_CLK_DDR#0 12 M_A_DIMA_CLK_DDR0 12 M_A_DIMA_CLK_DDR#1 12 M_A_DIMA_CLK_DDR1 12

M_A_DIMA_CKE0 12 M_A_DIMA_CKE1 12

M_A_DIMA_CS#0 12 M_A_DIMA_CS#1 12

TP_M_A_DIMA_ODT0

M_A_RAS# 12

M_A_WE# 12

M_A_CAS# 12

M_A_BS0 12 M_A_BS1 12 M_A_BS2 12

M_A_A[15:0] 12

M_A_DQS#[7:0] 12

M_A_DQS[7:0] 12

+V_SM_VREF_CNT 37 DDR_WR_VREF01 12 DDR_WR_VREF02 13

HSW_ULT _DD R3L

CPU1D

M_B_DQ[63:0]13

TP501TP501

1

M_B_DQ[63:0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25

AM29

AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AM26

AK25 AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HASWELL-6-GP

HSW_ULT _DD R3L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

TP_M_B_DIMB_ODT0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_DIMB_CLK_DDR#0 13 M_B_DIMB_CLK_DDR0 13 M_B_DIMB_CLK_DDR#1 13 M_B_DIMB_CLK_DDR1 13

M_B_DIMB_CKE0 13 M_B_DIMB_CKE1 13

M_B_DIMB_CS#0 13 M_B_DIMB_CS#1 13

1

M_B_RAS# 13

M_B_WE# 13

M_B_CAS# 13

M_B_BS0 13 M_B_BS1 13 M_B_BS2 13

M_B_A[15:0] 13

M_B_DQS#[7:0] 13

M_B_DQS[7:0] 13

TP503TP503

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Latitude300 Has well

1

5104Friday, April 19, 2013

X00

5

SSID = CPU

4

3

2

1

D D

CFG[19:0]96

C C

CFG[19:0]

1 2

R601

R601 49D9R2F-GP

49D9R2F-GP

1 2

R603

R603 8K2R2F-1-GP

8K2R2F-1-GP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

TD_IREF

CFG3

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62

V63

H18 B12

J20

CPU1S

A5

E1 D1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD#A5

RSVD#E1 RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF

12

DY

R604

R604 1KR2J-1-GP

1KR2J-1-GP

HSW_ULT_DDR3L

RESERVED

PROC_OPI_RCOMP

19 OF 19

RSVD_TP#AV63 RSVD_TP#AU63

RSVD_TP#C63 RSVD_TP#C62

RSVD#B43

RSVD_TP#A51 RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

RSVD#AV62

RSVD#D58

VSS VSS

RSVD#P20 RSVD#R20

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

AV63 AU63

C63 C62

EDP_SPARE

B43

A51 B51

L60

N60

W23

PROC_OPI_COMP3

Y22

PROC_OPI_COMP

AY15

AV62 D58

P22 N21

HVM_CLK#

P20

HVM_CLK

R20

TP605TP605

1

1127 add (follow EA40)

R606 49D9R2F-GP

1 2

DY

R602 49D9R2F-GPR602 49D9R2F-GP

1 2

1

TP619TP619

1

TP620TP620

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1 : DISABLED

B B

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

1 : DISABLED

NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

Latitude300 Haswell

6104Friday, April 19, 2013

1

X00

5

SSID = CPU

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

VCC_CORE

HSW_ULT_DDR3L

CPU1L

D D

12

TP701TP701

R701

43R2J-GP

1 2

H_CPU_SVIDCLK H_CPU_SVIDDAT H_VCCST_PWRGD

DY

VCC_CORE

1D35V_S3

VCC_CORE

TP_VCCIO_OUT

1

+VCCIOA_OUT

H_CPU_SVIDALRT#

PWR_DEBUG

1D05S_VCCST

C702

5

4

12

1127 Change net name of R703.2 from VR_SVID_ALERT# to H_CPU_SVIDALRT#

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

3D3V_S5

1D05S_VCCST

12

DY

12

R706

R706 10KR2J-3-GP

10KR2J-3-GP

DY

H_VCCST_PWRGD 96

R709

R709 47KR2F-GP

47KR2F-GP

1127_modify (follow EA40)

VCC_SENSE46

VR_SVID_ALERT#46

H_CPU_SVIDCLK46

H_CPU_SVIDDAT46

H_VR_ENABLE46

PWR_DEBUG96

1D05S_VCCST

VCC_CORE

R702

100R2F-L1-GP-U

R710 10KR2J-3-GP

1 2

IMVP _PWR GD_R

R705 150R2J-L1-GP-UR705 150R2J-L1-GP-U

1 2

1D05S_VCCST

R703 75R2F-2-GPR703 75R2F-2-GP

1 2

R704 130R2F-1-GPR704 130R2F-1-GP

1 2

VR_SVID_ALERT#

H_CPU_SVIDDAT

1127 130R change to 110R 1203 110R change to 130R

C C

SCD1U10V2KX-5GP

U701

1

NC#1

VCC

1D05V_VTT_PWRGD36,48

B B

2

A

DY

GND3Y

74LVC1G07GW-GP

73.01G07.0HG

1 2

R707

R707 100KR2F-L1-GP

100KR2F-L1-GP

L59

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

J58

CPU1L

RSVD#L59 RSVD#J58

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD#N58 RSVD#AC58

VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59

VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HASWELL-6-GP

HSW_ULT_DDR3L

HSW ULT POW ER

12 OF 19

1205 Add

1 2

R711

0R5J-5-GP

1D05S_VCCST

12

DY

IMVP _PWR GD24,46

12

C701

C703

DY

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

4

1 2

R713

R713 100KR2F-L1-GP

100KR2F-L1-GP

IMVP _PWR GD_R

12

R712

R712 47KR2F-GP

47KR2F-GP

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, April 19, 2013

Date: Sheet of

2

Date: Sheet of

CPU (VCC CORE)

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

7104

1

X00

1D05V_S0

A A

5

4

3

2

1

SSID = CPU

D D

HSW_ULT_DDR3L

CPU1A

HSW_ULT_DDR3L

1 OF 19

PCH_DPB_N055

CRT

PCH_DPB_P055 PCH_DPB_N155 PCH_DPB_P155

C C

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

HASWELL-6-GP

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

EDPDDI

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_COMP EDP_BRIGHTNESS

EDP_TX0_DN 53 EDP_TX0_DP 53 EDP_TX1_DN 53 EDP_TX1_DP 53

EDP_AUX_DN 53 EDP_AUX_DP 53

1

TP801TP801

R801

24D9R2F-L-GP

+VCCIOA_OUT

Design Guideline: EDP_COMP keep routing length max 100 mils.

12

Trace Width:20 mils.

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Latitude300 Haswell

8104Friday, April 19, 2013

X00

5

4

3

2

1

SSID = CPU

HSW_ULT_DDR3L

CPU1P

D33

VSS

D34

D D

C C

B B

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

HASWELL-6-GP

HSW_ULT_DDR3L

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

VSS_SENSE

12

VSS_SENSE 46

Layout Note:

R901

100R2F-L1-GP-U

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

Wistron Corporation

A A

Title

CPU (VSS)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU (VSS)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

9104Friday, April 19, 2013

1

X00

SSID = CPU

5

4

3

2

1

1D35V_S3

D D

12

C1001

C1002

SC10U6D3V3KX-GP

12

C C

C1018

C1017

SC2D2U6D3V2MX-GP

DY

SC2D2U6D3V2MX-GP

X01 DY C1004 C1005 C1006 0409

12

C1003

DY

SC10U6D3V3KX-GP

12

C1019

DY

SC2D2U6D3V2MX-GP

12

C1004

DY

SC10U6D3V3KX-GP

C1020

SC2D2U6D3V2MX-GP

C1006

C1005

DY

SC10U6D3V3KX-GP

Layout Note:

Direct tie to CPU VccIn/Vss balls

Layout Note:

As close to CPU as possible

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

10 104Wednesday, April 10, 2013

X00

5

4

3

2

1

X01 Change L1101 from 2.2uH to 0R and DY C1104 0410

X01 Change L1102 from 2.2uH to 0R and DY C1106 0410

MAX: 1.92A

1.838A 41mA 42mA

D D

R1101

1 2

0R5J-5-GP

CAP need close to pin K9 L10

+V1.05DX_MODPHY_PCH1D05V_HSIO

C1102

SC1U6D3V2KX-GP

C1102

SC1U6D3V2KX-GP

C1101

SC1U6D3V2KX-GP

C1101

12

SC1U6D3V2KX-GP

12

1D05V_HSIO

L1101

0R2J-2-GP

12

C1103

12

+V1.05S_AUSB3PLL

SC1U6D3V2KX-GP

C1104

12

DY

+V1.05S_AUSB3PLL

SC10U6D3V3KX-GPDYC1104

SC10U6D3V3KX-GP

C1123

SC10U6D3V3KX-GPDYC1123

SC10U6D3V3KX-GP

12

DY

CAP need close to pin B18

1D05V_HSIO

L1102 0R2J-2-GPL1102 0R2J-2-GP

12

C1105

SC1U6D3V2KX-GP

C1105

SC1U6D3V2KX-GP

12

CAP need close to pin B11

+V1.05S_ASATA3PLL

C1106

SC10U6D3V3KX-GPDYC1106

SC10U6D3V3KX-GP

12

DY

12

DY

C1107

SC10U6D3V3KX-GPDYC1107

SC10U6D3V3KX-GP

57mA 62mA 200mA

12

DY

+V1.05S_APLLOPI

C1110

SC10U6D3V3KX-GPDYC1110

SC10U6D3V3KX-GP

DY

1205 Add

R1103

0R3J-0-U-GP

C1124

SC10U6D3V3KX-GPDYC1124

SC10U6D3V3KX-GP

12

1 2

CAP need close to pin AC9

+V3.3A_PSUS3D3V_S5_PCH

12

C1108

C1108 SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

DY

L1103 IND-2D2UH-196-GP

1 2

68.2R21D.10R

C1111

SC1U6D3V2KX-GP

C1111

SC1U6D3V2KX-GP

12

DY

CAP need close to pin J18

12

+V1.05S_AXCK_DCB1D05V_S0

+V1.05S_AXCK_DCB

C1112

C1125

SC10U6D3V3KX-GPDYC1112

SC10U6D3V3KX-GP

12

DY

SC10U6D3V3KX-GPDYC1125

SC10U6D3V3KX-GP

X01 DY C1110 C1108 C1119 0410

1D05V_S0

C C

R1102

0R3J-0-U-GP

1 2

+V1.05S_APLLOPI

C1109

SC1U6D3V2KX-GP

C1109

SC1U6D3V2KX-GP

12

CAP need close to pin AA21

31mA 658mA 1.632A 1mA

1D05V_S0

IND-2 D2UH -196-G P

IND-2 D2UH -196-G P L1104

L1104

1 2

68.2R21D.10R

B B

+V1.05S_AXCK_LCPLL

C1113

SC1U6D3V2KX-GP

C1113

SC1U6D3V2KX-GP

C1114

12

DY

1D05V_S0

SC10U6D3V3KX-GPDYC1114

SC10U6D3V3KX-GP

R1104

0R3J-0-U-GP

1 2

C1116

SC1U6D3V2KX-GP

C1116

C1115

SC1U6D3V2KX-GP

SC10U6D3V3KX-GPDYC1115

SC10U6D3V3KX-GP

12

DY

1D05V_S0

12

R1105

0R5J-5-GP

1 2

SC1U6D3V2KX-GP

C1117

C1118

SC1U6D3V2KX-GP

C1118

SC1U6D3V2KX-GP

12

+V1.05S_CORE_PCH+1.05M_ASW

C1119

SC10U6D3V3KX-GPDYC1119

SC10U6D3V3KX-GP

12

DY

RTC_AUX_S5

C1121

SCD1U10V2KX-5GP

C1121

SCD1U10V2KX-5GP12C1122

SC1U6D3V2KX-GP

C1122

C1120

SCD1U10V2KX-5GPDYC1120

SCD1U10V2KX-5GP

12

SC1U6D3V2KX-GP

CAP need close to pin A20

A A

5

CAP need close to pin AE9

4

CAP need close to pin AE8 J11

3

CAP need close to pin AG10

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Latitude300 Haswell

1

X00

11 104Wednesday, April 10, 2013

X00

5

4

3

2

1

SSID = MEMORY

DM1

M_A_A[15:0]5

D D

M_A_BS25

M_A_BS05 M_A_BS15

M_A_DQ[63:0]5

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

C1202

12

C1206

C1216

SC1U6D3V2KX-GP

Layout Note:

Place these caps close to VREF_CA

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQS#[7:0]5

M_A_DQS[7:0]5

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

DDR3_DRAMRST#4,13

SCD1U10V2KX-5GPDYC1217

SCD1U10V2KX-5GP

M_VREF_CA_DIMMA

12

C1218

C1201

SCD1U10V2KX-5GP

C C

0D675V_S0

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

M_VREF_DQ_DIMMA

12

DY

C1204

C1205

SCD1U10V2KX-5GP

12

C1215

C1214

DY

SC1U6D3V2KX-GP

M_A_DIMA_ODT0 M_A_DIMA_ODT1

C1217

12

DY

0D675V_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ25 M_A_DQ24 M_A_DQ27 M_A_DQ26 M_A_DQ44 M_A_DQ41 M_A_DQ43 M_A_DQ47 M_A_DQ45 M_A_DQ40 M_A_DQ42 M_A_DQ46 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ22 M_A_DQ23 M_A_DQ36 M_A_DQ33 M_A_DQ34 M_A_DQ38 M_A_DQ37 M_A_DQ32 M_A_DQ35 M_A_DQ39 M_A_DQ62 M_A_DQ58 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ59 M_A_DQ56 M_A_DQ57

M_A_DQS#1 M_A_DQS#3 M_A_DQS#5 M_A_DQS#6 M_A_DQS#0 M_A_DQS#2 M_A_DQS#4 M_A_DQS#7

M_A_DQS1 M_A_DQS3 M_A_DQS5 M_A_DQS6 M_A_DQS0 M_A_DQS2 M_A_DQS4 M_A_DQS7

close to dimm

A A

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68

70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10

27

45

62 135 152 169 186

12

29

47

64 137 154 171 188

116 120

126

1

30

203 204

EVENT# DQ11 DQ12

VDDSPD DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19

NC#/TEST DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P-119-GP-U

1st = 62.10024.R31

2nd = 62.10017.P61

3rd = 62.10017.N41

4th = 62.10017.P41

X01 0409

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_A_RAS# 5 M_A_WE# 5 M_A_CAS# 5

M_A_DIMA_CS#0 5 M_A_DIMA_CS#1 5

M_A_DIMA_CKE0 5 M_A_DIMA_CKE1 5

M_A_DIMA_CLK_DDR0 5 M_A_DIMA_CLK_DDR#0 5

M_A_DIMA_CLK_DDR1 5 M_A_DIMA_CLK_DDR#1 5

PCH_SMBDATA 13,18,62,96 PCH_SMBCLK 13,18,62,96

C1203

SCD1U10V2KX-5GP

3D3V_S0

12

DY

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

DDR_PG_CTRL4

1 2

Q1201 Need check Vth=1V

X01 DY C1208 0410

12

DY

TC1201

DY

ST330U2VDM-4-GP

12

C1210

DY

SCD1U10V2KX-5GP

0R2J-2-GP

0R2J-2-GP R1205

R1205

DDR_PG_CTRL_R

C1211

SA0_DIMA SA1_DIMA

DY

C1207

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

12

C1208

SC10U6D3V5KX-1GP

12

C1212

SC1U6D3V2KX-GP

12

R1202

R1201

0R2J-2-GP

12

C1220

C1209

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

12

C1213

SC1U6D3V2KX-GP

1D35V_S3

G

DS

Q1201

Q1201 DMN5L06K-7-GP

DMN5L06K-7-GP

84.05067.031

2nd = 84.00301.A31

3rd = 84.2N702.W31

X01 0408

12

Note: SA0 DIM0 = 0 , SA1_DIM0 = 0 SO-DIMM A SPD Address is 0xA0 SO-DIMM A TS Address is 0x30

12

C1222

C1221

SCD1U10V2KX-5GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

5V_S5

X01 0408

12

R1208

R1208 200KR2F-L-GP

200KR2F-L-GP

DDR_VTT_PG_CTRL

12

R1204

R1204 2MR2-GP

2MR2-GP

DY

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF015

1D35V_S3

D

Q1202

Q1202 2N7002K-2-GP

2N7002K-2-GP

S

G

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL 49

R1217

0R2J-2-GP

DY

2R2F-GP

2R2F-GP R1210

R1210

1 2

12

C1219

C1219 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH1

12

R1212

R1212 24D9R2F-L-GP

24D9R2F-L-GP

R1206 66D5R2F-GPR1206 66D5R2F-GP

R1207 66D5R2F-GPR1207 66D5R2F-GP

R1203 66D5R2F-GPR1203 66D5R2F-GP

R1209 66D5R2F-GPR1209 66D5R2F-GP

12

1D35V_S3DDR_VREF_S3

12

1 2

R1211

R1211 1K8R2F-GP

1K8R2F-GP

R1213

R1213 1K8R2F-GP

1K8R2F-GP

M_VREF_DQ_DIMMA

M_A_DIMA_ODT0

M_A_DIMA_ODT1

M_B_DIMB_ODT0 13

M_B_DIMB_ODT1 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, April 19, 2013

Friday, April 19, 2013 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM1

Latitude300 Has well

1

12 104

X00

5

4

3

2

1

SSID = MEMORY

DM2

D D

M_VREF_CA_DIMMB

Layout Note:

EC1302

C1304

SC1U6D3V2KX-GP

5

SCD1U10V2KX-5GP

12

C1302

SCD1U10V2KX-5GP

12

C1306

SCD1U10V2KX-5GP

12

C1318

SC1U6D3V2KX-GP

Place these caps close to VREF_CA

12

C1301

SCD1U10V2KX-5GP

C C

M_VREF_DQ_DIMMB

12

DY

C1305

SC2D2U10V3KX-1GP

0D675V_S0

12

C1316

C1317

DY

B B

A A

C1317

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

M_B_A[15:0]5

M_B_BS25

M_B_BS05 M_B_BS15

M_B_DQ[63:0]5

Layout Note:

Place these caps close to VREF_DQ

Layout Note:

Place these caps close to VTT1 and VTT2.

M_B_DQS#[7:0]5

M_B_DQS[7:0]5

M_B_DIMB_ODT012 M_B_DIMB_ODT112

M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

DDR3_DRAMRST#4,12

close to dimm

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ8 M_B_DQ14 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ9 M_B_DQ13 M_B_DQ15 M_B_DQ28 M_B_DQ29 M_B_DQ26 M_B_DQ27 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ40 M_B_DQ41 M_B_DQ46 M_B_DQ42 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ43 M_B_DQ56 M_B_DQ57 M_B_DQ59 M_B_DQ58 M_B_DQ61 M_B_DQ60 M_B_DQ63 M_B_DQ62 M_B_DQ4 M_B_DQ1 M_B_DQ3 M_B_DQ7 M_B_DQ5 M_B_DQ0 M_B_DQ2 M_B_DQ6 M_B_DQ32 M_B_DQ37 M_B_DQ38 M_B_DQ34 M_B_DQ33 M_B_DQ36 M_B_DQ39 M_B_DQ35 M_B_DQ17 M_B_DQ16 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ23 M_B_DQ22 M_B_DQ52 M_B_DQ49 M_B_DQ48 M_B_DQ53 M_B_DQ51 M_B_DQ55 M_B_DQ54 M_B_DQ50

M_B_DQS#1 M_B_DQS#3 M_B_DQS#5 M_B_DQS#7 M_B_DQS#0 M_B_DQS#4 M_B_DQS#2 M_B_DQS#6

M_B_DQS1 M_B_DQS3 M_B_DQS5 M_B_DQS7 M_B_DQS0 M_B_DQS4 M_B_DQS2 M_B_DQS6

C1319

SCD1U10V2KX-5GPDYC1319

SCD1U10V2KX-5GP

0D675V_S0

12

DY

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40 42 50 52 57 59 67 69 56 58 68

70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10

27

45

62 135 152 169 186

12

29

47

64 137 154 171 188

116 120

126

30

203 204

NC#/TEST DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P-90-GP

1st = 62.10017.0A1

2nd = 62.10017.K11

3rd = 62.10017.P31

4th = 62.10017.N91

X01 0409

4

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_B_RAS# 5 M_B_WE# 5 M_B_CAS# 5

M_B_DIMB_CS#0 5 M_B_DIMB_CS#1 5

M_B_DIMB_CKE0 5 M_B_DIMB_CKE1 5

M_B_DIMB_CLK_DDR0 5 M_B_DIMB_CLK_DDR#0 5

M_B_DIMB_CLK_DDR1 5 M_B_DIMB_CLK_DDR#1 5

PCH_SMBDATA 12,18,62,96 PCH_SMBCLK 12,18,62,96

C1303

SCD1U10V2KX-5GP

1D35V_S3

Note: SO-DIMM B SPD Address is 0xA4 SO-DIMM B TS Address is 0x34

3D3V_S0

12

DY

12

DY

12

DY

Layout Note:

Place these Caps near SO-DIMMA.

3

12

C1307

C1308

DY

SC10U10V5KX-2GP

12

C1314

C1313

SCD1U10V2KX-5GP

3D3V_S0

SA1_DIMB

SA0_DIMB

X01 DY C1311 0410

12

C1309

DY

SC10U6D3V5KX-1GP

12

C1315

SCD1U10V2KX-5GP

12

C1311

DY

C1310

SC10U6D3V5KX-1GP

EC1301

SCD1U10V2KX-5GP

12

C1312

SC10U6D3V5KX-1GP

R1301

R1301 10KR2J-3-GP

10KR2J-3-GP

R1302

0R2J-2-GP

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF025

2

0R2J-2-GP

2R2F-GP

2R2F-GP R1305

R1305

1 2

12

C1321

C1321 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH2

12

R1310

R1310 24D9R2F-L-GP

24D9R2F-L-GP

DDR_VREF_S3 1D35V_S3

12

R1312

12

DY

12

R1306

R1306 1K8R2F-GP

1K8R2F-GP

R1303

R1303 1K8R2F-GP

1K8R2F-GP

M_VREF_DQ_DIMMB

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, April 19, 2013

Friday, April 19, 2013 Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM2

Latitude300 Has well

1

13 104

X00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

M3

Latitude300 Haswell

14 104Tuesday, March 26, 2013

1

X00

SSID = CPU

5

4

3

2

1

D D

HSW_ULT_DDR3L

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

CPU1I

eDP_BKL T_CTRL53

RN1503

1 2 3

OPS

SRN10KJ-5-GP

C C

3D3V_S0

B B

R1509

SRN10KJ-5-GP

1 2

DY

RN1505

1 2 3 4 5

SRN10KJ-6-GP

DGPU_HOLD_RST#

4

DGPU_PWR_EN

DGPU_PWROK

10KR2J-3-GP

8 7 6

PIRQC# PIRQD#

PIRQB#

PIRQA#20

DGPU_PWR_EN82,83 DGPU_HOLD_RST#73 DGPU_PWROK82,83

SC1KP25V2JX-GP

CLK_PCIE_WLAN_REQ3# 18,58

TP1501TP1501

EC1501

TP1503TP1503 TP1502TP1502

eDP_BKL EN

1

eDP_VDD EN

1

PIRQB# PIRQC# PIRQD# PCI_PME#

1

12

B8 A9 C6

U6 P4 N4 N2

AD4

U7 L1 L3 R5 L4

EC1502

EC1502 SC1KP25V2JX-GP

SC1KP25V2JX-GP

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA#/GPIO77 PIRQB#/GPIO78 PIRQC#/GPIO79 PIRQD#/GPIO80 PME#

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

HASWELL-6-GP

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

DDPB_AUXN

DDPB_AUXP

1

TP1506TP1506

1

TP1508TP1508

PCH_DPB_AUXN 55

PCH_DPB_AUXP 55

3D3V_S0

1

23

4

RN1509

RN1509 SRN2K2J-1-GP

SRN2K2J-1-GP

CRT_PCH_HPD 55

EDP_HPD 53

PCH_CRT_CLK 55 PCH_CRT_DATA 55

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( EDP/GPIO/DDI )

Latitude300 Haswell

15 104Friday, April 19, 2013

1

X00

5

4

3

2

1

SSID = PCH

PCIE Table

Port

1

D D

2

3

4

5(4lane)

6(4lane)

C C

B B

Device

TBD

WLAN

LAN

GPU

TBD

Share BUS

USB3.0_3

USB3.0_4

SATA0~3

CPU_RXN_C_dGPU_TXN073 CPU_RXP_C_dGPU_TXP073

dGPU_RXN_C_CPU_TXN073 dGPU_RXP_C_CPU_TXP073

CPU_RXN_C_dGPU_TXN173 CPU_RXP_C_dGPU_TXP173

dGPU_RXN_C_CPU_TXN173 dGPU_RXP_C_CPU_TXP173

CPU_RXN_C_dGPU_TXN273 CPU_RXP_C_dGPU_TXP273

dGPU_RXN_C_CPU_TXN273 dGPU_RXP_C_CPU_TXP273

CPU_RXN_C_dGPU_TXN373 CPU_RXP_C_dGPU_TXP373

dGPU_RXN_C_CPU_TXN373 dGPU_RXP_C_CPU_TXP373

PCIE_PRX_WLANTX_N358 PCIE_PRX_WLANTX_P358

PCIE_PTX_WLANRX_N3_C58 PCIE_PTX_WLANRX_P3_C58

PCIE_PRX_LANTX_N430 PCIE_PRX_LANTX_P430

PCIE_PTX_LANRX_N4_C30 PCIE_PTX_LANRX_P4_C30

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP C1606

C1606

1 2 1 2

C1605

C1605 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

OPS

OPS OPS

OPS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP C1608

C1608

1 2 1 2

C1607

C1607 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

OPS

OPS OPS

OPS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP C1610

C1610

1 2 1 2

C1609

C1609 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

OPS

OPS OPS

OPS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP C1612

C1612

1 2 1 2

C1611

C1611 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

OPS

OPS OPS

OPS

SCD1U10V2KX-5GP

C1601

1 2 1 2

C1602

C1602 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1603

1 2 1 2

C1604

C1604 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+V1.05S_AUSB3PLL

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil

2. Isolation Spacing: 12mil

3. Total trace length<500mil

R1601

3KR2F-GP

1 2

dGPU_RXN_CPU_TXN0 dGPU_RXN_CPU_TXP0

dGPU_RXN_CPU_TXN1 dGPU_RXN_CPU_TXP1

dGPU_RXN_CPU_TXN2 dGPU_RXN_CPU_TXP2

dGPU_RXN_CPU_TXN3 dGPU_RXN_CPU_TXP3

PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3

PCIE_PTX_LANRX_N4 PCIE_PTX_LANRX_P4

PCIE_RCOMP

E10

C23 C22

B23 A23

H10 G10

B21 C21

B22 A21

G11

C29 B30

G13

B29 A29

G17

C30 C31

G15

B31 A31

E15 E13 A27 B27

CPU1K

F10

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

PETN5_L3 PETP5_L3

PERN3

F11

PERP3

PETN3 PETP3

F13

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3

F17

PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

F15

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD#E15 RSVD#E13 PCIE_RCOMP PCIE_IREF

WLAN

LAN

HASWELL-6-GP

GPU

PCIE USB

HSW_ULT_DDR3L

11 OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1

USB3TP1

USB3RN2 USB3RP2

USB3TN2

USB3TP2

USBRBIAS#

USBRBIAS RSVD#AN10 RSVD#AM10

OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_PN3 USB_PP3

USB_COMP

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7

PM_SUSWARN#_R17

USB_PN0 34 USB_PP0 34

USB_PN1 34 USB_PP1 34

USB_PN2 63 USB_PP2 63

USB_PN4 52 USB_PP4 52

USB_PN5 58 USB_PP5 58

USB_PN6 52 USB_PP6 52

USB_PN7 32 USB_PP7 32

R1602

R1602 22D6R2F-L1-GP

22D6R2F-L1-GP

MCP_GPIO7318

1 1

1 2

TP1601TP1601 TP1602TP1602

USB3_PRX_CTX_N0 34 USB3_PRX_CTX_P0 34

USB3_PTX_CRX_N0 34 USB3_PTX_CRX_P0 34

USB3_PRX_CTX_N1 34 USB3_PRX_CTX_P1 34

USB3_PTX_CRX_N1 34 USB3_PTX_CRX_P1 34

USB_OC#0_1 18,35 USB_OC#2_3 35

USB_OC#4_5 20

USB_OC#2_3 USB_OC#6_7

USB 2.0 Table

Pair

Device

USB3.0 port1

0

USB3.0 Port2

1

USB2.0 Port3

2

TBD

3

CAMERA

4

WLAN

5

Touch Panel

6

Card Reader

7

Layout Note:

1. USB_COMP using 50 ohm single-ended impedance

2. Isolation Spacing :15mil

3. Total trace length<500mil

RN1601

8 7 6

SRN10KJ-6-GP

3D3V_S5_PCH

1 2 3 45

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PCIE/USB)

Latitude300 Haswell

16 104Friday, April 19, 2013

1

X00

5

4

3

2

1

SSID = PCH

RN1703

1

D D

R1717 10KR2J-3-GP

2 3

SRN10KJ-5-GP

12

DY

4

X01 2/26 Add PH 10K on XDP_DBRESET#

XDP_DBRESET#96

SYS_PWROK24,96 PCH_PWROK24,26,36

C C

PM_SUSWARN#_R16

PM_PWRBTN#24,96 AC_PRESENT24,76

BATLOW#20

3D3V_S5

RN1701

1

4

2 3

SRN10KJ-5-GP

B B

A A

SRN10KJ-5-GP

R1703 10KR2J-3-GPR1703 10KR2J-3-GP

1 2

3D3V_S5_PCH

1 2

DY

R1724 10KR2J-3-GP

12

EC1706

SC1KP25V2JX-GP

EC1702

SC1KP25V2JX-GP

12

5

EC1703

SC1KP25V2JX-GP

R1706 0R2J-2-GPR1706 0R2J-2-GP

MCP_GPIO12 AC_PRESENT

X01 2/26 modify PCH_WAKE# PU to 1K

PCH_WAKE#

PM_SUS_STAT#

12

EC1705

EC1704

SC1KP25V2JX-GP

3D3V_S0

12

1 2

PLT_RST#24,30,55,58,65,73,96

100KR2J-1-GP

MCP_GPIO12 20

XDP_DBRESET#

12

PM_RSMRST# PM_PCH_PWROK

SYS_PWROK

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

R1715

SYS_PWROK PLT_RST# PCH_PWROK KBC_DPWROK

1 2

TP1706TP1706 TP1705TP1705

12

DY

R1707

R1707 0R2J-2-GP

0R2J-2-GP

1 1

R1713

0R2J-2-GP

1 2

12

C1701

C1701 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

EMI 12/20

PCH strap pin:

On Die DSW VR Enable

DSWODVREN

HSW_ULT_DDR3L

CPU1H

PM_SUSACK#_R XDP_DBRESET# PCH_DPWROK PM_RSMRST# SYS_PWROK

PM_PCH_PWROK

MPWROK PCI_PLTRST#

PM_RSMRST#

PM_SUSWARN#_R

PM_PWRBTN# AC_PRESENT BATLOW# PCH_SLP_S0# PCH_SLP_WLAN#

PCI_PLTRST#

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/ GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPI O72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPI O29

HASWELL-6-GP

PM_SUSACK#24

PM_SUSWARN#24

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

RN1702

2 3

DS3

1

4

SRN0J-6-GP

3D3V_AUX_S5

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK#

SUS_STAT#/GPIO61

PM_SUSACK#_R PM_SUSWARN#_R

R1727

100KR2J-1-GP

1 2

Non DS3

Q1701

5

6

2N7002KDW-GP

84.2N702.A3F

2nd = 75.00601.07C

3rd = 84.2N702.E3F

4th = 84.DMN66.03F

8 OF 19

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4# SLP_S3#

SLP_A# SLP_SUS# SLP_LAN#

34

2

1

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

PCH_DPWROK

PM_RSMRST#

3V_5V_POK_C

Low = Disable High = Enable (default)

*

DSWODVREN

PCH_WAKE#

PM_CLKRUN# PM_SUS_STAT# SUS_CLK PM_SLP_S5#

PM_SLP_S4# PM_SLP_S3# PM_SLP_A# PM_SLP_SUS# PM_SLP_LAN#

R1729

R1729 0R2J-2-GP

0R2J-2-GP

1

R1718 0R2J-2-GP

1 2

DS3

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

1 2

R1728

1 2

NON DS3

0R2J-2-GP

1 2

DS3

NON DS3

0R2J-2-GP

0R2J-2-GP R1704

R1704

1 2 1 2

DY

R1705

X01 2/26 DY R1705 for OBFF disable

0R2J-2-GP

R1709 0R2J-2-GPR1709 0R2J-2-GP

1 2

TP1702TP1702

1 2

R1710

TP1703TP1703

0R2J-2-GP

TP1704TP1704

TP1707TP1707

R1725

R1725 100KR2F-L1-GP

100KR2F-L1-GP

DS3

1 2

RSMRST#_KBC 24

3V_5V_POK 45

PM_SLP_SUS#

X01 0408

4

3

2

DSWODVREN

PCIE_WAKE# 24,30

PM_CLKRUN#_EC 24

PCH_SUSCLK_KBC 24

PM_SLP_S4# 24,49

PM_SLP_S3# 24,36,48,49,51

PM_SLP_SUS# 24,38

KBC_DPWROK 24

PM_CLKRUN#

PCH_SUSCLK_KBC

Title

Size Document Number Rev

A3

Date: Sheet of

R1720

330KR2J-L1-GP

1 2

DY

R1721

330KR2J-L1-GP

R1714

8K2R2F-1-GP

1 2

RTC_AUX_S5

3D3V_S0

EC1701

DY

SC4D7P50V2CN-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PM)

Latitude300 Haswell

DY

1 2

17 104Friday, April 19, 2013

1

X00

5

4

3

2

1

SSID = PCH

X01 Follow vendor's suggestion, change C1801 C1802 to 15p 0417

C1801

0R2J-2-GP

D D

3D3V_S0

RN1801

1 2 3 4 5

SRN10KJ-6-GP

CLK_PCIE_WLAN_REQ3#15,58

CLK_PCIE_WLAN_N358 CLK_PCIE_WLAN_P358

CLK_PCIE_LAN_REQ4#20,30

CLK_PCIE_LAN_N430

C C

B B

CLK_PCIE_LAN_P430

PEG_CLKREQ#73

CLK_PCIE_VGA#73 CLK_PCIE_VGA73

LPC_AD[3..0]24,65

MCP_GPIO76

8

PEG_CLKREQ#

7

CLK_PCIE_REQ#

6

LPC_AD[3..0]

LPC_FRAME#24,65

SPI_CLK_R24,25 SPI_CS0#_R24,25

SPI_SI_R24,25

SPI_SO_R24,25

SPI_WP#25 SPI_HOLD#25

LPC_AD0 LPC_AD2 LPC_AD1 LPC_AD3

3D3V_S5

1

23

RN1802

RN1802 SRN1KJ-11-GP-U

SRN1KJ-11-GP-U

4

MCP_GPIO76 20

BOARD_ID1 2 0

RN1806

8 7 6

SRN0J-7-GP

1203 R1806 change to 33R

PCH_SPI_DQ3 PCH_SPI_DQ2

1 2 3 45

R18010R2J-2-GP R18010R2J-2-GP

1 2

1 2 1 2

1 2 1 2 1 2 1 2

CLK_PCIE_REQ#

CLK_PCIE_WLAN_REQ3#

CLK_PCIE_LAN_REQ4#

PEG_CLKREQ#

CLK_PCIE_REQ#

LPC_LAD0_PCH LPC_LAD1_PCH LPC_LAD2_PCH LPC_LAD3_PCH LPC_LFRAME#_PCH

PCH_SPI_CLK

R180633R2J-2-GP R180633R2J-2-GP

PCH_SPI_CS0#

R18070R2J-2-GP R18070R2J-2-GP

PCH_SPI_SI

R18080R2J-2-GP R18080R2J-2-GP

PCH_SPI_SO

R18090R2J-2-GP R18090R2J-2-GP

PCH_SPI_DQ2

R18110R2J-2-GP R18110R2J-2-GP

PCH_SPI_DQ3

R18120R2J-2-GP R18120R2J-2-GP

CPU1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASWELL-6-GP

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL-6-GP

HSW_ULT_DDR3L

WLAN

LAN

GPU

HSW_ULT_DDR3L

LPC

CLOCK

SIGNALS

SMBUS

C-LINKSPI

DIFFCLK_BIASREF

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPI O73

SML1DATA/GPIO74

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD#K21 RSVD#M21

TESTLOW_C 35 TESTLOW_C 34 TESTLOW_AK 8 TESTLOW_AL 8

CLKOUT_LPC_0 CLKOUT_LPC_1

7 OF 19

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO75

CL_CLK

CL_DATA

CL_RST#

XTAL24_IN

A25

XTAL24_OUT

B25

K21 M21

XCLK_BIASREF

C26

MCP_TESTLOW1

C35

MCP_TESTLOW2

C34

MCP_TESTLOW3

AK8

MCP_TESTLOW4

AL8

CLK_PCI_LPC_R

AN15

CLK_PCI_KBC_R

AP15

B35 A35

X01 change R1805 from 33 ohm to 0ohm 0410

MCP_GPIO11

AN2

SMB_CLK

AP2

SMB_DATA

AH1

CARD_PWR_EN

AL2

SML0_CLK

AN1

SML0_DATA

AK1

MCP_GPIO73

AU4

SML1_CLK

AU3

SML1_DATA

AH3

TP_CL_CLK

AF2 AD2 AF4

TP_CL_DATA TP_CL_RST#

1 1 1

+V1.05S_AXCK_LCPLL

R1803 3KR2F-GPR1803 3KR2F-GP

1 2

RN1803

1

4

SRN10KJ-5-GP

R1804 0R2J-2-GP

R1804 0R2J-2-GP R1805 0R2J-2-GPR1805 0R2J-2-GP

TP1803TP180 3 TP1804TP180 4 TP1805TP180 5

SMB_DATA

SMB_CLK

RN1804

23

4

LPC

1 2 1 2

SML0_CLK 53 SML0_DATA 53

MCP_GPIO73 16 SML1_CLK 24,26,5 3,76 SML1_DATA 24,26,53, 76

DY

EC1801

12

XTAL24_IN

XTAL24_OUT

23 1

SRN10KJ-5-GP

SC10P50V2JN-4GPDYEC1801

SC10P50V2JN-4GP

EC1802

12

DY

3D3V_S0

Q1801

6

5

2N7002KDW-GP

CLK_PCI_LPC 65 CLK_PCI_KBC 24

PCIE_CLK_XDP_N 9 6 PCIE_CLK_XDP_P 96

SC10P50V2JN-4GPDYEC1802

SC10P50V2JN-4GP

1

2

34

0R2J-2-GP

R1810

1 2

12

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

23

82.30004.891

2nd = 82.30004.841

3rd = 82.30023.A11

X01 0408

1128 Add EC1801 EC1802(DY)

SML1_CLK SML1_DATA SML0_DATA SML0_CLK

USB_OC#0_116,35

EC_SCI#20,24

CARD_PWR_EN

MCP_GPIO11

SMB_CLK SMB_DATA

RN1810

4

SRN10KJ-5-GP

84.2N702.A3F

2nd = 75.00601.07C

3rd = 84.2N702.E3F

4th = 84.DMN66.03F

X01 0408

XTAL24_IN_R

4 1

23 1

PCH_SMBDATA 12,13,62, 96

PCH_SMBCLK 12,13,62 ,96

C1801

1 2

SC15P50V2JN-2-G P

X1801

X1801 XTAL-24MHZ-86- GP

XTAL-24MHZ-86- GP

C1802

1 2

SC15P50V2JN-2-G P

RN1807

8 7 6

SRN2K2J-4-GP

RN1809

SRN10KJ-6-GP

8 7 6

RN1811

4

SRN2K2J-3-GP

3D3V_S0

3D3V_S5_PCH

1 2 3 45

1 23

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (CLOCK/SMBUS/CL/LPC/SPI)

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

18 104Friday, April 19, 2013

1

X00

5

4

3

2

1

SSID = CPU

RTC_X1

1 2

R1915 10MR2J-L-GPR1915 10MR2J-L-GP

X1901

X01 3/7 Change value from test report

HDA_SDIN027

R1903

TP1902TP1902

TP1901TP1901

RTC_AUX_S5

12

HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDIN0

HDA_SDOUT TP_HDA_DOCK_EN#

1

PCH_JTAG_TRST#

1

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

XDP_TCK_JTAGX

R1901

R1901 1MR2J-1-GP

1MR2J-1-GP

RTC_X1 RTC_X2

SM_INTRUDER#

PCH_INTVRMEN SRTC_RST# RTC_RST#

C1903

SC15P50V2JN-2-GP

CPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER#

AV7

INTVRMEN

AV6

SRTCRST#

AU7

RTCRST#

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST#/I2S_MCLK#

AY10

HDA_SDI0/I2S0_RX D

AU12

HDA_SDI1/I2S1_RX D

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN#/I2S1_ TXD#

AV10

HDA_DOCK_RST#/I2S1 _SFRM#

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD#AL11

AC4

RSVD#AC4

AE63

JTAGX

AV2

RSVD#AV2

HASWELL-6-GP

1 2

D D

RTC_AUX_S5

Q1901

RTCRST_ON24

R1902

10KR2J-3-GP

C C

G

12

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

C1901

21

12

G1901

GAP-OPEN

SC1U6D3V2KX-GP

GAP-OPEN

1

23

RN1901

RN1901 SRN20KJ-1-GP

SRN20KJ-1-GP

4

12

C1902

C1902 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

330KR2J-L1-GP

X01 0408

1203 R1907 change from 0R to 33R

R1907 33R2J-2-GPR1907 33R2J-2-GP

HDA_CODEC_BITCLK27

HDA_CODEC_SYNC27

HDA_CODEC_RST#27,29

Flash Descriptor Security Overide/ Intel ME De bug Mode

HDA_SDO UT

The internal pull-do wn is disabled af ter PLTRST# deasserts

B B

Low = Default High = Enable

R1913

1 2

DY

330KR2J-L1-GP

*

PCH_INTVRMEN

HDA_CODEC_SDOUT27

ME_UNLOCK24

1D05S_VCCST

Integrat ed SUS 1V VRM E nable

INTVRMEN

Low = External VRs High = Internal VRs

EC1901

HDA_CODEC_BITCLK

1 2

DY

SC10P50V2JN-L1-GP

*

1 2

R1908 0R2J-2-GPR1908 0R2J-2-GP

1 2

R1911 0R2J-2-GPR1911 0R2J-2-GP

1 2

R1912 33R2J-2-GPR1912 33R2J-2-GP

1 2

R1909 1KR2J-1-GPR1909 1KR2J-1-GP

1 2

X01 Change R1912 to 33ohm 0409

DY

DY DY

DY

1 2

DY

12

R1916 51R2J-2-GP

R1917 51R2J-2-GP

R1918 51R2J-2-GP

R1919 1KR2J-1-GP

R1920 51R2J-2-GP

HDA_BITCLK

HDA_SYNC

HDA_RST#

HDA_SDOUT

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

XDP_TCK_JTAGX

PCH_JTAG_TCK

X1901

41

2 3

X-32D768KHZ-65-GP

82.30001.A41

2nd = 82.30001.841

X01 0408

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

RTC_X2

C1904

C1904 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2

X01 3/7 Change value from test report

5 OF 19

RSVD#L11

RSVD#K10

SATALED#

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

EC_SMI#

V1 U1 V6 AC1

SATA_IREF

A12 L11 K10

SATA_RCOMP

C12

SATA_LED#

U3

SATA_ODD_PRSNT# EC_SMI#

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

SATA_RCOMP

SATA3_PRX_HDDTX_N0 56 SATA3_PRX_HDDTX_P0 56 SATA3_PTX_HDDRX_N0 56 SATA3_PTX_HDDRX_P0 56

SATA_PRX_ODDTX_N2 56 SATA_PRX_ODDTX_P2 56 SATA_PTX_ODDRX_N2 56 SATA_PTX_ODDRX_P2 56

EC_SMI# 24

SATA_ODD_PRSNT# 56

SATA_LED# 61

Layout Note:

4mil trace at break-out and 3 12-15mil trace with <0.2 ohms and length total <= 500mils.

RN1902

1 2 3

SRN10KJ-5-GP

1 2

3D3V_S0

4

HDD1

ODD

0114 Change

+V1.05S_ASATA3PLL

R1904

R1904 0R2J-2-GP

0R2J-2-GP

R1906

R1906 3KR2F-GP

3KR2F-GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

19 104Friday, April 19, 2013

1

X00

SSID = CPU

5

4

CPU1J

HSW_ULT_DDR3L

3

10 OF 19

2

1D05S_VCCST

12

R2018

R2018 1KR2J-1-GP

1KR2J-1-GP

1

MCP_GPIO7618

D D

3D3V_S5

RN2006

1 2 3

SRN10KJ-11-GP-U

3D3V_S5_PCH

X01 change R2013 from

12

0ohm to 10K 0417

R2013

R2013 10KR2J-3-GP

10KR2J-3-GP

X01 3/7 Add shotpad to 10K and R2013 to 0 ohm for power consumption

C C

MCP_R

3D3V_S5_PCH

4

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

RN2012

RN2012 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

BATLOW# MCP_GPIO27

R200110KR2J-3-GP R200110KR2J-3-GP R200210KR2J-3-GP R200210KR2J-3-GP R200410KR2J-3-GP R200410KR2J-3-GP R200910KR2J-3-GP R200910KR2J-3-GP R201510KR2J-3-GP R201510KR2J-3-GP R201610KR2J-3-GP R201610KR2J-3-GP R201710KR2J-3-GP R201710KR2J-3-GP R201910KR2J-3-GP R201910KR2J-3-GP R202010KR2J-3-GP R202010KR2J-3-GP R202110KR2J-3-GP R202110KR2J-3-GP R202210KR2J-3-GP R202210KR2J-3-GP R202310KR2J-3-GP R202310KR2J-3-GP

8 7 6

MCP_GPIO58 MCP_GPIO44

MCP_GPIO46 MCP_GPIO26

MCP_GPIO56

MCP_GPIO45 MCP_GPIO14

MCP_GPIO28 MCP_GPIO8 MCP_GPIO13 MCP_GPIO47 MCP_GPIO57

EC_SWI#

RTC_DET#

WLAN_PLT_RST#

BATLOW# 17

MCP_GPIO1217

SATA_ODD_DA#56 RTC_DET#25

3D3V_S0

USB_OC#4_5 16

BOARD_ID118

HSIOPC21

EC_SWI#24 EC_SCI#18,24

HDA_SPKR27

RN2011

RN2011 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

8 7 6

TP2002TP2002

TP2001TP2001

MCP_GPIO76 MCP_GPIO8 MCP_GPIO12 MCP_GPIO15

RTC_DET# MCP_GPIO27 MCP_GPIO28 MCP_GPIO26

MCP_GPIO56 MCP_GPIO57 MCP_GPIO58 WLAN_PLT_RST# MCP_GPIO44 MCP_GPIO47 BOARD_ID1 BOARD_ID2

HSIOPC MCP_GPIO13 MCP_GPIO14

CAMERA_PWR_EN

1

MCP_GPIO45 MCP_GPIO46

EC_SWI# EC_SCI# HDD_DEVSLP

1

HDA_SPKR

PIRQA# DBC_EN

BLUETOOTH_EN

P1

BMBUSY#/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO 71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO3 3

C4

SDIO_POWER_EN/ GPIO70

L2

DEVSLP1/GPIO3 8

N5

DEVSLP2/GPIO3 9

V2

SPKR/GPIO81

HASWELL-6-GP

PCH strap pin:

CLK_PCIE_LAN_REQ4# 18,30 PIRQA# 15

HDA_SPK R

The internal pull-do wn is disabled af ter PLTRST# deasserts

GPIO

NO REB OOT

Low = Disable (Default)

*

High = Enable

CPU/

CPU/ MISC

MISC

SERIAL IO

THRMTRIP#

RCIN#/GPIO8 2

SERIRQ

PCH_OPI_RCOMP

RSVD#AF20 RSVD#AB21

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO9 1

UART0_TXD/GPIO9 2 UART0_RTS#/GPIO 93 UART0_CTS#/GPIO 94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST#/GPIO 2 UART1_CTS#/GPIO 3

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

SDIO_CLK/GPIO6 4

SDIO_CMD/GPIO65

SDIO_D0/GPIO6 6 SDIO_D1/GPIO6 7 SDIO_D2/GPIO6 8 SDIO_D3/GPIO6 9

PCH_THERMTRIP

D60

H_RCIN#

V4

INT_ SERIRQ

T4

PCH_OPIRCOMP

AW15 AF20 AB21

R6 L6 N6

LPSS_GSPI0_MOSI_BBS0_R

L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4

I2C0 _SDA

F2

I2C0 _SCL

F3

I2C1 _SDA

G4

I2C1 _SCL

F1 E3 F4

LPSS_SDIO_D0_CMNHDR

D3 E4 C3 E2

3D3V_S0

1KR2J-1-GP

1KR2J-1-GP R2006

R2006

1 2

DY

KB_DET# 62

DBC_EN 52

BLUETOOTH_EN 58

HDA_SPKR

1 2

R2003

R2003 49D9R2F-GP

49D9R2F-GP

SATA_ODD_PWRGT 56

SATA_ODD_DA#56

H_RCIN# 24

INT_ SERIRQ 24

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

3D3V_S0

1 2 3 45

3D3V_S0

1 2 3 45

100KR2J-1-GP

H_RCIN#

INT_ SERIRQ KB_DET#

I2C0 _SCL I2C0 _SDA I2C1 _SCL I2C1 _SDA

HSIOPC

SRN10KJ-6-GP

8 7 6

SRN10KJ-6-GP

8 7 6

R2007

1 2

RN2002

RN2007

B B

BIOS strap pin:

BIOS UMA/DIS Strap pin

BOARD_ID2BOARD_ID1

UMA

DIS

A A

11

01

BOARD_ID2

3D3V_S0

12

OPS

12

UMA

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

Need SW double confirm if that's needed Top-Block swap

Top-Block Swap Override mode

SDIO_D0 / GPIO66

The internal pull-do wn is disabled af ter PLTRST# deasserts

High = Enable "Top-Block swap" mode (Default) Low = Disable "Top-Block swap" mode

*

TLS Confidentiality

Low = Disable Intel ME Crypto TLS

GPIO15

The internal pull-do wn is disabled af ter RSMRST# deasserts.

*

High = Enable Intel ME Crypto TLS

Boot BIOS Strap Bit BBS

Boot BIOS Destination

The internal pull-do wn is disabled af ter PLTRST# deasserts

*

Low = SPI High = LPC

Need double confirm, GPIO table set to GPI if that's needed PH or PL

5

4

3

3D3V_S0

12

R2011

DY

1KR2J-1-GP

LPSS_SDIO_D0_CMNHDR

3D3V_S5_PCH

12

R2014

DY

1KR2J-1-GP

3D3V_S0

12

R2012

DY

1KR2J-1-GP

LPSS_GSPI0_MOSI_BBS0_R

MCP_GPIO15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (GPIO/CPU)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

20 104Friday, April 19, 2013

1

X00

5

SSID = CPU

D D

1D05V_S0

DSW 20121019

3D3V_S5 3D3V_S0

C C

R2101 0R2J-2-GPR2101 0R2J-2-GP

1 2

1D05V_S0

1 2

0R2J-2-GP

0R2J-2-GP R2117

R2117

DY

12

+V3.3A_DSW_P

C2136

C2136 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+V1.05S_SSCF100

C2137

SC1U6D3V2KX-GP

C2137

SC1U6D3V2KX-GP

4

+V1.05DX_MODPHY_PCH

0R2J-2-GP

0R2J-2-GP R2105

R2105

1 2

C2105

SC1U6D3V2KX-GPDYC2105

SC1U6D3V2KX-GP

12

DY

TP2102TP2102

+V3.3A_1.5A_HDA3D3V_S5_PCH

R2108

1 2

0R2J-2-GP

R2112 0R2J-2-GPR2112 0R2J-2-GP

1 2

TP2107TP2107

C2116

SC1U6D3V2KX-GP

C2116

SC1U6D3V2KX-GP

12

TP2108TP2108

TP2103TP2103 TP2104TP2104 TP2101TP2101

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP_VCCAPLLOPI_VAL

1

+V1.05S_APLLOPI

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

12

C2123

C2123 SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

B18 B11

Y20

AA21

W21

AH14

AH13

AC9 AA9

AH10

K19 A20

R21

K18 M20

V21 AE20 AE21

L10

M9

N8 P9

J13

V8

W9

J18

J17

T21

CPU1M

K9

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD#Y20 VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3

3

2

1

DSW 20121019

3D3V_S5_PCH

R2102

R2102 0R2J-2-GP

1 2

12

C2109

C2109 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

RTC_AUX_S5

1 2

R2110

R2110 5D1R2F-GP

5D1R2F-GP

1 2

TP2106TP2106

1

12

0R2J-2-GP

PCH_VCCDSW_R+PCH_VCCDSW

3D3V_S0

TP2109TP2109

TP2105TP2105

C2135

SC1U6D3V2KX-GP

C2135

SC1U6D3V2KX-GP

12

C2147

C2147 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2114

C2114 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2128

SC1U6D3V2KX-GP

C2128

SC1U6D3V2KX-GP

12

3D3V_S5

1 2

1D05V_S0

HSIO

OPI

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20

VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

+3.3A_DSW_PRTCSUS

AH11 AG10

+VCCRTCEXT

AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8

+V1.05A_SUS_PCH

AD10 AD8

J15 K14 K16

U8 T9

+V1.05A_AOSCSUS

AB8

TP_V1.05S_APLLOPI

AC20 AG16 AG17

C2110

SCD1U10V2KX-5GP

1D05V_S0

+V1.05S_CORE_PCH

+1.05M_ASW

1

1D5V_S0

+V3.3S_1.8S_LPSS_SDIO

HASWELL-6-GP

1D05V_S0

B B

A A

0R2J-2-GP

0R2J-2-GP R2118

R2118

1 2

12

5

+V1.05S_SSCFF

C2138

SC1U6D3V2KX-GP

C2138

SC1U6D3V2KX-GP

+V1.05S_SSCFF

R2123

HSIOPC20

4

1 2

HSIO

0R2J-2-GP

5V_S5

1D05V_S0

HSIO

HSIOPC_R

12

C2141

C2141 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

X01 change U2101 from 74.22965.093 to 74.59147.093,dummy it. 0409

HASWELL-6-GP

9

U2101

ON

1

VDD

2

D#2

3

D#3 D#44S#5

HSIO

SLG59M1470VTR-GP

74.59147.093

R2122

R2122 0R5J-5-GP

0R5J-5-GP

1 2

Non-HSIO

8

GND

7

S#7

6

S#6

5

3

1D05V_HSIO1D05V_S0

HSIO_OUT

R2114

R2114 0R5J-5-GP

0R5J-5-GP

1 2

HSIO

1D05V_HSIO

HSIO

12

C2142

C2142 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

2

+V3.3S_1.8S_LPSS_SDIO

1 2

12

C2104

SC1U6D3V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (POWER2)

Latitude300 Haswell

0R2J-2-GP

0R2J-2-GP R2103

R2103

1

3D3V_S0

21 104Friday, April 19, 2013

X00

5

4

3

2

1

SSID = PCH

D D

HSW_ULT_DDR3L

CPU1Q

HSW_ULT_DDR3L

17 OF 19

DC_TEST_AY2_AW2

TP2201TP2201

TP2204TP2204

C C

B B

TP_DC_TEST_AY60

1

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

1

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASWELL-6-GP

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HASWELL-6-GP

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

18 OF 19

RSVD#N23 RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7 RSVD#AU10 RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST_A3_B3

A3

TP_DC_TEST_A4DC_TEST_AY3_AW3

A4

TP_DC_TEST_A60

A60

DC_TEST_A61_B61

A61

TP_DC_TEST_A62TP_DC_TEST_B2

A62

TP_DC_TEST_AV1

AV1

TP_DC_TEST_AW1

AW1

DC_TEST_AY2_AW2

AW2

DC_TEST_AY3_AW3

AW3

DC_TEST_AY61_AW61DC_TEST_C1_C2

AW61

DC_TEST_AY62_AW62

AW62

TP_DC_TEST_AW63

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

TP2202TP2202

1

TP2203TP2203

1

TP2205TP2205

1

TP2206TP2206

1

TP2207TP2207

1

TP2208TP2208

1

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Latitude300 Haswell

22 104Tuesday, March 26, 2013

1

X00

5

4

3

2

1

SSID = PCH

D D

HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HSW_ULT_DDR3L

CPU1N

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7

AC61 AD21

AD3

AD63

C C

B B

AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

HASWELL-6-GP

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

HSW_ULT_DDR3L

CPU1O

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASWELL-6-GP

15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Latitude300 Haswell

23 104Tuesday, March 26, 2013

1

X00

SSID = KBC

www.vinaﬁx.vn

1D05V_S0

D D

Layout Note:

Need very close to EC

3D3V_S0

12

C2412

DY

SCD1U10V2KX-5GP

DY

X01 3/5 move WPAN_LED# from GPIO85 to GPIO93

C C

LCD_TST_EN52

Don't PD

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

B B

ALL_SYS_PWRGD de-assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

eDP backlight Control from Travis Travis request response time < 1ms

LCD_TST52

L_BKLT_EN53

R2417 0R2J-2-GPR2417 0R2J-2-GP

5

EC_AGND

12

1 2

EC_VTT

12

C2401

C2414 SCD1U10V2KX-5GPC2414 SCD1U10V2KX-5GP

EC_FB_CLAMP_TGL_REQ#76

OVER_CURRENT_P8#76

TOUCH_PANEL_INTR#52

1 2

R2401

0R2J-2-GP

C2413

C2413 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

R2444 0R2J-2-GPR2444 0R2J-2-GP

VBAT

3D3V_AUX_KBC_VCC

12

C2405

C2404

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

AD_IA44

1 2

CARD_WPAN_OUT#58

PM_SLP_SUS#17,38 BOOST_MON44 DIS_DTM44

FAN1_DAC_126

IMVP_P WR GD7,46

SML1_DATA18,26,53,76

PM_LAN_ENABLE30

RTCRST_ON19

EC_FB_CLAMP75,76,83

ALL_SYS_PWRGD36

PWR_CHG_AD_OFF42

AD_IA_HW244

FAN_TACH126 PM_PWRBTN#17,96 WLAN_LED#61

PM_SLP_S3#17,36,48,49,51

EC_BRIGHTNESS52

AC_IN_KBC#42

CHG_AMBER_LED#61

KBC_DPWROK17

PCH_PWROK17,26,36

USB_PWR_EN#35

AC_PRESENT17,76

SYS_PWROK17,96

CARD_WLAN_OUT#58

WIFI_RF_EN58

PM_SUSWARN#17

PM_CLKRUN#_EC17

AMP_MUTE#27

EC_AGND

EC_VTT

PSID_EC42

AD_IA_HW44

BAT_SCL43,44 BAT_SDA43,44

SML1_CLK18,26,53,76

TPDATA62

BLON_OUT52

PWRLED#61

KBC_BEEP27

E51_TxD58

PCB_VER_AD

MODEL_ID_DET

BAT_SCL BAT_SDA

PROCHOT_EC LCD_TST_EN

ECSWI#_KBC

TPCLK62

L_BKLT_EN_EC

12

C2406

SCD1U10V2KX-5GP

KBC24

19

VCC

46

VCC

76

VCC

88

VCC

115

VCC

102

AVCC

4

VDD

12

VTT

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/EXT_PURST#/AD6

94

GPIO7/AD7/VD_IN2

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

70

GPIO17/SCL1/N2TCK

69

GPIO22/SDA1/N2TMS

67

GPIO73/SCL2/N2TCK

68

GPIO74/SDA2/N2TMS

119

GPIO23/SCL3/N2TCK

120

GPIO31/SDA3/N2TMS

24

GPIO47/SCL4/N2TCK

28

GPIO53/SDA4/N2TMS

26

GPIO51/TA3/N2TCK

123

GPIO67/N2TMS

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27/PSDAT2

25

GPIO50/PSCLK3/TDO

27

GPIO52/PSDAT3/RDY#

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DI O

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM/1_WIRE

81

GPIO66/G_PWM

66

GPO33/H_PWM/VD1_EN#

104

GPIO80/VD_IN1

110

GPIO82/IOX_LDSH/VD_OUT1

112

GPIO84/IOX_SCLK/VD_OUT2

84

GPIO77/SPI_MISO

83

GPIO76/SPI_MOSI

82

GPIO75/SPI_SCK

79

GPIO2/SPI_CS#

124

GPIO10/LPCPD#

121

GPIO85/GA20

111

GPIO83/SOUT_CR

9

GPIO65/SMI#

8

GPIO11/CLKRUN#

30

GPIO55/CLKOUT/IOX_DIN_ DIO

NPCE985PA0DX-1-GP

71.00985.C0G

EC_GPIO47 High Active

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

X01 0408

R2442

100KR2J-1-GP

PROCHOT_EC

12

DY

A A

5

4

0R3J-0-U-GP

12

C2408

C2407

DY

SCD1U10V2KX-5GP

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSOUT0/GPOB0/SOUT_CR/JEN K#

KBSOUT1/GPIOB1/TCK

KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GPI/O63/TRIST# KBSOUT14/GPI/O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

GPIO81/F_WP#/F_SDIO2 GPIO0/EXTCLK/F_SDIO3

PSL_IN2#/GPI6/EXT_PURST#

GPIO46/CIRRXM/TRST #

GPIO87/CIRRXM/SIN_C R

H_PROCHOT#_EC

D

4

R2402

12

2D2R3-1-U-GP

12

C2409

C2410

DY

SCD1U10V2KX-5GP

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

GPIO60/KBSOUT16 GPIO57/KBSOUT17

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

LFRAME#/GPIOF6

LRESET#/GPIOF7

F_CS0#

F_SCK GPIO30/F_WP# GPIO41/F_WP#

F_SDIO/F_SDIO0

F_SDI/F_SDIO1

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

VSBY

VBKUP

VCORF

SERIRQ/GPIOF0

GPIO24

GPIO36/TB3

GPIO44/TDI

GPIO43/TMS

GPIO42/TCK

GPIO34/CIRRXL

AGND

1 2

R2440

0R2J-2-GP

3D3V_AUX_KBC

R2403

12

SC2D2U10V3KX-1GP

PECI

GND GND GND GND GND GND

X01 change R2404 to 20K for PCB version change 0409

1 2

PCB_VER_AD

C2402

12

SCD1U10V2KX-5GP

C2411

KROW0

54

KROW1

55

KROW2

56

KROW3

57

KROW4

58

KROW5

59

KROW6

60

KROW7

61

KCOL0

53

KCOL1

52

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35

KCOL16

34 33

LPC_AD0

126

LPC_AD1

127

LPC_AD2

128

LPC_AD3

1 2 3

PLT_RST#_EC

7

EC_SPI_CS#_C

90

EC_SPI_CLK_C

92 109

BAT_IN#

80

EC_SPI_DI_C

87

EC_SPI_DO_C

86 91 77

PSL_IN1#

73

PSL_IN2#

93

PSL_OUT#

74

ECSCI#_KBC

29

ECRST#

85 122

75

EC_VBKUP

114

KBC_VCORF

44

PECI

13 125

ECSMI#_KBC

6 15

21 20 17 23

113 14

5 18 45 78 89 116

103

EC_AGND

12

C2421

C2421 SC47P50V2JN-3GP

SC47P50V2JN-3GP

DY

VBAT

12

DY

1 2

EC_AGND

KROW[0..7] 62

KCOL[0..16] 62

LPC_AD[3..0] 18,65

CLK_PCI_KBC 18 LPC_FRAME# 18,65

R2422 33R2J-2-GPR2422 33R2J-2-GP R2423 33R2J-2-GPR2423 33R2J-2-GP

H_RCIN# 20

R2428 0R2J-2-GPR2428 0R2J-2-GP

1 2

INT_S ERIRQ 20

BATT_WHITE_LED# 61

PM_SLP_S4# 17,49 RSMRST#_KBC 17 LID_CLOSE# 64 ME_UNLOCK 19

PCIE_WAKE# 17,30 S5_ENABLE 36

R2435

R2435 0R2J-2-GP

0R2J-2-GP

1 2

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2404

R2404 20KR2F-L-GP

20KR2F-L-GP

R2406

R2406 100KR2F-L1-GP

100KR2F-L1-GP

Reserved

Reserved 100.0K 215.0K 1.048V

33R2J-2-GPR2419 33R2J-2-GPR2419

12

33R2J-2-GPR2420 33R2J-2-GPR2420

12

12 12

Layout Note:

Need very close to EC

X01 change PCIE_WAKE# to GPIO87 0409

SPI_CS0#_R 18,25 SPI_CLK_R 18,25 CAP_LED# 62 BAT_IN# 42,43,44 SPI_SI_R 18,25 SPI_SO_R 18,25

PM_SUSACK# 17

PCH_SUSCLK_KBC 17

3D3V_AUX_S5 RTC_AUX_S5

1 2

C2422

SC100P50V2JN-3GPDYC2422

SC100P50V2JN-3GP

12

DY

PURE_HW_SHUTD OWN#26,36,76H_PROCHOT# 4,42,44,46

X01

X02

X03

A00

R2429

R2429 43R2J-GP

43R2J-GP

3

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP C2416

C2416

1 2

3

100.0KX00

100.0K

100.0K 1.358V

R2416

0R2J-2-GP

1 2

C2415

DY

SC220P50V2KX-3GP

1 2

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0KReserved 100.0K

PLT_RST# 17,30,55,58,65,73,96

Power Switch Logic(PSL)

KBC_PWRBTN#61

H_PECI 4

Layout Note:

Need very close to EC C2422 PDG is 47p

3D3V_AUX_S5

R2424

0R2J-2-GP

12

1 2

DY

R2439

R2439 10KR2J-3-GP

10KR2J-3-GP

Q2404

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

3rd = 84.03906.P11

X01 0408

B

AC_IN#44

C2418

12

E

DY

C

ECRST#

SC1U6D3V2KX-GP

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

1 2

R2427

0R2J-2-GP

1 2

R2430

0R2J-2-GP

PSL_OUT#

2

64K9R2F-1-GP

MODEL_ID_DET

SCD1U10V2KX-5GP

3D3V_AUX_S5

1 2

R2432

1 2

1KR2J-1-GP

2

R2446

N14P-GV2

C2403

DY

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

PSL_IN2#

PSL_IN1#

KBC_ON#_GATE_L

12

1 2

EC_AGND

VBAT

12

MODEL_ID_DET(GPIO07)

UMA

R2405

R2405 10KR2F-2-GP

10KR2F-2-GP

UMA

R2407

R2407 100KR2F-L1-GP

100KR2F-L1-GP

TBD TBD TBD 2.702V TBD TBD TBD TBD

DIS

N14M-GE N14P-GV2

TBD TBD TBD TBD TBD TBD TBD TBD TBD

ECSCI#_KBC

ECSMI#_KBC

ECSWI#_KBC

0111 Add

3D3V_AUX_S5 3D3V_AUX_S5

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

1 2

KBC_ON#_GATE

1 2

R2433

R2433 20KR2F-L-GP

20KR2F-L-GP

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

BAT_SCL BAT_SDA

ECRST#

X01 Modify R2414 from 100K to 10K 0409

AC_IN# BAT_IN#

AC_IN_KBC#

FAN_TACH1

TOUCH_PANEL_INTR#

LID_CLOSE#

C2417

C2417 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

G

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

X01 0408

Q2403

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

X01 0408

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Date: Sheet of

1

100.0K 3.0V

100.0K

S

G

D

Latitude300 Haswell

Friday, April 19, 2013

10.0K(64.10025.6DL)

13.7K(64.13725.6DL)

17.8K(64.17825.6DL)

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

57.6K(64.57625.6DL)

64.9K(64.64925.6DL)

73.2K(64.73225.6DL) 1.905V

82.5K(64.82525.6DL) 1.808V

93.1K(64.93125.6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)

R24080R2J-2- GP R24080R2J- 2-GP

12

R24090R2J-2- GP R24090R2J- 2-GP

12

R24100R2J-2- GP R24100R2J- 2-GP

12

3D3V_AUX_KBC

RN2401

23 1

4

SRN4K7J-8-GP

R2418 10KR2J-3-GPR2418 10KR2J-3-GP

1 2

R2413 100KR2J-1-GP

R2413 100KR2J-1-GP R2414 10KR2J-3-GPR2414 10KR2J-3-GP

R2426 100KR2J-1-GPR2426 100KR2J-1-GP

R2415 10KR2J-3-GPR2415 10KR2J-3-GP R2443 10KR2J-3-GPR2443 10KR2J-3-GP

D

3D3V_AUX_KBC

1 2

DY

1 2

3D3V_S0

1 2 1 2

3D3V_S5

R2421 100KR2J-1-GP

1 2

DY

R2434

DY

0R2J-2-GP

1 2

3D3V_AUX_KBC

KBC Nuvoton NPCE885

3D3V_AUX_KBC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

24 104

EC_SWI# 20

1

2.902V

2.801V

2.598V

2.492V

2.402V

2.304V

2.201V49.9K (64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

EC_SCI# 18,20

EC_SMI# 19

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

X00

5

SSID = Flash.ROM

4

3

2

1

R2501

4K7R2J-2-GP

12

DY

3D3V_S5

1 2

1203 RN2501 DY

4

RN2501

RN2501 SRN4K7J-8-GP

SRN4K7J-8-GP

DY

1

2 3

SPI25

1

CS#

2

DO/IO1

3 4

HOLD#/IO3 WP#/IO2 GND

W25Q64FVSSIQ-GP

72.25Q64.K01

2nd = 72.25647.00A

8

VCC

7 6

CLK

5

DI/IO0

SC4D7P50V2CN-1GP

SC10U6D3V5KX-1GP

3D3V_S5

12

EC2501

DY

C2501

12

DY

SPI Flash ROM(8M) for PCH

D D

SPI_CS0#_R18,24

SPI_SO_R18,24

SPI_WP#18

EC2502

SC4D7P50V2CN-1GP

EC2502

3D3V_S5

12

DY

SPI_HOLD# 18 SPI_CLK_R 18,24 SPI_SI_R 18,24

EC2503

EC2503 SC10P50V2JN-4GP

SC10P50V2JN-4GP

12

C2502

C2502 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Single SPI shared flash connection (SPI Quad I/O mode)

X01 0408

C C

SPI_CS0#_R SPI_SO_R SPI_WP#

SKT25

1

8

2

7

DY

3 6 4

5

SKT-G6179HT0321-001-GP

62.10089.011

3D3V_S5

SPI_HOLD# SPI_CLK_R SPI_SI_R

72.25Q64.K01

72.25Q64.F01

72.25Q64.D01

QUAD/DUAL fast read DUAL fast readSource

O

Refer to "NCPE985x/ NPCE995x board design reference guide"

O

SSID = RBATT

B B

TP2502TPAD14-OP-GP TP2502TPAD14-OP-GP

RTC1

PWR

GND

NP1 NP2

BAT-060003HA002M213ZL-GP-U1

62.70014.001

2nd = 62.70001.061

3rd = 20.F2316.002

1 2 NP1 NP2

+RTC_VCC

1

R2502

1KR2J-1-GP

TP2501

TPAD14-OP-GP

12

RTC_PWR

D2501

1

2

BAS40-05-7-F-1-GP

75.00040.A7D

2nd = 83.00040.E81

X01 0408

Q2505

A A

5

4

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

X01 0408

D

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

3

C2503

SC1U6D3V2KX-GP

1 2

RTC_DET# 20

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, April 19, 2013

Date: Sheet of

3

2

Date: Sheet of

Flash/RTC

Latitude300 Haswell

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 104

1

X00

5

4

3

2

1

SSID = Thermal

Fan controller1

FAN1

3 2

1

AFTP2803AFTP2803

5V_S0

12

C2605

C2611

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

5

4

1

FAN261

R2605

0R2J-2-GP

1 2

5V_S0

FAN_TACH124

SC4D7U6D3V3KX-GP

12

EC2602

SC10P50V2JN-L1-GP

DY

FAN_VCC1

C2604

12

DY

FAN_TACH1

FAN_VCC1

12

EC2601

DY

6

5

8 7

ALERT#

6 5

3D3V_S0 3D3V_S0

1

2

34

Q2601

Q2601 2N7002KDW-GP

2N7002KDW-GP

Q2602

G

D

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

X01 0408

1

23

RN2602

RN2602 SRN2K2J-1-GP

SRN2K2J-1-GP

4

84.2N702.A3F

2nd = 75.00601.07C

3rd = 84.2N702.E3F

4th = 84.DMN66.03F

X01 0408

12

DY

C2608

SCD1U10V2KX-5GP

12

C2610

DY

SCD1U10V2KX-5GP

THM_SML1_DATA

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DATA

12

C2609

SCD1U10V2KX-5GP

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW_SHUTDOW N# 24,36,76

FAN1_DAC_124

Layout Note:

Need 10 mil trace width.

D D

3D3V_S0

SML1_DATA18,24,53,76

12

X01 DY C2601 0410

DY

12

X01 0408

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

C C

2.System Sensor, Put on palm rest

3D3V_S0

B B

3rd = 84.03904.T11

3

Q2603

PMBS3904-1-GP

2

R2603 18K7R2F-GPR2603 18K7R2F-GP

R2604 2KR2F-3-GPR2604 2KR2F-3-GP

12

C2606

DY

1 2

C2606 SC470P50V3JN-2GP

SC470P50V3JN-2GP

1

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2602

C2601

SC10U6D3V3KX-GP

SCD1U10V2KX-5GP

NCT7718_DXP

12

NCT7718_DXN

Layout Note:

C2812 close U2801

ALERT#

T_CRIT#

C2607

C2607 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

12

T_CRIT#

R2601

R2601 0R2J-2-GP

0R2J-2-GP

SML1_CLK18,24,53,76

THM26

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

SCL SDA

ALERT#

1203 change to ALL_SYS_PWRGD

PCH_PWROK17,24,36

THERM_SYS_SHDN#

FAN261

FON#

1

FSM#

2

VIN

3

VOUT VSET4GND

APL5606AKI-TRG-GP

74.05606.A71

2nd = 74.03940.A71

3rd = 74.02113.0E1

X01 0410

R2606

0R2J-2-GP

1 2

21

D2601

DY

CH551H-30PT-GP

83.R5003.C8F

2nd = 83.R5003.H8H

3rd = 83.5R003.08F

SCD1U10V2KX-5GP

GND GND GND

FAN_TACH1_C

FAN_VCC1

12

C2603

DY

SC2200P50V2KX-2GP

8 7 6 5

AFTP2802AFTP2802 AFTP2801AFTP2801

ETY-CON3-8-GP

20.F1841.003

2nd = 20.F1295.003

X01 0408

FAN_TACH1_C

1

FAN_VCC1

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, April 19, 2013

Date: Sheet of

Reserved

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

26 104

1

X00

SSID = AUDIO

5

4

3

2

1

12

C2702

C2702 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

LDO1_CAP

25

26

27

AVSS1

AVDD1

LDO1_CAP

LINE2_L

LINE2_R

LINE1_L

LINE1_R

CPVREF

MIC_CAP

MIC2_R/SLEEVE

MIC2_L/RING2

MONO_OUT

SENSE_B

SENSE_A

12

AUD_PC_BEEP

MIC2_VREFO 29

AUD_AGND

+5V_AVDD

AUD_AGND

JDREF

+3V_AVDD

24

23

22

21

20

19

18

17

16

15

14

13

MIC_CAP

JDREF

AUD_SENSE_A

12

C2710

C2711

SCD1U10V2KX-5GP

AUD_AGND

SC4D7U6D3V3KX-GP

LINE1_L 29

LINE1_R 29

C2713 SC10U6D3V3KX-GPC2713 SC10U6D3V3KX-GP

1 2

SLEEVE 29

RING2 29

R2707 20KR2F-L-GPR2707 20KR2F-L-GP

1 2

AUD_SENSECOMBO-GPI

1 2

R2709

39K2R2F-L-GP

Layout Note:

Place close to Pin 13

HDA_SPKR20

KBC_BEEP24

5V_S0+5V_AVDD

R2703

1 2

0R3J-0-U-GP

Layout Note:

Place close to Pin 26

AUD_AGND

Layout Note:

Width>40mil, to improve Headpohone Crosstalk noise

AUD_AGND

AUD_SENSE 29

RN2701

2 3 1

4

SRN0J-6-GP

AUD_AGND

HDA_SPKR_R

KBC_BEEP_R

EC2707 SC1KP25V2JX-GPEC2707 SC1KP25V2JX-GP

1 2

EC2706 SC1KP25V2JX-GPEC2706 SC1KP25V2JX-GP

1 2

EC2705 SC1KP25V2JX-GPEC2705 SC1KP25V2JX-GP

1 2

EC2704 SC1KP25V2JX-GPEC2704 SC1KP25V2JX-GP

1 2

EC2703 SC1KP25V2JX-GPEC2703 SC1KP25V2JX-GP

1 2

R2706

1 2

0R5J-6-GP

Layout Note:

Tied at point only under Codec or near the Codec

BAT54CPT-2-GP

2

AUD_PC_BEEP_C

3

1

D2701

75.00054.K7D

2nd = 75.00054.J7D

3rd = 75.00054.A7D

X01 0408

SCD1U10V2KX-5GP

C2720

1 2

12

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

AUD_PC_BEEP

SC1U10V2KX-1GP

SC10U6D3V3KX-GP

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

SC4D7U6D3V3KX-GP

LINE1_VREFO_R29

LINE1_VREFO_L29

AUD_HP1_JACK_L29

AUD_HP1_JACK_R29

12

C2703

HDA27

CBP

37

CBP

38

AVSS2

LDO2_CAP

39

LDO2_CAP

40

AVDD2

41

PVDD1

42

SPK_L+

43

SPK_L-

44

SPK_R-

45

SPK_R+

46

PVDD2

EAPD#

47

PDB

48

SPDIFO/GPIO2

49

GND

ALC3223-CG-GP

+3V_AVDD

12

C2716

C2717

1 2

R2714 0R2J-2-GPR2714 0R2J-2-GP

1 2

R2716 0R2J-2-GPR2716 0R2J-2-GP

1 2

R2719 0R2J-2-GPR2719 0R2J-2-GP

1 2

R2720 0R2J-2-GPR2720 0R2J-2-GP

1 2

R2718 0R2J-2-GPR2718 0R2J-2-GP

HDA_CODEC_SYNC

HDA_CODEC_RST#

SC1U10V2KX-1GP

SC1U10V2KX-1GP C2704

C2704

1 2

+3V_AVDD

CPVEE

CBN

31

32

33

34

35

36

CBN

CPVEE

CPVDD

HP_OUT_L

HP_OUT_R

LINE1_VREFO_L

DVDD1GPIO0/DMIC_DATA2GPIO1/DMIC_CLK3DVSS4SDATA_OUT5BIT_CLK6LDO3_CAP7SDATA_IN8DVDD_IO9SYNC10RESET#11PCBEEP

12

SCD1U10V2KX-5GP

DMIC_DATA_R

DMIC_CLK_R

CODEC_SDOUT_R

CODEC_BITCLK_R

HDA_CODEC_SDIN0

LDO3_CAP

C2705

12

SC2D2U6D3V2MX-GP

AUD_VREF

28

29

30

VREF

MIC2_VREFO

LINE1_VREFO_R

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

C2719SCD1U10V2KX-5GP C2719SCD1U10V2KX-5GP

D D

3D3V_S0 +3V_AVDD

25mA

R2701 0R2J-2-GPR2701 0R2J-2-GP

1 2

1.5A

5V_S0 +5V_PVDD

R2702

0R5J-5-GP

12

R2704

0R5J-5-GP

12

C C

3D3V_S0

1D5V_S0

R2705 0R2J-2-GPR2705 0R2J-2-GP

1 2

R2710 0R2J-2-GP

1 2

DY

Add R2710 DY(3D3V_S0)

Azalia I/F EMI

EC2708

12

DY

SCD1U10V2KX-5GP

B B

Layout Note:

Close pin41

HDA_CODEC_SDOUT HDA_CODEC_BITCLK

EC2709

12

DY

SCD1U10V2KX-5GP

AUD_AGND

C2706

12

SC4D7U6D3V3KX-GP

12

C2701

SC4D7U6D3V3KX-GP

Close pin36

C2707

C2708

12

SCD1U10V2KX-5GP

Layout Note:

Close pin46

+3V_1D5V_AVDD

12

C2715

C2715 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

AUD_AGND

C2709

12

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

Close pin40

AUD_AGND

AMP_MUTE#24

C2712

AUD_SPK_L+29

AUD_SPK_L-29

AUD_SPK_R-29

AUD_SPK_R+29

1 2

R2708 0R2J-2-GPR2708 0R2J-2-GP

1 2

remove D2702 R2710 R2711 Add R2708_0R(PDB pin)

TP2702TP2702

DMIC_CLK52

SC22P50V2JN-4GP

Close pin3

C2723

DY

1 2

DMIC_DATA52

HDA_CODEC_SDOUT19

HDA_CODEC_BITCLK19

HDA_SDIN019

HDA_CODEC_SYNC19

HDA_CODEC_RST#19,29

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Audio Codec ALC3221

Latitude300 Has well

1

27 104Friday, April 19, 2013

X00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

28 104Tuesday, March 26, 2013

X00

5

4

3

2

1

SSID = AUDIO

Speaker

SPK1

AUD_SPK_R+_C

R29040R3J-0-U-GP R29040R3J-0-U-GP

D D

AUD_SPK_R+27

AUD_SPK_R-27 AUD_SPK_L+27 AUD_SPK_L-27

12

DY

EC2902

EC2903

EC2901

SC2K2P50V3KX-GP

EC2903

SC2K2P50V3KX-GP

DY

12

DY

EC2904

SC2K2P50V3KX-GP

12

R29030R3J-0-U-GP R29030R3J-0-U-GP

12

R29020R3J-0-U-GP R29020R3J-0-U-GP

12

R29010R3J-0-U-GP R29010R3J-0-U-GP

12

AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C

2nd = 20.F1639.004

3rd = 20.F1804.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

5

1

2 3 4

6

ACES-CON4-7-GP-U

20.F0772.004

X01 0408

1 1 1 1

AFTP5801AFTP5801 AFTP5802AFTP5802 AFTP5803AFTP5803 AFTP5804AFTP5804

CONN Pin

Pin1

Pin2

Pin3

Pin4

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L_

C C

RN2901

1

MIC2_VREFO27

RING227

AUD_HP1_JACK_L27

LINE1_L27

LINE1_VREFO_L27

AUD_SENSE27

AUD_HP1_JACK_R27

LINE1_R27

LINE1_VREFO_R27

SLEEVE27

C2907

C2907 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C2908

C2908 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1 2

LINE1-L_C

LINE1-L_R

4

2 3

SRN2K2J-3-GP

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 2K2R2J-2-GPR2912 2K2R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 2K2R2J-2-GPR2913 2K2R2J-2-GP

1 2

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EC2908

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

R2920

10KR2J-3-GP

R2920

10KR2J-3-GP

12

DY

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

12

SC100P50V2JN-3GPDYEC2906

SC100P50V2JN-3GP

R2919

10KR2J-3-GP

R2919

10KR2J-3-GP

12

DY

EC2906

DY

AUD_AGND

EC2905

SC100P50V2JN-3GPDYEC2905

SC100P50V2JN-3GP

12

DY

AUD_PORTA_L_R_B AUD_PORTA_R_R_B

AUD_SENSE

R29060R3J-0-U-GP R29060R3J-0-U-GP

12

R29070R3J-0-U-GP R29070R3J-0-U-GP

12

R29090R3J-0-U-GP R29090R3J-0-U-GP

12

R29110R3J-0-U-GP R29110R3J-0-U-GP

12

AFTP2906AFTP2906

1

AFTP2907AFTP2907

1

AFTP2908AFTP2908

1

AFTP2909AFTP2909

1

RING2_R

AUD_PORTA_L_R_B

AUD_PORTA_R_R_B

SLEEVE_R

Combo Jack

AUD_AGND

HPMIC1

3 1

5 6 2 4 7

AUDIO-JK363-GP

22.10270.P81

2nd = 22.10270.P91

X01 0408

B B

AUD_AGND AUD_AGND

1227 modify

AUD_PORTA_R_R_B

AUD_PORTA_L_R_B

RING2_R

AUD_SENSE

SLEEVE_R

AZ2025-01H-R7G-GP

ED2901

A A

DY

1 2

AUD_AGND AUD_AGND AUD_AGND AUD_AGNDAUD_AGND

5

DY

AZ2025-01H-R7G-GP

ED2902

1 2

DY

AZ2025-01H-R7G-GP

ED2903

1 2

DY

AZ2025-01H-R7G-GP

ED2904

ED2905

DY

1 2

4

12

R2915

R2915 470KR2J-2-GP

470KR2J-2-GP

AUD_AGND

U2901

S

G

5

D

6

DMN66D0LDW-7-GP

84.DMN66.03F

R2918

100KR2J-1-GP

D

34

G

MUTE_CTRLSLEEVE_CTRL

2

S

1

3

+3V_AVDD5V_PWR_2

12

DY

R2917 0R2J-2-GPR2917 0R2J-2-GP

1 2

12

C2901

C2901 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

HDA_CODEC_RST# 19,27

SLEEVE 27

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Latitude300 Haswell

Friday, April 19, 2013

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

29 104

1

X00

5

4

3

2

1

10/100 Need Only need C3021, C3022, C3023, C3024 in Pin3, 8, 22, 30

L3010

REGOUT

D D

L3010

1 2

IND-4 D7UH -242-G P

68.4R71E.10G

2nd = 68.4R790.201

X01 0408

12

C3012

12

SC4D7U6D3V3KX-GP

C3019

SCD1U16V2ZY-2GP

VDD10

12

C3022

C3021

SCD1U10V2KX-4GP

12

C3023

C3024

SCD1U10V2KX-4GP

C3024

SCD1U10V2KX-4GP

LAN CHIP

R3032

R3032 2K49R2F-GP

2K49R2F-GP

1 2

LAN_TXP_C_PCH_RXP4 LAN_TXN_C_PCH_RXN4

PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C

C3014 SCD1U10V2KX-5GPC3014 SCD1U10V2KX-5GP

1 2 1 2

C3016 SCD1U10V2KX-5GPC3016 SCD1U10V2KX-5GP

PCIE_PRX_LANTX_P4 16 PCIE_PRX_LANTX_N4 16

PCIE_PTX_LANRX_P4_C 16 PCIE_PTX_LANRX_N4_C 16

CLK_PCIE_LAN_P4 18 CLK_PCIE_LAN_N4 18

X5R

LED0

TP3003 TPAD14-OP-GPTP3003 TPAD14-OP-GP

1

LED1

TP3002 TPAD14-OP-GPTP3002 TPAD14-OP-GP

RSET

LANXOUT

VDD10

3D3V_LAN_S5

29

30

31

GND

MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 MDIP2 MDIN2 AVDD10

32

RSET

AVDD10

AVDD33

MDIP39MDIN310AVDD3311CLKREQB12HSIP13HSIN14REFCLK_P15REFCLK_N

LOM30

40 mils

C C

B B

3D3V_LAN_S5 VDDREG

R3006

1 2

0R3J-0-U-GP

3D3V_LAN_S5

1

23

DY

4

Q402_1

1

2

DY

Q3003

Q3003 PMBS3904-1-GP

PMBS3904-1-GP R3016

R3016

0R2J-2-GP

SCD1U10V2KX-5GP

0R3J-0-U-GP

RN3001

SRN10KJ-5-GP

3

12

R3021

R3021 10KR2J-3-GP

10KR2J-3-GP

R3022

R3022 20KR2F-L-GP

20KR2F-L-GP

1 2

PLT_RST#_LAN

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

PM_LAN_ENABLE_R

12

C3009

SCD1U16V2ZY-2GP

12

EC3001

DY

C3015

12

SC1U10V2KX-1GP

12

C3010

SC4D7U6D3V3KX-GP

12

DY

SCD1U16V2KX-3GP

251mA

DMP2130L-7-GP

S

12

2nd = 84.03904.P11

3rd = 84.03904.T11

PLT_RST#17,24,55,58,65,73,96

12

C3008

C3007

SCD1U10V2KX-4GP

84.03904.L06

X01 0408

3D3V_S5

SCD1U10V2KX-4GP

C3013

12

LAN_MDI0P31 LAN_MDI0N31

LAN_MDI1P31

LAN_MDI1N31 LAN_MDI2P31 LAN_MDI2N31

LAN_MDI0P LAN_MDI0N LAN_MDI1P LAN_MDI1N

12

EC3003

EC3002

DY

SCD1U16V2KX-3GP

X01 Q3004 change main source to 84.02130.031 0409

Q3004

D

G

DY

D

EC3004

SCD1U16V2KX-3GP

3D3V_LAN_S5

main: 84.00102.031 2nd: 84.03403.031

12

DY

C3017

LAN_MDI3P31 LAN_MDI3N31

SCD1U10V2KX-4GP

R3024 0R2J-2-GPR3024 0R2J-2-GP

12

R3025 0R2J-2-GPR3025 0R2J-2-GP

12

R3026 0R2J-2-GPR3026 0R2J-2-GP

12

R3027 0R2J-2-GPR3027 0R2J-2-GP

12

R3028 0R2J-2-GPR3028 0R2J-2-GP

12

R3029 0R2J-2-GPR3029 0R2J-2-GP

12

R3030 0R2J-2-GPR3030 0R2J-2-GP R3031 0R2J-2-GPR3031 0R2J-2-GP

X00 3/7 Change value from test report

LANXOUT

LANXIN

LAN_MDI0P_1 LAN_MDI0N_1 VDD10 LAN_MDI1P_1 LAN_MDI1N_1 LAN_MDI2P_1 LAN_MDI2N_1 VDD10

RTL8111GUS-CGT-GP

71.08111.X03

12 12

41

33

1 2 3 4 5 6 7 8

LAN_MDI3P_1 LAN_MDI3N_1

3D3V_LAN_S5 CLK_LAN_REQ4#_R PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C CLK_PCIE_LAN_P4 CLK_PCIE_LAN_N4

C3011

1 2

SC15P50V2JN-2-GP

X3001

X3001 XTAL-25MHZ-155-GP

XTAL-25MHZ-155-GP

82.30020.D41

2 3

2nd = 82.30020.K51

3rd = 82.30020.G71

4th = 82.30020.G61

X01 0408

C3001

1 2

SC15P50V2JN-2-GP

1

LANXIN

LED2

TP3001 TPAD14-OP-GPTP3001 TPAD14-OP-GP

1

25

26

27

LED2

LED0

CKXTAL128CKXTAL2

LED1/GPO

LANWAKE#

ISOLATE#

16

REGOUT VDDREG

DVDD10

PERST#

HSON HSOP

REGOUT

24

VDDREG

23

VDD10

22

PCIE_WAKE#

21

ISOL ATE#

20

PLT_RST#_LAN

19

LAN_TXN_C_PCH_RXN4

18

LAN_TXP_C_PCH_RXP4

17

PCIE_WAKE#

CLK_PCIE_LAN_REQ4#18,20

C3018

1 2

SC1U10V2KX-1GP

C3025

R3033

1 2

10KR2J-3-GP

SC1U10V2KX-1GP

1 2

SCD1U10V2KX-4GP

PCIE_WAKE# 17,24

12

R3015

15KR2F-GP

X01 0405 change PCIE_WAKE# power to 3D3V_S5

3D3V_S5

3D3V_LAN_S5

12

R3003

10KR2J-3-GP

CLK_LAN_REQ#_EN

DY

Q3002

0R2J-2-GP

DY

312

R3005

12

X01 0408

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

PMBS3904-1-GP

3D3V_S0

12

R3014

R3014 1KR2J-1-GP

1KR2J-1-GP

12

R3004

R3004 10KR2J-3-GP

10KR2J-3-GP

DY

CLK_LAN_REQ4#_R

Q3001

12

5

Q3001

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

X01 0408

LAN_ENABLE_R_C

D

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Latitude300 Haswell

Taipei Hsien 221, Taiwan, R.O.C.

LOM

1

30 104Friday, April 19, 2013

X00

A A

PM_LAN_ENABLE24

R3023

100KR2J-1-GP

Dell Latitude 300 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual