DELL D520 Schematics
1
2
3
4
5
6
7
8
DRAM Power
DC/DC
A A
+3V_SRC
+5VSUS
PG 46
IMVP-6
CPU VR
PG 45
RUN POWER
SW
PG 47
POWER DC/DC
B B
DDR2-SODIMM1
AC/BATT
CONNECTOR
BATT
SELECTOR
BATT
CHARGER
400/533/667 MHZ DDR II
1.8V, 0.9V
PG 43
1.5VSUS, 1.05V
PG 44
PG 48
PG 41
PG 42
PG 15,16
400/533/667 MHZ DDR II
DDR2-SODIMM2
PG 15,16
SATA - HDD
SATA
PG 21
Internal Media Bay
C C
CD-ROM
PG 21
ATA 66/100
USB2.0(P2)
AC97/Azalia
AUDIO
STAC9200
PG 34,35
MDC
PG 26
SPI
S/PDIF to
DOCK
D D
PG 39
Audio
Jacks
PG 35
RJ11 to
DOCK
PG 39
Tip
Ring
PG 26
Flash
PG 30
1
2
SHELBY-INTEGRATED
DMI X4 Interface
SPI
SIO MEC5004
128KB Flash
TMKBC
128 Pins VTQFP
PG 27
Keyboard
PG 27
Touchpad
PG 31
3
Yonah
(478 Micro-FCPGA)
PG 3,4
533/667
MHz FSB
Calistoga
1466 uFCBGA
PG 5,6,7,8,9,10
ICH7-M
652 BGA
PG 11,12,13,14
LPC
USB2.0 (P1)
SIO ECE5018
Expander
BC
USB 2.0 Hub(4)
128 Pins VTQFP
PG 28
PS/2
IrDA
PG 38
sDVO
USB2.0 (P5,P6)
USB2.0 (P3,P4)
USB2.0 (P7)
PCIE
ECE_USB2.0(P1)
ECE_USB2.0(P2)
Serial
PG 29
4
CLOCKS
ICS954301
PG 17
SI1362
PG 18
1394 CONN
PG 25
USB2.0 (P0)
MINI-PCIE
Wireless LAN
PG 23
Bluetooth
PG 31
5
2 Rear Ports
2 right Side
SYSTEM
RESET CKT
PG 40
LVDS
DVI
TVOUT
VGA
33MHz PCI
CARDBUS
OZ711
PG 24
PG 33
PG 33
PCMCIA
CON.
PG 24
DOCK LPC
6
SWTICH & LED &
IO CONN
PG 33
FAN & THERMAL
PG 32
Panel Connector
PG 19
S-Video
PG 20
CRT
PG 20
DOCKING
CONNECTOR
LAN (100/10)
BCM4401
PG 36
E-Switch
PI3L110Q
PG 37
I/O Board CONN
PG 33
PG 39
QUANTA
Title
Size Document Number Rev
Date: Sheet
COMPUTER
Schematic Block Diagram1
DM5 1A
星期二
27, 2005
十二月
7
of
159,
8
1
Pg# Description
1
Schematic Block Diagram 1
2
Front Page
3-4
A A
B B
C C
Yonah
5-10
Calistoga
11-14
ICH7
15-16
DDRII SO-DIMM(200P)
17
Clock Generator
18
SI1362
19
LCD Conn. & SSP
20
CRT & TV Conn.
21
SATA & IDE Conn.
22
PAD & Screw Hole
23
MiniCard
24
PCCARD&CONN
25
1394
26
MDC Conn.
27-28
SIO (MEC5004 & ECE5018)
29
Serial Port
30
Flash ROM
31
Touch Pad CONN.& Bluetooth CONN
FAN & Thermal
32
33
Switch Board Conn. & LED & IO Board
34-35
Azelia CODEC (STAC9751) & Phone Jack
LAN BCM4401 10/100
36
LAN SWITCH / LAN POWER
37
38
FIR
2
INDEX
3
DNI LIST
4
5
6
Power & Ground
Label Description
DC_IN+
PBATT+
PWR_SRC
VHCORE
1.05V AGTL+ POWER (1.05V) I/O
+3VRUN
+3VSUS
+5VALW
+5VRUN
+5VSUS
+5VHDD
+5VMOD
STRB#/5V
+5VRUN
VDDA
1_8VSUS
1_8VRUN
+3VALW 8051 POWER (3V)
V1_5RUN
GND ALL PAGES DIGIT AL GROUND
Pg#
AC ADAPTER (20V)
MAIN BATTERY + (10~17V)
MAIN POWER (10~20V)
CPU CORE POWER (1.25/1.15V)
SLP_S3# CTRLD POWER
SLP_S5# CTRLD POWER
8051 POWER (5V)
SLP_S3# CTRLD POWER
SLP_S5# CTRLD POWER
HDD POWER (5V)
MODULE POWER (5V)
EXTERNAL FDD POWER (5V)
FAN POWER (5V)
AUDIO ANALOG POWER (5V)
RESUME WELL IN ICH
SLP_S3# CTRLD POWER
ALVISO POWE R Non -CPU I/O
COMBO CONN GND
7
8
Control Signal
RUNPWROK
RUNPWROK
RUN_ON
SUS_ON
RUN_ON
SUS_ON
HDDC_EN#
MODC_EN#
FDD/LPT#
FAN_OFF/ON#
RUN_ON
39 Docking Conn.
40
SYSTEM RESET/POWER GOOD
41-42
Battery Selector & Charger
43
1.8VSUS/0.9V
44
1.5V/1.05V
45
CPU Power
D D
46
D/D Power
47
RUN Power Switch
48
DCIN , Batt
49
Power Block Diagram
50
SMBUS Block Diagram
1
QUANTA
Title
Size Document Number Rev
2
3
4
5
6
Date: Sheet
COMPUTER
Index, DNI, Power & Ground
DM5 3A
星期二
27, 2005
十二月
7
of
259,
8
1
2
3
4
5
6
7
8
M23
R24
N24
M24
N25
M26
AD26
C26
D25
C21
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
H26
F26
K22
H25
H23
G22
N22
K25
P26
R23
L25
L22
L23
P25
P22
P23
T24
L26
T25
B22
B23
J24
J23
J26
U6B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
BSEL[0]
BSEL[1]
BSEL[2]
Yonah
DATA GRP 0 DATA GRP 1
MISC
PWRGOOD
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
DATA GRP 2
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
DATA GRP 3
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
SLP#
PSI#
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0V_CPU_BTLREF
COMP1
COMP2
COMP3
H_D#[0..63]
H_D#[0..63]
H_DPRSTP# 11,45
H_DPSLP# 11
H_DPWR# 5
H_PWRGOOD 11
H_CPUSLP# 5,11
H_PSI# 45
H_D#[0..63] 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5
H_D#[0..63] 5
H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5
R156
R154
54.9/F
Comp0,2 connect with Zo=27.4ohm.
Comp1,3 connect with Zo=55ohm,
make these t race length shorter than 0.5".
27.4/F
1 2
54.9/F
1 2
R155
27.4/F
1 2
R158
1 2
AA1
AA4
AB2
AA3
B25
M3
K5
M1
N2
N3
P5
P2
L1
P4
P1
R1
L2
K3
H2
K2
L5
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
J4
L4
J1
J3
U6A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]#
RSVD[02]#
RSVD[03]#
RSVD[04]#
RSVD[05]#
RSVD[06]#
RSVD[07]#
RSVD[08]#
RSVD[09]#
RSVD[10]#
RSVD[11]#
Yonah
ADDR GROUP 0
DEFER#
CONTROL
RESET#
XDP/ITP SIGNALS
PROCHOT
THERMDA
THERMDC
THERMTRIP#
THERMH CLK
RSVD[12]#
RSVD[13]#
RSVD[14]#
RSVD[15]#
RSVD[16]#
RESERVED
RSVD[17]#
RSVD[18]#
RSVD[19]#
RSVD[20]#
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
BCLK[0]
BCLK[1]
TDI
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
H_INIT#
B3
H4
H_RESET#
B1
F3
F4
G3
G2
G6
E4
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
ITP_BPM#5
AC1
ITP_TCK
AC5
ITP_TDIH_A#26
AA6
ITP_TDO
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
C20
H_PROCHOT#
D21
H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP#
C7
A22
A21
T22
D2
F6
D3
C1
AF1
D22
C23
C24
H_ADS# 5
H_BNR# 5
H_BPRI# 5
H_DEFER# 5
H_DRDY# 5
H_DBSY# 5
H_BR0# 5
H_INIT# 11
H_LOCK# 5
H_RESET# 5
H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5
H_HIT# 5
H_HITM# 5
ITP_DBRESET# 13,27
H_THERMDA 32
H_THERMDC 32
H_THERMTRIP# 32
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
H_THERMTRIP#
H_IERR#
Routing together
Trace width/Spacing
=10/10 mil
R31 56
1 2
R165 56
1 2
+1.05V_VCCP
H_D#[0..63]5
H_D#[0..63]5
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V_VCCP
R146
1K/F
CT_1214:Change R29
from 51_NC to 1K_NC
R142
2K/F
H_D#[0..63]
H_DSTBN#05
H_DSTBP#05
H_DINV#05
H_D#[0..63]
H_DSTBN#15
H_DSTBP#15
H_DINV#15
R29 *1K_NC
1 2
51
1 2
R28
Pop R28 for Yonah B0 & forward
CPU_MCH_BSEL06,17
CPU_MCH_BSEL16,17
CPU_MCH_BSEL26,17
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
TEST1
TEST2
H_DPRSTP#
H_DPSLP#
Populate for Yonah A0,
de-pop for Yonah A1
R30 *56_NC
1 2
R32 *56_NC
1 2
H_A#[3..31]5
A A
H_ADSTB#05
H_REQ#05
H_REQ#15
H_REQ#25
H_REQ#35
H_REQ#45
H_A#[17..31]5
B B
H_ADSTB#15
H_A20M#11
H_FERR#11
H_IGNNE#11
H_STPCLK#11
H_INTR11
H_NMI11
H_SMI#11
C C
H_A#[3..16]
H_A#[17..31]
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_SMI#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19 ITP_BPM#0
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
+1.05V_VCCP +1.05V_VCCP
R220
R221
39.2/F
51
R219 22.6/F
R217 22.6/F
12
12
R222
150
1
2
5
7
3
12
11
8
9
10
14
16
18
20
22
JITP1
TDI
TMS
TCK
TDO
TRST#
RESET#
FBO
BCLKN
BCLKP
GND0
GND1
GND2
GND3
GND4
GND5
*ITP700_NC
2
VTT0
VTT1
VTAP
DBR#
DBA#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
NC0
NC1
+1.05V_VCCP +3.3V_SUS
27
28
26
1 2
25
24
ITP_BPM#0
23
ITP_BPM#1
21
ITP_BPM#2
19
ITP_BPM#3
17
ITP_BPM#4
15
ITP_BPM#5
13
4
6
3
C337
0.1U_10V
12
R215
150
+1.05V_VCCP
12
R216
*54.9/F_NC
H_PROCHOT# CPU_PROCHOT#
ITP disable guidelines
Signal Resistor Value Connect To Resistor Placement
150 ohm +/- 5%
TDI
39 ohm +/- 5%
TMS
680 ohm +/- 5%
TRST#
27 ohm +/- 5%
TCK
Open
TDO
ITP_EN R268 Depop +3VRUN Close to CK410M Pin8
Note: Populate R214, R216, C366, and R268 when ITP connector is populated.
4
VTT
VTT
GND
GND
VTT
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
5
12
R218
51/F
1 2
ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO
ITP_TRST#
H_RESET# ITP_DBRESET#
ITP_TCK
D D
CLK_CPU_ITP#17
CLK_CPU_ITP17
R150 27.4/F
ITP_TCK
1 2
ITP_TRST#
1 2
R153 680
1
1 2
1 2
+1.05V_VCCP
R168
75/F
1 2
0_0402
R448
6
CPU_PROCHOT# 28
QUANTA
Title
Size Document Number Rev
Date: Sheet
COMPUTER
Yonah Processor (HOST)
DM5 1A
星期二
27, 2005
十二月
7
of
359,
8
1
2
3
4
5
6
7
8
+VCC_CORE
C266
10U_4V
A A
C64
10U_4V
C60
10U_4V
B B
C C
C272
10U_4V
C62
10U_4V
C247
10U_4V
+VCC_CORE
C229
10U_4V
22uF 0805 X6S->105 degree C
8 inside ca vity north s i de secondary layer, 8 inside cavity
south side secondary layer, 6 inside cavity north side
primary lay er, 6 inside cavity south side primary layer.
C248
10U_4V
C63
10U_4V
C59
10U_4V
C271
10U_4V
C252
10U_4V
C246
10U_4V
C215
10U_4V
C67
10U_4V
+VCC_CORE
C61
10U_4V
+VCC_CORE
C58
10U_4V
+VCC_CORE
C270
10U_4V
+VCC_CORE
C251
10U_4V
+VCC_CORE
C245
10U_4V
C66
10U_4V
C269
10U_4V
C57
10U_4V
C268
10U_4V
C250
10U_4V
C281
10U_4V
C65
10U_4V
C267
10U_4V
C273
10U_4V
C283
10U_4V
C249
10U_4V
C282
10U_4V
+VCC_CORE
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
U6C
A7
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Yonah
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
A9
B7
B9
C9
D9
E7
E9
F7
F9
+VCC_CORE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AF7
AE7
Route VCCSENSE and VSSSENSE
traces at 27.4ohms with 50mil
spacing. Place PU and PD
within 0.5 inch of CPU.
+1.05V_VCCP
+
C261
*330U_2.5V_NC
CT_0530: Modify
netname.
CPU_VID0 45
CPU_VID1 45
CPU_VID2 45
CPU_VID3 45
CPU_VID4 45
CPU_VID5 45
CPU_VID6 45
VCCSENSE
VSSSENSE
12
C68
0.01U_25V
+VCC_CORE
R138
100/F
R139
100/F
+1.5V_RUN
12
C69
10U_4V
Place C28
near PIN B26
VCCSENSE 45
VSSSENSE 45
Place PU & PD within
1 inch of CPU
M22
M25
N23
N26
A11
A14
A16
A19
A23
A26
B11
B13
B16
B19
B21
B24
C11
C14
C16
C19
C22
C25
D11
D13
D16
D19
D23
D26
E11
E14
E16
E19
E21
E24
F11
F13
F16
F19
F22
F25
G23
G26
H21
H24
K23
K26
L21
L24
U6D
A4
VSS[001]
A8
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
B6
VSS[009]
B8
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
C5
VSS[017]
C8
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
C2
VSS[023]
VSS[024]
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
F5
VSS[044]
F8
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
F2
VSS[050]
VSS[051]
VSS[052]
G4
VSS[053]
G1
VSS[054]
VSS[055]
VSS[056]
H3
VSS[057]
H6
VSS[058]
VSS[059]
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
VSS[067]
VSS[068]
L3
VSS[069]
L6
VSS[070]
VSS[071]
VSS[072]
M2
VSS[073]
M5
VSS[074]
VSS[075]
VSS[076]
N1
VSS[077]
N4
VSS[078]
VSS[079]
VSS[080]
P3
VSS[081]
Yonah
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
D D
+1.05V_VCCP
12
C264
0.1U_10V
1
12
C254
0.1U_10V
12
C255
0.1U_10V
12
C256
0.1U_10V
12
C263
0.1U_10V
2
12
C262
0.1U_10V
QUANTA
Title
Size Document Number Rev
3
4
5
6
Date: Sheet
COMPUTER
Yonah Processor (POWER)
DM5 1A
星期二
27, 2005
十二月
7
of
459,
8
1
Layout note: H_XRCOMP & H_YRCOMP
trace width and spcaing is 10/20 mil
H_XRCOMP
12
R50
24.9/F
A A
Layout note: H_YSCOMP & H_XSCOMP
resistor should be less than 0.5" inch.
+1.05V_VCCP
12
R48
54.9/F
H_XSCOMP
B B
C C
H_SWING 0 ,H _SWING1 should be 10mil
wide & 20mil spacing.
H_SWING 0, H _ S WING1 Resistors & Caps
should be placed within 0.5"
12
R47
221/F
H_SWNG0 H_SWNG1
12
R46
100/F
C321
0.1U_10V
1 2
+1.05V_VCCP
+1.05V_VCCP+1.05V_VCCP
R55
100/F
12
12
12
12
H_YRCOMP
R57
24.9/F
R52
54.9/F
H_YSCOMP
R54
221/F
1 2
2
C84
0.1U_10V
3
H_D#[0..63]3
CLK_MCH_BCLK17
CLK_MCH_BCLK#17
H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_SWNG0
H_YRCOMP
H_YSCOMP
H_SWNG1
W11
AB7
AA9
AB8
AA4
AA7
AA2
AA6
AA10
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
AG2
AG1
K11
T10
U11
T11
Y10
F1
H1
H3
K2
G1
G2
K9
K1
K7
H4
G4
T3
U7
U9
W9
T1
T8
T4
W7
U5
T9
W6
T5
W4
W3
Y3
Y7
W5
W2
Y8
E1
E2
E4
Y1
U1
W1
J1
J6
J8
J3
4
U7A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_CLKIN
H_CLKIN#
Calistoga
H_ADSTB#_0
H_ADSTB#_1
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
5
H_A#3
H9
H_A#4
C9
H_A#5
E11
H_A#6
G11
H_A#7
F11
H_A#8
G12
H_A#9
F9
H_A#10
H11
H_A#11
J12
H_A#12
G14
H_A#13
D9
H_A#14
J14
H_A#15
H13
H_A#16
J15
H_A#17
F14
H_A#18
D12
H_A#19
A11
H_A#20
C11
H_A#21
A12
H_A#22
A13
H_A#23
E13
H_A#24
G13
H_A#25
F12
H_A#26
B12
H_A#27
B14
H_A#28
C12
H_A#29
A14
H_A#30
C14
H_A#31
D14
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
6
H_A#[3..31]
H_A#[3..31] 3
H_VREF decoupling cap should be
placed within 100mils
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_RESET# 3
H_DBSY# 3
H_DEFER# 3
H_DPWR# 3
H_DRDY# 3
H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3
H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3
H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3
H_RS#0 3
H_RS#1 3
H_RS#2 3
H_CPUSLP# 3,11
H_TRDY# 3
12
C336
0.1U_10V
H_VREF
7
+1.05V_VCCP
R212
100/F
1 2
12
R213
200/F
8
D D
QUANTA
Title
Size Document Number Rev
Custom
1
2
3
4
5
6
Date: Sheet
COMPUTER
Calistoga (Host)
DM5 1A
星期二
27, 2005
十二月
7
of
559,
8
1
2
3
4
5
6
7
8
U7B
T32
RSVD_1
R32
RSVD_2
F3
RSVD_3
F7
RSVD_4
AG11
RSVD_5
AF11
RSVD_6
H7
RSVD_7
J19
RSVD_8
A41
AH33
AH34
BA41
BA40
BA39
AY41
AW41
AW1
CFG7
CFG9
A35
A34
D28
D27
K16
K18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
K27
G28
F25
H26
H28
H27
K28
H32
C41
BA3
BA2
BA1
B41
AY1
A40
A39
J18
J25
J26
G6
D1
C1
B2
A4
A3
12
R223
*2.2K_NC
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
CLK_REQ#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
12
R205
*2.2K_NC
12
R195
*2.2K_NC
12
R207
*2.2K_NC
2
SM_OCDCOMP_0
SM_OCDCOMP_1
CFGRSVD
DDR MUXINGCLKDMI
D_REFSSCLKIN#
PM
D_REFSSCLKIN
MISC
NC
Calistoga
CFG10
Host PLL VCC Select
Low=Reserved
High=Mobility
CFG11
PSB 4X CLK Enable
Low=Calistoga
High=Reserved
CFG16
FSB Dynamic ODT
Low=Dynamic ODT Disable
High=Dynamic ODT Enable
SM_RCOMP#
SM_RCOMP
SM_VREF_0
SM_VREF_1
D_REFCLKIN#
D_REFCLKIN
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
CFG[2:0]
A A
001=FSB533
011=FSB667
Others = Reserved
CPU_MCH_BSEL03,17
CPU_MCH_BSEL13,17
CPU_MCH_BSEL23,17
R200
*2.2K_NC
Low=DMIx2
High=DMIx4
B B
THERMTRIP_MCH#32
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
C C
PAD
PAD
Note: CFG3:17 has internal pullup
CFG18:19 has internal pulldown
D D
T62
PAD
T5
PAD
12
PAD
PAD
PAD
PAD
PM_BMBUSY#13
PM_EXTTS#015
ICH_PWRGD13,40
SDVO_CTRLCLK18
SDVO_CTRLDATA18
MCH_ICH_SYNC#12
CLK_3GPLLREQ#17
T12
T60
T11
T33
T24
T32
T27
T35
T28
T8
T10
T25
T34
T22
T26
T4
T9
T7
T3
CFG[13:12]
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation(Default)
CFG6
Low= Moby
High=Calistoga
1
T61
T6
T59
T63
PM_EXTTS#0
PM_EXTTS#1
TP_NC0
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16
TP_NC17
TP_NC18
12
R184
*2.2K_NC
PCIE Graphics Lane
Low= Reverse Lane
High=Normal operation
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PLTRST#_R
CFG13 CFG12
CPU_Strap
Low=RSVD
High=Mobile CPU
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
G_CLKIN#
G_CLKIN
12
R196
*2.2K_NC
12
R192
*2.2K_NC
12
R204
*2.2K_NC
AY35
AR1
AW7
AW40
AW35
AT1
AY7
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
M_OCDOCMP0
AL20
M_OCDOCMP1
AF10
BA13
BA12
AY20
AU21
SMRCOMPN
AV9
SMRCOMPP
AT9
AK1
AK41
AF33
AG33
A27
A26
C40
D41
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
PLTRST#12,13,18,23,27,28
DMI Lane Reversal
Low=Normal
High=Lane Reversed
PCIe Backward
Interpoerability mode
Low=Only SDVO or PCIEx1
is operational
(defaults)
High=SDVO and PCIEx1 are
operating simultaneously
via PEG port
3
VCC Select
Low=1.05V
High=1.5V
CFG18
CFG19
CFG20
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 15
M_CLK_DDR3 15
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 15
M_CLK_DDR#3 15
DDR_CKE0_DIMMA 15,16
DDR_CKE1_DIMMA 15,16
DDR_CKE2_DIMMB 15,16
DDR_CKE3_DIMMB 15,16
DDR_CS0_DIMMA# 15,16
DDR_CS1_DIMMA# 15,16
DDR_CS2_DIMMB# 15,16
DDR_CS3_DIMMB# 15,16
R255 *40.2/F_NC
R247 *40.2/F_NC
M_ODT0 15,16
M_ODT1 15,16
M_ODT2 15,16
M_ODT3 15,16
V_DDR_MCH_REF
CLK_MCH_3GPLL# 17
CLK_MCH_3GPLL 17
MCH_DREFCLK# 17
MCH_DREFCLK 17
DREF_SSCLK# 17
DREF_SSCLK 17
DMI_MRX_ITX_N0 12
DMI_MRX_ITX_N1 12
DMI_MRX_ITX_N2 12
DMI_MRX_ITX_N3 12
DMI_MRX_ITX_P0 12
DMI_MRX_ITX_P1 12
DMI_MRX_ITX_P2 12
DMI_MRX_ITX_P3 12
DMI_MTX_IRX_N0 12
DMI_MTX_IRX_N1 12
DMI_MTX_IRX_N2 12
DMI_MTX_IRX_N3 12
DMI_MTX_IRX_P0 12
DMI_MTX_IRX_P1 12
DMI_MTX_IRX_P2 12
DMI_MTX_IRX_P3 12
PLTRST#_R
12
R62100
+3.3V_RUN
R225
*1K_NC
1 2
+3.3V_RUN
R232
*1K_NC
1 2
+3.3V_RUN
R224
*1K_NC
1 2
+3.3V_RUN
Stuff R255,R247
for A1 Calistoga
V_DDR_MCH_REF
12
4
R202 10K
1 2
1 2
R203 10K
Place R255,R247
close to MCH.
12
C93
.1U_10V
VGA_HSYNC20
VGA_VSYNC20
+1.8V_SUS
LCTLA_CLK
LCTLB_DAT
C559
.1U_10V
TV_CVBS20,39
TV_Y20,39
TV_C20,39
R190 150/F
1 2
R185 150/F
1 2
R187 150/F
1 2
R194 *150/F_NC
1 2
R193 *150/F_NC
1 2
R186 *150/F_NC
1 2
1 2
R35 39
1 2
R36 39
+3.3V_RUN
DPRSLPVR13,45
12
R263
80.6/F
SMRCOMPN
SMRCOMPP
12
R261
80.6/F
5
PANEL_BKEN19
LCD_ACLK-19
LCD_ACLK+19
LCD_BCLK-19
LCD_BCLK+19
LCD_A0-19
LCD_A1-19
LCD_A2-19
LCD_A0+19
LCD_A1+19
LCD_A2+19
LCD_B0-19
LCD_B1-19
LCD_B2-19
LCD_B0+19
LCD_B1+19
LCD_B2+19
+1.05V_VCCP
BIA_PWM19,27
LCD_DDCCLK19
LCD_DDCDAT19
1 2
R183 1.5K/F
ENVDD19
1 2
R208
4.99K/F
VGA_BLU20,39
VGA_GRN20,39
VGA_RED20,39
CLK_DDC220
DAT_DDC220
1 2
R214 255/F
R206 10K
1 2
R201 *10K_NC
1 2
R227 0
1 2
R226 75
1 2
THERMTRIP_MCH#
U7C
D32
L_BKLTCTL
J30
L_BKLTEN
H30
L_CLKCTLA
H29
L_CLKCTLB
G26
L_DDC_CLK
G25
L_DDC_DATA
B38
L_IBG
C35
L_VBG
F32
L_VDDEN
C33
L_VREFH
C32
L_VREFL
A33
LA_CLK#
A32
LA_CLK
E27
LB_CLK#
E26
LB_CLK
C37
LA_DATA#_0
B35
LA_DATA#_1
A37
LA_DATA#_2
B37
LA_DATA_0
B34
LA_DATA_1
A36
LA_DATA_2
G30
LB_DATA#_0
D30
LB_DATA#_1
F29
LB_DATA#_2
F30
LB_DATA_0
D29
LB_DATA_1
F28
LB_DATA_2
A16
TV_DACA_OUT
C18
TV_DACB_OUT
A19
TV_DACC_OUT
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
K30
TV_DCONSEL0
J29
TV_DCONSEL1
E23
CRT_BLUE
D23
CRT_BLUE#
C22
CRT_GREEN
B22
CRT_GREEN#
A21
CRT_RED
B21
CRT_RED#
C26
CRT_DDC_CLK
C25
CRT_DDC_DATA
G23
CRT_HSYNC
J22
CRT_IREF
H23
CRT_VSYNC
Calistoga
PM_EXTTS#0
PM_EXTTS#1 DVO_GREEN#_C
6
LVDS
TV
VGA
DVO_RED#_C
DVO_BLUE#_C
DVO_CLK#_C
DVO_RED_C
DVO_GREEN_C
DVO_BLUE_C
DVO_CLK_C
Title
Size Document Number Rev
Date: Sheet
VCC3G_PCIE_R
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
DVO_RED#_C
DVO_GREEN#_C
DVO_BLUE#_C
DVO_CLK#_C
DVO_RED_C
DVO_GREEN_C
DVO_BLUE_C
DVO_CLK_C
SDVOB_RED- 18
SDVOB_GREEN- 18
SDVOB_BLUE- 18
SDVOB_CLK- 18
SDVOB_RED+ 18
SDVOB_GREEN+ 18
SDVOB_BLUE+ 18
SDVOB_CLK+ 18
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
PCI-EXPRESS GRAPHICS
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
C326 .1U_10V
C325 .1U_10V
C335 .1U_10V
C339 .1U_10V
C323 .1U_10V
C322 .1U_10V
C330 .1U_10V
C334 .1U_10V
QUANTA
COMPUTER
Calistoga (VGA,DMI)
DM5 1A
星期二
27, 2005
十二月
7
VCC3G_PCIE
R188 24.9/F
1 2
SDVOB_INT- 18
SDVOB_INT+ 18
of
659,
8
1
A A
2
3
4
5
6
7
8
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AW2
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U7D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
Calistoga
DDR_A_BS0
AU12
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR SYSTEM MEMORY A
SA_WE#
AV14
BA20
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
AW14
AK23
AK24
AY14
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_RAS#
DDR_A_WE#
DDR_A_BS0 15,16
DDR_A_BS1 15,16
DDR_A_BS2 15,16
DDR_A_CAS# 15,16
DDR_A_DM[0..7] 15
DDR_A_DQS[0..7] 15
DDR_A_DQS#[0..7] 15
DDR_A_MA[0..13] 15,16
DDR_A_RAS# 15,16
T70 PAD
T69 PAD
DDR_A_WE# 15,16
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
B B
C C
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D[0..63]15DDR_A_D[0..63]15
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AN10
AK13
AH11
AK10
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ9
AJ8
AJ5
AJ3
U7E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
Calistoga
DDR_B_BS0
AT24
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
DDR SYSTEM MEMORY B
SB_WE#
AV23
AY28
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
AU23
AK16
AK18
AR27
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_RAS#
DDR_B_WE#
DDR_B_BS0 15,16
DDR_B_BS1 15,16
DDR_B_BS2 15,16
DDR_B_CAS# 15,16
DDR_B_DM[0..7] 15
DDR_B_DQS[0..7] 15
DDR_B_DQS#[0..7] 15
DDR_B_MA[0..13] 15,16
DDR_B_RAS# 15,16
T71 PAD
T68 PAD
DDR_B_WE# 15,16
D D
QUANTA
Title
Size Document Number Rev
Custom
1
2
3
4
5
6
Date: Sheet
COMPUTER
Calistoga (DDR2)
DM5 1A
星期二
27, 2005
十二月
7
of
759,
8
5
U7G
+1.05V_VCCP
D D
C C
B B
A A
5
AA33
W33
P33
N33
AA32
Y32
W32
V32
P32
N32
M32
AA31
W31
V31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
R30
P30
N30
M30
AA29
Y29
W29
V29
U29
R29
P29
M29
AB28
AA28
Y28
V28
U28
R28
P28
N28
M28
P27
N27
M27
P26
N26
N25
M25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
AC22
AB22
Y22
W22
P22
N22
M22
AC21
AA21
W21
N21
M21
AC20
AB20
Y20
W20
P20
N20
M20
AB19
AA19
Y19
N19
M19
N18
M18
P17
N17
M17
N16
M16
VCC_0
VCC_1
VCC_2
VCC_3
L33
VCC_4
J33
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
L32
VCC_13
J32
VCC_14
VCC_15
VCC_16
VCC_17
T31
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
T30
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
L30
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
L29
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
T28
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
L28
VCC_53
VCC_54
VCC_55
VCC_56
L27
VCC_57
VCC_58
VCC_59
L26
VCC_60
VCC_61
VCC_62
L25
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
L23
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
L22
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
L21
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
L20
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
L19
VCC_101
VCC_102
VCC_103
L18
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
L16
VCC_110
VCC
Calistoga
4
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
4
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
Place near C94 close to U2.AT41
Place near C92 close to U2.AM41
VCCSM_LF4
VCCSM_LF5
12
.1U_10V
C107
12
C92
0.47U_10V
12
.1U_10V
C106
12
C94
0.47U_10V
Place C104 close to U3.BA23
12
C104
0.47U_10V
+1.8V_SUS
+
C88
*330U_2.5V_NC
+1.8V_SUS
12
12
C373
C374
10U_4V
10U_4V
Place In Cavity
Place near U2.AV1 & AJ1
C97 0.47U_10V
VCCSM_LF2
VCCSM_LF1
1 2
C91 0.47U_10V
1 2
3
+1.05V_VCCP
C344
C345
C108
C103
0.47U_10V
+
+1.05V_VCCP
+
12
C105
.1U_10V
330U_2.5V
330U_2.5V
12
.1U_10V
12
Place C103 near pin U2.BA15
3
12
12
C342
10U_4V
C364
10U_4V
12
C360
1U_10V
12
C355
0.22U_10V
12
C350
0.22U_10V
12
C343
0.22U_10V
2
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
2
U7F
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
1
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
+1.5V_RUN
NCTF
Calistoga
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
QUANTA
Title
Size Document Number Rev
Custom
Date: Sheet
COMPUTER
Calistoga (VCC, NCTF)
DM5 1A
星期二
27, 2005
十二月
1
of
859,
5
L17
1 2
1 2
BLM18PG330SN1
L46
1 2
BLM18PG181SN1
+2.5V_RUN
VCCA_3GPLL_R
L41
1 2
BLM18PG181SN1
+1.5V_RUN
CT_1214: Removed
R49 0_0805 ohm.
+1.5V_RUN
D D
D18
R171 10
2 1
+1.05V_VCCP
RB751V
Route Caps within 250mil or
VCC3G_PCIE
C79
150U_2V_L
R249
0.5/F
VCCA_CRTDAC
12
C293
.1U_10V
12
+
C87
10U_4V
12
C354
10U_4V
R178 0
1 2
Calistoga. Route FB within
3" of Calistoga.
Route VSSACRTDAC gnd from GMCH to decoupling cap
ground lead and then connect to gnd plane.
+1.5V_RUN
C C
B B
A A
+3.3V_RUN
+1.5V_RUN
L42
10uH
L16
10uH
D17
2 1
RB751V
12
12
12
12
R163
10
1 2
+1.5V_RUN
12
C319
+
.1U_10V
12
C316
+
.1U_10V
L40
1 2
BLM18PG181SN1
5
VCCA_DPLLA
C71
470U_4V
C76
470U_4V
C278
10U_4V
2.2U_6.3V
L15
1 2
BLM18PG181SN1
C296
+1.5V_RUN
12
.1U_10V
.1U_10V
.1U_10V
12
.1U_10V
.1U_10V
.1U_10V
C284
C313
C279
C294
C280
C70
L45
BLM11A121S
L47
BLM11A121S
VCC_TVDACA
12
VCC_TVDACB
12
VCC_TVDACC
12
VCC_TVBG
12
VCCD_TVDAC
12
VCCQ_TVDAC
12
C306 *22NF_3P_NC
C285 *22NF_3P_NC
C295 *22NF_3P_NC
C307 *22NF_3P_NC
C286 *22NF_3P_NC
C72 *22NF_3P_NC
12
C90
10U_4V
12
C365
.1U_10V
1
3
C298
2
*22NF_3P_NC
12
12
C367
.1U_10V
12
12
C375
.1U_10V
R180 0
1 2
123
R172 0
1 2
123
R177 0
1 2
123
R181 0
1 2
123
R170 0
1 2
123
R33 0
1 2
123
4
VCC3G_PCIE
12
Place C79 and C87 on
same side as
Calostoga. No Vias.
VCCA_3GPLL
12
12
C324
.022U
VCCA_HPLL
12
C362
22U
VCCA_MPLLVCCA_DPLLB
12
C378
22U
VCC_TVDACA_R
12
C314
.022U
VCC_TVDACB_R
12
C320
.022U
VCC_TVDACC_R
12
C297
.022U
VCC_TVBG_R
12
C327
.022U
VSS_TVBG
VCCD_TVDAC_R
12
C289
.022U
VCCQ_TVDAC_R
12
C74
.022U
4
+2.5V_RUN
C328
.01U
12
+2.5V_RUN
3
12
C305
.1U_10V
4.7U
C329 .1U_10V
12
C312
+2.5V_RUN
12
VCC3G_PCIE
VCCA_3GPLL
C329 should be place within 200mils
+2.5V_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
+1.5V_RUN
10U_4V
+2.5V_RUN
C304
.1U_10V
12
.1U_10V
C310
C311
+3.3V_RUN
12
12
C308
10U_4V
C301
.01U
12
12
.1U_10V
C303
+1.5V_RUN
12
+1.5V_RUN
VCCA_MPLL
VCC_TVBG_R
VSS_TVBG
VCC_TVDACA_R
VCC_TVDACB_R
VCC_TVDACC_R
VCCD_TVDAC_R
VCCQ_TVDAC_R
12
C369
.1U_10V
Route VSSA_TVBG_GND from GMCH to
decoupling cap ground lead and then connect
to the GND plane.
4.7U, 10U and 22U should be placed <500mils with
in its pins.
0.1U should be placed <200mils with in its pins.
22n should be placed with in its pins.
3
H22
C30
AJ41
AB41
R41
N41
AC33
G41
H41
G21
C39
AF1
AF2
H20
G20
C20
D20
AH1
AH2
C28
D21
H19
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
AH15
AH14
AG14
AF14
AE14
AF13
AE13
AF12
AE12
AD12
B30
A30
Y41
V41
L41
F21
E21
B26
A38
B39
E19
F19
E20
F20
A28
B28
A23
B23
B25
P19
P16
P15
Y14
U7H
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCC_HV0
VCC_HV1
VCC_HV2
VCCD_QTVDAC
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
2
POWER
Calistoga
2
1
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
+1.05V_VCCP
+1.05V_VCCP
12
C346
2.2U_6.3V
Place in Cavity.
+1.05V_VCCP
C78
330U_2.5V
+
Place on the edge.
Place close to pin A6
VTTLF_CAP3
VTTLF_CAP2
VTTLF_CAP1
C73 .47U_10V
Place close to pin D2
1 2
12
C86
.47U_10V
12
C358
4.7U
12
C82
.22U
12
C75
.22U
Place close to pin AB1
QUANTA
Title
Size Document Number Rev
Custom
Date: Sheet
COMPUTER
Calistoga (Power)
DM5 1A
星期二
27, 2005
十二月
1
of
959,
5
U7I
AC41
VSS_0
AA41
VSS_1
W41
VSS_2
T41
VSS_3
P41
VSS_4
M41
VSS_5
J41
VSS_6
F41
VSS_7
AV40
VSS_8
AP40
VSS_9
AN40
VSS_10
D D
C C
B B
A A
AK40
AJ40
AH40
AG40
AF40
AE40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
W39
M39
G39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
R37
P37
N37
M37
H37
G37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
R35
P35
N35
M35
H35
G35
D35
AN34
B40
Y39
V39
T39
R39
P39
N39
L39
J39
H39
F39
T37
L37
J37
F37
T35
L35
J35
F35
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
Calistoga
VSS
4
AK34
VSS_97
AG34
VSS_98
AF34
VSS_99
AE34
VSS_100
AC34
VSS_101
C34
VSS_102
AW33
VSS_103
AV33
VSS_104
AR33
VSS_105
AE33
VSS_106
AB33
VSS_107
Y33
VSS_108
V33
VSS_109
T33
VSS_110
R33
VSS_111
M33
VSS_112
H33
VSS_113
G33
VSS_114
F33
VSS_115
D33
VSS_116
B33
VSS_117
AH32
VSS_118
AG32
VSS_119
AF32
VSS_120
AE32
VSS_121
AC32
VSS_122
AB32
VSS_123
G32
VSS_124
B32
VSS_125
AY31
VSS_126
AV31
VSS_127
AN31
VSS_128
AJ31
VSS_129
AG31
VSS_130
AB31
VSS_131
Y31
VSS_132
AB30
VSS_133
E30
VSS_134
AT29
VSS_135
AN29
VSS_136
AB29
VSS_137
T29
VSS_138
N29
VSS_139
K29
VSS_140
G29
VSS_141
E29
VSS_142
C29
VSS_143
B29
VSS_144
A29
VSS_145
BA28
VSS_146
AW28
VSS_147
AU28
VSS_148
AP28
VSS_149
AM28
VSS_150
AD28
VSS_151
AC28
VSS_152
W28
VSS_153
J28
VSS_154
E28
VSS_155
AP27
VSS_156
AM27
VSS_157
AK27
VSS_158
J27
VSS_159
G27
VSS_160
F27
VSS_161
C27
VSS_162
B27
VSS_163
AN26
VSS_164
M26
VSS_165
K26
VSS_166
F26
VSS_167
D26
VSS_168
AK25
VSS_169
P25
VSS_170
K25
VSS_171
H25
VSS_172
E25
VSS_173
D25
VSS_174
A25
VSS_175
BA24
VSS_176
AU24
VSS_177
AL24
VSS_178
AW23
VSS_179
3
U7J
AT23
VSS_180
AN23
VSS_181
AM23
VSS_182
AH23
VSS_183
AC23
VSS_184
W23
VSS_185
K23
VSS_186
J23
VSS_187
F23
VSS_188
C23
VSS_189
AA22
VSS_190
K22
VSS_191
G22
VSS_192
F22
VSS_193
E22
VSS_194
D22
VSS_195
A22
VSS_196
BA21
VSS_197
AV21
VSS_198
AR21
VSS_199
AN21
VSS_200
AL21
VSS_201
AB21
VSS_202
Y21
VSS_203
P21
VSS_204
K21
VSS_205
J21
VSS_206
H21
VSS_207
C21
VSS_208
AW20
VSS_209
AR20
VSS_210
AM20
VSS_211
AA20
VSS_212
K20
VSS_213
B20
VSS_214
A20
VSS_215
AN19
VSS_216
AC19
VSS_217
W19
VSS_218
K19
VSS_219
G19
VSS_220
C19
VSS_221
AH18
VSS_222
P18
VSS_223
H18
VSS_224
D18
VSS_225
A18
VSS_226
AY17
VSS_227
AR17
VSS_228
AP17
VSS_229
AM17
VSS_230
AK17
VSS_231
AV16
VSS_232
AN16
VSS_233
AL16
VSS_234
J16
VSS_235
F16
VSS_236
C16
VSS_237
AN15
VSS_238
AM15
VSS_239
AK15
VSS_240
N15
VSS_241
M15
VSS_242
L15
VSS_243
B15
VSS_244
A15
VSS_245
BA14
VSS_246
AT14
VSS_247
AK14
VSS_248
AD14
VSS_249
AA14
VSS_250
U14
VSS_251
K14
VSS_252
H14
VSS_253
E14
VSS_254
AV13
VSS_255
AR13
VSS_256
AN13
VSS_257
AM13
VSS_258
AL13
VSS_259
AG13
VSS_260
P13
VSS_261
F13
VSS_262
D13
VSS_263
B13
VSS_264
AY12
VSS_265
AC12
VSS_266
K12
VSS_267
H12
VSS_268
E12
VSS_269
AD11
VSS_270
AA11
VSS_271
Y11
VSS_272
VSS
Calistoga
2
J11
VSS_273
D11
VSS_274
B11
VSS_275
AV10
VSS_276
AP10
VSS_277
AL10
VSS_278
AJ10
VSS_279
AG10
VSS_280
AC10
VSS_281
W10
VSS_282
U10
VSS_283
BA9
VSS_284
AW9
VSS_285
AR9
VSS_286
AH9
VSS_287
AB9
VSS_288
Y9
VSS_289
R9
VSS_290
G9
VSS_291
E9
VSS_292
A9
VSS_293
AG8
VSS_294
AD8
VSS_295
AA8
VSS_296
U8
VSS_297
K8
VSS_298
C8
VSS_299
BA7
VSS_300
AV7
VSS_301
AP7
VSS_302
AL7
VSS_303
AJ7
VSS_304
AH7
VSS_305
AF7
VSS_306
AC7
VSS_307
R7
VSS_308
G7
VSS_309
D7
VSS_310
AG6
VSS_311
AD6
VSS_312
AB6
VSS_313
Y6
VSS_314
U6
VSS_315
N6
VSS_316
K6
VSS_317
H6
VSS_318
B6
VSS_319
AV5
VSS_320
AF5
VSS_321
AD5
VSS_322
AY4
VSS_323
AR4
VSS_324
AP4
VSS_325
AL4
VSS_326
AJ4
VSS_327
Y4
VSS_328
U4
VSS_329
R4
VSS_330
J4
VSS_331
F4
VSS_332
C4
VSS_333
AY3
VSS_334
AW3
VSS_335
AV3
VSS_336
AL3
VSS_337
AH3
VSS_338
AG3
VSS_339
AF3
VSS_340
AD3
VSS_341
AC3
VSS_342
AA3
VSS_343
G3
VSS_344
AT2
VSS_345
AR2
VSS_346
AP2
VSS_347
AK2
VSS_348
AJ2
VSS_349
AD2
VSS_350
AB2
VSS_351
Y2
VSS_352
U2
VSS_353
T2
VSS_354
N2
VSS_355
J2
VSS_356
H2
VSS_357
F2
VSS_358
C2
VSS_359
AL1
VSS_360
1
QUANTA
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
COMPUTER
Calistoga (VSS,NCTF)
DM5 1A
星期二
27, 2005
十二月
1
of
10 59,
1
32.768KHZ
12
C177
A A
Pop R1580 & no pop R1581
to disable internal VR.
B B
C C
R110 10M
12
W1
1 4
2 3
32.768KHZ
15P_50V
+RTC_CELL
SATA_TX0-21
SATA_TX0+21
Distance between the ICH-7 M and cap on the "P"
signal should be identical distance between the
ICH-6 M and cap on the "N" signal for same
pair.
+3.3V_RUN
R439
1 2
0_0402
R416
1M
12
R415
332K/F
12
R403
*0_NC
C472 3900P_25V
C469 3900P_25V
IDE_IRQ
SATA_ACT#
12
12
R381 8.2K
R8 *10K_NC
X1,X2 Docking
IAC_SYNC Port X Line
101X2,2X1
4X1
12
12
2
1 2
12
C532
1U_10V
SATA_C_TX0-
SATA_C_TX0+
R126
STUFF
UNSTUFF
ICH_RTCX2ICH_RTCX1
12
R417
20K
ICH_RTCRST#
SM_INTRUDER#
SM_INTVRMEN
R8 can be
removed on RTS
C178
15P_50V
ICH_AZ_CODEC_SDIN034
ICH_AZ_MDC_SDIN126
SATA_ACT#33
SATA_RX0-21
SATA_RX0+21
CLK_PCIE_SATA#17
CLK_PCIE_SATA17
Place within 500mils
of ICH6 ball
IDE_DIOR#21
IDE_DIOW#21
IDE_DDACK#21
IDE_IRQ21
IDE_DIORDY21
3
T54 PAD
T55 PAD
T49 PAD
T50 PAD
T94 PAD
T96 PAD
T88 PAD
T89 PAD
T95 PAD
T83 PAD
T84 PAD
T85 PAD
T52 PAD
R393 24.9/F
ICH_RTCX1
ICH_RTCX2
ICH_RTCRST#
SM_INTRUDER#
SM_INTVRMEN
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
SATA_ACT#
SATA_RX0-
SATA_RX0+
SATA_C_TX0SATA_C_TX0+
SATABIAS
12
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ
AB1
AB2
AA3
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AF15
AH15
AF16
AH16
AG16
AE15
W4
W1
W3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
U9A
RTXC1
RTCX2
RTCRST#
Y5
INTRUDER#
INTVRMEN
EE_CS
Y1
EE_SHCLK
Y2
EE_DOUT
EE_DIN
V3
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
ICH7-M
4
LPCCPU
RTCLAN
AC-97/AZALIA
SATA
IDE
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#/GPIO23
LFRAME#
A20GATE
A20M#
CPUSLP#
TP1/DPRSTP#
TP2/DPSLP#
FERR#
GPIO49/CPUPWRGD
IGNNE#
INIT3_3V#
INIT#
INTR
RCIN#
SMI#
STPCLK#
THERMTRIP#
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DA0
DA1
DA2
NMI
5
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AH24
AF23
AH22
AF26
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
LPC_LDRQ0#
LPC_LDRQ1#
SIO_A20GATE
R_CPUSLP#
THERMTRIP#_ICH
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
LPC_LAD0 27,28
LPC_LAD1 27,28
LPC_LAD2 27,28
LPC_LAD3 27,28
LPC_LDRQ0# 28
LPC_LDRQ1# 28
LPC_LFRAME# 27,28
SIO_A20GATE 27
H_A20M# 3
R364 0
1 2
H_FERR# 3
H_PWRGOOD 3
H_IGNNE# 3
H_INIT# 3
H_INTR 3
SIO_RCIN# 27
H_NMI 3
H_STPCLK# 3
IDE_DD[0..15]
IDE_DA0 21
IDE_DA1 21
IDE_DA2 21
IDE_DCS1# 21
IDE_DCS3# 21IDE_DDREQ21
6
R97 *0_NC
1 2
1 2
R99 0
R99 & R366 can be
removed on RTS
1 2
R366 0
IDE_DD[0..15] 21
7
H_CPUSLP# 3,5
H_DPRSTP# 3,45
H_DPSLP# 3
H_SMI# 3
H_FERR#
H_DPRSTP#
H_DPSLP#
SIO_A20GATE
SIO_RCIN#
THERMTRIP#_ICH
R361 56
1 2
R365 *56_NC
1 2
R363 *56_NC
1 2
1 2
+1.05V_VCCP
8
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+3.3V_RUN
R372
10K
R96
56
1 2
C167
*0.1U_10V_NC
1 2
R369
10K
1 2
R411 33
ACZ_SYNC
D D
1
1 2
R412 33
1 2
R108 33
1 2
R109 33
1 2
*27P_50V_NC
12
12
C180
Place All Series Term close to ICH except for the SDIN input lines, which should be close to
the source. All resister value should tuned during EA. Placement of R87,R88,R91,R92 should be
Equal distance to the "T" split trace point as R89,R90,R93,R94. resp. Basically, keep the same
distance from "T" for all seriess termination resistor.
2
ICH_AZ_MDC_SYNC 26
ICH_AZ_CODEC_SYNC 34
C179
*27P_50V_NC
ICH_AZ_MDC_BITCLK 26
ACZ_SDOUT
ACZ_RST#ACZ_BIT_CLK
3
R106 33
1 2
R111 33
1 2
R107 33
1 2
R112 33
1 2
ICH_AZ_MDC_SDOUT 26
ICH_AZ_CODEC_SDOUT 34
ICH_AZ_MDC_RST# 26
ICH_AZ_CODEC_RST# 34ICH_AZ_CODEC_BITCLK 34
Title
Size Document Number Rev
4
5
6
Date: Sheet
QUANTA
COMPUTER
ICH7-M (CPU,IDE,SATA,LPC,AC97)
DM5 1A
星期二
27, 2005
十二月
7
of
11 59,
8
1
A A
B B
OC2#
+3.3V_SUS
C C
PCI_AD[0..31]24,36
D D
PCI_PIRQB: for LOM
PCI_PIRQD: for CardBus
1
RP20
6
7
8
9
10
10P8R-10K
PCI_PIRQB#36
PCI_PIRQD#24
T91 PAD
T92 PAD
T48 PAD
T47 PAD
T87 PAD
5
4
3
2
1
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
MiniWLAN
ICH_EC_SPI_CLK27
ICH_EC_SPI_DO27
ICH_EC_SPI_DIN27
USB_OC5_6#
USB_OC3_4#OC7#
OC1#
OC0#
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9
2
U9B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PIRQA#
PIRQB#
PIRQC#
PIRQD#
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
ICH7-M
2
PCIE_RX2-23
PCIE_RX2+23
PCIE_TX2-23
PCIE_TX2+23
CT_1226: Change
to Circle pad.
ICH_EC_SPI_CLK
SPI_CS#27,30
+3.3V_SUS
PCI
Interrupt I/F
MISC
SPI_CS#
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
GPIO1/REQ5#
GPIO17/GNT5#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
PAR
3
1 2
C169 0.1U_10V
+3.3V_SUS
12
R394
10K
USB_OC3_4#33
USB_OC5_6#33
PCI_REQ0#
D7
PCI_GNT0#
E7
PCI_REQ1#PCI_AD2
C16
PCI_GNT1#
D16
PCI_REQ2#
C17
PCI_GNT2#
D17
PCI_REQ3#
E13
PCI_GNT3#
F13
PCI_REQ4#
A13
PCI_GNT4#
A14
PCI_REQ5#
C8
PCI_GNT5#
D8
B15
C12
D12
C15
A7
E10
PCI_RST#_G
B18
A12
C9
E11
B10
F15
F14
F16
C26
CLK_PCI_ICH
A9
B19
ICH_GPIO2_PIRQE#
G8
ICH_GPIO3_PIRQF#
F7
ICH_GPIO4_PIRQG#
F8
ICH_GPIO5_PIRQH#
G7
AE9
AG8
AH8
F21
AH20
3
1 2
C168 0.1U_10V
12
R404
10K
R331 NP boot from FWH,
populate boot from
MiniPCI.
PCI_PLTRST#
PCIE_TXN2_C
PCIE_TXP2_C
CT_1223: added R470
damping r e sistor per CDC.
12
R413
10K
R414 47
1 2
1 2
R470 47
R402
47
1 2
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#
T90PAD
PCI_REQ1# 24
PCI_GNT1# 24
T80PAD
PCI_REQ3# 36
PCI_GNT3# 36
PCI_C_BE0# 24,36
PCI_C_BE1# 24,36
PCI_C_BE2# 24,36
PCI_C_BE3# 24,36
PCI_IRDY# 24,36
PCI_PAR 24,36
PCI_DEVSEL# 24,36
PCI_PERR# 24,36
PCI_PLOCK#
PCI_SERR# 24,36
PCI_STOP# 24,36
PCI_TR D Y# 24,36
PCI_FRAME# 24,36
CLK_PCI_ICH 17
ICH_PME# 28
T86PAD
T46PAD
MCH_ICH_SYNC# 6
4
U9D
F26
PERn1
F25
PERp1
E28
PETn1
E27
PETp1
H26
PERn2
H25
PERp2
G28
PETn2
G27
PETp2
K26
PERn3
K25
PERp3
J28
PETn3
J27
PETp3
M26
PERn4
M25
PERp4
L28
PETn4
L27
PETp4
P26
PERn5
P25
PERp5
N28
PETn5
N27
PETp5
T25
PERn6
T24
PERp6
R28
PETn6
R27
PETp6
R2
SPI_CLK
P6
SPI_CS#
P1
SPI_ARB
P5
SPI_MOSI
P2
SPI_MISO
D3
OC0#
C4
OC1#
D5
OC2#
D4
OC3#
E5
OC4#
C3
OC5#/GPIO29
A2
OC6#/GPIO30
B3
OC7#/GPIO31
ICH7-M
Cardbus/1394
LOM(4401)
4
REQ0 : DOCKING
REQ1 : Card Bus
REQ4 : BroadCOM LAN
LPC 11
PCI
SPI
R391
1K
1 2
DOCK
Cardbus or
Cardbus/1394
1394/MediaCard
LOM(4401)
PCI-Express
SPI
R101
*1K_NC
1 2
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USB
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS
No stuff
No stuff
10
Stuff
01
PCI_GNT4#
PCI_GNT5#
5
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
D1
DMI_COMP
USBRBIAS
Place within 500mils of ICH-7
GNT4#GNT5#
No stuff
Stuff
No stuff
CLK_PCI_ICH
*8.2P_16V_NC
Place AC Term near pin U3.A9.
Final Value needs to be tuned if
required for EMI
REQ0
REQ1
REQ2
REQ3
5
GNT0
GNT1
GNT2
GNT3
PIRQA
PIRQD
PIRQC
PIRQD
PIRQB
CLK_PCIE_ICH# 17
CLK_PCIE_ICH 17
USBP0- 24
USBP0+ 24
USBP1- 28
USBP1+ 28
USBP2- 21
USBP2+ 21
USBP3- 33
USBP3+ 33
USBP4- 33
USBP4+ 33
USBP5- 33
USBP5+ 33
USBP6- 33
USBP6+ 33
USBP7- 39
USBP7+ 39
R410 22.6/F
R398
*10_NC
C515
6
DMI_MTX_IRX_N0 6
DMI_MTX_IRX_P0 6
DMI_MRX_ITX_N0 6
DMI_MRX_ITX_P0 6
DMI_MTX_IRX_N1 6
DMI_MTX_IRX_P1 6
DMI_MRX_ITX_N1 6
DMI_MRX_ITX_P1 6
DMI_MTX_IRX_N2 6
DMI_MTX_IRX_P2 6
DMI_MRX_ITX_N2 6
DMI_MRX_ITX_P2 6
DMI_MTX_IRX_N3 6
DMI_MTX_IRX_P3 6
DMI_MRX_ITX_N3 6
DMI_MRX_ITX_P3 6
R358 24.9/F
12
12
1 2
1 2
6
Place within 500mils of ICH-7
+1.5V_RUN
Cardbus
ECE_USB[0]
FDD
Ext Side Top
Ext Side Bottom
Ext Back Top
Ext Back Bottom
For Dock
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
C475
1 2
0.047U_10V
PCI_RST#_G
C465
1 2
0.047U_10V
PCI_PLTRST#
Title
Size Document Number Rev
Date: Sheet
7
PCI Pullups
RP18
PCI_DEVSEL# ICH_GPIO2_PIRQE#
PCI_SERR#
PCI_REQ4# PCI_REQ5#
PCI_TRDY#
PCI_STOP#
PCI_FRAME#
PCI_REQ1# PCI_REQ2#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
PCI_IRDY# ICH_GP IO5_ PIR Q H#
+3.3V_SUS
5
U26
2
1
7SH32
+3.3V_SUS
5
U24
2
1
7SH32
6
7
8
9
10
10P8R-8.2K
RP17
6
7
8
9
10
10P8R-8.2K
RP19
6
7
8
9
10
10P8R-8.2K
Add Buffers as needed for
Loading and fanout
concerns.
4
4
PCI_RST# 24,36
PLTRST# 6,13,18,23,27,28
+3.3V_RUN
5
4
PCI_PERR#
3
2
ICH_GPIO4_PIRQG#
1
+3.3V_RUN
5
PCI_PLOCK#
4
PCI_REQ3#
3
2
1
+3.3V_RUN
5
PCI_PIRQC#
4
ICH_GPIO3_PIRQF#
3
2
1
8
PCI_REQ0#
QUANTA
COMPUTER
ICH7-M (USB,DMI,PCIE,PCI)
DM5 1A
星期二
27, 2005
十二月
7
of
12 59,
8
1
+3.3V_RUN
A A
B B
R378
8.2K
1 2
CLKRUN#
12
R380
*10_NC
Option to " Disable "
clkrun. Pulling it down
will keep the clks
running.
+3.3V_SUS
R374
680
1 2
ICH_PCIE_WAKE#
2
R360 10K
R357 10K
SPKR34
BT_RADIO_DIS#31
ICH_PCIE_WAKE#28
SIO_EXT_WAKE#27
SIO_EXT_SMI#27
ICH_SMLINK0
ICH_SMLINK1
ICH_SMBCLK17,23
ICH_SMBDATA17,23
ITP_DBRESET#3,27
PM_BMBUSY#6
H_STP_PCI#17
H_STP_CPU#17
LCD_TST19
IDE_RST_MOD21
IRQ_SERIRQ24,27,28
SIO_THRM#27
IMVP_PWRGD40,45
LAMP_STAT#19
T43 PAD
CLKRUN#24,27,28,36
T53 PAD
3
1 2
1 2
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
ICH_RI#
ITP_DBRESET#
SMBALERT#
GL_BL_SUSPEND
SIO_THRM#
IMVP_PWRGD
1 2
LAMP_STAT#
SIO_EXT_SMI#
R452 0
+3.3V_SUS
U9C
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
SMLINK1
A28
RI#
A19
SPKR
A27
SUS_STAT#
A22
SYS_RST#
AB18
GPIO0/BM_BUSY#
B23
GPIO11/SMBALERT#
AC20
GPIO18/STPPCI#
AF21
GPIO20/STPCPU#
A21
GPIO26
B21
GPIO27
E23
GPIO28
AG18
GPIO32/CLKRUN#
AC19
GPIO33/AZ_DOCK_EN#
U2
GPIO34/AZ_DOCK_RST#
F20
WAKE#
AH21
SERIRQ
AF20
THRM#
AD22
VRMPWRGD
AC21
GPIO6
AC18
GPIO7
E21
GPIO8
ICH7-M
4
SMB
SYS
GPIO
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
SATA
GPIO
GPIO37/SATA3GP
Clocks
GPIO16/DPRSLPVR
TP0/BATLOW#
GPIO
Power MGT
R95 *10K_NC
1 2
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
LAN_RST#
RSMRST#
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
SIO_EXT_WAKE#
AF19
AH18
AH19
AE19
AC1
B2
C20
B24
D23
F22
AA4
AC22
C21
C23
C19
Y4
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
5
CLK_ICH_48M
SUS_CLK
ICH_PWRGD
ICH_BATLOW#
SUSPWROK
SIO_EXT_SCI#
PLTRST_DELAY#
+3.3V_RUN
R379
1 2
8.2K
6
CLK_ICH_14M 17
CLK_ICH_48M 17
T44PAD
SIO_SLP_S3# 27
T76PAD
SIO_SLP_S5# 27
ICH_PWRGD 6,40
SIO_PWRBTN# 27
PLTRST# 6,12,18,23,27,28
SUSPWROK 32,40
SIO_EXT_SCI# 27
T45PAD
USB_IDE# 21
RSVD_HDD_DET# 21
T102PAD
T103PAD
T93PAD
T79PAD
SATA_CLKREQ# 17
T78PAD
WWAN_RADIO_DIS#
DPRSLPVR 6,45
12
R371
100K
CT_1212: Removed HDDC_EN# and
MODC_EN# from ICH7 GPIO14 & 15.
Removed R463, R464 100Kohm.
7
Place these close to ICH7.
CLK_ICH_48M
CLK_ICH_14M
12
R105
*10_NC
12
C175
*4.7P_50V_NC
12
R418
*10_NC
12
C543
*4.7P_50V_NC
8
R375 *8.2K_NC
+3.3V_RUN
No Stuff since EC is push-pull.
+3.3V_RUN
RP46
ICH_BATLOW#
ICH_RI#
SIO_EXT_SMI#
SMBALERT#
SIO_EXT_SCI#
12
12
R373
10K
+3.3V_RUN
+3.3V_SUS
+3.3V_SUS
+3.3V_SUS
R370 8.2K
1 2
R352 8.2K
1 2
RP16
7 8
5 6
3 4
1 2
8P4R-10K
R446 2.2K
R447 2.2K
C C
D D
12
ICH_SMBDATA
ICH_SMBCLK
BT_RADIO _ D IS #
RSVD_HDD_DET#
LAMP_STAT#
IRQ_SERIRQ
WWAN_RADIO_DIS#LINKALERT#
R449 *10K_NC
1 2
7 8
5 6
3 4
1 2
8P4R-10K
1 2
SIO_THRM#
R406 10K
1 2
1 2
R405 10K
ICH_PWRGD
SUSPWROK
QUANTA
Title
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
COMPUTER
ICH7-M( PM,GPIO,S M B )
DM5 1A
星期二
27, 2005
十二月
7
of
13 59,
8
1
2
3
4
5
6
7
8
C27
D10
D13
D18
D21
D24
G14
G18
G21
G24
G25
G26
H24
H27
H28
M12
M13
M14
M15
M16
M17
M24
M27
M28
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
U9E
A4
VSS[1]
A23
VSS[2]
B1
VSS[3]
B8
VSS[4]
B11
VSS[5]
B14
VSS[6]
B17
VSS[7]
B20
VSS[8]
B26
VSS[9]
B28
VSS[10]
C2
VSS[11]
C6
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
E1
VSS[19]
E2
VSS[20]
E4
VSS[21]
E8
VSS[22]
E15
VSS[23]
F3
VSS[24]
F4
VSS[25]
F5
VSS[26]
F12
VSS[27]
F27
VSS[28]
F28
VSS[29]
G1
VSS[30]
G2
VSS[31]
G5
VSS[32]
G6
VSS[33]
G9
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
H3
VSS[41]
H4
VSS[42]
H5
VSS[43]
VSS[44]
VSS[45]
VSS[46]
J1
VSS[47]
J2
VSS[48]
J5
VSS[49]
J24
VSS[50]
J25
VSS[51]
J26
VSS[52]
K24
VSS[53]
K27
VSS[54]
K28
VSS[55]
L13
VSS[56]
L15
VSS[57]
L24
VSS[58]
L25
VSS[59]
L26
VSS[60]
M3
VSS[61]
M4
VSS[62]
M5
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
N1
VSS[73]
N2
VSS[74]
N5
VSS[75]
N6
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
P3
VSS[88]
P4
VSS[89]
P12
VSS[90]
P13
VSS[91]
P14
VSS[92]
P15
VSS[93]
P16
VSS[94]
P17
VSS[95]
P24
VSS[96]
P27
VSS[97]
ICH7-M
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
R100 100
+5V_RUN
+3.3V_RUN
A A
+5V_SUS
+3.3V_SUS
+1.5V_RUN
B B
1 2
D8
2 1
RB751V
R102 10
1 2
D9
2 1
RB751V
L22
1 2
BLM21PG600SN1D
ICH_V5REF_RUN
C503
0.1U_10V
1 2
ICH_V5REF_SUS
C518
0.1U_10V
1 2
+1.5VRUN_L
12
+
C164
220U_4V
C170
0.1U_10V
1 2
C163
0.1U_10V
1 2
C166
0.1U_10V
1 2
+3.3V_RUN
C462
0.1U_10V
1 2
+1.5V_RUN
R98
1 2
12
R104
0.5/F
C C
12
L24
10uH_100MA
12
C176
10U_6.3V
0.5/F
L23
BLM11A601S
1 2
+3.3V_RUN
C530
0.1U_10V
1 2
C171
0.01U_25V
1 2
+1.5V_DMIPLL
12
C172
10U_6.3V
C498
0.1U_10V
1 2
+1.5V_RUN
+1.5V_RUN
+1_5V_SATA_RX
C512
0.1U_10V
1 2
VCCSATPLL
+1_5V_SATA_TX
12
C513
1U_10V
+3.3V_SUS
+1.5V_RUN
C508
0.1U_10V
1 2
D D
C542
0.1U_10V
1 2
T51 PAD
T81 PAD
TP_VCCSUSLAN1
TP_VCCSUSLAN2
U9F
G10
V5REF[1]
AD17
V5REF[2]
F6
V5REF_Sus
AA22
Vcc1_5_B[1]
AA23
Vcc1_5_B[2]
AB22
Vcc1_5_B[3]
AB23
Vcc1_5_B[4]
AC23
Vcc1_5_B[5]
AC24
Vcc1_5_B[6]
AC25
Vcc1_5_B[7]
AC26
Vcc1_5_B[8]
AD26
Vcc1_5_B[9]
AD27
Vcc1_5_B[10]
AD28
Vcc1_5_B[11]
D26
Vcc1_5_B[12]
D27
Vcc1_5_B[13]
D28
Vcc1_5_B[14]
E24
Vcc1_5_B[15]
E25
Vcc1_5_B[16]
E26
Vcc1_5_B[17]
F23
Vcc1_5_B[18]
F24
Vcc1_5_B[19]
G22
Vcc1_5_B[20]
G23
Vcc1_5_B[21]
H22
Vcc1_5_B[22]
H23
Vcc1_5_B[23]
J22
Vcc1_5_B[24]
J23
Vcc1_5_B[25]
K22
Vcc1_5_B[26]
K23
Vcc1_5_B[27]
L22
Vcc1_5_B[28]
L23
Vcc1_5_B[29]
M22
Vcc1_5_B[30]
M23
Vcc1_5_B[31]
N22
Vcc1_5_B[32]
N23
Vcc1_5_B[33]
P22
Vcc1_5_B[34]
P23
Vcc1_5_B[35]
R22
Vcc1_5_B[36]
R23
Vcc1_5_B[37]
R24
Vcc1_5_B[38]
R25
Vcc1_5_B[39]
R26
Vcc1_5_B[40]
T22
Vcc1_5_B[41]
T23
Vcc1_5_B[42]
T26
Vcc1_5_B[43]
T27
Vcc1_5_B[44]
T28
Vcc1_5_B[45]
U22
Vcc1_5_B[46]
U23
Vcc1_5_B[47]
V22
Vcc1_5_B[48]
V23
Vcc1_5_B[49]
W22
Vcc1_5_B[50]
W23
Vcc1_5_B[51]
Y22
Vcc1_5_B[52]
Y23
Vcc1_5_B[53]
B27
Vcc3_3[1]
AG28
VccDMIPLL
AB7
Vcc1_5_A[1]
AC6
Vcc1_5_A[2]
AC7
Vcc1_5_A[3]
AD6
Vcc1_5_A[4]
AE6
Vcc1_5_A[5]
AF5
Vcc1_5_A[6]
AF6
Vcc1_5_A[7]
AG5
Vcc1_5_A[8]
AH5
Vcc1_5_A[9]
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
Vcc1_5_A[10]
AB9
Vcc1_5_A[11]
AC10
Vcc1_5_A[12]
AD10
Vcc1_5_A[13]
AE10
Vcc1_5_A[14]
AF10
Vcc1_5_A[15]
AF9
Vcc1_5_A[16]
AG9
Vcc1_5_A[17]
AH9
Vcc1_5_A[18]
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
VccSus1_05/VccLAN1_05[1]
Y7
VccSus1_05/VccLAN1_05[2]
ICH7-M
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
CORE
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
VCC PAUX
VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]
Vcc3_3/VccHDA
VccSus3_3/VccSusHDA
V_CPU_IO[1]
V_CPU_IO[2]
VCCA3GP
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
IDE
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
PCI
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
USB
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]
Vcc1_5_A[21]
ATXARX
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
USB CORE
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
V5
V1
W2
W7
U6
R7
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
P7
A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
AB17
AC17
T7
F17
G17
AB8
AC8
K7
C28
G20
A1
H6
H7
J6
J7
C494
0.1U_10V
1 2
+3.3V_SUS
C522
0.1U_10V
1 2
TP_ICHVCCSUS1
TP_ICHVCCSUS2
TP_ICHVCCSUS3
+3_3V_IDE
C482
0.1U_10V
1 2
+3_3V_PCI
C491
0.1U_10V
1 2
C507
0.1U_10V
1 2
C473
0.1U_10V
1 2
C528
0.1U_10V
1 2
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
C514
0.1U_10V
1 2
12
C488
1U_10V
C529
0.1U_10V
1 2
C517
0.1U_10V
1 2
C497
0.1U_10V
1 2
C506
0.1U_10V
1 2
C485
0.1U_10V
1 2
C511
0.1U_10V
1 2
T82PAD
T42PAD
T77PAD
C538
*0.1U_10V_NC
1 2
12
+
C165
330U_2.5V
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+RTC_CELL
+3.3V_SUS
+3.3V_SUS
C499
0.1U_10V
1 2
+1.5V_RUN
+1.05V_VCCP
C467
0.1U_10V
1 2
+1.5V_RUN
C470
0.1U_10V
1 2
12
C463
4.7U_10V_0805
+1.05V_VCCP
QUANTA
Title
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
COMPUTER
ICH7-M (POWER&GND)
DM5 1A
星期二
27, 2005
十二月
7
of
14 59,
8
1
+1.8V_SUS +1.8V_SUS
STD(BOT)
DDR_A_D0
A A
B B
DDR_CKE0_DIMMA6,16 DDR_CKE2_DIMMB6,16 DDR_CKE3_DIMMB 6,16
DDR_A_BS27,16
DDR_A_BS07,16
DDR_A_WE#7,16
DDR_A_CAS#7,16
DDR_CS1_DIMMA#6,16
M_ODT16,16
C C
D D
+3.3V_RUN
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10 DDR_B_D14
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51 DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SDATA
CLK_SCLK
V_DDR_MCH_REF
SMbus address A0
1
2
CT_1227: Change
JDIM2 part number
JDIM2
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
FOX_AS0A426-M2SN-7F
CLOCK 0,1
2
3
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
SO-DIMM (200P)
PC4800 DDR2 SDRAM
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
PM_EXTTS#0_R
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R302
10K
1 2
DDR_CKE1_DIMMA 6,16
DDR_CS0_DIMMA# 6,16
R303
10K
1 2
3
M_CLK_DDR0 6
M_CLK_DDR#0 6
1 2
R304
0
DDR_A_BS1 7,16
DDR_A_RAS# 7,16
M_ODT0 6,16
M_CLK_DDR1 6
M_CLK_DDR#1 6
4
DDR_A_DM[0..7] 7
DDR_A_D[0..63] 7
DDR_A_DQS[0..7] 7
DDR_A_DQS#[0..7] 7
DDR_A_MA[0..13] 7,16
PM_EXTTS#0 6
DDR_B_BS27,16
DDR_B_BS07,16
DDR_B_WE#7,16
DDR_B_CAS#7,16
DDR_CS3_DIMMB#6,16
M_ODT36,16
CLK_SDATA17
CLK_SCLK17
+3.3V_RUN
4
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D46
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CLK_SDATA
CLK_SCLK
SMbus address A4
5
+1.8V_SUS +1.8V_SUS
RVS(TOP)
V_DDR_MCH_REF
JDIM1
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
TYC_1775804-2
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
SO-DIMM (200P)
PC4800 DDR2 SDRAM
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
CLOCK 2,3
CKE 2,3CKE 0,1
5
+3.3V_RUN
6
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_D15
DDR_B_D20
DDR_B_D21
PM_EXTTS#0_R
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R343
10K
1 2
6
R344
10K
1 2
DDR_B_DM[0..7] 7
DDR_B_D[0..63] 7
DDR_B_DQS[0..7] 7
DDR_B_DQS#[0..7] 7
DDR_B_MA[0..13] 7,16
M_CLK_DDR3 6
M_CLK_DDR#3 6
DDR_B_BS1 7,16
DDR_B_RAS# 7,16
DDR_CS2_DIMMB# 6,16
M_ODT2 6,16
M_CLK_DDR2 6
M_CLK_DDR#2 6
7
+1.8V_SUS
8
Place these Caps near So-Dimm1.
12
2.2U_6.3V
12
C449
2.2U_6.3V
C448
12
C423
2.2U_6.3V
12
C444
.1U_10V
12
2.2U_6.3V
12
C425
.1U_10V
C424
12
C450
2.2U_6.3V
12
2.2U_6.3V
12
C446
.1U_10V
C427
12
C445
.1U_10V
+3.3V_RUN
12
C447
2.2U_6.3V
+1.8V_SUS
Place these Caps near So-Dimm1.
12
C443
.1U_10V
V_DDR_MCH_REF
12
C451
.1U_10V
Place these Caps near So-Dimm1.
No Vias Between the Trace of
PIN to CAP.
+1.8V_SUS
Place these Caps near So-Dimm2.
12
12
C139
2.2U_6.3V
12
C138
.1U_10V
12
C124
2.2U_6.3V
12
C140
2.2U_6.3V
12
C134
.1U_10V
12
C133
.1U_10V
+3.3V_RUN
C141
2.2U_6.3V
+1.8V_SUS
Place these Caps near So-Dimm2.
12
C142
.1U_10V
V_DDR_MCH_REF
12
C126
.1U_10V
12
2.2U_6.3V
12
C123
2.2U_6.3V
C130
12
C131
2.2U_6.3V
12
C125
.1U_10V
Place these Caps near So-Dimm2.
No Vias Between the Trace of
PIN to CAP.
QUANTA
Title
Size Document Number Rev
Date: Sheet
COMPUTER
System DRAM Expansion (200P-DDR_SODIMM X 2)
DM5 3A
星期二
27, 2005
十二月
7
of
15 59,
8
Loading...