Page 1
A
COMPAL CONFIDENTIAL
B
C
D
E
MODEL NAME :
PCB NO :
1 1
COMPAL P/N :
LA-3741P
JAU00
DA800008W0L
Carson Schematics Document
uFCBGA Mobile Merom-ULV
Intel Calistoga-GMS + ICH7M
2007-01-24
REV : 0.1 (DELL: X00)
HW POP option control table
2 2
BOM No.
CPU P/N
CPU Type
Speed/power
01 BOM 02 BOM
45148731L01 45148731L02 4514873 1L03 45148731L04
SA00001ND0L
Dual core
SA00001MA1L SA00001ND0L
Dual core
1.06G , 9W1.2G ,9W
C41,C44 220 uf 220 uf
C42,C43
3 3
C21,C26,C29,C31
C34,C36,C28,C23
Pop Pop
10 uf
10 uf
C694,C697,C37,C39,C22
C698,C693,C25,C40,C35
C699,C700,C30,C33,C27
Pop Pop
C703,C704,C38
03 BOM 04 BOM
SA00001MA1L
Dual core Dual core
1.06G , 9W1.2G ,9W
220 uf 220 uf
Pop Pop
10 uf 10 uf
Pop Pop
Location: U2
330 uf Poly Cap ; P/N : SGA00001P0L
220 uf Poly Cap ; P/N : SGA00002D0L
POP 2@ ; 220 uf for Dual core
220 uf Poly Cap ; ( P/N : SGA00002D0L)
10 uf MLCC Cap ; P / N ( S E 00000110L)
22 uf MLCC Cap ; P / N ( S E 1 6 0 106M8L)
POP 2@ ; 10 uf for Dual core
10 uf MLCC Cap ; P / N ( S E 1 6 0 106M8L)
JP3
U50
4 4
Depop
Pop
Depop
Pop Pop
Depop DepopPop
POP 4@ ; For with TAA Board
POP 1@ ; For without TAA Board
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
DA800008W0L
PCB 02F LA-3741P REV0 M/B
A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-3741P
153Friday, January 26, 2007
E
0.1
of
Page 2
A
Compal confidential
Model : HAU30
B
C
D
E
Block Diagram
FAN
+FAN1_VOUT
1 1
pg 18
+2.5V_RUN
pg 18
DVI
2 2
PCI BUS
IDSEL:AD24
(PIRQA#,GNT0#,REQ0#)
DOCKING PORT
+DOCK_PWR_SRC
+3.3V_RUN
+2.5V_LOM
pg 38
USB[7]
Mini Card2
WLAN
3 3
+3.3V_RUN
pg 36
DOCKING
BUFFER
+5V_RUN
Mini Card 1
+3.3V_RUN
+3.3V_LAN+3.3V_LAN
+1.5V_RUN+1.5V_RUN
SIM Card
+SIM_PWR
CardBus & 1394 & SD
R5C843 CSP208
pg 37
+3.3V_RUN/ +1.5V_RUN 100MHz
+3.3V_RUN
+3.3V_SUS
GIGA Enthernet
WWAN
pg 36
HUB USB[2]USB[0]
pg 36
+3.3V_LAN
Thermal
GUARDIAN
EMC4000
+3.3V_SUS
CRT CONN
+5V_RUN
LVDS CONN
+LCDVDD
+GFX_PWR_SRC
DVI Bridge SI1362
+3.3V_RUN
+1.8V_RUN
+3.3V_RUN 33MHz
IDSEL:AD17
(PIRQB,C,D#,GNT2#,REQ2#)
pg 31,32
BCM5752
pg 29
LAN SWITCH
PI3L500E
+3.3V_LAN
pg 30
pg 18
pg 21
RGB
pg 19
LVDS
DVO
pg 20
HUB USB[1]
TV
SD card SLOT
+SD_VCC
1394 CONNCard Bus SLOT
PCI Express BUS
LPC BUS
USB[1]
HUB USB[4]
HUB_USB[3]
pg 32
pg 31pg 32
+1.05V_VCCP
+VCC_CORE
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
100MHz
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP
+3.3V_RUN
33MHz
SMSC SIO
ECE5018
+3.3V_ALW
Pentium-M
Merom-2M ULV
uFCBGA CPU
479pin
System Bus
FSB 400/533 MHz
INTEL
Calistoga-GMS
998pin BGA
pg 10,11,12,13,14
DMI
INTEL
ICH7-M
652pin BGA
pg 22,23,24,25
HUB USB[1]
HUB USB[2]
pg 39
H_D#(0..63)H_A#(3..31)
pg 7,8
SPI
Memory BUS
(DDR2)
48MHz
Azalia I/F
ATA100
+1.05V_VCCP
+1.8V_SUS 400/533MHz
USB[4] REAR
USB[6] REAR
USB[5] REAR
PATA HDD
+3.3V_HDD
pg 26 pg 27
Azalia Codec
STAC9200
+3.3V_RUN
+VDDA
CPU ITP Port
Clock Generator
SLG84450VTR
+3.3V_RUN
DDRII 1GB on Board
+0.9V_DDR_VTT
+1.8V_SUS
DDRII-DIMM X1
BANK 2, 3
+0.9V_DDR_VTT
+1.8V_SUS
USB Ports X1
+5V_SUS
pg 33
USB Ports X1
+5V_SUS
PWR USB X1
+5V_SUS
DH_PORT_PWRSRC
pg 33
pg 33
MDC
+3.3V_SUS
RJ11
pg 30
pg 6pg 7
pg 16,17
pg 15
pg 34
Cable
RJ45
pg 30
Power Sequence
DC IN
4 4
BATT IN
CHARGER
pg 45
pg 46
pg 51
3V/5V/15V
1.5V/1.05V
1.8V/0.9V
VCORE (IMVP-6)
A
pg 47pg 42,43
pg 48
pg 49
pg 50
Transformer
+2.5V_LOM
pg 30
Power On/Off
SW & LED
pg 44
DC/DC Interface
pg 45
B
Bluetooth
+3.3V_RUN
USB_BIO
Fingerprint
+3.3V_RUN
pg 34
Smart Card
+5V_RUN
pg 41
+3.3V_RUN
OZ77C6
pg 35
SLOT
pg 35
FIR
pg 37
Int.KBD &
Stick
Stick
C
pg 41
+RTC_CELL
+3.3V_ALW
SMSC KBC
MEC5004
Touch Pad
+5V_RUN
pg 40
+3.3V_ALW
pg 41
SPI
ST M25P80
pg 40
AMP & INT.
Speaker
+5V_SUS +3.3V_RUN
INT MIC
+5V_SUS
pg 28 pg 28
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
D
Date: Sheet
HeadPhone &
MIC Jack
Compal Electronics, Inc.
Block Diagram
LA-3741P
253Friday, January 26, 2007
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Page 3
5
Ceramic Capacitors :
4
3
TABLE
PCI
2
1
0.1U_0402_6.3VXX
D D
Tolerance
Temperatur e Characteristics
Rated Voltage
PCI DEVICE
CARD BUS
DOCKING
IDSEL
AD17
AD24 0
REQ#/GNT#
2
PIRQ
B,C,D
A
Package Size
Value
PM TABLE
+5V_RUN
Tantalum or Polymer Capacitors :
power
plane
+3.3V_ALW
10U_D2_10VX_R45
C C
Low ESR Mark : 45 m ohm
Tolerance
Rated Voltage
Package Size
Value
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
ON
ON
ON
ON
+3.3V_SRC
+3.3V_SUS
+5V_SUS+5V_ALW
+1.8V_SUS
+15V_SUS
ON
ON
ON
OFF
OFF
+3.3V_RUN
+1.8V_RUN
+0.9V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_VCCP
+2.5V_RUN
ON
ON
OFF
OFF
OFFOFF
Capacitor Spec Guide:
Temperature Characteristics:
B B
A A
Symbol
CODE
Tolerance:
Symbol
CODE
Z5U
8
9
COG SJ
HI J
UK
UJ
A
+-0.1PF
+-0.05PF
M
K
+-20%
+-10%
+-30%
Z5V
X6SNPO
SL
N
A
1
B
2
Z5P
B
BJ
K
X5S
C
+-0.25PF
P
+100,-0%
4
5
G
X
6
X5R
SH
H
+-3%
Z
+80,-20%
30
Y5U X7R
C
CH
D
+-0.5PF +-1PF
Q
+20,-10%
+30,-10%
Y5P
Y5V
DEFG
CJ
CK
F
+-2%
V
+40,-20%
7
J
+-5%
NOTE1:
@XX : Depop component
USB
TABLE
USB PORT#
0
1
2
3
4,6
5
7
DESTINATION
Mini 2(WLAN)
USB Hub (5018)
N/A
N/A
REAR
PWR USB
Docking
USB H U B DESTINATION
1
2
3
4
USB HUB on
OZ77C6LN
DP_HUB
PC Card Bay
Mini 1(WWAN)
SMART CARD
Blue tooth
DESTINATION
Fingerprint
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-3741P
353Friday, January 26, 2007
1
0.1
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Page 4
5
4
3
2
1
ALWON
D D
ALWON
ADAPTER
+5V_ALW
+3.3V_ALW
+PWR_SRC
FDS4435 +GFX_PWR_SRC
RUN_ON
BATTERY
TPS51120
C C
SUS_ON
+5V_SUS
SUS_ON
+3.3V_SRC
AD3207 SC480
RUNPWROK
+VCC_CORE
SC483
RUNPWROK
+1.5V_RUN
RUNPWROK
+VCCP
SUSPWROK_5V
+1.8V_SUS
RUN_ON
+0.9V_DDR_VTT
B B
SI4800
RUN_ON
+5V_RUN
PL8
+15V_SUS
793475
VDDA
SI4800
RUN_ON
(Option)
AUDIO_AVDD_ON
+3.3V_RUN
SI3456
ENAB_3VLAN
+3.3V_LAN
SI3456
RUN_ON
+1.8V_RUN
L47
EMC4000
A A
+2.5V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-3741P
453Friday, January 26, 2007
1
of
0.1
Page 5
5
4
3
2
1
+3.3V_SUS
2.2K 2.2K 2.2K 2. 2K
ICH_SMBCLK
C22
D D
C C
ICH7-M
SIO
ICH_SMBDATA
B22
+3.3V_ALW
10K
CLK_SMB
6
DAT_SMB +3.3V_ALW
5
+5V_ALW
10K 10K
DOCK_SMB_CLK
10
DOCK_SMB_DAT
9
+3.3V_ALW
+3.3V_SUS
10K
SMBUS Address [TBD]
+5V_ALW
WWAN
2N7002
2N7002
3032
C8C7
5752M
LOM
SMBUS Address [C8]
SMBUS Address [TBD]
8
GUARDIAN
7
Power USB
DOG house
39
DOCKING
40
3032
WLAN
SMBUS Address [2F]
SMBUS Address [5A]
SMBUS Address [C4, 72, 70, 48]
CLK_SCLK
CLK_SDATA
+3.3V_RUN
16
CLK GEN.
17
SMBUS Address [D2]
DDR II 1G
ON Board
SMBUS Address [A0]
197
DIMM1
195
SMBUS Address [A2]
8.2K 8. 2K
112
Macallan IV
B B
A A
111
8
7
SBAT_SMBCLK
SBAT_SMBDAT
+3.3V_ALW
+3.3V_ALW
8.2K8.2K
PBAT_SMBCLK
PBAT_SMBDAT +3.3V_ALW
100
100
6
INV
5
3
BATTERY
4
CONN
9
CHARGER
10
Inverter
SMBUS Address [58]
SMBUS Address [16]
SMBUS Address [12]
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-3741P
553Friday, January 26, 2007
1
0.1
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Page 6
5
D
1
3
G S
2
2N7002
ICH_SMBDATA<24,29,36> CLK_SDATA <15,17>
D D
+3.3V_RUN
ICH_SMBCLK<24,29,36>
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
ICH_SMBDATA
ICH_SMBCLK
000
1
*
C C
00
1
0
11
0
1
1
0
1
1
11
0
00
1
0
1
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
133
166
B B
A A
0
0
+3.3V_RUN
5
1 2
12
2N7002W-7-F_SOT323~D
MHz
266
133
200
166
333
100
400
R69
10K_0402_5%~D
FSA
R72
@
10K_0402_5%~D
+3.3V_RUN
Q1
D
1 3
1 3
D
SRC
MHz
100
100
100
100
100
100
100
Reserve
12
S
G
2
2
G
Q2
S
2N7002W-7-F_SOT323~D
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
33.3
0
1
12
R5
R4
2.2K_0402_5%~D
2.2K_0402_5%~D
CLK_SDATA
CLK_SCLK
1
2
C10
4.7U_0603_6.3V6M~D
Place crystal within
500 mils of CK410
CLK_SD_48M<31>
CLK_ICH_48M<24>
CLK_SMCARD_48M<35>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>
CPU_MCH_BSEL2<8,10>
CLK_PCI_5004<40>
CLK_PCI_SIO<39>
CLK_PCI_PCCARD<31>
CLK_PCI_DOCK<38>
CLK_PCI_LOM<29>
CLK_ICH_14M<24>
CLK_SIO_14M<39>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<22>
CLK_ENABLE#<50>
FCTSEL1 PIN43 PIN44 PIN47 PIN48
01DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0
4
+3.3V_RUN
C6
0.1U_0402_16V4Z~D
CLK_SCLK <15,17>
+CK_VDD_48+CK_VDD_A +CK_VDD_REF
1
2
C11
0.047U_0402_16V7K~D
1
2
C12
4.7U_0603_6.3V6M~D
C15
27P_0402_50V8J~D
12
C16
27P_0402_50V8J~D
12
CLK_SD_48M
CLK_ICH_48M FSA
CLK_SMCARD_48M
CLK_PCI_5004
CLK_PCI_SIO
CLK_PCI_PCCARD PCI_PCCARD
CLK_PCI_LOM PCI_LOM
CLK_SIO_14M
MCH_DREFCLK# DOT96#
CLK_PCI_ICH PCI_ICH
CLK_ENABLE#
4
1 2
L1
BLM18PG600SN1_0603~D
1
60ohm,500mA,0.1ohm
2
1
2
12
L2
BLM18PG600SN1_0603~D
C13
0.047U_0402_16V7K~D
X1
14.31818MHz_20P_1BX14318CC1A~D
R30 0_0402_5%~D
R605 39_0402_5%~D
R32 39_0402_5%~D
R34 39_0402_5%~D
R561 8.2K_0402_5%~D@
R56 8.2K_0402_5%~D
R35 39_0402_5%~D
R36 39_0402_5%~D
R38 56_0402_5%~D
R39 56_0402_5%~D
R37 56_0402_5%~D
R40 15_0402_5%~D
R41 15_0402_5%~D
R42 33_0402_5%~D
R43 33_0402_5%~D
+3.3V_RUN
R48 56_0402_5%~D
+CK_VDD_MAIN2
1 2
60ohm,500mA,0.1ohm
1
2
1 2
12
12
1 2
12
12
12
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN
@
10K_0402_5%~D
1 2
12
R71
10K_0402_5%~D
+CK_VDD_MAIN
C14
0.047U_0402_16V7K~D
1 2
R25 1_0603_5%~D
1 2
R27 2.2_0603_5%~D
1 2
R46 10K_0402_5%~D
1 2
R51 475_0402_1%~D
R67
FCTSEL1
3
+CK_VDD_MAIN
1
C1
10U_0805_10V4Z~D
2
1
C7
10U_0805_10V4Z~D
2
1
C2
0.1U_0402_16V4Z~D
2
1
C8
0.1U_0402_16V4Z~D
2
1
C3
0.1U_0402_16V4Z~D
2
1
C9
0.1U_0402_16V4Z~D
2
2
1
C4
0.1U_0402_16V4Z~D
2
Place near each pin
W>40 mil
1 2
R15 2.2_0603_5%~D
U1
1
VDDSRC
49
VDDSRC
54
VDDSRC
65
VDDSRC
30
VDDPCI
36
VDDPCI
12
+CK_VDD_REF
+CK_VDD_48
CLK_XTAL_IN
CLK_XTAL_OUT
FSC
FCTSEL1
PCI_DOCKCLK_PCI_DOCK
CLK14M_REFCLK_ICH_14M
DOT96MCH_DREFCLK
CLKIREF
CLK_SCLK
CLK_SDATA
VDDCPU
18
VDDREF
40
VDD48
20
X1
19
X2
41
USB_48MHz/FSLA
45
FSLB/TEST_MODE
23
REF0/FSLC/TEST_SEL
34
PCICLK4/FCTSEL1
33
PCICLK3
32
PCICLK2
27
PCICLK1
22
REF1
43
DOTT_96MHz/27MHz
44
DOTC_96MHz/27MHz(SS)
37
ITP_EN/PCICLK_F0
39
Vtt_PwrGd#/PD
9
IREF
16
SMBCLK
17
SMBDAT
4
GNDSRC
15
GNDCPU
21
GNDREF
31
GNDPCI
35
GNDPCI
42
GND48
68
GNDSRC
73
THRM_PAD
74
THRM_PAD
75
THRM_PAD
76
THRM_PAD
SLG84450VTR_QFN72~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+CK_VDD_A
VDDA
GNDA
PCI_SRC_STOP#
CPU_STOP#
CPUT1
CPUC1
CPUT0
CPUC0
CPUT_ITP/SRCT10
CPUC_ITP/SRCC10
SRCT9
SRCC9
CLKREQ9#
SRCT8
SRCC8
CLKREQ8#
SRCT7
SRCC7
CLKREQ7#
SRCT6
SRCC6
CLKREQ6#
SRCT5
SRCC5
CLKREQ5#
SRCT4
SRCC4
CLKREQ4#
SRCT3
SRCC3
CLKREQ3#
SRCT2
SRCC2
CLKREQ2#
SRCT1
SRCC1
CLKREQ1#
LCD100/96/SRC0_T
LCD100/96/SRC0_C
Place near CK410+
7
8
H_STP_PCI#
25
H_STP_CPU#
24
11
10
CPU_BCLK
14
13
CPU_ITP
6
CPU_ITP#
5
3
2
72
MCH_3GPLL CLK_MCH_3GPLL
70
69
71
66
67
38
PCIE_ICH
63
PCIE_ICH#
64
62
60
61
29
58
59
57
55
56
28
PCIE_MINI2
52
PCIE_MINI2#
53
26
PCIE_MINI1
50
PCIE_MINI1#
51
46
DOT96_SSC
47
DOT96_SSC#
48
2
1
2
CLK_MCH_BCLKMCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_LOMPCIE_LOM
CLK_PCIE_LOM#PCIE_LOM#
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
1
C5
0.1U_0402_16V4Z~D
2
1 2
R24 33_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R26 33_0402_5%~D
R28 33_0402_5%~D
R29 33_0402_5%~D
R31 33_0402_5%~D
R33 33_0402_5%~D
R53 33_0402_5%~D
R54 33_0402_5%~D
R55 10K_0402_5%~D
R49 33_0402_5%~D
R50 33_0402_5%~D
R52 10K_0402_5%~D
R44 33_0402_5%~D
R45 33_0402_5%~D
R47 10K_0402_5%~D
R61 33_0402_5%~D
R62 33_0402_5%~D
R63 10K_0402_5%~D
R64 33_0402_5%~D
R65 33_0402_5%~D
R66 10K_0402_5%~D
R68 33_0402_5%~D
R70 33_0402_5%~D
1
C643
0.1U_0402_16V4Z~D
H_STP_PCI# <24>
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
H_STP_CPU# <24>
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_LOM <29>
CLK_PCIE_LOM# <29>
LOM_CLKREQ# <29>
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_3GPLLREQ# <10>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
CLK_PCIE_MINI2 <36>
CLK_PCIE_MINI2# <36>
MINI2CLK_REQ# <36>
CLK_PCIE_MINI1 <36>
CLK_PCIE_MINI1# <36>
MINI1CLK_REQ# <36>
DREF_SSCLK <10>
DREF_SSCLK# <10>
DREF_SSCLK#
R1 49.9_0402_1%~D
R2 49.9_0402_1%~D
R3 49.9_0402_1%~D
R6 49.9_0402_1%~D
R7 49.9_0402_1%~D
R8 49.9_0402_1%~D
R9 49.9_0402_1%~D
R10 49.9_0402_1%~D
R11 49.9_0402_1%~D
R12 49.9_0402_1%~D
R13 49.9_0402_1%~D
R14 49.9_0402_1%~D
R16 49.9_0402_1%~D
R17 49.9_0402_1%~D
R18 49.9_0402_1%~D
R19 49.9_0402_1%~D
R20 49.9_0402_1%~D
R21 49.9_0402_1%~D
R22 49.9_0402_1%~D
R23 49.9_0402_1%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-3741P
653Friday, January 26, 2007
1
of
0.1
Page 7
5
4
3
2
1
H_A#[3..31]<10>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]<10>
H_ADSTB#0<10>
C C
R82
56_0402_5%~D
@
1 2
C18
+1.05V_VCCP
B B
H_THERMDA<18>
2200P_0402_50V7K~D
H_THERMDC<18>
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
H_ADSTB#1<10>
CLK_CPU_BCLK<6>
CLK_CPU_BCLK#<6>
H_ADS#<10>
H_BNR#<10>
H_BPRI#<10>
H_BR0#<10>
H_DEFER#<10>
H_DRDY#<10>
H_HIT#<10>
H_HITM#<10>
H_LOCK#<10>
H_RESET#<10>
H_RS#[0..2]<10>
H_TRDY#<10>
ITP_DBRESET#<24,40>
H_DBSY#<10>
H_DPSLP#<23>
H_DPRSTP#<23,50>
H_DPWR#<10>
CPU_PROCHOT#<39>
H_PWRGOOD<23>
H_CPUSLP#<10,23>
1
2
H_THERMTRIP#<18>
5
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
CPU_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
TEST2
R84 51_0402_5%~D
R579 1K_0402_5%~D@
1 2
1 2
U2A
J4
A3#
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
K3
H2
K2
J3
L5
L2
V4
A22
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
YONAH-ULV
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
ADDR GROUP
A25#
A26#
A27#
A28#
A29#
A30#
A31#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
BCLK0
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMDA
THERMDC
THERMTRIP#
MISC
THERMAL
DIODE
Yonah-ULV_1.06G SC_UFCBGA479~D
DATA GROUP
LEGACY CPU
For Yonah B0
4
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
LINT0
LINT1
STPCLK#
+1.05V_VCCP
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
INIT#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
1 2
R83 56_0402_5%~D
1 2
R468 75_0402_5%~D
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_THERMTRIP#
CPU_PROCHOT#TEST1
H_D#0
E22
H_STPCLK# <23>
Link CIS
H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>
H_A20M# <23>
H_FERR# <23>
H_IGNNE# <23>
H_INIT# <23>
H_INTR <23>
H_NMI <23>
H_SMI# <23>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
H_D#[0..63] <10>
ITP_TDO
1 2
R80 22.6_0402_1%~D
H_DSTBN#[0..3] <10>
H_DSTBP#[0..3] <10>
+1.05V_VCCP
1
2
+3.3V_SUS
+1.05V_VCCP
1
C17
2
0.1U_0402_16V4Z~D
C633
1 2
R73 150_0402_1%~D
1 2
R74 51_0402_5%~D
1 2
R75 54.9_0402_1%~D
1 2
R76 39_0402_5%~D
1 2
R78 150_0402_1%~D
1 2
R575 54.9_0402_1%~D@
1 2
R79 680_0402_5%~D
1 2
R81 27.4_0402_1%~D
0.1U_0402_16V4Z~D
ITP_DBRESET#
ITP_TDO
H_RESET#
ITP_TMS
ITP_TDI
ITP_BPM#5
ITP_TRST#
ITP_TCK
This shall place near CPU
+1.05V_VCCP
J2
28
VTT1
27
VTT0
26
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
R77
22.6_0402_1%~D
H_RESET#
1 2
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
MOLEX_52435-2891_28P~D@
30
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Yonah-ULV in mFCPGA479
LA-3741P
753Friday, January 26, 2007
1
of
0.1
Page 8
5
4
3
2
1
Length match within 25 mils
VCCSENSE<50>
VSSSENSE<50>
+1.5V_RUN
D D
+VCC_CORE
1 2
R88 100_0402_1%~D
1 2
R89 100_0402_1%~D
Layout close CPU
VCCSENSE
VSSSENSE
1
C20
C19
2
0.01U_0402_16V7K~D
Close to U2.B26
10U_0805_6.3V6M~D
V_CPU_GTLREF
+1.05V_VCCP
R_A
12
R87
1K_0402_1%~D
R_B
12
R90
2K_0402_1%~D
VCCSENSE/VSSSENSE
Layout close CPU PIN AD26
0.5 inch (max)
C C
B B
trace width 18mil,
space 7mil, for
other signal 15mil
12
R91
R92
27.4_0402_1%~D
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
0
12
12
R93
27.4_0402_1%~D
54.9_0402_1%~D
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
12
mils away from any
other toggling signal.
R94
54.9_0402_1%~D
CPU_BSEL0
1
1
1
2
V_CPU_GTLREF
CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
+1.05V_VCCP
H_PSI#<50>
VID0<50>
VID1<50>
VID2<50>
VID3<50>
VID4<50>
VID5<50>
VID6<50>
+VCC_CORE
VCCSENSE
VSSSENSE
H_PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
COMP0
COMP1
COMP2
COMP3
U2B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH-ULV
T6
VCCP
R6
VCCP
K21
VCCP
J21
VCCP
M21
VCCP
N21
VCCP
T21
VCCP
R21
VCCP
V21
VCCP
W21
VCCP
V6
VCCP
G21
VCCP
AE6
PSI#
AD6
VID0
AF5
VID1
AE5
VID2
AF4
VID3
AE3
VID4
AF2
VID5
AE2
VID6
AD26
GTLREF
B22
BSEL0
B23
BSEL1
C21
BSEL2
R26
COMP0
U26
COMP1
U1
COMP2
V1
COMP3
E7
VCC
AB20
VCC
AA20
VCC
AF20
VCC
AE20
VCC
AB18
VCC
AB17
VCC
AA18
VCC
AA17
VCC
AD18
VCC
AD17
VCC
AC18
VCC
AC17
VCC
AF18
VCC
AF17
VCC
D2
RSVD
F6
RSVD
D3
RSVD
C1
RSVD
AF1
RSVD
D22
RSVD
C23
RSVD
C24
RSVD
AA1
RSVD
AA4
RSVD
AB2
RSVD
AA3
RSVD
M4
RSVD
N5
RSVD
T2
RSVD
V3
RSVD
B2
RSVD
C3
RSVD
T22
RSVD
B25
RSVD
Yonah-ULV_1.06G SC_UFCBGA479~D
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
AF3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
POWER, GROUNG, RESERVED SIGNALS AND NC
+VCC_CORE
U2C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
YONAH-ULV
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
Yonah-ULV_1.06G SC_UFCBGA479~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
Link CIS
Link CIS
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah-ULV in mFCBGA479
LA-3741P
853Friday, January 26, 2007
1
0.1
of
Page 9
5
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
D D
Place these inside
socket cavity on L8
(Sorth side
Secondary)
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C21
22U_0805_6.3V6M~D
C31
22U_0805_6.3V6M~D
<BOM Structure>
C693
2@
10U_0805_4VAM~D
1
C22
2@
10U_0805_4VAM~D
2
1
C32
@
10U_0805_4VAM~D
2
1
C694
2@
10U_0805_4VAM~D
2
1
C23
22U_0805_6.3V6M~D
2
1
C33
2@
10U_0805_4VAM~D
2
1
C695
@
10U_0805_4VAM~D
2
4
1
C24
@
10U_0805_4VAM~D
2
1
C34
22U_0805_6.3V6M~D
2
1
C696
@
10U_0805_4VAM~D
2
1
C25
2@
10U_0805_4VAM~D
2
1
C35
2@
10U_0805_4VAM~D
2
1
C697
2@
10U_0805_4VAM~D
2
1
C26
22U_0805_6.3V6M~D
2
1
C36
22U_0805_6.3V6M~D
2
1
C698
2@
10U_0805_4VAM~D
2
1
C27
2@
10U_0805_4VAM~D
2
1
C37
2@
10U_0805_4VAM~D
2
1
C699
2@
10U_0805_4VAM~D
2
3
1
C28
22U_0805_6.3V6M~D
2
1
C38
2@
10U_0805_4VAM~D
2
1
C700
2@
10U_0805_4VAM~D
2
1
C29
22U_0805_6.3V6M~D
2
1
C39
2@
10U_0805_4VAM~D
2
1
C701
@
10U_0805_4VAM~D
2
1
2
1
2
1
2
C30
2@
10U_0805_4VAM~D
C40
2@
10U_0805_4VAM~D
C702
@
10U_0805_4VAM~D
2
1
+VCC_CORE
1
C703
2@
10U_0805_4VAM~D
2
C C
1
C704
2@
10U_0805_4VAM~D
2
Note:
C21,C23,C26,C28,C29,C31,C34,C36
use 22U on Single Core CPU and
use 10U on Dual Core CPU.
High Frequence Decoupling
Temp. characteristics: X5R
Operating range: -55~+85degree
Near VCORE regulator.
+VCC_CORE
Note: C41,C44
will change to
220U 2.5V 6M on
South Side Secondary
1
+
C43
C42
2@
2@
2
220U_D_2VM_R7M~D
+
C705
+
@
2
2
330U_D_2.5VM_R6M~D
220U_D_2VM_R7M~D
1
+
C44
C41
2
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
1
1
North Side Secondary
1
1
+
+
C706
@
2
2
330U_D_2.5VM_R6M~D
Dual Core CPU for
CPU transition
noise
ESR <= 1.5m ohm
Capacitor = 1320uF
7mOhm
7mOhm
6mOhm
6/7mOhm
6/7mOhm
B B
+1.05V_VCCP
1
+
C45
@
2
330U_D2E_2.5VM_R9~D
PS CAP
1
C46
0.1U_0402_10V7K~D
2
PS CAP
PS CAP
1
C47
0.1U_0402_10V7K~D
2
PS CAP
1
2
CRB was 270uF
6mOhm
PS CAP
PS CAP
C48
0.1U_0402_16V4Z~D
1
C49
0.1U_0402_16V4Z~D
2
1
C50
0.1U_0402_10V7K~D
2
1
C51
0.1U_0402_10V7K~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU Bypass
LA-3741P
953Friday, January 26, 2007
1
0.1
of
Page 10
5
4
3
2
1
AF33
AG1
AM30
AG33
AF1
AK1
AN30
AN21
AN22
AF26
AF25
AG14
AF12
AK14
AH12
AJ21
AF11
AE12
AF14
AJ14
AJ12
AN12
AN14
AA33
AE1
Y29
Y32
Y28
Y31
V28
V31
V29
V32
AJ1
U3B
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
Calistoga-GMS_FCBGA998~D
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
DMI
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
CFG/RSVD
DDR2 MUXING
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
D_REFCLKN
D_REFCLKP
CLK
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
C18
E18
G20
G18
J20
J18
K32
K31
C17
F18
A3
E31
G21
F26
H26
J15
AB29
W27
A27
A26
J33
H33
J22
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CFG3
CFG5
CFG6
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST_R#
1 2
MCH_ICH_SYNC# <22>
PM_BMBUSY# <24>
PM_EX TTS#0 <15>
PM_EX TTS#1 <24>
THERMTRIP_MCH# <18>
ICH_PWRGD <24,43>
MCH_DREFCLK# <6>
MCH_DREFCLK <6>
DREF_SSCLK# <6>
DREF_SSCLK <6>
CLK_3GPLLREQ# <6>
Strap Pin Table
CFG5
CFG19
(DMI Lane Reversal)
Calistoga-GM S n ot ha ve CFG4,CFG[7..18],CFG[20]
Need to double check
CFG19<13>
Low = DMI x 2
High = DMI x 4
Low = Normal
Operation (Default):
Lane number in Order
High = Reverse Lane
PM_EXTTS#0
PM_EXTTS#1
CPU_MCH_BSEL0
THERMTRIP_MCH#
CFG5
R108 10K_0402_5%~D
R109 10K_0402_5%~D@
1 2
R110 1K_0402_5%~D @
1 2
R113 1K_0402_5%~D @
1 2
R114 75_0402_5%~D
1 2
R115 2.2K_0402_5%~D
12
12
CPU_MCH_BSEL0 <6,8>DMI_MRX_ITX_N0<24>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T2PAD~D
T3PAD~D
PLTRST# <20,22,24,29,36>
R100100_0402_1%~D
*
+3.3V_RUN
+1.05V_VCCP
H_D#[0..63]<7>
D D
C C
+1.05V_VCCP
12
12
R103
R104
54.9_0402_1%~D
54.9_0402_1%~D
B B
12
R106
24.9_0402_1%~D
Layout Note:
H_XRCOMP & H_YRCOMP trace width
A A
and spacing is 10/20
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_SWNG0
H_YRCOMP
H_YSCOMP
H_SWNG1
12
R107
24.9_0402_1%~D
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
A10
A6
C15
J1
K1
H1
U3A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
V_DDR_MCH_REF<15,16,17,49>
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
HCLKN
HOST
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
Calistoga-GMS_FCBGA998~D
V_DDR_MCH_REF
C55
@
0.1U_0402_10V6K~D
H_A#3
F8
H_A#4
D12
H_A#5
C13
H_A#6
A8
H_A#7
E13
H_A#8
E12
H_A#9
J12
H_A#10
B13
H_A#11
A13
H_A#12
G13
H_A#13
A12
H_A#14
D14
H_A#15
F14
H_A#16
J13
H_A#17
E17
H_A#18
H15
H_A#19
G15
H_A#20
G14
H_A#21
A15
H_A#22
B18
H_A#23
B15
H_A#24
E14
H_A#25
H13
H_A#26
C14
H_A#27
A17
H_A#28
E15
H_A#29
H17
H_A#30
D17
H_A#31
G17
H_ADS#
F10
H_ADSTB#0
C12
H_ADSTB#1
H16
H_VREF
E2
H_BNR#
B9
H_BPRI#
C7
H_BR0#
G8
H_RESET#
B10
H_VREF
E1
AA6
AA5
H_DBSY#
C10
H_DEFER#
C6
H5
J6
T9
U6
H_DPWR#
G7
H_DRDY#
E6
H_DSTBN#0
F3
H_DSTBN#1
M8
H_DSTBN#2
T1
H_DSTBN#3
AA3
H_DSTBP#0
F4
H_DSTBP#1
M7
H_DSTBP#2
T2
H_DSTBP#3
AB3
H_HIT#
C8
H_HITM#
B4
H_LOCK#
C5
H_REQ#0
G9
H_REQ#1
E9
H_REQ#2
G12
H_REQ#3
B8
H_REQ#4
F12
H_RS#0
A5
H_RS#1
B6
H_RS#2
G10
H_CPUSLP#
E8
H_TRDY#
E10
1
2
H_A#[3..31] <7>
+1.05V_VCCP
12
R95
221_0402_1%~D
12
R96
100_0402_1%~D
+1.05V_VCCP
12
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_RESET# <7>
CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>
H_DBSY# <7>
H_DEFER# <7>
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_DPWR# <7>
H_DRDY# <7>
H_DSTBN#[0..3] <7>
H_DSTBP#[0..3] <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_REQ#[0..4] <7>
H_RS#[0..2] <7>
H_CPUSLP# <7,23>
H_TRDY# <7>
12
+1.05V_VCCP
12
12
R105
R97
221_0402_1%~D
R98
100_0402_1%~D
R102
100_0402_1%~D
200_0402_1%~D
Stuff R111 & R112 for A1 Calistoga
1
2
1
2
1
C54
2
H_SWNG1
C52
0.1U_0402_10V6K~D
H_SWNG0
0.1U_0402_10V6K~D
H_VREF
0.1U_0402_10V6K~D
+1.8V_SUS
C53
R99 80.6_0402_1%~D
R101 80.6_0402_1%~D
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
T13 PAD~D
DDR_CKE2_DIMMA<15>
DDR_CKE3_DIMMA<15>
T14 PAD~D
DDR_CS2_DIMMA#<15>
DDR_CS3_DIMMA#<15>
T15 PAD~D
1 2
1 2
V_DDR_MCH_REF
Layout Note:
Route as short
as possible
12
R111
@
40.2_0402_1%~D
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
12
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0
DDR_CKE1
DDR_CKE2_DIMMA
DDR_CKE3_DIMMA
DDR_CS0#
DDR_CS1#
DDR_CS2_DIMMA#
DDR_CS3_DIMMA#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
M_OCDOCMP0
M_OCDOCMP1
M_CLK_DDR0<16,17>
M_CLK_DDR1<16,17>
M_CLK_DDR2<15>
M_CLK_DDR3<15>
M_CLK_DDR#0<16,17>
M_CLK_DDR#1<16,17>
M_CLK_DDR#2<15>
M_CLK_DDR#3<15>
DDR_CKE0<16,17>
DDR_CS0#<16,17>
M_ODT0<16,17>
M_ODT2<15>
M_ODT3<15>
R112
@
40.2_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(1 of 5)
LA-3741P
1
10 53Friday, January 26, 2007
0.1
of
Page 11
5
4
3
2
1
D D
DDR_A_BS0<16,17>
DDR_A_BS1<16,17>
DDR_A_BS2<16,17>
DDR_A_DM[0..7]<15,16>
DDR_A_DQS[0..7]<15,16>
DDR_A_DQS#[0..7]<15,16>
C C
B B
DDR_A_MA[0..13]<16,17>
DDR_B_MA[0..13]<15>
DDR_A_CAS#<16,17>
DDR_A_RAS#<16,17>
DDR_A_WE#<16,17>
DDR_B_BS0<15>
DDR_B_BS1<15>
DDR_B_BS2<15>
T4 PAD~D
T5 PAD~D
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7 DDR_A_D63
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AK12
AH11
AG17
AB30
AL31
AF30
AK26
AC28
AJ30
AK33
AL25
AM2
AC29
AK30
AJ33
AM25
AM3
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
AJ17
AK18
AN28
AM28
AH17
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
AG7
AK5
AH3
AN9
AH8
AE3
AN8
AE2
AL9
AJ8
U3C
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
DDR2 SYSTEM MEMORY
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#
Calistoga-GMS_FCBGA998~D
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
AG19
AG21
AG20
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
DDR_A_D[0..63] <15,16>
DDR_B_CAS# <15>
DDR_B_RAS# <15>
DDR_B_WE# <15>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistogo(2 of 5)
LA-3741P
11 53Friday, January 26, 2007
1
0.1
of
Page 12
5
D D
4
3
2
1
R116
24.9_0402_1%~D
1 2
C56 0.1U_0402_10V6K~D
C57 0.1U_0402_10V6K~D
C58 0.1U_0402_10V6K~D
C59 0.1U_0402_10V6K~D
C60 0.1U_0402_10V6K~D
C61 0.1U_0402_10V6K~D
C62 0.1U_0402_10V6K~D
C63 0.1U_0402_10V6K~D
12
AA26
H27
J27
Y26
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
D30
C30
A30
A29
G31
F32
D31
H31
G32
C31
F33
D33
F30
E33
D32
F29
U3F
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
EXP_A_COMPI
EXP_A_ICOMPO
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
MISC
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVO
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV
TV_IRTNB
LVDS VGA
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
Calistoga-GMS_FCBGA998~D
R28
M28
N30
R30
T29
M30
P30
T30
DVO_RED#_C
P28
DVO_GREEN#_C
N32
DVO_BLUE#_C
P32
DVO_CLK#_C
T32
DVO_RED_C
N28
DVO_GREEN_C
M32
DVO_BLUE_C
P33
DVO_CLK_C
R32
A21
C20
E20
G23
B21
C21
D21
G26
J26
+PEGCOMP
TVIREF
VGA_BLU<21,38>
VGA_GRN<21,38>
VGA_RED<21,38>
BIA_PWM<19,40>
ENVDD<19>
12
LCD_A0-<19>
LCD_A1-<19>
LCD_A2-<19>
LCD_A0+<19>
LCD_A1+<19>
LCD_A2+<19>
LCD_ACLK-
LCD_ACLK+
LCD_A1-
LCD_A1+
LCD_A0-
LCD_A0+
LCD_A2-
LCD_A2+
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLK_DDC2
G_DAT_DDC2
CRT_IREF
BIA_PWM
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDATA
L_IBG
LCD_ACLKLCD_ACLK+
LCD_A0LCD_A1LCD_A2-
LCD_A0+
LCD_A1+
LCD_A2+
C711
C712
C713
C714
2
1
1
2
1
2
1
2
SDVO_CTRLDATA<20>
SDVO_CTRLCLK<20>
CLK_MCH_3GPLL#<6>
CLK_MCH_3GPLL<6>
Close to U3.H25
C C
+3.3V_RUN
B B
A A
1 2
R580 2.2K_0402_5%~D
1 2
R581 2.2K_0402_5%~D
1 2
R123 10K_0402_5%~D
1 2
R124 10K_0402_5%~D
R126 150_0402_1%~D
R127 150_0402_1%~D
R128 150_0402_1%~D
12
12
12
LCD_DDCCLK
LCD_DDCDATA
LCTLA_CLK
LCTLB_DATA
VGA_RED
VGA_GRN
VGA_BLU
R117 255_0402_1%~D
VGA_VSYNC<21>
VGA_HSYNC<21>
12
PANEL_BKEN<19>
LCD_DDCCLK<19>
LCD_DDCDATA<19>
R118 1.5K_0402_1%~D
LCD_ACLK-<19>
LCD_ACLK+<19>
8.2P_0402_50V8J~D
3.3P_0402_50VJ~D
3.3P_0402_50VJ~D
3.3P_0402_50VJ~D
+1.5VRUN_PCIE
SDVOB_INT- <20>
SDVOB_INT+ <20>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
R119
R122
150_0402_1%~D
4.99K_0402_1%~D
Close to U3.G23
12
R120
SDVOB_RED- <20>
SDVOB_GREEN- <20>
SDVOB_BLUE- <20>
SDVOB_CLK- <20>
SDVOB_RED+ <20>
SDVOB_GREEN+ <20>
SDVOB_BLUE+ <20>
SDVOB_CLK+ <20>
TV_CVBS <38>
TV_Y <38>
TV_C <38>
12
R121
150_0402_1%~D
150_0402_1%~D
G_CLK_DDC2
G_DAT_DDC2
+3.3V_RUN
12
12
R129
2.2K_0402_5%~D
R130
+3.3V_RUN
2.2K_0402_5%~D
13
Q3
G
2N7002W-7-F_SOT323~D
2
G
2
13
D
S
Q4
2N7002W-7-F_SOT323~D
CLK_DDC2
DAT_DDC2
CLK_DDC2 <21,38>
DAT_DDC2 <21,38>
D
S
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(3 of 5)
LA-3741P
12 53Friday, January 26, 2007
1
0.1
of
Page 13
5
4
3
2
1
+1.05V_VCCP
D D
1
C65
10U_0805_6.3V6M~D
1
+
2
1
C66
2
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
1
1
C68
2
2
10U_0805_6.3V6M~D
1
C64
2
0.1U_0402_10V6K~D
C67
C C
C70
220U_D2_4M_R45~D
CRB 270uF
+1.05V_VCCP
1
+
C71
B B
A A
2
220U_D2_4M_R45~D
5
U3H
T25
VCC_NCTF1
R25
VCC_NCTF2
P25
VCC_NCTF3
N25
VCC_NCTF4
M25
VCC_NCTF5
P24
VCC_NCTF6
N24
VCC_NCTF7
M24
VCC_NCTF8
Y22
VCC_NCTF9
W22
VCC_NCTF10
V22
AB10
AA10
U22
R22
N22
M22
W21
U21
R21
N21
M21
W20
U20
R20
N20
M20
N19
M19
N18
M18
N17
M17
N16
M16
N15
M15
W14
U14
R14
N14
M14
R10
N10
M10
T22
P22
Y21
V21
T21
P21
Y20
V20
T20
P20
Y19
P19
Y18
P18
Y17
P17
Y16
P16
Y15
P15
Y14
V14
T14
P14
T10
P10
L10
D1
A18
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
Calistoga-GMS_FCBGA998~D
+1.5V_RUN
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
CFG19
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
4
CFG19 <10>
U3E
AH33
VSS_1
Y33
VSS_2
V33
VSS_3
R33
VSS_4
G33
VSS_5
AK32
VSS_6
AG32
VSS_7
AE32
VSS_8
AC32
VSS_9
AA32
VSS_10
U32
VSS_11
H32
VSS_12
E32
VSS_13
C32
VSS_14
AM31
VSS_15
AJ31
VSS_16
AA31
VSS_17
U31
VSS_18
T31
VSS_19
R31
VSS_20
P31
VSS_21
N31
VSS_22
M31
VSS_23
J31
VSS_24
F31
VSS_25
AL30
VSS_26
AG30
VSS_27
AE30
VSS_28
AC30
VSS_29
AA30
VSS_30
Y30
VSS_31
V30
VSS_32
U30
VSS_33
G30
VSS_34
E30
VSS_35
B30
VSS_36
AA29
VSS_37
U29
VSS_38
R29
VSS_39
P29
VSS_40
N29
VSS_41
M29
VSS_42
H29
VSS_43
E29
VSS_44
B29
VSS_45
AK28
VSS_46
AH28
VSS_47
AE28
VSS_48
AA28
VSS_49
U28
VSS_50
T28
VSS_51
J28
VSS_52
D28
VSS_53
AM27
VSS_54
AF27
VSS_55
AB27
VSS_56
AA27
VSS_57
Y27
VSS_58
U27
VSS_59
T27
VSS_60
R27
VSS_61
P27
VSS_62
N27
VSS_63
M27
VSS_64
G27
VSS_65
E27
VSS_66
C27
VSS_67
B27
VSS_68
AL26
VSS_69
AH26
VSS_70
W26
VSS_71
U26
VSS_72
AN25
VSS_73
AK25
VSS_74
AG25
VSS_75
AE25
VSS_76
J25
VSS_77
G25
VSS_78
A25
VSS_79
H23
VSS_80
F23
VSS_81
B23
VSS_82
AM22
VSS_83
AJ22
VSS_84
AF22
VSS_85
G22
VSS_86
E22
VSS_87
J21
VSS_88
H21
VSS_89
F21
VSS_90
AM20
VSS_91
AK20
VSS_92
AH20
VSS_93
AF20
VSS_94
D20
VSS_95
W19
VSS_96
R19
VSS_97
AM18
VSS_98
AH18
VSS_99
AF18
VSS_100
U18
VSS_101
H18
VSS_102
D18
VSS_103
AK17
VSS_104
V17
VSS_105
T17
VSS_106
F17
VSS_107
B17
VSS_108
AH16
VSS_109
U16
VSS_110
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
VSS
Calistoga-GMS_FCBGA998~D
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
2
U3G
W33
AM33
AL33
AN32
AN31
W28
W29
W32
AN19
AM19
AL19
AK19
AJ19
AH19
AM4
W31
AG4
AM1
NC1
NC2
NC3
C33
NC4
B33
NC5
NC6
A32
NC7
NC8
NC9
V27
NC10
NC11
J24
NC12
H24
NC13
NC14
G24
NC15
F24
NC16
E24
NC17
D24
NC18
K33
NC19
A31
NC20
E21
NC21
C23
NC22
NC23
NC24
NC25
NC26
NC27
NC28
AN3
NC29
Y9
NC30
J19
NC31
H19
NC32
G19
NC33
F19
NC34
E19
NC35
D19
NC36
C19
NC37
B19
NC38
A19
NC39
Y8
NC40
G16
NC41
F16
NC42
E16
NC43
D16
NC44
C16
NC45
B16
NC46
AN2
NC47
A16
NC48
Y7
NC49
NC50
AF4
NC51
AD4
NC52
AL4
NC53
AK4
NC54
NC55
AJ4
NC56
AH4
NC57
NC58
AE4
NC59
NC60
NC
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
Calistoga-GMS_FCBGA998~D
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(4 of 5)
LA-3741P
13 53Friday, January 26, 2007
1
0.1
of
Page 14
5
+1.05V_VCCP
D D
+1.5V_RUN
1
C89
2
C C
C631
0.47U_0402_16V4Z~D
C632
0.47U_0402_16V4Z~D
CRB 270uF
B B
C111
+1.05V_VCCP
A A
2
3
0.1U_0402_10V6K~D
+1.05V_VCCP
1 2
1 2
1
+
C123
2
220U_D2_4M_R45~D
1
1
C112
2
2
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
1
1
C120
C118
+2.5V_CRT
1
D2
MMBD4148W-7-F_SOT323~D
2
2
0.47U_0402_16V4Z~D
0.47U_0402_16V4Z~D
1 2
R134
10_0402_5%~D
U3_A14
U3_A7
U3_AA1
U3_F1
+2.5V_RUN
W18
W17
W16
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
R26
P26
N26
M26
V19
U19
T19
V18
T18
R18
U17
R17
V16
T16
R16
V15
U15
T15
H10
AE9
AD9
AD8
AD7
AD6
A14
D10
AA1
T26
J14
J10
U9
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
F1
U3D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
+1.5V_RUN
Calistoga-GMS_FCBGA998~D
2
3
CRT DAC Voltge Follower Circuit - 700mV TV DAC Volt g e Follower Circuit - 700mV
5
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
POWER
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS
VTT41
VTT42
VTT43
VTT44
VTT45
D1
MMBD4148W-7-F_SOT323~D
4
4
1
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
P1
L1
G1
U1
Y1
+3.3V_TV
+3VRUN_TVDACA
+3VRUN_TVDACB
+3VRUN_TVDACC
VSSA_TVBG
+1.5V_RUN
+1.5VRUN_QTVDAC
+1.5VRUN_MPLL
+1.5VRUN_HPLL
+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5V_RUN
+2.5V_RUN
+1.5VRUN_3GPLL
+2.5V_RUN
+2.5V_CRTDAC
+2.5V_RUN
+1.05V_VCCP
1 2
R133
10_0402_5%~D
+3VRUN_ATVBG
U3_AB33
U3_AM32
1
1
C94
U3_AN18
U3_AN4
U3_AH1
1
2
+3.3V_RUN
C93
C119
C95
1U_0402_6.3V4Z~D
C96
0.1U_0402_10V6K~D
2
2
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
1
C81
2
1
4.7U_0603_6.3V6M~D
2
1U_0402_6.3V4Z~D
Route +2.5VRUN from GMCH pinN33 to
decoupling cap (C66)<200mil to the edge.
C97
1
1U_0402_6.3V4Z~D
2
1
2
+1.5VRUN_3GPLL
1
C129
2
0.1U_0402_10V6K~D
Follow 945GMS desgin
guild to modify
1
2
C116
1
2
3
Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to t h e G ND plane.
Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to t h e G ND plane.
+3.3V_RUN
1
1
C79
C78
+1.8V_SUS
1
C82
2
4.7U_0603_6.3V6M~D
1
C117
2
0.022U_0402_16V7K~D
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to t h e g nd plane.
1 2
R132
0.5_0805_1%~D
C130
10U_0805_6.3V6M~D
2
2
0.1U_0402_10V6K~D
10U_0805_6.3V6M~D
+1.5VRUN_QTVDAC
1
C84
2
0.022U_0402_16V7K~D
+2.5V_RUN
1
C104
0.1U_0402_10V6K~D
2
1 2
L9
BLM18PG181SN1_0603~D
CRTDAC: Route FB
within 3" of Calistoga
0.1U_0402_10V6K~D
+3GPLL_R
BLM18PG181SN1_0603~D
+2.5V_RUN
180ohm,1500mA,0.09ohm
12
L11
180ohm,1500mA,0.09ohm
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.5V_RUN
1
C75
2
10U_0805_6.3V6M~D
L4
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
1
C85
2
0.1U_0402_10V6K~D
+2.5V_RUN
+3GPLL_L
1 2
R583
0_0805_5%~D
1
C76
2
0.1U_0402_10V6K~D
12
1
C115
2
+1.5V_RUN
+1.5V_RUN
1
+
C110
2
220U_D2_4M_R45~D
0.1U_0402_10V6K~D
1
close pin B31
C128
2
0.1U_0402_10V6K~D
2
+3VRUN_TVDACA
1 2
3
C72
0_0805_5%~D
+3VRUN_TVDACB
1 2
3
C77
0_0805_5%~D
+1.5V_RUN
C127
0.1U_0402_10V6K~D
1
2
+3VRUN_TVDACC
C105
@
330U_D2E_2.5VM_R9~D
1 2
C88
1
+
2
3
0_0805_5%~D
1
1
C86
2
0.022U_0402_16V7K~D
+1.5VRUN_HPLL +1.5VRUN_DPLLA
1
C99
2
0.1U_0402_10V6K~D
+1.5VRUN_PCIE
C113
10U_0805_6.3V6M~D
+2.5V_RUN
1
C124
2
0.1U_0402_10V6K~D
1
1
C114
2
2
10U_0805_6.3V6M~D
1
C125
2
BLM21PG600SN1D_0805~D
60ohm,3000mA,0.025ohm
0.01U_0402_16V7K~D
C87
2
0.1U_0402_10V6K~D
Close to U3.F20
45mA Max. 40mA Max.
L5
12
+1.5V_RUN
R582
0_0805_5%~D
1 2
+2.5V_RUN
1
C126
2
4.7U_0603_6.3V6M~D
+1.5V_RUN
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
1
C100
22U_0805_6.3V6M~D
2
+VCC3G_R
12
L8
close pin C29/D29
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
1
+3V_TVDAC
1
C73
2
0.1U_0402_10V6K~D
1
C80
2
0.1U_0402_10V6K~D
1
C91
2
0.1U_0402_10V6K~D
VSSA_TVBG
1
2
+1.5VRUN_MPLL
1
C108
2
0.1U_0402_10V6K~D
+1.5VRUN_DPLLB
1
2
+3VRUN_ATVBG
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
1
C74
2
10U_0805_6.3V6M~D
C65, C73, C83 replace by 0
ohm 0805 resistor
1 2
+3VRUN_ATV
1 2
3
C83
1
C90
@
2
+
C102
0.1U_0402_10V6K~D
4.7U_0603_6.3V6M~D
1
2
1
2
0_0805_5%~D
L6
C101
470U_D2_2.5VM~D
45mA Max.
L7
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
1
C109
22U_0805_6.3V6M~D
2
40mA Max.
L10
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
1
+
C121
C122
2
470U_D2_2.5VM~D
0.1U_0402_10V6K~D
Compal Electronics, Inc.
Calistoga(5 of 5)
LA-3741P
1
L3
R131
0_0603_5%~D
C92
0.1U_0402_10V6K~D
12
12
12
14 53Friday, January 26, 2007
12
+3.3V_RUN
+1.5V_RUN
+1.5V_RUN
of
+1.5V_RUN
0.1
Page 15
5
DDR_A_DQS#[0..7]<11,16>
DDR_A_D[0..63]<11,16>
DDR_A_DM[0..7]<11,16>
DDR_A_DQS[0..7]<11,16>
DDR_B_MA[0..13]<11>
D D
+1.8V_SUS
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C133
C134
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C138
1
2
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
B B
A A
C142
DDR_B_MA3
DDR_B_MA1
56_0404_4P2R_5%~D
DDR_B_MA10
DDR_B_BS0
56_0404_4P2R_5%~D
DDR_B_RAS#
DDR_CS2_DIMMA#
56_0404_4P2R_5%~D
DDR_B_WE#
DDR_B_CAS#
56_0404_4P2R_5%~D
DDR_CS3_DIMMA#
M_ODT3
56_0404_4P2R_5%~D
DDR_B_BS2
DDR_CKE2_DIMMA
56_0404_4P2R_5%~D
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
C143
1
2
2
C144
C145
RN1
1 4
2 3
RN3
1 4
2 3
RN5
1 4
2 3
RN7
1 4
2 3
RN9
1 4
2 3
RN12
2 3
1 4
5
2.2U_0603_6.3V6K~D
1
2
C139
1
2
0.1U_0402_16V4Z~D
1
2
C146
+0.9V_DDR_VTT
C135
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1
2
C140
1
2
0.1U_0402_16V4Z~D
1
2
C147
RN2
RN4
RN6
RN8
RN10
RN11
RN13
2.2U_0603_6.3V6K~D
C136
0.1U_0402_16V4Z~D
1
2
1
2
C148
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
Layout Note:
Place near JDIM1
C137
1
2
C141
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C150
C149
DDR_B_MA12
DDR_B_MA9
DDR_B_MA7
DDR_B_MA6
DDR_B_MA8
DDR_B_MA5
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
M_ODT2
DDR_B_MA13
DDR_CKE3_DIMMA
DDR_B_MA11
0.1U_0402_16V4Z~D
1
2
C151
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C152
C153
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
4
3
+1.8V_SUS +1.8V_SUS
ON Bottom SIDE
JDIMB
1
VREF
3
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
2.2U_0603_6.3V6K~D
C156
VSS
5
DQ0
7
DQ1
9
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
TYCO_1775803-2~D
DIMMA
STANDARD
DDR_A_D6
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D7
DDR_A_D3
DDR_A_D9
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D14
DDR_A_D17
DDR_A_D21
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D19
DDR_A_D23
DDR_A_D28
DDR_A_D24
DDR_A_DM3
DDR_A_D26 DDR_A_D30
DDR_A_D27
DDR_CKE2_DIMMA<10>
DDR_B_BS2<11>
DDR_B_BS0<11>
DDR_B_WE#<11>
DDR_B_CAS#<11>
DDR_CS3_DIMMA#<10>
M_ODT3<10>
0.1U_0402_16V4Z~D
1
2
C154
CLK_SDATA<6,17>
CLK_SCLK<6,17>
DDR_CKE2_DIMMA
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9 DDR_B_MA7
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMA#
M_ODT3
DDR_A_D32
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D35
DDR_A_D42
DDR_A_D40
DDR_A_DM5
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DM7
DDR_A_D62
DDR_A_D63
CLK_SDATA
CLK_SCLK
+3.3V_RUN
0.1U_0402_16V4Z~D
C155
1
1
2
2
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
1
V_DDR_MCH_REF
2
DDR_A_D0
4
DDR_A_D4
6
8
DDR_A_DM0
10
12
DDR_A_D1
14
DDR_A_D2
16
18
DDR_A_D12
20
DDR_A_D8
22
24
DDR_A_DM1
26
28
M_CLK_DDR3
30
M_CLK_DDR#3
32
34
DDR_A_D10
36
DDR_A_D11
38
40
42
DDR_A_D16
44
DDR_A_D20
46
48
50
NC
A7
A6
A4
A2
A0
NC
DDR_A_DM2
52
54
DDR_A_D22
56
DDR_A_D18
58
60
DDR_A_D25
62
DDR_A_D29
64
66
DDR_A_DQS#3
68
DDR_A_DQS3
70
72
74
DDR_A_D31
76
78
DDR_CKE3_DIMMA
80
82
84
86
88
DDR_B_MA11
90
92
DDR_B_MA6
94
96
DDR_B_MA4
98
DDR_B_MA2
100
DDR_B_MA0
102
104
DDR_B_BS1
106
DDR_B_RAS#
108
DDR_CS2_DIMMA#
110
112
M_ODT2
114
DDR_B_MA13
116
118
120
122
DDR_A_D33
124
DDR_A_D37
126
128
DDR_A_DM4
130
132
DDR_A_D39
134
DDR_A_D34
136
138
DDR_A_D45
140
DDR_A_D41
142
144
DDR_A_DQS#5
146
DDR_A_DQS5
148
150
DDR_A_D46DDR_A_D44
152
DDR_A_D47
154
156
DDR_A_D52
158
DDR_A_D53
160
162
M_CLK_DDR2
164
M_CLK_DDR#2
166
168
DDR_A_DM6
170
172
DDR_A_D50
174
DDR_A_D51
176
178
DDR_A_D56
180
DDR_A_D57
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D59
192
DDR_A_D58
194
196
R135 10K_0402_5%~D
198
200
1 2
R136 10K_0402_5%~D
1 2
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
R565 0_0402_5%~D
DDR_CKE3_DIMMA <10>
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMA# <10>
M_ODT2 <10>
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
2.2U_0603_6.3V6K~D
1
2
C131
PM_EXTTS#0
12
+3.3V_RUN
0.1U_0402_16V4Z~D
1
2
V_DDR_MCH_REF <10,16,17,49>
@
C132
R597100K_0402_5%~D
1 2
PM_EXTTS#0 <10>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA-3741P
15 53Friday, January 26, 2007
1
0.1
of
Page 16
5
DDR_A_D5
DDR_A_D6
DDR_A_D2
D D
DDR_A_D1
DDR_A_D4
DDR_A_D0
DDR_A_D3
DDR_A_D7
DDR_A_D8
DDR_A_D12
DDR_A_D14
DDR_A_D15
DDR_A_D13
DDR_A_D9
DDR_A_D11
DDR_A_D10
C C
DDR_A_D20
DDR_A_D16
DDR_A_D18
DDR_A_D22
DDR_A_D21
DDR_A_D17
DDR_A_D23
DDR_A_D19
DDR_A_D29
DDR_A_D25
DDR_A_D27
DDR_A_D26
B B
DDR_A_D24
DDR_A_D28
DDR_A_D31
DDR_A_D30
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1 DDR_SDQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
RN14
1 4
2 3
RN20
1 4
2 3
RN18
1 4
2 3
RN16
1 4
2 3
RN23
1 4
2 3
RN26
1 4
2 3
RN29
1 4
2 3
RN32
1 4
2 3
RN35
1 4
2 3
RN38
1 4
2 3
RN41
1 4
2 3
RN44
1 4
2 3
RN47
1 4
2 3
RN50
1 4
2 3
RN53
1 4
2 3
RN56
1 4
2 3
RN59
1 4
2 3
RN62
1 4
2 3
RN65
1 4
2 3
RN68
1 4
2 3
DDR_SDQ5
DDR_SDQ6
10_0404_4P2R_5%~D
DDR_SDQ2
DDR_SDQ1
10_0404_4P2R_5%~D
DDR_SDQ4
DDR_SDQ0
10_0404_4P2R_5%~D
DDR_SDQ3
DDR_SDQ7
10_0404_4P2R_5%~D
DDR_SDQ8
DDR_SDQ12
10_0404_4P2R_5%~D
DDR_SDQ14
DDR_SDQ15
10_0404_4P2R_5%~D
DDR_SDQ13
DDR_SDQ9
10_0404_4P2R_5%~D
DDR_SDQ11
DDR_SDQ10
10_0404_4P2R_5%~D
DDR_SDQ20
DDR_SDQ16
10_0404_4P2R_5%~D
DDR_SDQ18
DDR_SDQ22
10_0404_4P2R_5%~D
DDR_SDQ21
DDR_SDQ17
10_0404_4P2R_5%~D
DDR_SDQ23
DDR_SDQ19
10_0404_4P2R_5%~D
DDR_SDQ29
DDR_SDQ25
10_0404_4P2R_5%~D
DDR_SDQ27
DDR_SDQ26
10_0404_4P2R_5%~D
DDR_SDQ24
DDR_SDQ28
10_0404_4P2R_5%~D
DDR_SDQ31
DDR_SDQ30
10_0404_4P2R_5%~D
DDR_SDQS0
DDR_SDQS#0
10_0404_4P2R_5%~D
DDR_SDQS1
10_0404_4P2R_5%~D
DDR_SDQS2
DDR_SDQS#2
10_0404_4P2R_5%~D
DDR_SDQS3
DDR_SDQS#3
10_0404_4P2R_5%~D
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D38
DDR_A_D36
DDR_A_D32
DDR_A_D37
DDR_A_D33
DDR_A_D34
DDR_A_D39
DDR_A_D40
DDR_A_D42
DDR_A_D47
DDR_A_D46
DDR_A_D41
DDR_A_D45
DDR_A_D43
DDR_A_D44
DDR_A_D49
DDR_A_D48
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D57
DDR_A_D56
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D58
DDR_A_D59
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
RN15
1 4
2 3
RN17
1 4
2 3
RN19
1 4
2 3
RN21
1 4
2 3
RN24
1 4
2 3
RN33
1 4
2 3
RN30
1 4
2 3
RN27
1 4
2 3
RN36
1 4
2 3
RN39
1 4
2 3
RN42
1 4
2 3
RN45
1 4
2 3
RN48
1 4
2 3
RN51
1 4
2 3
RN54
1 4
2 3
RN57
1 4
2 3
RN60
1 4
2 3
RN63
1 4
2 3
RN66
1 4
2 3
RN69
1 4
2 3
DDR_SDQS#4
DDR_SDQS4
10_0404_4P2R_5%~D
DDR_SDQ35
DDR_SDQ38
10_0404_4P2R_5%~D
DDR_SDQ36
DDR_SDQ32
10_0404_4P2R_5%~D
DDR_SDQ37
DDR_SDQ33
10_0404_4P2R_5%~D
DDR_SDQ34
DDR_SDQ39
10_0404_4P2R_5%~D
DDR_SDQ40
DDR_SDQ42
10_0404_4P2R_5%~D
DDR_SDQ47
DDR_SDQ46
10_0404_4P2R_5%~D
DDR_SDQ41
DDR_SDQ45
10_0404_4P2R_5%~D
DDR_SDQ43
DDR_SDQ44
10_0404_4P2R_5%~D
DDR_SDQ49
DDR_SDQ48
10_0404_4P2R_5%~D
DDR_SDQ55
DDR_SDQ54
10_0404_4P2R_5%~D
DDR_SDQ53
DDR_SDQ52
10_0404_4P2R_5%~D
DDR_SDQ51
DDR_SDQ50
10_0404_4P2R_5%~D
DDR_SDQ57
DDR_SDQ56
10_0404_4P2R_5%~D
DDR_SDQ63
DDR_SDQ62
10_0404_4P2R_5%~D
DDR_SDQ61
DDR_SDQ60
10_0404_4P2R_5%~D
DDR_SDQ58
DDR_SDQ59
10_0404_4P2R_5%~D
DDR_SDQS5
DDR_SDQS#5
10_0404_4P2R_5%~D
DDR_SDQS6
DDR_SDQS#6
10_0404_4P2R_5%~D
DDR_SDQS7
DDR_SDQS#7
10_0404_4P2R_5%~D
4
DDR_A_DQS#[0..7]<11,15>
DDR_A_D[0..63]<11,15>
DDR_A_DM[0..7]<11,15>
DDR_A_DQS[0..7]<11,15>
DDR_A_MA[0..13]<11,17>
DDR_SDQS#[0..7]<17>
DDR_SDQS[0..7]<17>
DDR_SDQ[0..63]<17>
DDR_SDM[0..7]<17>
V_DDR_MCH_REF<10,15,17,49> M_CLK_DDR0 <10,17>
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
C157
0.1U_0402_16V4Z~D
C158
1
1
2
2
Place clost to each VREF pin
Layout Note:
Place near U4,U5,U6,U7
2.2U_0603_6.3V6K~D
C654
1
2
0.1U_0402_16V4Z~D
C659
1
2
2700P_0402_50V7K~D
C665
1
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C656
C655
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2700P_0402_50V7K~D
C661
C660
1
1
2
2
2700P_0402_50V7K~D
C666
C667
1
1
2
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C658
C657
1
1
2
2
0.1U_0402_16V4Z~D
C662
1
2
2700P_0402_50V7K~D
C668
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C663
1
1
2
2
2700P_0402_50V7K~D
2700P_0402_50V7K~D
C669
1
1
2
2
C159
C664
C670
3
DDR_SDQS0
DDR_SDQS#0
DDR_SDM0
DDR_SDQ0
DDR_SDQ1
DDR_SDQ4
DDR_SDQ2
DDR_SDQ3
DDR_SDQ5
DDR_SDQ7
DDR_SDQ6
V_DDR_MCH_REF
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C629
C160
1
1
2
2
2700P_0402_50V7K~D
2700P_0402_50V7K~D
C671
1
2
1
2
1
2
C672
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_SDQS4
DDR_SDQS#4
DDR_SDM4
DDR_SDQ33
DDR_SDQ35
DDR_SDQ37
DDR_SDQ38
DDR_SDQ34
DDR_SDQ32
DDR_SDQ39
DDR_SDQ36
V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
U4
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
U6
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
ODT
CKE
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
ODT
CKE
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
CK#
BA0
BA1
BA2
CS#
VSS
VSS
VSS
VSS
CK#
BA0
BA1
BA2
CS#
VSS
VSS
VSS
VSS
CK
NC
NC
NC
CK
NC
NC
NC
2
+1.8V_SUS +1.8V_SUS
E9
G1
G3
G7
G9
E1
J9
M9
R1
J1
M_ODT0
K9
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K2
DDR_A_BS0
L2
DDR_A_BS1 DDR_A_BS1
L3
DDR_A_BS2
L1
DDR_CS0#
L8
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
E7
F2
F8
H2
H8
E3
J3
N1
P9
J7
W8
W9
W1
+1.8V_SUS +1.8V_SUS+1.8V_SUS
E9
G1
G3
G7
G9
E1
J9
M9
R1
J1
M_ODT0
K9
M_CLK_DDR1
J8
M_CLK_DDR#1
K8
DDR_CKE0
K2
DDR_A_BS0
L2
DDR_A_BS1 DDR_A_BS1
L3
DDR_A_BS2 DDR_A_BS2
L1
DDR_CS0#
L8
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
E7
F2
F8
H2
H8
E3
J3
N1
P9
J7
W8
W9
W1
M_ODT0 <10,17>
M_CLK_DDR#0 <10,17>
DDR_CKE0 <10,17>
DDR_A_BS0 <11,17>
DDR_A_BS1 <11,17>
DDR_A_BS2 <11,17>
DDR_CS0# <10,17>
DDR_A_RAS# <11,17>
DDR_A_CAS# <11,17>
DDR_A_WE# <11,17>
M_CLK_DDR1 <10,17>
M_CLK_DDR#1 <10,17>
DDR_SDQS2
DDR_SDQS#2
DDR_SDM2
DDR_SDQ16
DDR_SDQ23
DDR_SDQ20
DDR_SDQ19
DDR_SDQ22
DDR_SDQ17
DDR_SDQ18
DDR_SDQ21
V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_SDQS6
DDR_SDQS#6
DDR_SDM6
DDR_SDQ52
DDR_SDQ51
DDR_SDQ53
DDR_SDQ50
DDR_SDQ55
DDR_SDQ48
DDR_SDQ54
DDR_SDQ49
V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
U5
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
U7
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
1
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
E1
VDD
J9
VDD
M9
VDD
R1
VDD
J1
VDDL
K9
ODT
J8
CK
K8
CK#
K2
CKE
L2
BA0
L3
BA1
L1
BA2
L8
CS#
K7
RAS#
L7
CAS#
K3
WE#
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
E3
VSS
J3
VSS
N1
VSS
P9
VSS
J7
VSSDL
W8
NC
W9
NC
W1
NC
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
E1
VDD
J9
VDD
M9
VDD
R1
VDD
J1
VDDL
K9
ODT
J8
CK
K8
CK#
K2
CKE
L2
BA0
L3
BA1
L1
BA2
L8
CS#
K7
RAS#
L7
CAS#
K3
WE#
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
E3
VSS
J3
VSS
N1
VSS
P9
VSS
J7
VSSDL
W8
NC
W9
NC
W1
NC
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS2
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0
DDR_A_BS0
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
A A
DDR_A_DM0 DDR_SDM0
DDR_A_DM1 DDR_SDM1
DDR_A_DM2 DDR_SDM2
DDR_A_DM3 DDR_SDM3
1 2
R566 10_0402_5%~D
1 2
R567 10_0402_5%~D
1 2
R568 10_0402_5%~D
1 2
R569 10_0402_5%~D
5
DDR_A_DM4 DDR_SDM4
DDR_A_DM5 DDR_SDM5
DDR_A_DM6 DDR_SDM6
DDR_A_DM7 DDR_SDM7
1 2
R570 10_0402_5%~D
1 2
R571 10_0402_5%~D
1 2
R572 10_0402_5%~D
1 2
R573 10_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-ON BOARD I
LA-3741P
16 53Friday, January 26, 2007
1
0.1
of
Page 17
5
Layout Note:
Place near U8,U9,U10,U11
+1.8V_SUS
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C162
1
2
0.1U_0402_16V4Z~D
C166
1
2
2700P_0402_50V7K~D
C675
1
2
0.1U_0402_16V4Z~D
1
2
C178
DDR_A_WE#
5
2.2U_0603_6.3V6K~D
1
2
0.1U_0402_16V4Z~D
C167
2700P_0402_50V7K~D
C676
0.1U_0402_16V4Z~D
1
2
C179
1 4
2 3
1 4
2 3
1 4
2 3
R625
56_0402_5%~D
1 4
2 3
R660
56_0402_5%~D
C163
1
2
1
2
0.1U_0402_16V4Z~D
RN70
RN72
RN74
RN78
2.2U_0603_6.3V6K~D
C161
D D
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
1
2
C175
B B
DDR_A_BS0<11,16>
DDR_A_BS1<11,16>
DDR_A_BS2<11,16>
A A
1
2
0.1U_0402_16V4Z~D
1
2
2700P_0402_50V7K~D
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C176
C177
DDR_A_MA1
DDR_A_MA8
56_0404_4P2R_5%~D
DDR_A_MA3
DDR_A_MA10
56_0404_4P2R_5%~D
DDR_CS0#<10,16>
DDR_A_WE#<11,16>
DDR_CS0#
M_ODT0
M_ODT0<10,16>
56_0404_4P2R_5%~D
DDR_A_BS0
DDR_A_BS1
56_0404_4P2R_5%~D
DDR_A_BS2 DDR_A_MA13
1
2
0.1U_0402_16V4Z~D
C168
2700P_0402_50V7K~D
C677
0.1U_0402_16V4Z~D
1
2
C180
+0.9V_DDR_VTT
12
12
2.2U_0603_6.3V6K~D
C164
C169
1
2
C678
1
2
1
2
C181
R661
56_0402_5%~D
C165
1
2
0.1U_0402_16V4Z~D
C673
1
2
2700P_0402_50V7K~D
C679
1
2
0.1U_0402_16V4Z~D
1
2
C182
RN71
RN73
RN75
RN77
RN79
1 2
RN81
0.1U_0402_16V4Z~D
C674
1
2
2700P_0402_50V7K~D
2700P_0402_50V7K~D
C680
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C184
C183
DDR_A_MA12
14
DDR_A_MA7
23
56_0404_4P2R_5%~D
DDR_A_MA6
14
DDR_CKE0
23
56_0404_4P2R_5%~D
DDR_A_MA4
14
DDR_A_MA2
23
56_0404_4P2R_5%~D
DDR_A_RAS#
14
DDR_A_MA11
23
56_0404_4P2R_5%~D
DDR_A_MA0
14
DDR_A_MA5
23
56_0404_4P2R_5%~D
DDR_A_CAS#
14
DDR_A_MA9
23
56_0404_4P2R_5%~D
1
2
0.1U_0402_16V4Z~D
2700P_0402_50V7K~D
C681
1
2
0.1U_0402_16V4Z~D
1
2
C185
+3.3V_RUN
CLK_SDATA<6,15>
R140 10K_0402_5%~D@
R141 10K_0402_5%~D@
DDR_CKE0 <10,16>
DDR_A_RAS# <11,16>
DDR_A_CAS# <11,16>
C682
1
2
C186
CLK_SCLK<6,15>
4
@
10K_0402_5%~D
4
12
12
R139
DDR_SDQS#[0..7]<16>
DDR_SDQS[0..7]<16>
DDR_SDQ[0..63]<16>
DDR_SDM[0..7]<16>
DDR_A_MA[0..13]<11,16>
V_DDR_MCH_REF<10,15,16,49>
12
CLK_SCLK
CLK_SDATA
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C171
C170
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C173
C172
1
2
1
1
2
2
Place clost to each VREF pin
3.3P_0402_50VJ~D
3.3P_0402_50VJ~D
U12
7
WP
6
SCL
5
SDA
1
SA0
2
SA1
SA23GND
24LC256T-I/ST_TSSOP8~D@
C174
C188
EEPROM
200_0402_5%~D
R137
1
2
200_0402_5%~D
R138
1
2
VDD
M_CLK_DDR0
200_0402_5%~D
12
12
R576
M_CLK_DDR#0
M_CLK_DDR1
200_0402_5%~D
12
12
R577
M_CLK_DDR#1
+3.3V_RUN
8
1
@
C189
0.1U_0402_16V4Z~D
2
4
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V4Z~D
C630
3
V_DDR_MCH_REF
1
2
V_DDR_MCH_REF
DDR_SDQS1
DDR_SDQS#1
DDR_SDM1
DDR_SDQ14
DDR_SDQ9
DDR_SDQ15
DDR_SDQ13
DDR_SDQ12
DDR_SDQ11
DDR_SDQ8
DDR_SDQ10
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_SDQS5
DDR_SDQS#5
DDR_SDM5
DDR_SDQ43
DDR_SDQ42
DDR_SDQ44
DDR_SDQ40
DDR_SDQ45
DDR_SDQ47
DDR_SDQ41
DDR_SDQ46
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
U8
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
U10
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
2
+1.8V_SUS
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
E1
VDD
J9
VDD
M9
VDD
R1
VDD
J1
VDDL
RAS#
CAS#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
RAS#
CAS#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
M_ODT0
K9
ODT
M_CLK_DDR0
J8
CK
M_CLK_DDR#0
K8
CK#
DDR_CKE0
K2
CKE
DDR_A_BS0
L2
BA0
DDR_A_BS1
L3
BA1
DDR_A_BS2
L1
BA2
DDR_CS0#
L8
CS#
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
WE#
E7
F2
F8
H2
H8
E3
VSS
J3
VSS
N1
VSS
P9
VSS
J7
W8
NC
W9
NC
W1
NC
+1.8V_SUS +1.8V_SUS
E9
G1
G3
G7
G9
E1
VDD
J9
VDD
M9
VDD
R1
VDD
J1
M_ODT0
K9
ODT
M_CLK_DDR1
J8
CK
M_CLK_DDR#1
K8
CK#
DDR_CKE0 DDR_CKE0
K2
CKE
DDR_A_BS0
L2
BA0
L3
BA1
L1
BA2
DDR_CS0#
L8
CS#
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
WE#
E7
F2
F8
H2
H8
E3
VSS
J3
VSS
N1
VSS
P9
VSS
J7
W8
NC
W9
NC
W1
NC
M_ODT0 <10,16>
M_CLK_DDR0 <10,16>
M_CLK_DDR#0 <10,16>
DDR_CKE0 <10,16>
DDR_A_BS0 <11,16>
DDR_A_BS1 <11,16>
DDR_A_BS2 <11,16>
DDR_CS0# <10,16>
DDR_A_RAS# <11,16>
DDR_A_CAS# <11,16>
DDR_A_WE# <11,16>
M_CLK_DDR1 <10,16>
M_CLK_DDR#1 <10,16>
2
DDR_SDQS3
DDR_SDQS#3
DDR_SDM3
DDR_SDQ27
DDR_SDQ25
DDR_SDQ26
DDR_SDQ29
DDR_SDQ28
DDR_SDQ31
DDR_SDQ24
DDR_SDQ30
V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_SDQS7
DDR_SDQS#7
DDR_SDM7
DDR_SDQ63
DDR_SDQ56
DDR_SDQ62
DDR_SDQ57
DDR_SDQ60
DDR_SDQ58
DDR_SDQ61
DDR_SDQ59
V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
Title
Size Document Number Rev
Date: Sheet
U9
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
U11
F7
DQS
E8
DQS#
F3
DM/RDQS
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
J2
VREF
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
R8
A13
E2
NU/RDQS
R3
NC
R7
NC
A1
NC
A2
NC
A8
NC
A9
NC
W2
NC
K4T1G084QA-ZCD5_FBGA68~D
Compal Electronics, Inc.
DDRII-ON BOARD II
LA-3741P
1
VSSDL
VSSDL
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
+1.8V_SUS
E9
G1
G3
G7
G9
E1
J9
M9
R1
J1
M_ODT0
K9
M_CLK_DDR0
J8
CK
M_CLK_DDR#0
K8
DDR_CKE0
K2
DDR_A_BS0
L2
DDR_A_BS1
L3
DDR_A_BS2
L1
DDR_CS0#
L8
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
E7
F2
F8
H2
H8
E3
J3
N1
P9
J7
W8
NC
W9
NC
W1
NC
E9
G1
G3
G7
G9
E1
J9
M9
R1
J1
M_ODT0
K9
M_CLK_DDR1
J8
CK
M_CLK_DDR#1
K8
K2
DDR_A_BS0
L2
DDR_A_BS1DDR_A_BS1
L3
DDR_A_BS2DDR_A_BS2
L1
DDR_CS0#
L8
DDR_A_RAS#
K7
DDR_A_CAS#
L7
DDR_A_WE#
K3
E7
F2
F8
H2
H8
E3
J3
N1
P9
J7
W8
NC
W9
NC
W1
NC
17 53Friday, January 26, 2007
0.1
of
Page 18
5
4
3
2
1
FAN1 Control and Tachometer
+3.3V_RUN
12
D D
R142
10K_0402_5%~D
FAN1_TACH <40>
1
C190
100P_0402_50V8J~D
@
2
+FAN1_VOUT
1
2 1
1
C194
2
+RTC_CELL
12
R152
147K_0402_1%~D
12
R157
68K_0402_1%~D
B
2
2200P_0402_50V7K~D
1
C192
C191
2
2
@
22U_0805_6.3V6M~D
1
C193
2
1
C196
0.1U_0402_16V4Z~D
2
1 2
R151 8.2K_0402_5%~D
1
2
C204
22U_0805_6.3V6M~D
1
2
SNIFFER_GREEN#<44>
SNIFFER_YELLOW#<44>
D3
RB751S40T1_SOD523-2~D
C C
+3.3V_SUS
12
R146
8.2K_0402_5%~D
2
B
+3.3V_SUS
2
B
C
E
3 1
12
C
E
3 1
THERMATRIP1#
1
Q5
C195
0.1U_0402_16V4Z~D
2
MMST3904-7-F_SOT323~D
R154
8.2K_0402_5%~D
THERMATRIP2#
1
Q7
C201
0.1U_0402_16V4Z~D
2
MMST3904-7-F_SOT323~D
0.1U_0402_16V4Z~D
C205
@
2200P_0402_50V7K~D
Place near the bottom SODIMM
+1.05V_VCCP
H_THERMTRIP#<7>
B B
+1.05V_VCCP
THERMTRIP_MCH#<10>
A A
R149
1 2
2.2K_0402_5%~D
R159
1 2
2.2K_0402_5%~D
5
@
Place C341 close to the Guardian
pins as possible
H_THERMDA<7>
2200P_0402_50V7K~D
H_THERMDC<7>
+3.3V_SUS
SET local temperature on M/B
VSET=(Tp-70)/21
=3.3V*R157/(R152+R157)
=1.044
Tp=92 degree
+3.3V_SUS
C199
REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil
1
2
R144
49.9_0603_1%~D
1 2
0.1U_0402_16V4Z~D
1
2
E
31
Q8 MMST3904-7-F_SOT323~D
C
4
FAN1_TACH
R145
+3.3V_SUS
+3VSUS_THRM
C200
2200P_0402_50V7K~D
1 2
SUSPWROK<24,43>
ICH_PWRGD#<43>
POWER_SW#<38,40,44>
R155
1 2
1K_0402_5%~D
REM_DIODE3_N
REM_DIODE3_P
Place cap close to the
Guardian pins as possible.
JFAN1
1
4
1
GND
2
5
2
GND
3
3
MOLEX_53780-0370~D
Use Rev:C
Need create P/N
U13
DAT_SMB<33,40>
CLK_SMB<33,40>
7.5K_0402_5%~D
1 2
R148 1K_0402_5%~D
1 2
R150 1K_0402_5%~D
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
+FAN1_VOUT
SNIFFER_GREEN#
SNIFFER_YELLOW#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
7
SMDATA
8
SMBCLK
23
LDO_SHDN#_ADDR
35
DP2
34
DN2
12
+3V_SUS
21
VSUS_PWRGD
18
+RTC_PWR3V
13
+3V_PWROK#
38
POWER_SW#
14
THERMTRIP1#
15
THERMTRIP2#
16
THERMTRIP3#
39
VSET
29
HW_LOCK#
9
VSS
1
DP3
2
DN3
6
FAN_OUT
33
FAN_DAC
10
GPIO1
11
GPIO2
19
GPIO3
20
GPIO4
32
GPIO5
EMC4000_QFN40~D
SMBUS ADDRESS : 2F
ATF_INT#
LDO_POK
THERMTRIP_SIO
ACAV_CLR
SYS_SHDN#
LDO_SET
LDO_OUT
LDO_OUT
VDD_5V
THERMAL PAD
1
C208
2
10U_0805_10V4Z~D
VCP
VCP
DN1
DP1
LDO_IN
LDO_IN
17
3
40
31
36
37
30
4
22
24
25
27
26
28
5
41
1
C209
0.1U_0402_16V4Z~D
2
+3.3V_RUN
12
R147
10K_0402_5%~D
REM_DIODE1_N
REM_DIODE1_P
LDO_SET
+3V_LDOIN
C202
10U_0805_6.3V6M~D
+5V_RUN
2
R143
10K_0402_5%~D
+3.3V_ALW
1
1
2
2
C206
12
+3.3V_SUS
ATF_INT# <40>
2.5V_RUN_PWRGD <43>
Place C197 clo se to the Guardian
pins as possible
12
R153
10K_0402_5%~D
C203
@
0.1U_0402_16V4Z~D
R160 0.27_1210_5%~D
1
1
0.1U_0402_16V4Z~D
2
2
1U_0603_10V4Z~D
1
C197
2
2200P_0402_50V7K~D
THERMTRIP_SIO <39>
ACAV_IN <40,51>
+2.5V_RUN
12
C207
@
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
B
2
Place under CPU
+3.3V_RUN
For Vmargin pop R578 and
R158=30K,R15 8 = 1 K for production.
Compal Electronics, Inc.
FAN & Thermal Sensor
LA-3741P
E
31
Q6
C
MMST3904-7-F_SOT323~D
R156
@
10K_0402_5%~D
31.6K_0402_1%~D
LDO_SET
1K_0603_5%~D
1
C198
@
2
2200P_0402_50V7K~D
12
+RTC_CELL
THERM_STP# <47>
+2.5V_RUN
12
R578
@
12
R158
1
18 53Friday, January 26, 2007
0.1
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Page 19
5
D D
JP1
31
MGND1
32
MGND2
33
MGND3
34
MGND4
C C
I-PEX_20143-030E-20F~D
B B
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LCD_ACLKLCD_ACLK+
LCD_A2LCD_A2+
LCD_A1LCD_A1+
LCD_A0LCD_A0+
LCD_DDCCLK
LCD_DDCDATA
LCD_TST
BIA_PWM
LAMP_D_STAT#
+GFX_PWR_SRC
1
2
D19
@
RB751S40T1_SOD523-2~D
C215
0.1U_0603_50V4Z~D
LCD_ACLK- <12>
LCD_ACLK+ <12>
LCD_A2- <12>
LCD_A2+ <12>
LCD_A1- <12>
LCD_A1+ <12>
LCD_A0- <12>
LCD_A0+ <12>
LCD_DDCCLK <12>
LCD_DDCDATA <12>
LCD_TST <24>
0.1U_0402_16V4Z~D
BIA_PWM <12,40>
SBAT_SMBCLK <40>
SBAT_SMBDAT <40>
21
FPBACK_EN<39>
PANEL_BKEN<12>
4
+3.3V_RUN
+LCDVDD
1
1
C213
C212
0.1U_0402_16V4Z~D
2
2
+5V_ALW
1
C214
0.1U_0402_16V4Z~D
2
LAMP_STAT#
M'07 inverter support - Depop D19.
D'05 inverter support - Populate D19
Ra
1 2
R166 0_0402_5%~D
12
R168
100K_0402_5%~D
LAMP_STAT# <24>
FPBACK_EN
PANEL_BKEN
M00 support D05 inverter
+3.3V_RUN
5
1
P
IN1
4
O
2
Ua
IN2
G
U14
@
3
SN74AHC1G08DCKR_SC70-5~D
3
+LCDVDD
12
R163
470_0402_5%~D
13
D
Q10
2
G
2N7002W-7-F_SOT323~D
S
ENVDD<12>
2
I
+PWR_SRC
40mil
1
C217
2
BIA_PWM
1000P_0402_50V7K~D
2
+15V_SUS
12
R162
100K_0402_5%~D
2
G
1
O
Q12
G
DDTC124EUA-7-F_SOT323~D
3
12
R165
200K_0402_5%~D
R167
1 2
100K_0402_5%~D
12
R161
100K_0402_5%~D
13
D
Q11
S
2N7002W-7-F_SOT323~D
Q13
FDS4435_NL_SO8~D
1
2
3
RUN_ON<40,42,43,47,48,49>
+LCDVDD
4
D
1 3
2
1
2
8
7
6
5
G
Q9
SI3456DV-T1-E3_TSOP6~D
S
4 5
G
3
C211
0.1U_0603_50V4Z~D
40mil
1
C216
0.1U_0603_50V4Z~D
2
Q14
2N7002W-7-F_SOT323~D
S
FDS4435: P CHANNAL
D
6
2
1
+GFX_PWR_SRC
1
+3.3V_RUN+15V_SUS
1
C210
2
0.1U_0402_16V4Z~D
M'07 inverter support - Populate Ra,U54 Depop Ua.
D'05 inverter support - Populate Ua, Depop Ra,U54
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Internal LVDS
LA-3741P
19 53Friday, January 26, 2007
1
0.1
of
Page 20
5
4
3
2
1
D D
+AVCC_TMDS+ 3 .3V_RUN
12
L12
C240
10U_0805_10V4Z~D
+AVCC_TMDS
1
C225
2
10U_0805_10V4Z~D
1
C241
0.1U_0402_16V4Z~D
2
SDVOB_INT+<12>
SDVOB_INT-<12>
SDVOB_RED+<12>
SDVOB_RED-<12>
SDVOB_GREEN+<12>
SDVOB_GREEN-<12>
SDVOB_BLUE+<12>
SDVOB_BLUE-<12>
SDVOB_CLK+<12>
SDVOB_CLK-<12>
1
C226
2
@
100P_0402_50V8J~D
+3.3V_RUN
R175 220_0402_5%~D
DVI_DETECT<38>
C227
@
1000P_0402_50V7K~D
1
C230
0.1U_0402_16V4Z~D
2
INT+
1 2
INT-
1 2
SDVOB_RED+
SDVOB_RED-
SDVOB_GREEN+
SDVOB_GREEN-
SDVOB_BLUE+
SDVOB_BLUE-
PLTRST#<10,22,24,29,36>
+VSWING
12
R178
1K_0402_5%~D
1
C228
2
0.1U_0402_16V4Z~D
1
C243
0.1U_0402_16V4Z~D
2
12
1
2
1
C242
0.1U_0402_16V4Z~D
2
C244 0.1U_0402_16V4Z~D
C249 0.1U_0402_16V4Z~D
2
C229
0.1U_0402_16V4Z~D
1
1
C231
10U_0805_10V4Z~D
2
U15
32
33
37
38
40
41
43
44
46
47
2
25
35
30
29
SDI+
SDI-
SDR+
SDR-
SDG+
SDG-
SDB+
SDB-
SDC+
SDC-
RESET#
EXT_SWING
EXT_RES
TEST
HTPLG
C C
+5V_RUN
12
R173
2.2K_0402_5%~D
+2.5V_RUN
12
R179
4.7K_0402_5%~D
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
R174
2.2K_0402_5%~D
R180
4.7K_0402_5%~D
+1.8V_RUN
B B
12
DVI_SCLK
DVI_SDATA
12
A A
SDVO_CTRLCLK
SDVO_CTRLDATA
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
L16
12
+VCC_TMDS
1
2
34
VCC10VCC
28
VCC
DVI_TX2-
DVI_TX2+
DVI_TX1-
DVI_TX1+
DVI_TX0-
DVI_TX0+
DVI_CLK-
DVI_CLK+
1
AVCC15AVCC21SVCC36SVCC
OVCC
PGND2
GND
GND31SGND39SGND
AGND18AGND
7
27
C218
12
0.1U_0402_16V4Z~D
C219
12
0.1U_0402_16V4Z~D
C220
12
0.1U_0402_16V4Z~D
C221
12
0.1U_0402_16V4Z~D
1
C222
0.1U_0402_16V4Z~D
2
1
2
42
48
26
11
TXC-
PVCC2
PVCC1
SPVCC
TXC+
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
SDADDC
SCLDDC
SDSCL
SDSDA
A1
SPGND
AGND
SII1362CLU_LQFP48~D
3
12
45
24
2
C223
0.1U_0402_16V4Z~D
1
1
1
C233
C232
2
2
@
10U_0805_10V4Z~D
1000P_0402_50V7K~D
DVI_CLKDVI_CLK+
DVI_TX0DVI_TX0+
DVI_TX1DVI_TX1+
DVI_TX2DVI_TX2+
@
1 2
13
14
16
17
19
20
22
23
9
8
5
4
6
1 2
110_0402_1%~D
1 2
110_0402_1%~D
1 2
110_0402_1%~D
1 2
110_0402_1%~D
+SVCC_TMDS
+SPVCC_TMDS
1
C235
C234
2
0.1U_0402_16V4Z~D
100P_0402_50V8J~D
DVI_SDATA <38>
DVI_SCLK <38>
SDVO_CTRLCLK <12>
SDVO_CTRLDATA <12>
1 2
R176 1K_0402_5%~D@
R177
1K_0402_5%~D
R169
R170
R171
R172
1
C224
10U_0805_10V4Z~D
2
L14
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
+PVCC1_TMDS
1
2
+PVCC2_TMDS
1
2
A1 LOW: Address = 0x70
DVI_TX2- <38>
DVI_TX2+ <38>
DVI_TX1- <38>
DVI_TX1+ <38>
DVI_TX0- <38>
DVI_TX0+ <38>
DVI_CLK- <38>
DVI_CLK+ <38>
L13
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
C236
10U_0805_10V4Z~D
C245
10U_0805_10V4Z~D
+3.3V_RUN
12
+1.8V_RUN
12
L15
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
1
1
C237
2
@
1
C246
2
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C238
2
1
C247
2
1
C239
0.1U_0402_16V4Z~D
2
1000P_0402_50V7K~D
L17
BLM18PG181SN1_0603~D
1
C248
2
1000P_0402_50V7K~D
HIGH: Address = 0x72
+3.3V_RUN
12
12
180ohm,1500mA,0.09ohm
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Internal LVDS
LA-3741P
20 53Friday, January 26, 2007
1
0.1
of
Page 21
5
D D
4
3
2
1
D5
D4
@
DA204U_SOT323~D
1
+3.3V_RUN
2
3
L18
22P_0402_50V8J~D
L21
BLM11A121S_0603~D
1 2
L22
BLM11A121S_0603~D
1 2
BLM18BB220SN1D_0603~D
1 2
L19
BLM18BB220SN1D_0603~D
1 2
L20
BLM18BB220SN1D_0603~D
1 2
+CRT_VCC
12
R184
@
C257
1K_0402_5%~D
22P_0402_50V8J~D
R185
@
1
C258
2
22ohm,500mA,0.1ohm
22ohm,500mA,0.1ohm
22ohm,500mA,0.1ohm
12
1K_0402_5%~D
1
2
22P_0402_50V8J~D
1
C253
@
10P_0402_50V8J~D
2
T12 PAD~D
R187
2.2K_0402_5%~D
R186
1 2
1 2
2.2K_0402_5%~D
VGA_RED<12,38>
VGA_GRN<12,38>
VGA_BLU<12,38>
C C
VGA_HSYNC<12>
B B
VGA_VSYNC<12>
VGA_RED
VGA_GRN
VGA_BLU
R189
1 2
39_0402_5%~D
R190
1 2
39_0402_5%~D
R181
150_0402_1%~D
DAT_DDC2<12,38>
CLK_DDC2<12,38>
12
R182
VGA_HSYNC_B
VGA_VSYNC_B
12
12
R183
150_0402_1%~D
150_0402_1%~D
+CRT_VCC
5
A2Y
3
SN74AHCT1G125GW_SOT-353~D
5
A2Y
3
1
C250
@
1
U16
P
4
OE#
G
1
U17
P
4
OE#
G
SN74AHCT1G125GW_SOT-353~D
2
22P_0402_50V8J~D
1 2
R650
0_0402_5%~D
1 2
R651
0_0402_5%~D
C251
@
1K_0402_5%~D
1 2
1
2
R188
@
22P_0402_50V8J~D
HSYNC_R <38>
VSYNC_R <38>
1
C252
2
120ohm,600mA,0.25ohm
120ohm,600mA,0.25ohm
1
2
1
C254
@
10P_0402_50V8J~D
2
0.1U_0402_16V4Z~D
@
DA204U_SOT323~D
3
1
2
C637
D6
@
DA204U_SOT323~D
1
2
3
C255
@
10P_0402_50V8J~D
1
2
+5V_RUN
21
D7
12
RB751S40T1_SOD523-2~D
R649
0_1206_5%~D
1
C256
2
0.01U_0402_16V7K~D
RED
DAT_DDC2
GREEN
JVGA_HS
BLUE
+CRT_VCC
JVGA_VS
M_ID2#
CLK_DDC2
+CRT_VCC
JCRT1
6
11
1
7
12
2
8
16
13
17
3
9
14
4
10
15
5
SUYIN_070546FR015S2307R~D
DA204U
K1 A2
A A
A1 K2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CRT Connector
LA-3741P
21 53Friday, January 26, 2007
1
0.1
of
Page 22
5
PCI_AD[0..31]<31,37>
D D
+3.3V_RUN
1 2
R191 8.2K_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R192 8.2K_0402_5%~D
R193 8.2K_0402_5%~D
R194 8.2K_0402_5%~D
R195 8.2K_0402_5%~D
R196 8.2K_0402_5%~D
R197 8.2K_0402_5%~D
R198 8.2K_0402_5%~D
+3.3V_RUN
C C
B B
R199 8.2K_0402_5%~D
R200 8.2K_0402_5%~D
R201 8.2K_0402_5%~D
R202 8.2K_0402_5%~D
R203 8.2K_0402_5%~D
R204 8.2K_0402_5%~D
R205 8.2K_0402_5%~D
R206 8.2K_0402_5%~D
R207 8.2K_0402_5%~D
R208 8.2K_0402_5%~D
R209 8.2K_0402_5%~D
R211 8.2K_0402_5%~D
R214 8.2K_0402_5%~D
R215 8.2K_0402_5%~D
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#<37>
PCI_PIRQB#<31>
PCI_PIRQC#<31>
PCI_PIRQD#<31>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
U19B
E18
AD0
C18
AD1
AG4
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
A3
B4
C5
B5
AE5
AD5
AH4
AD9
PCI
AD2
AD3
AD4
AD5
AD6
AD7
REQ4# / GPIO22
AD8
GNT4# / GPIO48
AD9
GPIO1 / REQ5#
AD10
GPIO17 / GNT5#
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
GPIO2 / PIRQE#
PIRQA#
GPIO3 / PIRQF#
PIRQB#
GPIO4 / PIRQG#
PIRQC#
GPIO5 / PIRQH#
PIRQD#
MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
82801GHM SL8YB B0_BGA652~D
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
PAR
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
B15
C12
D12
C15
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
C26
A9
B19
G8
F7
F8
G7
AE9
AG8
AH8
F21
AH20
3
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0# <38>
PCI_GNT0# <37,38>
PCI_REQ2# <31>
PCI_GNT2# <31>
PCI_C_BE0# <31,37>
PCI_C_BE1# <31,37>
PCI_C_BE2# <31,37>
PCI_C_BE3# <31,37>
PCI_IRDY# <31,37,38>
PCI_PAR <31,37>
PCI_DEVSEL# <31,37>
PCI_PERR# <31,37>
PCI_PLOCK# <37>
PCI_SERR# <31,37>
PCI_STOP# <31,37>
PCI_TRDY# <31,37>
PCI_FRAME# <31,37,38>
CLK_PCI_ICH <6>
ICH_PME# <39>
MCH_ICH_SYNC# <10>
PCI_PCIRST#
PCI_PLTRST#
2
+3.3V_SUS
14
U18A
1
P
IN1
3
OUT
2
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_SUS
14
U18B
4
P
5
10
9
13
12
IN1
OUT
IN2
G
7
+3.3V_SUS
14
P
IN1
OUT
IN2
G
7
+3.3V_SUS
14
P
IN1
OUT
IN2
G
7
PCI_RST#
6
74VHC08MTCX_NL_TSSOP14~D
U18C
PLTRST#
8
74VHC08MTCX_NL_TSSOP14~D
U18D
PLTRST2#
11
74VHC08MTCX_NL_TSSOP14~D
PCI_RST# <31,35,37>
PLTRST# <10,20,24,29,36>
PLTRST2# <39,40>
1
Place closely pin U45.A9
PCI_GNT5# PCI_GNT4#
12
R212
1K_0402_5%~D
GNT5#
R214
LPC
(11)
unstuffunstuff
12
R213
@
1K_0402_5%~D
GNT4#
R213
CLK_PCI_ICH
R210
@
10_0402_5%~D
C259
@
8.2P_0402_50V8J~D
1 2
1
2
PCI
(10)
SPI
(01)
A A
unstuff stuff
stuff
unstuff
*
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(1/4)
LA-3741P
22 53Friday, January 26, 2007
1
0.1
of
Page 23
5
4
3
2
1
+RTC_CELL
12
R216
1M_0402_5%~D
D D
C C
B B
SM_INTRUDER#
+3.3V_RUN
R229
8.2K_0402_5%~D
C260
12P_0402_50V8J~D
Package
9.6X4.06 mm
12P_0402_50V8J~D
ICH_AZ_CODEC_SDIN0<27>
IDE_IRQ
12
12
C261
12
+RTC_CELL
1
1U_0603_10V4Z~D
ICH_AZ_MDC_BITCLK<34>
ICH_AZ_MDC_SYNC<34>
ICH_AZ_MDC_RST#<34>
ICH_AZ_MDC_SDIN1<34>
ICH_AZ_MDC_SDOUT<34>
ICH_RTCX1
14
23
Y2
32.768K_12.5PF_Q13MC30610003~D
R643 0_0402_5%~D
CMOS1
@SHORT PADS~D
1
C262
1 2
ICH_RTCX2
12
1 2
R218
20K_0402_5%~D
2
2
C263 27P_0402_50V8J~D@
12
IDE_DIORDY<26>
IDE_IRQ<26>
IDE_DDACK#<26>
IDE_DIOW#<26>
IDE_DIOR#<26>
12
332K_0402_1%~D
1 2
1 2
1 2
R227
1 2
33_0402_5%~D
R217
10M_0402_5%~D
R219
1 2
ICH_RTCRST#
ICH_INTVRMEN
SM_INTRUDER#
ICH_AC_BITCLK_R
ICH_AC_SYNC_R
R22333_0402_5%~D
R22433_0402_5%~D
ICH_AC_RST_R#
R22533_0402_5%~D
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
ICH_AC_SDOUT_R
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
U19A
AB1
RTCX1
AB2
RTCX2
AA3
RTCRST#
W4
INTVRMEN
Y5
INTRUDER#
W1
EE_CS
Y1
EE_SHCLK
Y2
EE_DOUT
W3
EE_DIN
V3
LAN_CLK
U3
LAN_RSTSYNC
U5
LAN_RXD0
V4
LAN_RXD1
T5
LAN_RXD2
GPIO49 / CPUPWRGD
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
82801GHM SL8YB B0_BGA652~D
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AG16
AH16
AF16
AH15
AF15
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
RTC
LDRQ1# / GPIO23
LPCCPU
LFRAME#
LAN
A20GATE
CPUSLP#
TP1 / DPRSTP#
TP2 / DPSLP#
INIT3_3V#
STPCLK#
THERMTRIP#
SATA
IDE
AA6
LAD0
AB5
LAD1
AC4
LAD2
Y6
LAD3
AC3
LDRQ0#
AA5
AB3
AE22
AH28
A20M#
AG27
AF24
AH25
AG26
FERR#
AG24
AG22
IGNNE#
AG21
AF22
INIT#
AF25
INTR
AC-97/AZALIA
AG23
RCIN#
AF23
SMI#
AH24
NMI
AH22
AF26
AH17
DA0
AE17
DA1
AF17
DA2
AE16
DCS1#
AD16
DCS3#
AB15
DD0
AE14
DD1
AG13
DD2
AF13
DD3
AD14
DD4
AC13
DD5
AD12
DD6
AC12
DD7
AE12
DD8
AF12
DD9
AB13
DD10
AC14
DD11
AF14
DD12
AH13
DD13
AH14
DD14
AC15
DD15
AE15
DDREQ
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ0#
LPC_LDRQ1#
LPC_LFRAME#
H_CPUSLP_R#
DPRSLP#
H_FERR#
THRMTRIP_ICH#
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DSC1#
IDE_DSC3#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
LPC_LAD[0..3] <29,39,40>
LPC_LDRQ0# <39>
LPC_LDRQ1# <39>
LPC_LFRAME# <29,39,40>
R221 0_0402_5%~D@
R222 0_0402_5%~D
12
12
R226 56_0402_5%~D
1 2
IDE_DA[0..2] <26>
IDE_DSC1# <26>
IDE_DSC3# <26>
IDE_DD[0..15]
IDE_DDREQ <26>
IDE_DD[0..15] <26>
SIO_A20GATE
H_A20M#
H_CPUSLP#
H_DPRSTP#
H_DPSLP#
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
SIO_RCIN#
H_SMI#
H_NMI
H_STPCLK#
SIO_A20GATE <40>
H_A20M# <7>
H_CPUSLP# <7,10>
H_DPRSTP# <7,50>
H_DPSLP# <7>
H_FERR# <7>
H_PWRGOOD <7>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <40>
H_SMI# <7>
H_NMI <7>
H_STPCLK# <7>
+1.05V_VCCP
H_FERR#
SIO_A20GATE
SIO_RCIN#
R220 10K_0402_5%~D
R584 10K_0402_5%~D
+3.3V_RUN
12
12
DPRSTP# daisy
ICH7-M --> IMVP6 -->Yonah
+1.05V_VCCP
R228
56_0402_5%~D
12
Close to U19
R230
33_0402_5%~D
ICH_AC_SDOUT_R
ICH_AZ_CODEC_SDOUT<27>
ICH_AZ_CO D EC_SYNC<27>
ICH_AZ_CODEC_RST#<27>
A A
ICH_AZ_CODEC_BITCLK<27>
5
1 2
R231
33_0402_5%~D
1 2
R232
33_0402_5%~D
1 2
R233
33_0402_5%~D
1 2
1
C264
@
27P_0402_50V8J~D
2
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_BITCLK_R
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(2/4)
LA-3741P
23 53Friday, January 26, 2007
1
0.1
of
Page 24
5
+3.3V_SUS
+3.3V_RUN
1 2
R237 8.2K_0402_5%~D@
1 2
D D
+3.3V_SUS
C C
R242 10K_0402_5%~D
1 2
R244 8.2K_0402_5%~D
1 2
R245 10K_0402_5%~D
1 2
R247 10K_0402_5%~D
1 2
R254 10K_0402_5%~D
1 2
R249 10K_0402_5%~D
1 2
R250 10K_0402_5%~D
1 2
R251 8.2K_0402_5%~D
1 2
R253 680_0402_5%~D
1 2
R240 10K_0402_5%~D
1 2
R234 10K_0402_5%~D
1 2
R255 100K_0402_5%~D
SIO_THRM#
IRQ_SERIRQ
CLKRUN#
BT_RADIO_DIS#
WWAN_RADIO_DIS#
LAMP_STAT#
LINKALERT#
SMBALERT#
ICH_BATLOW#
ICH_PCIE_W AKE#
SIO_EXT_SMI#
SIO_EXT_SCI#
DPRSLPVR
R239
R238
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D
CLKRUN#<31,39,40>
(PCI Express Wake Event)
ICH_SMLINK1 ICH_SMLINK1
ICH_SMBCLK<6,29,36>
ICH_SMBDATA<6,29,36>
CLKRUN#
R370
10K_0402_5%~D
@
1 2
4
+3.3V_SUS
+3.3V_SUS
12
R235
2.2K_0402_5%~D
1 2
R246 8.2K_0402_5%~D
SPKR<27>
ITP_DBRESET#<7,40>
PM_BMBUSY#<10>
H_STP_PCI#<6>
H_STP_CPU#<6>
LCD_TST<19>
IDE_HRESET#<26>
BT_RADIO_DIS#<34>
ICH_PCIE_W AKE#<39>
IRQ_SERIRQ<29,31,39,40>
SIO_THRM#<40>
IMVP_PWRGD<43,50>
SIO_EXT_WAKE#<40>
LAMP_STAT#<19>
SIO_EXT_SMI#<40>
12
R236
2.2K_0402_5%~D
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0ICH_SMLINK0
ICH_RI#
SPKR
ITP_DBRESET#
PM_BMBUSY#
SMBALERT#
H_STP_PCI#
H_STP_CPU#
LCD_TST
IDE_HRESET#
BT_RADIO_DIS#
ICH_PCIE_W AKE#
IRQ_SERIRQ
SIO_THRM#
IMVP_PWRGD
SIO_EXT_WAKE#
LAMP_STAT#
SIO_EXT_SMI#
3
U19C
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
SMLINK1
A28
RI#
A19
SPKR
A27
SUS_STAT#
A22
SYS_RST#
AB18
GPIO0 / BM_BUSY#
B23
GPIO11 / SMBALERT#
AC20
GPIO18 / STPPCI#
AF21
GPIO20 / STPCPU#
A21
GPIO26
B21
GPIO27
E23
GPIO28
AG18
GPIO32 / CLKRUN#
AC19
GPIO33 / AZ_DOCK_EN#
U2
GPIO34 / AZ_DOCK_RST#
F20
WAKE#
AH21
SERIRQ
AF20
THRM#
AD22
VRMPWRGD
AC21
GPIO6
AC18
GPIO7
E21
GPIO8
GPIO21 / SATA0GP
SMB
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
SATA
GPIO
SYS
Clocks
GPIO
GPIO16 / DPRSLPVR
TP0 / BATLOW#
POWER MGT
GPIO
SATACLKREQ#/GPIO35
82801GHM SL8YB B0_BGA652~D
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
LAN_RST#
RSMRST#
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO38
GPIO39
AF19
AH18
AH19
AE19
CLK_ICH_14M
AC1
CLK_ICH_48M
B2
ICH_SUSCLK
C20
SIO_SLP_S3#
B24
D23
SIO_SLP_S5#
F22
ICH_PWRGD
AA4
DPRSLPVR
AC22
ICH_BATLOW#
C21
SIO_PWRBTN#
C23
PLTRST#
C19
SUSPWROK
Y4
1 2
R252 10K_0402_5%~D
SIO_EXT_SCI#
E20
A20
F19
E19
RSVD_HDDC_EN#
R4
E22
GPIO24
R3
D20
AD21
AD20
WWAN_RADIO_DIS#
AE20
2
R241
8.2K_0402_5%~D
1 2
+3.3V_RUN
CLK_ICH_14M <6>
CLK_ICH_48M <6>
SIO_SLP_S3# <40>
SIO_SLP_S5# <40>
ICH_PWRGD <10,43>
DPRSLPVR <50>
SIO_PWRBTN# <40>
PLTRST# <10,20,22,29,36>
SUSPWROK <18,43>
SIO_EXT_SCI# <40>
WWAN_RADIO_DIS# <36>
T6PAD~D
T17PAD~D
T7PAD~D
1 2
R248 10K_0402_5%~D
12
R574 0_0402_5%~D
1
Place closely pin U45.AC1
CLK_ICH_14M
12
R243
@
10_0402_5%~D
1
C265
@
4.7P_0402_50V8C~D
2
PM_EXTTS#1 <10>
close to ICH7-M
Mini Card 2--->
Mini Card 1--->
GIGA LAN--->
B B
A A
PCIE_IRX_WANTX_N1<36>
PCIE_IRX_WANTX_P1<36>
PCIE_ITX_WANRX_N1_C<36>
PCIE_ITX_WANRX_P1_C<36>
PCIE_IRX_WLANTX_N2<36>
PCIE_IRX_WLANTX_P2<36>
PCIE_ITX_WLANRX_N2_C<36>
PCIE_ITX_WLANRX_P2_C<36>
PCIE_IRX_LOMTX_N3<29>
PCIE_IRX_LOMTX_P3<29>
PCIE_ITX_LOMRX_N3_C<29>
PCIE_ITX_LOMRX_P3_C<29>
ICH_EC_SPI_CLK<40>
SPI_CS#<40>
ICHO_ECO_SPII_DATA<40>
ICHI_ECI_SPIO_DATA<40>
C266 0.1U_0402_10V6K~D
1 2
C267 0.1U_0402_10V6K~D
1 2
C268 0.1U_0402_10V6K~D
1 2
C269 0.1U_0402_10V6K~D
1 2
C270 0.1U_0402_10V6K~D
1 2
C271 0.1U_0402_10V6K~D
1 2
R266
ICH_EC_SPI_CLK
SPI_CS#
ICHI_ECI_SPIO_DATA
10K_0402_5%~D
R268
1 2
47_0402_5%~D
1 2
1 2
R269 47_0402_5%~D
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
PCIE_IRX_LOMTX_N3
PCIE_IRX_LOMTX_P3
PCIE_ITX_LOMRX_N3
PCIE_ITX_LOMRX_P3
+3.3V_SUS
R265
1 2
10K_0402_5%~D
R641 47_0402_5%~D
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
+3.3V_SUS+3.3V_SUS
12
R267
1 2
10K_0402_5%~D
ICH_SPI_CLK
ICHO_SPIIICHO_ECO_SPII_DATA
F26
F25
E28
E27
H26
H25
G28
G27
K26
K25
J28
J27
M26
M25
L28
L27
P26
P25
N28
N27
T25
T24
R28
R27
R2
P6
P1
P5
P2
D3
C4
D5
D4
E5
C3
A2
B3
U19D
PERn1
PERp1
PETn1
PETp1
PERn2
PERp2
PETn2
PETp2
PERn3
PERp3
PETn3
PETp3
PERn4
PERp4
PETn4
PETp4
PERn5
PERp5
PETn5
PETp5
PERn6
PERp6
PETn6
PETp6
SPI_CLK
SPI_CS#
SPI_ARB
SPI_MOSI
SPI_MISO
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31
82801GHM SL8YB B0_BGA652~D
PCI-EXPRESS
SPI
USB
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DIRECT MEDIA INTERFACE
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
D1
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USBP0-
USBP0+
USBP1USBP1+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBRBIAS
DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>
DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
R264 24.9_0402_1%~D
1 2
USBP0- <36>
USBP0+ <36>
USBP1- <39>
USBP1+ <39>
USBP4- <33>
USBP4+ <33>
USBP5- <33>
USBP5+ <33>
USBP6- <33>
USBP6+ <33>
USBP7- <38>
R271 22.6_0402_1%~D
USBP7+ <38>
1 2
Within 500 mils
Within 500 mils
+1.5V_RUN
<---Mini2 WLAN
<---SIO USB Hub
<---REAR
<---PWR USB
<---REAR
<---Docking
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC7#
USB_OC5#
USB_OC6#
USB_OC4#
1 2
R256 10K_0402_5%~D
1 2
R257 10K_0402_5%~D
1 2
R258 10K_0402_5%~D
1 2
R259 10K_0402_5%~D
1 2
R260 10K_0402_5%~D
1 2
R261 10K_0402_5%~D
1 2
R262 10K_0402_5%~D
1 2
R263 10K_0402_5%~D
Place closely pin U45.B2
USB_OC3#
USB_OC5# <33>
USB_OC6# <33>
USB_OC4# <33>
CLK_ICH_48M
12
R270
@
10_0402_5%~D
1
C272
@
4.7P_0402_50V8C~D
2
+3.3V_SUS
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(3/4)
LA-3741P
24 53Friday, January 26, 2007
1
0.1
of
Page 25
5
4
3
2
1
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
VccRTC
+1.05V_VCCP
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
U6
R7
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
P7
A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
AB17
AC17
T7
F17
G17
AB8
AC8
K7
C28
G20
A1
H6
H7
J6
J7
1
C273
2
1U_0603_10V4Z~D
1
C290
2
0.1U_0402_10V6K~D
1
C294
0.1U_0402_10V6K~D
2
1
2
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
1 2
C305
0.1U_0402_10V6K~D
1
C307
0.1U_0402_10V6K~D
2
1
2
1
2
C300
C274
+3.3V_SUS
C291
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
+1.5V_RUN
1
+
2
0.1U_0402_10V6K~D
CRB is 270uF
+1.05V_VCCP
+3.3V_RUN
1
C286
0.1U_0402_10V6K~D
2
1
C292
2
0.1U_0402_10V6K~D
+3.3V_SUS
1
C295
0.1U_0402_10V6K~D
2
+3.3V_SUS
1
C301
2
0.1U_0402_10V6K~D
C275
330U_V_6.3VM_R25M~D
C284
0.1U_0402_10V6K~D
1 2
1 2
C285
0.1U_0402_10V6K~D
1 2
C287
4.7U_0603_6.3V6M~D
+3.3V_RUN
U19E
A4
VSS[0]
A23
VSS[1]
B1
VSS[2]
B8
VSS[3]
B11
VSS[4]
B14
VSS[5]
B17
VSS[6]
B20
VSS[7]
B26
VSS[8]
B28
VSS[9]
C2
VSS[10]
C6
VSS[11]
C27
VSS[12]
D10
VSS[13]
D13
VSS[14]
D18
VSS[15]
D21
VSS[16]
D24
VSS[17]
E1
VSS[18]
E2
VSS[19]
E4
VSS[21]
+3.3V_RUN
1
C283
0.1U_0402_10V6K~D
2
C296
1
1
2
2
0.1U_0402_10V6K~D
+RTC_CELL
C297
0.1U_0402_10V6K~D
E8
VSS[22]
E15
VSS[23]
F3
VSS[24]
F4
VSS[25]
F5
VSS[26]
F12
VSS[27]
F27
VSS[28]
F28
VSS[29]
G1
VSS[30]
G2
VSS[31]
G5
VSS[32]
G6
VSS[33]
G9
VSS[34]
G14
VSS[35]
G18
VSS[36]
G21
VSS[37]
G24
VSS[38]
G25
VSS[39]
G26
VSS[40]
H3
VSS[41]
H4
VSS[42]
H5
VSS[43]
H24
VSS[44]
H27
VSS[45]
H28
VSS[46]
J1
VSS[47]
J2
VSS[48]
J5
VSS[49]
J24
VSS[50]
J25
VSS[51]
J26
VSS[52]
K24
VSS[53]
K27
VSS[54]
K28
VSS[55]
L13
VSS[56]
L15
VSS[57]
L24
VSS[58]
L25
VSS[59]
L26
VSS[60]
M3
VSS[61]
M4
VSS[62]
M5
VSS[63]
M12
VSS[64]
M13
VSS[65]
M14
VSS[66]
M15
VSS[67]
M16
VSS[68]
M17
VSS[69]
M24
VSS[70]
M27
VSS[71]
M28
VSS[72]
N1
VSS[73]
N2
VSS[74]
N5
VSS[75]
N6
VSS[76]
N11
VSS[77]
N12
VSS[78]
N13
VSS[79]
N14
VSS[80]
N15
VSS[81]
N16
VSS[82]
N17
VSS[83]
N18
VSS[84]
N24
VSS[85]
N25
VSS[86]
N26
VSS[87]
P3
VSS[88]
P4
VSS[89]
P12
VSS[90]
P13
VSS[91]
P14
VSS[92]
P15
VSS[93]
P16
VSS[94]
P17
VSS[95]
P24
VSS[96]
P27
VSS[97]
82801GHM SL8YB B0_BGA652~D
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
ICH_V5REF_RUN
+1.5V_RUN_L
D D
100_0402_5%~D
10_0402_5%~D
C C
B B
A A
R272
+5V_RUN
12
+5V_SUS
R273
+3.3V_RUN
12
+3.3V_SUS
21
D8
RB751S40T1_SOD523-2~D
ICH_V5REF_RUN
1
C282
0.1U_0402_10V6K~D
2
21
D9
RB751S40T1_SOD523-2~D
ICH_V5REF_SUS
1
C289
0.1U_0402_10V6K~D
2
+1.5V_RUN
1 2
R585
0.5_0805_1%~D
+1.5V_RUN
+DMIPLL_R
L23
1 2
BLM21PG600SN1D_0805~D
60ohm,3000mA,0.025ohm
+1.5V_DMIPLL
L24
BLM11A601S_0603~D
1 2
600ohm,100mA
C298
+3.3V_RUN
+3.3V_SUS
0.1U_0402_10V6K~D
C276
+3.3V_RUN
1
2
0.01U_0402_16V7K~D
C306
+1.5V_RUN_L
1
+
2
220U_D2_4M_R45~D
C293
1
C299
2
0.1U_0402_10V6K~D
10U_0805_6.3V6M~D
1
+1.5V_RUN
C303
2
1U_0603_10V4Z~D
0.1U_0402_10V6K~D
1
2
0.1U_0402_10V6K~D
+3.3V_SUS
0.1U_0402_10V6K~D
C277
1
2
+1.5V_RUN
+1.5V_RUN
ICH_V5REF_SUS
1
1
1
C278
0.1U_0402_10V6K~D
C304
C309
C302
C308
2
C279
0.1U_0402_10V6K~D
1
2
+1.5V_RUN
1
2
1
2
1
2
2
0.1U_0402_10V6K~D
+1.5V_DMIPLL
2
0.1U_0402_10V6K~D
U19F
G10
V5REF[1]
AD17
V5REF[2]
F6
V5REF_Sus
AA22
Vcc1_5_B[1]
AA23
Vcc1_5_B[2]
AB22
Vcc1_5_B[3]
AB23
Vcc1_5_B[4]
AC23
Vcc1_5_B[5]
AC24
Vcc1_5_B[6]
AC25
Vcc1_5_B[7]
AC26
Vcc1_5_B[8]
AD26
Vcc1_5_B[9]
AD27
Vcc1_5_B[10]
AD28
Vcc1_5_B[11]
D26
Vcc1_5_B[12]
D27
Vcc1_5_B[13]
D28
Vcc1_5_B[14]
E24
Vcc1_5_B[15]
E25
Vcc1_5_B[16]
E26
Vcc1_5_B[17]
F23
Vcc1_5_B[18]
F24
Vcc1_5_B[19]
G22
Vcc1_5_B[20]
G23
Vcc1_5_B[21]
H22
Vcc1_5_B[22]
H23
Vcc1_5_B[23]
J22
Vcc1_5_B[24]
J23
Vcc1_5_B[25]
K22
Vcc1_5_B[26]
K23
Vcc1_5_B[27]
L22
Vcc1_5_B[28]
L23
Vcc1_5_B[29]
M22
Vcc1_5_B[30]
M23
Vcc1_5_B[31]
N22
Vcc1_5_B[32]
N23
Vcc1_5_B[33]
P22
Vcc1_5_B[34]
P23
Vcc1_5_B[35]
R22
Vcc1_5_B[36]
R23
Vcc1_5_B[37]
R24
Vcc1_5_B[38]
R25
Vcc1_5_B[39]
R26
Vcc1_5_B[40]
T22
Vcc1_5_B[41]
T23
Vcc1_5_B[42]
T26
Vcc1_5_B[43]
T27
Vcc1_5_B[44]
T28
Vcc1_5_B[45]
U22
Vcc1_5_B[46]
U23
Vcc1_5_B[47]
V22
Vcc1_5_B[48]
V23
Vcc1_5_B[49]
W22
Vcc1_5_B[50]
W23
Vcc1_5_B[51]
Y22
Vcc1_5_B[52]
Y23
Vcc1_5_B[53]
B27
Vcc3_3[1]
AG28
VccDMIPLL
AB7
Vcc1_5_A[1]
AC6
Vcc1_5_A[2]
AC7
Vcc1_5_A[3]
AD6
Vcc1_5_A[4]
AE6
Vcc1_5_A[5]
AF5
Vcc1_5_A[6]
AF6
Vcc1_5_A[7]
AG5
Vcc1_5_A[8]
AH5
Vcc1_5_A[9]
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
Vcc1_5_A[10]
AB9
Vcc1_5_A[11]
AC10
Vcc1_5_A[12]
AD10
Vcc1_5_A[13]
AE10
Vcc1_5_A[14]
AF10
Vcc1_5_A[15]
AF9
Vcc1_5_A[16]
AG9
Vcc1_5_A[17]
AH9
Vcc1_5_A[18]
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
VccSus1_05/VccLAN1_05[1]
Y7
VccSus1_05/VccLAN1_05[2]
V5
VccSus3_3/VccLAN3_3[1]
V1
VccSus3_3/VccLAN3_3[2]
W2
VccSus3_3/VccLAN3_3[3]
W7
VccSus3_3/VccLAN3_3[4]
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
82801GHM SL8YB B0_BGA652~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(4/4)
LA-3741P
25 53Friday, January 26, 2007
1
0.1
of
Page 26
5
D D
IDE_DD[0..15]<23>
IDE_DA[0..2]<23>
+3.3V_RUN
R276 4.7K_0402_5%~D
+3.3V_HDD
C C
R278 510_0402_5%~D@
1 2
12
IDE_DIORDY
IDE_ACT#
4
HDD Connector
JHDD1
1
IDE_HRESET#<24>
IDE_DIOR#<23>
IDE_DIORDY<23>
IDE_DDACK#<23>
IDE_DSC1#<23>
IDE_ACT#<44>
IDE_HRESET#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_DA1
IDE_DA0
IDE_ACT#
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
GND
43
GND
FOX_QT510406-2101-7F~D
Need to modify of FPC ZIP connector
GND
GND
3
2
2
4
4
IDE_DD8
6
6
IDE_DD9
8
8
IDE_DD10
10
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
IDE_DD11
12
IDE_DD12
14
IDE_DD13
16
IDE_DD14
18
IDE_DD15
20
IDE_DDREQ
22
IDE_DIOW#
24
26
28
IDE_IRQ
30
PDIAG#
32
IDE_DA2
34
36
38
40
42
44
+3.3V_HDD
IDE_DDREQ <23>
IDE_DIOW# <23>
IDE_IRQ <23>
IDE_DSC3# <23>
1 2
R275
10K_0402_5%~D
+3.3V_HDD
2
+3.3V_HDD
0.1U_0402_16V4Z~D
1
C310
2
1000P_0402_50V7K~D
1
C311
2
Pleace near HD CONN
1
1
C312
2
1U_0603_10V4Z~D
1
C313
2
0.1U_0402_16V4Z~D
HDD PWR
B B
HDDC_EN#<39>
2N7002W-7-F_SOT323~D
12
HDD_EN_3.3V
13
D
2
G
S
@
Q16
+3.3V_HDD Source
A A
5
4
+3.3V_SUS+15V_SUS
R280
@
100K_0402_5%~D
1
C314
@
2
0.1U_0402_16V4Z~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
6
2
1
D
Q15
@
G
4 5
1
C315
2
10U_0805_10V4Z~D
3
SI3456DV-T1-E3_TSOP6~D
S
+3.3V_HDD
12
R281
100K_0402_5%~D
PJP1
1 2
PAD-OPEN 4x4m
+3.3V_RUN
3
DELL CONFIDENTIAL/PROPRIETARY
Title
IDE HDD Connector
Size Document Number Rev
2
Date: Sheet
LA-3741P
26 53Friday, January 26, 2007
1
0.1
of
Page 27
5
4
3
2
1
45
D D
+5V_SUS
C316
0.1U_0402_10V6K~D
U22
1
1
1
1
C317
C318
2
2
0.047U_0402_16V7K~D
AUDIO_AVDD_ON<39>
2
1U_0603_10V6K~D
AUDIO_AVDD_ON TPS793475_BYPASS
2
3
TPS793475DBVRG4_SOT23-5~D
IN
GND
EN
OUT
BYPASS
5
4
When L47 is popped, no pop U22.
+VDDA=4.75V
1
C324
2
0.1U_0402_10V6K~D
+VDDA
C320
2.2U_0603_6.3V6K~D
1
C321
2
@
BLM11A601S_0603~D
1
1
C322
2
2
0.1U_0402_10V6K~D
0.047U_0402_16V7K~D
W=30 mil
1
C C
ICH_AZ_CODEC_RST#<23>
+3.3V_RUN
R604 100K_0402_5%~D
DOCK_HP_MUTE#
12
ICH_AZ_CODEC_SDIN0<23>
ICH_AZ_CODEC_SYNC<23>
ICH_AZ_CODEC_SDOUT<23>
ICH_AZ_CODEC_BITCLK<23>
1 2
R284 33_0402_5%~D
+VREFOUT
Close to U24.3
ICH_AZ_CODEC_BITCLK
12
R285
@
22_0402_5%~D
1
C331
@
22P_0402_50V8J~D
B B
A A
2
Close to U24.5
ICH_AZ_CODEC_SDOUT
12
R289
47_0402_5%~D
@
1
C337
@
22P_0402_50V8J~D
2
Close to U24
ICH_AZ_CODEC_RST#
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_SDOUT
5
C338
@
10P_0402_50V8J~D
1 2
C339
@
10P_0402_50V8J~D
1 2
C342
@
10P_0402_50V8J~D
1 2
Close to U24.18
Close to U24.20
C340
C336
1U_0603_10V6K~D
HP_NB_SENSE<28,39>
AC97VREFI
1
2
1U_0603_10V6K~D
CAP2
1
1
C341
2
2
0.1U_0402_10V6K~D
4
HP_NB_SENSE
SPDIF_SHDN<39>
DOCK_HP_MUTE#<39>
EAPD<28>
SPDIF_DOCK<38>
1
C327
C326
2
0.1U_0402_10V6K~D
1U_0603_10V6K~D
ICH_AC_SDIN0_R
AC97VREFI
CAP2
R554 0_0402_5%~D@
SPDIF_SHDN
DOCK_HP_MUTE#
R591 0_0402_5%~D
C328
2
10U_0805_10V6K~D
12
12
Note: C336,C340,C341,C326,C327,C328,C619,C620 use
Temp. charact eristics: X5R
Operating range: -55~+85degree
+5V_RUN
1 2
L26
600ohm,100mA
SPKR<24>
BEEP<39>
+3.3V_RUN
+VDDA
W=20 mil
1
1
2
U24
8
RESET#
7
SYNC
2
SDATA_OUT
3
BIT_CLK
5
SDATA_IN
19
VREF_OUT
18
VREF_IN
20
CAP2
21
22
30
31
32
1
11
STAC9200
GPIO0
GPIO1
GPIO2
SPDIF _ IN/EAPD /GPIO3
SPDIF _OUT
NC1
NC2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
6
4
DVDD
DVSS
26
AVDD
AVSS117AVSS2
29
LINE_IN_L
LINE_IN_R
LOUT_L
LOUT_R
MONO_OUT
SENSE_A
STAC9200X5NAEB1XR_QFN32~D
1
C619
2
CD_L
CD_R
MIC1
MIC2
HP_L
HP_R
C620
2
10U_0805_10V6K~D
0.1U_0402_10V6K~D
15
16
10
12
INT_MIC <28>
This signal must be under 1V.
13
14
27
28
C332 0.1U_0402_10V6K~D
23
24
0.1U_0402_10V6K~D
25
SENSE_A
9
HP_NB_SENSE
2N7002W-7-F_SOT323~D
1 2
C333
1 2
Q17
NB_MICIN_L <28>
NB_MICIN_R <28>
HP_OUT_L <28>
HP_OUT_R <28>
12
R290
39.2K_0402_1%~D
13
D
2
G
S
1 2
R287 2.2K_0402_5%~D
1 2
R288 2.2K_0402_5%~D
+VDDA
1
5
1
P
A
2
B
G
3
1 2
C334 1000P_0402_50V7K~D
1 2
C335 1000P_0402_50V7K~D
1 2
C721 1000P_0402_50V7K~D
12
R291
13
D
G
Q18
S
2N7002W-7-F_SOT323~D
2
2
4
Y
U23
74AHCT1G86GW_SOT353~D
20K_0402_1%~D
2
2
single gate TTL
C323
0.1U_0402_10V6K~D
10K_0402_5%~D
1 2
STAC9200 Rev.
AUD_LINE_OUT <28>
MIC_SWITCH <28>
R282
2.2K_0402_5%~D
CA1
B1
Z2403 PC_BEEPZ2402
12
TRACE>15 mil
R283
SENSE_A
R286 5.1K_0402_1%~D
C325
0.1U_0402_10V6K~D
1 2
R22 R109
5.11K 10K
39.2K 20K
+VDDA
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Azalia (HD) Codec
LA-3741P
1
31
PC_BEEP <28>
27 53Friday, January 26, 2007
0.1
of
Page 28
5
1
3
U26
SHDNR#
SHDNL#
INR
INL
C1P
C1N
C357
PVss
5
PVSS
1
2
2
3
1
+3VRUN_4411
1
C344
1U_0603_10V6K~D
2
10
19
SVDD
PVDD
PGND
SVss
SGND
2
7
17
D21
@
DA204U_SOT323~D
+3.3V_RUN
12
R296
100K_0402_5%~D
D D
NB_MUTE
C350
1U_0603_10V6K~D
1U_0603_10V6K~D
INT_SPK_R1
INT_SPK_R2
1 2
1 2
C351
HP_OUT_R<27>
HP_OUT_L<27>
C C
2
G
1
C639
2
47P_0402_50V8J~D
HP_NB_SENSE
13
D
Q80
S
2N7002W-7-F_SOT323~D
AUD_LINE_IN_R
AUD_LINE_IN_L
1
1
C353
C640
2.2U_0603_10V6K~D
2
2
47P_0402_50V8J~D
+5V_SUS
2
3
@
DA204U_SOT323~D
1
14
18
15
13
C1P
C1N
2.2U_0603_10V6K~D
D20
15 mils trace
1
1
C361
B B
MIC1
1
2
WM-63PCY_2P~D
100P_0402_50V8J~D
A A
1
C652
@
2
2
3
1
INT_MIC+
INT_MIC-
D25
@
SM24_SOT23~D
2
C362
2
@
@
1000P_0402_50V7K~D
1000P_0402_50V7K~D
AUD_LINE_OUT<27>
+3.3V_RUN
2
NB_MUTE<39>
G
4
L27
BLM11A601S_0603~D
1 2
600ohm,100mA
HP_SPK_R1
11
OUTR
OUTL
NC-4
NC-6
NC-8
NC-12
NC-16
NC-20
MAX4411ETP+_TQFN20~D
Speaker Connector
4700P_0402_25V7K~D
1 2
13
D
S
HP_SPK_L1
9
4
6
8
12
16
20
JSPK1
1
1
2
2
3
GND
4
GND
MOLEX_53780-0270~D
PC_BEEP<27>
C368
12
R314
100K_0402_5%~D
EAPD<27>
Q21
2N7002W-7-F_SOT323~D
1
C370
2
47P_0402_50V8J~D
+3.3V_RUN
C352
2.2U_0603_6.3V6K~D
1 2
C358
2.2U_0603_6.3V6K~D
1 2
12
C621
47P_0402_50V8J~D
12
C367
4700P_0402_25V7K~D
13
D
2
G
Q79
@
S
2N7002W-7-F_SOT323~D
LM358DR2G_SOIC8~D
MIC_BIAS
+VDDA
INT_MIC+
INT_MIC-
12
C369
4700P_0402_25V7K~D
12
C371
4700P_0402_25V7K~D
SPK_SHUTDOWN#
U25A
1
O
12
R302
1K_0402_5%~D
12
R304
1K_0402_5%~D
C354
0.1U_0402_10V6K~D
1 2
1 2
C356
0.1U_0402_10V6K~D
12
R308
1K_0402_5%~D
12
R309
1K_0402_5%~D
2
1
RIN-
+VDDA
+VDDA
8
3
P
IN+
2
IN-
G
4
R305
10K_0402_5%~D
1 2
1 2
R306
10K_0402_5%~D
W=40mils
C363
1U_0603_10V6K~D
U27
7
RIN+
17
RIN-
9
LIN+
5
LIN-
19
SHUTDOWN
3
12
R294
100K_0402_5%~D
12
R298
100K_0402_5%~D
100K_0402_5%~D
1 2
+VDDA
5
IN+
6
IN-
1 2
100K_0402_5%~D
16
15
6
VDD
PVDD1
PVDD2
GND41GND311GND213GND1
GND_T
TPA6017A2PWP_TSSOP20~D
20
21
1
C347
2.2U_0603_6.3V6K~D
2
R303
C625
0.1U_0402_10V6K~D
U25B
8
LM358DR2G_SOIC8~D
P
7
O
G
4
R307
1 2
BLM21PG600SN1D_0805~D
60ohm,3000mA,0.025ohm
+5V_AMPVCC
2
GAIN0
3
GAIN1
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
12
NC
10
BYPASS
MIC_BIAS
12
C355
0.1U_0402_10V6K~D
L32
1
10U_0805_10V6K~D
2
AUD_GAIN0
AUD_GAIN1
INT_SPK_R1
INT_SPK_R2
BYPASS
12
INT_MIC <27>
C364
1
C372
0.47U_0402_16V4Z~D
2
NB_MICIN_L<27>
NB_MICIN_R<27>
+5V_SUS
MIC_SWITCH<27>
HP_SPK_L1
HP_SPK_R1
1
2
2
+VREFOUT
R295
4.99_0402_1%~D
R297
4.99_0402_1%~D
+3.3V_RUN
BLM18BD601SN1D_0603~D
BLM18BD601SN1D_0603~D
600ohm,200mA,0.65ohm
C365
0.1U_0402_10V6K~D
2.2U_0603_6.3V6K~D
MIC_L1
12
MIC_R1 MIC_R2
12
2.2U_0603_6.3V6K~D
12
R301
100K_0402_5%~D
L30
12
12
L31
+5V_AMPVCC
C345
1 2
C346
1 2
1
C359
2
100P_0402_50V8J~D
1
C366
0.1U_0402_10V6K~D
2
12
R292
4.7K_0402_5%~D
MIC_L2
12
R299
@
20K_0402_1%~D
C360
100P_0402_50V8J~D
C343
1 2
1000P_0402_50V7K~D
12
R293
600ohm,200mA,0.65ohm
4.7K_0402_5%~D
L28
BLM18BD601SN1D_0603~D
L29
BLM18BD601SN1D_0603~D
600ohm,200mA,0.65ohm
12
R300
@
20K_0402_1%~D
HP_SPK_L2
HP_SPK_R2
1
2
AUD_GAIN0
AUD_GAIN1
GAIN0 INPUTAV(inv)GAIN1
0
0
1
*
HP_NB_SENSE<27,39>
12
12
C348
100P_0402_50V8J~D
1
1
C349
2
2
100P_0402_50V8J~D
+5V_AMPVCC
12
12
0
1
0
11
1
Gain Setting
R310
1K_0402_5%~D
R312
@
1K_0402_5%~D
6dB
10dB
15.6dB
21.6dB
JP7
1
2
6
3
4
5
7
8
SUYIN_010030FR006G103ZL~D
JP8
1
2
6
3
4
5
7
8
SUYIN_010030FR006G103ZL~D
12
R311
@
1K_0402_5%~D
12
R313
1K_0402_5%~D
IMPEDANCE
90K ohm
70K ohm
45K ohm
25K ohm
DELL CONFIDENTIAL/PROPRIETARY
Note:
C343,C344,C345,C346,C350,C351,C353,C354,C355,C356,C357 use
Temp. characteristics: X5R
Operating range: -55~+85degree
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
AMP and PHONE JACK
LA-3741P
28 53Friday, January 26, 2007
1
0.1
of
Page 29
5
Layout Notice : Place as close
chip as possible.
+3.3V_SRC
D D
ENAB_3VLAN<42>
C C
LOM_TPM_EN#<39>
Support ASF2.0
LOM_SMB_ALERT#<40>
+3.3V_LAN
B B
A A
Q22
SI3456DV-T1-E3_TSOP6~D
D
6
S
45
2
1
LPC_LAD[0..3]<23,39,40>
LPC_LFRAME#<23,39,40>
PLTRST#<10,20,22,24,36>
IRQ_SERIRQ<24,31,39,40>
LOM_CABLE_DETECT<39>
@
4.7K_0402_5%~D
1 2
1 2
R331 4.7K_0402_5%~D@
2
C408
1
G
3
1
C726
4700P_0402_25V7K~D
2
1 2
R328 10K_0402_5%~D
1 2
R327 10K_0402_5%~D
1 2
R326 10K_0402_5%~D
1 2
R329 4.7K_0402_5%~D
@
CLK_PCI_LOM<6>
R324 0_0402_5%~D
R662 4.7K_0402_5%~D
+3.3V_LAN
ICH_SMBCLK<6,24,36>
ICH_SMBDATA<6,24,36>
R330
LINK_10#<30>
LINK_100#<30>
LAN_ACT#<30>
R334 330_0402_5%~D
25MHZ_18PF_1BX25000CK1D~D
X3
1 2
27P_0402_50V8J~D
Atmel AT45BCM021B
ST M45PE20
5
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2
TPM_EN#
CLK_PCI_LOM
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST#
IRQ_SERIRQ
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2
TPM_EN#
12
1 2
LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#
LINK_10#
LINK_100#
LAN_ACT#
XTALO
12
XTALI
2
C409
1
27P_0402_50V8J~D
2
2
2
C387
C386
1
1
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
U28A
J8
LCLK
J7
LAD0
L10
LAD1
J5
LAD2
K9
LAD3
J9
LFRAME
M10
LRESET
H7
SERIRQ
G4
TPM_GPIO0
J3
TPM_GPIO1
H3
TPM_GPIO2
J6
TPM_EN
H9
GPIO0
H11
GPIO1
C5
GPIO2
C4
GPIO3
C8
SMB_CLK
C7
SMB_DATA
C9
SCLK
E10
SI
D9
SO
C10
CS
M2
NV_STRAP0
M1
NV_STRAP1
A9
LINKLED
B9
SPD100LED
A10
SPD1000LED
B8
TRAFFICLED
M9
XTALO
L9
XTALI
BCM5752KFBG A2_FPBGA144~D
NV_STRAP1
0
000
2
C388
C389
C390
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
BCM5752
LPC/TPM
GPIO
SMBUS
SPI
LED
Clock
Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC
NV_STRAP0 SO SI CS# SCLK
00
1
1
1
2
1
Power
4
B
1C4
+3.3V_LAN
Rc, Rd are 1/2 W rating
B11
TRD3+
B12
TRD3-
C11
TRD2+
C12
TRD2-
D11
TRD1+
D12
TRD1-
E11
TRD0+
Media
E12
TRD0-
H4
LOW_PWR
A2
ATTN_BTTN
REGSUP12
REGCTL12
REGSEN12
REGCTL25
REGSEN25
PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP
WAKE
REFCLK-
REFCLK+
PERST
TCK
TDI
TDO
TMS
TRST
SERIAL_DI
SERIAL_DO
RDAC
11
1
4
G11
B6
K12
J11
J12
M11
M12
M3
L3
L7
M7
A4
L5
M5
B3
B1
B5
F3
B4
E3
D4
J1
M4
C6
A8
VMAINPRSNT
VAUXPRSNT
Control
Control
Regulator
PCI-ETEST
REFCLK_SEL
GPHY_TVCOI
Bias
MMJT9435
C
2
E
3
REGCTL_PNP12
1
C393
470P_0402_50V7K~D
2
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
REGCTL_PNP12
REGCTL_PNP25
PCIE_IRX_LOMTX_N3_C
PCIE_IRX_LOMTX_P3_C
PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM
PLTRST#
LAN_TX3+ <30>
LAN_TX3- <30>
LAN_TX2+ <30>
LAN_TX2- <30>
LAN_TX1+ <30>
LAN_TX1- <30>
LAN_TX0+ <30>
LAN_TX0- <30>
12
R603 0_0402_5%~D
R322 4.7K_0402_5%~D
R323 1K_0402_5%~D
R325 1K_0402_5%~D
1 2
R332 4.7K_0402_5%~D@
1 2
R338
1.18K_0402_1%~D
12
12
12
1 2
1 2
R333
@
4.7K_0402_5%~D
1 2
1 2
R335 4.7K_0402_5%~D@
1 2
R336 4.7K_0402_5%~D
1 2
R337 0_0402_5%~D@
+3.3V_LAN
0.1U_0402_16V4Z~D
C414
2
1
+3.3V_LAN
12
12
Rc Rd
R315
1
LOM_LOW_PWR
C4010.1U_0402_16V4Z~D
C4020.1U_0402_16V4Z~D
PCIE_WAKE# <36,39>
CLK_PCIE_LOM# <6>
CLK_PCIE_LOM <6>
PLTRST# <10,20,22,24,36>
+3.3V_LAN
R316
2_1210_5%~D
Q24
MMJT9435T1G_SOT223~D
2 3
4
+3.3V_LAN
+3.3V_RUN
+3.3V_LAN
+1.2V_LOM
+2.5V_LOM
PCIE_IRX_LOMTX_N3 <24>
PCIE_IRX_LOMTX_P3 <24>
PCIE_ITX_LOMRX_N3_C <24>
PCIE_ITX_LOMRX_P3_C <24>
U29
8
Q
7
VSS
6
VCC
5
W#
M45PE20-VMN6TP_SO8~D@
U30
8
SO
7
GND
6
VCC
5
WP#
AT45BCM021B-SU_SO8~D
3
+3.3V_LAN
0.1U_0402_16V4Z~D
2_1210_5%~D
1
C394
2
LOM_LOW_PWR <39>
RESET#
S#
SI
SCK
RESET#
CS#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
2
D
C
C384
0.1U_0402_16V4Z~D
C385
+1.2V_LOM
C395
1
2
3
4
1
2
3
4
3
4.7U_0603_6.3V6M~D
1
2
10U_0805_10V4Z~D
1
2
12
R620
4.7K_0402_5%~D @
LOM_SOLOM_SI
LOM_SCLK
LOM_CS#
R640
REGCTL_PNP25
Place closely pin J8
CLK_PCI_LOM
33_0402_5%~D
22P_0402_50V8J~D
2K_0402_5%~D
1 2
0.1U_0402_16V4Z~D
R321
@
C398
@
+2.5V_LOM
BLM11A601S_0603~D
600ohm,100mA
BLM11A601S_0603~D
600ohm,100mA
BLM11A601S_0603~D
600ohm,100mA
+3.3V_LAN
12
R339
4.7K_0402_5%~D
+3.3V_LAN
1
C710
2
+2.5V_LOM
12
1
2
L33
12
C399
0.1U_0402_16V4Z~D
L34
12
C400
0.1U_0402_16V4Z~D
L35
12
C403
0.1U_0402_16V4Z~D
+1.2V_LOM
BLM11A601S_0603~D
600ohm,100mA
4.7U_0603_6.3V6M~D
BLM11A601S_0603~D
600ohm,100mA
4.7U_0603_6.3V6M~D
BLM11A601S_0603~D
600ohm,100mA
4.7U_0603_6.3V6M~D
12
BLM11A601S_0603~D
R340
4.7U_0603_6.3V6M~D
4.7K_0402_5%~D
C396
1
0.1U_0402_16V4Z~D
1
2
1
2
1
2
1
2
L36
L37
L38
R341
2
Q23
MMJT9435T1G_SOT223~D
2 3
4
0.1U_0402_16V4Z~D
1
C397
2
+2.5V_XTALVDD
+1.2V_PCIE_SDS_VDD
+2.5V_BIASVDD
+2.5V_AVDD
+1.2V_PCIE_PLLVDD
+1.2V_GPHY_PLLVDD
12
1
C404
2
12
1
C406
2
12
1
C410
2
12
1
C412
@
2
2
0.1U_0402_16V4Z~D
1
C391
2
+1.2V_AVDDL
+2.5V_AVDD
1
2
1
2
1
2
1
2
4.7U_0603_6.3V6M~D
1
1
C375
C374
2
2
+2.5V_LOM
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1
C392
2
+1.2V_LOM
+3.3V_LAN
+2.5V_LOM
+2.5V_XTALVDD
+2.5V_BIASVDD
+1.2V_AVDDL
C405
0.1U_0402_16V4Z~D
+1.2V_GPHY_PLLVDD
C407
0.1U_0402_16V4Z~D
+1.2V_PCIE_PLLVDD
C411
0.1U_0402_16V4Z~D
+1.2V_PCIE_SDS_VDD
C413
@
0.1U_0402_16V4Z~D
1
Layout Notice : 1.2V filter. Place as close
chip as possible.
+1.2V_LOM
2
2
C376
1
0.1U_0402_16V4Z~D
U28B
D5
VDDC_0
D6
VDDC_1
D7
VDDC_2
D8
VDDC_3
H5
VDDC_4
H6
VDDC_5
H8
VDDC_6
J4
VDDC_7
Digial power
A3
VDDIO_0
C2
VDDIO_1
D10
VDDIO_2
F1
VDDIO_3
G10
VDDIO_4
J2
VDDIO_5
L1
VDDIO_6
L12
VDDIO_7
A5
VDDP_0
G3
VDDP_1
L11
VDDP_2
H12
XTALVDD
K4
PCIE_SDSVDD
A12
BIASVDD
F10
AVDDL_0
F11
AVDDL_1
A11
AVDD_0
F12
AVDD_1
K6
PCIE_PLLVDD
G12
GPHY_PLLVDD
Follow M07 schematic
Pop R341 to use BLM11A601S
If noise margi n on SDSVDD so that
pop C412,C413
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
2
C377
C378
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
BCM5752
BIAS
Analog
power
PLL
BCM5752KFBG A2_FPBGA144~D
LOM_CLKREQ#<6>
LOM_LOW_PWR
12
R599
@
20K_0402_5%~D
BCM5752_K5
12
R600
@
39K_0402_5%~D
Follow Travis to add that
Broadcom wil l be update for
next version.
BCM5751M
2
C380
C379
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
GND
R601 0_0402_5%~D@
LA-3741P
2
1
C381
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
1
2
2
C383
C382
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6
A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
E2
F2
G1
G2
G9
H1
H2
H10
J10
K1
K2
K3
BCM5752_K5
K5
K7
K8
K10
K11
L4
L8
M8
12
29 53Friday, January 26, 2007
2
1
0.1
of
Page 30
5
4
3
2
1
LAN ANALOG
SWITCH
48
0B1
VDD04VDD110VDD218VDD327VDD438VDD550VDD6
47
1B1
43
2B1
42
3B1
37
4B1
36
5B1
32
6B1
31
7B1
22
0LED1
23
1LED1
52
2LED1
46
0B2
45
1B2
41
2B2
40
3B2
35
4B2
34
5B2
30
6B2
29
7B2
25
0LED2
26
1LED2
51
2LED2
PI3L500E_TQFN56~D
55
LAN_ACT#
LINK_10#
LINK_100#
LAN_LEDACT# LAN_ACTLED_YEL_R#
LINK_LED10#
LINK_LED100#
JPHON1
1
1
2
2
3
GND1
4
GND2
FOX_JM74613-P2002-7F~D
SW_LAN_TX0SW_LAN_TX0+
SW_LAN_TX1SW_LAN_TX1+
SW_LAN_TX2SW_LAN_TX2+
SW_LAN_TX3SW_LAN_TX3+
LAN_LEDACT#
LINK_LED10#
LINK_LED100#
DOCK_LAN_TX0DOCK_LAN_TX0+
DOCK_LAN_TX1DOCK_LAN_TX1+
DOCK_LAN_TX2DOCK_LAN_TX2+
DOCK_LAN_TX3DOCK_LAN_TX3+
DOCK_LAN_ACTLED_YEL#
DOCK_LED_10#
DOCK_LED_100#
12
12
R352
R351
@
@
10K_0402_5%~D
1 2
R354 150_0402_5%~D
1 2
R355 150_0402_5%~D
1 2
R356 150_0402_5%~D
+3.3V_LAN
R353
@
10K_0402_5%~D
12
10K_0402_5%~D
LED_10_GRN_R#
LED_100_ORG_R#
DOCK_LAN_TX0- <38>
DOCK_LAN_TX0+ <38>
DOCK_LAN_TX1- <38>
DOCK_LAN_TX1+ <38>
DOCK_LAN_TX2- <38>
DOCK_LAN_TX2+ <38>
DOCK_LAN_TX3- <38>
DOCK_LAN_TX3+ <38>
DOCK_LAN_ACTLED_YEL# <38>
DOCK_LED_10# <38>
DOCK_LED_100# <38>
TO
DOCK
1 2
LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+
LAN_TX0-<29>
LAN_TX0+<29>
LAN_TX1-<29>
LAN_TX1+<29>
LAN_TX2-<29>
LAN_TX2+<29>
LAN_TX3-<29>
LAN_TX3+<29>
Layout Notice : Place bead as
close PI3L500 as possible
LAN_TX0-
1 2
L39 39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX0+
1 2
L40 39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+ LAN_TX3+R
DOCKED
DOCKED<38,39>
1 2
L41 39NH_ 0603CS-390EJTS_5%_2P~D
1 2
L42 39NH_ 0603CS-390EJTS_5%_2P~D
1 2
L43 39NH_ 0603CS-390EJTS_5%_2P~D
1 2
L44 39NH_ 0603CS-390EJTS_5%_2P~D
1 2
L45 39NH_ 0603CS-390EJTS_5%_2P~D
1 2
L46 39NH_ 0603CS-390EJTS_5%_2P~D
LAN_ACT#<29>
LINK_10#<29>
LINK_100#<29>
FROM NIC DOCKED
LAN_ACTLED_YEL_R#
LED_10_GRN_R#
LED_100_ORG_R#
NB_LAN_TX0+
NB_LAN_TX0NB_LAN_TX1+
NB_LAN_TX2+
NB_LAN_TX2NB_LAN_TX1NB_LAN_TX3+
NB_LAN_TX3-
12
12
12
12
R359 75_0402_1%~D
R358 75_0402_1%~D
R360 75_0402_1%~D
R357 75_0402_1%~D
RJ_TIP_L<38>
JP9
1
1
2
2
3
GND
4
GND
MOLEX_53780-0270~D
RJ_RING_L<38>
L47
RJ_TIP_L
FBMA-L11-160808-301LMA20T_2P~D
FBMA-L11-160808-301LMA20T_2P~D
L48
LAN_TX0-R
LAN_TX0+R
LAN_TX1-R
LAN_TX1+R
LAN_TX2-R
LAN_TX2+R
LAN_TX3-R
1: TO DOCK
0: TO RJ45
JP2
1
PR1+
2
PR1-
3
PR2+
4
PR3+
5
PR3-
6
PR2-
7
PR4+
8
PR4-
12
12
@
+3.3V_LAN
9
C641
300P_1808_3000V8K~D
LDE_ORANGE-
2
1
2
3
7
8
11
12
14
15
17
19
20
54
5
+3.3V_LAN
10
LDE_GREEN-
C642
@
300P_1808_3000V8K~D
56
U31
A0
A1
A2
A3
A4
A5
A6
A7
SEL
LED0
LED1
LED2
NC
GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13
GND P
57
12
13
11
14
A2
NC
LED_YELLOW-
LED_YELLOW+
SHLD1
SHLD2
FOX_JM36113-P2651-7F~D
15
16
RJ_TIP
RJ_RINGRJ_RING_L
2
1
C415 0.1U_0402_16V4Z~D
1 2
C416 0.1U_0402_16V4Z~D
1 2
C417 0.1U_0402_16V4Z~D
1 2
C418 0.1U_0402_16V4Z~D
1 2
D D
+2.5V_LOM
C C
B B
A A
12
L66
BLM11A601S_0603~D
TRM_CT
SW_LAN_TX0-
1
C419
0.1U_0402_10V6K~D
2
SW_LAN_TX0+
SW_LAN_TX1-
1
C420
0.1U_0402_10V6K~D
2
SW_LAN_TX1+
SW_LAN_TX2-
1
C421
0.1U_0402_10V6K~D
2
SW_LAN_TX2+
SW_LAN_TX3- NB_LAN_TX3-
1
C422
0.1U_0402_10V6K~D
2
SW_LAN_TX3+
TR8
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD21+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
H5015NLT_24P~D
1:1
1:1
1:1
1:1
R342 48.7_0402_1%~D
1 2
R343 48.7_0402_1%~D
1 2
R344 48.7_0402_1%~D
1 2
1 2
1 2
1 2
1 2
1 2
MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-
Layout Notice : Place
terminatio n a s close as
ASIC as possible
The resistors need at
least 1/16W
Z2805
24
NB_LAN_TX0-
23
NB_LAN_TX0+
22
Z2806
21
NB_LAN_TX1-
20
NB_LAN_TX1+
19
Z2807
18
NB_LAN_TX2-
17
NB_LAN_TX2+
16
Z2808
15
14
NB_LAN_TX3+
13
C423 1000P_1808_3KV7K~D
R345 48.7_0402_1%~D
R346 48.7_0402_1%~D
R347 48.7_0402_1%~D
R348 48.7_0402_1%~D
R349 48.7_0402_1%~D
GND
CHASIS
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
LAN TRANSFOMER
LA-3741P
1
30 53Friday, January 26, 2007
of
0.1
Page 31
5
W11
W12
R376
R380
C437
U32A
M2
AD31
M1
AD30
N5
AD29
N4
AD28
N2
AD27
N1
AD26
P5
AD25
P4
AD24
R4
AD23
R2
AD22
R1
AD21
T2
AD20
T1
AD19
U2
AD18
U1
AD17
V1
AD16
T7
AD15
V7
AD14
W7
AD13
R8
AD12
T8
AD11
V8
AD10
W8
AD9
R9
AD8
V9
AD7
W9
AD6
T11
AD5
V11
AD4
AD3
T12
AD2
V12
AD1
AD0
P2
C/BE3#
W2
C/BE2#
W6
C/BE1#
T9
C/BE0#
V6
PAR
V3
FRAME#
W4
TRDY#
V4
IRDY#
V5
STOP#
T5
DEVSEL#
P1
IDSEL
W5
PERR#
T6
SERR#
M4
REQ#
M5
GNT#
K1
PCICLK
L4
PCIRST#
G2
GBRST#
L5
CLKRUN#
J2
INTA#
K4
INTB#
K2
INTC#
J4
UDIO0/SERIRQ#
H1
UDIO1
H2
UDIO2
H4
UDIO3
H5
UDIO4
G1
UDIO5
G4
RI_OUT#/PME#
F1
SPKROUT
F2
HWSPND#
F4
TEST
56.2_0402_1%~D
12
56.2_0402_1%~D
12
Z3008
270P_0402_50V7K~D
2
1
R377
R381
R385
56.2_0402_1%~D
12
56.2_0402_1%~D
12
5.1K_0402_1%~D
1 2
PCI_AD[0..31]<22,37>
D D
PCI_C_BE3#<22,37>
PCI_C_BE2#<22,37>
PCI_C_BE1#<22,37>
PCI_C_BE0#<22,37>
PCI_PAR<22,37>
PCI_FRAME#<22,37,38>
C C
PCI_AD17 CBS_IDSEL
CLKRUN#<24,39,40>
+3.3V_R5C843
B B
A A
+3.3V_R5C843
+3.3V_R5C843
CLK_PCI_PCCARD
@
10_0402_5%~D
12
R378
@
4.7P_0402_50V8C~D
CK33M_CBS_TERM
C436
2
1
SYS_PME#<37,39>
CB_HWSPND#<39>
PCI_TRDY#<22,37>
PCI_IRDY#<22,37,38>
PCI_STOP#<22,37>
PCI_DEVSEL#<22,37>
1 2
PCI_PERR#<22,37>
PCI_SERR#<22,37>
PCI_REQ2#<22>
PCI_GNT2#<22>
CLK_PCI_PCCARD<6>
PCI_RST#<22,35,37>
CBUS_GRST#<39>
R367 0_0402_5%~D
1 2
PCI_PIRQD#<22>
PCI_PIRQB#<22>
PCI_PIRQC#<22>
R371 10K_0402_5%~D
1 2
R372 10K_0402_5%~D
1 2
R373 10K_0402_5%~D
1 2
R593 0_0402_5%~D@
R595 0_0402_5%~D@
R374 100K_0402_5%~D
1 2
+3.3V_R5C843
100K_0402_5%~D
12
R379
CBUS_GRST#
1U_0603_10V4Z~D
1
C435
2
5
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
R362100_0402_5%~D
PCI_PERR#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#
CLK_PCI_PCCARD
PCI_RST#
CBUS_GRST#
IRQ_SERIRQ<24,29,39,40>
12
CBS_SPK
12
IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
4
CAD31/CDATA10
CAD30/CDATA9
CAD29/CDATA1
R5C843
CSTSCHG/BVD1(STSCHG#/RI#)
C433
CAD28/CDATA8
CAD27/CDATA0
CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6
CAD19/CADR25
CAD18/CADR7
CAD17/CADR24
CAD16/CADR17
CAD15/IOWR#
CAD14/CADR9
CAD13/IORD#
CAD12/CADR11
CAD9/CADR10
CAD8/CDATA15
CAD7/CDATA7
CAD6/CDATA13
CAD5/CDATA6
CAD4/CDATA12
CAD3/CDATA5
CAD2/CDATA11
CAD1/CDATA4
CAD0/CDATA3
CC/BE3#/REG#
CC/BE2#/CADR12
CC/BE1#/CADR8
CC/BE0#/CE1#
CPAR/CADR13
CFRAME#/CADR23
CTRDY#/CADR22
CIRDY#/CADR15
CSTOP#/CADR20
CDEVSEL#/CADR21
RESERVED/CADR19
CPERR#/CADR14
CSERR#/WAIT#
CREQ#/INPACK#
CCLKRUN#/WP(IOIS16#)
CCLK/CADR16
CINT#/RDY(IREQ#)
CRST#/RESET
CAUDIO/BVD2(SPKR#/LED)
RESERVED/CDATA14
RESERVED/CDATA2
RESERVED/CADR18
R5C843-CSP208P_CSP208~D
0.01U_0402_16V7K~D
0.33U_0603_10V7K~D
C434
1
1
2
2
4
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
CAD11/OE#
T18
CAD10/CE2#
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
F16
K18
P15
V19
N15
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
CGNT#/WE#
E18
A18
L19
M18
H19
F19
T14
CCD1#/CD1#
D15
CCD2#/CD2#
R16
CVS1/VS1#
H16
CVS2/VS2#
W18
C19
N16
Close to U32
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD15
CBS_CAD13
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CPAR
CBS_CFRAME#
CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_INTERNAL
CBS_CINT#
CBS_CRST#
1 2
C428 0.01U_0402_16V7K~D@
CBS_CAUDIO
CBS_CCD1#_R5C843
CBS_CCD2#_R5C843
CBS_CVS1
CBS_CVS2
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
L49
@
4
4
3
3
2
2
1
1
857CM-0009~D
R382 0_0402_5%~D
R383 0_0402_5%~D
R384 0_0402_5%~D
R386 0_0402_5%~D
CBS_CAD16 <32>
CBS_CAD15 <32>
CBS_CAD14 <32>
CBS_CAD13 <32>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>
CBS_CINT# <32>
CBS_CRST# <32>
CBS_CAUDIO <32>
CBS_CCD1#_R5C843 <32>
CBS_CCD2#_R5C843 <32>
CBS_CVS1 <32>
CBS_CVS2 <32>
CBS_RSVD/D14 <32>
CBS_RSVD/D2 <32>
CBS_RSVD/A18 <32>
5
5
6
6
7
7
8
8
12
12
12
12
Close to J1
3
R365 22_0402_5%~D
Close to U32.A16,B16
1 2
C426
0.01U_0402_16V7K~D
Close to U32.A14
0.01U_0402_16V7K~D
10K_0402_5%~D
2
12
R361
C427
1
Close to U32.D13,B14
12
CBS_CCLK <32>
C424
12
18P_0402_50V8J~D
C425
12
18P_0402_50V8J~D
R5C843XI
R5C843XO
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
IEEE1394_TPBIAS0
USB_HUBP1+<32,39>
USB_HUBP1-<32,39>
VPPEN0<32>
VPPEN1<32>
VCC5EN#<32>
VCC3EN#<32>
X4
24.576MHz_16P_1BG24576CKIA~D
1 2
R617 0_0402_5%~D
+3.3V_RUN_PHY
USB_HUBP1+
USB_HUBP1-
100K_0402_5%~D
12
R363
R364
R5C843XI
R5C843XO
12
U32B
D11
CPS
A16
XI
B16
XO
A14
FIL0
B12
TPAP0
A12
TPAN0
B13
TPBP0
A13
TPBN0
B10
TPAP1
A10
TPAN1
B11
TPBP1
A11
TPBN1
D12
TPBIAS0
D10
TPBIAS1
D13
VREF
B14
REXT
V14
USBDP
W14
USBDM
V13
VPPEN0
W13
VPPEN1
R13
VCC5EN#
T13
VCC3EN#
R7
REGEN#
100K_0402_5%~D
12
C428 Close Car dbus connector
J1
6
GND
5
TPA0+
TPA0TPB0+
TPB0-
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
GND
4
A+
3
A-
2
B+
1
B-
FOX_UV31413-4TA-7F~D
2
C424, C425 need to
test the starting
vaule, then modify
the value
MDIO00
1
2
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
SD_CLK
C683
0.1U_0402_16V4Z~D
R5C843
R5C843-CSP208P_CSP208~D
SD_EN
2
1
MDIO06
B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8
100K_0402_5%~D
12
@
R366
U33
5
IN
OUT
4
GND
ON/OFF#
N.C
AAT4250IGV-T1_SOT23-5~D
R609 0_0402_5%~D@
R606 0_0402_5%~D
R594 33_0402_5%~D
R645 33_0402_5%~D
R646 33_0402_5%~D
R647 33_0402_5%~D
R648 33_0402_5%~D
C717 100P_0402_50V8J~D
C718 100P_0402_50V8J~D
C719 100P_0402_50V8J~D
C720 100P_0402_50V8J~D
CLK_SD_48M
1
2
3
Close to JP5 pin5 Close to JP5 pin5
SD_EN
12
CLK_SD_48M
12
12
12
12
12
12
12
12
12
12
@
10_0402_5%~D
12
R607
@
CK48M_SD
4.7P_0402_50V8C~D
C653
2
1
+3.3V_RUN_CARD+3.3V_R5C843
1
1
C432
C431
2
2
1 2
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CardBus Controller(R5C843)
LA-3741P
1
T16PAD~D
R618
150K_0402_5%~D
31 53Friday, January 26, 2007
SD_DET# <32>
SD_WP# <32>
CLK_SD_48M <6>
SD_CMD <32>
SD_CLK <32>
SD_DATA0 <32>
SD_DATA1 <32>
SD_DATA2 <32>
SD_DATA3 <32>
of
0.1
Page 32
5
+3.3V_RUN +3.3V_R5C843 +3.3V_R5C843
1 2
R592 0_0805_5%~D
+3.3V_R5C843
D D
C443
C C
B B
A A
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
C444
C445
1
1
2
2
0.01U_0402_16V7K~D
C446
C453
1
1
2
2
+3.3V_R5C843
C454
C458
1
2
5
1
2
2
1
0.01U_0402_16V7K~D
C459
SD_DATA1<31>
SD_DATA0<31>
SD_CMD<31>
SD_DATA3<31>
SD_DATA2<31>
+SIM_PWR
C504
1U_0603_10V4Z~D
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
1
2
1
2
C438
C455
SD_CLK<31>
SD_DET#<31>
SD_WP#<31>
UIM_RESET<36>
10U_0805_10V4Z~D
1
2
C707
0.1U_0402_16V4Z~D
1
2
0.01U_0402_16V7K~D
C460
+UIM_VPP
UIM_DATA<36>
UIM_CLK<36>
+SIM_PWR
1
2
1
2
C439
C456
0.01U_0402_16V7K~D
0.47U_0603_16V4Z~D
1
2
1
2
1
2
C441
1
2
0.01U_0402_16V7K~D
+3.3V_RUN_PHY
1
C508
2
33P_0402_50V8J~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C442
1
2
1
1
C505
2
2
33P_0402_50V8J~D
0.01U_0402_16V7K~D
C440
1
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C457
1
2
0.47U_0603_16V4Z~D
C461
1
2
C507
33P_0402_50V8J~D
4
U32C
F5
VCC_3V1
G5
VCC_3V2
J19
VCC_3V3
K19
VCC_3V4
R5C843
W3
VCC_PCI3V1
R11
VCC_PCI3V2
R12
VCC_PCI3V3
A4
VCC_MD3V
R6
VCC_RIN1
E13
VCC_RIN2
L1
VCC_ROUT1
E14
VCC_ROUT2
E10
AVCC_PHY1
E11
AVCC_PHY2
A17
AVCC_PHY3
B17
AVCC_PHY4
A9
AGND1
B9
AGND2
D9
AGND3
D14
AGND4
A15
AGND5
B15
AGND6
J1
GND1
J5
GND2
K5
GND3
E9
GND4
R10
GND5
T10
GND6
V10
GND7
W10
GND8
L15
GND9
M19
GND10
+3.3V_RUN_CARD
SD_WP#
+UIM_VPP
UIM_DATA
UIM_RESET
UIM_CLK
C506
33P_0402_50V8J~D
231
4
5
SIM & SD CARD will combine together,
the connector will update to 18pin
4
R5C843-CSP208P_CSP208~D
JP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
HRS_FH12-40(19)SA-1SH(55) ~D
D12
@
NNCD5.6LG~D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GND
GND
+3.3V_R5C843
L2
NC1
C1
NC2
D1
NC3
E1
NC4
C2
NC5
D2
NC6
E2
NC7
E4
NC8
E12
NC9
CBS_CAD[0..31]<31>
USB signal,impedance
90ohm,trace
width/space=5/6
3
L50
1 2
BLM21A601SPT_0805~D
+3.3V_R5C843
U65A
1 2
0.1U_0402_16V4Z~D
CBS_CCD1#
0.1U_0402_16V4Z~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
8
C723
P
1A21B
G
SN74CB3Q3306APWR_TSSOP8~D
4
R654 0_0402_5%~D@
+3.3V_R5C843
1 2
C716
CBS_CAD13 US B_ HUBP1+
CBS_CSTSCHNG<31>
CBS_CAUDIO<31>
CBS_CC/BE3#<31>
CBS_CREQ#<31>
CBS_CSERR#<31>
CBS_CRST#<31>
CBS_CFRAME#<31>
CBS_CTRDY#<31>
CBS_CDEVSEL#<31>
CBS_CSTOP#<31>
CBS_CBLOCK#<31>
CBS_RSVD/A18<31>
CBS_RSVD/D14<31>
0.01U_0402_16V7K~D
C448
1
1
C447
2
2
10U_0805_10V4Z~D
EXUSB_EN#_CCD EXUSB_EN#
1
1OE
CBS_CCD1#_R5C843
3
12
EXUSB_EN#
8
1
U63A
P
1OE
3
1A21B
G
SN74CB3Q3306APWR_TSSOP8~D
4
CBS_CCD2#<39>
CBS_CVS2<31>
+SC_PWR
SC_IO_R<35>
CBS_VPP
CBS_VCC
CBS_CVS1<31>
@
270P_0402_50V7K~D
SCCD-<35>
@
270P_0402_50V7K~D
1 2
C429
CBS_CCD2#
CBS_CAD31
CBS_CAD30
CBS_CAD28
CBS_CSTSCHNG
CBS_CAUDIO
CBS_CC/BE3#
CBS_CREQ#
CBS_CSERR#
CBS_CRST#
CBS_CVS2
CBS_CAD19
CBS_CAD17
CBS_CFRAME#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CBLOCK#
CBS_RSVD/A18
CBS_CAD16
CBS_CAD15
CBS_CAD13
CBS_CVS1
CBS_CAD10
CBS_CAD8
CBS_RSVD/D14
CBS_CAD6
CBS_CAD4
CBS_CAD2
CBS_CCD1#
1 2
C430
+3.3V_RUN_PHY
0.01U_0402_16V7K~D
C449
1
1
C451
C450
2
2
1000P_0402_50V7K~D
1000P_0402_50V7K~D
+3.3V_R5C843
1 2
1
5
P
NC
4
A2Y
G
U64
NC7SZ04P5X_NL_SC70-5~D
3
CBS_CCD1#_R5C843 <31>
VCC3EN#<31>
EXUSB_EN# <39>
USB_HUBP1+ <31,39>
C429, C430 Clo se Cardbus connector
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
FOX_QTS0080A-1021-9F~D
1
2
VPPEN0<31>
VPPEN1<31>
VCC5EN#<31>
C722
0.1U_0402_16V4Z~D
+3.3V_R5C843
5
U62
1
P
IN1
O
2
IN2
G
74AHC1G08GW_SOT353-5~D
3
12
R656 0_0402_5%~D@
JCBUS1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
+3.3V_R5C843
C462
1 2
VCC3EN#_R5531
4
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
2
+5V_RUN
1
2
1
0.1U_0402_16V4Z~D
C465
2
0.1U_0402_16V4Z~D
VCC3EN#_R5531
+3.3V_R5C843
1 2
R659
10K_0402_5%~D
C715
0.1U_0402_16V4Z~D
USB_HUBP1-<31,39>
CBS_CCLKRUN#
CBS_RSVD/D2
CBS_CAD29
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD18
CBS_CC/BE2#
CBS_CIRDY#
CBS_CCLK
CBS_CINT#
CBS_CGNT#
CBS_CPERR#
CBS_CPAR
CBS_CC/BE1#
CBS_CAD14
CBS_CAD12
CBS_CAD11
CBS_CAD9
CBS_CC/BE0#
CBS_CAD7
CBS_CAD5
CBS_CAD3
CBS_CAD1
CBS_CAD0
1
Close to U32
U34
11
VCC3IN
VCCOUT
VCCOUT
13
15
3
4
2
1
5
16
R5531V002-E2-FA_SSOP16~D
+3.3V_R5C843
CBS_CCD2#
R655
@
0_0402_5%~D
USB_HUBP1- CBS_CAD15
CBS_CCLKRUN# <31>
CBS_RSVD/D2 <31>
SC_DET# <35,39>
+SC_PWR
SC_RST#_R <35>
CBS_CC/BE2# <31>
SC_CLK_R <35>
CBS_CIRDY# <31>
CBS_CCLK <31>
SCCD+ <35>
CBS_VPP
CBS_VCC
CBS_CINT# <31>
CBS_CGNT# <31>
CBS_CPERR# <31>
CBS_CPAR <31>
CBS_CC/BE1# <31>
CBS_CC/BE0# <31>
VCCOUT
VCC5IN
VCC5IN
EN0
VPPOUT
EN1
VCC3_EN
VCC5_EN
FLG
GND
EXUSB_EN#_CCD
7
8
U65B
P
2OE
CBS_CCD2#_R5C843
6
2A52B
G
SN74CB3Q3306APWR_TSSOP8~D
4
12
+3.3V_R5C843
EXUSB_EN#
8
7
U63B
P
2OE
6
2A52B
G
SN74CB3Q3306APWR_TSSOP8~D
4
NC
NC
NC
CBS_VCC
9
14
12
CBS_VPP
8
1
C466
2
7
6
10
0.1U_0402_16V4Z~D
Close to JCBUS1 pin22,62
CBS_CCD2#_R5C843 <31>
EXUSB_EN#
CBS_VCC
1
C709
2
0.01U_0402_16V7K~D
Close to JCBUS1 pin23,63
1
2
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CardBus/SD card Socket
LA-3741P
1
0.01U_0402_16V7K~D
C684
C467
0.01U_0402_16V7K~D
1 2
R652
10K_0402_5%~D
1
C463
2
0.01U_0402_16V7K~D
32 53Friday, January 26, 2007
1
1
2
2
+3.3V_R5C843
C464
10U_0805_10V4Z~D
of
C708
10U_0805_10V4Z~D
0.1
Page 33
5
4
3
2
1
F1
PWRUSB_OC#<39>
2N7002W-7-F_SOT323~D
+USB_BACK_PWR
1 2
L58
MURATA BLM31PG500SNI_1206~D
D
Q30
@
S
C472
C469
0.1U_0402_16V4Z~D
1
2
USBP6_D-
0.1U_0402_16V4Z~D
1
2
USBP6_D+
USBP4_DUSBP4_D+
JP11
4
3
2
1
SUYIN_020173MR004S558ZL~D
4
3
2
1
SUYIN_020173MR004S558ZL~D
JP12
VCC
DD+
GND
VCC
DD+
GND
GND
GND
GND
GND
GND
GND
GND
GND
5
6
7
8
5
6
7
8
C468
1
+
2
150U_D_6.3VM_R55~D
Rear USB Ports
@
+5V_SUS
USB_BACK_EN#<39>
1
1
C475
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PORT_PWRUSB_SRC
1
12
R404
13
100K_0402_5%~D
2
G
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
1
C623
2
0.1U_0603_50V4Z~D
3
R406
200K_0402_5%~D
C482
0.1U_0603_50V4Z~D
2
DAT_SMB<18,40>
CLK_SMB<18,40>
2
+5V_SUS
1
C479
2
DAT_SMB
PWRUSB_SMBEN
C476
10U_0805_10V4Z~D
2
1
C480
10U_0805_10V4Z~D
2
D
S
1 3
Q26
2N7002W-7-F_SOT323~D
G
2
2
G
1 3
D
S
Q27
2N7002W-7-F_SOT323~D
@
+USBP5_PWR
JUMP1
PAD-OPEN2x2m
1 2
F2 0467005@
1 2
JUMP2
PAD-OPEN2x2m
1 2
F3 0467005@
1 2
DH_SMBDAT
DH_SMBCLKCLK_SMB
2
DBAY_MODPRES#<39>
1000P_0402_50V7K~D
Link CIS
+5V_FU5
USB_BACK_EN#
Link CIS
+5V_FUB
1
2
C473
@
150U_D_6.3VM_R55~D
C622
+
1
2
1
2
U35
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
U37
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
C474
0.1U_0402_16V4Z~D
1 2
R403
150_0402_5%~D
8
OC1#
7
OUT1
6
OUT2
5
OC2#
+USB_BACK_PWR
8
OC1#
7
OUT1
6
OUT2
5
OC2#
USBP5_DUSBP5_D+
PORT_PWRUSB_SRC
DH_SMBDAT
DH_SMBCLK
+USBP5_PWR
USB_OC5#
USB_OC4#
USB_OC6#USB_BACK_EN#
JDOG1
1
T1
2
T2
3
T3
4
T4
5
PWR_SRC
6
SMB_DATA
7
SMB_ALERT
8
SMB_CLK
9
GND2
FOX_UB1112C-PB202-7F_9P~D
USB_OC5# <24>
USB_OC4# <24>
USB_OC6# <24>USB_BACK_EN#<39>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
USB 2.0 Port
LA-3741P
33 53Friday, February 02, 2007
1
SHLD1
SHLD2
SHLD3
SHLD4
of
10
11
12
13
0.1
L53 DLW21SN900SQ2_0805~D@
USBP4+<24>
USBP4-<24>
D D
USBP6+<24>
USBP6-<24>
USBP5+<24>
USBP5-<24>
USBP4+
USBP4-
USBP6+
USBP6-
USBP5+
USBP5-
4
4
1
1
0_0402_5%~D
1 2
0_0402_5%~D
1 2
L56 DLW21SN900SQ2_0805~D@
4
4
1
1
0_0402_5%~D
1 2
0_0402_5%~D
1 2
DLW21SN900SQ2_0805~D
L57
@
1
1
4
4
0_0402_5%~D
1 2
0_0402_5%~D
1 2
R393
R394
R395
R396
R397
R398
3
2
3
2
2
3
USBP4_D+
3
USBP4_D-
2
USBP6_D+
3
USBP6_D-
2
USBP5_D+
2
USBP5_D-
3
USB Port
C C
+USBP5_PWR
U20
@
1
GND
USBP5+
USBP4+
USBP6+ USBP4-
B B
A A
5
IO2
2
IO1
VIN
PRTR5V0U2X_SOT143-4~D
U21
@
1
D1+
2
GND
3
D2-
IP4220CZ6_SO6~D
3
4
+USB_BACK_PWR
4
D2+
5
VCC
6
D1-
0.1U_0603_50V4Z~D
USBP5-
USBP6-
C481
+PWR_SRC
R399
Z2501
R401
12
100K_0402_5%~D
4
1 2
100K_0402_5%~D
Z2502
13
D
2
G
Q29
S
2N7002W-7-F_SOT323~D
4
123
Q25
FDS4435_NL_SO8~D
786
5
PWRUSB_SRC
1.5A_24V_MINISMDC150F/24~D
PWRUSB_EN <39>
1 2
1
2
Page 34
5
4
3
2
1
C483
1
2
+3.3V_RUN
1
2
12
C485
@
100P_0402_50V8J~D
Bluetooth
JBT1
1
1
2
2
3
3
4
4
5
5
GND
6
6
GND
7
7
8
8
9
9
10
10
JST_SM10B-SRSS-TB1(LF)(SN)~D
R408
10K_0402_5%~D
+5V_SUS
12
R411
10K_0402_5%~D
11
12
@
0_0402_5%~D
1 2
1 3
R409
D
S
Q32
BSS138W-7-F_SOT323~D
G
2
ICH_RST_MDC_R#
12
R410
100K_0402_5%~D
New MDC connector.
1
GND
3
IAC_SDATA0
5
GND
7
IAC_SYNC
9
IAC_SDATAIN
11 12
IAC_RESET#
IAC_BITCLK
RES
RES
3.3V
GND
GND
2
4
6
8
10
D D
0.1U_0402_16V4Z~D
12
R407
10K_0402_5%~D
BT_ACTIVE
BT_RADIO_DIS#
COEX3
1
C484
2
ICH_AZ_MDC_RST#<23>
MDC_RST_DIS#<39>
33P_0402_50V8J~D
COEX2_WLAN_ACTIVE<36>
COEX1_BT_ACTIVE<36>
USB_HUBP4-<39>
USB_HUBP4+<39>
C C
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
T9 PAD~D
BT_ACTIVE<36,44>
BT_RADIO_DIS#<24>
B B
JMDC1
1
ICH_AZ_MDC_SDOUT<23>
R414
33_0402_5%~D
ICH_AZ_MDC_SYNC<23>
ICH_AZ_MDC_SDIN1<23>
1 2
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SYNC
MDC_SDIN
ICH_RST_MDC_R#
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
131314141515161617171818191920
RES0
RES1
GND3
GND4
IAC_BITCLK
2
4
6
3.3V
8
10
12
TYCO_1-179397-2~D
20
W=20 mil
ICH_AZ_MDC_BITCLK
+3.3V_SUS
1
C486
2
4.7U_0603_6.3V6M~D
ICH_AZ_MDC_BITCLK<23>
1
C487
2
0.1U_0402_16V4Z~D
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK
R412
10_0402_5%~D@
R413
1 2
1 2
10_0402_5%~D@
Connector for MDC Rev1.5
C488
ICH_AZ_MDC_SDOUT
A A
ICH_AZ_MDC_SYNC
ICH_AZ_MDC_RST#
10P_0402_50V8J~D@
1 2
C491
10P_0402_50V8J~D@
1 2
C492
10P_0402_50V8J~D@
1 2
10P_0402_50V8J~D
MDC_AC_BITCLK_TERM
ICH_AC_SDOUT_MDCTERM
1
2
1
C490
10P_0402_50V8J~D
2
@
C489
@
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BT PORT & MDC
LA-3741P
34 53Friday, January 26, 2007
1
0.1
of
Page 35
8
D D
C C
B B
7
6
USB SMARTCARD READER.
TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.
+5V_RUN
+3.3V_RUN
12
R417
USB_HUBP3-<39>
USB_HUBP3+<39>
PCI_RST#<22,31,37>
1.5K_0402_1%~D
CLK_SMCARD_48M<6>
1
C493
2
USB_HUBP3USB_HUBP3+
PCI_RST#
1
C494
2
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
CLK_SMCARD_48M
12
R426
4.7K_0402_5%~D
MD0
U38
5
VCC5V_IN
28
VCC5V_IN
17
UPD-
16
UPD+
14
RST#
30
NC
31
NC
3
XI/48M_IN
4
XO
32
MODE0/SC_LED#
1
MODE1
2
MODE2
11
GND
13
GND
26
GND
C502
VRCPR
12
1U_0603_10V4Z~D
+3.3V_OUT
DPD+
EGATED-
EGATED+
SC_VCC
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
RF_OUT
RF_IN/RX
RF_CLK
RF_AUX
VR_CPR6VR_CPR
OZ77C6LN-B1_QFN32~D
12
DPD-
5
+3.3V_OUT
1
1
C495
C496
2
2
29
19
18
21
20
27
24
23
22
25
15
8
7
9
10
4.7U_0603_6.3V6M~D
SCCDSCCD+
+SC_PWR
4
HUB_USB_BIO-
HUB_USB_BIO+
12
12
R415
15K_0402_5%~D
0.1U_0402_16V4Z~D
C497
0.1U_0402_16V4Z~D
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
1
2
R562
R416
1 2
15K_0402_5%~D
1
C498
2
4.7U_0603_6.3V6M~D
3
1 2
R657 33_0402_5%~D
1 2
R658 33_0402_5%~D
L67
@
1
1
4
4
DLW21SN900SQ2_0805~D
R563
1 2
15K_0402_5%~D
15K_0402_5%~D
12
R418
10K_0402_5%~D
R422 220_0402_5%~D
R423 33_0402_5%~D
R424 220_0402_5%~D
R425 220_0402_5%~D
2
2
3
3
C724
@
1
C499
2
0.1U_0402_16V4Z~D
12
12
12
12
Close to Sma r t Card Conn.
47P_0402_50V8J~D
1
2
2
USB_BIO- <41>
USB_BIO+ <41>
1
1
2
2
C725
@
47P_0402_50V8J~D
+SC_PWR
12
C500
R420
47K_0402_5%~D
1U_0603_10V4Z~D
1
C501
2
0.1U_0402_16V4Z~D
SC_RST#_R
SC_CLK_R
SCCD+
SC_IO_R
SCCD-
<---Fingerprint
SC_RST#_R <32>
SC_CLK_R <32>
SCCD+ <32>
SC_IO_R <32>
SCCD- <32>
SC_DET# <32,39>
1
Place closely pin 3
CLK_SMCARD_48M
12
R427
@
10_0402_5%~D
1
C503
@
4.7P_0402_50V8C~D
A A
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
8
7
6
5
4
3
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Smart Card OZ77C6
LA-3741P
2
35 53Friday, January 26, 2007
1
0.1
of
Page 36
5
D D
L60 DLW21SN900SQ2_0805~D@
USB_HUBP2-<39>
USB_HUBP2+<39>
C C
1
1
4
4
1 2
1 2
Mini Card
2
2
3
3
R430
0_0402_5%~D
R431
0_0402_5%~D
Wire less LAN
4
USB_HUBP2_D-
USB_HUBP2_D+
JCLIP2
1
1
2
2
3
3
4
4
MOLEX_48099-5200~D
3
Mini Card
Wire less WAN
PCIE_WAKE#<29,39>
MINI1CLK_REQ#<6>
CLK_PCIE_MINI1#<6>
CLK_PCIE_MINI1<6>
PCIE_IRX_WANTX_N1<24>
PCIE_IRX_WANTX_P1<24>
PCIE_ITX_WANRX_N1_C<24>
PCIE_ITX_WANRX_P1_C<24>
PCIE_WAKE#
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
JMINI1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
MOLEX_67910-5200~D
2
JCLIP1
1
1
2
2
3
3
4
4
MOLEX_48099-5200~D
+3.3V_RUN+3.3V_RUN
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
+1.5V_RUN
UIM_DATA
UIM_CLK
UIM_RESET
+UIM_VPP
WWAN_RADIO_DIS#
PLTRST#
+3.3V_LAN
ICH_SMBCLK
ICH_SMBDATA
USB_HUBP2_DUSB_HUBP2_D+
+SIM_PWR
UIM_DATA <32>
UIM_CLK <32>
UIM_RESET <32>
+UIM_VPP
WWAN_RADIO_DIS# <24>
PLTRST# <10,20,22,24,29>
ICH_SMBCLK <6,24,29>
ICH_SMBDATA <6,24,29>
1
Mini-Card Latch
Mini-Card Latch
R638
8051TX<40>
+1.5V_RUN
1
C518
2
0.047U_0402_16V4Z~D
5
0_0402_5%~D
R6390_0402_5%~D
C519
1 2
1 2
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
1
2
0.047U_0402_16V4Z~D
PCIE_WAKE#<29,39>
COEX2_WLAN_ACTIVE<34>
COEX1_BT_ACTIVE<34>
MINI2CLK_REQ#<6>
CLK_PCIE_MINI2#<6>
CLK_PCIE_MINI2<6>
HOST_DEBUG_RX<40>
PCIE_IRX_WLANTX_N2<24>
PCIE_IRX_WLANTX_P2<24>
B B
A A
PCIE_ITX_WLANRX_N2_C<24>
PCIE_ITX_WLANRX_P2_C<24>
+3.3V_LAN
1
C517
2
0.1U_0402_16V4Z~D
+3.3V_RUN +3.3V_RUN
COEX2
COEX1
+3.3V_RUN
1
C520
0.047U_0402_16V4Z~D
2
JMINI2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
MOLEX_67910-5200~D
WLAN_RADIO_DIS#<39>
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
GND2
1
C521
0.047U_0402_16V4Z~D
2
+1.5V_RUN
WLAN_RADIO_OFF#
PLTRST#
+3.3V_LAN
LED_WLAN_OUT#
1 2
R555
@
0_0402_5%~D
D23
RB751S40T1_SOD523-2~D
@
4
21
1 2
R634
0_0402_5%~D
1
C522
0.1U_0402_16V4Z~D
2
HOST_DEBUG_TX <40>
PLTRST# <10,20,22,24,29>
ICH_SMBCLK <6,24,29>
ICH_SMBDATA <6,24,29>
USBP0- <24>
USBP0+ <24>
8051RX <40>
LED_WLAN_OUT# <44>
BT_ACTIVE <34,44>
WLAN_RADIO_OFF#
1
C523
0.1U_0402_16V4Z~D
2
1
C524
4.7U_0603_6.3V6M~D
2
+3.3V_RUN
1
C513
0.047U_0402_16V4Z~D
2
1
C514
0.047U_0402_16V4Z~D
2
PWR
Rail
+3.3V
+3.3Vaux
+1.5V
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C515
33P_0402_50V8J~D
2
Voltage
Tolerance
+-9%
+-9%
+-5%
1
C516
33P_0402_50V8J~D
2
Primary Power Aux Power
Peak Normal Normal
1000 750
330
500
2
1
+
C509
330U_V_6.3VM_R25M~D
2
250 (Wake enable)
250
5 (Not wake enable)
375
NA
1
+
C685
330U_V_6.3VM_R25M~D
2
+3.3V_LAN
1
C510
2
0.1U_0402_16V4Z~D
+1.5V_RUN
1
C511
0.047U_0402_16V4Z~D
1
C512
2
2
33P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Mini Card
LA-3741P
36 53Friday, January 26, 2007
1
of
0.1
Page 37
5
4
3
2
1
+5V_RUN
D D
C C
PCI_AD[0..31]<22,31>
D13
2 1
RB751S40T1_SOD523-2~D
QUIETE#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
+VCC_QBUFD
D14
2 1
RB751S40T1_SOD523-2~D
U39
1
NC1
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND1
11
NC2
12
A9
13
A10
14
A11
15
A12
16
A13
17
A14
18
A15
19
A16
20
GND2
21
NC3
22
A17
23
A18
24
A19
25
A20
26
A21
27
A22
28
A23
29
A24
30
GND3
31
NC4
32
A25
33
A26
34
A27
35
A28
36
A29
37
A30
38
A31
39
A32
40
GND4
PI5C34X2245BE_BQSOP80~D
VCC4
OE1#
VCC3
OE2#
VCC2
OE3#
VCC1
OE4#
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B1
B2
B3
B4
B5
B6
B7
B8
B9
+VCC_QBUF
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
1
C686
C687
2
2
0.1U_0402_16V4Z~D
C525
0.1U_0402_16V4Z~D
1 2
DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24
DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16
DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9
DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0
0.47U_0402_16V4Z~D
12
R432
1K_0402_5%~D
DOCK_AD[0..31] <38>
FIR
R433
47_0805_5%~D@
+IRVCC
C527
12
U40
6
VCC
SD_MODE
IRED_CATHODE
TXD
TFDU6102-TR3_8P~D@
IRED_ANODE
5
2
3
2
1
C528
1
2
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D@
@
MODE
GND
RXD
1
4
7
8
+3.3V_RUN
D_IRMODE<39>
12
R435
10K_0402_5%~D@
IRTX<39>
R436
+3.3V_RUN
IRRX <39>
12
1
C526
2
10K_0402_5%~D
4.7U_0603_6.3V6M~D@
@
R437
100K_0402_5%~D
1 2
+3.3V_RUN
5
U42
1
P
INA
4
O
2
INB
G
SN74AHC1G32DCKR_SC70-5~D
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
1
C529
0.1U_0402_16V4Z~D
2
QUIETE#
DOCKING BUFFER & FIR
LA-3741P
1
37 53Friday, January 26, 2007
0.1
of
C688
0.47U_0402_16V4Z~D
1 2
C530
B B
A A
5
PCI_PIRQA#<22>
PCI_GNT0#<22,38>
PCI_RST#<22,31,35>
SYS_PME#<31,39>
PCI_C_BE3#<22,31>
PCI_C_BE2#<22,31>
PCI_C_BE1#<22,31>
PCI_C_BE0#<22,31>
PCI_IRDY#<22,31,38>
PCI_FRAME#<22,31,38>
PCI_TRDY#<22,31>
PCI_STOP#<22,31>
PCI_PLOCK#<22>
PCI_DEVSEL#<22,31>
PCI_PERR#<22,31>
PCI_SERR#<22,31>
PCI_PAR<22,31>
QUIETE#
PCI_PIRQA#
PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_IRDY#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24
U41
47
OE1
VCC1
OE235VCC2
2
A0
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
1
13
PI5C162861BE_BQSOP48~D
Need to modify PAD width from 9mil to 8mil
4
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
GND1
NC1
GND2
NC2
0.1U_0402_16V4Z~D
36
48
46
45
44
43
42
41
40
39
38
37
34
33
32
31
30
29
28
27
26
25
12
24
1 2
DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#
DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL
DOCK_PIRQA# <38>
DOCK_GNT0# <38>
DOCK_PCIRST# <38>
DOCK_SPME# <38>
DOCK_C_BE3# <38>
DOCK_C_BE2# <38>
DOCK_C_BE1# <38>
DOCK_C_BE0# <38>
DOCK_IRDY# <38>
DOCK_FRAME# <38>
DOCK_TRDY# <38>
DOCK_STOP# <38>
DOCK_LOCK# <38>
DOCK_DEVSEL# <38>
DOCK_PERR# <38>
DOCK_SERR# <38>
DOCK_PAR <38>
DOCK_PCI_IDSEL <38>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DOCK_PCI_EN#<38>
QBUFEN#<39>
DOCK_PCI_EN#
QBUFEN#
2
Page 38
5
4
3
2
1
+DOCK_DC_IN
P5
P6
P7
P8
MH2
MH7
MH8
MH11
MH12
MH14
MH16
JDOCK1D
DOCK_AD[0..31] <37>
NB
PWR_SRC
LA-3741P
2
1
C531
0.1U_0603_50V4Z~D
C689
2
TYCO_2-1612415-3~D
1
SIGNAL 218P
RJ11 2P
VOID 52P
POWER 8P
VOID PIN: V14 V16 V44 V46 V56~V68 V123 V124
V129~V135 V191 V192 V197~V203 V219
V221 V249 V251 V260~V272
1 2
R439 150_0402_1%~D
1 2
R441 150_0402_1%~D
1 2
R442 150_0402_1%~D
no power dock
self powe r dock
38 53Friday, January 26, 2007
1
1000P_0402_50V7K~D
0.1
of
R448
1 2
100K_0402_5%~D
2
+DOCK_PW R_SRC
2
C532
1
0.1U_0603_50V4Z~D
Q33
FDS4435_NL_SO8~D
8
7
1
6
2
5
3
4
12
R446
100K_0402_5%~D
Z3307
13
D
Q35
2
2N7002W-7-F_SOT323~D
G
S
DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31
1
2
JDOCK1C
P1
P1
P2
P3
P4
MH1
MH5
MH6
MH9
MH10
MH13
MH15
+DOCK_PW R_SRC
C690
1000P_0402_50V7K~D
P5
P2
P6
P3
P7
P4
P8
MH1
MH2
SHLD1
SHLD3
SHLD2
SHLD4
SHLD5
SHLD7
SHLD6
SHLD8
MH14
MH13
MH16
MH15
TYCO_2-1612415-3~D
TV_C
TV_CVBS
TV_Y
DELL CONFIDENTIAL/PROPRIETARY
Title
DOCKING CONN.
Size Document Number Rev
Date: Sheet
JDOCK1A
1
S1
2
S2
DVI_CLK-<20>
DVI_CLK+<20>
DVI_TX4-
D D
PS_ID_IN<45>
CLK_PCI_DOCK<6>
DOCK_PIRQA#<37>
DOCK_SMB_CLK<40>
DOCK_SMB_DAT<40>
C C
CLK_DOCK<40>
DAT_DOCK<40>
POWER_SW#<18,40,44>
DVI_TX4+
DVI_TX3+
DVI_TX3-
DVI_TX5+
DVI_TX5-
DVI_TX2+<20>
DVI_TX2-<20>
DVI_TX1+<20>
DVI_TX1-<20>
DVI_TX0+<20>
DVI_TX0-<20>
DOCK_AD31
3
S3
4
S4
5
S5
6
S6
7
S7
8
S8
9
S9
10
S10
11
S11
12
S12
13
S13
15
S15
17
S17
18
S18
19
S19
20
S20
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
28
S28
29
S29
30
S30
31
S31
32
S32
33
S33
34
S34
35
S35
36
S36
37
S37
38
S38
39
S39
40
S40
41
S41
42
S42
43
S43
45
S45
47
S47
48
S48
49
S49
50
S50
51
S51
52
S52
53
S53
54
S54
55
S55
TYCO_2-1612415-3~D
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S125
S126
S127
S128
M136
69
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
VGA_RED
70
71
72
73
74
75
76
77
78
79
80
81
82
83
DOCK_AD8
84
DOCK_C_BE0#
85
86
87
DOCK_AD14
88
DOCK_AD15
89
90
91
92
93
94
95
DOCK_AD19
96
DOCK_AD20
97
98
99
DOCK_AD27
100
DOCK_AD28
101
DOCK_AD30
102
103
104
USBP7-
105
USBP7+
106
107
108
109
110
111
+2.5V_LOM
112
113
114
115
116
117
118
119
120
121
122
125
126
127
128
136
0_0402_5%~D
D_SERIRQ <39>
DOCK_PCI_IDSEL <37>
D_DLDRQ1# <39> D_LAD0 <39>
D_LFRAME# <39>
DVI_SCLK <20>
DVI_SDATA <20>
DVI_DETECT <20>
DOCK_C_BE0# <37>
DOCK_DEVSEL# <37>
DOCK_IRDY# <37>
DOCK_GNT0# <37>
USBP7- <24>
USBP7+ <24>
DOCK_SMB_INT# <40>
CLK_KBD <40>
DAT_KBD <40>
R440
+2.5V_LOM_DOCK
12
C533
0.01U_0402_16V7K~D
1 2
C535
0.01U_0402_16V7K~D
1 2
DOCK_LAN_TX3- <30>
DOCK_LAN_TX3+ <30>
DOCK_LAN_TX2- <30>
DOCK_LAN_TX2+ <30>
D_LAD1<39>
D_LAD2<39>
D_LAD3<39>
DOCK_PAR<37>
DOCK_SERR#<37>
DOCK_LOCK#<37>
DOCK_FRAME#<37>
DOCK_C_BE2#<37>
DOCK_SPME#<37>
DOCK_PCI_EN#<37>
SPDIF_DOCK<27>
DOCK_LED_10#<30>
DOCK_LED_100#<30>
+3.3V_RUN
C534
0.01U_0402_16V7K~D
12
C536
0.01U_0402_16V7K~D
12
DOCK_LAN_TX1-<30>
DOCK_LAN_TX1+<30>
DOCK_LAN_TX0-<30>
DOCK_LAN_TX0+<30>
RJ_TIP_L<30>RJ_RING_L <30>
DOCK_DET# DOCK_DET#
VGA_GRN
VGA_BLU
D_LAD1
D_LAD2
D_LAD3
DOCK_AD1
DOCK_AD0
DOCK_AD3
DOCK_AD4
DOCK_AD7
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_C_BE2#
DOCK_AD16
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD29
TV_C
SPDIF_DOCK
DOCK_LED_10#
DOCK_LED_100#
DOCK_OWNS_PCI
12
R438 100K_0402_5%~D@
JDOCK1B
137
S137
138
S138
139
S139
140
S140
141
S141
142
S142
143
S143
144
S144
145
S145
146
S146
147
S147
148
S148
149
S149
150
S150
151
S151
152
S152
153
S153
154
S154
155
S155
156
S156
157
S157
158
S158
159
S159
160
S160
161
S161
162
S162
163
S163
164
S164
165
S165
166
S166
167
S167
168
S168
169
S169
170
S170
171
S171
172
S172
173
S173
174
S174
175
S175
176
S176
177
S177
178
S178
179
S179
180
S180
181
S181
182
S182
183
S183
184
S184
185
S185
186
S186
187
S187
188
S188
189
S189
190
S190
193
S193
194
S194
195
S195
196
S196
204
M204
TYCO_2-1612415-3~D
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
S220
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
S250
S252
S253
S254
S255
S256
S257
S258
S259
205
206
207
208
209
210
211
212
213
214
215
216
217
218
220
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
250
252
253
254
255
256
257
258
259
HSYNC_R
VSYNC_R
D_LAD0
DOCK_SIO_ALERT#
DOCK_AD2
DOCK_AD5
DOCK_AD6
DOCK_AD12
DOCK_AD13
DOCK_C_BE1#
DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#
DOCK_AD17
DOCK_AD18
DOCK_AD21
DOCK_C_BE3#
DOCK_AD25
DOCK_AD26
PCI_REQ0#
DOCK_PCIRST#
TV_CVBS
TV_Y
DOCK_LAN_ACTLED_YEL#
R_PIDEACT
DAT_DDC2 <12,21>
CLK_DDC2 <12,21>
HSYNC_R <21>
VSYNC_R <21>
D_CLKRUN# <39>
DOCK_SIO_ALERT# <39>
DOCK_C_BE1# <37>
DOCK_PERR# <37>
DOCK_STOP# <37>
DOCK_TRDY# <37>
DOCK_C_BE3# <37>
PCI_REQ0# <22>
DOCK_PCIRST# <37>
DOCK_LAN_ACTLED_YEL# <30>
R_PIDEACT <44>
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR
CLK_PCI_DOCK
12
B B
R443
@
33_0402_5%~D
1
C537
@
22P_0402_50V8J~D
2
TV_C<12>
A A
TV_Y<12>
TV_CVBS<12>
VGA_RED<12,21>
VGA_GRN<12,21>
VGA_BLU<12,21>
PCI_GNT0#<22,37>
PCI_IRDY#<22,31,37>
PCI_FRAME#<22,31,37>
5
PCI_GNT0#
+3.3V_RUN
1
2
5
1
P
NC
A2Y
G
U43
NC7SZ04P5X_NL_SC70-5~D
3
PCI_IRDY#
PCI_FRAME#
TV_C
TV_Y
TV_CVBS
VGA_RED
VGA_GRN
VGA_BLU
C649
0.1U_0402_16V4Z~D
Z3305
4
+3.3V_RUN
1 2
C651
0.1U_0402_16V4Z~D
5
U45
1
P
IN1
O
2
IN2
G
74AHC1G08GW_SOT353-5~D
3
+3.3V_RUN
1 2
C650
0.1U_0402_16V4Z~D
5
U44
1
P
IN1
2
IN2
3
Z3306
4
4
DOCK_OWNS_PCI
4
O
G
74AHC1G08GW_SOT353-5~D
+5V_ALW
R447
100K_0402_5%~D
1 2
DOCK_DET#
DOCK_PWR_EN<39>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
1 2
13
2
3
+PWR_SRC
0.1U_0603_50V4Z~D
R445
100K_0402_5%~D
Q34
DDTC144EUA-7-F_SOT323~D
DOCK_PWR_EN
2
C538
1
2
3
1
U46
3
74AHC1G08GW_SOT353-5~D
2
G
IN2
O
1
IN1
P
5
+3.3V_SUS
1 2
R449
@
0_0402_5%~D
R444
100K_0402_5%~D
1 2
G_DOC_PWRSRC
DOCKED <30,39>
D15
@
SM05_SOT23~D
Z3308
4
Page 39
5
+3.3V_ALW
1 2
R450 10K_0402_5%~D
1 2
R452 10K_0402_5%~D
D D
C C
B B
A A
1 2
R453 10K_0402_5%~D
1 2
R454 10K_0402_5%~D
1 2
R559 10K_0402_5%~D
1 2
R451 10K_0402_5%~D
1 2
R644 100K_0402_5%~D
+3.3V_RUN
R596 100K_0402_5%~D
Follow Travis to add that
Broadcom will be update for
next version.
Place closely pin 64
CLK_SIO_14M
22_0402_5%~D
22P_0402_50V8J~D
BID0
BID1
BID2
BID3
@
@
R461
C549
R469
@
12
12
1
2
R470
1 2
10K_0402_5%~D
@
DOCK_SIO_ALERT#
PCIE_WAKE#
PBAT_ALARM#
DBAY_MODPRES#
PWRUSB_OC#
SYS_PME#
HDDC_EN#
IMVP6_PROCHOT#
*
R471
R472
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
@
@
5
PCIE_WAKE#<29,36>
DOCK_SIO_ALERT#<38>
PBAT_PRES#<46>
DOCK_PWR_EN<38>
SNIFFER_WIRELESS_ON/OFF#<44>
PWRUSB_OC#<33>
PWRUSB_EN<33>
MDC_RST_DIS#<34>
LOM_CABLE_DETECT<29>
SPDIF_SHDN<27>
IMVP6_PROCHOT#<50>
DOCK_HP_MUTE#<27>
HP_NB_SENSE<27,28>
PBAT_ALARM#<46>
LOM_TPM_EN#<29>
LOM_LOW_PWR<29>
AUDIO_AVDD_ON<27>
ADAPT_TRIP_SEL<51>
ICH_PCIE_WAKE#<24>
THERMTRIP_SIO<18>
CBUS_GRST#<31>
FPBACK_EN<19>
CB_HWSPND#<31>
CPU_PROCHOT#<7>
HDDC_EN#<26>
USB_BACK_EN#<33>
DBAY_MODPRES#<33>
+3.3V_ALW
1 2
R473 10K_0402_5%~D
1 2
R474 10K_0402_5%~D
1 2
R475 10K_0402_5%~D
1 2
R476 10K_0402_5%~D
1 2
SYS_PME#<31,37>
DOCKED<30,38>
QBUFEN#<37>
BC_INT#<40>
BC_DAT<40>
BC_CLK<40>
ADAPT_OC<51>
NB_MUTE<28>
CBS_CCD2#<32>
EXUSB_EN#<32>
SC_DET#<32,35>
ICH_PME#<22>
D_IRMODE<37>
R602 0_0402_5%~D@
R653 0_0402_5%~D
BEEP<27>
R564 0_0402_5%~D@
IRTX<37>
IRRX<37>
*
*
4
PCIE_WAKE#
SYS_PME#
DOCK_SIO_ALERT#
PBAT_PRES#
DOCKED
QBUFEN#
DOCK_PWR_EN
SINFFER_WIRELESS_ON/OFF#
BC_INT#
BC_DAT
BC_CLK
PWRUSB_OC#
PWRUSB_ EN
MDC_RST_DIS#
NB_MUTE
12
SPDIF_SHDN
IMVP6_PROCHOT#
12
EXUSB_EN#
HP_NB_SENSE
PBAT_ALARM#
LOM_TPM_EN#
AUDIO_AVDD_ON
BEEP
SC_DET#
ICH_PCIE_W AKE#
ICH_PME#
THERMTRIP_SIO
12
FPBACK_EN
CB_HWSP ND#
CPU_PROCHOT#
HDDC_EN#
BID3
BID2
BID1
BID0
IRTX
IRRX
D_IRMODE
USB_BACK_EN#
DBAY_MODPRES#
BID2 BID1
*
0
0
0
0
0
0
00
4
+3.3V_ALW
34
57
85
U47
97
GPIOA[0]
98
GPIOA[1]
99
GPIOA[2]
100
GPIOA[3]
101
GPIOA[4]
102
GPIOA[5]
103
GPIOA[6]
104
GPIOA[7]
24
GPIOH[0]
25
GPIOH[1]
26
GPIOH[4]
27
GPIOH[5]
58
BC_INT#
59
BC_DAT
60
BC_CLK
1
GPIOE[0]/RXD
2
GPIOE[1]/TXD
3
GPIOE[2]/RTS#
4
GPIOE[3]/DSR#
5
GPIOE[4]/CTS#
84
GPIOE[5]/DTR#
83
GPIOE[6]/RI#
6
GPIOE[7]/DCD#
65
GPIOB[0]/INIT#
66
GPIOB[1]/SLCTIN#
67
GPIOC[2]/SCLT
68
GPIOC[3]/PE
69
GPIOC[4]/BUSY
70
GPIOC[5]/ACK#
71
GPIOC[6]/ERROR#
73
GPIOC[7]/ALF#
74
GPIOD[0]/STROBE#
75
GPIOC[1]/PD7
76
GPIOC[0]/PD6
77
GPIOB[7]/PD5
78
GPIOB[6]/PD4
79
GPIOB[5]/PD3
80
GPIOB[4]/PD2
81
GPIOB[3]/PD1
82
GPIOB[2]/PD0
61
GPIOD[1]
62
GPIOD[2]
63
GPIOD[3]/VBUS_DET
28
GPIOD[4]/OCS1_N
29
GPIOD[5]/OCS2_N
30
GPIOD[6]/OCS3_N
31
GPIOD[7]/OCS4_N
32
GPIOH[6]
33
GPIOH[7]
88
GPIOG[0]
89
GPIOG[1]
90
GPIOG[2]
91
GPIOG[3]
92
GPIOG[4]
93
GPIOG[5]
94
GPIOG[6]
95
GPIOG[7]
106
SYSOPT1/GPIOH[2]
107
SYSOPT0/GPIOH[3]
109
GPIOF[7]
110
GPIOF[6]
111
GPIOF[5]
112
GPIOF[4]
113
IRTX
114
IRRX
115
GPIOF[3]/IRMODE/IRRX3B
116
GPIOF[2]/IRTX2
117
GPIOF[1]/IRRX2
118
GPIOF[0]/IRMODE/IRRX3A
ECE5018 A0_VTQFP128~D
BID0BID3
00
0
1
1X02
0
108
VCC1
VCC1
VCC1
VCC1
ECE5018
GPIO
REV
X00
X01
USB
TEST
CLK
LPC
DLPC
X0311
00
A0001
3
1
C539
0.1U_0402_16V4Z~D
2
1
2
8
VDDA33
14
VDDA33
20
VDDA33
119
VCC1
USBDP0
USBDN0
USBDP1
USBDN1
USBDP2
USBDN2
USBDP3
USBDN3
USBDP4
USBDN4
VDDA33PLL
VDDA18PLL
VDD18
CAP_LDO
RBIAS
TEST_PIN
ATEST
XTAL1/CLKIN
XTAL2
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLKI (14.318 MHz)
VSS
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
PWRGD
OUT65
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
USBP1+
9
USBP1-
10
USB_HUBP1+
13
USB_HUBP1-
12
USB_HUBP2+
15
USB_HUBP2-
16
USB_HUBP3+
19
USB_HUBP3-
18
USB_HUBP4+
21
USB_HUBP4-
22
125
124
120
86
127
TEST_PIN is a No Connect
35
126
123
122
54
52
49
47
42
41
56
37
46
44
39
64
96
55
53
50
48
43
38
45
40
7
105
11
17
23
36
51
72
87
121
128
RBIAS
REG_EN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_SIO
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
RUNPWROK
WLAN_RADIO_DIS#
1
C552
2
4.7U_0603_6.3V6M~D
USBP1+ <24>
USBP1- <24>
USB_HUBP1+ <31,32>
USB_HUBP1- <31,32>
USB_HUBP2+ <36>
USB_HUBP2- <36>
USB_HUBP3+ <35>
USB_HUBP3- <35>
USB_HUBP4+ <34>
USB_HUBP4- <34>
12
Route RBIAS and its
R458
return to pin 128 very
short.
12K_0402_1%~D
1
1
C554
C553
2
2
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
2
1
C540
0.1U_0402_16V4Z~D
2
C543
0.1U_0402_16V4Z~D
SIO_VDDA
<---PC Card Bay
<---Mini1 WWAN
<---Smart Card
<---Blue Tooth
+3.3V_ALW
ECE5018_XTAL1
ECE5018_XTAL2
LPC_LAD[0..3] <23,29,40>
LPC_LFRAME# <23,29,40>
PLTRST2# <22,40>
CLK_PCI_SIO <6>
CLKRUN# <24,31,40>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,29,31,40>
CLK_SIO_14M <6>
D_LAD0 <38>
D_LAD1 <38>
D_LAD2 <38>
D_LAD3 <38>
D_LFRAME# <38>
D_CLKRUN# <38>
D_DLDRQ1# <38>
D_SERIRQ <38>
RUNPW ROK <40,43,50>
WLAN_RADIO_DIS# <36>
1
C555
2
4.7U_0603_6.3V6M~D
2
1
C544
2
12
1
C545
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R459
10K_0402_5%~D
1
1
2
1
2
C546
0.1U_0402_16V4Z~D
C541
0.1U_0402_16V4Z~D
1
C547
2
4.7U_0603_6.3V6M~D
12
12
R560
R462
0_0402_5%~D
1
2
1M_0402_5%~D
1
C542
0.1U_0402_16V4Z~D
2
+3.3V_ALW
12
L61
BLM18PG181SN1_0603~D
120ohm,600mA,0.25ohm
C638
4.7U_0603_6.3V6M~D
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
LOM_TPM_EN#
C548
12P_0402_50V8J~D
1 2
12
Y1
24MHZ_12PF_1BX24000CE1B~D
C550
1 2
12P_0402_50V8J~D
Place closely pin 56
R455 100K_0402_5%~D
R456 100K_0402_5%~D
R457 100K_0402_5%~D
R460 100K_0402_5%~D
CLK_PCI_SIO
22_0402_5%~D
22P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ECE5018
LA-3741P
1
+3.3V_RUN
12
12
12
+3.3V_ALW
12
12
R463
@
1
C551
@
2
39 53Friday, January 26, 2007
0.1
of
Page 40
5
D D
KSO[0..16]<41>
+5V_RUN
1 2
R499 0_0402_5%~D
Depop 0ohm when
doing flash
recovery
R505
@
C565
@
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
12
1
2
+3.3V_ALW+3.3V_ALW
12
R497
10K_0402_5%~D
DEBUG_ENABLE#
KSI[0..7]<41>
SIO_A20GATE<23>
12
SIO_THRM#<24>
CLK_TP_SIO<41>
R498
DAT_TP_SIO<41>
CLK_KBD<38>
DAT_KBD<38>
10K_0402_5%~D
CLK_DOCK<38>
DAT_DOCK<38>
8051RX<36>
8051TX<36>
PLTRST2#<22,39>
CLK_PCI_5004<6>
LPC_LFRAME#<23,29,39>
LPC_LAD[0..3]<23,29,39>
ICH_EC_ SP I_C LK<24>
ICHI_ECI_SPIO_DATA<24>
ICHO_ECO_SPII_DATA<24>
LPC_LAD[0..3]
CLKRUN#<24,31,39>
IRQ_SERIRQ<24, 29,31,39>
SIO_PWRBTN#<24>
BC_CLK<39>
BC_DAT<39>
BC_INT#<39>
MEC5004_XTAL1
MEC5004_XTAL2
SIO_A20GATE
SIO_THRM#
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051RX
8051TX
PLTRST2#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ
ICH_EC_ S PI _CLK
ICHI_ECI_SPIO_DATA
ICHO_ECO_SPII_DATA
EC_FLASH_SPI_CLK
ECI_FLASHO_DATA
ECO_FLASHI_DATA
SIO_PWRBTN#
BC_CLK
BC_DAT
BC_INT#
MEC5004_XOSEL
12
R507
10K_0402_5%~D
1 2
R482 4. 7K_0402_5%~D
1 2
R484 4. 7K_0402_5%~D
1 2
R487 4. 7K_0402_5%~D
1 2
R488 4. 7K_0402_5%~D
JDEBUG1
+3.3V_ALW
5
5
4
4
3
3
2
2
1
1
Place closely pin 58
CLK_PCI_5004
22_0402_5%~D
22P_0402_50V8J~D
C C
Molex_53261
@
B B
32 KHz Clock
MEC5004_XTAL1
Y3
MEC5004_XTAL2
R506
0_0402_5%~D
A A
5
32.768K_12.5PF_Q13MC30610003~D
1 4
12
2 3
1
C569
2
22P_0402_50V8J~D
1
C570
2
22P_0402_50V8J~D
4
+RTC_CELL
R586
U48
12
KSO17/GPIOA1
13
KSO16/GPIOA0
14
GPIO5/KSO15
15
GPIO4/KSO14
16
KSO13/GPIO18
17
KSO12/OUT8
18
KSO11/GPIOC7
19
KSO10/GPIOC6
20
KSO9/GPIOC5
23
KSO8/GPIOC4
24
KSO7/GPIO3
25
KSO6/GPIO2
27
KSO5/GPIO1
28
KSO4/GPIO0
29
KSO3/GPIOC3
30
KSO2/GPIOC2
31
KSO1/GPIOC1
32
KSO0/GPIOC0
33
KSI7/GPIO19
34
KSI6/GPIO17
35
KSI5/GPIO10
36
KSI4/GPIO9
37
KSI3/GPIO8
38
KSI2/GPIO7
39
KSI1/GPIO6
40
KSI0/SGPIO30
92
SGPIO34/A20M
50
OUT5/KBRST
75
GPIO94/IMCLK
76
GPIO95/IMDAT
77
KCLK
78
KDAT
79
EMCLK
80
EMDAT
81
GPIO20/PS2CLK/8051RX
82
GPIO21/PS2DAT/8051TX
57
LRESET#
58
PCICLK
59
LFRAME#
60
LAD0
61
LAD1
62
LAD2
63
LAD3
64
CLKRUN#
56
SER_IRQ
102
HSTCLK
105
HSTDATAIN
107
HSTDATAOUT
103
FLCLK
106
FLDATAIN
108
FLDATAOUT
109
FLCS0
110
FLCS1
87
BC_CLK
86
BC_DAT
85
BC_INT
122
XTAL1
124
XTAL2
123
XOSEL
+3.3V_ALW
12
12
+RTC_CELL_VCC0
1
C556
0.1U_0402_16V4Z~D
2
BC Bus
125
+EC_AGND
12
L63
BLM11A121S_0603~D
R511
@
100K_0402_5%~D
low=write protected
R512
100K_0402_5%~D
1 2
0_0402_5%~D
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
FWP#
Flash write protect bottom 4K
of internal bootblock flash
4
+3.3V_ALW
21
44
65
83
116
121
VCC1
VCC1
VCC1
VCC1
VCC1
VCC0
Keyboard and Mouse Interface
PWR SW
LPC Interface
Host/8051
VSS
VSS
VSS
VSS
51
74
88
113
SPI_WE#
ECI_FLASHO_DATA
SPI_CS#
VR_CAP
22
+VR_CAP
1
2
VSS
AGND
26
120ohm,600mA,0.25ohm
3
1
C557
0.1U_0402_16V4Z~D
2
POWER_ SW_IN2#
POWER_ SW_IN1#
POWER_ SW_IN0#
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
OUT11/PWM1
OUT10/PWM0
nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
SGPIO36 (SFPI_EN)
GPIO96/TOUT1
GPIOA3/WINDMON
GPIO83/32KHZ_OUT
nRESET_OUT/OUT6
VSS_PLL
VCC_PLL
MEC5004_VTQFP128~D
101
104
C567
12
0.1U_0402_16V4Z~D
C568
4.7U_0603_6.3V6M~D
4@
2
2
4
4
6
6
8
8
10
10
12
12
20
4@ : when with TAA Board
, need pop JP3
1
2
120
ALWON
119
126
127
128
ACAV_IN
118
BGPO0
8
AB1B_CLK
7
AB1B_DATA
6
AB1A_CLK
5
AB1A_DATA
93
94
95
96
111
112
9
10
97
98
99
100
43
42
41
48
OUT2/PWM3
47
OUT9/PWM2
46
45
66
55
54
69
68
67
70
71
91
SGPIO40
90
SGPIO41
89
SGPIO42
4
SGPIO43
1
SGPIO35
2
3
SGPIO37
52
11
OUT7/nSMI
115
nPWR_LED
114
nBAT_LED
84
nFWP
73
117
49
PWRGD
53
72
TEST_PIN
+3.3V_ALW_EC
1 2
D22
@
RB751S40T1_SOD523-2~D
JP3
1
1
3
3
5
5
7
7
9
9
11
11
131314141515161617171818191920
TYCO_1-179373-2~D
The same MDC connctor
for TAA module
3
2
1
12
1 2
2
SPI_CS#
12
12
C559
0.1U_0402_16V4Z~D
ALWON <47>
ACAV_IN <18,51>
SNIF FER_LED _OFF# <44>
BREATH_LED <44>
SIO_EXT_SCI# <24>
LOM_SMB_ALERT# <29>
PS_I D <45>
DOCK_S MB_INT# <38>
PS_ID_DISABLE# <45>
ATF_INT# <18>
SIO_EXT_SMI# <24>
BAT2_LED# <44>
BAT1_LED# <44>
BIA_PWM <12,19>
RUNPWROK <39,43,50>
RESET_OUT # <43>
+3.3V_ALW
R629
@
100K_0402_5%~D
B
2
C558
0.1U_0402_16V4Z~D
ALWON
SNIFFER_PWR_SW#
INSTANT_ON_SW#
MAIN_PWR_SW#
ACAV_IN
PBAT_SMBCLK
PBAT_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT
AUX_EN
SUS_ON
RUN_ON
ITP_DBRESET#
SBAT_SMBDAT
SBAT_SMBCLK
DAT_SMB
CLK_SMB
SIO_SLP_S5#
SIO_SLP_S3#
SIO_RCIN#
SIO_EXT_WAKE#
SNIFFER_LED_OFF#
FAN1_TACH
BREATH_LED
SIO_EXT_SCI#
PS_ID
VGA_IDENTIFY
LID_CL_SIO #
DEBUG_ENABLE#
HOST_DEBUG_TX
HOST_DEBUG_RX
CAP_LED#
SCRL_LED#
NUM_LED#
R642 0_0402_5%~D
DOCK_SMB_INT#
SFPI_EN
PS_ID_DISABLE#
ATF_INT#
SIO_EXT_SMI#
BAT2_LED#
BAT1_LED#
FWP#
1 2
R590 0_0402_5%~D@
RUNPWROK
RESET_OUT#
R637
0_0402_5%~D
Pop for flash corruption issue.
+3.3V_ALW
L62
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
21
R630
@
10K_0402_5%~D
ECO_FLASHI_DATA EC_FLASH_SPI _CLK
EC_FLASH_SPI_CLK
SPI_HOLD#
+3.3V_SUS
1
C560
0.1U_0402_16V4Z~D
2
PBAT_SMBCLK <46,51>
PBAT_SMBDAT <46,51>
DOCK_S MB_CLK <38>
DOCK_SMB_DAT <38>
AUX_EN <42,47>
SUS_ON <42,43,47>
RUN_ON <19,42,43,47,4 8,49>
ITP_DBRESET# <7,24>
SBAT_SMBDAT <19>
SBAT_SMBCLK <19>
DAT_SMB <18,33>
CLK_SMB <18,33>
SIO_SLP_S5# <24>
SIO_SLP_S3# <24>
SIO_RCIN# <23>
SIO_EXT_WAKE# <24>
FAN1 _TACH <18>
CAP_LED# <44>
SCRL_LED# <44>
NUM_LED# <44>
SPI_C S# <24>
12
R628
@
10K_0402_5%~D
1 2
C691
@
E
3
4.7U_0603_6.3V6M~D
Q76
@
PMST3906_SOT323-3~D
C
1
2
G
12
R632
@
100K_0402_5%~D
12
Bat2 = Amber LED
Bat1 = Green LED
20mA drive pins
13
D
S
2
1
SNIFFER_PWR_SW#
LID_CL_SIO #
12
R500
R501
@
@
10K_0402_5%~D
10K_0402_5%~D
1 2
R631 22_0402_5%~D@
Q77
@
2N7002W-7-F_SOT323~D
C561
10U_0805_6.3V6M~D
+RTC_CELL
12
R479
100K_0402_5%~D
R481
10K_0402_5%~D
SNIFFER_SW#
1 2
1
C563
1U_0603_10V4Z~D
2
+3.3V_ALW
12
R491
1M_0402_1%~D
R495
10_0402_5%~D
12
1
C564
0.047U_0402_16V4Z~D
2
T10PAD~D
HOST_DEBUG_TX <36>
HOST_DEBUG_RX <36>
T11PAD~D
+VR_CAPALWON
SPI_CS#
ECI_FLASHO_DATA
SPI_WE#
1@ : without TAA Board
, need pop U50
LID_CL#
MAIN_P WR_SW#
SNIFFER _SW# <44>
LID_CL# <44>
+3.3V_SUS +3.3V_SUS
12
R508
10K_0402_5%~D
@
1
2
3
4
M25P80-VMW6TP_SO8~D
Flash ROM
150 MIL SO8
R510
47_0402_5%~D
1 2
U50
1
2
3
4
M25P16-VMW6TP_SO8~D 1@
200 MIL SO8
INSTANT_ON_SW#
DOCK_SMB_DAT
DOCK_SMB_CLK
DOCK_SMB_INT#
DAT_SMB
CLK_SMB
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
VGA_IDENTIFY
U49
S#
Q
W#
VSS
CS#
SO
WP#
GND
1
+RTC_CELL
12
R477
100K_0402_5%~D
R478
10K_0402_5%~D
1 2
1
C562
2
1U_0603_10V4Z~D
R614 100K_0402_5%~D
R483 8.2K_0402_5%~D
R485 8.2K_0402_5%~D
R486 10K_0402_5%~D
R489 10K_0402_5%~D
R490 10K_0402_5%~D
R492 8.2K_0402_5%~D
R493 8.2K_0402_5%~D
R494 8.2K_0402_5%~D
R496 8.2K_0402_5%~D
R558 10K_0402_5%~D
EC_FLASH_PAD1
@SHORT PADS~D
SFPI_EN
1=Flash Recovery Enabled
0=Flash Recovery Disabled
8
VCC
7
HOLD#
6
C
5
D
1M SPI
8
VCC
7
HOLD#
6
SCLK
5
SI
POWER_SW# <18,38,44>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_ALW
R503
1K_0402_5%~D
12
2M SPI
+RTC_CELL
+5V_ALW
12
+3.3V_ALW
1
1
2
2
12
12
R504
10K_0402_5%~D
1
R509
2
10K_0402_5%~D
SPI_HOLD#
ECO_FLASHI_DATA
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Doc u m en t N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
EMC5004
LA-3741P
1
40 53Friday, F eb rua ry 02, 2007
C566
0.1U_0402_16V4Z~D
0.1
of
Page 41
5
4
3
2
+5V_RUN
1
Touch PAD
JTPAD
16
GND
15
GND
14
D D
LID_CL#
*
+3.3V_ALW
KSO[0..16]<40>
KSI[0..7]<40>
C C
B B
A A
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
1
1
1
1
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C575
C577
C576
1
1
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C578
C580
C579
+5V_RUN
SP_Y SP_Y
SP_V+
SP_X
SP_GND
1
2
100P_0402_50V8J~D
@
C645
1
1
1
1
2
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C581
C583
C584
C582
1
C573
2
0.1U_0402_16V4Z~D
1
1
2
2
100P_0402_50V8J~D
@
@
C646
C647
1
1
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
C585
100P_0402_50V8J~D
C586
USB_BIO-<35>
USB_BIO+<35>
100P_0402_50V8J~D
+3.3V_RUN
1
2
100P_0402_50V8J~D
@
C648
1
2
C587
SP_X
SP_Y
SP_GND
SP_V+
TP_CLK
TP_DATA
USB_BIOUSB_BIO+
JP4
@
6
GND
5
GND
4
4
3
3
2
2
1
1
HRS_FH12-10(4)SA-1SH(55)~D
1
1
1
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C590
C589
C588
C644
100P_0402_50V8J~D
2
1
0.1U_0402_16V4Z~D
1
2
C591
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
HRS_FH12-30-14-SA-1SH-55~D
SP_V+
SP_X
SP_GND
Co-lay with JP4
1
1
1
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C594
C593
100P_0402_50V8J~D
C592
JP6
6
GND
5
GND
4
4
3
3
2
2
1
1
IPEX_20413-004E~D
1
1
2
2
100P_0402_50V8J~D
C596
C595
100P_0402_50V8J~D
L64
C571
10P_0402_50V8J~D
BLM11A601S_0603~D
1 2
600ohm,100mA
1 2
L65
BLM11A601S_0603~D
600ohm,100mA
1
C572
2
10P_0402_50V8J~D
TP_DATA
1
2
JKYBRD1
25
24
23
22
21
20
19
18
17
16
15
14
13
27
12
26
11
10
9
8
7
6
5
4
3
2
1
HRS_FH28D-25SB-1SH~D
1
1
1
2
2
2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
C599
C598
C597
12
12
R513
4.7K_0402_5%~D
1
2
SPKER1
Part Number Description
PK230005C0L
PCMCIA BODY
Part Number Description
DC000002T0L
Bluetooth wire set cable
Part Number Description
DC02000980L
MDC wire set cable
Part Number Description
DC02000960L
T/P FPC
Part Number Description
DA300001O1L FPC 00B LF-3072P REV1 T/P FPC WITH BIO
LCD cable
Part Number Description
DC020008Q0L H-CONN SET 00B MB-LCD 12 WXGA
HDD FPC cable
Part Number Description
DA300001N1L
RTC BATT
Part Number Description
GC020008R00
Touch-PAD MODULE
Part Number Description
PK090003M0L TRACK PAD ALPS KGDDEN010A BIOSENSOR
LED FPC cable
Part Number Description
DA300001S1L
R514
4.7K_0402_5%~D
DAT_TP_SIO
CLK_TP_SIOTP_CLK
1
C627
C626
2
10P_0402_50V8J~D
10P_0402_50V8J~D
SPK PACK 00B 1W 8OHM
PCMCIA
FOXCONN
1CA86501-CR-4F
H-CONN SET 00B M/B-B/T
H-CONN SET 00B M/B-MDC
FPC 00B LF-3071P REV1 HITACHI
BATT CR2025 W/CABLE 170MAH MB 00B 0FD
FPC 00B LF-3073P REV1 LED FPC
CLK_TP_SIO <40>
DAT_TP_SIO <40>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
INT KB & FT & LID & TOUCH PAD
LA-3741P
41 53Friday, February 02, 2007
1
of
0.1
Page 42
5
4
3
2
1
DC/DC Interface
+15V_SUS
+5V_ALW
12
13
D
2
G
S
R519
100K_0402_5%~D
SUS_ON_5V#
Q39
2N7002W-7-F_SOT323~D
D D
SUS_ON<40,43,47>
SUS_ON
12
13
D
2
G
S
R517
100K_0402_5%~D
SUS_ENABLE
Q38
2N7002W-7-F_SOT323~D
+3.3V_SRC
Q37
STS11NF30L_SO8~D
8
7
5
1
2
36
4
C600
10U_0805_10V4Z~D
1
2
+3.3V_SUS
+3.3V_SUS Source
12
R518
20K_0402_5%~D
Run Planes Enable
+5V_SUS
Q40
SI4800DY-T1-E3_SO8~D
8
7
5
D24
MMBD4148W-7-F_SOT323~D
+3.3V_SRC
3
2
+1.8V_SUS
6
2
1
12
Q51
2N7002W-7-F_SOT323~D
4
Q43
SI4800DY-T1-E3_SO8~D
8
7
5
D
S
45
G
Q44
R534
470K_0402_5%~D
C605
3
ENAB_3VLAN <29>
1
2
36
10U_0805_10V4Z~D
C601
10U_0805_10V4Z~D
4
+1.8V_RUN
1
2
1
2
+5V_RUN
1
2
36
12
+5V_RUN Source
12
R522
20K_0402_5%~D
+3.3V_RUN Source
+3.3V_RUN
12
1
R523
20K_0402_5%~D
10U_0805_10V4Z~D
2
+5V_RUN
12
R526
@
1K_0402_5%~D
C603
+1.8V_RUN Source
+5VRUN_DIS
13
R525
20K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
RUN_ON_5V#
SUS_ON_5V#
2
G
+1.8V_SUS
2
G
D
Q45
S
@
12
R619
22_0805_5%~D
+1.8VSUS_DIS
13
D
Q69
S
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
Discharge Circuit
+3.3V_RUN
2
G
2
12
@
+3.3VRUN_DIS
13
D
S
+1.8V_RUN
12
R527
1K_0402_5%~D
Q46
@
2N7002W-7-F_SOT323~D
@
+1.8VRUN_DIS
13
D
2
G
S
+1.5V_RUN
12
R528
1K_0402_5%~D
Q47
@
2N7002W-7-F_SOT323~D
R529
@
1K_0402_5%~D
+1.5VRUN_DIS
13
D
2
G
Q48
S
@
2N7002W-7-F_SOT323~D
+0.9V_DDR_VTT
+0.9VDDR_DIS
2
G
+2.5V_RUN
12
R530
@
1K_0402_5%~D
13
D
S
2
G
Q49
@
2N7002W-7-F_SOT323~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
POWER CONTROL
LA-3741P
42 53Friday, January 26, 2007
1
of
12
R531
@
1K_0402_5%~D
+2.5VRUN_DIS
13
D
Q50
S
@
2N7002W-7-F_SOT323~D
0.1
2
Q41
AUX_EN<40,47>
+15V_SUS
G
12
R521
100K_0402_5%~D
13
D
S
C602
2
RUN_ENABLE<47>
RUN_ENABLE
1
2
4700P_0402_25V7K~D
200K_0402_5%~D
470P_0402_50V7K~D
12
R533
100K_0402_5%~D
N21917830
13
D
G
S
Q52
2N7002W-7-F_SOT323~D
C692
R633
R535
1
1 2
12
SI3456DV-T1-E3_TSOP6~D
+PWR_SRC+PWR_SRC
12
R532
100K_0402_5%~D
13
D
2
G
12
S
200K_0402_5%~D
4
+5V_ALW
12
R520
100K_0402_5%~D
C C
RUN_ON<19,40,43,47,48,49>
B B
A A
5
RUN_ON_5V#
2N7002W-7-F_SOT323~D
13
D
2
G
S
2N7002W-7-F_SOT323~D
Q42
Page 43
5
+5V_SUS
+5V_RUN
R621
200K_0402_5%~D
D D
+3.3V_RUN
R623
200K_0402_5%~D
+1.8V_RUN
R626
100K_0402_5%~D
C C
G
2
+3.3V_SUS
2
+1.8V_SUS
G
2
At S3 step back-drive: 78mV, change to SI2303
SI2303BDS-T1-E3_SOT23-3~D
S
Q70
D
1 3
R622
4.7K_0402_5%~D
Q72
DDTA114EUA-7-F_SOT323~D
R624
1 3
4.7K_0402_5%~D
SI2303BDS-T1-E3_SOT23-3~D
S
Q74
D
1 3
R627
4.7K_0402_5%~D
C
2
B
E
3 1
C
Q73
2
B
MMST3904-7-F_SOT323~D
E
3 1
C
Q75
2
B
MMST3904-7-F_SOT323~D
E
3 1
Q71
MMST3904-7-F_SOT323~D
At S3 step back-drive:198mV, change to SI2303
+3.3V_SUS
IMVP_PWRGD<24,50>
RESET_OUT#<40>
B B
A A
IMVP_PWRGD
RESET_OUT#
100K_0402_5%~D
ICH_PWRGD
10
R538
9
2
G
IN1
IN2
+3.3V_SUS
14
P
8
OUT
G
U53C
74VHC08MTCX_NL_TSSOP14~D
7
12
ICH_PWRGD#
13
D
Q53
S
2N7002W-7-F_SOT323~D
R537
0_0402_5%~D
1 2
4
2.5V_RUN_PWRGD<18>
1.5V_RUN_PWRGD<48>
1.05V_RUN_PWRGD<48>
ICH_PWRGD# <18>
ICH_PWRGD <10,24>
Follow Travis to
modify
5V_3V_RUN_PW RGD
12
12
12
R587
0_0402_5%~D
R589
R588
0_0402_5%~D
0_0402_5%~D
SUSPWROK_1P8V<49>
3
+3.3V_RUN
12
R536
20K_0402_5%~D
1
C617
0.01U_0402_16V7K~D
2
10K_0402_5%~D
0.1U_0402_16V4Z~D
+3.3V_SUS
A6Y
12
R557
1
C624
2
+3.3V_RTC_LDO_1
BAT54CW_SOT323~D
C613
0.1U_0402_16V4Z~D
1 2
8
U52B
P
2
G
74LVC3G14DC_VSSOP8~D
4
+3.3V_SUS
12
R556
100K_0402_5%~D
13
D
2
G
Q63
S
2N7002W-7-F_SOT323~D
+COINCELL
12
R539
1K_0402_5%~D
Z4012
3
2
D16
1
+RTC_CELL
1
C618
1U_0603_10V4Z~D
2
+3.3V_SUS
8
U52C
P
5
A3Y
G
74LVC3G14DC_VSSOP8~D
4
RUN_ON<19,40,42,47,48,49>
SUS_ON<40,42,47>
8
U52A
P
7
A1Y
G
74LVC3G14DC_VSSOP8~D
4
COIN RTC Battery
2
13
12
+COINCELL
+3.3V_SUS
1 2
14
U53A
74VHC08MTCX_NL_TSSOP14~D
1
P
IN1
OUT
2
IN2
G
7
+3.3V_SUS+3.3V_SUS
14
U53D
P
IN1
OUT
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
C616
0.1U_0402_16V4Z~D
3
4
5
11
JCOIN1
1
1
2
2
3
GND
4
GND
MOLEX_53780-0270~D
+3.3V_SUS
14
U53B
P
IN1
6
OUT
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
RUNPWROK
1
RUNPW ROK <39,40,50>
SUSPWROK <18,24>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Good
LA-3741P
43 53Friday, January 26, 2007
1
0.1
of
Page 44
5
H3
@H_C315D126
1
H13
H_C236D91
1
H4
@H_C315D126
H14
H_C236D91
H18
H_C315D126@
1
1
1
H2
H1
@H_C315D126
@H_C315D126
1
1
H11
H12
H_C236D91
@H_C236D126
1
D D
@H_C472D376
1
H17
H16
@H_C472D431X376
1
1
H5
@H_C315D126
1
H15
H_C236D91
1
H6
@H_C315D126
1
H7
@H_C315D126
1
MYLAR1
MYLAR2
MYLAR3
MYLAR4
MDC Cable latch
R_CAP_LED#
12
R_NUM_LED#
12
R_SCRL_LED#
12
BT_ACT
WLAN_ACT
R_SCRL_LED#
R_CAP_LED#
R_NUM_LED#
2
2
Q62
CLP2
EMI_CLIP
1
GND
CLP4
EMI_CLIP
1
GND
JP10
1
2
3
4
5
6
7
8
9
10
11
12
IPEX_20403-010E~D
+3.3V_SUS
<BOM Structure>
DDTA114EUA-7-F_SOT323~D
Q60
1 3
+3.3V_SUS
1 3
RUBBER1
RUBBER2
SCREW1
1
2
3
4
5
6
7
8
9
10
GND
GND
SNIFFER_LED_OFF#<40>
R552
220_0402_5%~D
1 2
1 2
R553
220_0402_5%~D
CLP1
EMI_CLIP
1
GND
CLP3
EMI_CLIP
1
GND
C C
CAP_LED#<40>
NUM_LED#<40>
SCRL_LED#<40>
BT_ACT
WLAN_ACT
+3.3V_RUN
R_SCRL_LED#
R_CAP_LED#
R_NUM_LED#
B B
SNIFFER_GREEN#<18>
A A
SNIFFER_YELLOW#<18>
R545 510_0402_5%~D
R546 510_0402_5%~D
R548 510_0402_5%~D
JLED1
@
1
1
2
2
3
3
4
4
5
+3.3V_RUN
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
HRS_FH12-10S-0.5SH(55)~D
SNIFFER_GREEN#
SNIFFER_YELLOW#
DDTA114EUA-7-F_SOT323~D
5
Co-lay with JLED1
4
H8
@H_C315D126
Part Number Description
EL00B00040L
Part Number Description
EL00B00050L
Part Number Description
EL00B00060L
Part Number Description
EL00B00070L
Part Number Description
FH00B00060L
Part Number Description
EL00B000O00
Part Number Description
MAAA00153G0
H9
@H_C315D126
1
1
HAU30_DOCKING_HOLE_MYLAR
HAU30_DOCKING_LOCK_L_MYLAR
HAU30_DOCKING_LOCK_R_MYLAR
HAU30_MYLAR_DDR2
HAU30_MIC_RUBBER
HAU30_RUBBER_MDC
SCREW M M 2.0D 3.0L K 4.6D ZK NL + CR3+
+3.3V_ALW
SNIFFER_G
SNIFFER_Y
4
H10
@H_C315D126
1
MYLAR5
Part Number Description
EL00B000N00
MYLAR6
Part Number Description
EL00B000X00
MYLAR7
Part Number Description
EL00B000A0L
IDE_ACT#<26>
R_PIDEACT<38>
R636
@
10K_0402_5%~D
1 2
LED_WLAN_OUT#<36>
SNIFFER_WIRELESS_ON/OFF#<39>
SNIFFER_SW#<40>
12-22AUYSYGC/530-A2/TR8_G/Y~D
G
2
1
3
Y
D18
HAU30_MYLAR_WLAN_WWAN
HAU30_MYLAR_HDD
HAU30_MYLAR_FAN
IDE_ACT#
Q56
E
3
PMST3906_SOT323-3~D
B
2
C
1
SNIFFER_SW#
+3.3V_RUN
2
BT_ACTIVE<34,36>
BT_LED_DIS#
2
10K_0402_5%~D
Q54
DDTA114EUA-7-F_SOT323~D
1 3
1 2
R540
47_0402_5%~D
+3.3V_RUN
Q58
DDTA114EUA-7-F_SOT323~D
1 3
R547 510_0402_5%~D
+3.3V_ALW
12
R549
3
Fiducial Mark
FD1
1
FIDUCIAL MARK~D
FD7
1
FIDUCIAL MARK~D
FD13
1
FIDUCIAL MARK~D
FD19
FIDUCIAL MARK~D
1
FD25
1
FIDUCIAL MARK~D
FD31
1
FIDUCIAL MARK~D
LED1
LTST-C190KG K T_GRN_0603~D
12
R541
10K_0402_5%~D
1 2
WLAN_ACT
12
JSNIFF
6
GND
5
GND
4
4
3
3
2
2
1
1
1BS008-13130-002-7F_4P~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
13
D
2
G
S
FD2
1
FIDUCIAL MARK~D
FD8
1
FIDUCIAL MARK~D
FD14
1
FIDUCIAL MARK~D
FD20
FIDUCIAL MARK~D
1
FD26
1
FIDUCIAL MARK~D
FD32
1
FIDUCIAL MARK~D
+5V_RUN
2
BSS138W-7-F_SOT323~D
Q78
DDTA114EUA-7-F_SOT323~D
Q55
1 3
R542 470_0402_5%~D
1
FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
1 2
BAT1_LED#<40>
FD3
FD9
FD15
FD21
FD27
BAT2_LED#<40>
BT_ACT
BAT1_LED#
2
FD4
1
FIDUCIAL MARK~D
FD10
1
FIDUCIAL MARK~D
FD16
1
FIDUCIAL MARK~D
FD22
1
FIDUCIAL MARK~D
FD28
1
FIDUCIAL MARK~D
BREATH_LED<40>
BAT2_LED#
2
2
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FIDUCIAL MARK~D
POWER_SW#<18,38,40>
+3.3V_ALW
LID_CL#<40>
+3.3V_ALW
FD5
1
FD11
1
FD17
1
FD23
1
FD29
1
POWER_S W_LED
POWER_SW#
LID_CL#
R616
10K_0402_5%~D
1 2
R544
10K_0402_5%~D
1 2
+3.3V_ALW
2
1 3
Q61
DDTA114EUA-7-F_SOT323~D
1 3
R551 56_0402_5%~D
FD6
1
FIDUCIAL MARK~D
FD12
1
FIDUCIAL MARK~D
FD18
1
FIDUCIAL MARK~D
FD24
1
FIDUCIAL MARK~D
FD30
1
FIDUCIAL MARK~D
JPSW
1
1
GND
2
2
GND
3
3
MOLEX_53780-0370~D
JPLID
1
1
GND
2
2
GND
3
3
MOLEX_53780-0370~D
2
C
Q68
2
B
MMST3904-7-F_SOT323~D
E
3 1
BREATH_LED_B
Q59
DDTA114EUA-7-F_SOT323~D
R550
1 2
330_0402_5%~D
1 2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc u m en t N u m be r Re v
Date: Sheet
4
5
4
5
+3.3V_SUS
Q67
DDTA114EUA-7-F_SOT323~D
1 3
1 2
R615 51_0402_5%~D
+3.3V_SUS
R543
51_0402_5%~D
1 2
LED3
LTST-C190KGKT_GRN_0603~D
1 2
C
Q57
2
B
MMST3904-7-F_SOT323~D
E
3 1
BATT_AMBER_LED
BATT_GREEN_LED
LTST-C155KGKFKT_GRN/ORG~D
Compal Electronics, Inc.
PAD and Standoff
LA-3741P
1
POWER_S W_LED
LED5
4 3
2 1
1
O
G
44 53Friday, F eb rua ry 02, 2007
0.1
of
Page 45
5
4
3
2
1
D D
PS_ID_IN
PS_ID_IN<38>
2
PD3
SM24_SOT23
@
C C
PR4
3
1
1 2
100K_0402_1%~D
PR7
1 2
15K_0402_1%~D
PS_ID Detector
PR2
0_0402_5%~D@
1 2
PQ1
FDV301N_SOT23
D
S
1 3
G
2
C
PQ2
2
B
PMBT3904_SOT23~D
E
3 1
PR3
33_0402_5%~D
1 2
PD1
DA204U_SOT323~D
+5V_ALW
+5V_ALW
PR5
10K_0402_1%~D
+3.3V_ALW
2
3
PR1
2.2K_0402_5%~D
PD2
@
1 2
+5V_ALW
DA204U_SOT323~D
PS_I D <40>
2
3
1
PS_ID_DISABLE# <40>
+PWR_SRC
PC143
1U_0805_25V4Z~D
1
3
12
+3.3VX Source
PU10
IN
5
OUT
EN
4
NC
GND
MIC5235-3.3BM5_SOT23-5~D
2
+3.3V_RTC_LDO_1
1
PC142
2.2U_0603_6.3V6K~D
2
1
PS_ID
12
PR6
100_0402_5%~D@
1 2
+DC_IN Source
PL1
B B
PJDCIN
9
GND4
8
GND3
7
GND2
6
GND1
FOX_JPD113E-LB103-7F
SINGAL
DC+_1
DC+_2
DC-_1
DC-_2
5
1
+DCIN_JACK
2
3
4
-DCIN_JACK
BLM11B102S 0603~D
PWR_ID
FBM-L11-453215-900LMAT_1812~D
FBM-L11-453215-900LMAT_1812~D
PL2
1 2
PL3
1 2
12
PS_I D_IN <38>
12
PC6
0.01U_0402_25V7K~D
@
PC1
1 2
0.47U_0805_25V7k
+DOCK_DC_IN
12
PR8
240K_0402_5%~D
PQ3
SI4825DY_SO8~D
1
2
3 6
4
PQ_G
12
PR10
47K_0402_5%~D
8
7
5
12
12
12
PC2
0.01U_0402_25V7K~D
PC4
PC3
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
PR9
12
PC5
4.7K_0603_5%~D
10U_1206_25V6M~D
THE POINT
NOTE: "THE POINT LOCATED
AT PS MODULE
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Doc u m en t N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
+DCIN
LA-3741P
1
45 53Friday, J anu ary 26, 2007
0.1
of
Page 46
5
4
3
2
1
2
PD5
DA204U_SOT323~D@
PR13
1 2
ESD Diodes
2
3
1
PR14
100_0402_5%~D
1 2
3
100_0402_5%~D
1 2
9
8
2
3
2
+VCHGR
PD6
1
DA204U_SOT323~D@
PR15
PD7
1
DA204U_SOT323~D@
PBAT_SMBCLK <40,51>
PBAT_SMBDAT <40,51>
PBAT_ALARM# <39>
PC7
0.1U_0603_25V7K~D
PL4
FBM-L11-453215-900LMAT_1812~D
1 2
12
+3.3V_ALW
12
PR11
10K_0402_1%~D
PBAT_PRES# <39>
7
6
5
4
3
2
1
SUYIN_200028MR009G502ZL
TOP view
D D
+PBATT
Z4304
Z4305
Z4306
Z4307
+PBATT
Battery Connector
PJBAT1
SUYIN200277MR009G508ZR~D
12
PC8
2200P_0402_50V7K~D
C C
BATT_PRES#
10
GND
11
GND
BATT1+
BATT2+
SMB_CLK
SMB_DAT
SYSPRES#
BATT_VOLT
BATT1BATT2-
9
8
7
6
5
4
3
2
1
+3.3V_ALW
PD4
DA204U_SOT323~D@
PR12
100_0402_5%~D
1 2
3
1
100_0402_5%~D
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Battery Conn
LA-3741P
46 53Friday, January 26, 2007
1
0.1
of
Page 47
5
PJP2
@
1 2
PAD-OPEN 4x4m
PL5
FBM-L11-453215-900LMAT_1812~D
+PWR_SRC
D D
3.3 Volt +/- 5%
Design Current: 6.5 A
Maximum current: 9.1A
OCP: 10.95A
+3.3V_SRCP
+3.3V_SRCP
1
12
+
PC26
PC25
2
C C
+VCC_TPS51120
AUX_EN<40,42>
SUS_ON<40,42,43>
B B
+3.3V_SRCP
S
G
D
6
2451
+3.3V_ALW
3.3V OCP
Fsw=440 KHZ
Rds_on_MAX=15m; Itrip_MIN=8.5uA;L=2.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=3.3/2.7u * 1/440K *(1-3.3/19)=2.3A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*14.7K/15m=8.33A
Ivalley= Itrip*Rtrip/Rds_on=10u*14.7K/15m=9.8A
A A
Iocp_MIN=8.33+2.3/2=9.48A
Iocp=9.8+2.3/2=10.95A
0.1U_0603_25V7K~D
330U_D3L_6.3VM_R25~D
PC118
0.1U_0603_25V7K~D
3
RUN_ENABLE <42>
PQ24
FDC655BN_NL_SSOT-6~D
5
PR135
0_0402_5%~D
1
2
12
+3.3V_RTC_LDO
1 2
PR21
0_0402_5%~D
1 2
@
PR24
1 2
1 2
0_0402_5%~D
@
GNDA_DCDC1
PR136
0_0402_5%~D@
12
3
G
I1
4
O
I0
P
PU7
5
SN74AHC1G32DCKR_SSOP5~D
PR160
0_0402_5%~D
@
1 2
+3.3V_RTC_LDO_1
THERM_STP#<18>
2.7U_SIL1055R-2R7PF_9A
PL7
1 2
PR27
10K_0402_5%~D
PQ5
SI4800DY-T1_SO8~D
PQ7
FDS6690AS_NL_SO8~D
12
SUS_ON<40,42,43>
PD18
2
BAT54CW_SOT323~D
1
PC10
2200P_0402_50V7K~D
Place these CAPs
close to FETs
578
3 6
241
578
3 6
241
PR157
1 2
3
100K_0402_1%~D
4
+DC1_PWR_SRC
12
12
PC11
0.1U_0603_25V7K~D
+3.3V_SRCP_L
PR30
10K_0402_5%~D
ALWON<40>
4
12
PC12
10U_1206_25V6M~D
0.1U_0603_25V7K~D
12
12
PC32
PR40
4.7K_0402_5%~D
PC20
0.01U_0603_25V7K~D
PC120
@
0.1U_0603_25V7K~D
12
12
10U_1206_25V6M~D
12
PC22
12
1K_0402_5%~D
+3.3V_RTC_LDO
DC/DC +3V/ +5V/ +15V
+VCC_TPS51120
PR17
5.1_0603_5%~D
12
PR36
PC31
@
1000P_0402_50V7K~D
2
G
PR20
0_0603_5%~D
1 2
TPS51120_DRVH2
TPS51120_LL2
TPS51120_DRVL2
TPS51120_VO2
TPS51120_VFB2
12
12
@
S
PR159
12
PC19
1U_0603_10V6K~D
GNDA_DCDC1
22
20
13
14
15
16
17
12
29
PR162
19
0_0402_5%~D@
10
12
+3.3V_RTC_LDO
12
PC30
10U_0805_6.3V5K~D
PR161
0_0805_5%~D
12
D
13
PQ9
G
SI2301BDS-T1-E3 _SOT23~D
2
1
12
3
2.2M_0402_5%~D
13
D
PQ11
RHU002N06_SOT323
S
9
8
6
BAT54CW_SOT323~D
PU1
2
VIN
V5FILT
EN5
VBST2
DRVH2
LL2
DRVL2
PGND2
VO2
VFB2
EN2
EN1
VREG3
EN3
PD10
@
TPS51120
32 QFN 5X5
PR38
0_0402_5%~D
PD21
@
RB717F_SOT323~D
2
SKIPSEL
32
TPS51120_SKIP#
12
1
3
TONSEL
PGOOD1
PGOOD2
PAD
33
PR34
0_0402_5%~D@
1 2
PR35
0_0402_5%~D @
1 2
PR37
0_0402_5%~D @
1 2
RUN_ON<19,40,42,43,48,49>
VREG5
VBST1
DRVH1
DRVL1
PGND1
COMP1
COMP2
VREF2
3
PC14
SI4800DY-T1_SO8~D
SI4810BDY_SO8~D
10K_0402_1%~D
0.1U_0603_25V7K~D
1 2
12
578
3 6
578
3 6
PC15
2200P_0402_50V7K~D
241
+5V_SUSP_L
241
PC28
12
1000P_0402_50V7K~D
12
12
PC13
12
1 2
100K_0402_1%~D
+VCC_TPS51120
12
13
D
PQ10
RHU002N06_SOT323 @
S
PC134
10U_1206_25V6M~D
@
12
Place these CAPs
PC18
close to FETs
1U_0603_10V6K~D
PC21
0.1U_0603_25V7K~D
1 2
PC27
1000P_0402_50V7K~D
GNDA_DCDC1
PR39
0_0402_5%~D@
1 2
D
S
13
G
2
12
PQ8
SI2301BDS-T1-E3 _SOT23~D@
10U_1206_25V6M~D
PQ4
PQ6
PR25
SUSP WROK_5 V <49>
+5V_ALW
PC17
10U_1206_25V6M~D
PR18
21
0_0603_5%~D
28
1 2
TPS51120_DRVH1
27
TPS51120_LL1
26
LL1
TPS51120_DRVL1
25
24
TPS51120_VO1
1
VO1
TPS51120_VFB1
3
VFB1
2
7
TPS51120_CS1
23
CS1
TPS51120_CS2
18
CS2
4
31
5
GND
30
11
GNDA_DCDC1
+3.3V_SRCP
PR31
+VCC_TPS51120
+3.3V_ALW
PR41
200K_0402_1%~D
@
2
G
12
PC33
4.7U_1206_10V7K~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
2
PR16
0_0805_5%~D
+15VS_L
1 2
12
PC9
PD9
EC11FS2_SOD106~D
12
PR26
2 1
+15VS
1 4
14.7K_0402_1%~D
3 2
12
PC29
1 2
1000P_0402_50V7K~D
GNDA_DCDC1
2
2.2U_1206_25V7M~D
PL6
4.7U_SDT-1204P-4R7D-122GP_20%
PR28
@
PR32
@
PR137
PR19
0_0402_5%~D
@
PR22
0_0402_5%~D
@
GNDA_DCDC1
PR29
0_0402_5%~D
1 2
0_0402_5%~D
1 2
1
15 Volt
Maximum Current: 10mA
PQ25
2N2222_SOT23~D
31
CBE
12
2
PR138
0_0805_5%~D
1 2
@
1
10K_0805_5%~D
+5V_SUSP
1 2
1 2
0_0402_5%~D
1 2
PR23
PD8
2
3
MMBZ5245B_SOT23~D
+5V_SUSP
12
PC24
PC23
0.1U_0603_25V7K~D
1 2
0_0402_5%~D
330U_D3L_6.3VM_R25~D
+VCC_TPS51120
5V OCP
Fsw=290 KHZ
Rds_on_MAX=20m; Itrip_MIN=8.5uA;L=4.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=5/4.7u * 1/290K *(1-5/19)=2.7A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*10K/20m=4.25A
Ivalley= Itrip*Rtrip/Rds_on=10u*10K/20m=5A
Iocp_MIN=4.25+2.7/2=5.6A
Iocp=5+2.7/2=6.35A
+15VP
12
PC16
2.2U_1206_25V7M~D
5 Volt +/- 5%
Design Current:3.63A
Maximum current: 5.191 A
OCP: 6.35A
1
+
2
+15VP
+5V_SUSP
+3.3V_SRCP
PR133
0_0603_5%~D
PJP3
@
1 2
PAD-OPEN 4x4m
PJP4
@
1 2
PAD-OPEN 4x4m
PJP5
@
1 2
PAD-OPEN 4x4m
PJP12
@
1 2
PAD-OPEN 4x4m
12
GNDA_DCDC1
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc u m en t N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
+3.3V/+5V/+15V
LA-3741P
1
47 53Friday, January 26, 2007
of
+15V_SUS
+5V_SUS
+3.3V_SRC
0.1
Page 48
A
PJP6
@
1 2
PAD-OPEN 4x4m
PL8
FBM-L11-453215-900LMAT_1812~D
+PWR_SRC
1 1
1 2
12
PC35
10U_1206_25V6M~D
+DC2_PWR_SRC
12
12
PC37
PC36
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
1.5V +/- 5%
Thermal Design Current: 2.5A
Maximum Current: 3.6A
MIN_OCP: 3.7A
+1.5V_RUN_P
1
12
+
PC49
PC50
2 2
3 3
330U_D2E_2.5VM_R9
1U_0603_10V6K~D@
+1.5V_RUN_P
+1.05V_VCCP_P
2
RUN_ON<19,40,42,43,47,49>
PL9
3.3uH_PCMC063T-3R3MN_6A_20%
PJP7
@
1 2
PAD-OPEN 4x4m
PJP8
@
1 2
PAD-OPEN 4x4m
12
1.5V_RUN_PWRGD<43>
Place these CAPs
close to FETs
PQ12
FDS6994S_SO8~D
4
3
2
1
+1.5V_RUN
+1.05V_VCCP
5
D1
G1
6
S1
D1
7
G2
D2
8
D2
S2
Use PR56 and PR58 for
Voltage Margining.
0_0603_5%~D
0_0603_5%~D
GNDA_DC2A
PR63
PR64
15K_0402_1%
12
GNDA_DC2A
12
PR47
453K_0402_1%~D5@
PC47
0.1U_0603_25V7K~D
PR58
12
12
12
8.45K_0402_1%
1 2
9.09K_0603_1%~D5@
1 2
PR56
30K_0402_1%
+3.3V_RUN
PR140
PR51
PR54
12
12
100K_0402_1%~D
B
1M_0402_5%~D
PR43
PR45
1 2
12
PC44
PC43
1000P_0402_50V7K~D
PR49
0_0603_5%~D
12
PC55
18P_0402_50V8J
PD20
MMBD4148W-7-F_SOD323~D
10_0402_5%
1 2
1 2
1U_0603_6.3V6M
GNDA_DC2A
12
1 2
BAT54A-7-F_SOT23~L
12
PC41
PU2
3
VDDP1
1
PGND1
1U_0603_10V6K~D
25
VCCA1
28
AGND1
23
TON1
7
BST1
6
DH1
5
LX1
4
ILIM1
2
DL1
24
VOUT1
26
FBK1
22
EN/PSV1
27
PGOOD1
SC1485ITSTR-TPS51483_TSSOP28
1 2
PC141
@
0.1U_0603_25V7K~D
12
PR60
1K_0402_1%~D
+5V_SUS
1
PD17
VDDP2
PGND2
VCCA2
AGND2
SC483/TPS51483
VOUT2
EN/PSV2
PGOOD2
PR62
1K_0402_1%~D
1 2
TON2
BST2
DH2
LX2
ILIM2
DL2
FBK2
C
12
PC34
32
PC42
17
15
11
14
9
21
20
19
18
16
10
12
8
13
12
1U_0603_10V6K~D
GNDA_DC2B
1U_0603_10V6K~D
PR46
PC45
10_0402_5%
1 2
1 2
1U_0603_6.3V6M
0_0603_5%~D
PR52
12.7K_0402_1%
1 2
+3.3V_RUN
PR61
100K_0402_1%~D
750K_0402_1%~D
Create new P/N
PR44
1 2
12
PC46
1000P_0402_50V7K~D
12
PR50
12
PC54
82P_0402_50V8J
12
PR48
5@
499K_0402_1%
1 2
PC48
0.1U_0603_25V7K~D
12
PR53
10K_0402_1%~D 5@
1 2
12
PR55
16.5K_0402_1%
12
Use PR55 and P57 for
Voltage Margining.
PR57
15K_0402_1%~D
GNDA_DC2B
12
12
PC38
2200P_0402_50V7K~D
12
PC39
PC40
10U_1206_25V6M~D
0.1U_0603_25V7K~D
1.05V +/- 5%
Thermal Design Current: 3.36A
Place these CAPs
close to FETs
PQ13
FDS6994S_SO8~D
PR139
0_0402_5%~D@
1 2
5
6
7
8
4
D1
G1
3
S1
D1
2
G2
D2
1
D2
S2
3.3uH_PCMC063T-3R3MN_6A_20%
Maximum Current:4.8A
MIN_OCP:5.2A
PL10
12
D
+1.05V_VCCP_P
1
12
+
PC53
PC51
2
1U_0603_10V6K~D@
330U_D2E_2.5VM_R9
1.05V_RUN_PWRGD <43>
BOM
Structure Description
---------------------------------------------- @ Do Not Populate
4@ Populate for Semtech - SC483 Only
5@ Populate for Ti - TPS51483 Only
4 4
Ref Des SC483 TPS52483
-------------------------------- PR56 30.0K 15.0K
PR58 15.0K 15.0K
PR55 16.5K 11.8K
PR57 15.0K 29.4K
A
GNDA_DC2B
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.5VRUNP /+VCCP_1P05VP
LA-3741P
D
48 53Friday, January 26, 2007
of
0.1
Page 49
5
D D
+PWR_SRC
.9 Volt +/- 5%
Design Current:1.05A
Maximum current:1.5A
+0.9V_DDR_VTTP
+DDR_PWR_SRC
C C
B B
PJP10
@
PAD-OPEN 4x4m
+1.8V_SUSP
1 2
+1.8V_SUSP
PR67
1M_0402_5%~D
PC68
1000P_0402_50V7K~D
GNDA_DDR
+1.8V_SUS
1 2
1 2
V_DDR_MCH_REF<10,15,16,17>
<GMCH, DDR>
PR73
0_0402_5%~D
@
FBM-L11-453215-900LMAT_1812~D
12
GNDA_DDR
PJP9
@
1 2
PAD-OPE N 4x4m
PL11
1 2
4
PC63
PR71
10_0402_1%~D
1 2
12
PC72
1U_0603_10V6K~D
GNDA_DDR
3
NOTE: Component Values Shown for SEMTECH SC480 ONLY.
For Texas Instruments TPS51116, Please USE Reference BOM.
+DDR_PWR_SRC
Place these CAPs
1
2
10U_0805_6.3V5K~D
+1.8V_SUSP
PC64
10U_0805_6.3V5K~D
GNDA_DDR
+5V_SUS
+1.8V_SUSP
+5V_SUS
1
2
PR72
PC65
@
10_0402_1%~D
10U_0805_6.3V5K~D
1 2
RB751V-40_SOD323~D
1
PC66
2
1U_0603_10V6K~D
12
PC71
1U_0603_10V6K~D
GNDA_DDR
PR75
0_0402_5%~D
1 2
PD13
2 1
PR65
0_0603_5%~D
12
23
24
VTT
1
VTTIN
PGND2
2
VTTS
SC480ITSTR_MLPQ24~D
3
VSSA
TPS51116
4
20 QFN 4 X 4
TON
5
REF
6
VCCA
NC7VTTEN10FB
VDDQS
8
PR74
100_0402_5%~D
1 2
12
PC73
0.1U_0402_10V7K~D
GNDA_DDR
NOTE: For Test purposes only
close to FETs
12
PC59
12
0.1U_0603_25V7K~D
22
21
20
DH
BST
PU3
9
11
@
LX
PC119
19
PGND1
PGND1
VDDP
VDDP
18P_0402_50V8J
DL
PGD
PAD
NC12EN/PSV
ILIM
GNDA_DDR
+1.8V_SUSP
12
GNDA_DDR
18
17
16
15
14
13
25
PQ14
FDS6994S_SO8~D
5
D1
G1
6
S1
D1
7
G2
D2
8
D2
S2
PAD
12
PR76
27.4K_0603_1%~D
@
12
PR77
17.4K_0603_1%~D
@
PC56
4
3
2
1
PR66
12.4K_0402_1%~D
PR68
10K_0402_1%~D
@
12
PC69
1U_0603_10V6K~D
GNDA_DDR
@
Create new P/N
2200P_0402_50V7K~D
12
12
12
12
12
PC57
PC58
PC132
0.1U_0603_25V7K~D
10U_1206_25V6M~D
PL12
3.3uH_PCMC063T-3R3MN_6A_20%
12
12
PC67
1U_0603_10V6K~D
PR69
@
0_0402_5%~D
1 2
2
12
10U_1206_25V6M~D @
1
2
PC133
220U_D2_4VM~D
12
PC70
PR70
1U_0603_10V6K~D
100K_0402_1%~D
1.8 Volt +/- 5%
Design Current:3.5A
Maximum current:4.9A
MIN_OCP:5A
+1.8V_SUSP
1
12
+
+
PC62
PC60
2
0.1U_0402_10V7K~D
220U_D2_4VM~D
+5V_SUS
12
SUSPW ROK_1P 8V <43>
SUSPWROK_5V <47>
RUN_ON <19,40,42,43,4 7,48>
<5V_3V regulator>
<GMCH>
<EC>
1
PJP11
+0.9V_DDR_VTTP
A A
@
1 2
PAD-OPEN 43X79
5
+0.9V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
+1.8VSUSP/ +0.9 V _ DDR_VT
Size Doc u m en t N u m be r Re v
Date: Sheet
LA-3741P
49 53Friday, J anu ary 26, 2007
1
of
0.1
Page 50
8
7
6
5
4
3
2
1
IMVP-6 solution for Yonah ULV: 1-phase/9A
H H
12
NOTE
PR114
+5V_RUN
12
PC75
PU4
4.7U_0805_10V6K
1
2
3
4
5
ADP3419JRM_MSOP-10
Single Core
(YONAH ULV)
Dual Core
(YONAH ULV)
Dual Core
(MEROM ULV)
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
PR79
7.32K_0603_1%
@
12
RUNPWROK<39,40,43>
GNDA_CORE
PC87
27P_0402_50V8K
1 2
PR101
DPRSLPVR<24>
PR81
0_0402_5%~D
@
12
PH1
GNDA_CORE
100K_0603_5%_TH11-4H104FT
@
PR99
0_0402_5%~D
PC85
4700P_0402_25V7K
1 2
PR134
0_0603_5%~D
H_DPRSTP#<7,23>
GNDA_CORE
G G
Thermistor PH1 should be placed
close to the hot spot of the VR
F F
E E
D D
12
C C
B B
A A
+3.3V_RUN
12
12
PR89
PR90
1.91K_0402_1%~D
IMVP_PWRGD<24,43>
CLK_ENABLE#<6>
GNDA_CORE
PR100
1K_0402_1%
PR103
0_0402_5%~D
12
NOTE:PR111 is reversed for loop
gain measurement purpose
1 2
1 2
1.91K_0402_1%~D
PC84
1000P_0402_50V7K~D
1 2
PC86
100P_0402_50V8K
12
PC88
820P_0402_25V8K
12
1 2
1 2
@ 470P_0402_50V7K
PC90
@ 470P_0402_50V7K
390P_0402_50V7K
GNDA_COREGNDA_CORE
VCCSense <8>
VSSSense <8>
+VCC_CORE
8
10K_0603_0.1%~D
@20K_0603_1%~D
12
PC89
0.015U_0402_16V7K
PR107
0_0402_5%~D
PR113
100_0402_5%~D@
PR115
100_0402_5%~D@
NOTE: ( Connection VCORE output Cap GND)
De-populate PR113 and PR115 when CPU is present
H_PSI#<8>
12
VID6<8>
VID5<8>
VID4<8>
VID3<8>
VID2<8>
VID1<8>
VID0<8>
12
499_0402_1%
1 2
12
PC81
0.01U_0402_25V7K~D
@
GNDA_CORE
PR91 0_0402_5%~D
1 2
PR92 0_0402_5%~D
1 2
PR98 0_0402_5%~D
PU5
1
EN
2
PWRGD
3
PGDELAY
4
CLKEN
5
FBRTN
6
FB
7
COMP
8
SS
9
STSET
10
DPRSLP
PR141
GNDA_CORE
GNDA_CORE
7
GNDA_CORE
@
1 2
PR104
1 2
309K_0402_1%
@ 215K_0402_1%
PC94
GNDA_CORE
GNDA_CORE
0_0402_5%~D
ILIMIT11RRPM
1000P_0402_50V7K~D
+5V_RUN
12
PR82
10_0603_5%
12
PC82
1U_0805_25V4Z~D
PR88
12
12
12
PR940_0402_5%~D
PR950_0402_5%~D12PR960_0402_5%~D
PR930_0402_5%~D
39
ADP3207JCP-RL_LFCSP -40
RT14RAMPADJ15LLSET16CSREF17CSSUM18CSCOMP
VRPM
13
12
PR105
1 2
1 2
ADP3207_RAMPADJ
160K_0402_1%~D
PR106
392K_0402_1%
12
1 2
PR110 280K_0402_1%
12
12
PC95
PR112 0_0402_5%~D
1000P_0402_50V7K~D
+PWR_SRC
PC96
1000P_0402_50V7K~D
GNDA_CORE
RUNPWROK<39,40,43>
PR87
0_0402_5%~D
1 2
12
12
PR150
0_0402_5%~D
PR970_0402_5%~D
@
1 2
GNDA_CORE
32
33
31
PSI
VCC
VID634VID535VID436VID337VID238VID040VID1
DPRSTP
TTSENSE
PWM1
PWM2
PWM3
GND
20
19
GNDA_CORE
ADP3207_CSSUM
ADP3207_CSREF
VRTT
DCM
ADP3207_TTSENSE
30
ADP3207_VRTT
29
28
27
OD
26
25
24
PR102 0_0402_5%~D
23
SW1
22
SW2
21
SW3
PR108
1 2
12K_0402_1%
IMVP6_PROCHOT# <39>
13
D
2
G
PQ17
S
2N7002_SOT23~D@
ADP3207_#DCM
ADP3207_PWM1
PWM2, PWM3 pull high
12
@5.76K_0402_1%~D
2.37K_0402_1%~D
12
6
5
PD14
IN
SD#
DRVLSD#
CROWBAR
VCC
RB751V-40_SOD323~D
AD3419_BST1
12
12
PC76
DRVH
DRVL
PR80
10
BST
9
8
SW
7
GND
6
1 2
0_0603_5%~D
0.33U_0603_10V7K
AD3419_DRVH1
AD3419_DRVL1
PQ15
AD3419_SW1
IRF7821_SO8~D
1. Choke: PL14 is 0.88u H
2. MOS: PQ27
3 .PR104 is 309K.(OCP:14A)
4. PR114 is 2.37K.(Load Line: -5.1m)
5. PR101 is 10K.
6. PR88 is 820P ; 8. STUFF PC80
7. PR90 is 390P.
1. Choke: PL14 is 0.45u H
2. MOS: PQ27.
3. PR104 is 215K.(OCP:20A)
4. PR114 is 5.76K.(Load Line: -2.1m)
5. PR101 is 20K.
6. PR88 is 470P ; 8. NO-STUFF PC80
7. PR90 is 470P.
1. Choke: PL14 is 0.45u H
2. MOS: PQ16 and PQ27
3. PR104 is 215K.(OCP:20A)
4. PR114 is 5.76K.(Load Line: -2.1m)
5. PR101 is 20K. ;8. NO-STUFF PC80
6. PR88 is 470P
7. PR90 is 470P.
4
3
578
3 6
241
578
9
3 6
241
Rdson_typ
4.8mohms
PQ16
PC77
+CPU_PWR_SRC
12
1000P_0402_50V7K~D
IRF7832_SO8~D
12
12
PC80
PC79
PC78
0.1U_0805_25V7K~D
10U_1206_25V6M~D
@ 0.45U_MPC1040LR45_27A_20%~D
0.88UH_MPC1040LR88_17A_20%~D
578
9
PQ27
@
FDS7088SN3_SO8~D
3 6
241
@
@
12
10U_1206_25V6M~D
PR164
2.4_1206_5%
PC148
1500P_0603_50V7K
PC137
15U_D2_25M_R90~D
1 2
1 2
12
2
+PWR_SRC
1
+
2
PR85
PL14
0.001_2512_1%~D
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc u m en t N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
+VCORE
LA-3741P
PL13
FBMA-L11-321611-800LMA40T
+VCC_CORE
4
3
ADP3207_CSREF
50 53Friday, January 26, 2007
1
12
0.1
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Page 51
5
4
3
2
1
+DC_IN discharge path
PR119
MAX8731_LDO
PR130
12
PC116
PQ19
SI4835BDY_SO8~D
8
7
5
12
GNDA_CHGR
12
4.7K_0402_5%~D
12
12
PC112
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12
PR145
301K_0402_1%~D
12
PR147
56.2K_0402_1%
12
PR148
27.4K_0402_1%
4
1
2
36
4
PR120
100K_0402_1%~D
PC98
1U_0805_25V4Z~D
MAX8731_ACIN
MAX8731_ACOK
MAX8731_IINP
MAX8731_CCV
MAX8731_CCI
MAX8731_CCS
12
PC113
PC114
0.01U_0402_25V7K~D
Need modify
12
PC129
0.01U_0402_25V8K
12
12
MAX8731_REF
12
PC117
1U_0603_10V6K~D
0.1U_0402_10V7K~D
GNDA_CHGR
D D
+DC_IN_SS
12
PC97
10U_1206_25V6M~D
PR121
1 2
365K_0402_1%~D
C C
B B
Battery Type:
4cell: Charging Voltage=17.325V;Charging Current =1.6A
6cell: Charging Voltage=12.975V;Charging Current =3.15A
9cell:Charging Voltage=12.975V;Charging Current =3.15A
A A
PR124
49.9K_0402_1%~D
PC104
0.01U_0402_25V7K~D
PBAT_SMBCLK<40,46>
PBAT_SMBDAT<40,46>
GND
12
12
5
ACAV_IN
GNDA_CHGR
PR131
0_0603_5%~D
MAX8731_IINP
RHU002N06_SOT323
GNDA_CHGR
12
PQ21
2
G
PR122
15.8K_0402_1%~D
ACAV_IN<18,40>
+5V_ALW
PC106
0.1U_0402_10V7K~D
GNDA_CHGR
PR146
0_0402_5%
1 2
ADAPT_TRIP_SEL<39>
12
13
D
S
ACAV_IN
12
12
PC126
0.01U_0402_25V8K
12
PR117
10K_0402_1%~D
13
D
2
G
S
PR123
10K_0402_1%~D
1 2
PR126
0_0402_5%~D
1 2
12
PC115
PR132
10K_0402_1%~D
MAX8731_REF
12
PR154
154K_0402_1%@
PQ20
RHU002N06_SOT323
10K_0402_1%~D
0.1U_0402_10V7K~D
Smart Charger
N657586
PC139
@
0.01U_0402_50V7K~D
GNDA_CHGR
GNDA_CHGR
PU6
22
DCIN
2
ACIN
13
ACOK
11
VDD
10
SCL
9
SDA
14
BATSEL
8
IINP
6
CCV
5
CCI
4
CCS
3
REF
7
DAC
12
GND
MAX8731_DAC
12
12
PC127
PC128
100P_0402_50V8J
PR116
0.01_2512_1%~D
4
3
12
MAX8731_CSSP
1
28
GND
CSSP
MAX8731_TQFN28~D
2
3
12
100P_0402_50V8J
+5V_ALW
+PWR_SRC
PL15
1
2
12
PC140
@
0.01U_0402_50V7K~D
GNDA_CHGR
MAX8731_CSSN
27
MAX8731_VCC
26
VCC
CSSN
BST
LDO
DHI
DLO
PGND
CSIP
CSIN
FBSA
FBSB
4
G
IN-
O
IN+
P
8
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
25
MAX8731_LDO
21
MAX8731_DHI
24
MAX8731_LX
23
LX
20
19
18
17
15
16
PC135
@
0.01U_0603_25V7M~D
GNDA_CHGR
PR142
4.32M_0402_1%
1 2
PU9A
LM393DR_SO8~D
1
12
PC130
100P_0402_50V8J
PR125
0_0603_5%~D
1 2
MAX8731_DLO
12
PC131
0.01U_0402_25V8K
3
FBM-L11-453215-900LMAT_1812~D
MAX8731_BSTB
12
PC105
PD15
<BOM Structure>
0.1U_0603_25V7K~D
RB751V-40_SOD323~D
1 2
100_0402_5%~D
PR155
12
1 2
PC121
2200P_0402_50V7K~D
PC99
1U_0603_10V6K~D
1 2
PR127
PC107
1 2
33_0603_1%~D
1U_0603_10V6K~D
2 1
1 2
1_0603_5%~D
1 2
1 2
PC111
220P_0603_50V8J~D
MAX8731_CSIP
+VCHGR
MAX8731_CSIN
+5V_ALW +3.3V_ALW
12
PR143
100K_0402_1%~D
12
PC125
10P_0402_50V8J~D
<BOM Structure>
PR128
12
PC122
0.1U_0603_25V7M~D
GNDA_CHGR
<BOM Structure>
12
PR144
100K_0402_1%~D
13
D
2
G
S
PQ26
RHU002N06_SOT323
12
PC138
+CHRG_IN
PQ22
IRF7821_SO8~D
1 2
3300P_0402_50V7K~D
PQ23
SI4810BDY_SO8~D
PR149
1 2
100K_0402_1%~D
＠
Place these CAPs
close to FETs
578
3 6
241
578
3 6
241
5
6
SI4835BDY_SO8~D
1
2
3 6
PR118
12
PC100
2200P_0402_50V7K~D
PL16
5.6U_HMU1356-5R6_8.8A_20%~D
2 1
PR163
@
1 2
2.4_1206_5%
12
PC147
@
1500P_0603_50V7K
+5V_ALW
8
P
IN+
7
O
IN-
G
PU9B
LM393DR_SO8~D
4
ADAPT_OC <39>
2
PQ18
8
4
12
0.1U_0603_25V7M~D
12
PC102
10U_1206_25V6M~D
+VCHGR_L
7
5
12
12
PC103
10U_1206_25V6M~D
PR129
0.01_2512_1%~D
4
3
+VCHGR
+DC_IN_SS
1
2
12
PC108
0.1U_0805_50V7M~D
470K_0402_5%~D
PC101
Maximum Battery Charge current = 3.15A
when system off, S3, S4.
Table1
PR142 PR145 PR148 PR154
4.32M 301K 56.2K 27.4K NA
976K 49.9K 13.3K 9.31K 38.3K
976K 13.3K
ADAPTER(W)
65
90
130
150
TRIP CURRENT
(A)
3.17
4.43
6.44
7.44
DELL CONFIDENTIAL/PROPRIETARY
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Charger
LA-3741P
+5V_ALW
PD19
PR158
PC109
33.2K
20K649K
21
1SS355_SOD323~D
1K_0603_1%~D
1 2
12
10U_1206_25V6M~D
+VCHGR
12
12
PC110
PC146
10U_1206_25V6M~D
10U_1206_25V6M~D
Need double confirm
PR147
15K
10K
13K
1
51 53Friday, January 26, 2007
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66.1K
of
0.1
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5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
1
2
16,17
17
3
4 29,40 LOM 01/11/07' Dell Support ASF2.0
DDR On
board
DDR On
board
01/09/07' Compal Add Termination resistors Add R660 and R661(56_0402)
ECE501839 01/09/07' Compal Setting board ID from A00(Crockett) to X00(Carson) Pop R475 and depop R471
Owner
MEC5004 pin55(SGPIO45) connect to BCM5752 ball H9 (GPIO0), net
name is LOM_SMB_ALERT# ; Add R662(4.7K ohm)pull up resistor to
+3.3V_LAN
5 50 SPI ROM 01/23/07' Dell Add code to support different version of WLAN. Change U50 from M25P16-VMW6TP(1M) to M25P16-VMW6TP(2M) 0.1
6 37 IrDA 01/23/07' Dell For cost saving Depop U40, R433,R435,R436,C526~C528 0.1
C C
7 28 01/23/07' Dell For best audio performance(Vista) Change L28~L31 to BLM18BD601SN1D 0.1
8 33 USB 01/24/07' Dell For meet TUV's USB requirement Reserved F2,F3(depop),JUMP1 and JUMP3. Short Jump for X00
build.
Solution Description Rev.Page# Title
0.101/09/07' Compal Update Memory symbol form 64M*8 to 128M*8 Update U4~U11 Symbol
0.1
0.1
0.1
0.1
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Changed-List History 1
Size Document Number Rev
Date: Sheet
LA-3741P
52 53Friday, January 26, 2007
1
of
0.1
Page 53
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
1
page 51 1/09/07 Dell
2
page 51
3
page 50
C C
1/26/07 Dell
1/26/07
Owner
Dell
M08 charger update for potential audible noise. Add PC146 10uf/25V X5R C ap on charger output Cap.
M08 charger update for EMC.
M08 Vcore update for EMC. Add PC148 and PR164 from phase node to GND
Add PC147 and PR163 from phase node to GND
Solution Description Rev.Page# Title
X00
X00
X00
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Changed-List History 2
Size Document Number Rev
Date: Sheet
LA-3741P
53 53Friday, January 26, 2007
1
of
0.1
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