Dell AIO 2320 Schematic

5

IPPSB-FA

PAGE

D D

C C

B B

01

03

04~09

1002DDR3 CHANNEL A_G/F 11 12 13 PLTRST_CPU# & SMbus

14 15~16 17~25 27~28 29~30 31~32 33~35

36 37~38

39

40

41

42 43~44

45

46

47

48

49

50

51

52

53

54

55

56

57

58 59~61

62 63~64

65 66~67

68

69 70~71

72

73

74

75

76

77 MXM.NVVDD

78 Card Reader RTS5139-GR

TITLE

BLOCK DIAGRAM POWER FLOW POWER SEQUENCE CPU_LGA1155_DDR3_A 1-6

DDR3 CHANNEL B_G/F DDR3 TERMINATION A&B

Converter Controllor LVDS&AV CONN INTEL_PCH 1-9 LAN CODEC&CONN AMP&SWITCH USB&HUB&BT HPD_DET MINI CARD(WL&TVT&DMC) Misc. conn&Touch&Wcam&RTC FAN PWR LED & Button* IR LEDs EC 8519 SM BUS & SPI ROM SCREW HOLE UVP, OVP & +19VSB LOAD_SWITCH +3P3VSB&+5VSB +1P5V_DUAL & +1P2V Current Monitor +12V & +1P8V +1P05V_CPUIO&+0P925V_SA POWER_PROTECT +1P05V_CPUIO CAP +VTT_DDR +V_AXG DRIVER +VCORE CONTROLLER +VCORE CAP +1P05V&+1P05V_PCH CPU&PCH XDP DEBUG CONNECTOR VGA CONN GPU DDR3 VGA-N12P_STRAPPING+EEPROM MXM.VGA-N12P_Xtal/Thermal GPU HDMI(DMC&AV) GPU CTRL GPU.VGA_N12P_PCI-E I/F GPU PCI-E_LVDS_VGA MXM.GPU Discharge GPU_POWER&GND

EDP CH751179

4

LVDSpanel

Nvidia N12P/N12M

HDMI

LVDS

AV Board

Option

EDID rom

HDMI

Real USB 4 rear PORTS

Side USB 2 side PORTS

webcam + Dmic

PS8615

Touch

EDID rom

Card reader

Realtek/RTS5139

WLAN SLOT + BT

Realtek 8111E

GBE

IR learning/receiver /blaster

XDP

Debug port

3

100MHz

PCI-E BUS

USB 2.0

480Mb/s

USB 2.0

480Mb/s

USB 2.0

480Mb/s

USB 2.0

480Mb/s

USB 2.0

480Mb/s

USB 2.0

480Mb/s

PCIE BUS

100MHz

eDP

PCIE BUS

100MHz

Intel Processor

Sandy Bridge

LGA-1155 Pin Socket

FDI LINK

,17(/

Cougar Point

PCH

H61

942 Pin

27mm X 27mm

33MHz

LPC BUS

45W/65W

DMI

LPC BUS

33MHz

EC

IT8519E

Channel A

Channel B

3Gbps

SATA BUS

SPI

HDA

PCIE BUS

100MHz

2

Dual-Channel Memory x 2 Slots

DDR3 1066/1333

SATA0

SATA1

SPI FLASH

AUDIO CODEC ALC269Q-VA6

Mic

MINI SOLT(TVT)

Line-out

32MB

Option

AV Board

Audio Switch

1

AMP

TPA3110D2

SPK

A A

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

IPPSB-FA

A2

Date: Sheet

5

4

3

2

Date: Sheet

1

Title :

Engineer:

%/29.',$*5$0

Jerry Chung

179Tuesday, April 26, 2011

of

Rev

1.01

5

Adapter

+19VA

+19VA_VIN

D D

OVP/UVP

+19VSB_R

INA199A3

Current Monitor

+19VSB

4

+1P05V_CPUIO

SUSB#_PWR

+1P05V_PCH_PWRGD

+5V_DUAL

3

NCP6121S52MNR2G IRFH7914PBF*1+NTMFS4839NHT1G*2 (3-phase)

IRFH7914PBF*2+NTMFS4839NHT1G*2 (1-phase)

RT8204LGQW IRF8707PBF*1+IRF8707PBF*1

RT8204LGQW IRF8707PBF*1+IRFH7914*2

2

18.3A

+1P05V_CPUIO_PWRGD

22.66A

IPDH6N03LAG

RT9045GSP

1

+VCORE

S0/S1

75A

+V_AXG

S0/S1

35A

+12V

S0/S1

3.3A

+1P05V_CPUIO

9.5A

+0P925V_SA

8.8A

+1P5V_DUAL

13.75A

+VTTDDR

1.5A

S0/S1

S0/S1/S3

SUSB#_PWR

IRF8707PBF

C C

IRF8707PBF

+1P05V

10.03A

NVVDD_PWRGD

RT8204LGQW IRF8707PBF*1+IRF8707PBF*2

+1P5V

1.5A

+1P5V_GPU

5.91A

+1P05_PCH

6.2A

+1P05V

S0/S1

3.83A

+5V

6.5A

32:(5)/2:

XXXX-XX

279Tuesday, April 26, 2011

S0/S1

S0 ~ S5

S0/S1

S0/S1/S3

S0 ~ S5

S0/S1/S3

S0/S1

of

Rev

1.01

31.56A

+3P3V_GPU

TPS51125ARGER IRFH7914PBF*1+NTMFS4839NHT1G*1

RT8208AGQW IRFH7914PBF*1+NTMFS4839NHT1G*2

IPDH6N03LAG

B B

+1P5V_GPU

NVVDD

31.56A

+3P3VSB16.63A

5.67A

+1P8V_FSR

2.5A +1P8V

0.3A

SUSB#_PWR

IRF8707PBF

SUSB#_PWR

IRF8707PBF

SUSC#_PWR

IRFH7914PBF*1+NTMFS4839NHT1G*1

IRF8707PBF*2

A A

Power Rail

SPDT Linear

Control signal

5

Switching

4

3

SUSC#_PWR

SUSB#_PWR

IRF8707PBF

2

0413

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

,336%)$

+3P3V

4.43A

+3P3V_GPU

1.38A

+3P3V_DUAL

2.35A

+5VSB18.07A

1.57A

+5V_DUAL

10A

Title :

Engineer:

1

5

4

3

2

1

+19VSB

TPS51125

+5VA +3VA

D D

+3VA_EC

ENTRIP1

TPS51125

ENTRIP2

+3P3VSB

+3VA_EC

1

VSUS_ON

3

SUS_PWRGD

4

+5VSB

SUSC#_PWR

C C

+12VSUS

UMC4N

+5V_DUAL

+5VO

5903 NMOS

+3P3V_DUAL

+3VO

5903 NMOS

+1P5V_DUAL

8202 LIN REG.

+VTT_DDR

+1P1VSB_USB

RT9045

AND

+1P5V_DUAL_PWRGD

SUSB#_PWR

1Kohm

11

ALL_SYSTEM_PWRGD

1Kohm

Reset circuit

SUSC_EC#

9

SUSB_EC#

10

1-1

WRST#

PWR_SW#

2

(& ,7(

ALL_SYSTEM_PWRGD

PM_PWRBTN#

6

PM_RSMRST#

5

DPWROK

1-2

14

PWROK

PCH_PWROK

Power Button

PWRBTN#

RSMRST#

DPWROK

&RXJDU 3RLQW

APWROK PWROK

SYS_PWROK

DRAMPWROK

15

7

8

,QWHO

3&+

16

SLP_S4#

SLP_S3#

SLP_S4#

PLTRST#

PROCPWRGD

CPUPWRGD

LAN XDP EC etc.

PLTRST#

3.3V TO 1.1V SHIFTER

DRAM_PWROK

+12V

+12VSUS

+5VO

+3VO

+1.8V

4502

5903 NMOS

2304 NMOS

9024 LIN REG.

9026 LDO

+1P05V_PCH_PWRGD

+1P05V_CPUIO_PWRGD

VR_ON

9FRUH

PGOOD

4

12

VRM_PWRGD

13

CPU_VRON

17

SYS_PWROK

SM_DRAMPWROK

UNCOREPWRGOOD

RESET#

PLTRST_CPU#

18

6DQG\ %ULGJH

0413

Title :

32:(56(48(1&(

Title :

32:(56(48(1&(

Title :

32:(56(48(1&(

Mike Yen

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

3

2

Date: Sheet

,336%)$

Engineer:

Mike Yen

379Tuesday, April 26, 2011

1

379Tuesday, April 26, 2011

Rev

1.01

of

B B

+5V

+3P3V

+1P8V_SFR

+1P5V

+10P5V_PCH

+10P5V_CPUIO

+0P925V_SA

A A

+V_AXG

5

M_CHA_DQ[0..63][10]

M_CHA_DQS0[10] M_CHA_DQS0#[10]

D D

M_CHA_DQS1[10] M_CHA_DQS1#[10]

M_CHA_DQS2[10] M_CHA_DQS2#[10]

C C

B B

A A

5

M_CHA_DQS3[10] M_CHA_DQS3#[10]

M_CHA_DQS4[10] M_CHA_DQS4#[10]

M_CHA_DQS5[10] M_CHA_DQS5#[10]

M_CHA_DQS6[10] M_CHA_DQS6#[10]

M_CHA_DQS7[10] M_CHA_DQS7#[10]

4

XU1A

AW4

AW3

AW5

AW8

AW7 AW9

AV37 AV36

AU35

AW37

AU39 AU36

AW35

AY36 AU38 AU37

AP38 AP39

AR40 AR37 AN38 AN37 AR39 AR38 AN39 AN40

AK38 AK39

AL40 AL37 AJ38 AJ37 AL39 AL38 AJ39 AJ40

AF38 AF39

AG40 AG37 AE38 AE37 AG39 AG38 AE39 AE40

AK3 AK2

AJ3 AJ4 AL3 AL4 AJ2 AJ1 AL2 AL1

AP3 AP2

AN1 AN4 AR3 AR4 AN2 AN3 AR2 AR1

AV4

AV2

AV5

AU2 AU3 AU5 AY5

AV8

AY7 AU7 AV9 AU9 AV7

AY9

XU1A

SA_DQS_0 SA_DQS#_0

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7

SA_DQS_1 SA_DQS#_1

SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQS_2 SA_DQS#_2

SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23

SA_DQS_3 SA_DQS#_3

SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31

SA_DQS_4 SA_DQS#_4

SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39

SA_DQS_5 SA_DQS#_5

SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47

SA_DQS_6 SA_DQS#_6

SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55

SA_DQS_7 SA_DQS#_7

SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SOCKET_1155P

SOCKET_1155P I

I

M_CHA_DQS0 M_CHA_DQS0#

M_CHA_DQ0 M_CHA_DQ1 M_CHA_DQ2 M_CHA_DQ3 M_CHA_DQ4 M_CHA_DQ5 M_CHA_DQ6 M_CHA_DQ7

M_CHA_DQS1 M_CHA_DQS1#

M_CHA_DQ8 M_CHA_DQ9 M_CHA_DQ10 M_CHA_DQ11 M_CHA_DQ12 M_CHA_DQ13 M_CHA_DQ14 M_CHA_DQ15

M_CHA_DQS2 M_CHA_DQS2#

M_CHA_DQ16 M_CHA_DQ17 M_CHA_DQ18 M_CHA_DQ19 M_CHA_DQ20 M_CHA_DQ21 M_CHA_DQ22 M_CHA_DQ23

M_CHA_DQS3 M_CHA_DQS3#

M_CHA_DQ24 M_CHA_DQ25 M_CHA_DQ26 M_CHA_DQ27 M_CHA_DQ28 M_CHA_DQ29 M_CHA_DQ30 M_CHA_DQ31

M_CHA_DQS4 M_CHA_DQS4#

M_CHA_DQ32 M_CHA_DQ33 M_CHA_DQ34 M_CHA_DQ35 M_CHA_DQ36 M_CHA_DQ37 M_CHA_DQ38 M_CHA_DQ39

M_CHA_DQS5 M_CHA_DQS5#

M_CHA_DQ40 M_CHA_DQ41 M_CHA_DQ42 M_CHA_DQ43 M_CHA_DQ44 M_CHA_DQ45 M_CHA_DQ46 M_CHA_DQ47

M_CHA_DQS6 M_CHA_DQS6#

M_CHA_DQ48 M_CHA_DQ49 M_CHA_DQ50 M_CHA_DQ51 M_CHA_DQ52 M_CHA_DQ53 M_CHA_DQ54 M_CHA_DQ55

M_CHA_DQS7 M_CHA_DQS7#

M_CHA_DQ56 M_CHA_DQ57 M_CHA_DQ58 M_CHA_DQ59 M_CHA_DQ60 M_CHA_DQ61 M_CHA_DQ62 M_CHA_DQ63

4

3

SM_DRAMRST#

DDR3_A

3

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_WE# SA_CAS# SA_RAS#

SA_BS_0 SA_BS_1 SA_BS_2

SA_CS#_0 SA_CS#_1 SA_CS#_2 SA_CS#_3

SA_CKE_0 SA_CKE_1 SA_CKE_2 SA_CKE_3

SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3

SA_CK_0

SA_CK#_0

SA_CK_1

SA_CK#_1

SA_CK_2

SA_CK#_2

SA_CK_3

SA_CK#_3

SA_DQS_8

SA_DQS#_8

SA_ECC_CB_0 SA_ECC_CB_1 SA_ECC_CB_2 SA_ECC_CB_3 SA_ECC_CB_4 SA_ECC_CB_5 SA_ECC_CB_6 SA_ECC_CB_7

M_CHA_MAA0

AV27

M_CHA_MAA1

AY24

M_CHA_MAA2

AW24

M_CHA_MAA3

AW23

M_CHA_MAA4

AV23

M_CHA_MAA5

AT24

M_CHA_MAA6

AT23

M_CHA_MAA7

AU22

M_CHA_MAA8

AV22

M_CHA_MAA9

AT22

M_CHA_MAA10

AV28

M_CHA_MAA11

AU21

M_CHA_MAA12

AT21

M_CHA_MAA13

AW32

M_CHA_MAA14

AU20

M_CHA_MAA15

AT20

AW29 AV30 AU28

AY29 AW28 AV20

AU29 AV32 AW30 AU33

AV19 AT19 AU18 AV18

AV31 AU32 AU30 AW33

AY25 AW25 AU24 AU25 AW27 AY27 AV26 AW26

93

HR1

SM_DRAMRST#

AW18

AV13 AV12

AU12

127(

AU14 AW13

Sugar Bay platform does not support ECC

AY13 AU13 AU11 AY12 AW12

HR1

1 2

0

2

M_CHA_MAA[0..15] [10]

M_CHA_WE# [10] M_CHA_CAS# [10] M_CHA_RAS# [10]

M_CHA_BA0 [10] M_CHA_BA1 [10] M_CHA_BA2 [10]

M_CHA_CS#0 [10] M_CHA_CS#1 [10]

M_CHA_CKE0 [10] M_CHA_CKE1 [10]

M_CHA_ODT0 [10] M_CHA_ODT1 [10]

M_CHA_CLK0 [10] M_CHA_CLK0# [10] M_CHA_CLK1 [10] M_CHA_CLK1# [10]

12

1,

HC1

HC1 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

GND

2

1

DDR3_DRAMRST# [10,11]

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

Engineer:

,336%)$

1

''5B$

Mike Yen

of

479Wednesday, April 27, 2011

Rev

1.01

5

M_CHB_DQ[0..63][11]

M_CHB_DQS0[11] M_CHB_DQS0#[11]

D D

M_CHB_DQS1[11] M_CHB_DQS1#[11]

M_CHB_DQS2[11] M_CHB_DQS2#[11]

C C

M_CHB_DQS3[11] M_CHB_DQS3#[11]

M_CHB_DQS4[11] M_CHB_DQS4#[11]

B B

A A

5

M_CHB_DQS5[11] M_CHB_DQS5#[11]

M_CHB_DQS6[11] M_CHB_DQS6#[11]

M_CHB_DQS7[11] M_CHB_DQS7#[11]

4

XU1B

M_CHB_DQS0 M_CHB_DQS0#

M_CHB_DQ0 M_CHB_DQ1 M_CHB_DQ2 M_CHB_DQ3 M_CHB_DQ4 M_CHB_DQ5 M_CHB_DQ6 M_CHB_DQ7

M_CHB_DQS1 M_CHB_DQS1#

M_CHB_DQ13 M_CHB_DQ9 M_CHB_DQ11 M_CHB_DQ15 M_CHB_DQ12 M_CHB_DQ8 M_CHB_DQ14 M_CHB_DQ10

M_CHB_DQS2 M_CHB_DQS2#

M_CHB_DQ16 M_CHB_DQ17 M_CHB_DQ18 M_CHB_DQ19 M_CHB_DQ20 M_CHB_DQ21 M_CHB_DQ22 M_CHB_DQ23

M_CHB_DQS3 M_CHB_DQS3#

M_CHB_DQ24 M_CHB_DQ25 M_CHB_DQ26 M_CHB_DQ27 M_CHB_DQ28 M_CHB_DQ29 M_CHB_DQ30 M_CHB_DQ31

M_CHB_DQS4 M_CHB_DQS4#

M_CHB_DQ32 M_CHB_DQ33 M_CHB_DQ34 M_CHB_DQ35 M_CHB_DQ36 M_CHB_DQ37 M_CHB_DQ38 M_CHB_DQ39

M_CHB_DQS5 M_CHB_DQS5#

M_CHB_DQ40 M_CHB_DQ41 M_CHB_DQ42 M_CHB_DQ43 M_CHB_DQ44 M_CHB_DQ45 M_CHB_DQ46 M_CHB_DQ47

M_CHB_DQS6 M_CHB_DQS6#

M_CHB_DQ48 M_CHB_DQ52 M_CHB_DQ55 M_CHB_DQ51 M_CHB_DQ54 M_CHB_DQ49 M_CHB_DQ53 M_CHB_DQ50

M_CHB_DQS7 M_CHB_DQS7#

M_CHB_DQ56 M_CHB_DQ57 M_CHB_DQ58 M_CHB_DQ59 M_CHB_DQ60 M_CHB_DQ61 M_CHB_DQ62 M_CHB_DQ63

4

AM10

AL10

AP10

AR10

AN13 AN12

AM12 AM13

AR13 AP13

AL12

AL13 AR12 AP12

AN29 AN28

AR28 AR29

AL28

AL29 AP28 AP29

AM28 AM29

AP33 AR33

AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34

AL33

AM33

AM32 AM31

AL35

AL32

AM34

AL31

AM35

AL34

AG35 AG34

AH35 AH34 AE34 AE35

AJ35

AJ34 AF33 AF35

AH7 AH6

AG7 AG8

AG5 AG6

AM8 AL8

AL7 AM7

AL6 AM6 AL9 AM9

AR8 AP8

AP7 AR7

AP6 AR6 AP9 AR9

AJ9 AJ8

AJ6 AJ7

SB_DQS_0 SB_DQS#_0

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7

SB_DQS_1 SB_DQS#_1

SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15

SB_DQS_2 SB_DQS#_2

SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQS_3 SB_DQS#_3

SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31

SB_DQS_4 SB_DQS#_4

SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39

SB_DQS_5 SB_DQS#_5

SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47

SB_DQS_6 SB_DQS#_6

SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55

SB_DQS_7 SB_DQS#_7

SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

DDR3_B

SOCKET_1155P

SOCKET_1155P I

I

3

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SA_CK[2]

SA_CK[1]

SA_ODT[2]

SB_BS_0 SB_BS_1 SB_BS_2

SB_CS#_0 SB_CS#_1 SB_CS#_2 SB_CS#_3

SB_CKE_0 SB_CKE_1 SB_CKE_2 SB_CKE_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_CK_0 SB_CK#_0

SB_CK_1 SB_CK#_1

SB_CK_2 SB_CK#_2

SB_CK_3 SB_CK#_3

SB_DQS_8

SB_DQS#_8

SB_ECC_CB_0 SB_ECC_CB_1 SB_ECC_CB_2 SB_ECC_CB_3 SB_ECC_CB_4 SB_ECC_CB_5 SB_ECC_CB_6 SB_ECC_CB_7

3

M_CHB_MAA0

AK24

M_CHB_MAA1

AM20

M_CHB_MAA2

AM19

M_CHB_MAA3

AK18

M_CHB_MAA4

AP19

M_CHB_MAA5

AP18

M_CHB_MAA6

AM18

M_CHB_MAA7

AL18

M_CHB_MAA8

AN18

M_CHB_MAA9

AY17

M_CHB_MAA10

AN23

M_CHB_MAA11

AU17

M_CHB_MAA12

AT18

M_CHB_MAA13

AR26

M_CHB_MAA14

AY16

M_CHB_MAA15

AV16

AR25 AK25 AP24

AP23 AM24 AW17

AN25 AN26 AL25 AT26

AU16 AY15 AW15 AV15

AL26 AP26 AM26 AK26

AL21 AL22 AL20 AK20 AL23 AM22 AP21 AN21

AN16 AN15

AL16

127(

AM16 AP16

Sugar Bay platform does not support ECC

AR16 AL15 AM15 AR15 AP15

2

M_CHB_MAA[0..15] [11]

M_CHB_WE# [11] M_CHB_CAS# [11] M_CHB_RAS# [11]

M_CHB_BA0 [11] M_CHB_BA1 [11] M_CHB_BA2 [11]

M_CHB_CS#0 [11] M_CHB_CS#1 [11]

M_CHB_CKE0 [11] M_CHB_CKE1 [11]

M_CHB_ODT0 [11] M_CHB_ODT1 [11]

M_CHB_CLK0 [11] M_CHB_CLK0# [11] M_CHB_CLK1 [11] M_CHB_CLK1# [11]

2

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

Engineer:

,336%)$

1

''5B%

Mike Yen

of

579Wednesday, April 27, 2011

Rev

1.01

5

4

3

2

1

PEG_RXP[0..15][73]

PEG_RXN[0..15][73]

PEG_RXP0 PEG_TXP0

PEG_RXP0

PEG_RXN0

PEG_RXP1

PEG_RXN1

D D

C C

DMI_RXP0[18] DMI_RXN0[18]

DMI_RXP1[18] DMI_RXN1[18]

DMI_RXP2[18] DMI_RXN2[18]

B B

A A

DMI_RXP3[18] DMI_RXN3[18]

12%20

PEG_RXN1

PEG_RXP2

PEG_RXN2

PEG_RXP3

PEG_RXN3

PEG_RXP4

PEG_RXN4

PEG_RXP5

PEG_RXN5

PEG_RXP6

PEG_RXN6

PEG_RXP7

PEG_RXN7

PEG_RXP8

PEG_RXN8

PEG_RXP9

PEG_RXN9

PEG_RXP10

PEG_RXN10

PEG_RXP11

PEG_RXN11

PEG_RXP12

PEG_RXN12

PEG_RXP13

PEG_RXN13

PEG_RXP14

PEG_RXN14

PEG_RXP15

PEG_RXN15

HT26

1

HT27

1

HT28

1

5

XU1C

B11

PEG_RX_0

B12

PEG_RX#_0

D12

PEG_RX_1

D11

PEG_RX#_1

C10

PEG_RX_2

C9

PEG_RX#_2

E10

PEG_RX_3

E9

PEG_RX#_3

B8

PEG_RX_4

B7

PEG_RX#_4

C6

PEG_RX_5

C5

PEG_RX#_5

A5

PEG_RX_6

A6

PEG_RX#_6

E2

PEG_RX_7

E1

PEG_RX#_7

F4

PEG_RX_8

F3

PEG_RX#_8

G2

PEG_RX_9

G1

PEG_RX#_9

H3

PEG_RX_10

H4

PEG_RX#_10

J1

PEG_RX_11

J2

PEG_RX#_11

K3

PEG_RX_12

K4

PEG_RX#_12

L1

PEG_RX_13

L2

PEG_RX#_13

M3

PEG_RX_14

M4

PEG_RX#_14

N1

PEG_RX_15

N2

PEG_RX#_15

W5

DMI_RX_0

W4

DMI_RX#_0

V3

DMI_RX_1

V4

DMI_RX#_1

Y3

DMI_RX_2

Y4

DMI_RX#_2

AA4

DMI_RX_3

AA5

DMI_RX#_3

P3

PE_RX_0

P4

PE_RX#_0

R2

PE_RX_1

R1

PE_RX#_1

T4

PE_RX_2

T3

PE_RX#_2

U2

PE_RX_3

U1

PE_RX#_3

SOCKET_1155P

SOCKET_1155P I

I

Processor PCI Express* Receive/ Transmit Differential Pair. These signals are available for Workstation only.

PEG

DMI

GEN

PEG_TX_0

PEG_TX#_0

PEG_TX_1

PEG_TX#_1

PEG_TX_2

PEG_TX#_2

PEG_TX_3

PEG_TX#_3

PEG_TX_4

PEG_TX#_4

PEG_TX_5

PEG_TX#_5

PEG_TX_6

PEG_TX#_6

PEG_TX_7

PEG_TX#_7

PEG_TX_8

PEG_TX#_8

PEG_TX_9

PEG_TX#_9

PEG_TX_10

PEG_TX#_10

PEG_TX_11

PEG_TX#_11

PEG_TX_12

PEG_TX#_12

PEG_TX_13

PEG_TX#_13

PEG_TX_14

PEG_TX#_14

PEG_TX_15

PEG_TX#_15

DMI_TX_0

DMI_TX#_0

DMI_TX_1

DMI_TX#_1

DMI_TX_2

DMI_TX#_2

DMI_TX_3

DMI_TX#_3

PEG_ICOMPO

PEG_RCOMPO

PEG_COMPI

PE_TX_0

PE_TX#_0

PE_TX_1

PE_TX#_1

PE_TX_2

PE_TX#_2

PE_TX_3

PE_TX#_3

C13 C14

E14 E13

G14 G13

F12 F11

J14 J13

D8 D7

D3 C3

E6 E5

F8 F7

G10 G9

G5 G6

K7 K8

J5 J6

M8 M7

L6 L5

N5 N6

V7 V6

W7 W8

Y6 Y7

AA7 AA8

B5 C4 B4

P8 P7

T7 T8

R6 R5

U5 U6

4

PEG_TXP0

PEG_TXN0

PEG_TXP1

PEG_TXN1

PEG_TXP2

PEG_TXN2

PEG_TXP3

PEG_TXN3

PEG_TXP4

PEG_TXN4

PEG_TXP5

PEG_TXN5

PEG_TXP6

PEG_TXN6

PEG_TXP7

PEG_TXN7

PEG_TXP8

PEG_TXN8

PEG_TXP9

PEG_TXN9

PEG_TXP10

PEG_TXN10

PEG_TXP11

PEG_TXN11

PEG_TXP12

PEG_TXN12

PEG_TXP13

PEG_TXN13

PEG_TXP14

PEG_TXN14

PEG_TXP15

PEG_TXN15

+1P05V_CPUIO

12

PEG_COMP

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO HR3.2 ROUTE B5 TO HR3.2 AS A SEPERATE 10 MIL TRACE

HT39

1

12%20

DMI_TXP0 [18] DMI_TXN0 [18]

DMI_TXP1 [18] DMI_TXN1 [18]

DMI_TXP2 [18] DMI_TXN2 [18]

DMI_TXP3 [18] DMI_TXN3 [18]

,

HR3

24.9

24.9 1%

1%

PEG_TXP[0..15] [73]

PEG_TXN[0..15] [73]

XU1D

+1P05V_CPUIO

12

,

HR2

24.9

24.9 1%

1%

FDI_COMP

FDI_FSYNC_0[22] FDI_LSYNC_0[22]

FDI_FSYNC_1[22] FDI_LSYNC_1[22]

FDI_IN T[22]

XU1D

AE2

FDI_COMPIO

AE1

FDI_ICOMPO

AC5

FDI_FSYNC_0

AC4

FDI_LSYNC_0

AE5

FDI_FSYNC_1

AE4

FDI_LSYNC_1

AG3

FDI_INT

SOCKET_1155P

SOCKET_1155P I

I

FDI

FDI_TX_0

FDI_TX#_0

FDI_TX_1

FDI_TX#_1

FDI_TX_2

FDI_TX#_2

FDI_TX_3

FDI_TX#_3

FDI_TX_4

FDI_TX#_4

FDI_TX_5

FDI_TX#_5

FDI_TX_6

FDI_TX#_6

FDI_TX_7

FDI_TX#_7

AC8 AC7

AC2 AC3

AD2 AD1

AD4 AD3

AD7 AD6

AE7 AE8

AF3 AF2

AG2 AG1

FDI_TXP0 [22] FDI_TXN0 [22]

FDI_TXP1 [22] FDI_TXN1 [22]

FDI_TXP2 [22] FDI_TXN2 [22]

FDI_TXP3 [22] FDI_TXN3 [22]

FDI_TXP4 [22] FDI_TXN4 [22]

FDI_TXP5 [22] FDI_TXN5 [22]

FDI_TXP6 [22] FDI_TXN6 [22]

FDI_TXP7 [22] FDI_TXN7 [22]

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

3

2

Date: Sheet

Engineer:

,336%)$

1

3&,('0,)',

Mike Yen

of

679Wednesday, April 27, 2011

Rev

1.01

5

CK_100M_DMI[22] CK_100M_DMI#[22]

+1P05V_CPUIO

12

,

HR58

HR58 1K

1K

Description

X16(Default)

2X8

Reserved

X8, X4/X4

CK_100M_CPU_XDP[64] CK_100M_CPU_XDP#[64]

12

1,

HR5

HR5 Do Not Stuff

Do Not Stuff 1%

1%

127(

12

HR6

HR6 110

110 1%

1%

12

CPU_CFG0[64]

D D

VIDSCLK[58] VIDSOUT[58] VIDALERT#[58]

PLTRST_CPU#[13] CPUPWRGD[20,64] DRAM_PWROK[20]

C C

HR21 Do Not Stuff

1 2

1,

PECI_PCH[19]

H_PECI[43]

PROCHOT#[58]

H_THMTRIP#[19,54] PM_SYNC[19]

SKTOCC#[20] PROC_SEL[22]

B B

1,

HR20 0

1 2

93

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

- 1 = Normal operation

- 0 = Lane numbers reversed

CFG[0~15] is IPU

127(

CFG6 CFG5

11

,

10

01

00

H_DDR_VREF

12

,

D3CB17

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

5

+1P5V_DUAL

12

D3R39

D3R39 100

100 1%

1%

A A

12

D3R40

D3R40 100

100 1%

1%

GND GND

Place near CPU

12

,

12

HR14

2.2K

4

127(

+1P5V_DUAL

12

,

1,

HR7

HR4

75

Do Not Stuff

1%

HR11

,

HR70

,

127(

For VR Debug

TBD: CRB 0.7 is NI

+1P05V_CPUIO+1P8V_SFR

12

1,

HR16

HR17

Do Not Stuff

GND

4

12%20

12%20 12%20

12%20

ST29

ST29 ST48

ST48

Place HR57 near CPU 2"~3"

12

,

HR57

HR57 200

200 1%

1%

1 2

44.2

44.2 1%

1%

1 2

120

120 1%

1%

12

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

1 1

H_VIDALERT#

SM_DPWROK

12

1,

HR59

HR59 Do Not Stuff

Do Not Stuff

GNDGND

127(

CRB UN-STUFF

12

1,

,

HR19

HR18

Do Not Stuff

51

H_PECI_R CATERR_R#

H_DDR_VREF

PROC_SEL

HR24Do Not Stuff1,HR24Do Not Stuff

1,

H_CFG1

HR25Do Not Stuff1,HR25Do Not Stuff

1,

H_CFG2

HR27Do Not Stuff1,HR27Do Not Stuff

1,

H_CFG3

HR26Do Not Stuff1,HR26Do Not Stuff

1,

H_CFG4

HR28Do Not Stuff1,HR28Do Not Stuff

1,

H_CFG5

HR29Do Not Stuff1,HR29Do Not Stuff

1,

H_CFG6

HR30Do Not Stuff1,HR30Do Not Stuff

1,

H_CFG7

HR32Do Not Stuff1,HR32Do Not Stuff

1,

H_CFG8

HR31Do Not Stuff1,HR31Do Not Stuff

1,

H_CFG9

HR33Do Not Stuff1,HR33Do Not Stuff

1,

H_CFG10

HR34Do Not Stuff1,HR34Do Not Stuff

1,

H_CFG11

HR35Do Not Stuff1,HR35Do Not Stuff

1,

H_CFG12

HR37Do Not Stuff1,HR37Do Not Stuff

1,

H_CFG13

HR36Do Not Stuff1,HR36Do Not Stuff

1,

H_CFG14

HR39Do Not Stuff1,HR39Do Not Stuff

1,

H_CFG15

HR38Do Not Stuff1,HR38Do Not Stuff

1,

H_CFG16_SNB_PCUSTB0 H_CFG17_SNB_PCUSTB1

XU1E

W2

BCLK_0

W1

BCLK#_0

C40

RSVD_001

D40

RSVD_002

C37

VIDSCLK

B37

VIDSOUT

A37

VIDALERT#

F36

RESET#

J40

UNCOREPWRGOOD

AJ19

SM_DRAMPWROK

J35

PECI

E37

CATERR#

H34

PROCHOT#

G35

THERMTRIP#

E38

PM_SYNC

AJ22

SM_VREF

AJ33

SKTOCC#

K32

PROC_SEL

H36

CFG_0

J36

CFG_1

J37

CFG_2

K36

CFG_3

L36

CFG_4

N35

CFG_5

L37

CFG_6

M36

CFG_7

J38

CFG_8

L35

CFG_9

M38

CFG_10

N36

CFG_11

N38

CFG_12

N39

CFG_13

N37

CFG_14

N40

CFG_15

G37

CFG_16

G36

CFG_17

AT14

RSVD_016

AY3

RSVD_023

H7

RSVD_028

H8

RSVD_029

SOCKET_1155P

SOCKET_1155P I

I

3

MISC

VCCSA_VID

VCCSA_SENSE

VCC_SENSE

VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

VCCAXG_SENSE VSSAXG_SENSE

VCCP_SELECT

TDO

TCK TMS

TRST#

PRDY# PREQ#

DBR#

BPM#_0 BPM#_1 BPM#_2 BPM#_3 BPM#_4 BPM#_5 BPM#_6 BPM#_7

RSVD_024 RSVD_030 RSVD_037 RSVD_036 RSVD_033

RSVD_040 RSVD_039

RSVD_018 RSVD_020

RSVD_038 RSVD_032 RSVD_034

RSVD_035

RSVD_050 RSVD_053

RSVD_051 RSVD_052

2

P34 T2

A36 B36

AB4 AB3

L32 M32

+5V

12

,

HR52

HR52 10K

10K

P33

L39 L40

TDI

M40 L38 J39

12

,

HR53

4.7K

127(

TBD: CRB is NI

K38 K40 E39

H40 H38 G38 G40 G39 F38 E40 F40

B39 J33 L34 L33 K34

N33 M34

AV1 AW2

L9 J9 K9

L31

J31 K31

AD34 AD35

HR54 0

1 2

93

BPM0# [64] BPM1# [64] BPM2# [64] BPM3# [64] BPM4# [64] BPM5# [64] BPM6# [64] BPM7# [64]

2

+1P05V_CPUIO +1P05V_CPUIO

12

,

HR8

HR8 51

51

127(

Place near CPU

+3P3VSB

12

1,

HR15

HR15 Do Not Stuff

Do Not Stuff

12

GNDGND

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

,

HR9

HR9 51

51

,

HR12

HR12 51

51

12

GND

1

VCCSA_VID [53] VCCSA_SENSE [53]

VCC_SENSE [58] VSS_SENSE [58]

VCCIO_SENSE [53] VSSIO_SENSE [53]

VCCAXG_SENSE [58] VSSAXG_SENSE [58]

12

127(

,

HR10

Place near XDP connector

51

VCCIO_SEL [53]

TDO [64] TDI [64] TCK [64] TMS [64] TRST# [64]

,

HR13

HR13 51

51

H_PRDY# [64] H_PREQ# [64] SYS_RESET_DBR# [20,63,64]

Title :

Engineer:

,336%)$

1

0,6&

Mike Yen

779Wednesday, April 27, 2011

Rev

1.01

of

5

4

3

2

1

D D

C C

B B

A A

XU1F

A12

VCC_001

A13

VCC_002

A14

VCC_003

A15

VCC_004

A16

VCC_005

A18

VCC_006

A24

VCC_007

A25

VCC_008

A27

VCC_009

A28

VCC_010

B15

VCC_011

B16

VCC_012

B18

VCC_013

B24

VCC_014

B25

VCC_015

B27

VCC_016

B28

VCC_017

B30

VCC_018

B31

VCC_019

B33

VCC_020

B34

VCC_021

C15

VCC_022

C16

VCC_023

C18

VCC_024

C19

VCC_025

C21

VCC_026

C22

VCC_027

C24

VCC_028

C25

VCC_029

C27

VCC_030

C28

VCC_031

C30

VCC_032

C31

VCC_033

C33

VCC_034

C34

VCC_035

C36

VCC_036

D13

VCC_037

D14

VCC_038

D15

VCC_039

D16

VCC_040

D18

VCC_041

D19

VCC_042

D21

VCC_043

D22

VCC_044

D24

VCC_045

D25

VCC_046

D27

VCC_047

D28

VCC_048

D30

VCC_049

D31

VCC_050

D33

VCC_051

D34

VCC_052

D35

VCC_053

D36

VCC_054

E15

VCC_055

E16

VCC_056

E18

VCC_057

E19

VCC_058

E21

VCC_059

E22

VCC_060

E24

VCC_061

E25

VCC_062

E27

VCC_063

E28

VCC_064

E30

VCC_065

E31

VCC_066

E33

VCC_067

E34

VCC_068

E35

VCC_069

F15

VCC_070

F16

VCC_071

F18

VCC_072

F19

VCC_073

F21

VCC_074

F22

VCC_075

F24

VCC_076

F25

VCC_077

F27

VCC_078

F28

VCC_079

F30

VCC_080

F31

VCC_081

VCC_082 VCC_083 VCC_084 VCC_085 VCC_086 VCC_087 VCC_088 VCC_089 VCC_090 VCC_091 VCC_092 VCC_093 VCC_094 VCC_095 VCC_096 VCC_097 VCC_098 VCC_099 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125 VCC_126 VCC_127 VCC_128 VCC_129 VCC_130 VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153 VCC_154 VCC_155 VCC_156 VCC_157 VCC_158 VCC_159 VCC_160 VCC_161

F32 F33 F34 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G32 G33 H13 H14 H15 H16 H18 H19 H21 H22 H24 H25 H27 H28 H30 H31 H32 J12 J15 J16 J18 J19 J21 J22 J24 J25 J27 J28 J30 K15 K16 K18 K19 K21 K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18 M19 M21 M22 M24 M25 M27 M28 M30

+VCORE+VCORE

+1P05V_CPUIO

+0P925V_SA

+1P8V_SFR

AC24

4.7UF/6.3V

1 2

X5R 10%

,

mx_c0805

GND

M13

AA3 AB8 AF8

AG33

AJ16 AJ17 AJ26 AJ28

AJ32 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK30

D10

H10 H11 H12

M10 M11 M12

AK11 AK12

A11

A7

B9

D6 E3

E4 G3 G4

J3

J4

J7

J8

L3

L4

L7

N3

N4

N7

R3

R4

R7

U3

U4

U7

V8 W3

J10 K10 K11 L11 L12

XU1H

VCCIO_34

VCCIO_01 VCCIO_02 VCCIO_03 VCCIO_04 VCCIO_05 VCCIO_06 VCCIO_07 VCCIO_08 VCCIO_09 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCIO_15 VCCIO_16 VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29 VCCIO_30 VCCIO_31 VCCIO_32 VCCIO_33 VCCIO_35 VCCIO_36 VCCIO_37 VCCIO_38 VCCIO_39 VCCIO_40 VCCIO_41 VCCIO_42 VCCIO_43 VCCIO_44 VCCIO_45

VCCSA_01 VCCSA_02 VCCSA_03 VCCSA_04 VCCSA_05 VCCSA_06 VCCSA_07 VCCSA_08 VCCSA_09 VCCSA_10 VCCSA_11

VCCPLL_01 VCCPLL_02

SOCKET_1155P

SOCKET_1155P I

I

VDDQ_01 VDDQ_02 VDDQ_04 VDDQ_05 VDDQ_06 VDDQ_07 VDDQ_08 VDDQ_09 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23

VDDQ_03

AJ13 AJ14 AJ23 AJ24 AR20 AR21 AR22 AR23 AR24 AU19 AU23 AU27 AU31 AV21 AV24 AV25 AV29 AV33 AW31 AY23 AY26 AY28

AJ20

+1P5V_DUAL

Place on the bottom under XU1

12

GND GND GND

,

HCB1

HCB1 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

HCB6

HCB6 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

HCB3

HCB3 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

+V_AXG

AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40

W33 W34 W35 W36 W37 W38

T33 T34 T35 T36 T37 T38 T39 T40 U33 U34 U35 U36 U37 U38 U39 U40

Y33 Y34 Y35 Y36 Y37 Y38

XU1G

VCCAXG_01 VCCAXG_02 VCCAXG_03 VCCAXG_04 VCCAXG_05 VCCAXG_06 VCCAXG_07 VCCAXG_08 VCCAXG_09 VCCAXG_10 VCCAXG_11 VCCAXG_12 VCCAXG_13 VCCAXG_14 VCCAXG_15 VCCAXG_16 VCCAXG_17 VCCAXG_18 VCCAXG_19 VCCAXG_20 VCCAXG_21 VCCAXG_22 VCCAXG_23 VCCAXG_24 VCCAXG_25 VCCAXG_26 VCCAXG_27 VCCAXG_28 VCCAXG_29 VCCAXG_30 VCCAXG_31 VCCAXG_32 VCCAXG_33 VCCAXG_34 VCCAXG_35 VCCAXG_36 VCCAXG_37 VCCAXG_38 VCCAXG_39 VCCAXG_40 VCCAXG_41 VCCAXG_42 VCCAXG_43 VCCAXG_44

SOCKET_1155P

SOCKET_1155P I

I

5

SOCKET_1155P

SOCKET_1155P I

I

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

4

3

2

Date: Sheet

Engineer:

,336%)$

9&&

Mike Yen

879Tuesday, April 26, 2011

1

879Tuesday, April 26, 2011

Rev

1.01

of

5

XU1I

A17

VSS_001

A23

VSS_002

A26

VSS_003

A29

VSS_004

D D

C C

B B

A A

A35

VSS_005

AA33

VSS_006

AA34

VSS_007

AA35

VSS_008

AA36

VSS_009

AA37

VSS_010

AA38

VSS_011

AA6

VSS_012

AB5

VSS_013

AC1

VSS_014

AC6

VSS_015

AD33

VSS_016

AD36

VSS_017

AD38

VSS_018

AD39

VSS_019

AD40

VSS_020

AD5

VSS_021

AD8

VSS_022

AE3

VSS_023

AE33

VSS_024

AE36

VSS_025

AF1

VSS_026

AF34

VSS_027

AF36

VSS_028

AF37

VSS_029

AF40

VSS_030

AF5

VSS_031

AF6

VSS_032

AF7

VSS_033

AG36

VSS_034

AH2

VSS_035

AH3

VSS_036

AH33

VSS_037

AH36

VSS_038

AH37

VSS_039

AH38

VSS_040

AH39

VSS_041

AH40

VSS_042

AH5

VSS_043

AH8

VSS_044

AJ12

VSS_045

AJ15

VSS_046

AJ18

VSS_047

AJ21

VSS_048

AJ25

VSS_049

AJ27

VSS_050

AJ36

VSS_051

AJ5

VSS_052

AK1

VSS_053

AK10

VSS_054

AK13

VSS_055

AK14

VSS_056

AK16

VSS_057

AK22

VSS_058

AK28

VSS_059

AK31

VSS_060

AK32

VSS_061

AK33

VSS_062

AK34

VSS_063

AK35

VSS_064

AK36

VSS_065

AK37

VSS_066

AK4

VSS_067

AK40

VSS_068

AK5

VSS_069

AK6

VSS_070

AK7

VSS_071

AK8

VSS_072

AK9

VSS_073

AL11

VSS_074

AL14

VSS_075

AL17

VSS_076

AL19

VSS_077

AL24

VSS_078

AL27

VSS_079

AL30

VSS_080

AL36

VSS_081

AL5

VSS_082

AM1

VSS_083

AM11

VSS_084

AM14

VSS_085

AM17

VSS_086

AM2

VSS_087

AM21

VSS_088

AM23

VSS_089

AM25

VSS_090

A4

VSS_NCTF_01

AV39

VSS_NCTF_02

GND GND GND GND

SOCKET_1155P

SOCKET_1155P I

I

5

GND

VSS_091 VSS_092 VSS_093 VSS_094 VSS_095 VSS_096 VSS_097 VSS_098 VSS_099 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180

AM27 AM3 AM30 AM36 AM37 AM38 AM39 AM4 AM40 AM5 AN10 AN11 AN14 AN17 AN19 AN22 AN24 AN27 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN5 AN6 AN7 AN8 AN9 AP1 AP11 AP14 AP17 AP22 AP25 AP27 AP30 AP36 AP37 AP4 AP40 AP5 AR11 AR14 AR17 AR18 AR19 AR27 AR30 AR36 AR5 AT1 AT10 AT12 AT13 AT15 AT16 AT17 AT2 AT25 AT27 AT28 AT29 AT3 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT4 AT40 AT5 AT6 AT7 AT8 AT9 AU1 AU15 AU26 AU34 AU4 AU6 AU8 AV10

4

AV11 AV14 AV17

AV35 AV38

AW10 AW11 AW14 AW16 AW36

AW6 AY11 AY14 AY18 AY35

AY37

4

AV3

AV6

AY4 AY6 AY8 B10 B13 B14 B17 B23 B26 B29 B32 B35 B38

C11 C12 C17 C20 C23 C26 C29 C32 C35

D17

D20 D23 D26 D29 D32 D37 D39

E11 E12 E17 E20 E23 E26 E29 E32 E36

F10 F13 F14 F17

F20 F23 F26 F29 F35 F37 F39

G11 G12 G17 G20 G23 G26 G29 G34

B6

C7 C8

D2

D4 D5 D9

E7 E8 F1

F2

F5 F6 F9

G7

B3

XU1J

VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_NCTF_03 VSS_NCTF_04

GND

SOCKET_1155P

SOCKET_1155P I

I

VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

G8 H1 H17 H2 H20 H23 H26 H29 H33 H35 H37 H39 H5 H6 H9 J11 J17 J20 J23 J26 J29 J32 K1 K12 K13 K14 K17 K2 K20 K23 K26 K29 K33 K35 K37 K39 K5 K6 L10 L17 L20 L23 L26 L29 L8 M1 M17 M2 M20 M23 M26 M29 M33 M35 M37 M39 M5 M6 M9 N8 P1 P2 P36 P38 P40 P5 P6 R33 R35 R37 R39 R8 T1 T5 T6 U8 V1 V2 V33 V34 V35 V36 V37 V38 V39 V40 V5 W6 Y5 Y8

3

XU1K

AB7

RSVD_04

AD37

RSVD_05

AG4

RSVD_08

AJ29

RSVD_10

AJ30

RSVD_11

AJ31

RSVD_12

AV34

RSVD_19

AW34

RSVD_21

P35

RSVD_43

P37

RSVD_44

P39

RSVD_45

R34

RSVD_46

R36

RSVD_47

R38

RSVD_48

R40

RSVD_49

A38

NCTF_01

AU40

NCTF_02

AW38

NCTF_03

C2

NCTF_04

D1

NCTF_05

SOCKET_1155P

SOCKET_1155P I

I

,

%$&.3/$7(

INTEL LGA 1156P BACK PLATE,3 SCREW

PT44P11-6401

H28

1

Do Not Stuff

12%20

H29

1

Do Not Stuff

12%20

H30

1

Do Not Stuff

12%20

H31

1

Do Not Stuff

12%20

3

2

SA_DIMM_VR

AH1

FC_AH1 FC_AH4

RSVD_15 RSVD_14 RSVD_13 RSVD_17 RSVD_22

RSVD_07 RSVD_03 RSVD_06 RSVD_09

RSVD_27 RSVD_26 RSVD_25 RSVD_31 RSVD_41

NP_NC1 NP_NC2 NP_NC3 NP_NC4 NP_NC5 NP_NC6 NP_NC7

AH4

AT11 AP20 AN20 AU10 AY10

AF4 AB6 AE6 AJ11

D38 C39 C38 J34 N34

1 2 3 4 5 6 7

SB_DIMM_VR

SFA 1.01

2

12

,

HC2

0.1UF/16V

GND GND

,

,/0

INTEL LGA1156 SOCKET ILM

SOCKET1156_ILM

1

HR42 0

1 2

,9%

HR43 0

1 2

,9%

12

,

HC3

0.1UF/16V

DIMM_VREF_A [10] DIMM_VREF_B [11]

Stuff resistors HR42/HR43 for future IVB VREF capability

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

Engineer:

,336%)$

966

Mike Yen

979Wednesday, April 27, 2011

1

979Wednesday, April 27, 2011

Rev

1.01

of

5

4

3

2

1

ઃઃઃઃޏޏޏޏ

D D

M_CHA_MAA0 M_CHA_MAA1 M_CHA_MAA2 M_CHA_MAA3 M_CHA_MAA4 M_CHA_MAA5 M_CHA_MAA6 M_CHA_MAA7 M_CHA_MAA8 M_CHA_MAA9 M_CHA_MAA10 M_CHA_MAA11 M_CHA_MAA12 M_CHA_MAA13 M_CHA_MAA14 M_CHA_MAA15

M_CHA_CLK1[4] M_CHA_CLK1#[4] M_CHA_CLK0[4]

C C

B B

M_CHA_CLK0#[4]

M_CHA_CS#1[4] M_CHA_CS#0[4]

M_CHA_ODT1[4] M_CHA_ODT0[4]

M_CHA_WE#[4] M_CHA_RAS#[4] M_CHA_CAS#[4]

M_CHA_BA2[4] M_CHA_BA1[4] M_CHA_BA0[4]

M_CHA_CKE1[4] M_CHA_CKE0[4]

M_CHA_DQS7[4]

M_CHA_DQS7#[4]

M_CHA_DQS6[4]

M_CHA_DQS6#[4]

M_CHA_DQS5[4]

M_CHA_DQS5#[4]

M_CHA_DQS4[4]

M_CHA_DQS4#[4]

M_CHA_DQS3[4]

M_CHA_DQS3#[4]

M_CHA_DQS2[4]

M_CHA_DQS2#[4]

M_CHA_DQS1[4]

M_CHA_DQS1#[4]

M_CHA_DQS0[4]

M_CHA_DQS0#[4]

GND

SMB_CLK_M[11,37,38,45,63,64,79] SMB_DATA_M[11,37,38,45,63,64,79]

GND

5.2H

DIMMA0A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

DDR3_DIMM_204P I

I

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

30

M_CHA_DQ1 M_CHA_DQ5 M_CHA_DQ2 M_CHA_DQ3 M_CHA_DQ0 M_CHA_DQ4 M_CHA_DQ7 M_CHA_DQ6

M_CHA_DQ13 M_CHA_DQ12 M_CHA_DQ15 M_CHA_DQ14 M_CHA_DQ8 M_CHA_DQ9 M_CHA_DQ11

M_CHA_DQ10 M_CHA_DQ17 M_CHA_DQ20 M_CHA_DQ23 M_CHA_DQ18 M_CHA_DQ16 M_CHA_DQ21 M_CHA_DQ19 M_CHA_DQ22

M_CHA_DQ29

M_CHA_DQ28

M_CHA_DQ31

M_CHA_DQ30

M_CHA_DQ24

M_CHA_DQ25

M_CHA_DQ27

M_CHA_DQ26 M_CHA_DQ33 M_CHA_DQ36 M_CHA_DQ38 M_CHA_DQ39 M_CHA_DQ32 M_CHA_DQ37 M_CHA_DQ34 M_CHA_DQ35

M_CHA_DQ41

M_CHA_DQ45

M_CHA_DQ47

M_CHA_DQ42

M_CHA_DQ44

M_CHA_DQ40

M_CHA_DQ46

M_CHA_DQ43 M_CHA_DQ53 M_CHA_DQ52 M_CHA_DQ51 M_CHA_DQ50 M_CHA_DQ48 M_CHA_DQ49 M_CHA_DQ54 M_CHA_DQ55

M_CHA_DQ57

M_CHA_DQ56

M_CHA_DQ63

M_CHA_DQ62

M_CHA_DQ61

M_CHA_DQ60

M_CHA_DQ59

M_CHA_DQ58

M_CHA_MAA[0..15] [4]

M_CHA_DQ[0..63] [4]

DDR3_DRAMRST# [4,11]

I

+1P5V_DUAL

GND

+1P5V_DUAL +1P5V_DUAL

12

,

D3R30

D3R31

1K

1%

DIMM_VREF_A[9]

12

,

D3R32

D3R22

1K

1%

GND GND GND GND

12

,

D3CB48

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

DIMM_CA_VREF_A

DIMM_VREF_A

12

,

D3CB15

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

I

DIMMA0B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

VDD2 VDD4 VDD6

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VSS2

VSS4

VSS6

VSS8 VSS10 VSS12 VSS14 VSS16 VSS18 VSS20 VSS22 VSS24 VSS26 VSS28 VSS30 VSS32 VSS34 VSS36 VSS38 VSS40 VSS42 VSS44 VSS46 VSS48 VSS50 VSS52

GND1 GND2

NP_NC1 NP_NC2

VTT1 VTT2

VDDSPD

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

203 204

199

1UF/6.3V

X5R 10%

C9351

I

+1P5V_DUAL

12

C9350

1UF/6.3V

X5R 10%

GND

I

+3P3V

GNDGND

12

D3CB1

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

,

GND

12

D3CB49

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

,

4.7UF/6.3V

mx_c0805_small

D3CB16

X5R 10%

+VTT_DDR

12

,

GNDGND

A A

''5&+$11(/$

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

5

4

3

2

Date: Sheet

Engineer:

,336%)$

1

Mike Yen

10 79Wednesday, April 27, 2011

Rev

1.01

of

5

4

3

2

1

ઃઃઃઃޏޏޏޏ

D D

M_CHB_MAA0 M_CHB_MAA1 M_CHB_MAA2 M_CHB_MAA3 M_CHB_MAA4 M_CHB_MAA5 M_CHB_MAA6 M_CHB_MAA7 M_CHB_MAA8 M_CHB_MAA9 M_CHB_MAA10 M_CHB_MAA11 M_CHB_MAA12 M_CHB_MAA13 M_CHB_MAA14 M_CHB_MAA15

M_CHB_CLK1[5] M_CHB_CLK1#[5] M_CHB_CLK0[5]

C C

B B

M_CHB_CLK0#[5]

M_CHB_CS#1[5] M_CHB_CS#0[5]

M_CHB_ODT1[5] M_CHB_ODT0[5]

M_CHB_WE#[5] M_CHB_RAS#[5] M_CHB_CAS#[5]

M_CHB_BA2[5] M_CHB_BA1[5] M_CHB_BA0[5]

M_CHB_CKE1[5] M_CHB_CKE0[5]

M_CHB_DQS7[5]

M_CHB_DQS7#[5]

M_CHB_DQS6[5]

M_CHB_DQS6#[5]

M_CHB_DQS5[5]

M_CHB_DQS5#[5]

M_CHB_DQS4[5]

M_CHB_DQS4#[5]

M_CHB_DQS3[5]

M_CHB_DQS3#[5]

M_CHB_DQS2[5]

M_CHB_DQS2#[5]

M_CHB_DQS1[5]

M_CHB_DQS1#[5]

M_CHB_DQS0[5]

M_CHB_DQS0#[5]

GND

SMB_CLK_M[10,37,38,45,63,64,79] SMB_DATA_M[10,37,38,45,63,64,79]

+3P3V

GND

5.2H

+

',00%$

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

DDR3_DIMM_204P I

I

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

30

M_CHB_DQ0 M_CHB_DQ4 M_CHB_DQ7 M_CHB_DQ6 M_CHB_DQ1 M_CHB_DQ5 M_CHB_DQ2 M_CHB_DQ3 M_CHB_DQ13 M_CHB_DQ12 M_CHB_DQ15 M_CHB_DQ14 M_CHB_DQ8 M_CHB_DQ9 M_CHB_DQ10 M_CHB_DQ11 M_CHB_DQ20 M_CHB_DQ21 M_CHB_DQ23 M_CHB_DQ22 M_CHB_DQ16 M_CHB_DQ17 M_CHB_DQ18 M_CHB_DQ19 M_CHB_DQ24 M_CHB_DQ25 M_CHB_DQ27 M_CHB_DQ26 M_CHB_DQ28 M_CHB_DQ29 M_CHB_DQ30 M_CHB_DQ31 M_CHB_DQ32 M_CHB_DQ33 M_CHB_DQ38 M_CHB_DQ39 M_CHB_DQ36 M_CHB_DQ37 M_CHB_DQ34 M_CHB_DQ35 M_CHB_DQ40 M_CHB_DQ41 M_CHB_DQ47 M_CHB_DQ46 M_CHB_DQ44 M_CHB_DQ45 M_CHB_DQ42 M_CHB_DQ43 M_CHB_DQ52 M_CHB_DQ53 M_CHB_DQ51 M_CHB_DQ50 M_CHB_DQ49 M_CHB_DQ48 M_CHB_DQ54 M_CHB_DQ55 M_CHB_DQ61 M_CHB_DQ60 M_CHB_DQ62 M_CHB_DQ63 M_CHB_DQ57 M_CHB_DQ56 M_CHB_DQ59 M_CHB_DQ58

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

D3C4

,

GND

12

DDR3_DRAMRST# [4,10]

M_CHB_DQ[0..63] [5]

M_CHB_MAA[0..15] [5]

DIMM_VREF_B[9]

+1P5V_DUAL +1P5V_DUAL

12

,

D3R33

D3R36

1K

1%

12

,

D3R35

D3R35 1K

1K 1%

1%

GND GND GND GND

,

D3R37

D3R37 1K

1K 1%

1%

12

,

D3CB51

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

+1P5V_DUAL

GND

DIMM_CA_VREF_B DIMM_VREF_B

12

,

D3CB50

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

',00%%

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

DDR3_DIMM_204P I

I

VDD2 VDD4 VDD6

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VSS2 VSS4 VSS6

VSS8 VSS10 VSS12 VSS14 VSS16 VSS18 VSS20 VSS22 VSS24 VSS26 VSS28 VSS30 VSS32 VSS34 VSS36 VSS38 VSS40 VSS42 VSS44 VSS46 VSS48 VSS50 VSS52

GND1 GND2

NP_NC1 NP_NC2

VTT1

VTT2

VDDSPD

+1P5V_DUAL

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

203 204

199

+3P3V

GND

D3CB52

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

,

4.7UF/6.3V

4.7UF/6.3V X5R 10%

X5R 10%

mx_c0805_small

D3CB5

+VTT_DDR

12

,

GNDGND

A A

''5&+$11(/%

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

5

4

3

2

Date: Sheet

Engineer:

,336%)$

1

Mike Yen

11 79Wednesday, April 27, 2011

Rev

1.01

of

5

+1P5V_DUAL

ࣰࣣࣞ࣎࣋࣍࣎ࣞ࣊࣢ࣦ࣪

ࣰࣣࣞ࣎࣋࣍࣎ࣞ࣊࣢ࣰࣦࣣ࣪ࣞ࣎࣋࣍࣎ࣞ࣊࣢ࣦ࣪

4

3

2

1

1,

D3CB19

D3CB19 Do Not Stuff

Do Not Stuff X5R 10%

X5R 10%

,

D3CB33

D3CB33 1UF/25V

1UF/25V mx_c0603

mx_c0603 X5R 10%

X5R 10%

12

D D

12

GND

12

,

D3CB18

D3CB18 1UF/25V

1UF/25V X5R 10%

X5R 10%

GND GND GND

12

,

D3CB32

D3CB32 1UF/25V

1UF/25V mx_c0603

mx_c0603 X5R 10%

X5R 10%

,

D3CB20

D3CB20 1UF/25V

1UF/25V X5R 10%

X5R 10%

,

D3CB34

D3CB34 1UF/25V

1UF/25V mx_c0603

mx_c0603 X5R 10%

X5R 10%

GNDGND GNDGND

12

,

D3CB35

D3CB35 1UF/25V

1UF/25V mx_c0603

mx_c0603 X5R 10%

X5R 10%

,

D3CB21

D3CB21 1UF/25V

1UF/25V X5R 10%

X5R 10%

127(

Place those cap close to CH A DIMM0

127(

Place those cap close to CH B DIMM0

Place those cap between CH A DIMM0 to CH B DIMM0

C C

12

GND GND GNDGND GNDGND

,

D3CB72

D3CB72 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

D3CB73

D3CB73 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

D3CB74

D3CB74 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

D3CB75

D3CB75 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

,

D3CB76

D3CB76 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12



D3CE3

,

D3CB77

D3CB77 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

D3CE3 Do Not Stuff

Do Not Stuff NI

NI

GND GND GND GND

12



D3CE1

D3CE1 Do Not Stuff

Do Not Stuff NI

NI

12



D3CE2

D3CE2 Do Not Stuff

Do Not Stuff NI

NI

12



D3CE4

D3CE4 Do Not Stuff

Do Not Stuff NI

NI

TBD

Place D3CB77 near CH B DIMM0

B B

127(

',003ODFHPHQWIRUGLIIHUHQWSODWIRUP

',00

21 34

A A

LGA1156 LFD/CKD

LGA1155

SNB

CH BCH A

5

',00

134

2

CH A CH B

4

PEGATRON DT-MB RESTRICTED SECRET

''57(50,1$7,21$%

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

3

2

Date: Sheet

Engineer:

,336%)$

1

Mike Yen

12 79Tuesday, April 26, 2011

Rev

1.01

of

5

D D

4

3

2

1

PLTRST_CPU#

178 ohm in CRB and PDG

HR46 180 1%

R1808

C C

PLTRST#[20,43,54,63]

CPU_RST#[43]

R1808

R1806

0 OhmI

Do Not StuffNI

HR46 180 1%

1 2

,

GND

PLTRST_CPU# [7]

12

,

HR49

HR49 75

75

HR48 Do Not Stuff

1 2

1,

1%

CPURST_XDP# [63,64]

+3VA_EC+3VA_EC +12V

B B

SML0_CLK_EC[43]

SML0_DATA_EC[43]

(&

A A

5

R1804

R1804 Do Not Stuff

Do Not Stuff 5%

5% NI

NI

R1803

R1803 Do Not Stuff

Do Not Stuff 5%

5% NI

NI

3

R1813

1,

4

D

R1811

+12V

1

G

1

G

1,

Q63

Do Not Stuff

2

S

Q61

2N7002

2

S

,

Do Not Stuff

1,

3&+

0 OhmI

R1812

R1814

1,

1

G

Q64

Do Not Stuff

3

2

3

2

D

S

0 OhmI

+3P3V +3P3V

R1816

R1815

2.2KOHM

I

1

G

Q62

Q62 2N7002

2N7002

3

2

3

2

D

S

,

Do Not Stuff

R1805

0 OhmI

R1805

0 OhmI

R1807

0 OhmI

R1807

0 OhmI

3

SML1_CLK [17]

SML1_DATA [17]

GPU TEMP

SMB1_CLK_MXM [69]

SMB1_DATA_MXM [69]

PEGATRON DT-MB RESTRICTED SECRET

3/7567B&3860EXV

Title :

Engineer:

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

2

Date: Sheet

Engineer:

,336%)$

1

XXXX-XX

13 79Wednesday, April 27, 2011

Rev

1.01

of

5

D8825

BAT54CW

D8828

BAT54CW

1

2

BAT54CW

,

SCL_LCDEN[15,16]

3

SCL_BL_EN[15,16]

3

SCL_BL_PWM[15,16]

+3P3V

12

PCH_BL_EN[25]

5

MXM_LCDEN[69]

PCH_LCDPWR_EN[25]

ENABLE_CONTROL

R280

R280 10KOhm

10KOhm

I

ENABKL[79]

ENABLE_CONTROL

R120 0Ohm

ENAVDD[79]

2

EDPPWM[79]

R120 0Ohm

R125 Do Not Stuff

+3P3V

12

R281

R281 10KOhm

10KOhm

I

1

G

3

D

S

Q66

Q66 2N7002

2N7002 I

I

MXM_BL_EN[69]

R37546 0Ohm

1 2

I

R37534 Do Not Stuff

1 2

NI

MXM_BL_PWM[69]

1 2

,

1 2

1,

1

2

I

1

2

I

+19VSB

12

+19V

R287

R287 Do Not Stuff

Do Not Stuff

NI

GND

AVIN_DET#[15,16,19,36]

12

R289

R289 10KOhm

10KOhm

I

R291

R291 10KOhm

10KOhm

I

IN

D D

C C

B B

A A

D8827

4

+3P3V

3

1

G

2

+3P3V

12

R288

R288 Do Not Stuff

Do Not Stuff

NI

3

D

1

G

S

2

+3P3V

12

3

D

1

G

S

2

SFA1.04

4

12

R285

R285 Do Not Stuff

Do Not Stuff

NI

D

S

Q65

Q65 2N7002

2N7002 I

I

R322

R322 Do Not Stuff

Do Not Stuff

NI

Q67

Q67 2N7002

2N7002 I

I

Q69

Q69 2N7002

2N7002 I

I

+3P3V

GND

+3P3V

GND

12

+3P3V

12

GND

12

R316

R316 Do Not Stuff

Do Not Stuff

NI

12

100KOhm

100KOhm R752

R752

,

R295

R295 Do Not Stuff

Do Not Stuff

NI

Do Not Stuff

Do Not Stuff R334

R334

NI

R7841

R7841 Do Not Stuff

Do Not Stuff

NI

,

1KOhm

1KOhm R331

R331

SFA 1.01A

+19VSB

,

12

1%

1% 47KOHM

47KOHM R197

R197

I

R320 220Ohm

LVDS_LCDEN_B

1 2

3

+5VSB

+5V

R129

R129 0 Ohm

0 Ohm 5%

5%

1 2

NI

I

NI

12

1,

C44195

C44195 Do Not Stuff

Do Not Stuff Y5V +80-20%

Y5V +80-20%

GND

B

1

B

1

I

12

LVDS_LCDEN_C

3

C

Q310

PMBS3904

E

E 2

2

R321

R321 56KOHM

56KOHM I

I 1%

1%

I

12

,

C44194

0.1UF/16V

0.1UF/16V Y5V +80-20%

Y5V +80-20%

GND

ID2 ID1 ID0 Panel

0 0 0 CMI

0 0 1 SAMSUNG

0 1 0 TBD

0 1 1 TBD

21.5" Converter connector

Pin3 ->ID2

Pin6 ->ID1

Pin9 ->ID0

3

+12V

R128

R128 Do Not Stuff

Do Not Stuff 5%

5%

R130

R130 Do Not Stuff

Do Not Stuff 5%

5%

1 2

NI

1 2

I

10KOhm

10KOhm 1%

1%

B

1

B

1

R319

V_LCD_G

R317 10Ohm

V_LCD_C

3

C

Q308

PMBS3904

E

I

2

ID2 ID1 ID0 Panel

1 0 0 CMI

1 0 1 SAMSUNG

1 1 0 TBD

1 1 1 TBD

23" Converter connector

Pin3 ->ID2

Pin6 ->ID1

Pin9 ->ID0

AP2306GN

Q309

D

3

12

I

GND GNDGND GND

1

12

I

S

2

G

C44197

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10% I

I

+19V

2

+V_LCD

12

2

C44196

C44196 10UF/10V

10UF/10V Y5V +80-20%

Y5V +80-20% I

I

mx_c0805

ࣰࣣ࣑ࣞ࣎࣋࣍

ࣰࣰࣣ࣑ࣣ࣑ࣞ࣎࣋࣍ࣞ࣎࣋࣍

F204

1 2

3A/32V

3A/32V I

I

R37496

R37496 Do Not Stuff

Do Not Stuff 5%

5%

1 2

NI

3

D

Q68

Q68 Do Not Stuff

Do Not Stuff

1

NI

G

S

2

GND

PANEL_ID_2_R[19,79]

PANEL_ID_1_R[15,16,19,79]

PANEL_ID_0_R[15,16,19,79]

Pegatron Corp .

Size Project Name

A3

Date: Sheet

IN

INV_ADJ

IN

GND

Title :

Engineer:

,336%)$

INV_EN

1

FRQYHUWHU &RQQ

CON3

1 2 3

5 6 7 8 9410

WAFER_HD_1X9P

I

Converter Controllor

Hugo Liao

1

Rev

1.01

of

14 79Wednesday, April 27, 2011

5

բբբբଥଥଥଥޏޏޏޏݙݙݙݙګګګګ

URN9A

1 2

1,

Do Not Stuff

LVDS_U0N_NB[79]

LVDS_U0P_NB[79]

D D

LVDS_U1N_NB[79]

LVDS_U1P_NB[79]

LVDS_U2N_NB[79]

LVDS_U2P_NB[79]

LVDS_UCLKN_NB[79]

LVDS_UCLKP_NB[79]

LVDS_U3N_NB[79]

LVDS_U3P_NB[79]

LVDS_L0N_NB[79]

LVDS_L0P_NB[79]

C C

IN

Do Not Stuff

14

23

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL9

UL9

URN9B

3 4

1,

Do Not Stuff

URN12A

1 2

1,

Do Not Stuff

IN

23

3 4

1,

1 2

1,

23

3 4

1,

1 2

1,

23

3 4

1,

1 2

1,

23

3 4

1,

1 2

1,

23

3 4

1,

14

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL11

UL11

Do Not Stuff

14

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL12

UL12

Do Not Stuff

14

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL13

UL13

Do Not Stuff

14

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL14

UL14

Do Not Stuff

14

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL15

UL15

Do Not Stuff

URN12B

URN14A

URN14B

URN16A

URN16B

URN18A

URN18B

URN20A

URN20B

/9'6&2113&+

LVDS_U0N_NB_CON LVDS_U0P_NB_CON LVDS_U1N_NB_CON LVDS_U1P_NB_CON LVDS_U2N_NB_CON LVDS_U2P_NB_CON

LVDS_UCLKN_NB_CON LVDS_UCLKP_NB_CON LVDS_U3N_NB_CON LVDS_U3P_NB_CON LVDS_L0N_NB_CON LVDS_L0P_NB_CON

4

LCD CONN NB & GPU colay

Adjust value on 5/31

12

C44168

2.2PF/50V

I

P174

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

WtoB_CON_2X15P

WtoB_CON_2X15P I

I

GND

SIDE2

SIDE1

10 12 14 16 18 20 22 24 26 28 30

2 4 6 8

32 2 4 6

R37547 Do Not StuffNIR37547 Do Not StuffNI

8 10 12 14 16 18 20 22 24 26 28 30 31

1 2

GND

LVDS_L3P_NB_CON LVDS_L3N_NB_CON LVDS_LCLKP_NB_CON LVDS_LCLKN_NB_CO N LVDS_L2P_NB_CON LVDS_L2N_NB_CON LVDS_L1P_NB_CON LVDS_L1N_NB_CON

12

C44169

0.1UF/25V

+V_LCD

I

GNDGNDGND

90OHM/100MHZ/330mA

3

12

C44170

C44170 1UF/16V

1UF/16V

I

URN22B

URN22A

URN24B

URN24A

URN26B

URN26A

URN28A

URN28B

1.01 20101019 EMI revised

12

C44171

470uF/6.3V

10PF/50V

10PF/50V NPO 5%

NPO 5% I

I

34

Do Not Stuff

14

23

UL16

,

12

1,

Do Not Stuff

34

Do Not Stuff

14

23

UL17

,

12

1,

Do Not Stuff

34

Do Not Stuff

14

23

UL18

,

12

1,

Do Not Stuff

12

Do Not Stuff

,

UL19

1 4

2 3

34

1,

Do Not Stuff

C44252

1,

12



,

ࣰࣣࣞ࣎࣋࣍࣎

ࣰࣰࣣࣣࣞ࣎࣋࣍࣎ࣞ࣎࣋࣍࣎

IN

LVDS_L3P_NB [79]

IN

LVDS_L3N_NB [79]

IN

LVDS_LCLKP_NB [79]

IN

LVDS_LCLKN_NB [79]

IN

LVDS_L2P_NB [79]

IN

LVDS_L2N_NB [79]

IN

LVDS_L1P_NB [79]

IN

LVDS_L1N_NB [79]

12

1,

CB4101

CB4101 Do Not Stuff

Do Not Stuff mx_c0603_small

mx_c0603_small Y5V +80-20%

Y5V +80-20%

+V_LCD

12

1,

CB4102

CB4102 Do Not Stuff

Do Not Stuff mx_c0603_small

mx_c0603_small Y5V +80-20%

Y5V +80-20%

GND

2

1

$9%RDUGFRQQHFWRU

1 2

Do Not Stuff

URN100A

1,

,

1 4

3 4

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL30

UL30

2 3

URN100B

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL33

UL33

2 3

URN101B

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL29

UL29

2 3

URN102B

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL31

UL31

2 3

URN103B

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL32

UL32

2 3

URN104B

URN101A

URN102A

URN103A

URN104A

HDMI_CLKP_PCH[21]

B B

HDMI_CLKN_PCH[21]

HDMI_TXP0_PCH[21]

HDMI_TXN0_PCH[21]

HDMI_TXP1_PCH[21]

HDMI_TXN1_PCH[21]

HDMI_TXP2_PCH[21]

HDMI_TXN2_PCH[21]

HDMI_CLK_PCH[21]

HDMI_DAT_PCH[21]

ࣰࣣࣞ࣎࣋࣍࣎

A A

ࣰࣰࣣࣣࣞ࣎࣋࣍࣎ࣞ࣎࣋࣍࣎

5

EMI

HDMI_CLKP_PCH_R

HDMI_CLKN_PCH_R

HDMI_TXP0_PCH_R

HDMI_TXN0_PCH_R

HDMI_TXP1_PCH_R

HDMI_TXN1_PCH_R

HDMI_TXP2_PCH_R

HDMI_TXN2_PCH_R

HDMI_CLK_PCH_R

HDMI_DAT_PCH_R

ଥଥଥଥޏޏޏޏ

3&+

BACKLIGHT_UP[16,19,35,79]

UART_TX[16,43]

UART_RX[16,43] V_UP[16,17,35] V_DOWN[16,17,35] SLP_S3#[16,20,43,44]

&KHFNLIZHQHHGFRPSRUW

4

OUT IN IN IN IN

R185 0OhmIR185 0OhmI R186 0OhmIR186 0OhmI R190 0OhmIR190 0OhmI

IN

1 2 1 2 1 2

+3P3V

C44199

2.2PF/50V

I

Modified for Scalar ap plication on 5/26

Modified on 4/6

1.01 20101019 EMI revised

+5VSB

+5V

12

I

12

NI

NI 0Ohm

0Ohm

Do Not Stuff

R37495

R37512

12

C44198

C111

C111 1UF/16V

1UF/16V

Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

NPO 5%

NPO 5% I

I

NI

GND

IN

PANEL_ID_0_R [14,16,19,79]

IN

PANEL_ID_1_R [14,16,19,79]

IN

AVIN_DET# [14,16,19,36]

IN

SCL_LCDEN [14,16]

IN

SCL_Bl_EN [14,16]

IN

SCL_Bl_PWM [14,16]

IN

PC_MODE [16,17]

IN

AV_MODE [16,17]

IN

AUDIO_INDICATE [16,29,32]

IN

AUDIO_MUTE [16,31]

IN

PC_STATUS [16,19]

IN

INR [16,32]

IN

INL [16,32]

IN

SPDIF-OUT [16,29]

ࣰࣣࣞ࣎࣋࣍࣎

ࣰࣰࣣࣣࣞ࣎࣋࣍࣎ࣞ࣎࣋࣍࣎

+3P3VSB

+3P3V

12

I

NI

0Ohm

Do Not Stuff

R215

R239

12

C75

0.1UF/10V

0.1UF/10V I

I

1.01 20101019 EMI revised

12

Engineer:

,336%)$

1

12

C88

0.1UF/10V

0.1UF/10V I

I

GND GND Modified on 5/20

PEGATRON CORPORATION

Size Project Name

A2

Date: Sheet

C113

C113 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5% NI

NI

Title :

/9'6&21

Mike Yen

15 79Wednesday, Apr il 27, 2011

Rev

1.01

of

բբբբଥଥଥଥޏޏޏޏ آآآآݙݙݙݙګګګګ

+V_LCD

R257

R232

2.2KOHM

2.2KOHM I

I

1 2

5%

12

GNDGND

12

C44156

C44150

Do Not Stuff

NI

12

C44155

C44151

Do Not Stuff

NI

GNDGND GNDGND GNDGND

3

AP_VOLUME_DOW N_NB_R

AP_VOLUME_UP_NB_R

12

C44149

C44152

Do Not Stuff

NI

12

C44154

C44153

Do Not Stuff

NI

1.01 20101020 EMI revised

GPIO208_NB_N

CN8

1

2

1

2

3

4

3

4

5

6

5

6

7

8

7

8

9

10

9

10

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

GND GNDGND

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

SIDE141SIDE2

WtoB_CON_2X20P

WtoB_CON_2X20P I

I

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

12

GND

5VSB_CN8

NB_PANEL_ID0 NB_PANEL_ID1

3VSB_CN8

2668_DETECT_N_NB_R 2668_LVDD_EN_NB_R 2668_BK_ENA_NB_R 2668_BK_PWM_NB_R PC_MODE_NB_R AV_MODE_NB_R AUDIO_INDICATE_NB_R AUDIO_MUTE_NB_R PC_STATUS_NB_R INR_NB_R INL_NB_R SPDIF-OUT_NB_R

2

1.01 20101019 EMI revised

Adjust value on 5/31

12

C91

C91 Do Not Stuff

Do Not Stuff

I

NPO 5%

NPO 5% NI

NI

GND GND

IN

BACKLIGHT_DOW N [16,19,35,79]

R254 0OhmIR254 0OhmI

1 2

R255 0OhmIR255 0OhmI

1 2

R230 0OhmIR230 0OhmI

1 2

R229 0OhmIR229 0OhmI

1 2

R226 0OhmIR226 0OhmI

1 2

R227 0OhmIR227 0OhmI

1 2

R225 0OhmIR225 0OhmI

1 2

R224 0OhmIR224 0OhmI

1 2

R223 0OhmIR223 0OhmI

1 2

R221 0OhmIR221 0OhmI

1 2

R209 0OhmIR209 0OhmI

1 2

R208 0OhmIR208 0OhmI

1 2

R118 0OhmIR118 0OhmI

1 2

R204 0OhmIR204 0OhmI

1 2

12

C90

0.1UF/10V

5

4

3

2

1

12

C234

0.1UF/25V

+V_LCD

I

12

GNDGNDGND

C235

C235 1UF/16V

1UF/16V

12

I

1.01 20101019 EMI revised

C236

C236 10PF/50V

10PF/50V NPO 5%

NPO 5% I

I

URN41B

UL25

90OHM/100MHZ/330mA

URN41A

URN43B

UL26

90OHM/100MHZ/330mA

URN43A

URN45B

UL27

90OHM/100MHZ/330mA

URN45A

URN47A

90OHM/100MHZ/330mA

UL28

URN47B

34

1,

Do Not Stuff

IN

14

23

,

12

1,

Do Not Stuff

34

1,

Do Not Stuff

14

23

,

12

1,

Do Not Stuff

34

1,

Do Not Stuff

14

23

,

12

1,

Do Not Stuff

12

Do Not Stuff

1,

,

1 4

2 3

34 Do Not Stuff

Do Not Stuff

1,

IN

LVDS_L3N_MXM [74]

IN

LVDS_LCLKP_MXM [74]

IN

LVDS_LCLKN_MXM [74]

IN

LVDS_L2N_MXM [74]

IN

LVDS_L3P_MXM [74]

LVDS_L2P_MXM [74]

LVDS_L1P_MXM [74]

LVDS_L1N_MXM [74]

բբբբଥଥଥଥޏޏޏޏݙݙݙݙګګګګ

3 4

Do Not Stuff

URN32B

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

3 4

1,

14

1 2

Do Not Stuff

1,

1 2

1,

1 4

3 4

Do Not Stuff

1,

3 4

1,

14

1 2

Do Not Stuff

1,

14

1 2

1,

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL24

UL24

2 3

URN39B

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL20

UL20

2 3

URN31B

Do Not Stuff

23

UL22

UL22 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

URN35A

Do Not Stuff

,

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA UL23

UL23

2 3

URN37B

Do Not Stuff

23

UL21

UL21 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

URN33A

ࣰࣣࣞ࣎࣋࣍࣎

ࣰࣰࣣࣣࣞ࣎࣋࣍࣎ࣞ࣎࣋࣍࣎

Do Not Stuff

URN39A

URN31A

URN35B

URN37A

URN33B

23

UL10

UL10 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

URN32A

LVDS_U0N_MXM[74]

D D

C C

LVDS_U0P_MXM[74]

LVDS_U1N_MXM[74]

LVDS_U1P_MXM[74]

LVDS_U2N_MXM[74]

LVDS_U2P_MXM[74]

LVDS_UCLKN_MXM[74]

LVDS_UCLKP_MXM[74]

LVDS_U3N_MXM[74]

LVDS_U3P_MXM[74]

LVDS_L0N_MXM[74]

LVDS_L0P_MXM[74]

IN

/9'6&211*38

LVDS_U0N_MXM_CON LVDS_U0P_MXM_CON LVDS_U1N_MXM_CON LVDS_U1P_MXM_CON LVDS_U2N_MXM_CON LVDS_U2P_MXM_CON

LVDS_UCLKN_MXM_CON LVDS_UCLKP_MXM_CON LVDS_U3N_MXM_CON LVDS_U3P_MXM_CON LVDS_L0N_MXM_CON LVDS_L0P_MXM_CON

P7

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

WtoB_CON_2X15P

WtoB_CON_2X15P I

I

GND

SIDE2

SIDE1

32 2

2

4

6

R337 Do Not StuffNIR337 Do Not StuffNI

8

1 2

8

10

12

14

16

18

20

22

24

26

28

30

31

GND

Adjust value on 5/31

12

C233

2.2PF/50V

I

LVDS_L3P_MXM_CON LVDS_L3N_MXM_CON LVDS_LCLKP_MXM_CON LVDS_LCLKN_MXM_CON LVDS_L2P_MXM_CON LVDS_L2N_MXM_CON LVDS_L1P_MXM_CON LVDS_L1N_MXM_CON

12

1,

CB21

CB21 Do Not Stuff

Do Not Stuff mx_c0603_small

mx_c0603_small Y5V +80-20%

Y5V +80-20%

+V_LCD

12

1,

CB22

CB22 Do Not Stuff

Do Not Stuff mx_c0603_small

mx_c0603_small Y5V +80-20%

Y5V +80-20%

GND

B B

$9%RDUGFRQQHFWRU

3 4

Do Not Stuff

URN105B

1,

14

1 2

Do Not Stuff

1,

3 4

1,

Do Not Stuff

14

1 2

1,

3 4

1,

Do Not Stuff

14

1 2

1,

3 4

1,

Do Not Stuff

14

1 2

1,

3 4

,

0

14

1 2

,

23

UL34

UL34 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

URN105A

URN106B

23

UL35

UL35 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

Do Not Stuff

URN107B

23

UL36

UL36 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

Do Not Stuff

URN108B

23

UL37

UL37 90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

,

Do Not Stuff

URN109B

23

UL38

UL38 Do Not Stuff

Do Not Stuff

1,

0

URN106A

URN107A

URN108A

URN109A

HDMI_CLKP_GPU[71]

HDMI_CLKN_GPU[71]

HDMI_TXP0_GPU[71]

HDMI_TXN0_GPU[71]

HDMI_TXP1_GPU[71]

HDMI_TXN1_GPU[71]

HDMI_TXP2_GPU[71]

A A

HDMI_TXN2_GPU[71]

HDMI_DDC_CLK[71]

HDMI_DDC_DAT[71]

5

EMI

HDMI_CLKP_GPU_R

HDMI_CLKN_GPU_R

HDMI_TXP0_GPU_R

HDMI_TXN0_GPU_R

HDMI_TXP1_GPU_R HDMI_TXN1_GPU_R HDMI_TXP2_GPU_R HDMI_TXN2_GPU_R

ଥଥଥଥޏޏޏޏ

*38

HDMI_DDC_CLK_R

HDMI_DDC_DAT_R

UART_TX[15,43]

UART_RX[15,43] V_UP[15,17,35] V_DOWN[15,17,35] SLP_S3#[15,20,43,44]

&KHFNLIZHQHHGFRPSRUW

4

OUT IN IN IN IN

R352 0O hmIR352 0O hmI R355 0O hmIR355 0O hmI R357 0O hmIR357 0O hmI

1 2 1 2 1 2

+3P3V

բբբբଥଥଥଥޏޏޏޏ آآآآݙݙݙݙګګګګ

+V_LCD

12

C237

0.1UF/10V

GND

5VSB_CN26

GPU_PANEL_ID0 GPU_PANEL_ID1

3VSB_CN26

2668_DETECT_N_GPU _R 2668_LVDD_EN_GPU_R 2668_BK_ENA_GPU_R 2668_BK_PWM_GPU_R PC_MODE_GPU_R AV_MODE_GPU_R AUDIO_INDICATE_GPU_R AUDIO_MUTE_GPU_R PC_STATUS_GPU_R INR_GPU_R

INL_GPU_R

SPDIF-OUT_GPU_R

1.01 20101019 EMI revised

Adjust value on 5/31

12

C238

C238 Do Not Stuff

Do Not Stuff

I

NPO 5%

GND GND GND

NI

IN

BACKLIGHT_DOW N [15,19,35,79]

R344 0OhmIR344 0OhmI

1 2

R343 0OhmIR343 0OhmI

1 2

R345 0OhmIR345 0OhmI

1 2

R347 0OhmIR347 0OhmI

1 2

R346 0OhmIR346 0OhmI

1 2

R348 0OhmIR348 0OhmI

1 2

R350 0OhmIR350 0OhmI

1 2

R349 0OhmIR349 0OhmI

1 2

R351 0OhmIR351 0OhmI

1 2

R354 0OhmIR354 0OhmI

1 2

R353 0OhmIR353 0OhmI

1 2

R356 0OhmIR356 0OhmI

1 2

R358 0OhmIR358 0OhmI

1 2

R359 0OhmIR359 0OhmI

1 2

2

R339

R340

2.2KOHM

2.2KOHM I

I

1 2

I

I 5%

5%

1 2

5%

BACKLIGHT_UP[15,19,35,79]

12

C245

C44253

Do Not Stuff

NI

12

C44254

C44254 Do Not Stuff

Do Not Stuff

NI

GNDGND GNDGND GNDGND

GNDGND

12

C248

C248 Do Not Stuff

Do Not Stuff

NI

12

C246

C246 Do Not Stuff

Do Not Stuff

NI

IN

AP_VOLUME_DOWN_GPU_R

AP_VOLUME_UP_GPU_R

12

C247

C247 Do Not Stuff

Do Not Stuff

NI

12

C250

C249

Do Not Stuff

NI

1.01 20101020 EMI revised

3

GPIO208_GPU_N

CN26

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

GND GNDGND

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 SIDE141SIDE2

Do Not Stuff

Do Not Stuff NI

NI

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

C241

2.2PF/50V

I

Modified for Scalar ap plication on 5/26

Modified on 4/6

+5VSB

+5V

12

I

12

0Ohm

R341

1.01 20101019 EMI revised

12

C239

C239 1UF/16V

1UF/16V X7R 10%

X7R 10% I

I

IN

PANEL_ID_0_R [14,15,19,79]

IN

PANEL_ID_1_R [14,15,19,79]

IN

AVIN_DET# [14,15,19,36]

IN

SCL_LCDEN [14,15]

IN

SCL_Bl_EN [14,15]

IN

SCL_Bl_PWM [14,15]

IN

PC_MODE [15,17]

IN

AV_MODE [15,17]

IN

AUDIO_INDICATE [15,29,32]

IN

AUDIO_MUTE [15,31]

IN

PC_STATUS [15,19]

IN

INR [15,32]

IN

INL [15,32]

IN

SPDIF-OUT [15,29]

NI

NI Do Not Stuff

Do Not Stuff

R37575

+3P3VSB

C240

C240 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5% NI

NI

+3P3V

12

I

I 0Ohm

0Ohm

R342

12

C242

0.1UF/10V

0.1UF/10V I

I

GND GND Modified on 5/20

PEGATRON CORPORATION

Size Project Name

A2

Date: Sheet

NI

NI Do Not Stuff

Do Not Stuff

R37576

C243

0.1UF/10V

0.1UF/10V I

I

1.01 20101019 EMI revised

12

C244

C244 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5% NI

NI

Title :

Engineer:

,336%)$

1

/9'6&21

Mike Yen

16 79Wednesday, Apr il 27, 2011

Rev

1.01

of

5

Strapping Options Flash

127(

SATA1GP /GPIO19

00

D D

C C

10

+3P3V

I2C/en(dis)able/S3 for accelerometer

B B

A A

11

Boot DeviceGNT1#

,

;<

Crystal Holder

5

LPC

PCI

SPI

SMB_CLK[27,45] SMB_DATA[27,45]

SRTCRST#[39]

3 4 7 8 1 2 1 2

SML1_CLK[13] SML1_DATA[13]

RTCRST#[39]

CK_33M_PCIFB[22]

8.2KOHM

5%

8.2KOHM

5%

I

8.2KOHM

5%

I

I 5%

5%

I

I I

I

+3P3VSB

RN5023B

RN5023B RN5026D

RN5026D RN5026A

RN5026A RN5022A

RN5022A

+3P3V

12

PC_MODE[15,16] AV_MODE[15,16]

V_DOWN[15,16,35]

SR5

2.7K

1,

SC1

SC1 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

12

V_UP[15,16,35]

,

SC8

SC8 18PF/50V

18PF/50V NPO 5%

NPO 5%

12

1,

SR4

SR4 Do Not Stuff

Do Not Stuff

1 2 5 6 5 6 5 6 3 4 7 8 7 8 7 8

12

,

SR6

2.7K

12

1,

SC2

SC2 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

,

Y5

32.768Khz

1

GND GND

324

4

8.2KOHM

5%

8.2KOHM

5%

I

8.2KOHM

5%

I

8.2KOHM

5%

I

8.2KOHM

5%

I

8.2KOHM

5%

I

8.2KOHM

5%

I

I 5%

5%

I

I I

I

3

4

+3P3V

12

1 2

4

GND GNDGND

12

1,

SR3

SR3 Do Not Stuff

Do Not Stuff

RN5025A

RN5025A RN5026C

RN5026C RN5025C

RN5025C RN5022C

RN5022C RN5025B

RN5025B RN5023D

RN5023D RN5025D

RN5025D RN5022D

RN5022D

12

,

SR7

2.2K

12

1,

SC3

SC3 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

GNDGNDGNDGND GNDGND

,

SR15

SR15 10M

10M

mx_r0603_small

Y5_RTC

2

1 2

8.2KOHM

8.2KOHM 5%

5%

5 6

8.2KOHM

8.2KOHM I

I

3 4

8.2KOHM

5%

3 4

8.2KOHM

5%

I

1 2

8.2KOHM

5%

I

5 6

8.2KOHM

5%

I

3 4

8.2KOHM

5%

I

7 8

8.2KOHM

5%

I

I 5%

5%

I

I I

I

12

1,

SR2

SR2 Do Not Stuff

Do Not Stuff

GNDGNDGNDGND

,

SR8

2.2K

1,

SC44

SC44 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

93

SR14

1 2

0

RN5024A

RN5024C

RN5024C RN5026B

RN5026B RN5024B

RN5024B RN5023A

RN5023A RN5023C

RN5023C RN5022B

RN5022B RN5024D

RN5024D

,38. ,38.

1,

SR1

SR1 Do Not Stuff

Do Not Stuff

12

,

SR9

2.2K

12

1,

SC5

SC5 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

,38.

1DWLYH&RUH,38. 1DWLYH&RUH 1DWLYH&RUH

1DWLYH&RUH 1DWLYH&RUH 1DWLYH&RUH

*3,&RUH *3,&RUH *3,&RUH *3,&RUH

12

,

SR10

2.2K

1DWLYH6XV 1DWLYH6XV

12

1,

SC6

SC6 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

PCH_RTCX1

PCH_RTCX2

12

,

SC9

SC9 18PF/50V

18PF/50V NPO 5%

NPO 5%

,

, 8$

8$

AV14

PCIRST#

AV15

PME#

BH8

PAR

BH9

DEVSEL#

BD15

CLKIN_PCILOOPBACK

BF11

IRDY#

BR6

SERR#

BC12

STOP#

BA17

PLOCK#

BC8

TRDY#

BM3

PERR#

BC11

FRAME#

BE2

GNT3#/GPIO55

BU12

GNT2#/GPIO53

AV8

GNT1#/GPIO51

BA15

GNT0#

AV11

REQ3#/GPIO54

BK8

REQ2#/GPIO52

BT5

REQ1#/GPIO50

BG5

REQ0#

BK10

PIRQA#

BJ5

PIRQB#

BM15

PIRQC#

BP5

PIRQD#

BN9

PIRQE#/GPIO2

AV9

PIRQF#/GPIO3

BT15

PIRQG#/GPIO4

BR4

PIRQH#/GPIO5

BT47

SMBCLK

BR49

SMBDATA

BT51

SML0CLK

BM50

SML0DATA

BJ46

SML1CLK/GPIO58

BK46

SML1DATA/GPIO75

BT41

RTCRST#

BN37

SRTCRST#

BR39

RTCX1

BN39

RTCX2

COUGARPOINT

3

C/BE0# C/BE1# C/BE2# C/BE3#

PCI

SMBUS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPI O74

RTC

3

Rev=1.0

SPI

SPI_CS1#

SPI_CS0# SPI_MOSI SPI_MISO

SPI_CLK

BN4 BP7 BG2 BP13

12/6 0200-00JK000--->0200-00KJ000

BF15

AD0

BF17

AD1

BT7

AD2

BT13

AD3

BG12

AD4

BN11

AD5

BJ12

AD6

BU9

AD7

BR12

AD8

BJ3

AD9

BR9

AD10

BJ10

AD11

BM8

AD12

BF3

AD13

BN2

AD14

BE4

AD15

BE6

AD16

BG15

AD17

BC6

AD18

BT11

AD19

BA14

AD20

BL2

AD21

BC4

AD22

BL4

AD23

BC2

AD24

BM13

AD25

BA9

AD26

BF9

AD27

BA8

AD28

BF8

AD29

AV17

AD30

BK12

AD31

BN49

1DWLYH6XV

BU49

1DWLYH6XV

BR46

1DWLYH6XV

AR56 AT57 AU53

,3'.

AT55

,38.

AR54

PCH_SPI_CS1# PCH_SPI_CS0# PCH_SPI_MOSI

PCH_SPI_CLK

2

+3P3VSB +3P3VSB+3P3VSB

12

+3P3VSB

2

,

SR16

SR16 10K

10K

12

1,

SR19

SR19 Do Not Stuff

Do Not Stuff

12

1

12

,

SR17

2.2K

ST39

,

SR18

SR18 10K

10K

12%20

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

,336%)$

SPI_CS0# [45] SPI_MOSI [45] SPI_MISO [45] SPI_CLK [45]

Title :

Engineer:

1

3&,6063,57&

Mike Yen

17 79Wednesday, April 27, 2011

Rev

1.01

of

5

D D

127(

Used for for DMI, PCIe(PCIe 2.0 jitter spec compliant).

12

C C

B B

WLAN

TVT

LAN

PE1_RXN0_WLAN[37] PE1_RXP0_WLAN[37] PE1_TXN0_WLAN[37] PE1_TXP0_WLAN[37]

PE1_RXN1_TV[38] PE1_RXP1_TV[38] PE1_TXN1_TV[38] PE1_TXP1_TV[38]

PCIE_RXN4_LAN[27]

PCIE_RXP4_LAN[27] PCIE_TXN4_LAN[27] PCIE_TXP4_LAN[27]

GND GND

for H61,

A A

PCIe ports 7 and 8 are disabled.

5

4

DMI_TXN0[6] DMI_TXP0[6 ] DMI_RXN0[6] DMI_RXP0[6]

DMI_TXN1[6] DMI_TXP1[6 ] DMI_RXN1[6] DMI_RXP1[6]

DMI_TXN2[6] DMI_TXP2[6 ] DMI_RXN2[6] DMI_RXP2[6]

DMI_TXN3[6] DMI_TXP3[6 ] DMI_RXN3[6] DMI_RXP3[6]

12

,

SR36

SR37

10K

127(

trace length < 450 mils

SC29 0.1UF/16V X7R 10%

,

, ,

,

, ,

,

, ,

,

12

SC32 0.1UF/16V X7R 10%

12

SC33 0.1UF/16V X7R 10%

12

SC34 0.1UF/16V X7R 10%

12

SC15 0.1UF/16V X7R 10%

12

SC16 0.1UF/16V X7R 10%

12

ST16

12%20

ST14

12%20

ST13

12%20

ST15

12%20

ST9

12%20

ST10

12%20

ST11

12%20

ST12

12%20

4

+1P05V_PCH

12

DMICOMP

DMI2RBIAS

12

GND

PE1_TXN0_WLAN_C PE1_TXP0_WLAN_C

PE1_TXN1_TV_C PE1_TXP1_TV_C

PCH_PE1_TXN1_C PCH_PE1_TXP1_C

TP_PCH_RN7

1

TP_PCH_RP7

1

TP_PCH_TN7

1

TP_PCH_TP7

1

TP_PCH_RN8

1

TP_PCH_RP8

1

TP_PCH_TN8

1

TP_PCH_TP8

1

,

SR30

49.9

49.9 1%

1%

,

SR31

SR31 750

750 1%

1%

8%

D33 B33

J36

H36

A36 B35 P38 R38

B37 C36 H38

J38

E37 F38 M41 P41

P33 R33

B31 E31

A32

J20 L20 F25 F23

P20 R20 C22 A22

H17

J17 E21 B21

P17 M17 F18 E17

N15 M15 B17 C16

J15 L15 A16 B15

J12 H12 F15 F13

H10

J10 B13 D13

COUGARPOINT

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

CLKIN_DMI_N CLKIN_DMI_P

DMI

DMI_IRCOMP DMI_ZCOMP

DMI2RBIAS

PCIE

PERn1 PERp1 PETn1 PETp1

PERn2 PERp2 PETn2 PETp2

PERn3 PERp3 PETn3 PETp3

PERn4 PERp4 PETn4 PETp4

PERn5 PERp5 PETn5 PETp5

PERn6 PERp6 PETn6 PETp6

PERn7 PERp7 PETn7 PETp7

PERn8 PERp8 PETn8 PETp8

3

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

USB

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

CLKIN_DOT_96N CLKIN_DOT_96P

USBRBIAS#

USBRBIAS

3

BF36 BD36

BC33 BA33

BM33 BM35

BT33 BU32

BR32 BT31

BN29 BM30

BK33 BJ33

BF31 BD31

BN27 BR29

BR26 BT27

BK25 BJ25

BJ31 BK31

BF27 BD27

BJ27 BK27

BM43 BD41 BG41 BK43 BP43 BJ41 BT45 BM45

BD38 BF38

BP25 BM25

,3'. ,3'.

1DWLYH6XV 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV

USBRBIAS

12

GND

OC6#/GPIO10 OC7#/GPIO14

12

,

SR33

SR33 10K

10K

GNDGND

127(

,

SR35

trace length < 200 mils

22.6

22.6 1%

1%

2

USBN0 [35] USBP0 [35]

USBN1 [35] USBP1 [35]

USBN2 [34] USBP2 [34]

USBN3 [34] USBP3 [34]

USBN4 [34] USBP4 [34]

USBN5 [34] USBP5 [34]

USBN8 [39] USBP8 [39]

USBN9 [78] USBP9 [78]

USBN_Web [39]

USBP_Web [39]

OC01# [35] OC23# [34] OC48# [34]

7 8

8.2KOHM

1 2 5 6

I

3 4

I I I

side x2

Rear x4

Touch Panel

CARD READER

Web Can

+3P3VSB

12

R37567D

R37567D R37567A8.2KOHMIR37567A8.2KOHM R37567C8.2KOHMIR37567C8.2KOHM R37567B8.2KOHMIR37567B8.2KOHM

86%'HEXJSRUW

R179 0 Ohm IR179 0 Ohm I R178 0 Ohm IR178 0 Ohm I

R181 Do Not StuffNIR181 Do Not Stuff NI R180 Do Not StuffNIR180 Do Not Stuff NI

,

SR32

SR32 10K

10K

86%'HEXJSRUW

1 2 1 2

127(

Used for integrated graphics, generate USB backbone,

24MHz HDA bit, and 48MHz clock.

,

SR34

SR34 10K

10K

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

2

Date: Sheet

USBN10 [37] USBP10 [37]

HUB_USBN10 [33] HUB_USBP10 [33]

,336%)$

1

Title :

Engineer:

1

WL

HUB

3&,(86%'0,

Mike Yen

of

18 79Wednesday, April 27, 2011

Rev

1.01

5

127(

SR40 SR41

INI

NI I

D D

SR41 0

1 2

,

1 2 1 2 1 2 1 2

,

3 4 7 8 3 4 7 8 5 6 5 6 1 2 1 2

CLPWD#[39]

PC_STATUS[15,16]

5

10KOHM

10KOHM 10KOHM

10KOHM

5%

5% 10KOHM

10KOHM

5%

I

I 10KOHM

10KOHM

5%

I

I 10KOHM

10KOHM

5%

I

I 10KOHM

10KOHM

5%

I

I 10KOHM

10KOHM

5%

I

I 10KOHM

10KOHM

5%

I

I 5%

5%

I

I I

I

RN5027B

RN5027B RN5027D

RN5027D RN5028B

RN5028B RN5028D

RN5028D RN5028C

RN5028C RN5027C

RN5027C RN5027A

RN5027A RN5028A

RN5028A

PCH_PWROK[20,43]

+3P3V

C C

B B

+3P3V

SR59 10K

,

SR56 10K

,

SR57 10K

,

SR58 10K

,

A A

PANEL_ID_2_R[14,79]

SDATAOUT0/GPIO39

Description

iAMT

non iAMT

TOUCH_EN[39] BACKLIGHT_UP[15,16,35,79] BACKLIGHT_DOWN[15,16,35,79]

GND

12

12%20

12%20 12%20

12%20

1,

SC30

SC30 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

4

1 2

4

ST24

ST24 ST25

ST25 ST26

ST26 ST27

ST27

1,

SR69

SR69 Do Not Stuff

Do Not Stuff

,38,3' ,38,3'

PCH_MEPWROK

TP_PCH_PWM0

1

TP_PCH_PWM1

1

TP_PCH_PWM2

1

TP_PCH_PWM3

1

,38. ,38. ,38. ,38. ,38. ,38. ,38. ,38.

GND

GND GND

1,

SR71

SR71 Do Not Stuff

Do Not Stuff

1 2

GNDGND

1DWLYH&RUH 1DWLYH&RUH

SST

12

1,

SC31

SC31 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

12

,

SR38

SR38 10K

10K

*3,&RUH *3,&RUH *3,&RUH *3,&RUH *3,&RUH *3,&RUH

,3'.

*3,&RUH *3,&RUH *3,&RUH *3,&RUH

12

SR39

SR39 10K

10K

BA50

BF50 BF49

BC46

BN21

BT21 BM20 BN19

BT17 BR19 BA22 BR16 BU16 BM18 BN17 BP15

BC43

BA53 BE54

BF55

AW53

AF55 AG56

,

AY20

8&

COUGARPOINT

CLINK

CL_CLK1 CL_DATA1 CL_RST1#

APWROK

FAN

PWM0 PWM1 PWM2 PWM3

TACH0/GPIO17 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

SST

GPIO

SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48

CLKIN_SATA_N CLKIN_SATA_P

NC_1

3

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP/GPIO16 SATA5GP/GPIO49

SATAICOMPI

SATAICOMPO

SATA3COMPI

SATA3RCOMPO

SATALED#

TP16

SATA3RBIAS

HOST

A20GATE

INIT3_3V#

RCIN#

SERIRQ

THRMTRIP#

PECI

PMSYNCH

3

AC56 AB55 AE46 AE44

AA53 AA56 AG49 AG47

AL50 AL49 AL56 AL53

AN46 AN44 AN56 AM55

AN49 AN50 AT50 AT49

AT46 AT44 AV50 AV49

*3,&RUH

BC54

*3,&RUH

AY52

*3,&RUH

BB55

*3,&RUH

BG53

*3,&RUH

AU56

*3,&RUH

BA56

127(

trace length

< 450 mils

AJ55 AJ53

AE54 AE52

2'

BF57

AE50

SATA3RBIAS

AC52

BB57

,38.

BN56 BG56 AV52 E56 H48

,3'.

F55

,38. ,3'. ,3'.

SATAICOMP

SATA3COMP

12

GND

INIT3_3V#

SATA2GP_GPIO36 SATA3GP_GPIO37 SATA4GP_GPIO16

+1P05V_PCH

12

,

SR66

37.4

37.4 1%

1%

127(

trace length < 450 mils

,

SR70

SR70 750

750 1%

1%

12

1,

SR79

SR79 Do Not Stuff

Do Not Stuff

+3P3V

GND

GPU_TRIP#[43,54,69]

SATA_RXN0 [26] SATA_RXP0 [26]

SATA_TXN0 [26] SATA_TXP0 [26]

SATA_RXN1 [26] SATA_RXP1 [26]

SATA_TXN1 [26] SATA_TXP1 [26]

SFA1.02

+1P05V_PCH

12

,

SR67

49.9

49.9 1%

1%

GND GND

127(

trace length < 200 mils

+3P3V +3P3V

+3P3V

12

1 2

SR304 Do Not Stuff

,

SR74

SR74 10K

10K

,

SR72

SR72 10K

10K

1

G

1,

2

PANEL_ID_0_R [14,15,16,79]

PANEL_ID_1_R [14,15,16,79]

1

SFA1.04

,

SR6010K

12

SR6110K

12

,

SR62Do Not Stuff1,SR62Do Not Stuff

12

1,

SR63Do Not Stuff1,SR63Do Not Stuff

12

1,

,

SR6410K

12

SR6510K

12

,

12

R37602

12

,

12

,

SR73

SR73 10K

10K

Q9359

Q9359 Do Not Stuff

Do Not Stuff

1,

,

SR298

SR298 10K

10K

SR138

SR138 10K

10K

3

D

S

2

R37602

0 Ohm

0 Ohm I

I

+3P3V

12

,

SR68

SR68 10K

10K

A20GATE [43]

RST_KB# [43]

SERIRQ [43]

H_THMTRIP# [7,54] PECI_PCH [7] PM_SYNC [7]

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

,336%)$

+3P3V

AVIN_DET# [14,15,16,36]

HD_LED# [41]

Title :

Engineer:

1

SFA1.02

6$7$+267)$1

Mike Yen

of

19 79Wednesday, April 27, 2011

Rev

1.01

5

+3P3V

1,

+3P3V

12

1,

D D

LPC_FRAME#[43,44]

HDA_SYNC

127(

1,

SR81

SR81 Do Not Stuff

Do Not Stuff

1,

SR80

SR80 Do Not Stuff

Do Not Stuff

1 2

LDRQ1#_GPIO23

LAD0[43,44] LAD1[43,44] LAD2[43,44] LAD3[43,44]

On-die PLL VR voltage selector.

Hi: supplied by 1.5V.

Low: supplied by 1.8V.

HDA_SDO

127(

SFA 1.01A

Disable ME in Manufacturing Mode

C C

--> connect to 3.3VSB.

AZ_SDATA_OUT[29]

AZ_SYNC[29]

AZ_BITCLK[29]

AZ_RST#[29]

J3106:23

MINI_JUMPER

I

12

1,

SC35

SC35 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

GND GND GND GND

TBD

CRB 0.7 is 1.1K ohm with 1%

For platform not supporting deep sleep connect directly to RSMRST#.

The DSW rails must be stable for at least 10 ms

B B

before DPWROK is asserted to PCH.

VRM_PWRGD[43,54,58,64]

CPUPWRGD[7,64] DRAM_PWROK[7] PCH_PWROK[19,43]

SYS_PWROK[43]

SYS_RESET_DBR#[7,63,64]

A A

SLP_SUS#

1 2

PM_RSMRST#[43]

DPWROK[43,63]

1,

SR191

Do Not Stuff

12

1,

SR96

SR96 Do Not Stuff

Do Not Stuff

PLTRST#[13,43,54,63]

B

1

B

1

AZ_SDATA_IN0[29]

GND

5

12

3

C

E

E 2

2

+3P3VSB

1,

SC36

SC36 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

1,

12

93

93 93

93 1,

1,

SQ3

SQ3 Do Not Stuff

Do Not Stuff

HEADER_1X3P

I

GND

12

1,

SC37

SC37 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

SR186 Do Not Stuff

1 2

12

1,

,

SC40

SR97

Do Not Stuff

10K

X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

GND GNDGNDGND

SR134 0

1 2

SR137 0

1 2

SR143 Do Not Stuff

1 2

+3VA

12

1,

SR190

SR190 Do Not Stuff

Do Not Stuff

RSMRST_CUTOFF

J3106

213

SR113 Do Not Stuff

1,

SR85 33

,

SR86 33

,

SR87 33

,

SR88 33

,

1,

SC38

SC38 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

12%20

+3P3VSB

1 2

ST32

1 2

1,

1 2

,

PCH_JTAG_TMS[63] PCH_JTAG_TDO[63] PCH_JTAG_TDI[63] PCH_JTAG_TCK[63] PCH_JTAG_RST[63]

+3P3VSB

12

ST30

12%20

ST31

12%20

J3106

TBD: Both are 390Kohm in CRB 0.7

12

1,

SC41

12

Do Not Stuff

,

NPO 5%

SR144

SR144 10K

10K

12

1,

SR84

SR84 Do Not Stuff

Do Not Stuff

SQ8_C

1,

3

SQ8

C

Do Not Stuff

B

1

B

1

E

E 2

2

GND

1 1 1

GND

,

SR182

SR182 10K

10K

+BATT

12

4

TP_PCH_SDIN1 TP_PCH_SDIN2 TP_PCH_SDIN3

SR82 Do Not Stuff

SR82 Do Not Stuff SR83 1K

SR83 1K

HDA_SDO_R

HDA_SYNC_R

HDA_BITCLK_24MHZ_R

HDA_AZRST#_R

1,

SC53

SC53 Do Not Stuff

Do Not Stuff

+BATT+3P3V

12

,

SR92

SR94

390K

DSWVRMEN PCH_INTVRMEN

PCH_RSMRST#

PCH_DPOWEROK

12

1,

SC42

SR93

Do Not Stuff

NPO 5%

12

GNDGND

GND

4

1DWLYH&RUH,38.

,38. ,38. ,38. ,38.

,38.

,3'. ,3'. ,3'. ,3'.

,3'.

,38.

,38. ,3'.

12

1,

SC54

SC54 Do Not Stuff

Do Not Stuff

GND

NPO 5%

,

SR95

SR95 100K

100K

GND

BA20

BK15

BG20

BK17

BG17

BD22

BK22

BP23

BU22

BC22

BC50

BC52 BA43 BC49

BG46

BR42 BN41 BK48 BE52

BK38

12

,

SR98

SR98 100K

100K

BJ17 BJ20

BF22

BJ22

BT23

BF47

BJ38 BJ53

BT37

D53

8'

LPC

LDRQ1#/GPIO23

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

FWH4/LFRAME#

AUDIO

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_SYNC

HDA_BCLK

HDA_RST#

JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK TP12

PROCPWRGD DRAMPWROK PWROK SYS_PWROK

DSWVRMEN INTVRMEN PLTRST# SYS_RESET#

RSMRST# DPWROK

COUGARPOINT

3

BMBUSY#/GPIO0

CLKRUN#/GPIO32

HDA_DOCK_EN#/GPIO33

STP_PCI#/GPIO34

GPIO35

LAN_PHY_PWR_CTRL/G PIO12

HDA_DOCK_RST#/GPIO13

PCIECLKRQ2#/GPIO20 PCIECLKRQ5#/GPIO44 PCIECLKRQ6#/GPIO45 PCIECLKRQ7#/GPIO46

SUSWARN#/SUSPW RDNACK/GPIO30

GPIO8

GPIO15

GPIO24/MEM_LED

GPIO28

SLP_LAN#/GPIO29

GPIO27 GPIO31

GPIO57

BATLOW#/GPI O72

SUSACK#

SUSCLK/GPIO62

SUS_STAT#/GPIO61

127(

SUSACK# and SUSWARN#

can be tied together if EC/SIO

does not want to involve in

the handshake mechanism

for the Deep Sleep state

entry and exit.

WAKE#

INTRUDER#

SPKR

PWRBTN#

SLP_S3# SLP_S4#

SLP_S5#/GPIO63

SLP_A#

SLP_SUS#

3

2

127(

+3P3V

PDG 0.7 is 1Kohm

12

,

SR100

SR100 10K

10K

*3,&RUH

AW55 BC56 BC25 BL56 BJ57 BP51 BK50 BA25 BM55 BP53 BJ55 BH49 BJ43 BG43

AV43 BL54 AV44 BP55 BT53

AV46

BU46

BP45

BA47

BN54

BJ48

RI#

BC44

BM38

BE56

BT43

BM53 BN52 BH50 BC41 BD43

*32&RUH *32&RUH *3,&RUH *32&RUH *326XV 1DWLYH6XV *3,6XV *326XV *326XV *326XV *3,6XV *3,'6: *3,'6:

1DWLYH&RUH 1DWLYH6XV 1DWLYH6XV 1DWLYH6XV *3,6XV

*3,'6:

,387%'

1DWLYH6XV

,3'.

,38.

1DWLYH6XV

2

CLKRUN#_GPIO32 HDA_DOCK_EN#_GPIO33 STP_PCI#_GPIO34

,38.

,3'.

GPIO24_MEM_LED

,38.

GPIO27

,38. ,3'7%'

PCIECLKRQ2#_GPIO20

,387%' ,38. ,38.

,38.1DWLYH6XV

PCH_SUSWARN#

,

PCH_SUSACK#

SUSCLK_GPIO62

12

1,

SR183

SR183 Do Not Stuff

Do Not Stuff

GND

modem_wake_event

INTRUDER#

PCH_PWRBTN#

SLP_A#

12

1,

,

SR101

SR300

Do Not Stuff

10K

SR305 Do Not Stuff

12

1,

SR111

SR155

Do Not Stuff

GND GND

GND

+3P3VSB

12

,

SR124

SR124 10K

10K

SR158 0

1 2

12

1,

SC45

SC45 Do Not Stuff

Do Not Stuff NPO 5%

NPO 5%

GND

+3P3VSB +3P3V+BATT +3P3VSB

12

,

SR75

SR75 10K

10K

1

1,

12

1,

SR112

SR112 Do Not Stuff

Do Not Stuff

+3VA

12

1,

SR159

SR159 Do Not Stuff

Do Not Stuff

12

,

SLP_S3# [15,16,43,44] SLP_S4# [43,44]

ST36

SLP_SUS# [43]

2

+3P3VSB +3VA

12

,

1,

SR301

SR106

10K

Do Not Stuff

12

+3P3V

12

,

SR116

SR115

10K

TBD

1,

1

12

1,

SR117

SR133

Do Not Stuff

GND GND

SR123 Do Not Stuff

1 2

SR132 Do Not Stuff

ST38

12%20

127(127(

PIN HIGH LOW DESCRIPTION

GPIO15

GPIO28

12

,

SR76

SR76 1M

1M

,

SR77

SR77 1K

1K

SR139 0

12%20

12

1,

SR107

SR107 Do Not Stuff

Do Not Stuff

12

1,

SR108

SR108 Do Not Stuff

Do Not Stuff

12

,

SR109

SR109 10K

10K

12

,

SR110

SR110 10K

10K

1,

127(

+3P3VSB

12

GND

12

,

SR118

SR118 10K

10K

1,

SR256

SR256 Do Not Stuff

Do Not Stuff

GPIO27 can be configured as wake input

to allow wakes from Deep Sleep.

12

,

SR119

SR129

10K

12

1,

SR180

SR130

Do Not Stuff

GNDGND

PCH_SUS_WARN# [43]

SUS_ACK# [43]

Enable Disable TLS confidentiality

Enable Disable On-Die PLL VR

12

1,

SR78

SR78 Do Not Stuff

Do Not Stuff

PCIE_WAKE# [27,37,38]

SPKR [29]

PM_PWRBTN# [43]

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

,336%)$

1

+3P3VSB

12

,

SR303

SR302

10K

SHUT_DOWN# [29,31] PM_CLKRUN# [43] AMP_GAN0 [31]

AMP_GAN1 [31]

EXT_SMI# [43] EXT_SCI# [43]

SR114 Do Not Stuff

1

Market_ID [39]

ST37

12

12%20

SKTOCC# [7]

127(

External PU resistor required

if used for CLKREQ# functionality.

WLAN_CLKREQ# [37] TVT_CLKREQ# [38]

LED_PWREN [41]

$8',2/3&0,6&

Title :

Engineer:

Mike Yen

of

20 79Wednesday, April 27, 2011

1

20 79Wednesday, April 27, 2011

Rev

1.01

5

8(

Y18

TP6

Y17

TP7

AB18

TP8

AB17

TP9

R393 0 Ohm 5%

R393 0 Ohm 5% R389 0 Ohm 5%

ST72

ST72 ST73

ST73

ST76

ST76 ST77

ST77

R389 0 Ohm 5%

TP_PCH_DDPBAUXP

1

TP_PCH_DDPBAUXN

1

TP_PCH_DDPDAUXP

1

TP_PCH_DDPDAUXN

1

C57 0.1UF/10V

C57 0.1UF/10V C58 0.1UF/10V

C58 0.1UF/10V

VGA_DDCA_CLK[65,74] VGA_DDCA_DATA[65,74]

D D

+3P3V

NR111

NR112

2.2KOHM

NR114

NR118

Do Not Stuff

+3P3V

,

+3P3V

2.2KOHM

12%20

,

12%20

HDMI_HPD_DMC[36]

NR113

2.2KOHM

12%20

,

12%20

HDMI_HPD_PCH[36]

1,

DP_AUX_PCH_D[79]

DP_AUX#_PCH_D[79]

SFA 1.01A

2.2KOHM

R236 0O hm

1 2

,

HDMI_CLK_DMC[37] HDMI_DATA_DMC[37]

C C

R237 0O hm

HDMI_CLK_PCH[15]

HDMI_DAT_PCH[15]

,

1 2

,

2.2KOHM

SFA 1.01A

To enable portD

R240 0O hm

1 2

,

EDP_HPD_PCH_D[36,79]

B B

1 2 1 2

12

,

5%

5% 100KOHM

100KOHM SR120

SR120

GND

12

,

5%

5% 100KOHM

100KOHM SR121

SR121

GND

12 12

1,

12

5%

5% Do Not Stuff

Do Not Stuff SR122

SR122

GND

,3'.

,

AW3

,

AW1

R8 R9

AL15 AL17

T1

U14 U12

AL12 AL14

N2

N6

,

R6

,

AL9 AL8

M1

CRT_DDC_CLK CRT_DDC_DATA

DDPB_AUXP DDPB_AUXN

SDVO_CTRLCLK SDVO_CTRLDATA

DDPB_HPD

DDPC_AUXP DDPC_AUXN

DDPC_CTRLCLK DDPC_CTRLDATA

DDPC_HPD

DDPD_AUXP DDPD_AUXN

DDPD_CTRLCLK DDPD_CTRLDATA

DDPD_HPD

COUGARPOINT

,

4

CRT_HSYNC CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

DAC_IREF

CRT_IRTN

DDPB_0P DDPB_0N DDPB_1P DDPB_1N DDPB_2P DDPB_2N DDPB_3P DDPB_3N

SDVO_INTP SDVO_INTN

SDVO_STALLP SDVO_STALLN

SDVO_TVCLKINP

SDVO_TVCLKINN

DDPC_0P DDPC_0N DDPC_1P DDPC_1N DDPC_2P DDPC_2N DDPC_3P DDPC_3N

DDPD_0P DDPD_0N DDPD_1P DDPD_1N DDPD_2P DDPD_2N DDPD_3P DDPD_3N

3

R396

VGA_HSYNC_3P3V

AR4

VGA_VSYNC_3P3V

AR2

VGA_RED_S

AN6

VGA_GREEN_S

AN2

VGA_BLUE_S

AM1

12

1,

SC50

SC50 Do Not Stuff

Do Not Stuff

12

Place capacitors close to PCH for EMI

DACREFSET

AT3

AM6

GND

,3' ,3'

,3'

DDPC_0P DDPC_0N DDPC_1P DDPC_1N DDPC_2P DDPC_2N DDPC_3P DDPC_3N

DDPB_0P DDPB_0N DDPB_1P DDPB_1N DDPB_2P DDPB_2N DDPB_3P DDPB_3N

SDVO_INTP SDVO_INTN

SDVO_STALLP SDVO_STALLN

SDVO_TVCLKINP

SDVO_TVCLKINN

R14 R12 M11 M12 H8 K8 L5 M3

U2 T3

W3 U5

U8

U9

L2 J3 G2 G4 F3 F5 E4 E2

D5 B5 C6 D7 B7 C9 E11 B11

C32 0.1UF/10V

C32 0.1UF/10V C33 0.1UF/10V

C33 0.1UF/10V C34 0.1UF/10V

C34 0.1UF/10V C35 0.1UF/10V

C35 0.1UF/10V C36 0.1UF/10V

C36 0.1UF/10V C37 0.1UF/10V

C37 0.1UF/10V C38 0.1UF/10V

C38 0.1UF/10V C39 0.1UF/10V

C39 0.1UF/10V

1 1

1

DP2_PCH_D DP2#_PCH_D DP3_PCH_D DP3#_PCH_D

12

GND

ST78

ST78 ST79

ST79

ST83

ST83 ST84

ST84

ST85

ST86

JP20 Do Not Stuff

JP21 Do Not Stuff

JP22 Do Not Stuff

12

1,

SC51

SC52

Do Not Stuff

GNDGND GND

,

SR131

Replace DACREFSET resistor

1K

close to PCH within 500mils

1%

R205 0O hm

12

,

1 2

R206 0O hm

12%20

12%20 12%20

12%20

12%20 12%20

12%20

ST96

ST96 ST97

ST97 ST98

ST98 ST99

ST99

1 2

,

R207 0O hm

1 2

,

R210 0O hm

1 2

,

R211 0O hm

1 2

,

R212 0O hm

1 2

,

R213 0O hm

1 2

,

R214 0O hm

1 2

,

12%20

12%20 12%20

12%20

12 12 12 12 12 12 12

1 1 1 1

1 2

,

, ,

,

HDMI_TXP2_PCH [15] HDMI_TXN2_PCH [15]

HDMI_TXP1_PCH [15]

HDMI_TXN1_PCH [15] HDMI_TXP0_PCH [15] HDMI_TXN0_PCH [15]

HDMI_CLKP_PCH [15]

HDMI_CLKN_PCH [15]

EDP0_PCH_D [79] EDP0#_PCH_D [79]

EDP1_PCH_D [79] EDP1#_PCH_D [79]

12%20

12

,

SR247

150

150 1%

1%

GND GND GND

127(

R396

SR245 33

1 2

,

SR246 33

1 2

,

VGA_RED_J

VGA_GREEN_J

VGA_BLUE_J

12

,

SR248

SR249

150

1%

R394 0 Ohm 5%

1 2

R395 0 Ohm 5%

1 2

Place RGB resistors close to PCH within 250mils

R220 Do Not Stuff

1 2

1,

R222 Do Not Stuff

1 2

1,

R228 Do Not Stuff

1 2

1,

R217 Do Not Stuff

1 2

1,

R219 Do Not Stuff

1 2

1,

R231 Do Not Stuff

1 2

1,

R216 Do Not Stuff

1 2

1,

R218 Do Not Stuff

1 2

1,

VGA_HSYNC [65,74] VGA_VSYNC [65,74]

,

VGA_RED [65,74]

,

VGA_GREEN [65,74]

0 Ohm 5%

,

VGA_BLUE [65,74]

HDMI_TXP2_DMC [37] HDMI_TXN2_DMC [37]

HDMI_TXP1_DMC [37]

HDMI_TXN1_DMC [37] HDMI_TXP0_DMC [37] HDMI_TXN0_DMC [37]

HDMI_CLKP_DMC [37]

HDMI_CLKN_DMC [37]

HDMI_TXP2_MXM [70] HDMI_TXN2_MXM [70] HDMI_TXP1_MXM [70] HDMI_TXN1_MXM [70] HDMI_TXP0_MXM [70] HDMI_TXN0_MXM [70] HDMI_CLKP_MXM [70] HDMI_CLKN_MXM [70]

2

Digital Display Interface Differential Pairs

DDSP_B_TX0_DN DDSP_B_TX0_DP DDSP_B_TX1_DN DDSP_B_TX1_DP DDSP_B_TX2_DN DDSP_B_TX2_DP DDSP_B_TX3_DN DDSP_B_TX3_DP TMDSB_CLK

DDPB_HPD

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI Signals

TMDSB_DATA2# TMDSB_DATA2 TMDSB_DATA1# TMDSB_DATA1 TMDSB_DATA0# TMDSB_DATA0 TMDSB_CLK#

DDSP_B_HPD0 HDMIB_CTRL_CLK HDMIB_CTRL_DATA

1

PCH Digital Display Interface Pins

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

Hot plug detect used by HDMI Port B.

HDMI DDC lines for Port B

A A

PEGATRON DT-MB RESTRICTED SECRET

0413

PEGATRON CORPORATION

Size Project Name

A2

,336%)$

Date: Sheet

5

4

3

2

Date: Sheet

1

Title :

Engineer:

9*$'3+'0,

Mike Yen

21 79Wednesday, Apr il 27, 2011

of

Rev

1.01

5

FDI_TXN0[6 ] FDI_TXP0[6] FDI_TXN1[6 ] FDI_TXP1[6] FDI_TXN2[6 ] FDI_TXP2[6] FDI_TXN3[6 ]

D D

HR23 4.7K

,

PROC_SEL[7]

,

FDI_TXP3[6] FDI_TXN4[6 ] FDI_TXP4[6] FDI_TXN5[6 ] FDI_TXP5[6] FDI_TXN6[6 ] FDI_TXP6[6] FDI_TXN7[6 ] FDI_TXP7[6]

12

Place HR23 close to NVRAM connector

and minimize this stub to <100 mils

with PCH and NVRAM connector

C C

12

B B

A A

12

GND GND GND

5

12

,

SR125

SR125 10K

10K

GND GND GND GND

SR140

1 2

1MOHM

,

Y12

Y12 25Mhz

25Mhz

,

12

SR142

0

12

GND

1 2

,

SC55

SC55 27PF/50V

27PF/50V NPO 5%

NPO 5%

12

,

SR126

SR127

10K

GND

1%I SR140

1%I

Y10_R

3

12

4

DF_TVS

+1P05V_PCH

PCH_CLKIN_BCLK_GND0# PCH_CLKIN_BCLK_GND0

PCH_CLKIN_DMI2_GND1# PCH_CLKIN_DMI2_GND1

12

,

SR128

SR128 10K

10K

SR157 10K

,

SC56

SC56 27PF/50V

27PF/50V NPO 5%

NPO 5%

4

,3'.

12

,

SR136

90.9

90.9 1%

1%

XCLK_RCOMP

12

XTAL_25M_PCH_IN

XTAL_25M_PCH_OUT

AB46

W53

C42 B43 F45 F43 H41

C46 D47 B45 A46 B47 C49

H43 M43 P43

M48 R47 Y41 M50 M49 U43

G56

K49 K50

Y44 L53

AL2

V52

R27 P27

AN8

AJ3

AJ5

H31

C29 E29

L27 F28 E27

L25 C26 B27 L22

B25 D25

J41

J43

J57

J31

J27

J25

J22

8)

FDI_RXN0 FDI_RXP0 FDI_RXN1 FDI_RXP1 FDI_RXN2 FDI_RXP2 FDI_RXN3 FDI_RXP3 FDI_RXN4 FDI_RXP4 FDI_RXN5 FDI_RXP5 FDI_RXN6 FDI_RXP6 FDI_RXN7 FDI_RXP7

Reserved_001 DF_TVS Reserved_002 Reserved_003 Reserved_004 Reserved_005 Reserved_006

Reserved_007 Reserved_008 Reserved_009 Reserved_010

Reserved_011 Reserved_012

XCLK_RCOMP

CLKIN_GND0_N CLKIN_GND0_P

CLKIN_GND1_N CLKIN_GND1_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

TP21 TP25 TP29 TP33 TP22 TP26 TP30 TP34 TP23 TP27 TP31 TP35 TP24 TP28 TP32 TP36

COUGARPOINT

FDI_FSYNC0 FDI_LSYNC0

FDI_FSYNC1 FDI_LSYNC1

FDI

RSD

Reserved_013 Reserved_014 Reserved_015 Reserved_016 Reserved_017 Reserved_018 Reserved_019 Reserved_020 Reserved_021 Reserved_022 Reserved_023 Reserved_024 Reserved_025 Reserved_026 Reserved_027 Reserved_028

Reserved_029

CLOCK

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE5N

CLKOUT_PCIE5P

CLKOUT_PCIE4N

CLKOUT_PCIE4P

CLKOUT_PCIE3N

CLKOUT_PCIE3P

CLKOUT_PCIE2N

CLKOUT_PCIE2P

CLKOUT_PCIE1N

CLKOUT_PCIE1P

CLKOUT_PCIE0N

CLKOUT_PCIE0P

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

3

FDI_INT

B51 E49

C52 D51

H46

AB50 Y50 AB49 AB44 U49 R44 U50 U46 U44 H50 K46 L56 J55 F53 H52 E52

TP_NV_RCOMP

R50

CLKOUT_ITPXDP#

R52

CLKOUT_ITPXDP

N52

CLKOUT_DMI#

P31

CLKOUT_DMI

R31

TP_CLKOUT_DP#_CLKOUT_BCLK1#

N56

TP_CLKOUT_DP_CLKOUT_BCLK1

M55

AE2 AF1

CLKOUT_PCIE6#

AB3

CLKOUT_PCIE6

AA2

CLKOUT_PCIE5#

AF3

CLKOUT_PCIE5

AG2

TP_CLKOUT_PCIE4#

Y9

TP_CLKOUT_PCIE4

Y8

AB9 AB8

CLKOUT_PCIE2#

AB12

CLKOUT_PCIE2

AB14

AA5 W5

AE6 AC6

CLKOUT_PEG_A#

AG8

CLKOUT_PEG_A

AG9

TP_CLKOUT_PEG_B#

AE12

TP_CLKOUT_PEG_B

AE11

AT11 AN14 AT12 AT17 AT14

AT9 BA5 AW5 BA2

PCH_CLKOUT_PCI0

,3'. ,3'.

PCH_CLKOUT_PCI2

,3'.

PCH_CLKOUT_PCI3

,3'.

PCH_CLKOUT_PCI4

,3'.

PCH_CLKOUTFLEX3_48M

,3'.

TP_CLKOUTFLEX1_GPIO65

,3'.

TP_CLKOUTFLEX2_GPIO66

,3'.

TP_CLKOUTFLEX0_GPIO64

,3'.

1

SR147 0

93

SR148 0

93

SR229 0

93

SR230 0

93

SR153 0

,

SR154 0

,

SR233 0

93

SR234 0

93

SR241 0

93

SR242 0

93

SR235 0

93

SR236 0

93

SR239 0

93

SR240 0

93

FDI_FSYNC_0 [6] FDI_LSYNC_0 [6]

FDI_FSYNC_1 [6] FDI_LSYNC_1 [6]

FDI_IN T [6 ]

ST1

12%20

1 2 1 2

ST40

1

12%20

ST41

1

12%20

ࣰࣣࣞ࣎࣋࣍࣎

1 2 1 2

1 1

SR265 Do Not Stuff

1,

SR264 22 OHM

,

SR266 22 OHM

,

ࣰࣰࣣࣣࣞ࣎࣋࣍࣎ࣞ࣎࣋࣍࣎

ST54

12%20

ST55

12%20

SR262 22 OHM

1 2

,

SR251 22 OHM

1 2

,

1

SR253 22 OHM

1 2

,

ST3

1

12%20

1 2 1 2 1 2

ST56

127(

1.Prioritize 27/14/24/48/25-MHz FLEX on FLEX1/3.

2.Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0/2

if more than 2 PCI clocks + PCI loopback are routed.

3.With 2 PCI clocks routed (or less), prioritize the FLEX clocks to FLEX1/3

a. 27MHz(SSC/non-SSC) b.14.31818MHz c.24/48 d.25MHz

3

2

12%20

2

1

CK_100M_CPUXDP# [64] CK_100M_CPUXDP [64]

CK_100M_DMI# [7] CK_100M_DMI [7]

CLK_100M_MINI4# [38] CLK_100M_MINI4 [38]

CLK_100M_MINI1# [37] CLK_100M_MINI1 [37]

CK_100M_PCHXDP# [63] CK_100M_PCHXDP [63]

FRO REAR I/O MODULE, LAN

CK_100M_LAN# [27] CK_100M_LAN [27]

CLK_PEGA# [73] CLK_PEGA [73]

CLK_DBGPCI1 [44]

CLK_KBCPCI [43]

CK_33M_PCIFB [17]

CK_27M_eDP [79] CK_48M_CR [78] CK_27M_GPU [69]

0413

Date: Sheet

FRO REAR I/O MODULE, USB3.0

PEGATRON DT-MB RESTRICTED SECRET

&/.195$0)',

Title :

PEGATRON CORPORATION

Size Project Name

A3

,336%)$

Title :

Engineer:

Mike Yen

22 79Wednesday, April 27, 2011

1

22 79Wednesday, April 27, 2011

Rev

1.01

of

5

+1P05V_PCH

D D

127(

Splitting 2 power trace/shape

on pin Y20/Y22/V22 to other pins.

C C

127(

Splitting 2 power trace/shape

B B

A A

127(

Install those cap during initial power-on.

,

SCB1

SCB1 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10% mx_c0805_small

mx_c0805_small

12

,

SCB2

SCB2 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10% mx_c0805_small

mx_c0805_small

12

,

SCB5

0.1UF/16V

GND GND

12

,

SCB3

0.1UF/16V

12

SCB6

0.1UF/16V

12

GND GND GND GND

127(

Trace needs to be at least 20 mils width with full VSS/ VCC reference plane

+1P05V_PCH

,

SCB12

SCB12 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10% mx_c0805_small

mx_c0805_small

12

,

SCB10

SCB10 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

GND GND

12

,

SCB11

SCB11 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

12

GND

127(

Install SCB12 during initial power-on.

5

12

,

+1P05V_CPUIO

12

GND

+1P05V_PCH

12

GND

+1P05V_PCH

12

GND

12

GND

+1P05V_PCH

12

GND

,

SCB4

0.1UF/16V

,

SCB7

SCB7 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

SCB8

SCB8 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

SCB9

SCB9 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

1,

SCB16

SCB16 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

1,

SCB13

SCB13 Do Not Stuff

Do Not Stuff

V25 V27 V31 V33 Y24 Y26 Y30 Y32 Y34 V22

AA34 AA36

Y20 Y22

B41 E41

AL40 AN40 AN41

BA38

AG38 AG40 AG41

AJ38

AG24 AG26 AG28

AJ24

AJ26

AJ28

AL24

AL28 AN22 AN24 AN26 AN28 AR24 AR26 AR28 AR30 AR36 AR38 AU30 AU36

AU34 AV36 AU32

8*

F20

VccIO_024

F30

VccIO_025 VccIO_026 VccIO_027 VccIO_028 VccIO_029 VccIO_030 VccIO_031 VccIO_032 VccIO_033 VccIO_034 VccIO_035

VccIO_022 VccIO_023

VccIO_036 VccIO_037

VccDMI_02 VccDMI_01

VccIO_008 VccIO_009 VccIO_010

VccIO_019

VccIO_020 VccIO_021 VccIO_007 VccIO_011

VccASW_004 VccASW_005 VccASW_006 VccASW_007 VccASW_008 VccASW_009 VccASW_010 VccASW_011 VccASW_012 VccASW_013 VccASW_014 VccASW_015 VccASW_016 VccASW_017 VccASW_018 VccASW_019 VccASW_020 VccASW_021 VccASW_022 VccASW_023

VccASW_003 VccASW_002 VccASW_001

COUGARPOINT

4

VccCore_001 VccCore_002 VccCore_003 VccCore_004 VccCore_005 VccCore_006 VccCore_007 VccCore_008 VccCore_009 VccCore_010 VccCore_011 VccCore_012 VccCore_013 VccCore_014 VccCore_015 VccCore_016 VccCore_017 VccCore_018 VccCore_019 VccCore_020 VccCore_021 VccCore_022

VccIO_018 VccSSC_01 VccSSC_02

VccIO_001

VccIO_002

VccIO_003

VccIO_004

VccIO_013

VccIO_012

VccIO_014

VccDIFFCLKN_01 VccDIFFCLKN_02 VccDIFFCLKN_03

VccAFDIPLL

VccAClk

VccAPLLEXP

VccAPLLSATA

VccAPLLDMI2

VccClkDMI

VccADAC

VccADPLLA

VccADPLLB

3

AC24 AC26 AC28 AC30 AC32 AE24 AE28 AE30 AE32 AE34 AE36 AG32 AG34 AJ32 AJ34 AJ36 AL32 AL34 AN32 AN34 AR32 AR34

12

,

SCB14

SCB14 1UF/10V

1UF/10V mx_c0603_small

mx_c0603_small

GND

+1P05V_PCH

12

,

SCB15

SCB15 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10% mx_c0805_small

mx_c0805_small

GND

127(

VccAPLLEXP, VccAPLLSATA, and VccAPLLDMI2 can be NC

in On-Die VR mode.

1,

SR168

Do Not Stuff

127(

+1P05V_PCH

AE40 AC20 AE20

AV24 AV26 AY25 AY27

V36

Y36

Y28

AE15 AE17 AG15

C54

AL5

127(

VccAFDIPLL and VccAClk can be NC in on-die VR mode.

B53

U56

A19

AJ20

AT1

AB1

AC2

Splitting 2 power trace/shape

on pins AV24/AV26 to AY25/AY27,

and AE40 to AG38/AG40.

12

GND GND

127(

Splitting 2 power traces

on pins AC20 to AE20.

+1P05V_PCH

12

SCB65

SCB65 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

GND

1,

SR160

VCCFDIPLL

VCCACLKPLL

VCCAPLLEXP

VCCAPLLSATA

VCCAPLLDMI2

VCCCLKDMI

VCCADAC

VCCA_DPLLA

VCCA_DPLLB VCCA_DPLLB_R

SR160

Do Not Stuff

,

SCB32

SCB32 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

12

3

SR161

12

1,

Do Not Stuff

,

SCB33

SCB33 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

+1P05V_PCH+1P05V_PCH

12

127(

If filter is unstuffed, 0 ohm resistor(SR163) must be stuffed in R and L site.

12

GND

12

GND

12

GND

12

GND

12

GND GND

12

GND

12

GND

1,

SCB28

SCB28 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

SCB29

SCB29 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

SCB30

SCB30 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

2

1,

SCB20

SCB20 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

1,

SCB22

SCB22 Do Not Stuff

Do Not Stuff mx_c0603_small

mx_c0603_small

1,

SCB24

SCB24 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

,

SCB26

SCB26 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

2

12

1,

SCB21

SCB21 Do Not Stuff

Do Not Stuff X5R 10%

X5R 10%

mx_c0805_small

GND

12

1,

SCB23

SCB23 Do Not Stuff

Do Not Stuff X5R 10%

X5R 10%

mx_c0805_small

12

1,

SCB25

SCB25 Do Not Stuff

Do Not Stuff X5R 10%

X5R 10%

mx_c0805_small

GND

12

,

SCB27

SCB27 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10%

mx_c0805_small

GND

12



SCE4

SCE4 220UF/16V

220UF/16V I

I

GND

12



SCE5

SCE5 220UF/16V

220UF/16V I

I

GND

12



SCE6

SCE6 220UF/16V

220UF/16V I

I

GND

VCCAPLLEXP_R

SR162

600Ohm/100Mhz/0.5A

127(

Backup SL5 to 10X2121R0040(1 ohm/0402)

if have no power noise issue.

93

SR165

0

93

SR167

0

1

+1P05V_PCH

1,

SL1

2 1

Do Not Stuff

Do Not Stuff mx_l0805_small

mx_l0805_small

1,

SL2

2 1

Do Not Stuff

mx_l0805_small

1,

12

Do Not Stuff

VCCAPLLDMI2_R

127(

1,

SL3

2 1

Do Not Stuff

Do Not Stuff mx_l0805_small

mx_l0805_small

Backup to 0 ohm 1/8W(0805)JUMP

if power noise is pass on SL3 and SL4.

,

SR163

VCCIOPLL_R

12

1

127(

CRB 0.7:

SR174

1 2

0 Ohm

0 Ohm 5%

5% I

I

SCB27 is NI and

SR163 is 0 ohm.

127(

+3P3V

2 1

10UH/125mA

,

SL6

mx_l0805_small

,

SL5

2 1

mx_l0603_small

VCCA_DPLLA_R

12

Backup to 0 ohm 1/8W(0805)JUMP

if power noise is pass on SL6 and SL7.

,

SL7

12

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

2 1

10UH/125mA

mx_l0805_small

,336%)$

Title :

Engineer:

1

9&&3//

Mike Yen

of

23 79Tuesday, April 26, 2011

Rev

1.01

5

+3P3VSB

12

,

SCB35

0.1UF/16V

D D

0.1UF/16V X7R 10%

X7R 10%

+3P3VSB

127(

Place SCB59 and SCB66 near pin AU20,

SCB60 near pin AL38,

SCB61 and SCB67 near BC17.

+3P3V

127(

Splitting 2 power trace/shape on

pin AV20/AU20 and AU22.

,

SCB58

SCB58 22UF/6.3V

22UF/6.3V X5R 20%

X5R 20% mx_c0805_small

mx_c0805_small

12

SCB59

SCB59 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

GND GND GNDGND

12

,

1,

SCB66

SCB66 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

%27720

12

,

SCB60

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

+3P3V

,

SCB61

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

C C

127(

Install SCB58 during initial power-on.

12

,

SCB38

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GND GND

+1P05V_CPUIO

B B

,

SCB41

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

SCB42

SCB42 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

1,

12

A A

GND GND GND GND GND

12

GND

12

,

SCB40

4.7UF/6.3V

4.7UF/6.3V X5R 10%

X5R 10%

1,

SCB43

SCB43 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

12

,

SCB62

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GND GND

+1P5V_STBY_INT +1P1V_DSW_INT

+1P1V_INT_DCPSUS1

12

1,

SCB44

SCB44 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

127(

Just for measurement.

5

4

12

1,

SCB36

SCB36 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

%27720

GNDGND

12

,

SCB37

SCB37 1UF/16V

1UF/16V X7R 10%

X7R 10%

mx_c0603_small

GND

12

,

SCB67

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GNDGND

12

,

SCB39

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

12

,

SCB63

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

VCCSUS_INT +1P1V_USB

12

1,

SCB45

SCB45 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

CRB 0.7 is 1uF

4

AV28

AN52

AU20 AV20 AU22

AL38

AN38

BC17 BD17 BD20

AF57

BA46 AV41

AA32

AT41

A12

D55 B56

A39

8+

VccSusHDA

VccSPI

Vcc3_3_09 Vcc3_3_10 Vcc3_3_07

Vcc3_3_05 Vcc3_3_06

Vcc3_3_02 Vcc3_3_03 Vcc3_3_04

Vcc3_3_08 Vcc3_3_01

V_PROC_IO V_PROC_IO_NCTF

DcpSST DcpSusByp

DcpSus_01 DcpSus_02 DcpSus_03

COUGARPOINT

V5REF_Sus

V5REF

VccVRM_01 VccVRM_04 VccVRM_03 VccVRM_02

VccDFTERM_01 VccDFTERM_02

VccSus3_3_011

VccSus3_3_002 VccSus3_3_003 VccSus3_3_004 VccSus3_3_005 VccSus3_3_006 VccSus3_3_007 VccSus3_3_008

VccSus3_3_009 VccSus3_3_010

VccSus3_3_001

VccDSW3_3

VccRTC

DcpRTC

DcpRTC_NCTF

BT25

BF1

VCC_XCKPLL

AJ1

VCC_DMIVRM

R2

VCC_XCKPLL_AFDI

R54 R56

T55 T57

BT35

AV30 AV32 AY31 AY33 BJ36 BK36 BM36

AT40 AU38

U31

AV40

BU42

BR54 BT56

3

V5REF_SUS

V5REF

DCPRTC_NCTF

3

12

,

SCB48

SCB48 1UF/16V

1UF/16V X7R 10%

X7R 10%

mx_c0603_small

GND

+1P8V_SFR

12

93

SR172

SR172 0

0

12

1,

SCB49

SCB49 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

GND

+1P8V_SFR

12

1,

SCB52

SCB52 Do Not Stuff

Do Not Stuff X7R 10%

X7R 10%

GND

12

,

SCB53

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GND GND

+3VA

12

,

SCB55

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GND

12

,

SCB57

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

GND

12

93

SR173

SR173 0

0

,

SCB31

SCB31 10UF/6.3V

10UF/6.3V X5R 10%

X5R 10% mx_c0805_small

mx_c0805_small

12

,

SCB54

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

+5V

12

93

SR175

SR175 0

0

+3P3VSB

12

GND

,

SCB69

2.2UF/6.3V

2.2UF/6.3V X5R 10%

X5R 10% mx_c0603_small

mx_c0603_small

,

SR171

SR171 10

10

+1P8V_SFR +1P8V_SFR

12

GND

127(

Place SCB56 near PCH within 40mils.

+BATT

12

,

C59

C59 1UF/16V

1UF/16V X7R 10%

X7R 10% mx_c0603_small

mx_c0603_small

GND

12

,

SCB56

0.1UF/16V

0.1UF/16V X7R 10%

X7R 10%

2

,

1,

SCB46

SCB46 Do Not Stuff

Do Not Stuff

GND

12

,

SCB47

0.1UF/16V

,

SR170

SR170 10

10

+5VSB

12

127(

NI or install is decided to DSW support or not.

127(

Install SCB31 during initial power-on.

127(

Splitting 2 power trace/shape on

pin AV28, AY31/AY33, and AV30/AV32.

127(

Place SCB53 near pin BT35, SCB54 near pin U31.

,and SCB69 near pin AV30/AT40.

0413

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORPORATION

Size Project Name

A3

Date: Sheet

2

Date: Sheet

3

BAT54CW

3

BAT54CW

SD1

SD2

,

1

2

1

2

,336%)$

1

+3P3VSB

+3P3V

Title :

Engineer:

1

9&&686

Mike Yen

of

24 79Tuesday, April 26, 2011

Rev

1.01

Dell AIO 2320 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual