Dell 1545 Schematics
5
hexainf@hotmail.com
GRATIS - FOR FREE
D D
4
3
2
1
Roberts Discrete VGA ATI M92LP-S2 Schematics Document
uFCPGA Mobile Penryn
Intel PM45 + ICH9M
C C
2009-05-19
REV :-1
B B
DY : Nopop Component
A A
5
4
3
2
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Cover Page
Cover Page
Roberts Discrete
Roberts Discrete
Roberts Discrete
1
1 60Tuesday, May 19, 2009
1 60Tuesday, May 19, 2009
1 60Tuesday, May 19, 2009
-1
-1
-1
5
4
3
2
1
CPU DC/DC
Roberts Discrete Block Diagram
Clock Generator
D D
SLG8SP513VTR
19
Intel Mobile CPU
Penryn
Socket P
4,5,6
VRAM
32Mx32bx2 (256MB)
55
4
FSB
800/1066MHz
GDDR3
700MHz
CRT
(on I/Oboard)
LCD
C C
RGB CRT
48
LVDS(Dual Channel)
20
ATI M92LP-S2
51,52,53,54
PCIe x 16
DMIx4
CardReader
SD/SDIO/MMC
MS/MS Pro/xD
B B
26
Digital Mic Array
MIC IN
Internal Analog MIC
Realtek
RTS5159
Azalia
CODEC
IDT
92HD71B7
32
36
USB2.0
AZALIA
Intel
PM45
AGTL+ CPU I/F
DDR Memory I/F
External Graphics
7,8,9,10,11,12
Intel
ICH9-M
USB 2.0/1.1 ports (12)
PCI Express ports (6)
High Definition Audio
SATA ports (4)
LPC I/F
ACPI 1.1
PCI/PCI BRIDGE
13,14,15,16
DDRII 667/800 Channel A
DDR II 667/800 Channel B
C-LINK
PCIE
USB 2.0
Project code : 91.4AQ01.001
PCB P/N : 48.4AQ12.011
Revision : 08224-1
DDRII
667/800
DDRII
667/800
PCIE x 1
LPC Bus
Slot 0
17
Slot 1
18
PCIE x 1 & USB 2.0 x 1
10/100 NIC
Marvell 88E8040
PCIE x 1& USB 2.0 x 1
38
USB 2.0 x 2
USB 2.0 x 1
USB 2.0 x 1
USB 2.0 x 1
Power SW
G577BR91U
New Card
I/O Board
Connector
Mini-Card
802.11a/b/g
CAMERA
(Option)
Bluetooth
Right Side:
USB x 1
25
25
RJ45
CONN
Left Side:
48
USB x 2
26
25
25
31
ISL6266A
INPUTS
+PWR_SRC
SYSTEM DC/DC
TPS51117
INPUTS
+PWR_SRC
SYSTEM DC/DC
MAX17020
INPUTS
+PWR_SRC
+5V_ALW2
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
SYSTEM DC/DC
TPS51116
INPUTS
+PWR_SRC
+1.8V_SUS
+0.9V_DDR_VTT
+V_DDR_MCH_REF
SYSTEM DC/DC
APL5912
INPUTS
+1.8V_SUS
VGA
TPS51117
INPUTS
+PWR_SRC
MAXIM CHARGER
MAX8731A
26
INPUTS
+DC_IN
+PBATT
SYSTEM DC/DC
LDO
INPUTS
26
+5V_ALW
+3.3V_ALW +3.3V_RUN
+1.8V_SUS +1.8V_RUN
PCB LAYER
L1: Top
L2: GND
L3: Signal
L4: Signal
L5: VCC
L6: Signal
L7: GND
HP1
OP AMP
MAX9789C
SPI
SATA
37
SATA
WINBOND
WPCE773L
29
KBC
L8: Bottom
Main Source
Main Source
2CH SPEAKER
A A
HDD
5
4
ODD
23 23
Flash ROM
2MB
3
Touch
PAD
30 33 25
33
KB
ThermalInt.
EMC2102
Fan
23
2
35
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
Roberts Discrete
Roberts Discrete
Roberts Discrete
1
2 60Tuesday, May 19, 2009
2 60Tuesday, May 19, 2009
2 60Tuesday, May 19, 2009
39,40
OUTPUTS
+VCC_CORE
OUTPUTS
+1.05V_VCCP
OUTPUTS
OUTPUTS
OUTPUTS
+1.5V_RUN
+1.1V_RUN
OUTPUTS
+VCC_CORE_RUN
OUTPUTS
+PWR_SRC
OUTPUTS
+5V_RUN
-1
-1
-1
43
41
44
42
50
45
34
28,29
30
27
31
32
33
26
ICH9M Functional Strap Definitions
hexainf@hotmail.com
GRATIS - FOR FREE
Signal
HDA_SDOUT
HDA_SYNC PCIE config1 bit0,
GNT2#/
GPIO53
GPIO20 Reserved.
GNT1#/
GPIO51
GNT3#/
GPIO55
GNT0#:
SPI_CS1#/
GPIO58
SPI_MOSI Integrated TPM Enable,
GPIO49 DMI Termination
SATALED# PCI Express Lane
SPKR
TP3
GPIO33/
HDA_DOCK
_EN#
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK.
Rising Edge of PWROK.
PCIE config2 bit2,
Rising Edge of PWROK.
ESI Strap (Server Only)
Rising Edge of PWROK.
Top-Block Swap
override. Rising Edge
of PWROK.
Selection 0:1.
Rising Edge of PWROK.
Rising Edge of CLPWROK.
Voltage. Rising Edge
of CLPWROK.
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor
Security Override
Strap. Rising Edge of
PWROK.
Allows entrance to XOR Chain testing when TP3
pulled low. When TP3 not pulled low at rising edge
of PWROK, sets bit1 of RPC.PC (Cofig Registers:
offset 224h). This signal has weak internal
pull-down.
This signal has a weak internal pull-down.
Sets bit0 of PRC.PC (Config Registers: Offset
224h).
This signal has a weak internal pull-up.
Sets bit2 of PRC.PC2 (Config Registers: Offset
224h).
This signal should not be pulled high.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desktop
and mobile.
Sampled low: Top-Block Swap mode (inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers: Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC
Sample low: the Integrated TPM will be disable.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
The signal is required to be low for desktop
applications and required to be high for mobile
applications.
Signal has weak internal pull-up. Sets bit 27
of MPC.LR (Device 28: Function 0:Offset D8).
If sampled high, the system is strapped to the
"No Reboot" mode (ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
This signal should not be pull low unless using
XOR Chain testing.
Sampled low: the Flash Descriptor Security will be
overridden. If high, the security measures will be
in effect. This should only be enabled in
manufacturing environments using an external
pull-up resister.
ICH9 EDS 642879 Rev.1.5
Comment
ICH9 Integrated pull-up
and pull-down Resistors
SIGNAL Resistor Type/Value
CL_CLK[1:0]
CL_DATA[1:0]
CL_RST0#
DPRSLPVR/GPIO16
ENERGY_DETECT
HDA_BIT_CLK
HDA_DOCK_EN#/GPIO33
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GLAN_DOCK#
GNT[3:0]#/GPIO[55,53,51]
GPIO20
GPIO49
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#/GPIO58/CLGPIO6
SPI_MOSI
SPI_MISO
SPKR
TACH_[3:0]
TP[3]
USB[11:0][P,N]
ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
The pull-up or pull-down
active when configured
for native GLAN_DOCK#
functionality and determined
by LAN controller.
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 15K
Cantiga chipset and ICH9M I/O controller
Hub strapping configuration
Pin Name
CFG[2:0] FSB Frequency Select 000 = FSB1067
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
CFG5 DMI x2 Select 0 = DMI x2
CFG6 iTPM Host Interface
CFG7 Intel Management
CFG9
CFG10 PCIE Loopback enable 0 = Enable (Note 3)
CFG[13:12] XOR/ALL
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered in
CFG20 Digital Display Port
SDVO
_CTRLDATA
L_DDC_DATA Local Flat Panel
NOTE:
1. All strap signals are sampled with respect to the leading edge of the (G)MCH
Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
Strap Description Configuration
011 = FSB667
010 = FSB800
Reserved
engine crypto strap
PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..
(SDVO/DP/iHDMI)
Concurrent with PCIe
SDVO Present 0 = No SDVO Card Present (Default)
(LFP) Present
others = Reserved
1 = DMI x4 (Default)
0 = The iTPM Host Interface is enabled (Note 2)
1 = The iTPM Host Interface is disabled (default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
1 = TLS cipher suite with confidentiality(Default)
1 = Normal operation (Default): Lane Numbered in
Order
1 = Disable (Default)
00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enable (Note 3)
11 = Disabled (Default)
1 = Dynamic ODT Enabled (Default)Boot BIOS Destination
Order
1 = Reverse Lanes
DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
DMI x2 mode [MCH->ICH]: (3->0, 2->1)
0 = Only Digital Display Port or PCIE is
operational (Default)
1 = Digital display Port and PCIe are operating
simulataneously via the PEG port
1 = SDVO Card Present
0 = LFP Disabled (Default)
1 = LFP Card Present; PCIE disabled
LANE2
MiniCard WLAN
LANE3 LAN
LANE5 New Card
USB TablePCIE Routing
0
1
2
3
4
5
6
7
8
9
10
11
USB
USB1
USB2
USB3
RESERVED
MINI CARD
RESERVED
BLUETOOTH
NEW CARD
RESERVED
RESERVED
Card Reader
CAMERA
Pair Device
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Table of Content
Table of Content
Roberts Discrete
Roberts Discrete
Roberts Discrete
3 60Tuesday, May 19, 2009
3 60Tuesday, May 19, 2009
3 60Tuesday, May 19, 2009
-1
-1
-1
SSID = CPU
H_A#[35..3]7
H_A#[35..3]
1 OF 4
1 OF 4
U41A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
RSVD_CPU_1
1
RSVD_CPU_2
1
RSVD_CPU_3
1
RSVD_CPU_4
1
RSVD_CPU_5
1
RSVD_CPU_6
1
RSVD_CPU_7
1
RSVD_CPU_8
1
RSVD_CPU_9
1
RSVD_CPU_10
1
RSVD_CPU_11
1
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#07
H_REQ#[4..0]7
H_ADSTB#17
H_A20M#14
H_FERR#14
H_IGNNE#14
H_STPCLK#14
H_INTR14
H_NMI14
H_SMI#14
TP30TP30
TP31TP31
TP13TP13
TP23TP23
TP21TP21
TP24TP24
TP19TP19
TP55TP55
TP25TP25
TP34TP34
TP12TP12
U41A
J4
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
SKT-CPU478P-GP
SKT-CPU478P-GP
62.10040.221
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
ICH
ICH
TEST7
RESERVED
RESERVED
DEFER#
DRDY#
DBSY#
LOCK#
RESET#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TRST#
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL
THERMAL
THERMAL
PROCHOT#
THRMDA
THRMDC
THERMTRIP#
HCLK
HCLK
BCLK0
BCLK1
ADS#
BNR#
BPRI#
BR0#
IERR#
INIT#
RS0#
RS1#
RS2#
HIT#
HITM#
TCK
TDO
TMS
DBR#
H1
E2
G5
H5
F21
E1
F1
CPU_IERR#
D20
B3
H4
H_CPURST#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
ITP_BPM#0
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
ITP_BPM#5
AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
ITP_TDO
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
ITP_DBRESET#
C20
R50 Do Not Stuff
R50 Do Not Stuff
R51 56R2J-4-GPR51 56R2J-4-GP
D21
A24
B25
C7
R76 Do Not Stuff
R76 Do Not Stuff
A22
A21
R47 56R2J-4-GPR47 56R2J-4-GP
1 2
ITP_BPM#0 26
ITP_BPM#1 26
ITP_BPM#2 26
ITP_BPM#3 26
ITP_BPM#4 26
ITP_BPM#5 26
ITP_TCK 26
ITP_TDO 26
ITP_TMS 26
ITP_TRST# 26
1 2
DY
DY
1 2
1 2
DY
DY
ITP_DBRESET# 26
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BREQ#0 7
H_INIT# 14
H_LOCK# 7
H_CPURST# 7,26
H_RS#[2..0] 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
ITP_TDI 26
+1.05V_VCCP
H_THERMDA 35
H_THERMDC 35
H_THRMTRIP# 8,14,29,34
+1.05V_VCCP
CLK_CPU_BCLK 19
CLK_CPU_BCLK# 19
+1.05V_VCCP
CPU_PROCHOT# 39
H_THERMDA
H_THERMDC
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THRMTRIP# should connect to
ICH9 and MCH without T-ing.
DY
DY
12
C49
C49
Do Not Stuff
Do Not Stuff
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU-FSB(1/3)
CPU-FSB(1/3)
CPU-FSB(1/3)
Roberts Discrete
Roberts Discrete
Roberts Discrete
4 60Tuesday, May 19, 2009
4 60Tuesday, May 19, 2009
4 60Tuesday, May 19, 2009
-1
-1
-1
SSID = CPU
hexainf@hotmail.com
GRATIS - FOR FREE
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
Layout notes
Z= 55 Ohm 0.5" MAX for CPU_GTLREF0
+1.05V_VCCP
R357
R357
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R354
R354
2KR2F-3-GP
2KR2F-3-GP
DY
DY
CPU_GTLREF0
12
C376
C376
Do Not Stuff
Do Not Stuff
H_DINV#[3..0] 7
H_DSTBN#[3..0] 7
H_DSTBP#[3..0] 7
H_D#[63..0] 7
H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_DSTBN#17
H_DSTBP#17
H_DINV#17
R53 Do Not Stuff
R53 Do Not Stuff
1 2
DY
DY
R60 Do Not Stuff
R60 Do Not Stuff
1 2
DY
DY
R58 Do Not Stuff
R58 Do Not Stuff
1 2
DY
DY
R7 Do Not Stuff
R7 Do Not Stuff
1 2
DY
DY
CPU_BSEL019
CPU_BSEL119
CPU_BSEL219
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
TEST1
TEST2
CPU_TEST3
CPU_TEST5
U41B
U41B
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
SKT-CPU478P-GP
SKT-CPU478P-GP
62.10040.221
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL0
BSEL1
BSEL2
2 OF 4
2 OF 4
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
MISC
MISC
DPRSTP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
R350 27D4R2F-L1-GPR350 27D4R2F-L1-GP
1 2
R349 54D9R2F-L1-GPR349 54D9R2F-L1-GP
1 2
R14 27D4R2F-L1-GPR14 27D4R2F-L1-GP
1 2
R13 54D9R2F-L1-GPR13 54D9R2F-L1-GP
1 2
H_DPRSTP# 8,14,39
H_DPSLP# 14
H_DPWR# 7
H_PWRGOOD 14,34
H_CPUSLP# 7
PSI# 39
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5".
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5".
Route the CPU_TEST3 and CPU_TEST5 signals
through a ground referenced Zo = 55-ohm trace
that ends in a via that is near a GND via
and is accessible through an oscilloscope connection.
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU-FSB(2/3)
CPU-FSB(2/3)
CPU-FSB(2/3)
Roberts Discrete
Roberts Discrete
Roberts Discrete
5 60Tuesday, May 19, 2009
5 60Tuesday, May 19, 2009
5 60Tuesday, May 19, 2009
-1
-1
-1
5
4
3
2
1
SSID = CPU
D D
+VCC_CORE
3 OF 4
3 OF 4
U41C
U41C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C C
B B
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
SKT-CPU478P-GP
SKT-CPU478P-GP
62.10040.221
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
+VCC_CORE
layout note: "+1.5V_VCCA"
as short as possible
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
R311 100R2F-L1-GP-UR311 100R2F-L1-GP-U
R302 100R2F-L1-GP-UR302 100R2F-L1-GP-U
1 2
1 2
CPU_VID[6..0] 39
+VCC_CORE
12
DY
DY
+VCC_CORE
12
+VCC_CORE
12
+1.05V_VCCP
12
DY
DY
12
C36
C36
C25
C25
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C14
C14
C15
C15
DY
DY
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C17
C17
C12
C12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C44
C44
TC17
TC17
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
+VCC_CORE
VCC_SENSE 39
VSS_SENSE 39
DY
DY
DY
DY
DY
DY
12
C31
C31
12
C352
C352
12
C32
C32
12
C43
C43
12
C11
C11
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C26
C26
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C30
C30
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C45
C45
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C374
C374
VCC_SENSE and VSS_SENSE lines
should be of equal length.
C5
C5
C370
C370
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C35
C35
C338
C338
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C29
C29
C340
C340
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C7
C7
C9
C9
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+1.5V_RUN+1.5V_VCCA
R356
R356
1 2
Do Not Stuff
Do Not Stuff
C377
C377
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
DY
DY
12
12
12
12
12
12
C3
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C13
C13
C367
C367
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C344
C344
C347
C347
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C8
C8
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Layout Note:
Place as close as possible
to the CPU VCCA pin.
C366
C366
C365
C365
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C357
C357
C363
C363
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C336
C336
C368
C368
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
C6
C6
C3
12
C10
C10
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C24
C24
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
U41D
U41D
A4
VSS
A8
VSS
A11
VSS
A14
VSS
A16
VSS
A19
VSS
A23
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
SKT-CPU478P-GP
SKT-CPU478P-GP
62.10040.221
4 OF 4
4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
CPU_GND1
CPU_GND2
CPU_GND3
CPU_GND4
NCTF
PIN
1
TP10TP10
1
TP224TP224
1
TP20TP20
1
TP56TP56
A A
5
4
3
2
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU-Power(3/3)
CPU-Power(3/3)
CPU-Power(3/3)
Roberts Discrete
Roberts Discrete
Roberts Discrete
6 60Tuesday, May 19, 2009
6 60Tuesday, May 19, 2009
6 60Tuesday, May 19, 2009
1
-1
-1
-1
SSID = MCH
hexainf@hotmail.com
GRATIS - FOR FREE
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
1 2
R361
R361
H_SWING
12
C399
C399
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
H_RCOMP
24D9R2F-L-GP
24D9R2F-L-GP
Place R51 near to the chip ( < 0.5")
+1.05V_VCCP
12
R368
R368
221R2F-2-GP
221R2F-2-GP
12
R367
R367
100R2F-L1-GP-U
100R2F-L1-GP-U
+1.05V_VCCP
R369
R369
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R372
R372
2KR2F-3-GP
2KR2F-3-GP
1 OF 10
U52A
U52A
F2
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
AD14
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
AA13
H_D#_42
AA9
H_D#_43
AA11
H_D#_44
AD11
H_D#_45
AD10
H_D#_46
AD13
H_D#_47
AE12
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
AE14
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
AE11
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
HOST
HOST
H_AVREF
H_D#[63..0]
H_CPURST#4,26
H_CPUSLP#5
DY
DY
12
C403
C403
Do Not Stuff
Do Not Stuff
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_D#[63..0]5
1 OF 10
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[35..3]
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 19
CLK_MCH_BCLK# 19
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
H_A#[35..3] 4
H_DINV#[3..0] 5
H_DSTBN#[3..0] 5
H_DSTBP#[3..0] 5
H_REQ#[4..0] 4
H_RS#[2..0] 4
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga-HOST(1/6)
Cantiga-HOST(1/6)
Cantiga-HOST(1/6)
Roberts Discrete
Roberts Discrete
Roberts Discrete
7 60Tuesday, May 19, 2009
7 60Tuesday, May 19, 2009
7 60Tuesday, May 19, 2009
-1
-1
-1
SSID = MCH
is current setting
*
CFG Strap HighLow
CFG 5
CFG 6
CFG 7
CFG 9 PCIE GFX lane reversed
CFG 10 PCIE loopback enable PCIE loopback disable
CFG 12 ALLZ mode enable ALLZ mode disable
CFG 13 XOR mode enable XOR mode disable
CFG 16
CFG 19
DMI Lane Reserved
CFG 20
SDVO concurrent
with PCIE
SDVO_CTRLDATA
SDVO interface disable
L_DDC_DATA LFP disable LFP card present
DDPC_CTRLDATA
+3.3V_RUN
R104 Do Not Stuff
R104 Do Not Stuff
1 2
DY
DY
R128 Do Not Stuff
R128 Do Not Stuff
1 2
DY
DY
R117 Do Not Stuff
R117 Do Not Stuff
1 2
DY
DY
R121 Do Not Stuff
R121 Do Not Stuff
1 2
DY
DY
RN20
RN20
4
SRN10KJ-5-GP
SRN10KJ-5-GP
R383 Do Not Stuff
R383 Do Not Stuff
1 2
DY
DY
R112 Do Not Stuff
R112 Do Not Stuff
1 2
DY
DY
R111 Do Not Stuff
R111 Do Not Stuff
1 2
DY
DY
R102 Do Not Stuff
R102 Do Not Stuff
1 2
DY
DY
R382 Do Not Stuff
R382 Do Not Stuff
1 2
DY
DY
R375 Do Not Stuff
R375 Do Not Stuff
1 2
DY
DY
R101 Do Not Stuff
R101 Do Not Stuff
1 2
DY
DY
R105 Do Not Stuff
R105 Do Not Stuff
1 2
DY
DY
R103 Do Not Stuff
R103 Do Not Stuff
1 2
DY
DY
1
23
PM_EXTTS#0
PM_EXTTS#1
DMI X 2
ITPM enable
TLS cipher suite with
no confidentiality
FSB dynamic ODT disable
Normal operation Reverse DMI lanes
Only PCIE or SDVO
is operational
*
*
*
SDVO/iHDMI/DP
interface disabled
CFG11
CFG18
CFG19
CFG20
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG12
CFG13
CFG16
PM_PWROK15,29,35
H_THRMTRIP#4,14,29,34
DPRSLPVR15,39
*
*
PLT_RST#13,25,26,29,32,38
ITPM disable
TLS cipher suite with
confidentiality
PCIE GFX lane
numbered in oder
FSB Dynamic ODT enable
PCIE and SDVO are
operatiing simultaneously
via the PEG port
SDVO interface enable
SDVO/iHDMI/DP
interface enabled
FSB setting
MCH_CLKSEL019
MCH_CLKSEL119
MCH_CLKSEL219
PM_SYNC#15
H_DPRSTP#5,14,39
PM_EXTTS#017
PM_EXTTS#118
A00
1 2
Do Not Stuff
Do Not Stuff
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
Do Not Stuff
Do Not Stuff
DMI X 4
TP86TP86
TP88TP88
TP84TP84
TP85TP85
TP87TP87
R139
R139
R94
R94
C94
C94
1
1
1
1
1
DY
DY
2 OF 10
U52B
U52B
M36
RESERVED#M36
N36
RESERVED#N36
R33
RESERVED#R33
T33
RESERVED#T33
AH9
RESERVED#AH9
AH10
RESERVED#AH10
AH12
RESERVED#AH12
AH13
RESERVED#AH13
K12
*
*
*
*
*
*
*
*
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PWROK_R
RSTIN#
12
RESERVED#K12
AL34
RESERVED#AL34
AK34
RESERVED#AK34
AN35
RESERVED#AN35
AM35
RESERVED#AM35
T24
RESERVED#T24
B31
RESERVED#B31
B2
RESERVED#B2
M1
RESERVED#M1
AY21
RESERVED#AY21
BG23
RESERVED#BG23
BF23
RESERVED#BF23
BH18
RESERVED#BH18
BF18
RESERVED#BF18
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC#BG48
BF48
NC#BF48
BD48
NC#BD48
BC48
NC#BC48
BH47
NC#BH47
BG47
NC#BG47
BE47
NC#BE47
BH46
NC#BH46
BF46
NC#BF46
BG45
NC#BG45
BH44
NC#BH44
BH43
NC#BH43
BH6
NC#BH6
BH5
NC#BH5
BG4
NC#BG4
BH3
NC#BH3
BF3
NC#BF3
BH2
NC#BH2
BG2
NC#BG2
BE2
NC#BE2
BG1
NC#BG1
BF1
NC#BF1
BD1
NC#BD1
BC1
NC#BC1
F1
NC#F1
A47
NC#A47
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
RSVD
RSVD
CFG
CFG
PM
PM
NC
NC
MISC
MISC
2 OF 10
AP24
SA_CK_0
AT21
SA_CK_1
AV24
SB_CK_0
AU20
SB_CK_1
AR24
SA_CK#_0
AR21
SA_CK#_1
AU24
SB_CK#_0
AV20
SB_CK#_1
BC28
SA_CKE_0
AY28
SA_CKE_1
AY36
SB_CKE_0
BB36
SB_CKE_1
BA17
SA_CS#_0
AY16
SA_CS#_1
AV16
SB_CS#_0
AR13
SB_CS#_1
BD17
SA_ODT_0
AY17
SA_ODT_1
BF15
SB_ODT_0
AY13
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
CLK
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI
DMI
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
MEHDA
MEHDA
CL_VREF
BG22
BH21
BF28
BH28
AV42
AR36
BF17
BC36
B38
A38
E41
F41
F43
E43
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
M_RCOMPP
M_RCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_REXT
R374 499R2F-2-GPR374 499R2F-2-GP
1 2
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
MCH_CLVREF
M_CLK_DDR0 17
M_CLK_DDR1 17
M_CLK_DDR2 18
M_CLK_DDR3 18
M_CLK_DDR#0 17
M_CLK_DDR#1 17
M_CLK_DDR#2 18
M_CLK_DDR#3 18
M_CKE0 17
M_CKE1 17
M_CKE2 18
M_CKE3 18
M_CS0# 17
M_CS1# 17
M_CS2# 18
M_CS3# 18
M_ODT0 17
M_ODT1 17
M_ODT2 18
M_ODT3 18
For Discrete
CLK_MCH_3GPLL 19
CLK_MCH_3GPLL# 19
DMI_TXN0 13
DMI_TXN1 13
DMI_TXN2 13
DMI_TXN3 13
DMI_TXP0 13
DMI_TXP1 13
DMI_TXP2 13
DMI_TXP3 13
DMI_RXN0 13
DMI_RXN1 13
DMI_RXN2 13
DMI_RXN3 13
DMI_RXP0 13
DMI_RXP1 13
DMI_RXP2 13
DMI_RXP3 13
CL_CLK0 15
CL_DATA0 15
M_PWROK 15
CL_RST#0 15
MCH_CLVREF ~= 0.35V
CLKREQ#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
N28
M28
G36
E36
K36
H36
B12
B28
B30
B29
C29
A28
TSATN#
TP271TP271
1
CLKREQ#_B 19
MCH_ICH_SYNC# 15
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
80D6R2F-L-GP
80D6R2F-L-GP
80D6R2F-L-GP
80D6R2F-L-GP
+V_DDR_MCH_REF
1 2
12
R145
R145
DY
DY
Do Not Stuff
Do Not Stuff
+1.05V_VCCP
1 2
12
12
C175
C175
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+1.8V_SUS
R380
R380
R377
R377
+1.8V_SUS
DY
DY
R142
R142
Do Not Stuff
Do Not Stuff
TSATN#
R126
R126
1KR2F-3-GP
1KR2F-3-GP
R130
R130
499R2F-2-GP
499R2F-2-GP
12
12
SM_RCOMP_VOH
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
SM_RCOMP_VOL
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
R370
R370
56R2J-4-GP
56R2J-4-GP
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C159
C159
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C145
C145
+3.3V_RUN+1.05V_VCCP
12
R371
R371
DY
DY
Do Not Stuff
Do Not Stuff
TSATN#_KBC
C
Q19
Q19
B
DY
DY
Do Not Stuff
Do Not Stuff
E
R131
CLKREQ#_B
R131
1 2
10KR2J-3-GP
10KR2J-3-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga-DMI/CFG(2/6)
Cantiga-DMI/CFG(2/6)
Cantiga-DMI/CFG(2/6)
Roberts Discrete
Roberts Discrete
Roberts Discrete
C162
C162
C151
C151
+3.3V_RUN
12
12
8 60Tuesday, May 19, 2009
8 60Tuesday, May 19, 2009
8 60Tuesday, May 19, 2009
+1.8V_SUS
R122
R122
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R116
R116
3K01R2F-3-GP
3K01R2F-3-GP
R119
R119
1KR2F-3-GP
1KR2F-3-GP
1 2
TSATN#_KBC 29
-1
-1
-1
SSID = MCH
hexainf@hotmail.com
GRATIS - FOR FREE
M_A_DQ[63..0]17
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U52D
U52D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
4 OF 10
4 OF 10
BD21
SA_BS_0
BG18
SA_BS_1
AT25
SA_BS_2
BB20
SA_RAS#
BD20
SA_CAS#
AY20
SA_WE#
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_DM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DM0
AM37
M_A_BS#0 17
M_A_BS#1 17
M_A_BS#2 17
M_A_RAS# 17
M_A_CAS# 17
M_A_WE# 17
M_A_DM[7..0] 17
M_A_DQS[7..0] 17
M_A_DQS#[7..0] 17
M_A_A[14..0] 17
M_B_DQ[63..0]18
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U52E
U52E
AK47
SB_DQ_0
AH46
SB_DQ_1
AP47
SB_DQ_2
AP46
SB_DQ_3
AJ46
SB_DQ_4
AJ48
SB_DQ_5
AM48
SB_DQ_6
AP48
SB_DQ_7
AU47
SB_DQ_8
AU46
SB_DQ_9
BA48
SB_DQ_10
AY48
SB_DQ_11
AT47
SB_DQ_12
AR47
SB_DQ_13
BA47
SB_DQ_14
BC47
SB_DQ_15
BC46
SB_DQ_16
BC44
SB_DQ_17
BG43
SB_DQ_18
BF43
SB_DQ_19
BE45
SB_DQ_20
BC41
SB_DQ_21
BF40
SB_DQ_22
BF41
SB_DQ_23
BG38
SB_DQ_24
BF38
SB_DQ_25
BH35
SB_DQ_26
BG35
SB_DQ_27
BH40
SB_DQ_28
BG39
SB_DQ_29
BG34
SB_DQ_30
BH34
SB_DQ_31
BH14
SB_DQ_32
BG12
SB_DQ_33
BH11
SB_DQ_34
BG8
SB_DQ_35
BH12
SB_DQ_36
BF11
SB_DQ_37
BF8
SB_DQ_38
BG7
SB_DQ_39
BC5
SB_DQ_40
BC6
SB_DQ_41
AY3
SB_DQ_42
AY1
SB_DQ_43
BF6
SB_DQ_44
BF5
SB_DQ_45
BA1
SB_DQ_46
BD3
SB_DQ_47
AV2
SB_DQ_48
AU3
SB_DQ_49
AR3
SB_DQ_50
AN2
SB_DQ_51
AY2
SB_DQ_52
AV1
SB_DQ_53
AP3
SB_DQ_54
AR1
SB_DQ_55
AL1
SB_DQ_56
AL2
SB_DQ_57
AJ1
SB_DQ_58
AH1
SB_DQ_59
AM2
SB_DQ_60
AM3
SB_DQ_61
AH3
SB_DQ_62
AJ3
SB_DQ_63
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
5 OF 10
5 OF 10
BC16
SB_BS_0
BB17
SB_BS_1
BB33
SB_BS_2
AU17
SB_RAS#
BG16
SB_CAS#
BF14
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_DM0
AM47
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_BS#0 18
M_B_BS#1 18
M_B_BS#2 18
M_B_RAS# 18
M_B_CAS# 18
M_B_WE# 18
M_B_DM[7..0] 18
M_B_DQS[7..0] 18
M_B_DQS#[7..0] 18
M_B_A[14..0] 18
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga-DDR(3/6)
Cantiga-DDR(3/6)
Cantiga-DDR(3/6)
Roberts Discrete
Roberts Discrete
Roberts Discrete
9 60Tuesday, May 19, 2009
9 60Tuesday, May 19, 2009
9 60Tuesday, May 19, 2009
-1
-1
-1
SSID = MCH
+1.8V_SUS
for Discrete
VCC_AXG_SENSE
1
VSS_AXG_SENSE
TP83TP83
1
TP82TP82
U52G
U52G
AP33
VCC_SM
AN33
VCC_SM
BH32
VCC_SM
BG32
VCC_SM
BF32
VCC_SM
BD32
VCC_SM
BC32
VCC_SM
BB32
VCC_SM
BA32
VCC_SM
AY32
VCC_SM
AW32
VCC_SM
AV32
VCC_SM
AU32
VCC_SM
AT32
VCC_SM
AR32
VCC_SM
AP32
VCC_SM
AN32
VCC_SM
BH31
VCC_SM
BG31
VCC_SM
BF31
VCC_SM
BG30
VCC_SM
BH29
VCC_SM
BG29
VCC_SM
BF29
VCC_SM
BD29
VCC_SM
BC29
VCC_SM
BB29
VCC_SM
BA29
VCC_SM
AY29
VCC_SM
AW29
VCC_SM
AV29
VCC_SM
AU29
VCC_SM
AT29
VCC_SM
AR29
VCC_SM
AP29
VCC_SM
BA36
VCC_SM/NC
BB24
VCC_SM/NC
BD16
VCC_SM/NC
BB21
VCC_SM/NC
AW16
VCC_SM/NC
AW13
VCC_SM/NC
AT13
VCC_SM/NC
Y26
VCC_AXG
AE25
VCC_AXG
AB25
VCC_AXG
AA25
VCC_AXG
AE24
VCC_AXG
AC24
VCC_AXG
AA24
VCC_AXG
Y24
VCC_AXG
AE23
VCC_AXG
AC23
VCC_AXG
AB23
VCC_AXG
AA23
VCC_AXG
AJ21
VCC_AXG
AG21
VCC_AXG
AE21
VCC_AXG
AC21
VCC_AXG
AA21
VCC_AXG
Y21
VCC_AXG
AH20
VCC_AXG
AF20
VCC_AXG
AE20
VCC_AXG
AC20
VCC_AXG
AB20
VCC_AXG
AA20
VCC_AXG
T17
VCC_AXG
T16
VCC_AXG
AM15
VCC_AXG
AL15
VCC_AXG
AE15
VCC_AXG
AJ15
VCC_AXG
AH15
VCC_AXG
AG15
VCC_AXG
AF15
VCC_AXG
AB15
VCC_AXG
AA15
VCC_AXG
Y15
VCC_AXG
V15
VCC_AXG
U15
VCC_AXG
AN14
VCC_AXG
AM14
VCC_AXG
U14
VCC_AXG
T14
VCC_AXG
AJ14
VCC_AXG_SENSE
AH14
VSS_AXG_SENSE
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
3000mA
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC GFX NCTF
VCC GFX NCTF
7 OF 10
7 OF 10
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH
for Discrete
12
C99
C99
Place CAP where
LVDS and DDR2 taps
12
C92
C92
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C81
C81
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
C431
C431
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
1
1
C134
C134
2
2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
FOR VCC SM
12
12
TC21
TC21
DY
DY
ST220U2D5VBM-2GP
ST220U2D5VBM-2GP
Place on the Edge
12
C182
C182
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
12
C426
C426
Do Not Stuff
Do Not Stuff
12
C186
C186
C178
C178
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+1.8V_SUS
C435
C435
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+1.05V_VCCP
FOR VCC CORE
12
12
C390
C390
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C98
C98
C84
C84
DY
DY
Do Not Stuff
Do Not Stuff
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
DY
DY
Coupling CAP 370 mils from the Edge
DY
DY
12
C111
C111
Do Not Stuff
Do Not Stuff
12
C166
C166
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
C113
C113
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
Coupling CAP
R125
R125
1 2
Do Not Stuff
Do Not Stuff
Supply Signal Group
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
VCCA_SM
+1.05V_VCCP
+1.05V_VCCP
VCCA_SM_CK 26mA
VCCA_HPLL 24mA
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP 50mA
VCCD_PEG_PLL
VCC_AXF+1.05V_VCCP
+1.5V_RUN VCCD_TVDAC 35mA
+1.8V_SUS
+1.8V_SUS 124mA
VCC_SM_CK
+1.5V_RUN VCCA_PEG_BG 414uA
+3.3V_RUN VCC_HV 105.3mA
12
12
12
C91
C91
DY
DY
Do Not Stuff
Do Not Stuff
C156
C156
Do Not Stuff
Do Not Stuff
VCC_GMCH_35
A00
Imax
3060mAVCC+1.05V_VCCP
852mAVTT
1782mAVCC_PEG
456mAVCC_DMI
720mA+1.05V_VCCP
139.2mAVCCA_MPLL
157.2mAVCCD_HPLL
50mAVCCA_PEG_PLL
321.35mA
3000mAVCC_SM
C80
C80
Do Not Stuff
Do Not Stuff
6 OF 10
U52F
U52F
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
VCC
AE33
AC33
AA33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
2898.52mA
VCC
VCC
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T32
VCC
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
VCC CORE
VCC CORE
POWER
POWER
Cantiga-Power(4/6)
Cantiga-Power(4/6)
Cantiga-Power(4/6)
6 OF 10
AM32
VCC_NCTF
AL32
VCC_NCTF
AK32
VCC_NCTF
AJ32
VCC_NCTF
AH32
VCC_NCTF
AG32
VCC_NCTF
AE32
VCC_NCTF
AC32
VCC_NCTF
AA32
VCC_NCTF
Y32
VCC_NCTF
W32
VCC_NCTF
U32
VCC_NCTF
AM30
VCC_NCTF
AL30
VCC_NCTF
AK30
VCC_NCTF
AH30
VCC_NCTF
AG30
VCC_NCTF
AF30
VCC_NCTF
AE30
VCC_NCTF
AC30
VCC_NCTF
AB30
VCC_NCTF
AA30
VCC_NCTF
Y30
VCC_NCTF
W30
VCC_NCTF
V30
VCC_NCTF
U30
VCC_NCTF
AL29
VCC_NCTF
AK29
VCC_NCTF
AJ29
VCC_NCTF
AH29
VCC_NCTF
AG29
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
10 60Tuesday, May 19, 2009
10 60Tuesday, May 19, 2009
10 60Tuesday, May 19, 2009
VCC NCTF
VCC NCTF
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Roberts Discrete
Roberts Discrete
Roberts Discrete
+1.05V_VCCP
-1
-1
-1
SSID = MCH
hexainf@hotmail.com
GRATIS - FOR FREE
+1.05V_VCCP
A00
R351
R351
Do Not Stuff
Do Not Stuff
L12
L12
1 2
120ohm 100MHz
+M_VCCA_MPLL_HPLL
120ohm 100MHz
+1.05V_VCCP
220ohm 100MHz
+1.5V_RUN
180ohm 100MHz
1 2
FCM1608KF-1-GP
FCM1608KF-1-GP
L11
L11
1 2
FCM1608KF-1-GP
FCM1608KF-1-GP
L16
L16
1 2
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
R115
R115
1 2
Do Not Stuff
Do Not Stuff
L5128
L5128
1 2
HCB1608K-181T20GP
HCB1608K-181T20GP
M_VCCA_HPLL
12
M_VCCA_MPLL
12
DY
DY
1D05V_RUN_PEGPLL
12
1D5VRUN_TVDAC
12
1D5VRUN_QDAC
12
12
C393
C393
C387
C387
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C391
C391
C384
C384
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C450
C450
C443
C443
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C152
C152
C153
C153
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C5381
C5381
C5382
C5382
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
+1.5V_RUN
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
R402
R402
1 2
Do Not Stuff
Do Not Stuff
R120
R120
1 2
Do Not Stuff
Do Not Stuff
R360
R360
1 2
Do Not Stuff
Do Not Stuff
12
C442
C442
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C127
C127
DY
DY
12
C140
C140
12
C385
C385
12
12
C126
C126
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C144
C144
DY
DY
Do Not Stuff
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
for Discrete
12
C438
C438
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
for Discrete
M_VCCA_HPLL
M_VCCA_MPLL
for Discrete
VCCA_PEG_BG
1D05V_RUN_PEGPLL
12
C130
C130
C129
C129
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D05V_SM_CK
C157
C157
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5VRUN_TVDAC
1D5VRUN_QDAC
1D05V_RUN_HPLL
1D05V_RUN_PEGPLL
for
Discrete
B27
A26
A25
B25
F47
L48
AD1
AE1
J48
J47
AD48
AA48
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
SC1U10V3KX-3GP
SC1U10V3KX-3GP
AP16
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
B24
A24
A32
M25
L28
AF1
AA47
M38
L37
U52H
U52H
VCCA_CRT_DAC
VCCA_CRT_DAC
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
24mA
VCCA_HPLL
139.2mA
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
414uA
VCCA_PEG_PLL
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_TV_DAC
VCCA_TV_DAC
VCC_HDA
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS
VCCD_LVDS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
50mA
720mA
26mA
35mA
2mA
157.2mA
50mA
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
118.8mA
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
AXF
AXF
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
124mA
SM CK
SM CK
VCC_TX_LVDS
HV
HV
PEG
PEG
DMI
DMI
VTTLF
VTTLF
8 OF 10
8 OF 10
852mA
VTT
VTT
VCC_AXF
VCC_AXF
VCC_AXF
321.35mA
VCC_HV
VCC_HV
VCC_HV
105.3mA
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
1782mA
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
456mA
VTTLF
VTTLF
VTTLF
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
for Discrete
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
1
1
C143
C143
2
2
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
1D05V_VCC_AXF
+VCC_AXF
VTTLF1
VTTLF2
VTTLF3
12
C135
C135
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
+3.3V_VCC_HV
12
C447
C447
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
1
C395
C395
2
2
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
12
C123
C123
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
+1.05V_VCCP
12
C191
C191
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
1
C394
C394
2
2
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
12
C128
C128
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
3
BAT54-7-F-GP
BAT54-7-F-GP
12
C408
C408
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
C133
C133
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C445
C445
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
1
C90
C90
2
2
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
+1.05V_VCCP
12
DY
DY
12
D22
D22
12
1 2
1 2
12
12
TC3
TC3
DY
DY
EC48
EC48
Do Not Stuff
Do Not Stuff
SCD1U25V3KX-GP
SCD1U25V3KX-GP
+3.3V_RUN +3.3V_VCC_HV
R396
R396
2
R373
R373
1 2
Do Not Stuff
Do Not Stuff
C407
C407
Do Not Stuff
Do Not Stuff
R97
R97
1 2
Do Not Stuff
Do Not Stuff
R100
R100
1R3F-GP
1R3F-GP
C137
C137
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C446
C446
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C185
C185
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
10R2J-2-GP
10R2J-2-GP
+1.05V_VCCP
+1.8V_SUS
+1.05V_VCCP
+1.05V_VCCP
Cantiga-Power/Filter(5/6)
Cantiga-Power/Filter(5/6)
Cantiga-Power/Filter(5/6)
R398
R398
1 2
Do Not Stuff
Do Not Stuff
Roberts Discrete
Roberts Discrete
Roberts Discrete
12
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
11 60Tuesday, May 19, 2009
11 60Tuesday, May 19, 2009
11 60Tuesday, May 19, 2009
C437
C437
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
-1
-1
-1
SSID = MCH
U52I
U52I
AU48
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
AF47
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AY46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
BC43
AV43
AU43
AM43
BG42
AY42
AT42
AN42
AE42
BD41
AU41
AM41
AH41
AD41
AA41
BG40
BB40
AV40
AN40
AT39
AM39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AW37
AT37
AN37
BG36
BD36
AK15
AU36
M44
F44
J43
C43
AJ42
N42
L42
Y41
U41
T41
M41
G41
B41
H40
E40
AJ39
N39
L39
B39
Y38
U38
T38
J38
F38
C38
AJ37
H37
C37
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
9 OF 10
9 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
U52J
U52J
BG21
VSS
L12
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
R17
VSS
M17
VSS
H17
VSS
C17
VSS
BA16
VSS
AU16
VSS
AN16
VSS
N16
VSS
K16
VSS
G16
VSS
E16
VSS
BG15
VSS
AC15
VSS
W15
VSS
A15
VSS
BG14
VSS
AA14
VSS
C14
VSS
BG13
VSS
BC13
VSS
BA13
VSS
AN13
VSS
AJ13
VSS
AE13
VSS
N13
VSS
L13
VSS
G13
VSS
E13
VSS
BF12
VSS
AV12
VSS
AT12
VSS
AM12
VSS
AA12
VSS
J12
VSS
A12
VSS
BD11
VSS
BB11
VSS
AY11
VSS
AN11
VSS
AH11
VSS
Y11
VSS
N11
VSS
G11
VSS
C11
VSS
BG10
VSS
AV10
VSS
AT10
VSS
AJ10
VSS
AE10
VSS
AA10
VSS
M10
VSS
BF9
VSS
BC9
VSS
AN9
VSS
AM9
VSS
AD9
VSS
G9
VSS
B9
VSS
BH8
VSS
BB8
VSS
AV8
VSS
AT8
VSS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
VSS
VSS
VSS NCTF
VSS NCTF
VSS SCB
VSS SCB
NC
NC
10 OF 10
10 OF 10
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48
Place R133
close to
MCH within
500 mils.
R133
R133
49D9R2F-GP
49D9R2F-GP
PCIE_MRX_GTX_N[0..15]
PCIE_MRX_GTX_P[0..15]
C572 SCD1U16V2KX-3GPC572 SCD1U16V2KX-3GP
1 2
C649 SCD1U16V2KX-3GPC649 SCD1U16V2KX-3GP
1 2
C653 SCD1U16V2KX-3GPC653 SCD1U16V2KX-3GP
1 2
C569 SCD1U16V2KX-3GPC569 SCD1U16V2KX-3GP
1 2
C658 SCD1U16V2KX-3GPC658 SCD1U16V2KX-3GP
1 2
C692 SCD1U16V2KX-3GPC692 SCD1U16V2KX-3GP
1 2
C693 SCD1U16V2KX-3GPC693 SCD1U16V2KX-3GP
1 2
C694 SCD1U16V2KX-3GPC694 SCD1U16V2KX-3GP
1 2
C700 SCD1U16V2KX-3GPC700 SCD1U16V2KX-3GP
1 2
C712 SCD1U16V2KX-3GPC712 SCD1U16V2KX-3GP
1 2
C688 SCD1U16V2KX-3GPC688 SCD1U16V2KX-3GP
1 2
C690 SCD1U16V2KX-3GPC690 SCD1U16V2KX-3GP
1 2
C699 SCD1U16V2KX-3GPC699 SCD1U16V2KX-3GP
1 2
C703 SCD1U16V2KX-3GPC703 SCD1U16V2KX-3GP
1 2
C711 SCD1U16V2KX-3GPC711 SCD1U16V2KX-3GP
1 2
C718 SCD1U16V2KX-3GPC718 SCD1U16V2KX-3GP
1 2
C573 SCD1U16V2KX-3GPC573 SCD1U16V2KX-3GP
1 2
C650 SCD1U16V2KX-3GPC650 SCD1U16V2KX-3GP
1 2
C657 SCD1U16V2KX-3GPC657 SCD1U16V2KX-3GP
1 2
C574 SCD1U16V2KX-3GPC574 SCD1U16V2KX-3GP
1 2
C656 SCD1U16V2KX-3GPC656 SCD1U16V2KX-3GP
1 2
C704 SCD1U16V2KX-3GPC704 SCD1U16V2KX-3GP
1 2
C807 SCD1U16V2KX-3GPC807 SCD1U16V2KX-3GP
1 2
C746 SCD1U16V2KX-3GPC746 SCD1U16V2KX-3GP
1 2
C811 SCD1U16V2KX-3GPC811 SCD1U16V2KX-3GP
1 2
C814 SCD1U16V2KX-3GPC814 SCD1U16V2KX-3GP
1 2
C713 SCD1U16V2KX-3GPC713 SCD1U16V2KX-3GP
1 2
C727 SCD1U16V2KX-3GPC727 SCD1U16V2KX-3GP
1 2
C731 SCD1U16V2KX-3GPC731 SCD1U16V2KX-3GP
1 2
C734 SCD1U16V2KX-3GPC734 SCD1U16V2KX-3GP
1 2
C736 SCD1U16V2KX-3GPC736 SCD1U16V2KX-3GP
1 2
C739 SCD1U16V2KX-3GPC739 SCD1U16V2KX-3GP
1 2
PCIE_MRX_GTX_N[0..15] 51
PCIE_MRX_GTX_P[0..15] 51
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N[0..15]
PCIE_MTX_GRX_P[0..15]
PCIE_MTX_GRX_N[0..15] 51
PCIE_MTX_GRX_P[0..15] 51
PEG_CMP
T37
T36
PCIE_MRX_GTX_N0
H44
PCIE_MRX_GTX_N1
J46
PCIE_MRX_GTX_N2
L44
PCIE_MRX_GTX_N3
L40
PCIE_MRX_GTX_N4
N41
PCIE_MRX_GTX_N5
P48
PCIE_MRX_GTX_N6
N44
PCIE_MRX_GTX_N7
T43
PCIE_MRX_GTX_N8
U43
PCIE_MRX_GTX_N9
Y43
PCIE_MRX_GTX_N10
Y48
PCIE_MRX_GTX_N11
Y36
PCIE_MRX_GTX_N12
AA43
PCIE_MRX_GTX_N13
AD37
PCIE_MRX_GTX_N14
AC47
PCIE_MRX_GTX_N15
AD39
PCIE_MRX_GTX_P0
H43
PCIE_MRX_GTX_P1
J44
PCIE_MRX_GTX_P2
L43
PCIE_MRX_GTX_P3
L41
PCIE_MRX_GTX_P4
N40
PCIE_MRX_GTX_P5
P47
PCIE_MRX_GTX_P6
N43
PCIE_MRX_GTX_P7
T42
PCIE_MRX_GTX_P8
U42
PCIE_MRX_GTX_P9
Y42
PCIE_MRX_GTX_P10
W47
PCIE_MRX_GTX_P11
Y37
PCIE_MRX_GTX_P12
AA42
PCIE_MRX_GTX_P13
AD36
PCIE_MRX_GTX_P14
AC48
PCIE_MRX_GTX_P15
AD40
PCIE_MTX_GRX_C_N0
J41
PCIE_MTX_GRX_C_N1
M46
PCIE_MTX_GRX_C_N2
M47
PCIE_MTX_GRX_C_N3
M40
PCIE_MTX_GRX_C_N4
M42
PCIE_MTX_GRX_C_N5
R48
PCIE_MTX_GRX_C_N6
N38
PCIE_MTX_GRX_C_N7
T40
PCIE_MTX_GRX_C_N8
U37
PCIE_MTX_GRX_C_N9
U40
PCIE_MTX_GRX_C_N10
Y40
PCIE_MTX_GRX_C_N11
AA46
PCIE_MTX_GRX_C_N12
AA37
PCIE_MTX_GRX_C_N13
AA40
PCIE_MTX_GRX_C_N14
AD43
PCIE_MTX_GRX_C_N15
AC46
PCIE_MTX_GRX_C_P0
J42
PCIE_MTX_GRX_C_P1
L46
PCIE_MTX_GRX_C_P2
M48
PCIE_MTX_GRX_C_P3
M39
PCIE_MTX_GRX_C_P4
M43
PCIE_MTX_GRX_C_P5
R47
PCIE_MTX_GRX_C_P6
N37
PCIE_MTX_GRX_C_P7
T39
PCIE_MTX_GRX_C_P8
U36
PCIE_MTX_GRX_C_P9
U39
PCIE_MTX_GRX_C_P10
Y39
PCIE_MTX_GRX_C_P11
Y46
PCIE_MTX_GRX_C_P12
AA36
PCIE_MTX_GRX_C_P13
AA39
PCIE_MTX_GRX_C_P14
AD42
PCIE_MTX_GRX_C_P15
AD46
+1.05V_VCCP
1 2
for Discrete
AH8
VSS
Y8
VSS
L8
VSS
E8
VSS
B8
VSS
AY7
VSS
AU7
VSS
AN7
VSS
AJ7
VSS
AE7
VSS
AA7
VSS
N7
VSS
J7
VSS
BG6
VSS
BD6
VSS
AV6
VSS
AT6
VSS
AM6
VSS
M6
VSS
C6
VSS
BA5
VSS
AH5
VSS
AD5
VSS
Y5
VSS
L5
VSS
J5
VSS
H5
VSS
F5
VSS
BE4
VSS
BC3
VSS
AV3
VSS
AL3
VSS
R3
VSS
P3
VSS
F3
VSS
BA2
VSS
AW2
VSS
AU2
VSS
AR2
VSS
AP2
VSS
AJ2
VSS
AH2
VSS
AF2
VSS
AE2
VSS
AD2
VSS
AC2
VSS
Y2
VSS
M2
VSS
K2
VSS
AM1
VSS
AA1
VSS
P1
VSS
H1
VSS
U24
VSS
U28
VSS
U25
VSS
U29
VSS
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
GMCH_GND1
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
GMCH_GND2
GMCH_GND3
GMCH_GND4
1
TP103TP103
1
NCTF
TP80TP80
1
PIN
TP226TP226
1
TP78TP78
U52C
U52C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
LVDS
LVDS
TV VGA
TV VGA
3 OF 10
3 OF 10
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Cantiga-GND/LVDS/VGA(6/6)
Cantiga-GND/LVDS/VGA(6/6)
Cantiga-GND/LVDS/VGA(6/6)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Roberts Discrete
Roberts Discrete
Roberts Discrete
12 60Tuesday, May 19, 2009
12 60Tuesday, May 19, 2009
12 60Tuesday, May 19, 2009
-1
-1
-1
5
hexainf@hotmail.com
GRATIS - FOR FREE
SSID = ICH
5 OF 6
5 OF 6
U25E
U25E
AA26
VSS
AA27
VSS
AA3
VSS
AA6
VSS
AB1
VSS
AA23
VSS
AB28
D D
C C
B B
A A
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
B11
B14
B17
B20
B23
C26
C27
E11
E14
E18
E21
E24
G12
G14
G18
G21
G24
G26
G27
H23
H28
H29
AJ8
F16
F28
F29
G8
H2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B2
VSS
VSS
VSS
B5
VSS
B8
VSS
VSS
VSS
VSS
VSS
VSS
E2
VSS
VSS
VSS
E5
VSS
E8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ICH9M-GP-NF
ICH9M-GP-NF
5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
Mini Card
New Card
ICH_GND1
ICH_GND2
ICH_GND3
ICH_GND4
1
1
1
1
+3.3V_ALW
LAN
TP177TP177
TP178TP178
TP125TP125
TP127TP127
PLT_RST#8,25,26,29,32,38
SPI_WP#
SPI_MOSO
SPI_CS#0
NCTF PIN
4
+3.3V_RUN
U32
U32
B
5
VCC
DY
DY
PLT_RST#
12
C5388
C5388
SC220P50V2KX-3GP
SC220P50V2KX-3GP
R245
R245
1 2
DY
DY
Do Not Stuff
Do Not Stuff
U27
U27
4
GND
3
2
1
USB_OC#11
USB_OC#6 USB_OC#0
USB_OC#1
PCIE_RXN226
PCIE_RXP226
PCIE_TXN226
PCIE_TXP226
PCIE_RXN338
PCIE_RXP338
PCIE_TXN338
PCIE_TXP338
PCIE_RXN525
PCIE_RXP525
PCIE_TXN525
PCIE_TXP525
4
SI
WP#
SCLK
DY
DY
SO
HOLD#
CS#
VCC
Do Not Stuff
Do Not Stuff
RP1
RP1
1
2
3
4
5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
C500 SCD1U16V2KX-3GPC500 SCD1U16V2KX-3GP
C497 SCD1U16V2KX-3GPC497 SCD1U16V2KX-3GP
C506 SCD1U16V2KX-3GPC506 SCD1U16V2KX-3GP
C510 SCD1U16V2KX-3GPC510 SCD1U16V2KX-3GP
C518 SCD1U16V2KX-3GPC518 SCD1U16V2KX-3GP
C517 SCD1U16V2KX-3GPC517 SCD1U16V2KX-3GP
SPI_CLK
R233 Do Not Stuff
R233 Do Not Stuff
SPI_CS#0
R241 Do Not Stuff
R241 Do Not Stuff
SPI_MOSI
R230 Do Not Stuff
R230 Do Not Stuff
SPI_MOSO
R237 Do Not Stuff
R237 Do Not Stuff
4
Y
Do Not Stuff
Do Not Stuff
R262
R262
1 2
Do Not Stuff
Do Not Stuff
SPI_MOSI
5
SPI_CLK
6
SPI_HOLD#
7
8
10
9
USB_OC#5
8
USB_OC#7USB_OC#2
7
USB_OC#4
12
12
12
12
12
12
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
USB_OC#048
USB_OC#148
USB_OC#231
A
GND
Do Not Stuff
Do Not Stuff
R208
R208
1 2
22R2F-1-GP
22R2F-1-GP
3
1
PCI_PLTRST#
2
3
+3.3V_RUN
12
R240
R240
DY
DY
+3.3V_ALW +3.3V_ALW
12
DY
DY
PCIE_C_TXN2
PCIE_C_TXP2
PCIE_C_TXN3
PCIE_C_TXP3
PCIE_C_TXN5
PCIE_C_TXP5
SPI_CLK_R
SPI_CS#0_R
SPI_CS#1
SPI_MOSI_R
SPI_MOSO_R
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
USB_RBIAS_PN
C315
C315
Do Not Stuff
Do Not Stuff
U25D
U25D
N29
PERN1
N28
PERP1
P27
PETN1
P26
PETP1
L29
PERN2
L28
PERP2
M27
PETN2
M26
PETP2
J29
PERN3
J28
PERP3
K27
PETN3
K26
PETP3
G29
PERN4
G28
PERP4
H27
PETN4
H26
PETP4
E29
PERN5
E28
PERP5
F27
PETN5
F26
PETP5
C29
PERN6/GLAN_RXN
C28
PERP6/GLAN_RXP
D27
PETN6/GLAN_TXN
D26
PETP6/GLAN_TXP
D23
SPI_CLK
D24
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
D25
SPI_MOSI
E23
SPI_MISO
N4
OC0#/GPIO59
N5
OC1#/GPIO40
N6
OC2#/GPIO41
P6
OC3#/GPIO42
M1
OC4#/GPIO43
N2
OC5#/GPIO29
M4
OC6#/GPIO30
M3
OC7#/GPIO31
N3
OC8#/GPIO44
N1
OC9#/GPIO45
P5
OC10#/GPIO46
P3
OC11#/GPIO47
AG2
USBRBIAS
AG1
USBRBIAS#
ICH9M-GP-NF
ICH9M-GP-NF
3
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
RN55
RN55
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
4 OF 6
4 OF 6
V27
DMI0RXN
V26
DMI0RXP
U29
DMI0TXN
U28
DMI0TXP
Y27
DMI1RXN
Y26
DMI1RXP
W29
DMI1TXN
W28
DMI1TXP
AB27
DMI2RXN
AB26
DMI2RXP
AA29
DMI2TXN
AA28
DMI2TXP
AD27
DMI3RXN
AD26
DMI3RXP
AC29
DMI3TXN
AC28
DMI3TXP
T26
DMI_CLKN
PCI-Express
PCI-Express
DMI_ZCOMP
DMI_IRCOMP
SPI
SPI
USB
USB
T25
DMI_CLKP
Direct Media Interface
Direct Media Interface
AF29
AF28
AC5
USBP0N
AC4
USBP0P
AD3
USBP1N
AD2
USBP1P
AC1
USBP2N
AC2
USBP2P
AA5
USBP3N
AA4
USBP3P
AB2
USBP4N
AB3
USBP4P
AA1
USBP5N
AA2
USBP5P
W5
USBP6N
W4
USBP6P
Y3
USBP7N
Y2
USBP7P
W1
USBP8N
W2
USBP8P
V2
USBP9N
V3
USBP9P
U5
USBP10N
U4
USBP10P
U1
USBP11N
U2
USBP11P
U25B
U25B
D11
AD0
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
J5
E1
J6
1
2
3
45
USB_PN3
USB_PP3
USB_PN5
USB_PP5
USB_PN8
USB_PP8
USB_PN9
USB_PP9
USB_PN10
USB_PP10
PCI
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#C4PIRQH#/GPIO5
ICH9M-GP-NF
ICH9M-GP-NF
USB_OC#3
USB_OC#10
USB_OC#8
USB_OC#9
DMI_RXN0 8
DMI_RXP0 8
DMI_TXN0 8
DMI_TXP0 8
DMI_RXN1 8
DMI_RXP1 8
DMI_TXN1 8
DMI_TXP1 8
DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8
DMI_RXN3 8
DMI_RXP3 8
DMI_TXN3 8
DMI_TXP3 8
CLK_PCIE_ICH# 19
CLK_PCIE_ICH 19
DMI_IRCOMP_R
USB_PN0 48
USB_PP0 48
USB_PN1 48
USB_PP1 48
USB_PN2 31
USB_PP2 31
1
TP246TP246
1
TP247TP247
USB_PN4 26
USB_PP4 26
1
TP250TP250
1
TP251TP251
USB_PN6 25
USB_PP6 25
USB_PN7 25
USB_PP7 25
1
TP248TP248
1
TP249TP249
1
TP252TP252
1
TP253TP253
USB_PN10 32
USB_PP10 32
USB_PN11 25
USB_PP11 25
2 OF 6
2 OF 6
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
2
F1
REQ0#
G4
GNT0#
B6
A7
F13
F12
E6
F6
D8
C/BE0#
B4
C/BE1#
D6
C/BE2#
A5
C/BE3#
D3
IRDY#
E3
PAR
R1
PCIRST#
C6
DEVSEL#
E4
PERR#
C2
PLOCK#
J4
SERR#
A4
STOP#
F5
TRDY#
D7
FRAME#
C14
PLTRST#
D4
PCICLK
R2
PME#
H4
K6
F2
G2
USB1
USB2
USB3
BlUETOOTH
New Card
Card Reader
CAMERA
2
1
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_IRDY#
PCIRST1#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
ICH_PME#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
1
TP179TP179
1
TP261TP261
1
TP135TP135
CLK_PCI_ICH 19
1
TP138TP138
PCI_GNT0#
R442 Do Not Stuff
R442 Do Not Stuff
SPI_CS#1
R443 Do Not Stuff
R443 Do Not Stuff
PCI_GNT3#
R441 Do Not Stuff
R441 Do Not Stuff
1 2
1 2
1 2
DY
DY
DY
DY
DY
DY
PCI_PIRQF#
PCI_TRDY#
PCI_REQ3#
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQG#
PCI_REQ0#
PCI_PIRQH#
PCI_STOP#
PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
PCI_DEVSEL#
PCI_REQ1#
PCI_FRAME#
PCI_REQ2#
PCI_SERR#
PCI_PIRQE#
PCI_PIRQA#
PCI_PIRQC#
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
BOOT BIOS Strap
SPI_CS#1 BOOT BIOS LocationPCI_GNT#0
0 1 SPI
01
PCI
11
LPC(Default)
A16 swap override strap
low = A16 swap override enable
high = default
USB
Pair
0
1
2
3
Device
USB1
USB2
USB3
RESERVED
+1.5V_RUN
1 2
PCI_GNT#3
R429
R429
24D9R2F-L-GP
24D9R2F-L-GP
4 MINI CARD
RESERVED
5
6
BLUETOOTH
NEW CARD
7
RESERVED
8
RESERVED
9
10
Card Reader
11
Main Source
Main Source
Main Source
Title
Title
Title
ICH9-PCI/PCIE/DMI/USB/GND(1/4)
ICH9-PCI/PCIE/DMI/USB/GND(1/4)
ICH9-PCI/PCIE/DMI/USB/GND(1/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
CAMERA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Roberts Discrete
Roberts Discrete
Roberts Discrete
1
RN57
RN57
SRN8K2J-4-GP
SRN8K2J-4-GP
RN25
RN25
SRN8K2J-4-GP
SRN8K2J-4-GP
RN26
RN26
SRN8K2J-4-GP
SRN8K2J-4-GP
RN58
RN58
SRN8K2J-4-GP
SRN8K2J-4-GP
RN56
RN56
SRN8K2J-4-GP
SRN8K2J-4-GP
13 60Tuesday, May 19, 2009
13 60Tuesday, May 19, 2009
13 60Tuesday, May 19, 2009
1
2
3
45
1
2
3
45
1
2
3
45
1
2
3
45
1
2
3
45
+3.3V_RUN
-1
-1
-1
5
4
3
2
1
SSID = ICH
ICH_RTCX1
R445 10MR2J-L-GPR445 10MR2J-L-GP
1 2
X4
X4
1
4
2 3
D D
SC12P50V2JN-3GP
SC12P50V2JN-3GP
C522
C522
12
X-32D768KHZ-38GPU
X-32D768KHZ-38GPU
ICH_RTCX2
12
C520
C520
SC12P50V2JN-3GP
SC12P50V2JN-3GP
1 OF 6
+RTC_CELL
R456
R456
1 2
20KR2F-L-GP
20KR2F-L-GP
C307
C307
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+RTC_CELL
R461
R461
1 2
20KR2F-L-GP
20KR2F-L-GP
C C
+1.5V_RUN
Place within 500 mil of SB.
R201 33R2J-2-GPR201 33R2J-2-GP
ICH_AZ_CODEC_BITCLK36
ICH_AZ_CODEC_SYNC36
ICH_AZ_CODEC_RST#36
ICH_SDOUT_CODEC36
12
C227
C227
DY
Do Not Stuff
Do Not Stuff
DY
HDD
B B
ODD
1 2
R197 33R2J-2-GPR197 33R2J-2-GP
1 2
R205 33R2J-2-GPR205 33R2J-2-GP
1 2
1 2
R194 33R2J-2-GPR194 33R2J-2-GP
12
C230
C230
DY
DY
Do Not Stuff
Do Not Stuff
TP235TP235
SATA_RXN0_C23
SATA_RXP0_C23
SATA_TXN023
SATA_TXP023
SATA_RXN1_C23
SATA_RXP1_C23
SATA_TXN123
SATA_TXP123
ICH_RTCRST#
12
21
G49
G49
Do Not Stuff
Do Not Stuff
12
C526
C526
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1 2
24D9R2F-L-GP
24D9R2F-L-GP
ICH_SDIN_CODEC36
1
C473 SCD01U50V2KX-1GPC473 SCD01U50V2KX-1GP
1 2
C474 SCD01U50V2KX-1GPC474 SCD01U50V2KX-1GP
1 2
C475 SCD01U50V2KX-1GPC475 SCD01U50V2KX-1GP
1 2
C476 SCD01U50V2KX-1GPC476 SCD01U50V2KX-1GP
1 2
1 2
R444
R444
Do Not Stuff
Do Not Stuff
R506
R506
DY
DY
ICH_RTCRST#
SRTCRST#
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
GPIO56
GLAN_COMP
ACZ_BIT_CLK
ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDATAOUT_R
SATA_LED#
SATA_TXN0_C
SATA_TXP0_C
SATA_TXN1_C
SATA_TXP1_C
U25A
U25A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD0
D12
LAN_TXD1
E13
LAN_TXD2
B10
GLAN_DOCK#/GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
SATA0RXN
AH16
SATA0RXP
AF17
SATA0TXN
AG17
SATA0TXP
AH13
SATA1RXN
AJ13
SATA1RXP
AG14
SATA1TXN
AF14
SATA1TXP
ICH9M-GP-NF
ICH9M-GP-NF
1 OF 6
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLAN
LPCCPU
RTCLAN / GLAN
LPCCPU
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
RCIN#
STPCLK#
THRMTRIP#
SATA4RXN
IHDA
IHDA
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATA
SATA
SATARBIAS#
SATARBIAS
INIT#
INTR
NMI
SMI#
PECI
LPC_LAD0
K5
LPC_LAD1
K4
LPC_LAD2
L6
LPC_LAD3
K2
K3
J3
J1
N7
AJ27
H_DPRSTP#
AJ25
AE23
H_FERR#_R
AJ26
AD22
AF25
AE22
AG25
L3
AF23
AF24
AH27
H_THERMTRIP_R
AG26
AG27
AH11
AJ11
AG12
AF12
AH9
AJ9
AE10
AF10
AH18
AJ18
AJ7
AH7
Placed Within 2" from SB.
SATARBIAS
Place within 500 mils from SB.
LPC_LAD[0..3]
LPC_LFRAME# 26,29
KA20GATE 29
H_A20M# 4
H_DPRSTP# 5,8,39
H_DPSLP# 5
1 2
R166 56R2J-4-GPR166 56R2J-4-GP
H_PWRGOOD 5,34
H_IGNNE# 4
H_INIT# 4
H_INTR 4
H_NMI 4
H_SMI# 4
H_STPCLK# 4
H_THERMTRIP_1
1 2
R165 54D9R2F-L1-GPR165 54D9R2F-L1-GP
CLK_PCIE_SATA# 19
CLK_PCIE_SATA 19
1 2
R187 24D9R2F-L-GPR187 24D9R2F-L-GP
LPC_LAD[0..3] 26,29
R438
R438
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R163
R163
1 2
56R2J-4-GP
56R2J-4-GP
R242
R242
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R164
R164
1 2
R167 Do Not StuffR167 Do Not Stuff
1 2
+3.3V_RUN
+1.05V_VCCP
+3.3V_RUN
+1.05V_VCCP
56R2J-4-GP
56R2J-4-GP
-1
H_FERR# 4
KBRCIN# 29
H_THRMTRIP# 4,8,29,34
+RTC_CELL
R448
R448
330KR2F-L-GP
A A
330KR2F-L-GP
R271
R271
330KR2F-L-GP
330KR2F-L-GP
R264
R264
1MR2J-1-GP
1MR2J-1-GP
12
12
12
5
ICH_INTVRMEN
LAN100_SLP
SM_INTRUDER#
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
High=Enable Low=Disable
integrated VccLan1_05VccCL1_05
LAN100_SLP
High=Enable Low=Disable
4
Main Source
Main Source
Main Source
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ICH9-LAN/HDA/SATA/LPC(2/4)
ICH9-LAN/HDA/SATA/LPC(2/4)
ICH9-LAN/HDA/SATA/LPC(2/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Roberts Discrete
Roberts Discrete
Roberts Discrete
1
-1
-1
14 60Tuesday, May 19, 2009
14 60Tuesday, May 19, 2009
14 60Tuesday, May 19, 2009
-1
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
SSID = ICH
U25C
+3.3V_ALW
RN60
RN60
1
4
23
SRN2K2J-1-GP
D D
C C
+3.3V_RUN
B B
A A
SRN2K2J-1-GP
R267 10KR2J-3-GPR267 10KR2J-3-GP
1 2
RN59
RN59
1
4
23
SRN10KJ-5-GP
SRN10KJ-5-GP
R455 10KR2J-3-GPR455 10KR2J-3-GP
1 2
RN61
RN61
1
8
2
7
3
6
45
SRN8K2J-4-GP
SRN8K2J-4-GP
R451 10KR2J-3-GPR451 10KR2J-3-GP
1 2
RN63
RN63
1
4
23
DY
DY
Do Not Stuff
Do Not Stuff
R235 8K2R2J-3-GPR235 8K2R2J-3-GP
1 2
R244 8K2R2J-3-GPR244 8K2R2J-3-GP
1 2
R247 10KR2J-3-GPR247 10KR2J-3-GP
R421 10KR2J-3-GPR421 10KR2J-3-GP
R424 10KR2J-3-GPR424 10KR2J-3-GP
R180 Do Not Stuff
R180 Do Not Stuff
R238 10KR2J-3-GPR238 10KR2J-3-GP
+3.3V_RUN
1 2
DY
DY
12
DY
DY
12
12
12
12
12
R449
R449
Do Not Stuff
Do Not Stuff
iTPM_EN
R446
R446
100KR2J-1-GP
100KR2J-1-GP
5
SMB_DATA
SMB_CLK
ME_EC_DATA1
ME_EC_CLK1
SMB_ALERT#
PM_BATLOW#_R
ITP_DBRESET#_1
ICH_RI#
ECSMI#
H_STP_CPU#
H_STP_PCI#
PM_CLKRUN#
INT_SERIRQ
GPIO18
ECSCI#
ECSWI#
GPIO22
CLKSATAREQ#
iTPM Select
iTPM_EN
0 = Disable
1 = Enable
SMB_CLK25,26
SMB_DATA25,26
TP257TP257
TP186TP186
TP181TP181
TP168TP168
TP123TP123
TP184TP184
TP262TP262
TP124TP124
TP263TP263
1
1
1
1
1
1
1
1
1
4
ITP_DBRESET#_126
PM_SYNC#8
H_STP_PCI#19
H_STP_CPU#19
PM_CLKRUN#29
PCIE_WAKE#25,38
INT_SERIRQ29
THERM_SCI#35
VGATE_PWRGD29,39
R263 Do Not Stuff
R263 Do Not Stuff
1 2
DY
DY
ECSCI#29
ECSWI#29
ECSMI#29
CLKSATAREQ#19
SB_SPKR36
MCH_ICH_SYNC#8
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
ICH_RI#
SUS_STAT#
ITP_DBRESET#_1
SMB_ALERT#
H_STP_PCI#
H_STP_CPU#
PCIE_WAKE#PCIE_WAKE#
INT_SERIRQ
VGATE_PWRGD
ICH_TP7
ECSCI#
PLTRST_DELAY#_SB
ECSWI#
ECSMI#
GPIO12
GPIO13
GPIO17
GPIO18
GPIO22
GPIO27
GPIO28
CLK_SEL0
CLK_SEL1
GPIO48
iTPM_EN
ICH_TP3
+3.3V_RUN
R179
R179
Do Not Stuff
Do Not Stuff
DY
DY
R185
R185
Do Not Stuff
Do Not Stuff
DY
DY
ICH_SMBDATA17,18,19
U25C
G16
SMBCLK
A13
SMBDATA
E17
LINKALERT#/GPIO60/CLGPIO4
C17
SMLINK0
B18
SMLINK1
F19
RI#
R4
SUS_STAT#/LPCPD#
G19
SYS_RESET#
M6
PMSYNC#/GPIO0
A17
SMBALERT#/GPIO11
A14
STP_PCI#
E19
STP_CPU#
L4
CLKRUN#
E20
WAKE#
M5
SERIRQ
AJ23
THRM#
D21
VRMPWRGD
A20
SST
AG19
TACH1/GPIO1
AH21
TACH2/GPIO6
AG21
TACH3/GPIO7
A21
GPIO8
C12
LAN_PHY_PWR_CTRL/GPIO12
C21
ENERGY_DETECT/GPIO13
AE18
TACH0/GPIO17
K1
GPIO18
AF8
GPIO20
AJ22
SCLOCK/GPIO22
A9
GPIO27
D19
GPIO28
L1
SATACLKREQ#/GPIO35
AE19
SLOAD/GPIO38
AG22
SDATAOUT0/GPIO39
AF21
SDATAOUT1/GPIO48
AH24
GPIO49
A8
GPIO57/CLGPIO5
M7
SPKR
AJ24
MCH_SYNC#
B21
TP3
AH20
PWM0
AJ20
PWM1
AJ21
PWM2
ICH9M-GP-NF
ICH9M-GP-NF
12
12
R423
R423
Do Not Stuff
Do Not Stuff
DY
DY
CLK_SEL0
CLK_SEL1
12
12
R427
R427
Do Not Stuff
Do Not Stuff
DY
DY
SMB_CLK
3 OF 6
3 OF 6
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
GPIO
GPIO
SATA
SATA
SMB
SMB
Clocks
Clocks
SYS GPIO
SYS GPIO
Power MGTController Link
Power MGTController Link
GPIO
GPIO
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
MISC
MISC
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
S4_STATE#/GPIO26
PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
GPIO24/MEM_LED
GPIO9/WOL_EN
CLK Gen Select
CLK_SEL0
Disable X X
Seligo
Realtek
ICS
RN62
RN62
1
4
23
SRN2K2J-1-GP
SRN2K2J-1-GP
U56
U56
1
2
3 4
2N7002SPT
2N7002SPT
3
1
1
0
+3.3V_RUN
SMB_DATA
6
5
AH23
AF19
AE21
AD20
H1
AF3
P1
C16
E16
G17
C10
G20
M2
B13
R3
D20
D22
R5
R6
B16
F24
B19
F22
C19
C25
A19
F21
D18
A16
C18
C11
C20
CLL_SEL1
SATA0GP
SATA1GP
SATA2GP
SATA3GP
ICH_SUSCLK
SB_SLP_S3#
PM_SLP_S5#
GPIO26
PM_PWROK
PM_BATLOW#_R
LAN_RST#1
M_PWROK
PM_SLP_M#
CL_VREF0_ICH
CL_VREF1_ICH
GPIO24
GPIO10
GPIO14
1
0
1
ICH_SMBCLK 17,18,19
CLK_14M_ICH 19
CLK_48M_ICH 19
ICH_SUSCLK 35
PM_SLP_S4# 25,29,44
1
TP259TP259
1
TP182TP182
DPRSLPVR 8,39
PM_PWRBTN# 29
RSMRST#_KBC 29
CK_PWRGD 19
M_PWROK 8
1
TP183TP183
CL_CLK0 8
CL_DATA0 8
CL_RST#0 8
1
TP180TP180
2
SB_SLP_S3#
RN49
SATA2GP
SATA3GP
SATA1GP
SATA0GP
PM_PWROKLINKALERT#
DPRSLPVR
LAN_RST#1
RSMRST#_KBC
GPIO10
GPIO13
GPIO14
GPIO17
GPIO48
M_PWROK
+3.3V_ALW
12
R268
R268
DY
DY
Do Not Stuff
Do Not Stuff
12
12
C309
C309
R261
DY
DY
U29
U29
1
2
3
Do Not Stuff
Do Not Stuff
R261
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
R5398
R5398
PLTRST_DELAY#PLTRST_DELAY#_SB
1 2
DY
DY
Do Not Stuff
Do Not Stuff
+3.3V_ALW
B
5
VCC
DY
DY
A
GND
R265
R265
1 2
Do Not Stuff
Do Not Stuff
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
PM_SLP_S3#
4
Y
ICH9-GPIO/PM/CL(3/4)
ICH9-GPIO/PM/CL(3/4)
ICH9-GPIO/PM/CL(3/4)
RN49
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
R440 10KR2J-3-GPR440 10KR2J-3-GP
1 2
R232 Do Not Stuff
R232 Do Not Stuff
1 2
DY
DY
R266 Do Not StuffR266 Do Not Stuff
1 2
R447 10KR2J-3-GPR447 10KR2J-3-GP
1 2
R502 Do Not Stuff
R502 Do Not Stuff
1 2
DY
DY
R503 Do Not Stuff
R503 Do Not Stuff
1 2
DY
DY
R507 Do Not Stuff
R507 Do Not Stuff
1 2
DY
DY
R504 Do Not Stuff
R504 Do Not Stuff
1 2
DY
DY
R505 Do Not Stuff
R505 Do Not Stuff
1 2
DY
DY
R439
R439
1 2
Do Not Stuff
Do Not Stuff
+3.3V_RUN
12
R454
R454
3K24R2F-GP
3K24R2F-GP
12
12
Roberts Discrete
Roberts Discrete
Roberts Discrete
R450
R450
C523
C523
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PLTRST_DELAY# 29,51
PM_SLP_S3# 25,29,34,35,42,43,44,50
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
+3.3V_RUN
1
2
3
45
PM_PWROK 8,29,35
453R2F-1-GP
453R2F-1-GP
15 60Tuesday, May 19, 2009
15 60Tuesday, May 19, 2009
15 60Tuesday, May 19, 2009
-1
-1
-1
5
+RTC_CELL
SSID = ICH
D D
C C
B B
A A
*Within a given well, 5VREF needs to
be up before the corresponding 3.3V rail
V5REF_S0 V5REF_S5
+3.3V_RUN
SB_VCCLAN3_3
R269
R269
1 2
Do Not Stuff
Do Not Stuff
+1.5V_RUN
R5400
R5400
1 2
Do Not Stuff
Do Not Stuff
A00
VCC_GLAN_PLL
+3.3V_RUN +5V_ALW+3.3V_ALW+5V_RUN
21
D15
D15
CH751H-40PT
CH751H-40PT
1 2
12
C304
C304
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+1.5V_RUN
12
12
C306
C306
C301
C301
DY
DY
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C303
C303
C312
C312
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
5
R274
R274
10R2J-2-GP
10R2J-2-GP
+1.5V_RUN
DY
DY
12
C276
C276
C489
C489
DY
DY
Do Not Stuff
Do Not Stuff
+1.5V_RUN
12
12
+1.5V_RUN
21
12
12
C512
C512
DY
DY
Do Not Stuff
Do Not Stuff
+1.5V_RUN
R183
R183
1 2
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C279
C279
DY
DY
D14
D14
CH751H-40PT
CH751H-40PT
C242
C242
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
TC9
TC9
Do Not Stuff
Do Not Stuff
L4
L4
1 2
L-10UH-11-GP
L-10UH-11-GP
DY
DY
C521
C521
+3.3V_RUN
Do Not Stuff
Do Not Stuff
12
C524
C524
R213
R213
10R2J-2-GP
10R2J-2-GP
1 2
12
C246
C246
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
+VCCSATAPLL+1.5V_RUN
12
C222
C222
Do Not Stuff
Do Not Stuff
VCCLAN1D05
12
DY
DY
R453
R453
1 2
Do Not Stuff
Do Not Stuff
4
12
C525
C525
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C244
C244
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C213
C213
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C481
C481
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
12
C480
C480
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_USB_S0
12
12
C482
C482
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SB_VCCLAN3_3
VCC_GLAN_PLL
3D3V_GLAN_S0
A00
4
V5REF_S0
V5REF_S5
C251
C251
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
C219
C219
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C220
C220
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C485
C485
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C483
C483
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
W24
W25
AJ19
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
AC18
AC19
AC21
AC12
AC13
AC14
A23
AE1
G25
H24
H25
K24
K25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
U24
U25
V24
V25
U23
K23
Y24
Y25
AC9
G10
AA7
AB6
AB7
AC6
AC7
A10
A11
A12
B12
A27
D28
D29
E26
E27
A26
F25
J24
J25
L23
L24
L25
T24
T27
T28
T29
G9
AJ5
U25F
U25F
A6
ICH9M-GP-NF
ICH9M-GP-NF
VCCRTC
2mA
V5REF
V5REF_SUS
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCCSATAPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCUSBPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCLAN1_05
VCCLAN1_05
VCCLAN3_3
VCCLAN3_3
VCCGLANPLL
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN3_3
2mA
646mA
47mA
1342mA
11mA
78mA
23mA
80mA
1mA
6 OF 6
6 OF 6
CORE
CORE
23mA
50mA
2mA
VCCA3GP ATXARX USB CORE
VCCA3GP ATXARX USB CORE
VCCP_CORE
VCCP_CORE
PCI
PCI
11mA
11mA
VCCPSUSVCCPUSB
VCCPSUSVCCPUSB
212mA
GLAN POWER
GLAN POWER
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
1634mA
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCCDMIPLL
VCCDMI
VCCDMI
V_CPU_IO
V_CPU_IO
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
308mA
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCHDA
VCCSUSHDA
VCCSUS1_05
VCCSUS1_05
VCCSUS1_5
VCCSUS1_5
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCCL1_05
VCCCL1_5
VCCCL3_3
VCCCL3_3
73mA
3
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
R29
W23
Y23
AB23
AC23
AG29
AJ6
AC10
AD19
AF20
AG24
AC20
B9
F9
G3
G6
J2
J7
K7
AJ4
AJ3
AC8
F17
AD8
F18
A18
D16
D17
E22
AF1
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
G22
G23
A24
B24
3
12
C496
C496
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_DMIPLL_ICH_S0
VCCDMI
SB_V_CPU_IO
SB_VCC_3_3_C
3D3V_VCCPCORE_ICH_S0
PCI_VCCP_CORE_S0
SB_VCCHDA
+VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
SB_VCCSUS3_3
VCCSUS1_05[3]
VCCSUS1_5[3]
SB_VCCCL3_3
1 2
Do Not Stuff
Do Not Stuff
12
C501
C501
1
TP243TP243
1
TP260TP260
C515
C515
1 2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R452
R452
12
C495
C495
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_DMIPLL_ICH_S0
12
C263
C263
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C488
C488
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R430
R430
1 2
Do Not Stuff
Do Not Stuff
12
C477
C477
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C507
C507
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R172
R172
1 2
DY
DY
Do Not Stuff
Do Not Stuff
12
C308
C308
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C493
C493
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3.3V_RUN
12
C492
C492
DY
DY
Do Not Stuff
Do Not Stuff
IND-1D2UH-7-GP
IND-1D2UH-7-GP
12
C265
C265
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C252
C252
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
+3.3V_RUN
12
C509
C509
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+1.5V_RUN
12
C313
C313
DY
DY
Do Not Stuff
Do Not Stuff
12
C491
C491
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C513
C513
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2
12
C503
C503
Do Not Stuff
Do Not Stuff
L5
L5
1 2
12
C253
C253
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
12
C516
C516
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
1 2
12
C302
C302
Do Not Stuff
Do Not Stuff
1 2
12
C490
C490
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
12
C511
C511
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
+1.5V_RUN
12
R434
R434
Do Not Stuff
Do Not Stuff
R437
R437
Do Not Stuff
Do Not Stuff
R191
R191
Do Not Stuff
Do Not Stuff
R270
R270
Do Not Stuff
Do Not Stuff
R436
R436
Do Not Stuff
Do Not Stuff
12
C514
C514
+1.05V_VCCP
1
A00
+1.05V_VCCP
SB_V_CPU_IO
12
12
12
C478
C478
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3.3V_RUN
+3.3V_ALW
12
C217
C217
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3.3V_ALW
+3.3V_ALW
Main Source
Main Source
Main Source
Title
Title
Title
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SB_VCC_3_3_C
12
12
C232
C232
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SB_VCCHDA
12
C221
C221
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
ICH9-POWER(4/4)
ICH9-POWER(4/4)
ICH9-POWER(4/4)
Roberts Discrete
Roberts Discrete
Roberts Discrete
C231
C231
C479
C479
Do Not Stuff
Do Not Stuff
12
C223
C223
EC56
EC56
SCD1U25V3KX-GP
SCD1U25V3KX-GP
R188
R188
1 2
Do Not Stuff
Do Not Stuff
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
+1.05V_VCCP
R431
R431
1 2
Do Not Stuff
Do Not Stuff
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
R177
R177
1 2
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3.3V_RUN
16 60Tuesday, May 19, 2009
16 60Tuesday, May 19, 2009
16 60Tuesday, May 19, 2009
+3.3V_RUN
-1
-1
-1
5
hexainf@hotmail.com
GRATIS - FOR FREE
SSID = MEMORY
M_A_DQS#[7..0]9
D D
+1.8V_SUS
DY
DY
12
C101
C101
Do Not Stuff
Do Not Stuff
12
C132
C132
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C409
C409
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C C
+0.9V_DDR_VTT
B B
A A
M_A_DQ[63..0]9
M_A_DM[7..0]9
M_A_DQS[7..0]9
M_A_A[14..0]9
Layout Note:
Place near DM1
12
C122
C122
DY
DY
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT.
12
12
C103
C103
Do Not Stuff
Do Not Stuff
5
C138
C138
C160
C160
DY
DY
Do Not Stuff
Do Not Stuff
12
C96
C96
C83
C83
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
DY
DY
12
C116
C116
12
C432
C432
12
DY
DY
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
Do Not Stuff
Do Not Stuff
12
C93
C93
C109
C109
Do Not Stuff
Do Not Stuff
12
C87
C87
C114
C114
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
4
12
C100
C100
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C118
C118
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
+V_DDR_MCH_REF
C203
C203
4
12
C106
C106
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C119
C119
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
DY
DY
12
TC8
TC8
12
C115
C115
M_A_BS#29
M_A_BS#09
M_A_BS#19
Do Not Stuff
Do Not Stuff
12
C428
C428
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_ODT08
M_ODT18
DY
DY
12
C420
C420
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C202
C202
Do Not Stuff
Do Not Stuff
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_BS#2
M_A_BS#0
M_A_BS#1
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_ODT0
M_ODT1
3
DM2
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
SKT-SODIMM200-37GP 62.10017.E21
SKT-SODIMM200-37GP 62.10017.E21
3
VDDSPD
NC#120
NC#163/TEST
RAS#
WE#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0
CK0#
CK1
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
SA0
SA1
NC#50
NC#69
NC#83
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
MH2
108
109
113
110
115
79
80
30
32
164
166
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
MH2
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
ICH_SMBDATA
ICH_SMBCLK
R55 Do Not StuffR55 Do Not Stuff
1 2
R56 Do Not StuffR56 Do Not Stuff
1 2
+1.8V_SUS
2
M_A_WE# 9
+3.3V_RUN
2
M_A_RAS# 9
M_A_CAS# 9
M_CS0# 8
M_CS1# 8
M_CKE0 8
M_CKE1 8
M_CLK_DDR0 8
M_CLK_DDR#0 8
M_CLK_DDR1 8
M_CLK_DDR#1 8
ICH_SMBDATA 15,18,19
ICH_SMBCLK 15,18,19
-1
PM_EXTTS#0 8
Layout Note:
Place these resistors close to DM1,
all trace length Max=1.5".
M_A_A9
M_A_A12
M_A_A10
M_A_BS#0
M_ODT0
M_CS0#
M_CKE1
M_A_A14
M_A_WE#
M_A_CAS#
M_CS1#
M_ODT1
M_A_A11
M_A_A7
1
put near connector
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
12
12
C74
C74
C72
C72
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
+3.3V_RUN
12
12
C54
C54
C53
C53
DY
DY
Do Not Stuff
Do Not Stuff
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
+0.9V_DDR_VTT
RN37
RN37
1
4
2 3
SRN56J-4-GP
SRN56J-4-GP
RN31
RN31
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN4
RN4
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN12
RN12
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN29
RN29
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN28
RN28
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN11
RN11
1
4
23
SRN56J-4-GP
SRN56J-4-GP
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
RN6
RN6
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN35
RN35
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN10
RN10
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN33
RN33
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN39
RN39
1
4
2 3
SRN56J-4-GP
SRN56J-4-GP
RN8
RN8
1
4
23
SRN56J-4-GP
SRN56J-4-GP
RN17
RN17
1
4
23
SRN56J-4-GP
SRN56J-4-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Roberts Discrete
Roberts Discrete
Roberts Discrete
1
12
M_A_A13
M_A_A5
M_A_A8
M_A_A6
M_A_A2
M_A_A1
M_A_A3
M_CKE0
M_A_BS#2
M_A_BS#1
M_A_RAS#
M_A_A0
M_A_A4
17 60Tuesday, May 19, 2009
17 60Tuesday, May 19, 2009
17 60Tuesday, May 19, 2009
C192
C192
Do Not Stuff
Do Not Stuff
12
C195
C195
Do Not Stuff
Do Not Stuff
-1
-1
-1
5
SSID = MEMORY
M_B_DQS#[7..0]9
D D
+1.8V_SUS
C C
+0.9V_DDR_VTT
B B
A A
DY
DY
12
C430
C430
Do Not Stuff
Do Not Stuff
12
C136
C136
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C415
C415
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_B_DQ[63..0]9
M_B_DM[7..0]9
M_B_DQS[7..0]9
M_B_A[14..0]9
Layout Note:
Place near DM2
12
DY
DY
12
C97
C97
12
C425
C425
5
Do Not Stuff
Do Not Stuff
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C112
C112
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C414
C414
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C105
C105
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C406
C406
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C107
C107
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT.
12
C418
C418
DY
DY
Do Not Stuff
Do Not Stuff
12
C124
C124
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C405
C405
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY
DY
12
C150
C150
12
C95
C95
4
12
C104
C104
Do Not Stuff
Do Not Stuff
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C410
C410
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
4
12
12
C131
C131
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C117
C117
Do Not Stuff
Do Not Stuff
+V_DDR_MCH_REF
12
Do Not Stuff
Do Not Stuff
TC4
TC4
12
C88
C88
C404
C404
DY
DY
Do Not Stuff
Do Not Stuff
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
ICH_SMBCLK15,17,19
ICH_SMBDATA15,17,19
C200
C200
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_B_BS#29
M_B_BS#09
M_B_BS#19
12
PM_EXTTS#18
M_CS2#8
M_CS3#8
M_CKE28
M_CKE38
M_B_RAS#9
M_B_CAS#9
M_B_WE#9
M_ODT28
M_ODT38
C102
C102
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C201
C201
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_BS#2
M_B_BS#0
M_B_BS#1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
ICH_SMBCLK
ICH_SMBDATA
M_ODT2
M_ODT3
3
3
DM1
DM1
MH1
MH1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC#50
69
NC#69
83
NC#83
120
NC#120
163
NC#163/TEST
110
CS0#
115
CS1#
79
CKE0
80
CKE1
108
RAS#
113
CAS#
109
WE#
197
SCL
195
SDA
114
ODT0
119
ODT1
1
VREF
201
GND
SKT-SODIMM200-38GP
SKT-SODIMM200-38GP
62.10017.E31
62.10017.E31
MH2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
CK0#
CK1#
VDD_SPD
GND
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
CK0
CK1
SA0
SA1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MH2
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
10
26
52
67
130
147
170
185
30
32
164
166
198
200
199
81
82
87
88
95
96
103
104
111
112
117
118
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
202
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
R57 Do Not StuffR57 Do Not Stuff
1 2
R54 Do Not StuffR54 Do Not Stuff
1 2
+1.8V_SUS
2
M_CLK_DDR2 8
M_CLK_DDR#2 8
M_CLK_DDR3 8
M_CLK_DDR#3 8
+3.3V_RUN
2
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
-1
+3.3V_RUN
12
EC12
EC12
SCD1U25V3KX-GP
SCD1U25V3KX-GP
Layout Note:
Place these resistors close to DM2,
all trace length Max=1.5".
RN7
M_B_CAS#
M_B_WE#
M_B_BS#2
M_CKE2
M_B_A5
M_B_A8
M_B_A0
M_B_A1
M_B_A3
M_CS3#
M_ODT3
M_CKE3
RN7
4
SRN56J-4-GP
SRN56J-4-GP
RN13
RN13
4
SRN56J-4-GP
SRN56J-4-GP
RN16
RN16
4
SRN56J-4-GP
SRN56J-4-GP
RN32
RN32
4
SRN56J-4-GP
SRN56J-4-GP
RN15
RN15
4
SRN56J-4-GP
SRN56J-4-GP
RN5
RN5
4
SRN56J-4-GP
SRN56J-4-GP
RN40
RN40
4
SRN56J-4-GP
SRN56J-4-GP
Main Source
Main Source
Main Source
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
put near connector
12
12
C75
C75
C71
C71
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
+3.3V_RUN
12
12
C52
C52
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
+0.9V_DDR_VTT
RN27
RN27
4
1
23
1
23
1
23
1
23
1
23
1
23
1
23
SRN56J-4-GP
SRN56J-4-GP
RN38
RN38
4
SRN56J-4-GP
SRN56J-4-GP
RN36
RN36
4
SRN56J-4-GP
SRN56J-4-GP
RN34
RN34
4
SRN56J-4-GP
SRN56J-4-GP
RN9
RN9
4
SRN56J-4-GP
SRN56J-4-GP
RN30
RN30
4
SRN56J-4-GP
SRN56J-4-GP
RN14
RN14
4
SRN56J-4-GP
SRN56J-4-GP
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
Roberts Discrete
Roberts Discrete
Roberts Discrete
M_ODT2
1
M_B_A13
23
M_B_A14
1
M_B_A11
23
M_B_A7
1
M_B_A6
23
M_B_A4M_B_BS#1
1
M_B_A2
23
M_B_A10
1
M_B_BS#0
23
M_B_RAS#
1
M_CS2#
23
M_B_A12
1
M_B_A9
23
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
12
C56
C56
Do Not Stuff
Do Not Stuff
18 60Tuesday, May 19, 2009
18 60Tuesday, May 19, 2009
18 60Tuesday, May 19, 2009
C193
C193
Do Not Stuff
Do Not Stuff
12
C197
C197
Do Not Stuff
Do Not Stuff
-1
-1
-1
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