Dell 1427 KFW11 Schematics

A
B
C
D
E
www.sp860.com QQ:453100829
A-PDF Watermark DEMO: Purchase from www.A-PDF.com to remove the watermark
1 1
2 2
Compal Confidential
Schematic Document
Cantiga + ICH9
2008 / 12 / 10
3 3
Rev:1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4841P
E
145Monday, December 15, 2008
1.0
of
A
B
C
D
E
Compal confidential
www.sp860.com QQ:453100829
MLK 14
File Name : LA-4841P
ZZZ1
PCB
1 1
CRT
P.17
Thermal Sensor ADT7421ARMZ
P.4
Fan conn
P.4
LVDS Panel Interface
P.16
2 2
CardBus Controller
MXM II VGA/B NB9M-GS 512M
P.33
PCI
DMI X4
Penryn -4MB (Socket P)
uFCPGA-478 CPU
P.4,5,6
H_A#(3..35) H_D#(0..63)
FSB
667/800MHz 1.05V
Intel Cantiga MCH
1329pin BGA
P.7,8,9,10,11,12
C-Link
DDR2 667/800MHz 1.8V
Dual Channel
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
P.13,14
USB conn x 4
CK505
TSSOP-64
Clock Generator ICS9LPRS397AKLFT
P.15
P.30
O2MICRO OZH24
1394
P.26
Media Card
PCI-E BUS
Intel ICH9-M
676pin BGA
P.18,19,20,21
USB2.0
Azalia
SATA Master SATA Slave
BT Conn
Camera
P.30
P.30
10/100/1000 LAN
REALTEK RTL8111C-GR
3 3
P.22
Mini-CardX1 (WLAN)
P.24
Mini-CardX1
P.24
Express Card
P.27
Express Card
Mini-Card-3
P.27
P.23
RJ45/11 CONN
LPC BUS
Audio CODEC ALC272
P.25 P.25
AMP & Audio Jack
ENE KB926
P.28
Power On/Off CKT.
4 4
DC/DC Interface CKT.
Power Circuit DC/DC
A
RTC CKT.
Power OK CKT.
Touch Pad CONN. Int.KBD
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BIOS(System/EC)
2007/1/15 2008/1/15
C
P.28P.29P.29
Deciphered Date
SATA HDD Connector
P.23
CDROM Conn.
P.23
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Block diagram
LA-4841P
E
of
245Monday, December 15, 2008
1.0
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
1 1
O MEANS ON X MEANS OFF
power plane
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+5VS
+3VS
+1.5VS
+0.9V
+B
O
O
O
O
O
X
+5VALW
+3VALW
O
O
O
O
X
XX X
+1.8V
O
XX
X
+VCCP
+CPU_CORE
+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA
OO
OO
X
X
SMBUS Control Table
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build DEBUG@ : means just reserve for debug.
SOURCE
INVERTER BATT EEPROM
SERIAL SENSOR
THERMAL (CPU)
SODIMM CLK CHIP
MINI CARD
LCD
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0A4 1 1 0 1 0 0 1 0
SMB_EC_CK1 SMB_EC_DA1
SMB_EC_CK2 SMB_EC_DA2
SMB_CK_CLK1 SMB_CK_DAT1 ICH9
LCD_CLK LCD_DAT
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
KB926
KB926
Cantiga
2005/03/10 2006/03/10
X X
X XX
Deciphered Date
VV
XX X
X XX
XX
V
X
X
X
X
VVV
XX
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
LA-4841P
XX X
X X
X
Notes List
V
345Monday, December 15, 2008
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D D
H_A#[3..16]7
H_ADSTB#07 H_REQ#07
H_REQ#17 H_REQ#27 H_REQ#37 H_REQ#47
C C
B B
A A
H_A#[17..35]7
H_ADSTB#17 H_A20M#19
H_FERR#19 H_IGNNE#19
H_STPCLK#19 H_INTR19 H_NMI19 H_SMI#19
+VCCP
B
H_PROCHOT# OCP#
H_IERR#
E
3 1
Q2
@
MMBT3904_SOT23
+VCCP
12
@
R17 56_0402_5%
2
C
R18 56_0402_5%
1 2
5
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
H_A20M# H_FERR# H_IGNNE#
H_STPCLK# H_INTR H_NMI H_SMI#
CONN@
JCPU1A
J4 L5 L4 K5
M3 N2
J1
N3
P5 P2 L2 P4 P1
R1 M1
K3
H2
K2 J3 L1
Y2
U5 R3 W6 U4
Y5
U1 R4
T5 T3
W2 W5
Y4
U2
V4
W3 AA4 AB2 AA3
V1 A6
A5
C4
D5
C6
B4 A3
M4
N5
T2 V3 B2
D2 D22
D3
F6
Penryn
OCP# 20
ADDR GROUP_0
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
A[17]# A[18]#
ADDR GROUP_1
A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
A20M# FERR# IGNNE#
STPCLK# LINT0 LINT1 SMI#
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
XDP/ITP SIGNALS
THERMAL
PROCHOT#
THERMDA THERMDC
ICH
THERMTRIP#
H CLK
RESERVED
ADS# BNR#
BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
PRDY# PREQ#
TCK
TDI TDO TMS
TRST#
DBR#
BCLK[0] BCLK[1]
H1 E2 G5
H5 F21 E1
F1 D20
B3 H4 C1
F3 F4 G3 G2
G6 E4
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
D21 A24 B25
C7
A22 A21
H_ADS# H_BNR# H_BPRI#
H_DEFER# H_DRDY# H_DBSY#
H_BR0# H_IERR#
H_INIT# H_LOCK# H_RESET#
H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H_HIT# H_HITM#
XDP_TCK XDP_TDI
XDP_TMS XDP_TRST# XDP_DBRESET#
H_PROCHOT#
H_THERMDC_R H_THERMTRIP#
CLK_CPU_BCLK CLK_CPU_BCLK#
4
H_ADS# 7 H_BNR# 7 H_BPRI# 7
H_DEFER# 7 H_DRDY# 7 H_DBSY# 7
H_BR0# 7
H_INIT# 19
H_LOCK# 7 H_RESET# 7
H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7
H_HIT# 7 H_HITM# 7
XDP_DBRESET# 20
R146 56_0402_5% R57 100_0402_5%
R53 100_0402_5%
H_THERMTRIP# 7,19
CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15
12
1 2 1 2
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
+3VS
1
C13
2
0.1U_0402_16V4Z
+VCCP
H_THERMDAH_THERMDA_R H_THERMDC
+3VS
C5
1 2
R16
1 2
10K_0402_5%
H_THERMDA H_THERMDC
2200P_0402_50V7K
L_THERM#
FAN Control circuit
C94
2
EN_DFAN1
+3VS
12
10K_0402_5%
2
1
EN_DFAN129
FAN_SPEED129
0.01U_0402_16V7K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
Thermal Sensor EMC1402-1-ACZL-TR
U2
1
VDD
2 3
EMC1402-2-ACZL-TR MSOP 8P
Address:100_1100
R61
SCLK
D+
SDATA
ALERT#
D­THERM#4GND
C76
10U_1206_16V4Z~N
C88
1000P_0402_50V7K~N
FAN1_POWER
Title
Size Document Number Rev
Custom
Date: Sheet
No need in check list
XDP_DBRESET#
XDP_TDI XDP_TMS
XDP_TRST# XDP_TCK
1 2
R51
@
R5 54.9_0402_1%
1 2
R4 54.9_0402_1%
1 2
R11 54.9_0402_1%
1 2
R35 54.9_0402_1%
1 2
This shall place near CPU
EC_SMB_CK2
8
EC_SMB_DA2
7 6 5
12
+5VS
1 2
12
40mil
C77 10U_1206_16V4Z~N U3
1
VEN
2
VIN
3
VO
4
VSET
RT9027BPS SO 8P
JFAN1
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
CONN@
FAN1
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
LA-4841P
GND GND GND GND
1
+3VS
1K_0402_5%
+VCCP
EC_SMB_CK2 29,33 EC_SMB_DA2 29,33
8 7 6 5
445Monday, December 15, 2008
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H_D#[0..15]7
D D
H_DSTBN#07 H_DSTBP#07 H_DINV#07 H_D#[16..31]7
C C
R52 1K_0402_5%@
1 2
R22 1K_0402_5%@
1 2
No need in check list
CPU_BSEL015 CPU_BSEL115 CPU_BSEL215
H_DSTBN#17 H_DSTBP#17 H_DINV#17
T2 T3 T4 T5 T6
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
V_CPU_GTLREF
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL CPU_BSEL2 CPU_BSEL1
B B
166
200
01
0
1
266 0 0 0
CONN@
JCPU1B
E22 F24 E26
G22
F23
G25
E25 E23 K24
G24
J24 J23 H22 F26 K22 H23 J26
H26 H25
N22 K25 P26 R23 L23
M24
L22
M23
P25 P23 P22 T24
R24
L25 T25
N25
L26
M26 N24
AD26
C23 D25 C24
AF26
AF1
A26
C3 B22 B23
C21
Penryn
CPU_BSEL0
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
1
0
DATA GRP 0
DATA GRP 1
MISC
PWRGOOD
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#
DATA GRP 2DATA GRP 3
D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]# COMP[0]
COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP# DPWR#
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
V_CPU_GTLREF
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP0 COMP1 COMP2 COMP3
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
+VCCP
12
R27 1K_0402_1%
12
R29 2K_0402_1%
H_D#[32..47] 7
H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7
H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7
H_DPRSTP# 7,19,43 H_DPSLP# 19
H_DPWR# 7
H_PWRGOOD 19 H_CPUSLP# 7
H_PSI# 43
To IMVP
R23
12
54.9_0402_1%
Resistor placed within
0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4
R24
12
54.9_0402_1%
27.4_0402_1%
R25
12
27.4_0402_1%
For 6 layer
Z=27.4 ohm VCCSENSE, VSSSENSE/ 14mils (MS), 16mils (SL) width, 7mils space, 25mils space to other signals Mismatch =25mils.
+CPU_CORE +CPU_CORE
R26
12
CONN@
JCPU1C
A7
VCC[001]
VCC[068]
VCC[002]
VCC[069]
VCC[003]
VCC[070]
VCC[004]
VCC[071]
VCC[005]
VCC[072]
VCC[006]
VCC[073]
VCC[007]
VCC[074]
VCC[008]
VCC[075]
VCC[009]
VCC[076]
VCC[010]
VCC[077]
VCC[011]
VCC[078]
VCC[012]
VCC[079]
VCC[013]
VCC[080]
VCC[014]
VCC[081]
VCC[015]
VCC[082]
VCC[016]
VCC[083]
VCC[017]
VCC[084]
VCC[018]
VCC[085]
VCC[019]
VCC[086]
VCC[020]
VCC[087]
VCC[021]
VCC[088]
VCC[022]
VCC[089]
VCC[023]
VCC[090]
VCC[024]
VCC[091]
VCC[025]
VCC[092]
VCC[026]
VCC[093]
VCC[027]
VCC[094]
VCC[028]
VCC[095]
VCC[029]
VCC[096]
VCC[030]
VCC[097]
VCC[031]
VCC[098]
VCC[032]
VCC[099]
VCC[033]
VCC[100] VCC[034] VCC[035]
VCCP[01] VCC[036]
VCCP[02] VCC[037]
VCCP[03] VCC[038]
VCCP[04] VCC[039]
VCCP[05] VCC[040]
VCCP[06] VCC[041]
VCCP[07] VCC[042]
VCCP[08] VCC[043]
VCCP[09] VCC[044]
VCCP[10] VCC[045]
VCCP[11] VCC[046]
VCCP[12] VCC[047]
VCCP[13] VCC[048]
VCCP[14] VCC[049]
VCCP[15] VCC[050]
VCCP[16] VCC[051] VCC[052]
VCCA[01] VCC[053]
VCCA[02] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]
VCCSENSE VCC[065] VCC[066] VCC[067]
VSSSENSE
Penryn
For 8 layer condition
AA10 AA12 AA13 AA15 AA17 AA18 AA20
AC10 AB10 AB12 AB14 AB15 AB17 AB18
A9 A10 A12 A13 A15 A17 A18 A20
B7
B9 B10 B12 B14 B15 B17 B18 B20
C9 C10 C12 C13 C15 C17 C18
D9 D10 D12 D14 D15 D17 D18
E7
E9 E10 E12 E13 E15 E17 E18 E20
F7
F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9
AB9
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VCCSENSE
AF7
VSSSENSE
AE7
.
Length match within 25 mils.
CPU_VID0 43 CPU_VID1 43 CPU_VID2 43 CPU_VID3 43 CPU_VID4 43 CPU_VID5 43 CPU_VID6 43
VCCSENSE 43
No stuff 27.4 pull down near IMVP for testing
VSSSENSE 43
+VCCP
1
Check 220u?
+
C10 330U_D2E_2.5VM_R7
2
0814 Change to 220uF 0819 Change to C_D2E
1
2
10U_0805_6.3V6M
1
C12
C11
2
0.01U_0402_16V7K
Near pin B26
+1.5VS
The trace width/space/other is 20/7/25.
+CPU_CORE
R28 100_0402_1%
1 2
R30 100_0402_1%
1 2
VCCSENSE
VSSSENSE
Close to CPU pin AD26 within 500mils.
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
2
Close to CPU pin within 500mils.
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-4841P
1
of
545Monday, December 15, 2008
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
High Frequence Decoupling
10uF 0805 X5R -> 85 degree.
+CPU_CORE
D D
C C
B B
A A
CONN@
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080] VSS[081]P3VSS[162]
Penryn
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]
VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
.
Place these caps inside the CPU socket cavity.
( Left side on Top ).
Place these caps inside the CPU socket cavity.
( Right side on Top side).
Place these caps inside the CPU socket cavity.
( Left side on Bottom ).
Place these caps inside the CPU socket cavity.
( Right side on Bottom ).
Place these caps inside the CPU socket.
+VCCP
1
C213
0.1U_0402_10V6K
2
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
330U_D2E_2.5VM_R9
1
C196
+
2
1
C209
0.1U_0402_10V6K
2
C202 10U_0805_6.3V6M
C162 10U_0805_6.3V6M
C501 10U_0805_6.3V6M
C502 10U_0805_6.3V6M
330U_D2E_2.5VM_R9
1
C198
+
2
1
C197 10U_0805_6.3V6M
2
1
C508 10U_0805_6.3V6M
2
1
C510 10U_0805_6.3V6M
2
C258
1
C212
0.1U_0402_10V6K
2
1
C529 10U_0805_6.3V6M
2
1
C252 10U_0805_6.3V6M
2
1
C514 10U_0805_6.3V6M
2
1
C515 10U_0805_6.3V6M
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
Place these caps inside
1
1
C250
the CPU socket.
+
+
2
( Right side on Top side).( Left side on Top ).
2
1
C185
0.1U_0402_10V6K
2
1
C232 10U_0805_6.3V6M
2
1
C190 10U_0805_6.3V6M
2
1
C519 10U_0805_6.3V6M
2
1
C520 10U_0805_6.3V6M
2
1
C183
0.1U_0402_10V6K
2
1
C255 10U_0805_6.3V6M
2
1
C203 10U_0805_6.3V6M
2
1
C522 10U_0805_6.3V6M
2
1
C526 10U_0805_6.3V6M
2
1
C505 10U_0805_6.3V6M
2
1
C200 10U_0805_6.3V6M
2
1
C533 10U_0805_6.3V6M
2
1
C532 10U_0805_6.3V6M
2
ESR <= 1.5m ohm Capacitor > 880 uF
Place these inside socket cavity on L8 (North side Secondary)
1
C184
0.1U_0402_10V6K
2
1
C504 10U_0805_6.3V6M
2
1
C161 10U_0805_6.3V6M
2
1
C254 10U_0805_6.3V6M
2
1
C199 10U_0805_6.3V6M
2
1
C257 10U_0805_6.3V6M
2
1
C208 10U_0805_6.3V6M
2
Place these caps inside the CPU socket.
1
( Left side on Top ).
C214 10U_0805_6.3V6M
2
Place these caps inside the CPU socket.
1
( Right side on Top ).
C226 10U_0805_6.3V6M
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
LA-4841P
1
1.0
of
645Monday, December 15, 2008
5
H_D#[0..63]5
D D
C C
H_RESET#4
H_CPUSLP#5
B B
H_RCOMP Dual core 24.9 ohm_1% pull down Quad core 16.9 ohm_1% pull down H_SWNG Dual core 100 ohm_1% pull down Quad core 75 ohm_1% pull down
Layout Note: H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R45
1K_0402_1%
A A
12
R46
2K_0402_1%
0.1U_0402_16V4Z
H_SWNG H_RCOMP
H_RESET# H_CPUSLP#
H_VREF
H_VREF
1
C391
2
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
U4A
F2
G8
F8
E6 G2 H6 H2
F6 D4 H3 M9
M11
J1
J2
N12
J6
P2
L2 R2 N9
L6 M5
J3 N2 R1 N5 N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10 Y12 Y14
Y7 W2
AA8
Y9
AA13
AA9 AA11 AD11 AD10 AD13 AE12
AE9
AA2
AD8
AA3
AD3
AD7 AE14
AF3
AC1
AE3
AC3 AE11
AE8
AG2
AD6
C5
E3
C12
E11
A11
B11
CANTIGA_1p0
H_RCOMP
12
R324
24.9_0402_1%
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_SWING H_RCOMP
H_CPURST# H_CPUSLP#
H_AVREF H_DVREF
www.sp860.com QQ:453100829
H_ADSTB#_0 H_ADSTB#_1
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
+VCCP
12
R322
221_0603_1%
100_0402_1%
H_SWNG
12
1
C386
R323
2
0.1U_0402_16V4Z
Near B3 pinwithin 100 mils from NB
5
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31
H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS#
H_BNR# H_BPRI#
H_BREQ# H_DBSY#
H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
4
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
J8 L3 Y13 Y1
L10 M7 AA5 AE6
L9 M8 AA6 AE5
B15 K13 F13 B13 B14
B6 F12 C8
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
ICH_PWROK20,29
VGATE20,29,43
H_A#[3..35] 4
SMRCOMP_VOH
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4
H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5
H_DSTBN#0 5 H_DSTBN#1 5 H_DSTBN#2 5 H_DSTBN#3 5
H_DSTBP#0 5 H_DSTBP#1 5 H_DSTBP#2 5 H_DSTBP#3 5
H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4
H_RS#0 4 H_RS#1 4 H_RS#2 4
PLT_RST#18,22,24,28,29,33
H_THERMTRIP#4,19
DPRSLPVR20,43
1 2
R408 0_0402_5%
1 2
R407 0_0402_5%@
C398
2.2U_0603_6.3V4Z
C403
2.2U_0603_6.3V4Z
1
1
C400
2
2
1
1
C404
2
2
1 2
R56 0_0402_5%
+1.8V
0.01U_0402_25V7K
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
0913 Delete V_DDR_MCH_REF from POWER circuit
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
V_DDR_MCH_REF13,14
4
V_DDR_MCH_REF
1
2
0.1U_0402_16V4Z
+1.8V
12
12
C121
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R331 1K_0402_1%
12
R332
3.01K_0402_1%
NA lead free
12
R333 1K_0402_1%
R42 1K_0402_1%
R43 1K_0402_1%
3
R82
1 2
10K_0402_5% R83
1 2
10K_0402_5%
MCH_CLKSEL015 MCH_CLKSEL115 MCH_CLKSEL215
CFG59 CFG69 CFG79
T37PAD
CFG99
CFG169
CFG199 CFG209
PM_BMBUSY#20
H_DPRSTP#5,19,43 PM_EXTTS#013 PM_EXTTS#114
1 2
R523 100_0402_5%
1
2
3
U4B
@
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
AL34
RSVD10
AK34
RSVD11
AN35
RSVD12
AM35
RSVD13
T24
RSVD14
B31
RSVD15
B2
RSVD16
M1
RSVD17
AY21
RSVD20
BG23
RSVD22
BF23
RSVD23
BH18
RSVD24
BF18
RSVD25
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC_1
BF48
NC_2
BD48
NC_3
BC48
NC_4
BH47
NC_5
BG47
NC_6
BE47
NC_7
BH46
NC_8
BF46
NC_9
BG45
NC_10
BH44
NC_11
BH43
NC_12
BH6
NC_13
BH5
NC_14
BG4
NC_15
BH3
NC_16
BF3
NC_17
BH2
NC_18
BG2
NC_19
BE2
NC_20
BG1
NC_21
BF1
NC_22
BD1
NC_23
BC1
NC_24
F1
NC_25
A47
NC_26
CANTIGA_1p0
Deciphered Date
T7 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T24
T25 T26 T27
T28
T41 T44 T73 T74
+3VS
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
T8PAD T9PAD
CFG5 CFG6 CFG7
CFG9
T65PAD T40PAD
CFG12
T67PAD
CFG13
T47PAD T10PAD T66PAD
CFG16
T68PAD T39PAD
CFG19 CFG20
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1
PM_PWROK_R
PLT_RST#_NBPLT_RST# THERMTRIP# DPRSLPVR
H_DPRSTP#
1
C53
C55
@
10P_0402_50V8J
2
10P_0402_50V8J
2006/02/13 2006/03/10
2
RSVD
CFG
DMI
PM
NC
MISC
2
1
M_CLK_DDR0
AP24
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST# DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
CLK
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
GRAPHICS VID
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
M_CLK_DDR1
AT21
M_CLK_DDR2
AV24
M_CLK_DDR3
AU20
M_CLK_DDR#0
AR24
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#SMRCOMP_VOL
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
SMRCOMP_VOH
BF28
SMRCOMP_VOL
BH28
V_DDR_MCH_REF
AV42 AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_DREFCLK
B38
CLK_MCH_DREFCLK#
A38
MCH_SSCDREFCLK
E41
MCH_SSCDREFCLK#
F41
CLK_MCH_3GPLL
F43
CLK_MCH_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33 B32 G33 F33 E33
C34
AH37 AH36 AN36 AJ35 AH34
N28 M28 G36 E36 K36 H36
B12
B28 B30 B29 C29 A28
T30 T31 T32 T33 T34
T35
CL_CLK0 CL_DATA0 M_PWROK CL_RST# CL_VREF CL_VREF
CLKREQ#_7 MCH_ICH_SYNC#
TSATN#
T99 T100 T101 T102 T103
0905 Add test point
Title
Cantiga(1/6)-AGTL/DMI/DDR
Size Document Number Rev
Custom
LA-4841P
Date: Sheet
M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR2 14 M_CLK_DDR3 14
M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#2 14 M_CLK_DDR#3 14
DDR_CKE0_DIMMA 13 DDR_CKE1_DIMMA 13 DDR_CKE2_DIMMB 14 DDR_CKE3_DIMMB 14
DDR_CS0_DIMMA# 13 DDR_CS1_DIMMA# 13 DDR_CS2_DIMMB# 14 DDR_CS3_DIMMB# 14
M_ODT0 13 M_ODT1 13 M_ODT2 14 M_ODT3 14
R328 80.6_0402_1%
1 2
R329 80.6_0402_1%
1 2
R39 10K_0402_1%
1 2
R40 499_0402_1%
1 2
T29 PAD
CLK_MCH_DREFCLK 15 CLK_MCH_DREFCLK# 15 MCH_SSCDREFCLK 15 MCH_SSCDREFCLK# 15
CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15
DMI_TXN0 20 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20
DMI_RXN0 20 DMI_RXN1 20 DMI_RXN2 20 DMI_RXN3 20
DMI_RXP0 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20
CL_CLK0 20 CL_DATA0 20 M_PWROK 20 CL_RST# 20
0.1U_0402_16V4Z
T36 T48 T63 T64
CLKREQ#_7 15 MCH_ICH_SYNC# 20
TSATN#
R521 56_0402_5%
DMI_TXP0 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20
C181
12
0814 Add pull up R
Compal Electronics, Inc.
1
1
2
+VCCP
+VCCP
12
12
745Monday, December 15, 2008
+1.8V
R100 1K_0402_1%
R99 511_0402_1%
of
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
D D
DDR_A_D[0..63]13
C C
B B
DDR_A_D0 DDR_B_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
AJ38
AJ41 AN38 AM38
AJ36
AJ40
AM44 AM42
AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36
AW36
BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12
AU10 BA11
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
BB9 BA9
AV9 BD9
AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5
AJ9 AJ8
U4D
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CANTIGA_1p0
DDR_A_BS0
BD21
SA_BS_0 SA_BS_1 SA_BS_2
SA_RAS# SA_CAS#
SA_WE#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
DDR SYSTEM MEMORY A
BG18 AT25
BB20 BD20 AY20
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_BS1 DDR_A_BS2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS#0 13 DDR_A_BS#1 13 DDR_A_BS#2 13
DDR_A_RAS# 13 DDR_A_CAS# 13 DDR_A_WE# 13
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..14] 13
DDR_B_D[0..63]14
DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AK47 AH46 AP47 AP46
AJ46
AJ48
AM48
AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44
BG43
BF43 BE45 BC41 BF40 BF41
BG38
BF38 BH35
BG35
BH40
BG39 BG34
BH34 BH14
BG12
BH11 BH12
BF11
BG8
BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1
AH1 AM2 AM3 AH3
AL1 AL2 AJ1
AJ3
U4E
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CANTIGA_1p0
DDR_B_BS0
BC16
SB_BS_0 SB_BS_1 SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8
SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
DDR SYSTEM MEMORY B
BB17 BB33
AU17 BG16 BF14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_BS1 DDR_B_BS2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS#0 14 DDR_B_BS#1 14 DDR_B_BS#2 14
DDR_B_RAS# 14 DDR_B_CAS# 14 DDR_B_WE# 14
DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
DDR_B_MA[0..14] 14
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
LA-4841P
1
1.0
of
845Monday, December 15, 2008
5
1 2 1 2
T38
T46
3VDDCCL 3VDDCDA CRT_HSYNC
CRT_VSYNC
0_0402_5%
BIA_PWM
www.sp860.com QQ:453100829
GMCH_ENBKL
GMCH_EDID_CLK_LCD GMCH_EDID_DAT_LCD
GMCH_LVDDEN
GMCH_LVDSAC­GMCH_LVDSAC+
GMCH_LVDSA0­GMCH_LVDSA1­GMCH_LVDSA2­GMCH_LVDSA3-
GMCH_LVDSA0+ GMCH_LVDSA1+ GMCH_LVDSA2+ GMCH_LVDSA3+
0_0402_5% R143
1 2
CRT_B CRT_G CRT_R
R74
1 2
R676
VGA@
CTRL_CLK CTRL_DATA
2.4K for check list
1 2
R94 2.37K_0402_1%~D
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
0_0402_5% R144
1 2
R76
R75
UMA@
UMA@
1 2
1 2
VGA@
150_0402_1%
0_0402_5% R675
1 2
150_0402_1%
150_0402_1%
1 2
UMA@
R334
1.02K_0402_1%
UMA@
1 2
BIA_PWM16
GMCH_ENBKL16
+3VS
D D
For Cantiga:2.37kohm For Crestline:2.4kohm For Calero: 1.5Kohm
R81 10K_0402_5%UMA@ R80 10K_0402_5%UMA@
GMCH_EDID_CLK_LCD16 GMCH_EDID_DAT_LCD16
GMCH_LVDDEN16
GMCH_LVDSAC-16 GMCH_LVDSAC+16
GMCH_LVDSA0-16 GMCH_LVDSA1-16 GMCH_LVDSA2-16
GMCH_LVDSA0+16 GMCH_LVDSA1+16 GMCH_LVDSA2+16
UMA place 75 ohm
0_0402_5% R142
C C
+3VS
UMA@
R483 2.2K_0402_5%
UMA@
R484 2.2K_0402_5%
B B
R74
0_0402_5%
VGA@
R76
1 2
1 2
GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD
R75
0_0402_5%
VGA@
1 2
CRT_B17 CRT_G17 CRT_R17
3VDDCCL17 3VDDCDA17 CRT_HSYNC17
CRT_VSYNC17
L32 G32 M32
M33
K33
J33
M29 C44
B43
E37
E38 C41 C40
B37
A37 H47
E46 G40
A40 H48
D45
F40
B40
A41 H38 G37
J37
B42 G38
F37
K37
F25 H25
K25 H24
C31
E32
E28 G28
J28 G29 H32
J32
J29
E29
L29
4
U4C
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK
L_CTRL_DATA L_DDC_CLK L_DDC_DATA
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
TVA_DAC TVB_DAC TVC_DAC
TV_RTN
TV_DCONSEL_0 TV_DCONSEL_1
CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK
CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
CANTIGA_1p0
R56 within 500 mils from pin T37,T36
T37
PEG_COMPI
T36
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6
LVDS
TV
R334
0_0402_5%
VGA@
PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8
PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12
PCI-EXPRESS GRAPHICS
PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3
VGA
PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
PEG_NRX_GTX_N0
H44
PEG_NRX_GTX_N1
J46
PEG_NRX_GTX_N2
L44
PEG_NRX_GTX_N3
L40
PEG_NRX_GTX_N4
N41
PEG_NRX_GTX_N5
P48
PEG_NRX_GTX_N6
N44
PEG_NRX_GTX_N7
T43
PEG_NRX_GTX_N8
U43
PEG_NRX_GTX_N9
Y43
PEG_NRX_GTX_N10
Y48
PEG_NRX_GTX_N11
Y36
PEG_NRX_GTX_N12
AA43
PEG_NRX_GTX_N13
AD37
PEG_NRX_GTX_N14
AC47
PEG_NRX_GTX_N15
AD39
PEG_NRX_GTX_P0
H43
PEG_NRX_GTX_P1
J44
PEG_NRX_GTX_P2
L43
PEG_NRX_GTX_P3
L41
PEG_NRX_GTX_P4
N40
PEG_NRX_GTX_P5
P47
PEG_NRX_GTX_P6
N43
PEG_NRX_GTX_P7
T42
PEG_NRX_GTX_P8
U42
PEG_NRX_GTX_P9
Y42
PEG_NRX_GTX_P10
W47
PEG_NRX_GTX_P11
Y37
PEG_NRX_GTX_P12
AA42
PEG_NRX_GTX_P13
AD36
PEG_NRX_GTX_P14
AC48
PEG_NRX_GTX_P15
AD40
PEG_TXN0
J41
PEG_TXN1
M46
PEG_TXN2
M47
PEG_TXN3
M40
PEG_TXN4
M42
PEG_TXN5 PEG_NTX_GRX_N5
R48
PEG_TXN6
N38
PEG_TXN7
T40
PEG_TXN8
U37
PEG_TXN9
U40
PEG_TXN10
Y40 AA46
PEG_TXN12
AA37
PEG_TXN13
AA40
PEG_TXN14
AD43
PEG_TXN15
AC46
PEG_TXP0
J42
PEG_TXP1
L46
PEG_TXP2
M48
PEG_TXP3
M39
PEG_TXP4
M43
PEG_TXP5
R47
PEG_TXP6
N37
PEG_TXP7
T39
PEG_TXP8
U36
PEG_TXP9
U39
PEG_TXP10
Y39
PEG_TXP11
Y46
PEG_TXP12
AA36
PEG_TXP13
AA39
PEG_TXP14
AD42
PEG_TXP15
AD46
3
R95
1 2
49.9_0402_1%
C568 0.1U_0402_16V7KVGA@
1 2
C537 0.1U_0402_16V7KVGA@
1 2
C538 0.1U_0402_16V7KVGA@
1 2
C539 0.1U_0402_16V7KVGA@
1 2
C540 0.1U_0402_16V7KVGA@
1 2
C541 0.1U_0402_16V7KVGA@
1 2
C542 0.1U_0402_16V7KVGA@
1 2
C543 0.1U_0402_16V7KVGA@
1 2
C544 0.1U_0402_16V7KVGA@
1 2
C545 0.1U_0402_16V7KVGA@
1 2
C546 0.1U_0402_16V7KVGA@
1 2
C547 0.1U_0402_16V7KVGA@
1 2
C548 0.1U_0402_16V7KVGA@
1 2
C549 0.1U_0402_16V7KVGA@
1 2
C550 0.1U_0402_16V7KVGA@
1 2
C551 0.1U_0402_16V7KVGA@
1 2
C552 0.1U_0402_16V7KVGA@
1 2
C553 0.1U_0402_16V7KVGA@
1 2
C554 0.1U_0402_16V7KVGA@
1 2
C555 0.1U_0402_16V7KVGA@
1 2
C556 0.1U_0402_16V7KVGA@
1 2
C557 0.1U_0402_16V7KVGA@
1 2
C558 0.1U_0402_16V7KVGA@
1 2
C559 0.1U_0402_16V7KVGA@
1 2
C560 0.1U_0402_16V7KVGA@
1 2
C561 0.1U_0402_16V7KVGA@
1 2
C562 0.1U_0402_16V7KVGA@
1 2
C563 0.1U_0402_16V7KVGA@
1 2
C564 0.1U_0402_16V7KVGA@
1 2
C565 0.1U_0402_16V7KVGA@
1 2
C566 0.1U_0402_16V7KVGA@
1 2
C567 0.1U_0402_16V7KVGA@
1 2
+VCC_PEG
PEG_NRX_GTX_N[0..15]
PEG_NRX_GTX_P[0..15]
PEGCOMP trace width and spacing is 20/25 mils.
PEG_NRX_GTX_N[0..15] 33
PEG_NRX_GTX_P[0..15] 33
PEG_NTX_GRX_N[0..15] 33
PEG_NTX_GRX_N0 PEG_NTX_GRX_N1 PEG_NTX_GRX_N2 PEG_NTX_GRX_N3 PEG_NTX_GRX_N4
PEG_NTX_GRX_N6 PEG_NTX_GRX_N7 PEG_NTX_GRX_N8
PEG_NTX_GRX_N9 PEG_NTX_GRX_N10 PEG_NTX_GRX_N11PEG_TXN11 PEG_NTX_GRX_N12 PEG_NTX_GRX_N13 PEG_NTX_GRX_N14 PEG_NTX_GRX_N15
PEG_NTX_GRX_P0
PEG_NTX_GRX_P1
PEG_NTX_GRX_P2
PEG_NTX_GRX_P3
PEG_NTX_GRX_P4
PEG_NTX_GRX_P5
PEG_NTX_GRX_P6
PEG_NTX_GRX_P7
PEG_NTX_GRX_P8
PEG_NTX_GRX_P9 PEG_NTX_GRX_P10 PEG_NTX_GRX_P11 PEG_NTX_GRX_P12 PEG_NTX_GRX_P13 PEG_NTX_GRX_P14 PEG_NTX_GRX_P15
PEG_NTX_GRX_P[0..15] 33
2
1
Strap Pin Table
CFG[2:0] FSB Freq select
CFG[4:3] Reserved
CFG5 (DMI select)
CFG6
CFG6
CFG7 (Intel Management Engine Crypto strap)
CFG8
CFG9 (PCIE Graphics Lane Reversal)
CFG10 (PCIE Lookback enable)
CFG11 CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
CFG57 CFG67 CFG77 CFG97 CFG167
CFG197 CFG207
CFG[19:20] have internal pulldown
000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
0 = DMI x 2 1 = DMI x 4 0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no confidentiality 1 =(TLS)chiper suite with confidentiality
*
Reserved
0 = Reverse Lane,15->0, 14->1 1 = Normal Operation,Lane Number in order
0 = Enable 1 = Disable
*
Reserved 00 = Reserved
01 = XOR Mode Enabled 10 = All Z Mode Enabled
ReservedCFG[15:14]
0 = Disabled 1 = Enabled
*
ReservedCFG[18:17]
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.
R66 2.21K_0402_1%~D@
1 2
R58 2.21K_0402_1%~D@
1 2
R59 2.21K_0402_1%~D@
1 2
R55 2.21K_0402_1%~D@
1 2
R70 2.21K_0402_1%~D@
1 2
CFG[5:16] have internal pullup
R72 2.21K_0402_1%~D@ R73 2.21K_0402_1%~D@
1 2 1 2
+3VS
*
*
*
(Default)11 = Normal Operation
*
*
*
0_0402_5%
VGA@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Custom
LA-4841P
2
Date: Sheet
1
945Monday, December 15, 2008
1.0
of
5
+3VS_DAC_CRT
C407
UMA@
D D
+3VS_DAC_BG
C405
UMA@
C C
+3VS_DAC_CRT
0.01U_0402_25V7K~N
C401
1
UMA@
2
B B
L11
1 2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
0.01U_0402_25V7K~N C411
1
1
UMA@
2
2
R836 0_0402_5%~D
0.1U_0402_16V4Z
0.01U_0402_25V7K~N C408
1
1
UMA@
2
2
R97
1 2
+1.5VS
0_0603_5%
+VCCP
R71
1 2
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
C402
1
UMA@
2
UMA@
1 2
UMA@
220U_D2_4VY_R15M
1
+
C68
2
C103
+3VS
+3VS_DAC_CRT
1
C175
0.1U_0402_16V4Z
2
R50
1 2
0_0805_5%
C82
1
2
+1.05VS_A_SM_CK
C104
1
1
2
2
HDMI disable connected to GND
www.sp860.com QQ:453100829
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA +1.05VS_DPLLB
+1.05VS_HPLL +1.05VS_MPLL
+1.8V_TXLVDS
+1.5VS_PEG_BG
10U_0805_10V4Z
C83
4.7U_0805_10V4Z
10U_0805_10V4Z
C122
1
2
+1.05VS_PEGPLL
+1.05VS_A_SM
1
2
1U_0603_10V4Z
C123
1
2
+3VS_DAC_CRT
+1.5VS_TVDAC
+1.5VS_QDAC +1.05VS_HPLL +1.05VS_PEGPLL
+1.8V_LVDS
1
C413
UMA@
1000P_0402_50V7K
2
1
C72
2
1U_0603_10V4Z
0.1U_0402_16V4Z
TVA 24.15mA TVB 39.48mA TVX 24.15mA
60.31mA
58.67mA
48.363mA
157.2mA
4
U4H
AXF
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
PEG
DMI
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8
VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15
VTT
VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
VCC_HV_1 VCC_HV_2 VCC_HV_3
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
VTTLF1 VTTLF2 VTTLF3
VTTLF
73mA
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
64.8mA
F47
64.8mA
139.2mA
13.2mA
720mA
50mA
VCCA_DPLLA
L48
VCCA_DPLLB
24mA
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
26mA 321.35mA
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
CRTPLLA PEGA SM
A LVDS
POWER
A CK
TV
HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
AA47
M38
L37
VCCD_HPLL VCCD_PEG_PLL
VCCD_LVDS_1 VCCD_LVDS_2
D TV/CRT
50mA
LVDS
CANTIGA_1p0
852mA
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
B22 B21 A21
124mA
BF21 BH20 BG20 BF20
118.8mA
K47 C35
B35 A35
1732mA
V48 U48 V47 U47 U46
456mA
AH48 AF48 AH47 AG47
20mils
A8 L1 AB2
C382
3
+VCCP
+V1.05VS_AXF
+1.8V_SM_CK
105.3mA
0.47U_0603_10V7K C385
1
2
220U_D2_4VY_R15M
1
+
C370
2
0.47U_0603_10V7K
1
C383
2
+1.8V_TXLVDS
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
0.47U_0603_10V7K
C65
1
2
C373
+3VS_HV
1
2
C384
1
2
C410
4.7U_0805_10V4Z
1
2
4.7U_0805_10V4Z
C56
0.1U_0402_16V4Z
1
2
2.2U_0805_16V4Z
1
2
+1.5VS_QDAC
C97
1
2
+1.05VS_DPLLA
220U_D2_4VY_R15M
1
C191
2
UMA@
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.01U_0402_25V7K~N C98
1
2
C173
+
UMA@
C174
C178
UMA@
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
10U_0805_10V4Z
C182
1
1
2
2
UMA@
L14
1 2
10U_FLC-453232-100K_0.25A_10%
10U_0805_10V4Z
1
UMA@
UMA@
2
+1.05VS_HPLL
0.1U_0402_16V4Z
C388
C387
1
2
+1.05VS_MPLL
1
C63
2
+1.05VS_PEGPLL
0.1U_0402_16V4Z C176
1
2
R69
1 2
100_0603_1%
+VCCP
1 2
L13 10U_FLC-453232-100K_0.25A_10%
UMA@
+VCCP+1.05VS_DPLLB
L29
1 2
MBK2012121YZF_0805
10U_0805_10V4Z
1
2
L9
1 2
MBK2012121YZF_0805
1
C62 10U_0805_10V4Z
2
2 1
+3VS
+VCCP
D3
@
CH751H-40PT_SOD323-2
L12
1 2
BLM18PG121SN1D_0603
10U_0805_10V4Z
C179
1
2
+1.5VS
+VCCP
+VCCP
+VCCP
+VCCP_D
1
C204
2
@
1 2
10_0402_5%
10U_0805_10V4Z
1
@
C87
2
+1.5VS_TVDAC
1
2
10U_0805_10V4Z
R113
+V1.05VS_AXF
10U_0805_10V4Z
1
2
+1.8V_SM_CK
C96
1
2
UMA@
1
C115
2
+VCC_PEG
1
+
C95
2
+1.05VS_DMI
1
C66
2
10U_0805_10V4Z
R114
1 2
0_0402_5%
1
C113
10U_0805_10V4Z
UMA@
0.022U_0402_16V7K
C114
220U_D2_4VY_R15M
C117
R112
1 2
0_0603_5%
0.1U_0402_16V4Z
C116
1U_0603_10V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
2
1
R101
1 2
0_0603_5%
C69
R102
1 2
0_0805_5%
C102
R64
1 2
0_0805_5% UMA@
R109
1 2
0_0805_5%
+VCC_PEG
+3VS_HV
+VCCP
+1.8V
+1.5VS
+VCCP
UMA@
2
+1.8V_LVDS
10U_0805_10V4Z
1
2
C187
UMA@
R110
UMA@
1
2
1 2
0_0603_5%
C186
1U_0603_10V4Z
+1.8V
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Cantiga(4/6)-PWR
LA-4841P
C401
0_0402_5%
VGA@
A A
5
C405
0_0402_5%
VGA@
C407
0_0402_5%
VGA@
C413
0_0402_5%
VGA@
C173
0_0402_5%
VGA@
C174
0_0402_5%
VGA@
C115
0_0402_5%
VGA@
U4
CRESTLINE_1p0
VGA@
C186
0_0603_5%
VGA@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
40 mils
1000P_0402_50V7K
+1.8V_TXLVDS
C414
1
2
UMA@
R350
1 2
0_0603_5%
10U_0805_10V4Z
C418
1
2
UMA@
1
10 45Monday, December 15, 2008
UMA@
+1.8V
1.0
of
5
4
3
2
1
www.sp860.com QQ:453100829
Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA
+1.8V
1
1U_0603_10V4Z VGA@
C78
2
330U_V_2.5VM
C148
330U_V_2.5VM
1
+
2
10U_0805_10V4Z
1
C165
1
+
2
2
0317 change value
10U_0805_10V4Z
1
C100
C57
VGA@
VGA@
2
10U_0805_10V4Z
0.01U_0402_16V7K
10U_0805_10V4Z
C147
1
2
+VCCP
0.1U_0402_16V4Z
1
C79
VGA@
2
T42PAD T43PAD
1
2
2
1
C80
VGA@
C164
AG34 AC34 AB34 AA34
AM33 AK33
AJ33 AG33 AF33
AE33 AC33 AA33
W33
AH28 AF28 AC28 AA28
AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24
AJ23 AH23 AF23
Y34 V34 U34
Y33 V33
U33
T32
U4F
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34
VCC_35
CANTIGA_1p0
VCC CORE
POWER
VCC NCTF
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8
VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
+VCCP
+VCCP
D D
0.22U_0402_10V4Z
10U_0805_10V4Z
220U_D2_4VY_R15M
1
C118
1
+
C374
2
2
C C
B B
0.1U_0402_16V4Z
0.22U_0402_10V4Z
C143
1
2
C120
C119
1
1
2
2
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32
AW32
AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29
AW29
AV29 AU29 AT29 AR29 AP29
BA36 BB24 BD16
BB21 AW16 AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14 AM14
AJ14
AH14
Y26
Y24
Y21
T17 T16
Y15 V15 U15
U14 T14
U4G
3000mA
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35
VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC
6326.84mA
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
VCC_AXG_SENSE VSS_AXG_SENSE
VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22
POWER
VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30
VCC SMVCC GFX
VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56
VCC GFX NCTF
VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
AV44 BA37 AM40 AV21 AY5 AM10 BB13
+VCCP
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
0.1U_0402_16V4Z
1
C99
VGA@
2
0.22U_0402_10V4Z
C70 0.1U_0402_16V4Z
1
2
4.7U_0603_6.3V6M
1
1
C86
VGA@
2
C67 0.22U_0603_10V7K
C71 0.1U_0402_16V4Z
1
1
2
2
C101
VGA@
2
C163 1U_0603_10V4Z
C145 1U_0603_10V4Z
C81 0.22U_0603_10V7K
C146 0.47U_0402_6.3V6K
1
1
1
1
2
2
2
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
CANTIGA_1p0
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
LA-4841P
1
1.0
of
11 45Monday, December 15, 2008
5
4
3
2
1
www.sp860.com QQ:453100829
U4I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
D D
C C
B B
A A
AD47 AB47
BD46 BA46 AY46 AV46 AR46
AM46
BF44 AH44 AD44 AA44
BC43 AV43 AU43
AM43
BG42 AY42 AT42 AN42
AJ42
AE42
BD41 AU41
AM41
AH41 AD41 AA41
BG40 BB40 AV40 AN40
AT39
AM39
AJ39
AE39
BH38 BC38 BA38 AU38 AH38 AD38 AA38
BF37 BB37
AW37
AT37 AN37
AJ37
BG36 BD36 AK15 AU36
N47 G47
R46 H46
U44 M44
C43
N42
U41 M41
G41
H40
N39
U38
C38
H37 C37
Y47 T47
L47
V46 P46 F46
Y44 T44 F44
J43
L42
Y41 T41
B41
E40
L39 B39
Y38 T38
J38 F38
VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
CANTIGA_1p0
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BG21
AW21
AU21 AP21 AN21 AH21 AF21 AB21
BC20 BA20
AW20
AT20
AJ20
AG20
BG19 BG17
BC17
AW17
AT17
BA16 AU16
AN16
BG15 AC15
W15
BG14 AA14
BG13 BC13 BA13
AN13
AJ13
AE13
BF12 AV12 AT12
AM12
AA12
BD11 BB11 AY11 AN11 AH11
BG10 AV10 AT10
AJ10 AE10 AA10
AM9
L12
R21 M21
G21
Y20 N20 K20 F20 C20 A20
A18
R17 M17 H17 C17
N16 K16 G16 E16
A15
C14
N13 L13 G13 E13
A12
Y11 N11 G11 C11
M10 BF9 BC9 AN9
AD9
BH8 BB8 AV8 AT8
J21
J12
G9
B9
U4J
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233
VSS_235 VSS_237
VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252
VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273
VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
CANTIGA_1p0
VSS
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14
VSS NCTF
VSS_NCTF_15 VSS_NCTF_16
VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5
VSS SCB
NC
VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325
VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350
VSS_351 VSS_352 VSS_353 VSS_354
NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
U24 U28 U25 U29
AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
BH48 BH1 A48 C1 A3
E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
LA-4841P
1
1.0
of
12 45Monday, December 15, 2008
5
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8 DDR_A_DQS[0..7]8 DDR_A_MA[0..13]8
D D
Layout Note: Place near JDIM1
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C C
B B
A A
C124
C105
1
1
2
2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
+0.9VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C106
C125
DDR_A_MA5 DDR_A_MA8
DDR_A_MA1 DDR_A_MA3
DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_BS#0 DDR_A_MA10
DDR_A_CAS# DDR_A_WE#
DDR_CS1_DIMMA# M_ODT1
DDR_CKE1_DIMMA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K C149
1
2
DDR_A_V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C126
RP14
1 4 2 3
RP13
56_0404_4P2R_5%
1 4 2 3
RP7
56_0404_4P2R_5%
1 4 2 3
RP6
56_0404_4P2R_5%
1 4 2 3
RP5
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
RP1
2 3 1 4
56_0404_4P2R_5%
1 2
R96 56_0402_5%
5
1
2
C127
C166
1
2
0.1U_0402_16V4Z
DDR_A_V
1
2
C150
www.sp860.com QQ:453100829
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C169
C154
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C167
C151
RP22 56_0404_4P2R_5%
DDR_CKE0_DIMMA
14
DDR_A_MA12
23
RP17 56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
RP15 56_0404_4P2R_5%
DDR_A_MA9
14
DDR_A_BS#2
23
RP16 56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
RP8 56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS#1
23
RP2 56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
RP23 56_0404_4P2R_5%
DDR_A_MA14
14
DDR_A_MA11
23
0.1U_0402_16V4Z
C131
C130
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C128
C107
4
0.1U_0402_16V4Z
330U 2.5V Y D2
C108
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C152
C129
Layout Note: Place these resistor closely JP41,all trace length Max=1.5"
4
3
+1.8V
JDIM2
1
VREF
3
DDR_A_D4 DDR_A_D1
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D14
DDR_A_D16 DDR_A_D17
+3VS
C58
0.1U_0402_16V4Z
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D29 DDR_A_D24
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2 DDR_A_MA12 DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS#0
DDR_A_CAS# DDR_CS1_DIMMA#
M_ODT1 DDR_A_D37
DDR_A_D36 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D35
DDR_A_D34 DDR_A_D40
DDR_A_D44 DDR_A_DM5 DDR_A_D41
DDR_A_D46 DDR_A_D49
DDR_A_D48
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D54 DDR_A_D50
DDR_A_D61 DDR_A_D60
DDR_A_DM7 DDR_A_D59
DDR_A_D58 CLK_SMBDATA
CLK_SMBCLK
1
1
2
2
C59
2.2U_0603_6.3V6K
1
C84
+
@
2
DDR_CKE0_DIMMA7
DDR_A_BS#28
DDR_A_BS#08
DDR_A_WE#8
DDR_A_CAS#8
0.1U_0402_16V4Z
1
1
2
2
C153
C168
DDR_CS1_DIMMA#7
M_ODT17
ICH_SM_DA14,15,20,24
ICH_SM_CLK14,15,20,24
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
SO-DIMM A
REVERSE
VSS DQ4 DQ5
VSS DM0
VSS DQ6 DQ7
VSS
DQ12 DQ13
VSS DM1
VSS
CK0
CK0#
VSS
DQ14 DQ15
VSS
VSS
DQ20 DQ21
VSS DM2
VSS
DQ22 DQ23
VSS
DQ28 DQ29
VSS
DQS3#
DQS3
VSS
DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36 DQ37
VSS DM4
VSS
DQ38 DQ39
VSS
DQ44 DQ45
VSS
DQS5#
DQS5
VSS
DQ46 DQ47
VSS
DQ52 DQ53
VSS
CK1
CK1#
VSS DM6
VSS
DQ54 DQ55
VSS
DQ60 DQ61
VSS
DQS7#
DQS7
VSS
DQ62 DQ63
VSS
SA0
SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
A11
92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110
S0#
112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
2
DDR_A_D5 DDR_A_D0
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D13
DDR_A_D12 DDR_A_DM1 M_CLK_DDR0
M_CLK_DDR#0 DDR_A_D11
DDR_A_D10DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_DM2 DDR_A_D23
DDR_A_D22 DDR_A_D28
DDR_A_D25 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D31
DDR_A_D30 DDR_CKE1_DIMMA
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7DDR_A_MA9 DDR_A_MA6
DDR_A_MA4 DDR_A_MA2 DDR_A_MA0
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#DDR_A_WE#
M_ODT0 DDR_A_MA13
DDR_A_D32 DDR_A_D33
DDR_A_DM4 DDR_A_D39
DDR_A_D38 DDR_A_D45
DDR_A_D47 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D43
DDR_A_D42 DDR_A_D52
DDR_A_D53 M_CLK_DDR1
M_CLK_DDR#1 DDR_A_DM6 DDR_A_D51
DDR_A_D55 DDR_A_D57
DDR_A_D56 DDR_A_DQS#7
DDR_A_DQS7 DDR_A_D62
DDR_A_D63
12
R32
R31
10K_0402_5%
10K_0402_5%
Close to VREF pins of SO-DIMM
2.2U_0805_16V4Z C201
1
2
M_CLK_DDR0 7 M_CLK_DDR#0 7
PM_EXTTS#0 7
DDR_CKE1_DIMMA 7
DDR_A_MA14 8
DDR_A_BS#1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7
M_ODT0 7
M_CLK_DDR1 7 M_CLK_DDR#1 7
12
1
0.1U_0402_16V4Z C220
1
2
V_DDR_MCH_REF 7,14
Bottom side
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/1/15 2008/1/15
3
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
DDR2 SO-DIMM I
LA-4841P
1.0
of
13 45Monday, December 15, 2008
1
5
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8 DDR_B_DQS[0..7]8 DDR_B_MA[0..13]8
D D
Layout Note: Place near JDIM2
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K C112
1
2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
C C
+0.9VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C134
C110
B B
A A
DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0
DDR_B_MA0 DDR_B_BS#1
DDR_CS2_DIMMB# DDR_B_RAS#
DDR_B_CAS# DDR_B_WE#
M_ODT3 DDR_CS3_DIMMB#
DDR_CKE3_DIMMB
C160
C139
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C135
RP18
1 4 2 3
RP10
56_0404_4P2R_5%
1 4 2 3
RP12
56_0404_4P2R_5%
1 4 2 3
RP11
56_0404_4P2R_5%
1 4 2 3
RP9
56_0404_4P2R_5%
1 4 2 3
RP3
56_0404_4P2R_5%
2 3 1 4
56_0404_4P2R_5%
1 2
R335 56_0402_5%
5
1
2
C156
www.sp860.com QQ:453100829
0.1U_0402_16V4Z C109
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C171
DDR_B_MA12 DDR_B_MA9
DDR_B_MA14 DDR_B_MA11
DDR_B_MA8 DDR_B_MA5
DDR_B_MA7 DDR_B_MA6
DDR_B_MA4 DDR_B_MA2
DDR_B_MA13 M_ODT2
DDR_B_BS#2 DDR_CKE2_DIMMB
0.1U_0402_16V4Z
C111
0.1U_0402_16V4Z
C132
1
2
0.1U_0402_16V4Z
1
2
C136
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K C138
1
2
DDR_B_V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C157
DDR_B_V
RP24 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP20 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP25
56_0404_4P2R_5%
C177
1
2
1
2
C170
14 23
14 23
14 23
14 23
14 23
14 23
14 23
0.1U_0402_16V4Z
C133
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C158
Layout Note: Place these resistor closely JP42,all trace length Max=1.5"
4
1
2
1
2
4
C137
C155
3
+1.8V
JDIM1
1
VREF
3
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
330U 2.5V Y D2
1
C189
+
@
2
DDR_CKE2_DIMMB7
DDR_B_BS#28
DDR_B_BS#08
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C159
C172
DDR_B_CAS#8
DDR_CS3_DIMMB#7
M_ODT37
ICH_SM_DA13,15,20,24
ICH_SM_CLK13,15,20,24
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_B_D17 DDR_B_D20
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D19
DDR_B_D28 DDR_B_D25
DDR_B_DM3
DDR_B_D30 DDR_B_D31
DDR_CKE2_DIMMB
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9 DDR_B_MA8
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_CS3_DIMMB#
M_ODT3 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D48
DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D51 DDR_B_D50
DDR_B_D56 DDR_B_D61
DDR_B_DM7 DDR_B_D59
DDR_B_D58 CLK_SMBDATA
CLK_SMBCLK
+3VS
1
2
1
C60
2.2U_0603_6.3V6K
2
C61
0.1U_0402_16V4Z
2007/1/15 2008/1/15
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692A-A0G16-N
SO-DIMM B REVERSE
Bottom side
Deciphered Date
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0 CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD RAS#
VDD ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1 CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
NC
A11
A7 A6
A4 A2
A0 BA1 S0#
NC
SA1
2
1
Close to VREF pins of SO-DIMM
+DDR_MCH_REF1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_B_D5 DDR_B_D4
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D13 DDR_B_DM1 M_CLK_DDR2
M_CLK_DDR#2 DDR_B_D14
DDR_B_D15
DDR_B_D21 DDR_B_D16
DDR_B_DM2 DDR_B_D22
DDR_B_D23 DDR_B_D29
DDR_B_D24 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D26
DDR_B_D27 DDR_CKE3_DIMMB
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB#
M_ODT2 DDR_B_MA13
DDR_B_D36 DDR_B_D37
DDR_B_DM4 DDR_B_D39
DDR_B_D38 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D47 DDR_B_D52
DDR_B_D53 M_CLK_DDR3
M_CLK_DDR#3 DDR_B_DM6 DDR_B_D54
DDR_B_D55 DDR_B_D60
DDR_B_D57 DDR_B_DQS#7
DDR_B_DQS7 DDR_B_D62
DDR_B_D63
10K_0402_5%
2
12
R34
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
1
C221
C222
2
2
M_CLK_DDR2 7 M_CLK_DDR#2 7
PM_EXTTS#1 7
DDR_CKE3_DIMMB 7
DDR_B_MA14 8
DDR_B_BS#1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7DDR_B_WE#8
M_ODT2 7
M_CLK_DDR3 7 M_CLK_DDR#3 7
R33
1 2
10K_0402_5%
Title
Size Document Number Rev
Custom
Date: Sheet
+3VS
Compal Electronics, Inc.
DDR2 SO-DIMM II
LA-4841P
V_DDR_MCH_REF 7,13
of
14 45Monday, December 15, 2008
1
1.0
5
PCI
SRC
CPU
CLKSEL1
0
FSA
CLKSEL0
MHz
266
MHz
1000
MHz
DOT_96
MHz
MHz
www.sp860.com QQ:453100829
33.30
14.318 96.0 48.0
FSC FSB REF
CLKSEL2
0 1000 133 33.31 14.318 96.0 48.0
0 1001 200 33.30 14.318 96.0 48.0
D D
0 1001 166 33.31 14.318 96.0 48.0
1 1000 333 33.30 14.318 96.0 48.0
1 1000 100 33.31 14.318 96.0 48.0
1 1001 400 33.30 14.318 96.0 48.0
111
R983
FSA
1 2
2.2K_0402_5% R985
FSB
1 2
0_0402_5%
R1003
1 2
0_0402_5%
CPU_BSEL05
C C
CPU_BSEL15
R973
@
1 2
56_0402_5%
1 2
R984 1K_0402_5%
12
@
R986 1K_0402_5%
+VCCP
@
R993 1K_0402_5%
1 2
1 2
R998 1K_0402_5%
12
@
R1009
0_0402_5%
Reserved
+VCCP
MCH_CLKSEL0 7
MCH_CLKSEL1 7
CLK_14M_ICH20
CLK_PCI_CB27 CLK_DEBUG_PORT24
CLK_PCI_EC29 CLK_PCI_TPM PCI_CLK18
0905 Connect PCI_CLK
4
USB MHz
NB CPU
CK_PWRGD20
CLK_SMBDATA CLK_SMBCLK
Routing the trace at least 10mil
14.31818MHZ_16P Y7
2
C1196
22P_0402_50V8J
CLK_MCH_BCLK#7 CLK_MCH_BCLK7 CLK_CPU_BCLK#4 CLK_CPU_BCLK4
R987 0_0402_5%
R991 33_0402_1%
R1000 33_0402_5% R1001 33_0402_1% R1004 33_0402_1% R1006 33_0402_5% R1008 33_0402_1%
1 2
1 2
1 2 1 2 1 2 1 2 1 2
1
R976 0_0402_5% R978 0_0402_5% R980 0_0402_5% R982 0_0402_5%
T120PAD
CLK_XTAL_OUT CLK_XTAL_IN
12
2
C1197
22P_0402_50V8J
1
1 2 1 2
R_CKPWRGD FSB
CLK_XTAL_OUT CLK_XTAL_IN
FSC
R_CLK_PCI_CB PCI2_TME R_CLK_PCI_EC 27_SEL ITP_EN
12 12
+3VS_CK505
3
R_MCH_BCLK# R_MCH_BCLK R_CPU_BCLK# R_CPU_BCLK
U55
1
CKPWRGD/PD#
2
FS_B/TEST_MODE
3
VSS_REF
4
XTAL_OUT
5
XTAL_IN
6
VDD_REF
7
REF_0/FS_C/TEST_
8
REF_1
9
SDA
10
SCL
11
NC
12
VDD_PCI
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
+3VS
+3VS_CK505
73
70
72
71
GND
CPU_0
VDD_CPU
R971
1 2
0_0805_5%
67
69
68
CPU_1
CPU_0#
CPU_1#
VSS_CPU
+3VS_CK505
1
C1189 10U_0805_10V4Z
2
0905 Connect to +VCCP
+1.05VS_CK505
R_CLKREQ#_EXPCARD
63
64
60
66
62
65
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
61
SRC_7
VDD_SRC_IO
SRC_8#/CPU_ITP#
59
SRC_7#
VSS_SRC
58
CLKREQ_6#
R_PCIE_EXPR R_PCIE_EXPR#
56
55
57
SRC_6
SRC_6#
VDD_SRC
1
2
+VCCP
+3VS_CK505
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#
C1190
0.1U_0402_16V4Z
R972
1 2
0_0805_5%
2
1
C1191
0.1U_0402_16V4Z
2
Place close to U55
0.1U_0402_16V4Z
1
C1198
2
10U_0805_10V4Z
R977 0_0402_5%
1 2
R979 0_0402_5%
1 2
R981 0_0402_5%
1 2
+1.05VS_CK505
H_STP_PCI#
54
H_STP_CPU#
53 52
R_CLK_Rob#
51
R_CLK_Rob
50
R_CLKREQ#_ROB
49
R_PCIE_SATA
48
R_PCIE_SATA#
47
R_CLKSATAREQ#
46
R_CLK_PCIE_LAN#
45
R_CLK_PCIE_LAN
44
R_CLKREQ#_GLAN
43 42 41
R_CLK_PCIE_MCARD#
40
R_CLK_PCIE_MCARD
39 38 37
1
C1192
0.1U_0402_16V4Z
2
1
1
2
C1200
C1199
2
0.1U_0402_16V4Z
EXPCARD_REQ#16 28 CLK_PCIE_EXPR 28 CLK_PCIE_EXPR# 28
H_STP_PCI# 20
H_STP_CPU# 20
R988 0_0402_5%
1 2
R989 0_0402_5%
1 2
R990 0_0402_5%
1 2
R992 0_0402_5%
1 2
R994 0_0402_5%
1 2
R995 0_0402_5%
1 2
R996 0_0402_5%
1 2
R997 0_0402_5%
1 2
R999 0_0402_5%
1 2
R1002 0_0402_5%
1 2
R1005 0_0402_5%
1 2
R1007 0_0402_5%
1 2
1
C1193
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
C1201
2
0.1U_0402_16V4Z
Express Card
0.1U_0402_16V4Z
1
C1202
2
CPU_STP
1
1
C1194
0.1U_0402_16V4Z
2
+1.05VS_CK505
1
1
C1203
2
2
0.1U_0402_16V4Z
CLK_PCIE_Rob# 24 CLK_PCIE_Rob 24 ROBSON_REQ#10 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19 CLKSATAREQ# 20 CLK_PCIE_LAN# 22 CLK_PCIE_LAN 22 GLAN_REQ#9 22
WLAN_REQ#4 24 CLK_PCIE_MCARD# 24 CLK_PCIE_MCARD 24
1
C1195
0.1U_0402_16V4Z
2
C1204
MiniCard_Roboson
ICH_SATA
GLAN
MiniCard_WLAN
VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO26VDD_PLL327LCDCLK/27M
+VCCP
12
@
R1011
B B
CPU_BSEL25
A A
FSC
R1016
1 2
10K_0402_5% R1020
1 2
0_0402_5%
1K_0402_5%
1 2
R1017 1K_0402_5%
12
@
R1025 0_0402_5%
ITP_EN
27_SEL
PCI2_TME
+3VS_CK505 +3VS_CK505
12 @
12
5
0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable SRC0 & 27MHz(DIS)
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
R1029 10K_0402_5%
ITP_EN 27_SEL
R1032 10K_0402_5%
MCH_CLKSEL2 7
12
VGA@
R1030 10K_0402_5%
12
UMA@
R1033 10K_0402_5%
NB (UMA)
VGA (Discrete)
+3VS_CK505
1 2
PCI2_TME
1 2
R1031 10K_0402_5%
R1034 10K_0402_5%
@
CLK_48M_ICH20 CLKREQ#_77
CLK_MCH_DREFCLK7 CLK_MCH_DREFCLK#7
CLK_PCIE_VGA33 CLK_PCIE_VGA#33
4
R1013 33_0402_1%
1 2
R1014 0_0402_5%
1 2
R1019 0_0402_5%UMA@ R1021 0_0402_5%UMA@
R1024 0_0402_5%VGA@ R1026 0_0402_5%VGA@
12 12
12 12
SB, MINI PCI
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FSA R_CLKREQ#_7
+1.05VS_CK505
R_MCH_DREFCLK R_MCH_DREFCLK#
ICH_SM_DA13,14,20,24
ICH_SM_CLK13,14,20,24
Issued Date
+3VS_CK505
2006/02/13 2006/03/10
3
LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#
24
25
28
1 2
R1112
1 2
R1132 0_0402_5%
S IC ICS9LPRS397AKLFT MLF 72P CLK GEN
36
R_PCIE_ICH# R_PCIE_ICH
R_MCH_3GPLL# R_MCH_3GPLL
+1.05VS_CK505
SSCDREFCLK# SSCDREFCLK
0_0402_5%
R1010 0_0402_5% R1012 0_0402_5%
R1015 0_0402_5% R1018 0_0402_5%
R1022 0_0402_5%UMA@ R1023 0_0402_5%UMA@
R1067 0_0402_5%VGA@ R1195 0_0402_5%VGA@
Deciphered Date
2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
CLK_SMBDATA
CLK_SMBCLK
CLK_PCIE_ICH# 20 CLK_PCIE_ICH 20
CLK_MCH_3GPLL# 7 CLK_MCH_3GPLL 7
MCH_SSCDREFCLK# 7 MCH_SSCDREFCLK 7
CLK_NVSS_27M 33 CLK_NV_27M 33
EXPCARD_REQ#16 ROBSON_REQ#10 CLKSATAREQ# GLAN_REQ#9 WLAN_REQ#4 CLKREQ#_7
Title
Size Document Number Rev
Date: Sheet
ICH
NB_3GPLL
NB_SSC (UMA) VGA_27M (DIS)
+3VS
1 2
R90 10K_0402_5%
1 2
R89 10K_0402_5%
1 2
R88 10K_0402_5%
1 2
R87 10K_0402_5%
1 2
R85 10K_0402_5%
1 2
R60 10K_0402_5%
Compal Electronics, Inc.
Clock Generator CK505
LA-4841P
15 45Monday, December 15, 2008
1
of
1.0
A
B
C
D
E
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1 1
JEPICO Conn.
2 2
L C D
+LCDVDD +5VALW
100_0603_1%
2
Q9
2
G
12
MXMII Conn.
R135
1 2
47K_0402_5%
R136 1K_0402_5%
BSS138_NL_SOT23
13
D
0.047U_0402_16V7K
S
1 2
C415 470P_0402_50V7K
1 2
C416 470P_0402_50V7K
1 2
C417 470P_0402_50V7K
R137
1 2 13
D
Q7
2N7002LT1G_SOT23
GMCH_LVDDEN9
VGA_LVDDEN33
LCD_VCC_TEST_EN29
3 3
GMCH_LVDDEN
CH751H-40PT_SOD323-2 UMA@
VGA_LVDDEN
CH751H-40PT_SOD323-2
LCD_VCC_TEST_EN
D9
2 1
D8
2 1
R662
VGA@
0_0402_5%
G
S
R138
@
12
10K_0402_5%
Routing Diagram
LVDS
Use Daisy chain to route
BIA_PWM9
4 4
INVERTER Conn.
INVT_PWM29 DAC_BRIG29
BIA_PWM INVT_PWM
INVT_PWM DISPOFF# DAC_BRIG
R20 10_0402_5%@
INVPWR_B+
A
12
1
C36
1U_0603_10V4Z@
2
JIVT1
1 2 3 4 5 6 7
MOLEX_53780-0790
CONN@
DAC_BRIG INVT_PWM DISPOFF#
12
C46
LVDS Bus
W=60mils
2
1
2
G
4.7U_0805_10V4Z
NBR
+3VS
S
SI2301BDS-T1-E3 1P SOT23 Q6
7.3
D
1 3
+LCDVDD
1
C43
0.1U_0402_16V4Z
2
B
W=60mils
+LCDVDD
1
C41
2
+LCDVDD
INVPWR_B+
EC_ENBKL29
BKOFF#29
GMCH_ENBKL9
VGA_ENBKL33
LCD/PANEL BD. Conn.
R41 47K_0402_5%
1
2
R19
1 2
LVDSA0­LVDSA0+
+LCDVDD_L
C796 220P_0402_50V7K
B+
+3VS
LCD_DET#29
60 MIL
L55
12
0_0805_5%
+3VS +3VS
1 2
0_0805_5%
2
2
C32
C34
0.1U_0603_50V4Z
1
1
0.1U_0603_50V4Z
EC_ENBKL
BKOFF#
R655
12
0_0402_5%UMA@
R651
12
0_0402_5%VGA@
JLVDS1
112
3
3
5
5
7
7 9910 111112
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
GND1
32
GND2
ACES_88242-3001 CONN@
EC_ENBKL
2 4
4
6
6
8
8
10 12 14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
Follow HEL80's pin definition Except pin 29
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+3VS
12
R21
4.7K_0402_5%
DISPOFF#
21
21
R652
2.2K_0402_5%
VGA@
BISTLCD_DET#
EDID_DAT_LCD EDID_CLK_LCD
D26 CH751H-40_SC76
D25 CH751H-40_SC76@
BIST 29
LVDSA1­LVDSA1+
LVDSA2­LVDSA2+
LVDSAC­LVDSAC+
1
C797 220P_0402_50V7K
2
0208 Add C796 , C797 for EMI
Issued Date
2007/1/15 2008/1/15
R652
100K_0402_5%
UMA@
Compal Secret Data
Deciphered Date
D
LVDSAC+ LVDSAC-
LVDSA0+ LVDSA0-
LVDSA1+ LVDSA1-
LVDSA2+ LVDSA2-
EDID_CLK_LCD EDID_DAT_LCD
VGA_LVDSAC+33
VGA_LVDSAC-33
VGA_CLK_LCD33 VGA_DAT_LCD33
R508 0_0402_5%UMA@
1 2
R510 0_0402_5%UMA@
1 2
R1196 0_0402_5%UMA@
1 2
R570 0_0402_5%UMA@
1 2
R595 0_0402_5%UMA@
1 2
R596 0_0402_5%UMA@
1 2
R597 0_0402_5%UMA@
1 2
R598 0_0402_5%UMA@
1 2
R599 0_0402_5%UMA@
1 2
R600 0_0402_5%UMA@
1 2
VGA_LVDSAC+ VGA_LVDSAC-
VGA_LVDSA0+33 VGA_LVDSA0-33
VGA_LVDSA1+33 VGA_LVDSA1-33
VGA_LVDSA2+33 VGA_LVDSA2-33
VGA_LVDSA0+ VGA_LVDSA0-
VGA_LVDSA1+ VGA_LVDSA1-
VGA_LVDSA2+ VGA_LVDSA2-
VGA_CLK_LCD VGA_DAT_LCD
Title
Size Document Number Rev
Custom
Date: Sheet
GMCH_LVDSAC+ GMCH_LVDSAC-
GMCH_LVDSA0+ GMCH_LVDSA0-
GMCH_LVDSA1+ GMCH_LVDSA1-
GMCH_LVDSA2+ GMCH_LVDSA2-
GMCH_EDID_CLK_LCD GMCH_EDID_DAT_LCD
R630 0_0402_5% VGA@
1 2
R633 0_0402_5% VGA@
1 2
R634 0_0402_5% VGA@
1 2
R635 0_0402_5% VGA@
1 2
R601 0_0402_5% VGA@
1 2
R602 0_0402_5% VGA@
1 2
R603 0_0402_5% VGA@
1 2
R604 0_0402_5% VGA@
1 2
R644 0_0402_5% VGA@
1 2
R645 0_0402_5% VGA@
1 2
Compal Electronics, Inc.
CRT CONN/LCD CONN
LA-4841P
E
GMCH_LVDSAC+ 9 GMCH_LVDSAC- 9
GMCH_LVDSA0+ 9 GMCH_LVDSA0- 9
GMCH_LVDSA1+ 9 GMCH_LVDSA1- 9
GMCH_LVDSA2+ 9 GMCH_LVDSA2- 9
GMCH_EDID_CLK_LCD 9 GMCH_EDID_DAT_LCD 9
LVDSAC+ LVDSAC-
LVDSA0+ LVDSA0-
LVDSA1+ LVDSA1-
LVDSA2+ LVDSA2-
EDID_CLK_LCD EDID_DAT_LCD
16 45Monday, December 15, 2008
of
1.0
5
4
3
2
1
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DAN217_SC59@
1
2
3
1
C28
2
4.7P_0402_50V8C
1 2
R326 0_0603_5%
R325 0_0603_5%
D20
DAN217_SC59@
C3
1 2
1
2
3
1
2
4.7P_0402_50V8C
MSEN#29
1
2
CRT_R_L
CRT_G_L
CRT_B_L
1
C27
2
4.7P_0402_50V8C
D27
C R T
VGA@
VGA_CRT_R33
VGA_CRT_G33
D D
VGA_CRT_B33
CRT_R9
CRT_G9
CRT_B9
CRT_HSYNC9
VGA_HSYNC33
C C
VGA_VSYNC33
CRT_VSYNC9
12
R63 0_0402_5%
VGA@
12
R125 0_0402_5%
VGA@
12
R98 0_0402_5%
UMA@
12
R376 0_0402_5%
UMA@
12
R374 0_0402_5%
UMA@
12
R375 0_0402_5%
C433 0.1U_0402_16V4Z
CRT_HSYNC
CRT_VSYNC
UMA@
1 2
R124 30_0402_5%
VGA@
R392 0_0402_5%
VGA@
R393 0_0402_5%
UMA@
1 2
R123 30_0402_5%
Close to GMCH
CRT_R_C
CRT_G_C
CRT_B_C
12
12
R367
R364
1 2
R366
150_0402_1%
150_0402_1%
150_0402_1%
12
12
CRT_VSYNC_B D_CRT_VSYNC
1
12
@
@
C430
C432
2
22P_0402_50V8J
+CRT_VCC
5
1
P
4
OE#
A2Y
G
U6
74AHCT1G125GW_SOT353-5
3
1 2
C26 0.1U_0402_16V4Z
22P_0402_50V8J
Close to VGA
1
C431
2
1
@
2
22P_0402_50V8J
+CRT_VCC
1 2
L25
BK1608LL121-T 0603
1 2
L20
BK1608LL121-T 0603
1 2
L21
BK1608LL121-T 0603
For EMI
R368 10K_0402_5%
5
1
P
4
OE#
A2Y
G
U574AHCT1G125GW_SOT353-5
3
+3VS
12
D_CRT_HSYNC
1
D22
DAN217_SC59@
2
3
HSYNC_L
VSYNC_L
C397
15P_0402_50V8J
+5VS
1
C399
2
15P_0402_50V8J
DDC_MD2
1
C24
2
1
C435
2
100P_0402_50V8J
D52
2 1
RB411DT146 SOT23
0.1U_0402_16V4Z
1
100P_0402_50V8J
C4
2
100P_0402_50V8J
C25
C6
1
2
W=40milsW=40mils
1
2
VGA_DDC_DATA_C
VGA_DDC_CLK_CCRT_HSYNC_B
100P_0402_50V8J
+CRT_VCC
1
2
C436
@
0.1U_0402_16V4Z JCRT1
6
11
1
16
7
17
12
2 8
13
3 9
14
4 10 15
5
SUYIN_070549FR015S208CR
CONN@
原本為
VGA_DDC_DATA_C
VGA_DDC_CLK_C
4.7K
+CRT_VCC +3VS
R103
R6
1 2
1 2
2K_0402_5%
2K_0402_5%
1 3
D
BSS138_NL_SOT23
BSS138_NL_SOT23
+3VS+CRT_VCC +3VS
R77
R108
1 2
2.2K_0402_5%
2
G
S
2
G
Q3
1 3
D
Q5
R107
1 2
2.2K_0402_5%
S
原本為
10K
1 2
2.2K_0402_5%
UMA@
12
R126 0_0402_5%
UMA@
12
R84 0_0402_5%
VGA@
12
R127 0_0402_5%
VGA@
12
R78 0_0402_5%
3VDDCDA 9
3VDDCCL 9
VGA_DDCDATA 33
VGA_DDCCLK 33
B B
A A
Title
<Title>
Size Document Number Rev
LA-4841P 1.0
Custom
5
4
3
2
Date: Sheet
1
of
17 45Monday, December 15, 2008
5
4
3
2
1
+3VS
R1035 8.2K_0402_5%
1 2
R1036 8.2K_0402_5%
1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
12
R1037 8.2K_0402_5% R1038 8.2K_0402_5%
D D
C C
R1039 8.2K_0402_5% R1040 8.2K_0402_5% R1041 8.2K_0402_5% R1042 8.2K_0402_5%
+3VS
R1043 8.2K_0402_5% R1044 8.2K_0402_5% R1045 8.2K_0402_5% R1046 8.2K_0402_5% R1047 8.2K_0402_5% R1048 8.2K_0402_5% R1049 8.2K_0402_5% R1050 8.2K_0402_5%
R1051 8.2K_0402_5% R1052 8.2K_0402_5% R1053 8.2K_0402_5% R1054 8.2K_0402_5%
PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR#
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#
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PCI_AD[0..31]27
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQG# PCI_PIRQD#
U56B
D11
AD0
C8 D9
E12
E9 C9
E10
B7 C7 C5
G11
F8
F11
E7 A3 D2
F10
D5
D10
B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
J5
E1
J6
PCI
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
Interrupt I/F
PIRQA# PIRQB# PIRQC# PIRQD#C4PIRQH#/GPIO5
ICH9M REV 1.0
REQ0#
GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
C/BE0# C/BE1# C/BE2# C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR# STOP# TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2 PIRQF#/GPIO3
PIRQG#/GPIO4
F1 G4 B6 A7 F13 F12 E6 F6
D8 B4 D6 A5
D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
C14 D4 R2
H4 K6 F2 G2
PCI_REQ0# PCI_GNT0# PCI_REQ1#
PCI_REQ2# PCI_REQ3#
PCI_GNT3# PCI_CBE#0
PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
PCI_PLTRST# PCI_CLK
PCI_PIRQE# PCI_PIRQF#
PCI_PIRQH#
C2
12
@
R10 33_0402_5%@
22P_0402_50V8J
PCI_REQ0# 27 PCI_GNT0# 27
PCI_CBE#0 27 PCI_CBE#1 27 PCI_CBE#2 27 PCI_CBE#3 27
PCI_IRDY# 27 PCI_PAR 27
PCI_DEVSEL# 27
PCI_STOP# 27 PCI_TRDY# 27 PCI_FRAME# 27
PCI_CLK 15 EC_PME# 20,29
PCI_PIRQG# 27
1 2
PCI_CLK
B B
PCI_GNT3#
A A
A16 swap override Strap
Low= A16 swap override Enble High= Default
R1055
PCI_GNT3#
@
1 2
5
*
1K_0402_5%
Boot BIOS Strap
PCI_GNT0# SPI_CS#1
0
1
1
SPI_CS1#_R20
4
1
0
1
SPI_CS1#_R
PCI_GNT0#
Boot BIOS Location
SPI
PCI
LPC
*
R1058
@
1 2
1K_0402_5%
R1060
@
1 2
1K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VALW
3
PCI_PCIRST#
PCI_PLTRST#
2006/02/13 2006/03/10
Deciphered Date
2
R1057 0_0402_5%
12
+3VALW
5
U58
@
2
P
B
1
A
R1061 0_0402_5%
12
Title
Size Document Number Rev
Date: Sheet
PLT_RST#
4
Y
G
MC74VHC1G08DFT2G SC70 5P
3
Compal Electronics, Inc.
ICH9(1/4)-PCI/INT
LA-4841P
12
R1056 100K_0402_5%
12
R1059 100K_0402_5%
1
PCI_RST# 27
PLT_RST# 7,22,24,28,29,33
of
18 45Monday, December 15, 2008
1.0
5
4
3
2
1
+RTCVCC
1 2
R1062 1M_0402_5%
1 2
R1064 330K_0402_1%
1 2
R1065 330K_0402_1%
D D
SM_INTRUDER# LAN100_SLP ICH_INTVRMEN
PLACE UNDER OPNE DOOR
1U_0603_10V4Z
R1069
C C
C1211
4.7P_0402_50V8J
1 2
10M_0402_5%
1
2
Y8
1 4 2 3
32.768KHZ_12.5P_MC-146
ICH_RTCX1
ICH_RTCX2
1
C1212
4.7P_0402_50V8J
2
HDD
ODD
XOR CHAIN ENTRANCE STRAP:RSVD
B B
+3VS
R1082
@
1 2
1K_0402_5%
R1083
@
1 2
1K_0402_5%
RTCVREF
A A
BAT54CW_SOT323~D
D55
27.4
ICH_RSVD
2
ACZ_SDOUT
+COINCELL
12
Z4012
3
1
5
R1234 1K_0402_5%~D
+RTCVCC
1
C1451 1U_0603_10V4Z~D
2
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C1220
ADC_ACZ_SDIN025 HDA_SDIN128
PSATA_IRX_DTX_N0_C23
PSATA_IRX_DTX_P0_C23 PSATA_ITX_DRX_N023 PSATA_ITX_DRX_P023
ODD_IRX_DTX_N0_C23
ODD_IRX_DTX_P0_C23 ODD_ITX_DRX_N023 ODD_ITX_DRX_P023
ICH_RSVD 20
+RTCVCC
1 2
R1068 20K_0402_5%
1 2
R1109 20K_0402_5%
1
JOPEN2
@
1U_0603_10V4Z
1 2
2
+1.5VS
1
C1210
2
R1073 24.9_0402_1%
PSATA_ITX_DRX_N0 PSATA_ITX_DRX_P0
ACZ_SYNC25
HDA_SYNC_MDC28
ACZ_BITCLK25 HDA_BITCLK_MDC28
ACZ_RST#25 HDA_RST_MDC#28
ACZ_SDOUT25 HDA_SDOUT_MDC28
4
JOPEN1
@
1 2
0.01U_0402_50V7K
C1213
1 2
C1214
1 2
0.01U_0402_50V7K
0.01U_0402_50V7K
C1215
1 2 1 2
C1216
0.01U_0402_50V7K
R315 33_0402_5% R306 33_0402_5%
R316 33_0402_5% R307 33_0402_5%
R317 33_0402_5% R312 33_0402_5%
1 2
1 2 1 2
1 2 1 2
1 2 1 2
T123PAD T124PAD
PSATA_ITX_DRX_N0_C PSATA_ITX_DRX_P0_C
ODD_ITX_DRX_N0_CODD_ITX_DRX_N0 ODD_ITX_DRX_P0_CODD_ITX_DRX_P0
1 2
R817 0_0402_5%
1 2
R818 0_0402_5% @
ICH_RTCX1 ICH_RTCX2
ICH_RTCRST# SRTCRST# SM_INTRUDER#
ICH_INTVRMEN LAN100_SLP
GLAN_COMP HDA_BITCLK
HDA_SYNC HDARST# ADC_ACZ_SDIN0
HDA_SDIN1
HDA_SDOUT
HDA_SYNC
HDA_BITCLK_MDC_R
HDARST#
HDA_SDOUT
U56A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD0
D12
LAN_TXD1
E13
LAN_TXD2
B10
GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
SATA0RXN
AH16
SATA0RXP
AF17
SATA0TXN
AG17
SATA0TXP
AH13
SATA1RXN
AJ13
SATA1RXP
AG14
SATA1TXN
AF14
SATA1TXP
ICH9M REV 1.0
1 2
R1198
1 2
R1130 33_0402_5%
33_0402_5%
@
RTCLAN / GLANIHDASATA
LPCCPU
HDA_BITCLKHDA_BITCLK_AUDIO_R
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT# INTR
RCIN#
SMI#
STPCLK#
THRMTRIP#
TP12
SATA4RXN SATA4RXP SATA4TXN
SATA4TXP
SATA5RXN SATA5RXP SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
LPC_AD0
K5
LPC_AD1
K4
LPC_AD2
L6
LPC_AD3
K2
LPC_FRAME#
K3
LPC_DRQ0#
J3 J1
GATEA20
N7
H_A20M#
AJ27 AJ25
H_DPSLP#
AE23
R_H_FERR#
AJ26
H_PWRGOOD
AD22
H_IGNNE#
AF25
H_INIT#
AE22
H_INTR
AG25
KB_RST#
L3
H_NMI
AF23
NMI
H_SMI#
AF24
H_STPCLK#
AH27
THRMTRIP_ICH#
AG26 AG27
AH11 AJ11 AG12 AF12
AH9 AJ9 AE10 AF10
CLK_PCIE_SATA#
AH18
CLK_PCIE_SATA
AJ18 AJ7
R1081
AH7
1 2
24.9_0402_1%
Within 500 mils
modify_11/12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Deciphered Date
LPC_AD[0..3] 24,29
LPC_FRAME# 24,29
T121 PAD T122 PAD
GATEA20 29 H_A20M# 4
R1071
1 2
1 2
H_PWRGOOD 5 H_IGNNE# 4 H_INIT# 4
H_INTR 4
KB_RST# 29
H_NMI 4 H_SMI# 4
H_STPCLK# 4 1 2
2
0_0402_5%
56_0402_5%
R1072
R1078 54.9_0402_1%
H_DPRSTP#H_DPRSTP_R#
H_FERR#
3/28 add 56ohm
CLK_PCIE_SATA# 15 CLK_PCIE_SATA 15
+3VS
GATEA20
KB_RST#
+VCCP
R1063
1 2
10K_0402_5% R1066
1 2
10K_0402_5%
+VCCP
R1070
H_DPRSTP# 5,7,43 H_DPSLP# 5
56_0402_5%
1 2
H_FERR# 4
within 2" from R1557
12
R1075 56_0402_5%
H_THERMTRIP# 4,7
placed within 2" from ICH8M
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
ICH9(2/4)_LAN,HD,IDE,LPC
LA-4841P
1
19 45Monday, December 15, 2008
1.0
of
5
ICH8 don't have
1 2
R1096 10K_0402_5% @
SERIRQ PCI_CLKRUN# EC_THERM# OCP# CLKSATAREQ# PM_BMBUSY# EC_SCI#
SB_SPKR
+3VALW
www.sp860.com QQ:453100829
R1085 2.2K_0402_5% R1087 2.2K_0402_5%
ICH_SMBCLK24,28 ICH_SMBDATA24,28
+3VS
D D
1 2
R1084 10K_0402_5%
1 2
R1086 8.2K_0402_5%
1 2
R1088 8.2K_0402_5%@
1 2
R1090 10K_0402_5%
1 2
R1093 10K_0402_5%
1 2
R1094 8.2K_0402_5%@
1 2
R1095 8.2K_0402_5%
+3VS
low-->default
High -->No boot
+3VS
R1101 10K_0402_5%@
1 2
VGATE7,29,43
R1102 100K_0402_5%
checklist pull hi
0825 Change GPIO pin assignment 0612 Change GPIO pin assignment
ICH_PCIE_WAKE_R_ECARD#22,24,28
LANWAKE_R_ICH_WAKE#22,24,28
C C
WL_WAKE_R_ICH_WAKE#22,24,28
+3VALW
R1108 10K_0402_5% R1110 8.2K_0402_5% R1111 1K_0402_5% R1113 10K_0402_5% R1114 10K_0402_5% R1115 10K_0402_5% R1116 10K_0402_5% R1117 10K_0402_5%
R1163 10K_0402_5% R1119 8.2K_0402_5%
ICH_PCIE_WAKE_R_ECARD# ICH_PCIE_WAKE#
LANWAKE_R_ICH_WAKE# WL_WAKE_R_ICH_WAKE# EC_PME#
1 2
CL_RST#1 ICH_LOW_BAT# ICH_PCIE_WAKE# ICH_RI# XDP_DBRESET# ME_EC_CLK1 ME_EC_DATA1 EC_LID_OUT#
CLGPIO5 EC_SMI#
1 2 1 2 1 2 1 2 1 2 1 2
1 2
1 2 1 2
1 2
R1229 0_0402_5%
1 2
R1230 0_0402_5%
@
SB_SPKR26
GLAN
WLAN
B B
Express Card
3G
EC_SWI# USB_OC#1 USB_OC#2 USB_OC#4
A A
USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0
USB_OC#3 USB_OC#5 USB_OC#10 USB_OC#11
RP39
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
RP40
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
RP41
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
5
+3VALW
+3VS
12
12
2.2K_0402_5% R1124
R11232.2K_0402_5%
ICH_SM_DA13,14,15,24
ICH_SM_CLK13,14,15,24
+5VS
Q106 SSM3K7002FU_SC70-3
D
S
13
S
G
2
G
4
1 2 1 2
XDP_DBRESET#4 PM_BMBUSY#7
EC_LID_OUT#29
H_STP_PCI#15 H_STP_CPU#15
PCI_CLKRUN#27,29
SERIRQ29 EC_THERM#29
1 2
@
ISOLATEB22
CLKSATAREQ#15
EC_PME# 18,29
MCH_ICH_SYNC#7
ICH_RSVD19
GLAN_RXN22 GLAN_RXP22
GLAN_TXN22 GLAN_TXP22
PCIE_RXN324
PCIE_RXP324 PCIE_TXN324 PCIE_TXP324
PCIE_RXN428
PCIE_RXP428 PCIE_TXN428 PCIE_TXP428
PCIE_RXN524
PCIE_RXP524 PCIE_TXN524 PCIE_TXP524
SPI_CS1#_R18
ICH_SMBDATA
D
ICH_SMBCLK
13
Q107
2
SSM3K7002FU_SC70-3
4
T125PAD
1 2
R1099 0_0402_5% T128PAD
OCP#4
EC_SMI#29 EC_SCI#29
T130PAD
T132PAD
T133PAD T134PAD T135PAD
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
ICH_SMBDATA 24,28 ICH_SMBCLK 24,28
ICH_SMBCLK ICH_SMBDATA CL_RST#1 ME_EC_CLK1 ME_EC_DATA1
ICH_RI# SUS_STAT#
XDP_DBRESET# PM_BMBUSY# EC_LID_OUT# H_STP_PCI#
R_STP_CPU# PCI_CLKRUN# ICH_PCIE_WAKE#
SERIRQ EC_THERM#
VRMPWRGD
OCP# ISOLATEB
EC_SMI# EC_SCI#
CLKSATAREQ#
GPIO49 CLGPIO5
SB_SPKR MCH_ICH_SYNC# ICH_RSVD
USB_OC#031 USB_OC#131 USB_OC#231 USB_OC#331
EC_SWI#29
G16 A13 E17 C17 B18
F19
G19
A17 A14
E19
E20
AJ23
D21 A20
AG19 AH21 AG21
A21 C12 C21
AE18
AF8
AJ22
D19
AE19 AG22 AF21 AH24
AJ24
B21
AH20
AJ20 AJ21
C12210.1U_0402_16V7K~N
12
C12220.1U_0402_16V7K~N
12
C12230.1U_0402_16V7K~N
12
C12240.1U_0402_16V7K~N
12
C1225
12
C1226
12
C1228
12
C1227
12
12
Within 500 mils
R1125
22.6_0402_1%
3
U56C
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
RI#
R4
SUS_STAT#/LPCPD# SYS_RESET#
M6
PMSYNC#/GPIO0 SMBALERT#/GPIO11 STP_PCI#
STP_CPU#
L4
CLKRUN# WAKE#
M5
SERIRQ THRM#
VRMPWRGD TP11 GPIO1
GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17
K1
GPIO18 GPIO20 SCLOCK/GPIO22
A9
GPIO27 GPIO28
L1
SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49
A8
GPIO57/CLGPIO5
M7
SPKR MCH_SYNC# TP3 TP8 TP9 TP10
ICH9M REV 1.0
GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C
PCIE_RXN3 PCIE_RXP3 PCIE_C_TXN3 PCIE_C_TXP3
PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4
PCIE_RXN5 PCIE_RXP5 PCIE_C_TXN5 PCIE_C_TXP5
SPI_CS1#_R
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 EC_SWI# USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11
USBRBIAS
U56D
N29
PERN1
N28
PERP1
P27
PETN1
P26
PETP1
L29
PERN2
L28
PERP2
M27
PETN2
M26
PETP2
J29
PERN3
J28
PERP3
K27
PETN3
K26
PETP3
G29
PERN4
G28
PERP4
H27
PETN4
H26
PETP4
E29
PERN5
E28
PERP5
F27
PETN5
F26
PETP5
C29
PERN6/GLAN_RXN
C28
PERP6/GLAN_RXP
D27
PETN6/GLAN_TXN
D26
PETP6/GLAN_TXP
D23
SPI_CLK
D24
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
D25
SPI_MOSI
E23
SPI_MISO
N4
OC0#/GPIO59
N5
OC1#/GPIO40
N6
OC2#/GPIO41
P6
OC3#/GPIO42
M1
OC4#/GPIO43
N2
OC5#/GPIO29
M4
OC6#/GPIO30
M3
OC7#/GPIO31
N3
OC8#/GPIO44
N1
OC9#/GPIO45
P5
OC10#/GPIO46
P3
OC11#/GPIO47
AG2
USBRBIAS
AG1
USBRBIAS#
ICH9M REV 1.0
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
SATA
GPIO
SMBSYS GPIO
Clocks
Power MGTController Link
GPIO
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
CLK14 CLK48
SUSCLK
SLP_S3# SLP_S4# SLP_S5#
S4_STATE#/GPIO26
PWROK
DPRSLPVR/GPIO16
BATLOW# PWRBTN# LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0 CL_CLK1
CL_DATA0 CL_DATA1
CL_VREF0 CL_VREF1
CL_RST0# CL_RST1#
MEM_LED/GPIO24
WOL_EN/GPIO9
MISC
DMI0RXN DMI0RXP DMI0TXN
DMI0TXP
DMI1RXN DMI1RXP DMI1TXN
DMI1TXP
DMI2RXN DMI2RXP DMI2TXN
DMI2TXP
DMI3RXN DMI3RXP DMI3TXN
DMI3TXP
DMI_CLKN
PCI-Express
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N
SPI
USBP5P USBP6N
USB
USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P
2006/02/13 2006/03/10
GPIO21
AH23
GPIO19
AF19
GPIO36
AE21
GPIO37
AD20
CLK_14M_ICH
H1
CLK_48M_ICH
AF3
ICH_SUSCLK
P1
SLP_S3#
C16
SLP_S4#
E16
SLP_S5#
G17 C10
ICH_PWROK
G20 M2
1 2
ICH_LOW_BAT#
B13
PWRBTN_OUT#
R3 D20
1 2
R1100 0_0402_5%
R_EC_RSMRST#GPIO49
D22
CK_PWRGD_R
R5
M_PWROK
R6 B16
CL_CLK0
F24 B19
CL_DATA0
F22 C19
CL_VREF0_ICH
C25 A19
CL_RST#
F21 D18
A16 C18 C11 C20
DMI_RXN0
V27
DMI_RXP0
V26
DMI_TXN0
U29
DMI_TXP0
U28
DMI_RXN1
Y27
DMI_RXP1
Y26
DMI_TXN1
W29
DMI_TXP1
W28
DMI_RXN2
AB27
DMI_RXP2
AB26
DMI_TXN2
AA29
DMI_TXP2
AA28
DMI_RXN3
AD27
DMI_RXP3
AD26
DMI_TXN3
AC29
DMI_TXP3
AC28
CLK_PCIE_ICH#
T26
CLK_PCIE_ICH
T25 AF29
DMI_IRCOMP
AF28
USB20_N0
AC5
USB20_P0
AC4
USB20_N1
AD3
USB20_P1
AD2
USB20_N2
AC1
USB20_P2
AC2
USB20_N3
AA5
USB20_P3
AA4
USB20_N4
AB2
USB20_P4
AB3
USB20_N5
AA1
USB20_P5
AA2
USB20_N6
W5
USB20_P6
W4
USB20_N7
Y3
USB20_P7
Y2
USB20_N8
W1
USB20_P8
W2
USB20_N9
V2
USB20_P9
V3
USB20_N10
U5
USB20_P10
U4 U1 U2
R10980_0402_5%
+3VALW
R1120 24.9_0402_1%
Deciphered Date
1 2
R1089 8.2K_0402_5%
CLK_14M_ICH 15 CLK_48M_ICH 15
T126 PAD
SLP_S3# 29 SLP_S4# 29 SLP_S5# 29
T127 PAD
DPRSLPVR 7,43
PBTN_OUT# 29
R1105 0_0402_5%
1 2
T129 PAD
CL_CLK0 7
CL_DATA0 7
CL_RST# 7
1 2
R1118 10K_0402_5%
DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7
DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7
DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7
DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7
CLK_PCIE_ICH# 15 CLK_PCIE_ICH 15
1 2
USB20_N0 31 USB20_P0 31 USB20_N1 31 USB20_P1 31 USB20_N2 31 USB20_P2 31 USB20_N3 24 USB20_P3 24 USB20_N4 31 USB20_P4 31 USB20_N5 31 USB20_P5 31 USB20_N6 24 USB20_P6 24 USB20_N7 28 USB20_P7 28 USB20_N8 31 USB20_P8 31 USB20_N9 31 USB20_P9 31 USB20_N10 USB20_P10
2
R695 100_0402_5%
1 2
@
USB0 USB1 Camera 3G/TV
BlueTooth FingerPrinter WLAN Express Card USB2 USB3 Mini Card2
2
+3VS
M_PWROK
ICH_PWROK 7,29
1 2
R1097 10K_0402_5%@
R_EC_RSMRST#
CK_PWRGD 15
M_PWROK 7
D54
@
2 1
RB411DT146 SOT23
EC_RSMRST#29
Within 500 mils
+1.5VS
1
Place closely pin H1Place closely pin AF3
CLK_14M_ICHCLK_48M_ICH
12
@
R1091 10_0402_5%
@
1
C1217
4.7P_0402_50V8C
2
R1104 10K_0402_5%
1 2
0.1U_0402_16V4Z
1
C1219
2
ACIN 29,37,38
1 2
12
R1107 453_0402_1%
NA lead free
12
@
R1092 10_0402_5%
@
1
C1218
4.7P_0402_50V8C
2
R1106
3.24K_0402_1%
+3VS
RSMRST circuit
R1103 0_0402_5%
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
ICH9(3/4)_DMI,USB,GPIO,PCIE
LA-4841P
R656
@
0_0402_5%
1 2
R_EC_RSMRST#
1
of
20 45Monday, December 15, 2008
POK 39
1.0
5
+RTCVCC
1
C1229
0ohm Change to BEAD
L96
1 2
+1.5VS
R1127
R1128
+1.5VS
1
2
+5VS +3VS
10UH_LB2012T100MR_20%_0805~D
+1.5VS
BLM21PG600SN1D_0805~D
12
21
D45 CH751H-40PT_SOD323-2
ICH_V5REF_RUN
1
C1241 1U_0603_10V6K~D
2
+3VALW+5VALW
12
21
D46
CH751H-40PT_SOD323-2
ICH_V5REF_SUS
1
C1306 1U_0603_10V6K~D
2
L99
1 2
1 2
L100 1UH_20%_0805~D
5
D D
100_0402_5%~D
100_0402_5%~D
C C
B B
+LAN_IO
C1268
A A
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
40 mils
1
+
2
C1234
220U_D2_4VM
22U_0805_6.3V6M~D
20 mils
20 mils
1
C1255
2 T143
1U_0603_10V4Z
1 2
R1129 0_0603_5%
1
2
10U_0805_10V4Z
20 mils
1U_0603_10V4Z~D
www.sp860.com QQ:453100829
1
1
2
2
0.1U_0402_16V4Z
22U_0805_6.3V6M~D
1
C1236
2
2.2U_0603_6.3V4Z
C1231
1
C1237
2
C1230
C1235
0.1U Change to 1U
+1.5VS
C1254
C1269
1
2
10U_0805_10V4Z
+1.5VS
0.1U_0402_16V4Z
+1.5VS
0.1U_0402_16V4Z
C1267
0.1U_0402_16V4Z~D
2.2U_0603_6.3V4Z
1U_0603_10V4Z
+1.5VS
1U_0603_10V4Z
1 2
1
C1270
2
C1256
C1258
C1262
C1263
G3: 6uA
ICH_V5REF_RUN ICH_V5REF_SUS
646mA
1
2
1342mA
1
2
1
2
1
2
11mA
1
11mA
2
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
19/78/78mA
+1.5VS
1
C1271
2
4.7U_0603_6.3V6M~D
47mA
+3VS
2mA 2mA
23mA 80mA
1mA
AE1
AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29
G25
M24 M25
W24 W25
AJ19
AC16 AD15 AD16 AE15 AF15 AG15 AH15
AJ15
AC11 AD11 AE11 AF11 AG10 AG11 AH10
AJ10
AC9
AC18 AC19
AC21
G10
AC12 AC13 AC14
AA7 AB6 AB7 AC6 AC7
A23
A6
F25 H24
H25 J24 J25 K24 K25 L23 L24 L25
N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23
K23 Y24 Y25
G9
AJ5
A10 A11
A12 B12
A27 D28
D29 E26 E27
A26
4
U56F
VCCRTC V5REF V5REF_SUS VCC1_5_B[1]
VCC1_5_B[2] VCC1_5_B[3] VCC1_5_B[4] VCC1_5_B[5] VCC1_5_B[6] VCC1_5_B[7] VCC1_5_B[8] VCC1_5_B[9] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49]
VCCSATAPLL VCC1_5_A[1]
VCC1_5_A[2] VCC1_5_A[3] VCC1_5_A[4] VCC1_5_A[5] VCC1_5_A[6] VCC1_5_A[7] VCC1_5_A[8]
VCC1_5_A[9] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]
VCC1_5_A[17] VCC1_5_A[18]
VCC1_5_A[19] VCC1_5_A[20] VCC1_5_A[21]
VCC1_5_A[22] VCC1_5_A[23]
VCC1_5_A[24] VCC1_5_A[25]
VCCUSBPLL VCC1_5_A[26]
VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]
VCCLAN1_05[1] VCCLAN1_05[2]
VCCLAN3_3[1] VCCLAN3_3[2]
VCCGLANPLL VCCGLAN1_5[1]
VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4]
VCCGLAN3_3
ICH9M REV 1.0
4
CORE
VCCA3GP ATXARX USB CORE
VCCP_CORE
PCI
VCCSUS1_05[1] VCCSUS1_05[2]
VCCSUS1_5[1] VCCSUS1_5[2]
VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3]
VCCPSUSVCCPUSB
VCCSUS3_3[4]
VCCSUS3_3[5] VCCSUS3_3[6]
VCCSUS3_3[7] VCCSUS3_3[8]
VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]
GLAN POWER
VCC1_05[1] VCC1_05[2] VCC1_05[3] VCC1_05[4] VCC1_05[5] VCC1_05[6] VCC1_05[7] VCC1_05[8]
VCC1_05[9] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]
VCCDMIPLL VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1] V_CPU_IO[2]
VCC3_3[1] VCC3_3[2] VCC3_3[7] VCC3_3[3]
VCC3_3[4] VCC3_3[5] VCC3_3[6]
VCC3_3[8]
VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]
VCCHDA
VCCSUSHDA
VCCCL1_05
VCCCL1_5
VCCCL3_3[1] VCCCL3_3[2]
+VCCP
1634mA
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
R29
23mA
W23 Y23
48mA
AB23 AC23
2mA
AG29 AJ6
0.1U_0402_16V4Z
AC10 AD19
AF20 AG24 AC20
308mA
B9 F9 G3 G6 J2 J7 K7
AJ4
11mA
AJ3
11mA
AC8 F17
VCCSUS1_5_ICH_1
AD8
VCCSUS1_5_ICH_2
F18
A18 D16 D17 E22
AF1
212mA
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
VCCCL1_05_ICH
G22 G23
19/73/73mA
A24
+LAN_IO
B24
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V4Z
1
C1232
2
0.01U_0402_16V7K
1
2
+3VS
C1248
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
T140 T141
T142
0.1U_0402_16V4Z~D
1
C1259
2
1
@
C1265 1U_0603_10V4Z
2
3
0.1U_0402_16V4Z
1
C1233
2
L97
BLM18PG181SN1_0603~D
1 2
1
1
2
0.1U_0402_16V4Z
+3VS
C1247
C1249
1
2
+3VALW
+3VALW
1
2
1
2
C1239
C1238
22U_0805_6.3VAM
1
2
C1250
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
C1253
2
0.022U_0402_16V7K~D
C1260
@
C1266 0.1U_0402_16V4Z~D
10U_0805_10V4Z
2
5ohm@100MHz
1 2
L98 BLM18PG181SN1_0603~D
C1240
0.1U_0402_16V4Z
1
+3VS
C1245
2
+VCCP
+VCCP
4.7U_0603_6.3V6M C1242
+3VS
1
C1246
2
1
2
Add 0.1uF
+3VS
1
C1252
+3VALW
2
1
C1257
0.1U_0402_16V4Z
2
0.022U_0402_16V7K~D
1
C1261
2
T144
1
C1264
0.1U_0402_16V4Z
2
2006/02/13 2006/03/10
Deciphered Date
0.1U_0402_16V4Z C1243
1
2
(DMI)
+1.5VS
2
0.1U_0402_16V4Z C1244
1
2
Title
Size Document Number Rev
Custom
2
Date: Sheet
U56E
AA26
VSS[1]
AA27
VSS[2]
AA3
VSS[3]
AA6
VSS[4]
AB1
VSS[5]
AA23
VSS[6]
AB28
VSS[7]
AB29
VSS[8]
AB4
VSS[9]
AB5
VSS[10]
AC17
VSS[11]
AC26
VSS[12]
AC27
VSS[13]
AC3
VSS[14]
AD1
VSS[15]
AD10
VSS[16]
AD12
VSS[17]
AD13
VSS[18]
AD14
VSS[19]
AD17
VSS[20]
AD18
VSS[21]
AD21
VSS[22]
AD28
VSS[23]
AD29
VSS[24]
AD4
VSS[25]
AD5
VSS[26]
AD6
VSS[27]
AD7
VSS[28]
AD9
VSS[29]
AE12
VSS[30]
AE13
VSS[31]
AE14
VSS[32]
AE16
VSS[33]
AE17
VSS[34]
AE2
VSS[35]
AE20
VSS[36]
AE24
VSS[37]
AE3
VSS[38]
AE4
VSS[39]
AE6
VSS[40]
AE9
VSS[41]
AF13
VSS[42]
AF16
VSS[43]
AF18
VSS[44]
AF22
VSS[45]
AH26
VSS[46]
AF26
VSS[47]
AF27
VSS[48]
AF5
VSS[49]
AF7
VSS[50]
AF9
VSS[51]
AG13
VSS[52]
AG16
VSS[53]
AG18
VSS[54]
AG20
VSS[55]
AG23
VSS[56]
AG3
VSS[57]
AG6
VSS[58]
AG9
VSS[59]
AH12
VSS[60]
AH14
VSS[61]
AH17
VSS[62]
AH19
VSS[63]
AH2
VSS[64]
AH22
VSS[65]
AH25
VSS[66]
AH28
VSS[67]
AH5
VSS[68]
AH8
VSS[69]
AJ12
VSS[70]
AJ14
VSS[71]
AJ17
VSS[72]
AJ8
VSS[73]
B11
VSS[74]
B14
VSS[75]
B17
VSS[76]
B2
VSS[77]
B20
VSS[78]
B23
VSS[79]
B5
VSS[80]
B8
VSS[81]
C26
VSS[82]
C27
VSS[83]
E11
VSS[84]
E14
VSS[85]
E18
VSS[86]
E2
VSS[87]
E21
VSS[88]
E24
VSS[89]
E5
VSS[90]
E8
VSS[91]
F16
VSS[92]
F28
VSS[93]
F29
VSS[94]
G12
VSS[95]
G14
VSS[96]
G18
VSS[97]
G21
VSS[98]
G24
VSS[99]
G26
VSS[100]
G27
VSS[101]
G8
VSS[102]
H2
VSS[103]
H23
VSS[104]
H28
VSS[105]
H29
VSS[106]
ICH9M REV 1.0
Compal Electronics, Inc.
ICH9(4/4)_POWER&GND
LA-4841P
1
VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]
VSS_NCTF[1] VSS_NCTF[2] VSS_NCTF[3] VSS_NCTF[4] VSS_NCTF[5] VSS_NCTF[6] VSS_NCTF[7] VSS_NCTF[8]
VSS_NCTF[9] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
1
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
21 45Monday, December 15, 2008
1.0
of
5
+3VALW
1
C1431
1U_0603_10V6K
B+_BIAS
D D
SSM3K7002FU_SC70-3
Q27
+LAN_VDD
60mil
1
C C
B B
A A
1
C412
C1437
2
2
22U_1206_6.3V6M
0.1U_0402_10V7K~N
L92, C788, C778 close to U28(Pin 1) <200mil
C409 0.01U_0402_16V7K
C1415 0.01U_0402_16V7K
C1442 0.01U_0402_16V7K
C419 0.01U_0402_16V7K
2
R1200 470K_0402_5%
1 2
EN_WOL
13
D
2
G
S
L23
1 2
4.7UH_1098AS-4R7M_1.3A_20%
ISOLATEB20
1 2
1 2
1 2
1 2
5
Q108
D
6 2
1
G
EN_WOL# 29
+3VS
12
R327 1K_0402_5%
LANWAKE_R_ICH_WAKE#20,24,28
R1205 15K_0402_5%
1 2
1 2
2
25MHZ_20P_1BX25000CK1A
C422
1
27P_0402_50V8J
FBMA-L11-322513-201LMA40T_1210
S
+3VALW_Q
45
SI3456BDV-T1-E3_TSOP6
3
R1201 1.5M_0402_5%@
12
GLAN_RXP20
GLAN_RXN20 GLAN_TXP20 GLAN_TXN20
GLAN_REQ#915
CLK_PCIE_LAN15
CLK_PCIE_LAN#15
PLT_RST#7,18,24,28,29,33
+LAN_VDD_L
Y6
V_DAC LAN_MDIN3 LAN_MDIP3 V_DAC LAN_MDIN2 LAN_MDIP2
V_DAC LAN_MDIN1 LAN_MDIP1
V_DAC LAN_MDIN0 LAN_MDIP0
www.sp860.com QQ:453100829
60mil
C423
27P_0402_50V8J
1 2 3 4 5 6 7 8
9 10 11 12
W=60mils
1
1
C1432
C420
@
2
2
22U_1206_6.3V6M
22U_1206_6.3V6M
0.1U_0402_16V7K~N
GLAN_RXP_C
12
C452
0.1U_0402_16V7K~N
GLAN_RXN_C
12
C453
GLAN_TXP GLAN_TXN
GLAN_REQ#9
+LAN_VDD
1 2
+LAN_IO
1 2
R1222 2.49K_0402_1%
R1231 0_0402_5%
1 2
T51
TCT1
MCT1
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
TD2+
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
TCT4
MCT4
TD4+
MX4+
TD4-
MX4-
350uH_GSL5009LF
L22
1 2
2
1
4
+LAN_IO
1.5A
1
C406
2
0.1U_0402_10V7K~N
R1204 0_0402_5%
LANWAKE#LANWAKE_R_ICH_WAKE#
ISOLATEB
LAN_XTAL1 LAN_XTAL2
24
RJ45_TX3-
23
RJ45_TX3+
22 21
RJ45_TX2-
20
RJ45_TX2+
19 18
RJ45_RX1-
17
RJ45_RX1+
16 15
RJ45_TX0-
14
RJ45_TX0+
13
4
1
C394
2
0.1U_0402_10V7K~N
These caps close to U47: Pin 16, 37, 46, 53
U47
29
HSOP
30
HSON
23
HSIP
24
HSIN
33
CLKREQB
26
REFCLK_P
27
REFCLK_N
20
PERSTB
1
SROUT12
5
FB12
62
ENSR
64
RSET
19
LANWAKEB
36
ISOLATEB
60
CKTAL1
61
CKTAL2
65
EXPOSE_PAD
25
EGND
31
EGND
15
NC
17
NC
18
NC
34
NC
35
NC
39
NC
40
NC
41
NC
42
NC
RTL8111C-GR_QFN64_9X9
75_1206_8P4R_5%
1
C1419
2
0.1U_0402_10V7K~N
45 36 27 18
RP42
R1223 0_0402_5%
R7 0_0402_5%
R321 0_0402_5%
R1224 0_0402_5%
EEDO
EEDI/AUX
EESK EECS
LED3 LED2 LED1 LED0
MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3
DVDD12 DVDD12 DVDD12 DVDD12 DVDD12 DVDD12
EVDD12 EVDD12
VDD33 VDD33 VDD33 VDD33
VDDSR
AVDD33 AVDD33
AVDD12 AVDD12 AVDD12 AVDD12
IGPIO
OGPIO
C1441 1000P_1206_2KV7K
1 2
1 2
1 2
1 2
1
C1433
2
0.1U_0402_10V7K~N
45
LAN_EEDI
47 48 44
54 55 56 57
LAN_MDIP0
3
LAN_MDIN0
4
LAN_MDIP1
6
LAN_MDIN1
7
LAN_MDIP2
9
LAN_MDIN2
10
LAN_MDIP3
12
LAN_MDIN3
13
21 32 38 43 49 52
22 28
16 37 46 53
63 2
59 8
11 14 58
50 51
12
+LAN_VDDSR LAN_AVDD33
LAN_CABDT
1
C1447
2
0.1U_0402_10V7K~N
3.6K_0402_5%
TP58
@
R1199
1 2
TP59
@
TP60
@
LAN_LED3 LAN_LED2 LAN_LED1 LAN_LED0
LAN_DVDD12
30mil
+LAN_IO
@
1 2
C389 0.1U_0402_16V7K~N C390 0.1U_0402_16V7K~N
W=40mils
+LAN_VDDSR
LAN_AVDD12
LAN_DVDD12
LAN_CABDT
R1206
+3VS
10K_0402_5%
LAN_LED2
CH751H-40PT_SOD323-2
LAN_LED3
CH751H-40PT_SOD323-2
LAN_LED1 LED1_LED3
CH751H-40PT_SOD323-2
LAN_LED3
CH751H-40PT_SOD323-2
3
+LAN_VDD
1 2
R1221
+LAN_IO
FBML10160808121LMT_0603
1 2 1 2
C1440 0.1U_0402_16V7K~N C1426 0.1U_0402_16V7K~N
D2
D4
D5
D6
3
L101
12
LAN_AVDD12
FBML10160808121LMT_0603
1 2 1 2
21
21
21
21
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LED2_LED3
Issued Date
+LAN_IO
12
+LAN_IO
12
L24
12
R358 10K_0402_5%
R359 10K_0402_5%
+LAN_IO
LED2_LED3 LED1_LED3 LINK_100_1000#
2007/1/15 2008/1/15
0_0603_5%
R106
1 2
220_0402_5%
R79
1 2
220_0402_5%
Compal Secret Data
1
C14500.1U_0402_10V7K~N
2
+LAN_IO
1 2
220_0402_5%
+LAN_IO
2
LAN_DVDD12
1
C14480.1U_0402_10V7K~N
2
1
1
C3950.1U_0402_10V7K~N
C14340.1U_0402_10V7K~N
2
2
These caps close to U47: Pin 21, 32, 38, 43, 49, 52
+LAN_IO
12
R1203 0_0805_5%
W=40mils
+LAN_VDDSR
1
C421
2
22U_1206_6.3V6M
C792 close to U47(PIN63) , then C783 close to C792
1 2
R2
0_0603_5%
LAN_AVDD12
1
C14250.1U_0402_10V7K~N
2
+LAN_VDD
These caps close to U47: Pin 8, 11, 14, 58
LAN_ACTIVITY#LAN_LED0
R105
RJ45_TX3­RJ45_TX3+ RJ45_RX1­RJ45_TX2­RJ45_TX2+ RJ45_RX1+ RJ45_TX0­RJ45_TX0+
LINK_100_1000#
Deciphered Date
2
LAN_DVDD12
1
C14200.1U_0402_10V7K~N
2
1
2
LAN_AVDD12
12 11
8 7 6 5 4 3 2 1
10
9
Compal Electronics, Inc.
1
C14490.1U_0402_10V7K~N
2
C1436
0.1U_0402_10V7K~N
1
1
C14390.1U_0402_10V7K~N
C14380.1U_0402_10V7K~N
2
2
JLAN1
Amber LED+ Amber LED­PR4­PR4+ PR2­PR3­PR3+ PR2+ PR1­PR1+ Green LED­Green LED+
TYCO_3-440470-4
CONN@
1
1
C14350.1U_0402_10V7K~N
C1421
2
2
0.1U_0402_10V7K~N
1
C3960.1U_0402_10V7K~N
2
16
SHLD2
15
SHLD1
14
SHLD2
13
SHLD1
1
C1422
2
Title
Size Document Number Rev
Custom
Date: Sheet
1
C1423
2
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
Broadcom BCM5787M
LA-4841P
1
1
22 45Monday, December 15, 2008
1.0
of
5
4
3
2
1
SATA HDD CONN
C574
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
R304 0_0402_5%@ R305 0_0402_5%@
1
2
1 2 1 2
1
C296
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C377
PSATA_ITX_DRX_P019
PSATA_ITX_DRX_N019 PSATA_IRX_DTX_N0_C19 PSATA_IRX_DTX_P0_C19
D D
+5VS_HD
10U_0805_10V4Z~N
1
+
C C
C575
150U_B2_6.3VM_R45M
2
www.sp860.com QQ:453100829
R308 0_0402_5%@
R314 0_0402_5%@
IRX_DTX_N0_C IRX_DTX_P0_C
+5VS_HD
1
2
1 2 1 2
C393
3900P_0402_50V7K
12
3900P_0402_50V7K
12
C392
1
C376
2
1000P_0402_50V7K~N
ITX_DRX_P0 ITX_DRX_N0
1 2 3 4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
+5VS +5VS_HD
JSATA1
GND A+ A­GND B­B+ GND
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
SUYIN_127043FB022S338ZR_RV
CONN@
L1
1 2
FBMA-L11-160808-301LMA20T_1206~D
+5VS
10U_0805_10V4Z
1
C498
2
1U_0603_10V4Z
1
C506
2
0.1U_0402_16V4Z
1
C503
2
1
C499
2
1000P_0402_50V7K~N
SATA ODD CONN
ODD_ITX_DRX_P019 ODD_ITX_DRX_N019
ODD_IRX_DTX_N0_C19 ODD_IRX_DTX_P0_C19
close JSATA2
ODD_ITX_DRX_P0 ODD_ITX_DRX_N0
1 2
C326 0.01U_0402_50V7K
1 2
C327 0.01U_0402_50V7K
+5VS
ODD_IRX_DTX_N0 ODD_IRX_DTX_P0
JSATA2
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
DP
9
5V
10
5V MD GND GND
GND GND
11 12 13
SUYIN_127382FR013S52_NR
14 15
Close to ODD Conn
Close to SATA HDD
+1.8VS
Output Swing Control
SEL2_ [A:B]
0
**
1
B B
A A
PSATA_ITX_DRX_P019 PSATA_ITX_DRX_N019
PSATA_IRX_DTX_P0_C19 PSATA_IRX_DTX_N0_C19
+1.8VS
+1.8VS
Swing
1x
1.2x
PSATA_ITX_DRX_P0 PSATA_ITX_DRX_N0 ITX_DRX_P0
C1251 0.01U_0402_16V7K
1 2
C1272
1 2
0.01U_0402_16V7K
R290 0_0402_5%
1 2
R292 0_0402_5%
1 2
R293 0_0402_5%@
1 2
R294 0_0402_5%@
1 2
R295 0_0402_5%
1 2
R298 0_0402_5%
1 2
R299 0_0402_5%
1 2
R300 0_0402_5%
1 2
R616 5.1K _0402_1%
1 2
R617 5.1K _0402_1%
1 2
R352 470_0402_5%@
1 2
R301 0_0402_5%
1 2
R303 0_0402_5%
1 2
Output De-emphasis Adjustment
SEL3_ [A:B]
0 1
De-emphasis
0dB
-3.5dB
U23
2
AI+
3
AI-
7
BO+
8
BO-
34
SEL0_A
13
SEL0_B
33
SEL1_A
14
SEL1_B
32
SEL2_A
15
SEL2_B
31
SEL3_A
16
SEL3_B
30
EN_A
29
EN_B
19
IREF
11
CLKIN+
12
CLKIN-
PI2EQX3201BZFE_TQFN36_6X5~D
VDD VDD VDD VDD VDD
AVDD
AO+
OUT+
OUT­SD_A
SD_B
GND GND GND GND
AGND
PAD
AO-
BI­BI+
1
1
C691
2
1 6 10 23 28 5
27 26
21 22
17 18
36 35
25 20 9 4 24
37
IRX_DTX_N0_C IRX_DTX_P0_C
R285 0_0402_5%@
1 2
R286 0_0402_5%@
1 2
R288 0_0402_5%@
1 2
R289 0_0402_5%@
1 2
1
1
C286
C287
0.1U_0402_16V4Z~N
R1074
2
470_0402_5%~D
C288
2
0.1U_0402_16V4Z~N
C1053 4700P_0402_25V7K~D
12
C1052 4700P_0402_25V7K~D
12
2
10U_1206_16V4Z
12
SEL0_ [A:B] SEL1_ [A:B]
00 01
*
1 11
1
1
C290
C289
2
2
0.1U_0402_16V4Z~N
0.1U_0402_16V4Z~N
0.1U_0402_16V4Z~N
ITX_DRX_N0
Equalizer Selection
Compliance Channel no equalization [0:2.5dB] @ 1.6 GHz [2.5:4.5dB] @ 1.6 GHz
0
[4.5:6.5dB] @ 1.6 GHz
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
HDD/CDROM
LA-4841P
1
23 45Monday, December 15, 2008
1.0
of
A
www.sp860.com QQ:453100829
Mini-Express Card for 3G Or TV Tuner
B
C
D
E
+3VS +3VALW
1 1
WL_WAKE_R_ICH_WAKE#20,22,28
2 2
1
C193
4.7U_0805_10V4Z
2
+3VS
CLK_PCIE_Rob#15 CLK_PCIE_Rob15
2005/09/27 modified. Base on OPTION GTM351E Datasheet Rev0.1
Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA
1
C180
0.1U_0402_16V4Z
2
1 2
R1232
@
1 2
R661 10K_0402_5%
CLK_PCIE_Rob# CLK_PCIE_Rob
PLT_RST#
PCIE_RXN520 PCIE_RXP520
PCIE_TXN520 PCIE_TXP520
0_0402_5%
3G_CLKREQ#
R284 0_0402_5%
1 2
CLK_DB_R
WL_WAKE#WL_WAKE_R_ICH_WAKE#
+1.5VS
1
C195
4.7U_0805_10V4Z
2
JMINI3
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
FOX_AS0B226-S56N-7F
CONN@
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1
C194
0.1U_0402_16V4Z
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
(WWAN_LED#)
44 46 48 50 52
54
1
C192
0.1U_0402_16V4Z
2
LPC_FRAME_R# LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R
MINI2_OFF#
ICH_SMBCLK ICH_SMBDATA
10K_0402_5%
MINI2_OFF#
2N7002_SOT23
PLT_RST# 7,18,22,28,29,33
+3VALW
+3VS
12
R737
13
D
Q52
@
S
1
C188
0.1U_0402_16V4Z
2
+3VS +1.5VS
1 2
R280 0_0402_5% @
1 2
R282 0_0402_5%@
1 2
R281 0_0402_5%@
1 2
R283 0_0402_5%@
1 2
R287 0_0402_5% @
ICH_SMBCLK 20,28
ICH_SMBDATA 20,28
USB20_N3 20 USB20_P3 20
@
R388 0_0402_5%
1 2
3G_OFF#
2
G
LPC_FRAME#
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
LPC_FRAME# 19,29
LPC_AD[0..3] 19,29
3G_OFF# 29
Mini-Express Card---WLAN
3 3
ICH_PCIE_WAKE#
WLAN_ACTIVE31
BT_ACTIVE31
WLAN_REQ#415
CLK_PCIE_MCARD#15
CLK_PCIE_MCARD15
CLK_DEBUG_PORT15
PCIE_RXN320 PCIE_RXP320
PCIE_TXN320
PCIE_TXP320
+3V_WLAN
4 4
ICH_PCIE_WAKE# WLAN_ACTIVE MINI_PIN3 BT_ACTIVE MINI_PIN4
R380 0_0402_5%@
1 2
R381 0_0402_5%@
1 2
WLAN_REQ#4
CLK_DEBUG_PORT CLK_DB_R PCIE_RXN3 PCIE_C_RXN3
PCIE_RXP3 PCIE_C_RXP3
PCIE_TXN3 PCIE_TXP3
R384 0_0402_5%
1 2
R403 0_0402_5%
1 2
R404 0_0402_5%
1 2
R406 0_0402_5%@
A
1 2
PLT_RST#
JMINI2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
FOX_AS0B226-S56N-7F
CONN@
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
+3V_WLAN
1 2
+1.5VS
2
2
4
4
6
6
8
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
54
LPC_FRAME#
LED_WLAN#
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
1 2 1 2
R412 0_0402_5%
LPC_FRAME# 19,29
MINI_RF_OFF#
R3730_0402_5% R3430_0402_5%
USB20_N6 USB20_P6
12
R86100K_0402_5%
LED_WLAN# 32
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS
MINI_RF_OFF#
LPC_AD[0..3] 19,29
MINI_RF_OFF#
PLT_RST# 7,18,22,28,29,33
+3V_WLAN +1.5VS
ICH_SM_CLK 13,14,15,20
ICH_SM_DA 13,14,15,20
USB20_N6 20 USB20_P6 20
+5VS
+1.5VS
+3V_WLAN
Issued Date
C
+3VS
12
R1233
@
10K_0402_5%
R389 0_0402_5%
1 2
13
D
Q109
@
2N7002_SOT23
2
G
S
2007/1/15 2008/1/15
0.01U_0402_16V7K~N
1
C500
2
WL_OFF#
WL_OFF# 29
Deciphered Date
C489
0.1U_0402_16V4Z~N
0.01U_0402_16V7K~N
D
1
2
1
C485
2
+3V_WLAN
4.7U_0805_10V4Z~N
1
C456
2
+1.5VS
0.01U_0402_16V7K~N
1
C488
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Mini-Card/LED
LA-4841P
of
24 45Monday, December 15, 2008
E
1.0
5
4
3
2
+3VS
1
www.sp860.com QQ:453100829
R313
100K_0402_5%
@
HD Audio Codec
20mil
D D
L41
+VDDA
MIC2_L26 MIC2_R26
C C
ACZ_RST#19
ACZ_SYNC19
ACZ_SDOUT19
C686
@
10P_0402_50V8J
1 2
FBM-L11-160808-800LMT_0603
C140 2.2U_0603_6.3V6K C141 2.2U_0603_6.3V6K
MONO_IN26
2
1
2
2
C674
C682
1
1
@
@
10P_0402_50V8J
10P_0402_50V8J
10U_1206_16V4Z
MIC_JD
EAPD26
0.1U_0402_16V4Z
1
C669
C687
2
+MIC2_VREFO
MIC-L
1 2
C689 2.2U_0603_10V6K
MIC-R C_MIC2_R
1 2
C690 2.2U_0603_10V6K
MONO_IN
ACZ_RST# ACZ_SYNC ACZ_SDOUT
1 2
R614 20K_0402_1%
HP_JD
R611 39.2K _0402_1%@
CPLS HP-JD
R615 5.1K _0402_1%
R572
10mil
1
2
0.1U_0402_16V4Z
MIC2_C_L MIC2_C_R
C_MIC1_L
R_MIC_JD R_HP_JD
12
12 12
0_0402_5%
GND
40mil
1
C685
2
+AVDD_AC97
U22
14
LINE2-L(PORT E)
15
LINE2-R(PORT E)
16
MIC2_L(PORT F)
17
MIC2_R(PORT F)
23
LINE1_L(PORT C)
24
LINE1_R(PORT C)
18
LINE1-VREF
20
LINE2-VREF
19
MIC2-VREF
21
MIC1_L(PORT B)
22
MIC1_R(PORT B)
12
PCBEEP
11
RESET#
10
SYNC
5
SDATA_OUT
2
GPIO0/DMIC1/2
3
GPIO3/DMIC3/4
13
SENSE A
34
SENSE B
47
EAPD
48
SPDIFO1
4
DVSS1
7
DVSS2
38
AVDD125AVDD2
LOUT2-L(PORT A)
LOUT2-R(PORT A)
HPOUT-R(PORT I)
HPOUT-L(PORT I)
ALC272-GR_LQFP48
1
9
DVDD
DVDD_IO
LINE1_OUT_L LINE1_OUT_R
SPDIFO2
DMIC_CLK1/2
DMIC_CLK3/4
BIT_CLK
SDATA_IN
CBN CBP
MONO_OUT
MIC1_VREFO_L
VREF JDREF CPVEE
AVSS1 AVSS2
0.1U_0402_16V4Z
1
C671
2
LINEL
35
LINER
36 39 41 45 46 43
NC
44 6 8 30 29 37 28 32 33 27
+AC97_VREF
40 31
26 42
GNDA
1
C680
2
0.1U_0402_16V4Z
ACZ_BITCLK_CODEC AC97_SDIN0_CODEC
R613
C142 2.2U_0603_6.3V6K
1 2
10mil
For EMI
0_0603_5%
1 2
R568
1
C666 10U_1206_16V4Z
2
C672 1000P_0402_50V7K~N C677 1000P_0402_50V7K~N
1 2
R610 0_0402_5%
0_0402_5%
1 2
+MIC1_VREFO
C667 1000P_0402_50V7K~N@
C668
@
1000P_0402_50V7K~N
+AC97_VREF=10mil
1
R569
2.2U_0603_6.3V6K
2
+3VS
1 2
R593 6.8K_0402_5%
1 2
R589 6.8K_0402_5%
12
R612 10_0402_5%
ADC_ACZ_SDIN0 19
1 2
C673 10P_0402_50V8J
ACZ_BITCLK 19
modify_11/12
+MIC1_VREFO 26
1 2
R546 27.4_0603_1%
1 2
R554 27.4_0603_1%
12
C681 20K_0402_1%
27 ohm
HPRHP_ROUT HPLHP_LOUT
0.1U_0402_16V4Z
AMP_LEFT 26 AMP_RIGHT 26
MIC_JD
MIC-R MIC-L
CPLS HP-JD
PLUG_IN26 HPR HPL
HPR HPL
1
1
2
C1453 10U_0805_10V4Z
2
C1452
modify_11/12
PLUG_IN26
MIC_JD MIC-R MIC-L
PLUG_IN HPR HPL
1 2
PLUG_IN#
+MIC1_VREFO 26
12
10mil 10mil
220P_0402_50V7K
0_0402_5%
R131
@
2.2K_0402_5%
1
C37
220P_0402_50V7K
2
12
12
R92
R130 0_0402_5%
@
C39
100K_0402_5%
@
1 2
PLUG_IN#
13
D
2
G
S
12
R111
2.2K_0402_5%
1
2
10P_0402_50V8J
R302
Q25 SSM3K7002FU_SC70-3
@
C50
2
G
1
2
HP_JD
13
D
Q24 SSM3K7002FU_SC70-3
S
@
1
C51 10P_0402_50V8J
2
JMIC1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
G1
14
G2
ACES_87212-1200
CONN@
12/13 Modified this symbol for pin 13 and 14. Do not re-copy this symbol for other use
B B
26
26
26
26
INTSPK_L2
INTSPK_L1
INTSPK_R2
INTSPK_R1
Place U50 close to U6
1 2
+5VS
C881
A A
4.7U_0805_10V4Z
0.1U_0402_16V7K~N
1 2
10K_0603_1%
C882
R900
R129 0_0603_5%@
U50
1
EN
2
GND
3
VIN
RT9198-4GPBG SOT-23 5P 4.75V
VOUT
5
NC
4
+VDDA
1
2
C883 4.7U_0805_10V4Z~N
1
2
C884 0.1U_0402_16V7K~N
GND
R14
1 2
R115
1 2
R116
1 2
R117
1 2
R118
1 2
GNDA
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
GNDAGND
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
D14 SM05T1G_SOT23-3~D
@
2008/05/07 2009/05/07
1
1
3 2
D18 SM05T1G_SOT23-3~D
@
Deciphered Date
Speaker Connector
INTSPK_L1 INTSPK_L2 INTSPK_R1
3
INTSPK_R2
2
2
1 2 3 4 5 6
JSPK2
1 2 3 4 GND1 GND2
ACES_88231-0400
CONN@
@
INTSPK_R2
C9
100P_0402_25V8K
LA-4841P
@
INTSPK_L2
INTSPK_L1
C16
C15
100P_0402_25V8K
of
1
25 45
@
INTSPK_R1
C8
100P_0402_25V8K
100P_0402_25V8K
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
HD CODEC 92HD81
Monday, December 15, 2008
@
1.0
A
B
C
D
E
15
16
VDD
PVDD1
GND41GND311GND213GND1
20
R537
12
+5VS
0_0402_5%
6
U18
PVDD2
2
GAIN0
3
GAIN1
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
12
NC
10
BYPASS
P3017THF TSSOP 20P
R171
1 2
2.7K_0402_5%
+5VS
R520 10K_0402_5% R512 10K_0402_5%@
1
C654
2
1U_0603_10V4Z
PLUG_IN
1 2 1 2
SPK_R1
SPK_R2
SPK_L1
SPK_L2
PLUG_IN 25
R513 10K_0402_5%
1 2
R573 10K_0402_5%@
1 2
1 2
R505 0_0603_5%
1 2
R504 0_0603_5%
1 2
R502 0_0603_5%
1 2
R503 0_0603_5%
INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2
GAIN0 GAIN1 GAIN
00
0
*
1
0
1
1
INTSPK_R1 25
INTSPK_R2 25
INTSPK_L1 25
INTSPK_L2 25
6dB
10dB
15.6dB
21.6dB1
+MIC2_VREFO
MIC_L1
GND GND
ACES_88231-02001
+MIC2_VREFO
MIC_R1
GND GND
ACES_88231-02001
1
1
2
2
3 4
1
1
2
2
3 4
D10
2 1
RB751V_SOD323
MIC_GND
D12
2 1
RB751V_SOD323
MIC_GND
R128 4.7K_0402_5%
1 2
MIC2_R_L
12
C52
@
100P_0402_50V8J
R132 4.7K_0402_5%
1 2
MIC2_R_R
C54
@
100P_0402_50V8J
L102
1 2
MBK1608121YZF_0603
R1228 0_0603_5%
@
GNDA
L58
1 2
12
R134 0_0402_5%
@
PSOT05C-LF-T7 SOT-23-3
12
L59
0_0603_5%
D53
3 2
1 2
0_0603_5%
220P_0402_50V7K
MIC_L_3
@
C770
1
2
1
MIC_R_3
1
2
C769 220P_0402_50V7K
MIC_GND
R801
12
1K_0402_5%
MIC2_L 25
modify_11/12
R805
12
1K_0402_5%
MIC2_R 25
www.sp860.com QQ:453100829
W=40Mil
1
1
C648
0.1U_0402_16V4Z
4 4
AMP_RIGHT25
AMP_LEFT25
3 3
EC_MUTE#29
Change to 100p from 0.01u for EMI
-1012
Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off
C642
0.47U_0603_10V7K
C638
0.47U_0603_10V7K
C650
0.47U_0603_10V7K
C636
0.47U_0603_10V7K
12
+3VS
12
13
D
2
G
S
1
C624
2
1 2
AMP_R
1 2
1 2
AMP_L
1 2
R50610K_0402_5% @
R170 100K_0402_5%
Q31 SSM3K7002FU_SC70-3
100P_0402_50V8J
C651 10U_0805_10V4Z
2
2
7
17
9
5
19
D28 CH751H-40_SC76
12
1K_0402_5% R507
EAPD25
RIN+
RIN-
LIN+
LIN-
SHUTDOWN
GND
21
2 1
@
2 2
+VDDA
12
R626 10K_0402_5%
C695
1 2
12
1U_0603_10V4Z
R624
C366
EC Beep
1 1
ICH Beep
A
BEEP#29
SB_SPKR20
R156
1 2
47K_0402_5%
R157
1 2
47K_0402_5%
1 2
1U_0603_10V4Z
C367
1 2
1U_0603_10V4Z
R311
1 2
560_0402_5%
R160
1 2
560_0402_5%
10K_0402_5%
B
R310
10K_0402_5%
1
C
Q36
2
B
E
2SC2411K_SC59
3
12
D11 RB751V_SOD323
2 1
C688
1 2
1U_0603_10V4Z
1 2
R623
2.4K_0402_5%
MONO_IN
MONO_IN 25
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
AMP/Audio Jack
LA-4121P
E
of
26 45Monday, December 15, 2008
1.0
5
+1.8V
SUSP36,42
D D
PLACE C1136, C1137, C1138 AS CLOSE AS U44
SUSP
2
G
C C
R514
1 2
100_0402_5%
PCI_CLKRUN#20,29
B B
A A
AP2301GN_SOT23-3
S
R1214
1 2
100K_0402_5%
C679
PLACE C1141, C1142 AS CLOSE AS U44
PCI_AD[0..31]18
+1.8VS_CR
12
R1215 470_0402_5%
13
D
Q21 SSM3K7002FU_SC70-3
S
CLK_PCI_CB15 PCI_DEVSEL#18 PCI_FRAME#18
PCI_GNT0#18
PCI_RST#18
PCI_PIRQG#18
R524 100K_0402_5%
R525 0_0402_5%~D@
+1.8VS_CR
Q34
D
13
4.7U_ 0603_6.3V
0.01U_0402_25V7K~N
G
2
C647
1
2
PCI_CBE#318 PCI_CBE#218 PCI_CBE#118 PCI_CBE#018
PCI_IRDY#18 PCI_TRDY#18 PCI_STOP#18
PCI_PAR18
PCI_REQ0#18
CB_PME#
1 2
LED behave: Idel ---------> low Accress data --> always high
IEEE1394_TPBIAS0
R547
R559
C659
0.1U_0402_10V6K
1
C620
2
12
56.2_0402_1%
12
56.2_0402_1%
12
270P_0402_50V7K
2
1
0.1U_0402_10V6K
1
C632
2
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0
CBS_IDSELPCI_AD21 CLK_PCI_CB PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PAR PCI_REQ0# PCI_GNT0# PCI_RST# PCI_PIRQG# CB_PME#
56.2_0402_1%
12
R555
56.2_0402_1%
12
R1219
5.1K_0402_1%
R571
1 2
IEEE1394_TPAP0 IEEE1394_TPAN0 IEEE1394_TPBP0 IEEE1394_TPBN0
+3VS
C660
C656
www.sp860.com QQ:453100829
4.7U_ 0603_6.3V
0.1U_0402_10V6K
1
C675
2
19 20 21 22 23 24 25 27 29 30 31 32 34 35 36 37 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64
28 38 46 55
45 42 39 40 41 43 44 17 18
11
106
1U_0603_10V4Z
1
2
U44
5
1 3
6
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
C/BE3# C/BE2# C/BE1# C/BE0#
IDSEL PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCI_REQ# PCI_GNT# PCI_RST# INTA# PME# CLKRUN#
MEDIA_LED
15
26
56
PCI_VCC
PCI_VCC
GND
GND
GND
GND
12
16
33
68
66
Layout Note: Place close to OZ129 Chipset.
5
4
7
125
120
102
91
VCC3.3
VCC1.814VCC1.8
VCC1.8
VCC1.8
VCC1.892VCC1.8
OZH24TN
GND
GND
GND
GND
GND
GND
GND
124
123
121
116
115
104
R235 0_0402_5%
1 2
R238 0_0402_5%
1 2
R236 0_0402_5%
1 2
R237 0_0402_5%
1 2
4
122
103
VCC3.3
VCC3.3
VCC3.3
SD_CLK/MS_CLK
MS_D1/XD_D7
MS_BS/XD_D3
MS_D0/XD_D2 MS_D2/XD_D1 MS_D3/XD_D0
AGND
AGND
AGND
82
80
77
R542 5.9K_0402_1%
OZ129XI OZ129XO
IEEE1394_TPBIAS0 IEEE1394_TPAP0 IEEE1394_TPAN0 IEEE1394_TPBP0 IEEE1394_TPBN0
MC_3V# SDCLK_MSCLK SDDATA3 SDDATA2 SDDATA1 SDDATA0 SD_CMD SD_WP SDCD#
MSDATA1
MSBS MSDATA0 MSDATA2 MSDATA3
MSCD#
L16
12
C619
1 2
+3VS_PHY
81
79
73
67
AVCC
AVCC
AVCC
AVCC
78
REF
83
XI
84
XO
76
TPBIAS
75
TPA+
74
TPA-
72
TPB+
71
TPB-
4
MC_3V#
113 111
SD_D3
112
SD_D2
107
SD_D1
108
SD_D0
110
SD_CMD
117
SD_WP
114
SD_CD#
95 93
XD_D6
89
XD_D5
87
XD_D4
88 90 94 96 119
XD_CE#
100
XD_RB#
118
XD_CLE
109
XD_ALE
105
XD_WE#
101
XD_RE#
98
XD_WPO#
99
MS_CD#
97
XD_CD#
85
PHY_TEST0
86
PHY_TEST1
2
NC
8
NC
9
NC
10
NC
13
NC
126
NC
127
NC
128
NC
AGND70AGND
AGND
OZH24TN LQFP 128P_14X14
69
65
0_0603_5%
IEEE1394TPA+/- and IEEE1394TPB+/­Same Wire Length
Layout Note: Shield GND for IEEE1394_TPA and TPB
+3VS
0.1U_0402_10V6K
4.7U_ 0603_6.3V
1
C621
2
3
PLACE C1139, C1140 AS CLOSE AS U44
+3VS
R594 22K_0402_5%
CLK_PCI_CB
10_0402_5%~D
12
R1216
@
4.7P_0402_50V8C
1
C676
@
2
P-TWO_CU8042-A0G1G-P
4 3 2 1
J1394A
3
2
AS CLOSE AS U44
L15
1 2
+3VS
FBM-L11-160808-601LMT_0603
Layout Note: Place close to OZ129 and Shield GND.
C643
12
15P_0402_50V8J
15P_0402_50V8J
MC_3V#
X3
24.576MHz_16P_3XG-24576-43E1
1 2
C635
12
+3VS
G
2
1 3
OZ129XI
OZ129XO
S
U45 AP2301GN_SOT23-3
D
1U 10V Z Y5V 0603
C332
C337
+3VS_CR
1
2
0.1U_0402_10V6K
1
1
C343
2
2
+3VS_PHY
0.1U_0402_10V6K
C345
12
13
D
Q82
SSM3K7002FU_SC70-3
S
4.7U_ 0603_6.3V
R241 470_0402_5%
MC_3V#
2
G
3 in 1 Card Reader
+3VS_CR
6
TPA+
GND
5
TPA-
GND TPB+ TPB-
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/09/01 2008/09/01
SDDATA0 SDDATA1 SDDATA2 SDDATA3
SD_WP SD_CMD SDCD#
MSDATA1
MSCD# MSDATA0 MSBS MSDATA3 MSDATA2
Compal Secret Data
Deciphered Date
2
R199 22_0402_5%
1 2
R200 22_0402_5%
1 2
C323
+3VS_CR
4.7U_ 0603_6.3V
SDCLKSDCLK_MSCLK
MSCLKSDCLK_MSCLK
10P_0402_50V8J
0.1U_0402_10V6K
1
C1444
2
10P_0402_50V8J
J3IN1
6
VDD_SD
9
DAT0_SD
10
DAT1_SD
2
DAT2_SD
3
CD/DAT3_SD
7
CLK_SD
11
WP_SD
4
CMD_SD
1
CD_SD
5
VSS_SD
8
VSS_SD
19
VCC_MS
13
VCC_MS
14
SCLK_MS
16
INS_MS
18
SDIO_MS
20
BS_MS
15
RESERVED_MS
17
RESERVED_MS
21
VSS_MS
12
VSS_MS
22
GND
23
GND
PROCO_MDR019-C0-1202
CONN@
Title
OZ129_Card Reader / 1394
Size Document Number Rev
Custom
LA-4841P
Date: Sheet
1
SDCLK
1
C324
2
MSCLK
1
C325
2
Compal Electronics, Inc.
1
27 45Monday, December 15, 2008
1.0
of
5
4
3
2
1
Express card
D D
C C
MDC Conn.
HDA_SDOUT_MDC19 HDA_SYNC_MDC19
HDA_SDIN119
HDA_RST_MDC#19 HDA_BITCLK_MDC 19
1 2
R49 33_0402_5%
www.sp860.com QQ:453100829
C90
C92
C75
+1.5VS_PEC
1
2
+3VALW_PEC
1
2
+3VS_PEC
1
2
4.7U_0805_10V4Z~N
1
C89
2
ICH_PCIE_WAKE_R_ECARD#20,22,24
4.7U_0805_10V4Z~N
1
C93
2
4.7U_0805_10V4Z~N
1
C73
2
EXPCARD_REQ#1615
USB20_N7 USB20_P7
CLK_PCIE_EXPR15
USB20_N720
USB20_P720
Express Card Power Switch
+1.5VS
12
C91 0.1U_0402_16V4Z~N
CPUSB# EXPR_CPUSB#
+3VS
+3VALW
PLT_RST#
SYSON
SUSP#
12
C74 0.1U_0402_16V4Z~N
12
C85 0.1U_0402_16V4Z~N
PLT_RST#7,18,22,24,29,33
SYSON29,36,41 SUSP#29,33,36,40,41 CLK_PCIE_EXPR#15
+1.5V_CARD Max. 650mA, Average 500mA
+3V_CARD Max. 1300mA, Average 1000mA
JMDC1
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
@
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
GND13GND14GND15GND16GND17GND
U11
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
P2231NL_QFN20
RES0 RES1
3.3V GND3 GND4
IAC_BITCLK
18
+1.5VS_PEC
11
1.5Vout
13
1.5Vout
3.3Vout
3.3Vout
PERST#
2 4 6 8 10 12
OC#
NC
GND
20mil
1
C1429
@
22P_0402_50V8J
2
3 5
15 19 8 16 7
+3VS_PEC
+3VALW_PEC
PERST#
+MDC_VCC
0.1U_0402_16V4Z~N
0.1U_0402_16V4Z~N
0.1U_0402_16V4Z~N
ICH_SMBCLK20,24 ICH_SMBDATA20,24
R37 0_0402_5%
1 2
+3VALW_PEC
+3VS_PEC
PCIE_RXN420 PCIE_RXP420
PCIE_TXN420
PCIE_TXP420
R48 0_0402_5%
1 2
R47 0_0402_5%
1 2
EXPR_CPUSB#
ICH_SMBCLK
+1.5VS_PEC
ICH_SMBDATA
PCIE_PME#_RICH_PCIE_WAKE_R_ECARD# PERST#
EXPCARD_REQ#16 CPUSB# CLK_PCIE_EXPR# CLK_PCIE_EXPR
PCIE_RXN4 PCIE_RXP4
PCIE_TXN4 PCIE_TXP4
USB20_N7_R USB20_P7_R
JEXP1
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
29
GND
30
GND
FOX_1CX41201_26P_LT-S
CONN@
Connector for MDC Rev1.5
B B
ACES_88018-124G
CONN@
+3VALW
W=40mils
1
C749 1U_0603_10V4Z
2
@
+MDC_VCC
C751
0.1U_0402_16V4Z
@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
EXPRESS CARD
LA-4841P
1.0
28 45Monday, December 15, 2008
1
of
C748
0.1U_0402_16V4Z
@
MDC_ON#29
A A
9/29 follow HEL80's
5
1 2
R735 100K_0402_5%
@
4.7U_0805_10V4Z
S
G
2
Q51 SI2301BDS_SOT23
@
D
1 3
1
C750
2
@
4
10K_0402_5%
CLK_PCI_EC
12
R272 10_0402_5%@
+3VALW
1
C282
@
15P_0402_50V8J
2
EC_SMB_DA1 EC_SMB_CK1
EC_SMB_DA2 EC_SMB_CK2
MSEN#
R271
TP_DATA TP_CLK
KSO1 KSO2
EC_MUTE#
4.7K_0402_5%
1 2 1 2
R270
4.7K_0402_5%
1 2 1 2
1 2
Place under open door location
+3VALW
E51_TXD
R228
1 2
47K_0402_5%
0.1U_0402_16V4Z
R263 4.7K_0402_5% R262 4.7K_0402_5%
R264 4.7K_0402_5% R265 4.7K_0402_5%
R309 10K_0402_5%
1 2
+5VS_HD
R229
47K_0402_5% 47K_0402_5%
R230
10K_0402_5%
R277
JECDB1
1
1
2
2
3
3
4
4
ACES_85205-0400
CONN@
LID_SW#
+3VALW
R405
1 2
EC_PME#
2
C268
1
12 12
12 12
+3VALW
32.768KHZ_12.5PF_Q13MC14610002
Q1 APX9132ATI-TRL_SOT23-3
LID_SW#
3
VOUT
PCI_CLKRUN#20,27
+5VALW
+3VS
C292
EC_SCI#20
15P_0402_50V8J
1
EC_PME# 18,20
VGA_THER#33 FAN_SPEED14
KILL_ON#30
R278
1 2
20M_0603_5%@
1
2
2
VDD
GND
LID Switch
+3VALW +EC_AVCC
111
125
67
VCC
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
ACOFF/FANPWM2/GPIO13
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
AD Input
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
GPIO
BATT_LOW_LED#/GPIO54
VR_ON/XCLK32K/GPIO57
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04
ICH_PWROK/GPXO06
GPO
PM_SLP_S4#/GPXID1
GPI
GND
AGND
GND
GND
69
94
113
1000P_0402_50V7K~N
FANPWM1/GPIO12
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D
SDICS#/GPXOA00 SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPICLK/GPIO58
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
CAPS_LED#/GPIO53 SUSP_LED#/GPIO55
SYSON/GPIO56
AC_IN/GPIO59
EC_ON/GPXO05
EC_SWI#/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
ENBKL/GPXID2
ECAGND
C277
0.1U_0402_16V4Z~N
C285
0.1U_0402_16V4Z~N
C281
0.1U_0402_16V4Z~N
www.sp860.com QQ:453100829
GATEA2019 KB_RST#19 SERIRQ20 LPC_FRAME#19,24 LPC_AD319,24 LPC_AD219,24 LPC_AD119,24 LPC_AD019,24
CLK_PCI_EC15 PLT_RST#7,18,22,24,28,33
EC_SCI#
PCI_CLKRUN#
KSI[0..7]30
KSO[0..15]30
BT_ON#31
EC_SMB_CK144 EC_SMB_DA144 EC_SMB_CK24,33 EC_SMB_DA24,33
SLP_S3#20 SLP_S5#20 EC_SMI#20
EC_PME#18,20
ON_OFF30
PWR_LED#30,32
XCLKIXCLKO
C297
OSC4OSC
NC3NC
X2
+3VALW
1
1
2
2
KSI[0..7] KSO[0..15]
T57PAD
R257 0_0402_5%
1 2
@
KILL_ON#
T59PAD
15P_0402_50V8J
1
2
GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
CLK_PCI_EC PLT_RST# EC_RST#
BT_ON#
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
SLP_S3# SLP_S5# EC_SMI# LID_SW#
EC_PME# FAN_SPEED1
E51_TXD
ON_OFF PWR_LED# NUMLED#
XCLKI XCLKO
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2
KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14
KSO15
0.1U_0402_16V4Z~N
C493
1
2
1 2 3 4 5 7 8
10 12
13 37 20 38
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
77 78 79 80
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
122 123
C291
1000P_0402_50V7K~N
C269
1000P_0402_50V7K~N
U29
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
XCLK1 XCLK0
KB926QFD2_LQFP128
1
2
LPC & MISC
1
2
Int. K/B Matrix
SM Bus
9
22
33
96
VCC
VCC
VCC
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPIO
GND
GND
11
24
35
ECAGND
SPIDI/RD#
SPIDO/WR#
SPICS#
GPXO10 GPXO11
GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
V18R
1
C481
2
21
BEEP#
23 26
ACOFF
27
63
BATT_OVP
64
ADP_I
65
AD_BID
66 75 76
DAC_BRIG
68
EN_DFAN1
70
IREF
71
M_PWROK_EC
72
EC_MUTE#
83 84
VGA_ON
85
WL_OFF#
86
TP_CLK
87
TP_DATA
88
SPI_PULLDOWNKSO3
97
EN_WOL#
98 99
VGATE
109
FRD#SPI_SO
119
FWR#SPI_SI
120
SPI_CLK
126
FSEL#SPICS#
128
LCD_DET#
73
MSEN#
74
FSTCHG
89
BATT_CHG_LED#
90
CAPSLED#
91
BATT_LOW_LED#
92
SCRLED#
93
SYSON
95
VR_ON
121
ACIN
127
EC_RSMRST#
100
EC_LID_OUT#
101
EC_ON
102
EC_SWI#
103
ICH_PWROK
104
BKOFF#
105
3G_OFF#
106
MDC_ON#
107 108
SLP_S4#
110
EC_ENBKL
112
USB_EN
114
EC_THERM#
115 116 117
LCD_VCC_TEST_EN
118
C322 4.7U_0603_6.3V6M
124
C270 0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L18
12
FBM-11-160808-601-T_0603
2
C482
0.1U_0402_16V4Z~N
1
R266 0_0402_5%
1 2
C273 0.01U_0402_16V7K
1 2
BATT_TEMP
BIST
1 2
R256 0_0402_5%
R274
LCD_DET# 16
C251 100P_0402_25V8K
SUSP#
PBTN_OUT#
1 2
12
2007/1/15 2008/1/15
+3VALW+EC_AVCC
12
L19FBM-11-160808-601-T_0603
INVT_PWM 16 BEEP# 26
ACOFF 38
BATT_TEMP 44 BATT_OVP 44 ADP_I 38
BIST 16
DAC_BRIG 16 EN_DFAN1 4 IREF 38
EC_MUTE# 26 VGA_ON 33
WL_OFF# 24 TP_CLK 30 TP_DATA 30
@
4.7K_0402_5%
12
EN_WOL# 22 VGATE 7,20,43
MSEN# 17
FSTCHG 38
BATT_CHG_LED# 32
T58 PAD
BATT_LOW_LED# 32
T56 PAD
SYSON 28,36,41 VR_ON 43 ACIN 20,37,38
EC_RSMRST# 20 EC_LID_OUT# 20 EC_ON 30 EC_SWI# 20 ICH_PWROK 7,20
BKOFF# 16 3G_OFF# 24 MDC_ON# 28
SLP_S4# 20 EC_ENBKL 16 USB_EN 31
EC_THERM# 20
SUSP# 28,33,36,40,41
PBTN_OUT# 20
LCD_VCC_TEST_EN 16
Deciphered Date
ECAGND
CHGVADJ 38
C314
1 2
0.1U_0402_16V4Z~N
FSEL#SPICS# SPI_CS#
R439 15_0402_5%
FRD#SPI_SO
+3VALW
1 2
R437
12
10K_0402_5%
12
R27515_0402_5%
Custom
Board ID
M/B rev:0.1; 0.2; 0.3; 1.0 Voltage:0.0; 0.4; 0.8; 1.0
20mils
U37
1
CS#
2
SO
HOLD#
3
WP#
4
GND
MX25L1605AM2C-12G_SO8
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BIOS & EC I/O Port
LA-4841P
+3VALW
2007-09-19 change Brd ID
R232 47K_0402_5%
Ra
@
1 2
Rb
1 2
SPI Flash (8Mb*1)
C507
@
0_0402_5%
1 2
0.1U_0402_16V4Z~N
8
VCC
7
SPI_CLK_RSPI_SO
6
SCLK
5
SI
R231 15K_0402_5%
1 2
1 2
SPI_SI
1 2
AD_BID
1
C272
0.1U_0402_16V4Z
2
R419
R42015_0402_5% R43815_0402_5%
of
29 45Monday, December 15, 2008
SPI_CLK_R
FWR#SPI_SI
SPI_CLK
1.0
A
www.sp860.com QQ:453100829
Power Button
1 1
EC_ON29
PWR_ON-OFF_BTN#
CHN202UPT SC-70
+3VALW
R296
4.7K_0402_5%
@
1 2
EC_ON
R291 0_0402_5%
1 2
B
+3VALW
R297
1 2
D15
100K_0402_5%
2
1
2
G
3
13
D
Q26
SSM3K7002FU_SC70-3
S
51ON#
2
1
ON_OFF 29 51ON# 37
C1418 1000P_0402_50V7K~N
12
D13 RLZ20A_LL34
C
INT_KBD CONN.
KSI[0..7]29
KSO[0..15]29
KSI[0..7]
KSO[0..15]
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15
JKB1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
G1
27
G2
ACES_85202-2505L
@CONN
D
KSO8
C449 100P_0402_25V8K
KSI3
C239 100P_0402_25V8K
KSO9
C249 100P_0402_25V8K
KSI2
C240 100P_0402_25V8K
KSI1 KSO10
C248 100P_0402_25V8K
KSO11
C247 100P_0402_25V8K
KSI0
C242 100P_0402_25V8K
KSO12
C246 100P_0402_25V8K
KSO13
C245 100P_0402_25V8K
KSO14
C244 100P_0402_25V8K
KSO15
C243 100P_0402_25V8K
KSI7 KSI6 KSI5 KSO0 KSO1 KSO2 KSI4 KSO3 KSO4 KSO5 KSO6 KSO7
E
C235 100P_0402_25V8K C236 100P_0402_25V8K C237 100P_0402_25V8K C441 100P_0402_25V8K C442 100P_0402_25V8K C241 100P_0402_25V8K C443 100P_0402_25V8K C238 100P_0402_25V8K C444 100P_0402_25V8K C445 100P_0402_25V8K C446 100P_0402_25V8K C447 100P_0402_25V8K C448 100P_0402_25V8K
For EMI
SW/B CONN.
2 2
+5VALW
PWR_ON-OFF_BTN# PWR_LED#
1
1
2
2
C1416100P_0402_25V8K
ACES_85201-0405
1
@
@
2
C1417100P_0402_25V8K
JFN1
4
4
3
3
2
2
1
1
ME@
6
6
5
5
TP_CLK TP_DATA
2
3
D24 SM05T1G_SOT23-3~D
@
1
JTP1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_85201-06051
@CONN
112233G14G2
KILL_ON#
2-3:ON, 1-2:OFF
TP50
@
Touch PAD/B CONN.
PWR_LED#29,32
TP_CLK29 TP_DATA29
0.01U_0402_16V7K
+5VS
C300
SW1
Wireless_SW
+3VALW
+3VS
12
R12
@
0_0402_5%
KILL_ON#29
3 3
4 4
R1131 100K_0402_5%
1 2
1BS003-1210L_3P
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
PWR_OK/BTN/TP
LA-4841P
E
30 45Monday, December 15, 2008
1.0
of
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C64
0.1U_0402_16V4Z
USB20_P520
USB20_N520
C228
+5VALW
1
2
C253
1
2
+5VALW
+3VS +5VS
USB_EN29
1
2
Fingerprint
USB20_P5 USB20_N5
80 mils
USB_EN#
80 mils
USB_EN#
80 mils
USB_EN#
+5VALW
USB_EN
2
G
USB20_N5
JFP1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_85201-06051
CONN@
R1226 10K_0402_5%
1 2 13
D
Q4 SSM3K7002FU_SC70-3
S
OUT OUT OUT OC#
OUT OUT OUT OC#
C30
8 7 6 5
8 7 6 5
8
OUT
7
OUT
6
OUT
5
OC#
USB20_P5
Camera
1
2
USB20_N2 USB20_P2
+USB_AS+5VALW
1
+
150U_B2_6.3VM_R45M
2
+USB_CS
1 2
R44 0_0402_5%
+USB_BS
+5VS
1
C29
0.1U_0402_16V4Z
2
2
3
D1
@
PSOT24C_SOT23
1
0.1U_0402_16V4Z
C434
+5VS
R13
12
0_0402_5%
12
R15 0_0402_5%
USB_OC#0 20
USB_EN#
USB_N2 USB_P2
C223
USB_EN#
12
R154 100K_0402_5%
USB_OC#3 20 USB_OC#2 20
USB_EN#
USB_EN#
12
USB_OC#1 20
USB_OC#1 20
13
D
2
G
S
JCAM1
1
1
2
2
3
3
4
4
5
5
6
GND1
7
GND2
ACES_88266-05001
CONN@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R155 30K_0402_5%
13
D
2
G
S
2
G
R36 30K_0402_5%
Q8 SSM3K7002FU_SC70-3
BT_ON#29
Q14 SSM3K7002FU_SC70-3
USB20_N020
USB20_P020
12
R38 30K_0402_5%
13
D
Q13 SSM3K7002FU_SC70-3
S
0.1U_0402_16V4Z
1 2
R755 100K_0402_5%
2007/1/15 2008/1/15
USB20_N0
USB20_P0
USB20_N120
USB20_P120
+3VS +3VALW
12
@
R8 0_0402_5%
C759
4.7U_0805_10V4Z
Deciphered Date
2
C761
G
BT_LED#32
USB20_N1
USB20_P1
D
1 3
1
2
R1 0_0402_5%
R3 0_0402_5%
10K_0402_5%
2N7002_SOT23
12
S
Q56 SI2301BDS_SOT23
W=40mils
12
12
+USB_BS/+USB_CS =80mils
USB20_N820
USB20_P820
USB20_N920
USB20_P920
+5VS
12
R605
BT_LED#
13
D
Q43
2
G
S
R9 0_0402_5%
1
C760 1U_0603_10V4Z
2
+BT_VCC
C762
0.1U_0402_16V4Z
USB_P1
USB_N1
USB_N0 USB_P0
USB20_N8 USB20_P8
USB20_N9 USB20_P9
12
R606 10K_0402_5%
12
12
+USB_CS+USB_BS
BT_ACTIVE24
WLAN_ACTIVE24
USB20_N420 USB20_P420
Title
Size Document Number Rev
Custom
Date: Sheet
R54 0_0402_5%
R62 0_0402_5%
www.sp860.com QQ:453100829
U12
1
GND
2
IN
3
IN
4
EN#
RT9711BPS SO 8P
U14
1
GND
2
IN
3
IN
4
EN#
RT9711BPS SO 8P
U13
1
GND
2
IN
3
IN
4
EN#
RT9711BPS SO 8P
D29
1 2
USB_EN#
3
GND
IO2
4
IO1
VIN
PRTR5V0U2X_SOT143-4
@
4.7U_0805_10V4Z
USB20_N220 USB20_P220
CM1293-04SO_SOT23-6
1
CH1
2
Vn
3
CH2
D19
@
USB_N1 USB_P1
JUSB3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
G1
14
G2
E&T_3703-E12N-03R
ME@
+USB_AS
+USB_AS
4
CH4
5
Vp
6
CH3
W=80mils
W=80mils
USB_P0
USB_N0
1 2 3 4
5 6 7 8
1 2 3 4
5 6 7 8
+USB_AS
Bluetooth
BT_ACTIVE WLAN_ACTIVE BTON_LED USB20_N4 USB20_P4
+BT_VCC
Compal Electronics, Inc.
USB/BlueTooth/FP/Felcia
LA-4841P
JUSB1
VCC D­D+ GND
GND1 GND2 GND3
GND4
SUYIN_020173MR004G565ZR
CONN@
JUSB2
VCC
D-
D+
GND
GND1
GND2
GND3
GND4
SUYIN_020173MR004G565ZR
ME@
JBT1
1 2 3 4 5 6 7 8
ACES_87212-0800
of
31 45Monday, December 15, 2008
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
D D
+5VALW
C C
+5VALW
+5VALW
+5VS
+5VS
B B
R93
2.2K_0402_5%
1 2
R710
3.3K_0402_5%
1 2
R711
3.3K_0402_5%
1 2
R708
3.3K_0402_5%
1 2
R709
3.3K_0402_5%
1 2
White
2 1
19-213A/T1D-CP2Q2HY/3T 0603 WHITE
LED3
LED2
A
4 3
B
2 1
HT-297UD/CB _BLUE/AMB_0603
LED5
A
4 3
B
2 1
HT-297UD/CB _BLUE/AMB_0603
PWR_LED#
Amber
BATT_LOW_LED#
BATT_CHG_LED#
Blue
Amber
Blue
BT_LED#
LED_WLAN#
PWR_LED# 29,30
BATT_LOW_LED# 29
BATT_CHG_LED# 29
BT_LED# 31
LED_WLAN# 24
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Deciphered Date
Title
PWR_OK/BTN/TP
Size Document Number Rev
Custom
LA-4841P
2
Date: Sheet
1
32 45Monday, December 15, 2008
1.0
of
5
4
3
2
1
1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN
RUNPWROK
5VRUN
GND GND GND
PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2
PEG_NRX_GTX_N[0..15] PEG_NRX_GTX_P[0..15]
PEG_NTX_GRX_N[0..15] PEG_NTX_GRX_P[0..15]
2 4 6 8 10 12 14 16 18 20 22 24
26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108
PEG_NTX_GRX_N15 PEG_NTX_GRX_P15
PEG_NTX_GRX_N14 PEG_NTX_GRX_P14
PEG_NTX_GRX_N13 PEG_NTX_GRX_P13
PEG_NTX_GRX_N12 PEG_NTX_GRX_P12
PEG_NTX_GRX_N11 PEG_NTX_GRX_P11
PEG_NTX_GRX_N10 PEG_NTX_GRX_P10
PEG_NTX_GRX_N9 PEG_NTX_GRX_P9
PEG_NTX_GRX_N8 PEG_NTX_GRX_P8
PEG_NTX_GRX_N7 PEG_NTX_GRX_P7
PEG_NTX_GRX_N6 PEG_NTX_GRX_P6
PEG_NTX_GRX_N5 PEG_NTX_GRX_P5
PEG_NTX_GRX_N4 PEG_NTX_GRX_P4
PEG_NTX_GRX_N3 PEG_NTX_GRX_P3
PEG_NTX_GRX_N2 PEG_NTX_GRX_P2
www.sp860.com QQ:453100829
D D
B+ +1.8VS
PEG_NRX_GTX_N15 PEG_NRX_GTX_P15
PEG_NRX_GTX_N14 PEG_NRX_GTX_P14
C C
B B
PEG_NRX_GTX_N13 PEG_NRX_GTX_P13
PEG_NRX_GTX_N12 PEG_NRX_GTX_P12
PEG_NRX_GTX_N11 PEG_NRX_GTX_P11
PEG_NRX_GTX_N10 PEG_NRX_GTX_P10
PEG_NRX_GTX_N9 PEG_NRX_GTX_P9
PEG_NRX_GTX_N8 PEG_NRX_GTX_P8
PEG_NRX_GTX_N7 PEG_NRX_GTX_P7
PEG_NRX_GTX_N6 PEG_NRX_GTX_P6
PEG_NRX_GTX_N5 PEG_NRX_GTX_P5
PEG_NRX_GTX_N4 PEG_NRX_GTX_P4
PEG_NRX_GTX_N3 PEG_NRX_GTX_P3
PEG_NRX_GTX_N2 PEG_NRX_GTX_P2
JP57A
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
GND
19
GND
21
GND
23
GND
25
PEX_RX15#
27
PEX_RX15
29
GND
31
PEX_RX14#
33
PEX_RX14
35
GND
37
PEX_RX13#
39
PEX_RX13
41
GND
43
PEX_RX12#
45
PEX_RX12
47
GND
49
PEX_RX11#
51
PEX_RX11
53
GND
55
PEX_RX10#
57
PEX_RX10
59
GND
61
PEX_RX9#
63
PEX_RX9
65
GND
67
PEX_RX8#
69
PEX_RX8
71
GND
73
PEX_RX7#
75
PEX_RX7
77
GND
79
PEX_RX6#
81
PEX_RX6
83
GND
85
PEX_RX5#
87
PEX_RX5
89
GND
91
PEX_RX4#
93
PEX_RX4
95
GND
97
PEX_RX3#
99
PEX_RX3
101
GND
103
PEX_RX2#
105
PEX_RX2
107
GND
ACES_88990-2D08
PEG_NRX_GTX_N[0..15] 9 PEG_NRX_GTX_P[0..15] 9 PEG_NTX_GRX_N[0..15] 9 PEG_NTX_GRX_P[0..15] 9
SUSP# 28,29,36,40,41
+5VS
JP57B
PEG_NRX_GTX_N1 PEG_NRX_GTX_P1
PEG_NRX_GTX_N0 PEG_NRX_GTX_P0
VGA_PWGOD#36
CLK_PCIE_VGA# CLK_PCIE_VGA
VGA_ON
VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA
CLK_NVSS_27M CLK_NV_27M
+3VALW +5VALW
+1.5VS
VGA_PWGOD#
CLK_PCIE_VGA#15
CLK_PCIE_VGA15
PLT_RST#7,18,22,24,28,29
VGA_ON29
EC_SMB_DA24,29
EC_SMB_CK24,29
VGA_THER#29
VGA_HSYNC17
VGA_VSYNC17
VGA_DDCCLK17
VGA_DDCDATA17
CLK_NVSS_27M15
CLK_NV_27M15
109
PEX_RX1#
111
PEX_RX1
113
GND
115
PEX_RX0#
117
PEX_RX0
119
GND
121
PEX_REFCLK#
123
PEX_REFCLK
125
CLK_REQ#
127
PEX_RST#
129
RSVD
131
RSVD
133
SMB_DAT
135
SMB_CLK
137
THERM#
139
VGA_HSYNC
141
VGA_VSYNC
143
DDCA_CLK
145
DDCA_DAT
147
IGP_UCLK#
149
IGP_UCLK
151
GND
153
RSVD
155
RSVD
157
RSVD
159
IGP_UTX2#
161
IGP_UTX2
163
GND
165
IGP_UTX1#
167
IGP_UTX1
169
GND
171
IGP_UTX0#
173
IGP_UTX0
175
GND
177
IGP_LCLK#/DVI_B_CLK#
179
IGP_LCLK/DVI_B_CLK
181
DVI_B_HPD/GND
183
RSVD
185
RSVD
187
GND
189
IGP_LTX2#/DVI_B_TX2#
191
IGP_LTX2/DVI_B_TX2
193
GND
195
IGP_LTX1#/DVI_B_TX1#
197
IGP_LTX1/DVI_B_TX1
199
GND
201
IGP_LTX0#/DVI_B_TX0#
203
IGP_LTX0/DVI_B_TX0
205
DVI_A_HPD
207
DVI_A_CLK#
209
DVI_A_CLK
211
GND
213
DVI_A_TX2#
215
DVI_A_TX2
217
GND
219
DVI_A_TX1#
221
DVI_A_TX1
223
GND
225
DVI_A_TX0#
227
DVI_A_TX0
229
GND
ACES_88990-2D08
GND
PEX_TX1#
PEX_TX1
GND
PEX_TX0#
PEX_TX0 PRSNT1#
TV_C/HDTV_Pr
GND
TV_Y/HDTV_Y
TV_CVBS/HDTV_Pb
GND GND
VGA_RED
GND
VGA_GRN
GND
VGA_BLU
GND
LVDS_UCLK#
LVDS_UCLK
GND
LVDS_UTX3#
LVDS_UTX3
GND
LVDS_UTX2#
LVDS_UTX2
GND
LVDS_UTX1#
LVDS_UTX1
GND
LVDS_UTX0#
LVDS_UTX0
GND
LVDS_LCLK#
LVDS_LCLK
GND
LVDS_LTX3#
LVDS_LTX3
GND
LVDS_LTX2#
LVDS_LTX2
GND
LVDS_LTX1#
LVDS_LTX1
GND
LVDS_LTX0#
LVDS_LTX0
GND DDCC_DAT DDCC_CLK
LVDS_PPEN
LVDS_BL_BRGHT
LVDS_BLEN
DDCB_DAT DDCB_CLK
2V5RUN
GND
3V3RUN 3V3RUN 3V3RUN
110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230
PEG_NTX_GRX_N1 PEG_NTX_GRX_P1
PEG_NTX_GRX_N0 PEG_NTX_GRX_P0
VGA_TV_CRMA VGA_TV_LUMA VGA_TV_COMPS VGA_CRT_R VGA_CRT_GVGA_CRT_HSYNC VGA_CRT_B
VGA_LVDSAC­VGA_LVDSAC+
VGA_LVDSA2­VGA_LVDSA2+
VGA_LVDSA1­VGA_LVDSA1+
VGA_LVDSA0­VGA_LVDSA0+
VGA_DAT_LCD VGA_CLK_LCD ENVDD
VGA_ENBKL
+3VS
VGA_TV_CRMA VGA_TV_LUMA
VGA_TV_COMPS VGA_CRT_R 17 VGA_CRT_G 17 VGA_CRT_B 17
VGA_LVDSAC- 16 VGA_LVDSAC+ 16
VGA_LVDSA2- 16 VGA_LVDSA2+ 16
VGA_LVDSA1- 16 VGA_LVDSA1+ 16
VGA_LVDSA0- 16 VGA_LVDSA0+ 16
VGA_DAT_LCD 16 VGA_CLK_LCD 16
VGA_LVDDEN 16 VGA_ENBKL 16
+1.8VS +3VS +5VSB+
2
C1443
0.1U_0603_25V7K
VGA@
A A
1
4.7U_0805_10V4Z
5
C424
VGA@
1
2
1
C425
0.1U_0402_16V4Z
2
VGA@
4.7U_0805_10V4Z
C426
VGA@
4
1
2
1
C427
0.1U_0402_16V4Z
2
VGA@
1
C429
0.1U_0402_16V4Z
2
VGA@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
MXM Connector
LA-4841P
1
33 45Monday, December 15, 2008
of
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
D D
H_3P0
H14 HOLEA
H_3P7
H_4P2
C C
H_3P2
H_5P6
H19 HOLEA
1
H23 HOLEA
1
H31 HOLEA
1
1
H20 HOLEA
H24 HOLEA
H_4P4
B B
H34 HOLEA
1
H2 HOLEA
1
H15 HOLEA
1
1
1
H3 HOLEA
H16 HOLEA
H21 HOLEA
1
H25 HOLEA
1
1
1
H4
H5
HOLEA
HOLEA
1
1
H17
H18
HOLEA
HOLEA
1
1
H22 HOLEA
1
H27
H26
HOLEA
HOLEA
1
1
H_3P1N
H6 HOLEA
H28 HOLEA
1
H9 HOLEA
1
H10 HOLEA
1
H8
H7
HOLEA
HOLEA
1
H29 HOLEA
1
H33 HOLEA
1
1
1
H30 HOLEA
1
H11 HOLEA
1
H12 HOLEA
1
H13 HOLEA
1
FD4
FD3
FD2
FD1
@
@
@
@
1
1
1
1
H36
H35
HOLEA
HOLEA
1
1
H37 HOLEA
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Screws
LA-4841P
1
34 45Monday, December 15, 2008
1.0
of
A
KAL80 POWER UP SEQUENCE
www.sp860.com QQ:453100829
Suspend Clock (32KHz) ICH9 internal clock
This signal is asserted high when
A A
both SLP_S3# and VRMPWRGD are high
ACIN/BATT-IN
51ON# (only BATT-IN)
5VALW/3VALW
RSMRST#
SUSCLK
ON/OFF#
EC_ON
PWRBTN_OUT#
SYSON#
1.8V
SLP_S5#
SLP_S4#
SLP_S3#
SUSP#
+5VS
+3VS
+1.5VS
+0.9VS
VCCP
VR_ON
CPU_CORE
VGATE
CK_PWRGD
CLK_MCH_BCLK
ICH_PWROK
PCI_RST#
H_PWRGOOD
H_RESET#
126ms
←→
644ms
864us
244ms
→←
360ms
1.59ms
←→
→←
2.74ms
250ms
30.6us
3.88s
30us
→←
888us
104us
112us
←→
→←
2.02ms
→←
1.46ms
←→
24.1ms
←→
1.20ms
5.26ms
1.03ns
←→
114ms
←→
1.20ms
←→
1.06ms
2.20ms
Title
<Title>
Size Document Number Rev
LA-4841P 1.0
Custom
A
Date: Sheet
of
35 45Monday, December 15, 2008
A
B
C
D
E
www.sp860.com QQ:453100829
+3VS+3VALW
B+_BIAS
1
C271
2
10U_0805_10V4Z~N
1 2
R197 100K_0402_5%
SYSON28,29,41
8 7 6 5
12
R198
330K_0402_5%
1 1
SUSP
2 2
RUNON 3VS_GATE
13
D
2
Q18
G
SSM3K7002FU_SC70-3
S
4A 8A
U40
S
D
S
D
S
D
G
D
SI4800DY_SO8
1
C264
0.01U_0402_25V7K~N
2
1 2 3 4
1
2
0.1U_0402_16V4Z~N
R409
100K_0402_5%
SYSON#
SYSON
2
R365 10K_0402_5%
1 2
10U_0805_10V4Z~N
1
C465
C256
2
+3VALW
12
13
D
Q42 SSM3K7002FU_SC70-3
G
S
+5VALW to +5VS Transfer+3VALW to +3VS Transfer
1
C278
2
10U_0805_10V4Z~N
RUNON 5VS_GATE
+CPU_CORE
U39
8
D
7
D
6
D
5
D
SI4800DY_SO8
1 2
R267 47K_0402_5%
+5VS+5VALW
1
S
2
S
3
S
4
G
1
2
0.1U_0402_16V4Z~N
C279
0.01U_0402_25V7K~N
1 2
C211 0.1U_0402_16V4Z~N
1
C284
2
1
C283 10U_0805_10V4Z~N
2
+VCCP
+1.8V to +1.8VS Transfer
VGA_PWGOD#33
VGA_PWGOD#
SUSP
1 2
R665
0_0402_5%@
B+_BIAS
VGA@
2
G
1
R1227
C727
1 2
2
10U_0805_10V4Z~N
47K_0402_5%
VGA@
1.8VS ON 1.8VS_GATE
1 2
R608 100K_0402_5%
VGA@
13
D
Q48
SSM3K7002FU_SC70-3
S
VGA@
U41
8
D
7
D
6
D
5
D
SI4800DY_SO8
VGA@
1
C696
0.01U_0402_25V7K~N
2
VGA@
1
S
2
S
3
S
4
G
+1.8VS+1.8V
10U_0805_10V4Z~N
1
C728
0.1U_0402_16V4Z~N
2
VGA@
4.7A
1
2
C697
VGA@
+5VALW
12
2
G
R338 10K_0402_5%
1 2
R340 100K_0402_5%
13
D
Q32 SSM3K7002FU_SC70-3
S
Discharge circuit-1
B
+1.8V
12
R133 470_0402_5%
13
SYSON#
D
2
G
Q12
S
SSM3K7002FU_SC70-3
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Deciphered Date
SUSP
+0.9VS
12
13
D
2
G
S
R351 470_0402_5%
SUSP SUSPSUSP
Q33 SSM3K7002FU_SC70-3
D
+5VS
12
13
D
2
G
S
+3VS
12
R391
470_0402_5%
Q39 SSM3K7002FU_SC70-3
Title
Size Document Number Rev
Custom
Date: Sheet
R383
470_0402_5%
13
D
2
G
Q38
S
SSM3K7002FU_SC70-3
Compal Electronics, Inc.
DC/DC Circuits
LA-4841P
+1.5VS
12
13
D
2
G
S
E
R382 470_0402_5%
Q37 SSM3K7002FU_SC70-3
of
36 45Monday, December 15, 2008
1.0
3 3
SUSP27,42
SUSP#28,29,33,40,41
4 4
SUSP
SUSP#
SYSON -> SUSP# -> VGA_ON->VGA_PWGOD
A
5
4
3
2
1
www.sp860.com QQ:453100829
PJPDC1
1
1
2
D D
BATT+
C C
51ON#30
2
3
4
ACES_88290-044G
@
PD3
12
RLS4148_LL34-2
CHGRTCP
PR11
100K_0402_5%~D
PR12
22K_0402_5%~D
1 2
12
3
4 5 6
PJP1 JUMP_43X118@
2
112
PQ1
TP0610K-T1-E3_SOT23-3
13
12
12
PC11
0.22U_1206_25V7K
51ON#_Gate
2
12
PC2
100P_0402_50V8J~D
VIN
PD2
RLS4148_LL34-2
1 2 12
PR10
68_1206_5%
12
PC12
0.1U_0603_25V7K~D
PC3
VS
1000P_0402_50V7K~D
12
PR14
68_1206_5%
ADPIN
PL1
SMB3025500YA_2P
1 2
12
12
PC5
PC4
1000P_0402_50V7K~D
100P_0402_50V8J~D
12
PC6
100P_0402_50V8J~D
VIN
VIN
12
PC7
1000P_0402_50V7K~D
PC10
0.1U_0402_16V7K~D
12
PR3
82.5K_0402_1%~D PR6
22K_0402_1%~D
1 2
12
PR8
19.6K_0402_1%~D
+
-
8
PU1B
P
O
G
LM393DR_SO8
4
12
7
12
32.3
5 6
PC1
2200P_0402_50V7K~D
@
1 2
VinDe_INN41 VinDe_Ref
PC9 1000P_0402_50V7K~D
Vin Detector Max. typ. Min.
L-->H 18.234 17.841 17.449 H-->L 17.597 17.210 16.813
56K_0402_5%~D@
1 2
PR2 1M_0402_1%~N
1 2
VS
8
PU1A
3
P
+
2
-
G
LM393DR_SO8
4
PR9
10K_0402_5%~D
12
PR1
O
12
PC8
1
0.01U_0402_25V7K~D
VinDe_Out
RLZ4.3B_LL34
RTCVREF
3.3V
PD1
VIN
12
PR5 10K_0402_5%~D
12
PR4 1K_0402_5%~D
1 2
12
PR7 10K_0402_5%~D
ACIN 20,29,38
12
PR13 200_0805_5%
12
PC14 1U_0805_25V4Z~D
4
PJP7 JUMP_43X118@
112
PJP11 JUMP_43X118@
112
PJP13 JUMP_43X118@
112
2
+0.9VS
2
+1.8V
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/10/1 2007/5/01
Deciphered Date
Title
DCIN / Precharge
Size Document Number Rev
2
Date: Sheet
KFW11
1
37 45Monday, December 15, 2008
1.0Custom
of
3
4.7U_0805_6.3V6K~D
+5VALW
+3VALW
+1.5VS
+VCCP
APL5156-33DI-TRL_SOT89-3
PU3
VOUT
GND
2
VIN
1
+0.9VSP
+1.8VP
RTCVREF
PJP2 JUMP_43X118@
PJP4 JUMP_43X118@
PJP6 JUMP_43X118@
PJP8 JUMP_43X118@
PJP10 JUMP_43X118@
PJP12 JUMP_43X118@
5
112
112
112
112
112
112
12
PC13
2
2
2
2
2
2
B B
+5VALWP
+3VALWP
+1.5VSP
A A
+VCCPP
A
B
C
D
E
www.sp860.com QQ:453100829
PQ4
VIN
12
12
3.3_1210_5%~D
1 2
PR23
3.3_1210_5%~D
PR26
PC27
2.2U_0805_25V6K
1 2
1 1
90W adapter Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3A
2 2
Iadapter=(Vacset/Vvdac)*(0.1/PR217)=4.27A Input OVP : 22.3V
FDS4435BZ_SO8
8
D
7
D
6
D
5
D
PC15
0.01U_0603_50V7K~D
PR25 340K_0402_1%~D
1 2
ACDET
PR30
54.9K_0402_1%
1 2
PR33 340K_0402_1%~D
1 2
OVPSET
1
S
2
S
3
S
4
G
PC20
1 2
+3VALW
CP setting
Input UVP : 16.98V
ACGOOD#
PR34
54.9K_0402_1%
1 2
SI2301BDS-T1-E3_SOT23-3
PR35
100K_0402_1%~D
1 2
PC40
0.1U_0603_25V7K~D
GATE
2
12
ACSET
Fsw : 300KHz
3 3
PQ5
FDS4435BZ_SO8
1 2 3 4
12
PR24
100K_0402_1%~D
0.01U_0402_25V7K~D
ACDRV
56.2K_0402_1%~D
0.01U_0402_25V7K~D
PQ9
S S S G
PR31
1 2
PC29
@
1 3
8
D
7
D
6
D
5
D
12
PC17
0.1U_0603_25V7K~D
12
1U_0603_10V6K~D
+3VALW
COIN RTC Battery
+COINCELL
PR21
0.015_2512_1%
1 2
0.1U_0402_16V7K~D
PC38
1 2
0_0402_5%~D
PC24
1 2
ACP
ACSET
12
PR32 100K_0402_1%~D
1 2
0.47U_0603_16V7K~N
VREF
12
PR86
4 3
ACN
VADJ
/BATDRV
PJP15
1
1
2
2
3
G1
@
4
G2
SUYIN_060003FA002G201NL
PU4
CHGEN#
1
CHGEN
12
PC18
0.1U_0603_25V7K~D
2
ACN
3
ACP
4
ACDRV
5
ACDET
6
ACSET
ACOP
7
ACOP
PC34
8
OVPSET
9
AGND
10
VREF
PR87 0_0402_5%~D
@
1 2
11
VDAC
12
VADJ
13
ACGOOD
14
BATDRV
BQ24751ARHDR_QFN28_5X5
ADP_I29
PVCC
BTST
HIDRV
REGN
LODRV
PGND
LEARN
CELLS
SRSET
IADAPT
SRP SRN BAT
28
27
26
25
PH
24
23
22
21
20
19 18 17
29
TP
16
15
B+
PC16
0.1U_0805_25V7K
PVCC
1 2
PR27
2.2_0603_5%~D
BTST
1 2
DH_CHG
LX_CHG
PD7
RLS4148_LL34-2
REGN
12
PC30 1U_0603_10V6K~D
DL_CHG
SRP SRN
12
PC39
0.1U_0603_25V7K~D
IADAPT
1 2
PR42
10_0603_5%~D
PC42
100P_0402_50V8J~D
PJP14
2
112
JUMP_43X118@
AO4466_SO8
12
1 2
PC28
0.1U_0603_25V7K~D
AO4712_SO8
ACOFF 29
ICHG setting
12
PR38 100K_0402_1%~D
12
578
PQ6
578
PQ8
12
IREF Current
0.486V 0.5A
2.916V 3A
CHG_B+
PC254.7U_1206_25V6K~D
1 2
3 6
241
3 6
241
47K_0402_1%~D
PC41
0.01U_0402_25V7K~D
@
PL3
10U_LF919AS-100M-P3_4.5A_20%
1 2
12
PR29
4.7_1206_5%~D
12
PC31
680P_0603_50V7K~D
PR37
12
12
PC211000P_0402_50V7K~D
1 2
IREF 29
PC261000P_0402_50V7K~D
PC224.7U_1206_25V6K~D
12
PC32
1 2
10U_1206_25V6M~D
12
PC36
0.1U_0603_25V7K~D
PC194.7U_1206_25V6K~D
1 2
/BATDRV
0.02_2512_1%
1 2
0.1U_0402_16V7K~D
1 2
PC23
1 2
PR28
4 3
PC35
PR39
100K_0402_1%~D
ACGOOD#
0.01U_0402_25V7K~D
@
RTCVREF
12
12
PR22 100K_0402_1%~D
12
PC37
0.1U_0603_25V7K~D
VREF
1 2
13
2
G
3
4
S1S2S
G
D8D7D6D
5
12
@
PR40
100K_0402_1%~D
D
PQ11 SSM3K7002F_SC59-3
S
@
PQ7 FDS4435BZ_SO8
BATT+
PC33
10U_1206_25V6M~D
ACIN 20,29,37
REGN
PR43
1 2
B+
100_0805_5%~D
+5VALW
PR47
1 2
12
1 2
1SS355_SOD323-2
220K_0402_5%
470K_0402_5%~D
2
G
A
PD9
PR51
4 4
1 2
220K_0402_5%
12
PC46
PR53
0.1U_0603_25V7K~D
TP0610K-T1-E3_SOT23-3
13
2
13
D
PQ16 RHU002N06_SOT323-3
S
PQ12
PC44
B+_BIAS
PR48
210K_0402_1%~D
1 2
0.1U_0805_25V7M~N
CHGVADJ29
1 2
12
PR44 0_0402_5%~D@
VADJ
12
PR50 499K_0402_1%~D
ACOFF
1 2
PC45
0.1U_0402_16V7K~D
PR49
100K_0402_1%~D
CHGVADJ Battery Voltage/per cell
0V 3V
3.3V 4.2V
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/10/1 2007/5/01
VREF
VREF
12
2
G
12
PR52 340K_0402_1%~D
12
PR45 200K_0402_1%~D
13
D
S
Deciphered Date
13
D
2
G
S
PQ14 SSM3K7002F_SC59-3
GATE
PQ13 SSM3K7002F_SC59-3
D
FSTCHG29
Title
Size Document Number Rev
B
Date: Sheet
VREF
PR46 100K_0402_1%~D
1 2
CHGEN#
13
D
PQ15
2
SSM3K7002F_SC59-3
G
S
Compal Electronics, Inc.
Charger KFW11
38 45Monday, December 15, 2008
E
1.0
of
5
B+
PJP16 JUMP_43X118@
2
112
D D
+3VALWP
1
+
PC57
330U_D3L_6.3VM_R25M
C C
2
PR59
1 2
PR61
1 2
@
www.sp860.com QQ:453100829
12
12
PC48
PC47
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
PL5
1 2
4.7UH_PCMC063T-4R7MN_5.5A_20%
0_0402_5%~D
10K_0402_1%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
3.3VALWP
VS
Imax=6A
PD10
RLZ5.1B_LL34
1 2
Iocp=9A
B B
A A
Fsw=300kHz
1 3
4
12
PC49
2200P_0402_50V7K~D
12
PR56
4.7_1206_5%~D
12
PC60
680P_0603_50V7K~D
100K_0402_1%~D
1 2
MAINPWON44
2
TP0610K-T1-E3_SOT23-3
PD11
1 2
1SS355_SOD323-2
ISL6237_B+
578
3 6
241
578
3 6
241
PR65
PR66
PQ21
PQ17 AO4466_SO8
PQ19 AO4712_SO8
PC64
0.22U_0603_25V7-K
1 2
1 2
200K_0402_5%~D
VL
PR71
PR72
12
0_0402_5%~D
PC58
0.1U_0603_25V7K~D
1 2
1 2
806K_0603_1%
PC66
12
PR54
0_0805_5%
1 2
0.1U_0603_25V7K~D
PR55
BST3A BST5A
12
0_0603_5%~D
LX3
DL3
FB3
VL
2VREF_ISL6237
1 2
PC63 0.22U_0603_10V7K~D
EN_LDO
6237_EN1
6237_EN2
PR69
@
0_0402_5%~D
PR73
47K_0402_5%~D@
1 2
0.047U_0603_16V7K~D
1 2
12
PC67
@
0.047U_0402_16V7K~N
PC53
1 2
2VREF_ISL6237
3
1 2
PU5
33
TP
26
DRVH2
24
VBST2
25
LL2
23
DRVL2
30
VOUT2
32
REFIN2
1
VREF2
8
LDOREFIN
20
NC
4
EN_LDO
14
EN1
27
EN2
PR70
0_0402_5%~D
PC65
1U_0603_10V6K~D
6
5
6237_NC
12
VIN
VREF3
1 2
PC54
1U_0603_10V6K~D
3
V5FILT
TONSE
2
6237_TON
12
PR74
@
0_0402_5%~D
2VREF_ISL6237
VL
12
PC55
7
4.7U_0805_6.3V6K~D
19
LDO
V5DRV DRVH1 VBST1
LL1
DRVL1
PGND
VOUT1
FB1
VSW
SKIPSEL
PGOOD2
PGOOD1
TRIP1
TRIP2
GND
SN0806081RHBR_QFN32_5X5
21
DH5DH3
15 17
LX5
16
DL5
18
22
10
FB5
11
9
6237_SKIP
29
28
13
ILM1
12
ILIM2
31
2
ISL6237_B+
PC56
1U_0603_10V6K~D
1 2
PR58
0_0603_5%~D
0.1U_0603_25V7K~D
12
PC59
PR63 0_0402_5%~D@
PR64 0_0402_5%~D
1 2
AO4466_SO8
AO4712_SO8
1 2
12
PR67
255K_0402_1%~D
PR68
255K_0402_1%~D
PQ18
PQ20
578
3 6
578
3 6
241
241
12
PC51
PC50
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7UH_PCMC063T-4R7MN_5.5A_20%
12
PR57
4.7_1206_5%~D
12
PC61
680P_0603_50V7K~D
VL
POK 20
12
12
12
PL4
12
PC52
2200P_0402_50V7K~D
12
PR60
61.9K_0402_1%~D
PR62
10K_0402_1%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
5VALWP
Imax=6A
Iocp=9A
Fsw=400kHz
1
+5VALWP
1
+
PC62
1 2
1 2
330U_D3L_6.3VM_R25M
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2006/10/1 2007/05/30
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
+3VALWP, +5VALWP
Size Document Number Rev
Date: Sheet
2
KFW11
Monday, December 15, 2008
1
of
39 45
1.0Custom
5
4
3
2
1
www.sp860.com QQ:453100829
D D
PJP17 JUMP_43X118@
B+
C C
SUSP#28,29,33,36,41
B B
112
0_0402_5%~D
1 2
PR80
2
6268_1.5V
12
PC72
2.2U_0603_6.3V6K~D
PC75
0.1U_0402_16V7K~D
12
PC69
10U_1206_25V6M~D
PC68
12
@
10U_1206_25V6M~D
12
@
PC77
6268_B+
12
22P_0402_50V8J~D
6268_1.5V
3
4
5
PC79
2200P_0402_50V7K~D
PR75
1 2
10K_0402_1%~D
@
8
GND
VIN
VCC
EN
COMP6FB7FSET
12
PR83
49.9K_0402_1%~D
12
45.3K_0402_1%~D
2
PGOOD
PR84
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
PHASE_1.5V
PR76
1 2
0_0603_5%~D
BOOT_1.5V
15
16
1
UG
BOOT
PHASE
9
12
14
PVCC
13
LG
12
PGND
11
ISEN
VO
PU6
10
ISL6268CAZ-T_SSOP16
12
PC78
0.01U_0402_25V7K~D
UG_1.5V
1 2
+5VS
12
PR77
0_0603_5%~D
PR78 4.7_0603_5%~D
1 2
PC71
1 2
2.2U_0603_6.3V6K~D
LG_1.5V
ISEN_1.5V
1 2
PR81
5.11K_0402_1%~D
PC70
0.1U_0603_25V7K~D
6268_1.5V
PQ23
AO4712_SO8
578
PQ22
AO4466_SO8
3 6
241
4.7U_D104C-919AS-4R7N_5.2A_20%
578
3 6
241
1 2
PR79
4.7_1206_5%~D
1 2
PC76 680P_0603_50V8J~D
1 2
PL6
1.5VSP
Imax=3.5A
Iocp=6A
Fsw=294kHz
PR85
1.33K_0402_1%~D
PR82 2K_0402_1%~D
1 2
12
+1.5VSP
12
PC74
4.7U_0805_6.3V6K~D
1
+
PC73 220U_6.3V_M
2
+1.5VSP
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/10/1 2007/05/30
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
1.5VSP
KFW11
Monday, December 15, 2008
1
40 45
1.0
of
5
4
3
2
1
www.sp860.com QQ:453100829
D D
PC98
12
12
4
VCC1
1U_0402_6.3V6K~D
PR109
1 2
2.2_0603_1%~D
12
1000P_0402_50V7K~D
3
2
VIN2
VCC2
1 2
PC101
0.1U_0603_25V7K~D
PR112
10_0603_1%
PC105
12
1 2
1
GND_T
FSET2
PGOOD2
FB2
VO2
OCSET2
EN2
PHASE2
UGATE2
21
BST_1.8VP
+5VALWP
PC122 1U_0402_6.3V6K~D
12
PR115
22K_0402_1%~D
29
28
27
26
25
24
23
22
PR131
1 2
2.2_0603_5%~D
LG_1.8VP
0_0402_5%~D
1 2
0.01U_0402_25V7K~D@
UG_1.8VP
PR126
PC111
1 2
PR120
1K_0402_1%~D
@
LX_1.8VP
PC120
1 2
0.1U_0402_16V7K~D
12
+5VALWP
SYSON 28,29,36
578
3 6
4
G
3
241
D6D5D7D
S
2
S
PQ30 FDS8884_SO8
8
S
1
FB2_+1.8VP
ISL6228_B+
12
PC112
4.7U_1206_25V6K~D
12
PR130
4.7_1206_5%~D PQ32 FDS6670AS_NL_SO8
12
PC123
1 2
12
PC113
680P_0603_50V8J~D
PR121 34K_0402_1%~D
4.7U_1206_25V6K~D
681_0402_1%~D
1000P_0402_50V7K~D
PR122
PC107
12
1 2
PR123
1 2
68K_0402_1%~D
PR124
1 2
12.1K_0402_1%~D
.01U_0402_16V7K~D
PC114
1 2
PR128
12.1K_0402_1%~D
1 2
PL9
1 2
1.8U_D104C-919AS-1R8N_9.5A_30%
+1.8VP
+1.8VP
1
+
220U_D2_4VM
PC119
2
DCR 7.6m ohm(max)
1.8VP
Imax=6A
Iocp=9A
Fsw=303kHz
PC97
1U_0402_6.3V6K~D
PR108
2.2_0603_1%~D
12
FSET1
12
12
5
VIN1
PU8
+5VALWP +5VALWP
PC100
0.1U_0603_25V7K~D
ISL6228_B+ ISL6228_B+
12
1000P_0402_50V7K~D
8
FB1
9
VO1
10
OCSET1
11
EN1
12
PHASE1
13
UGATE1
14
BOOT1
+5VALWP
PC121
PR111
10_0603_1%
12
PC104
PR114
18K_0402_1%~D
1 2
6
7
PGOOD1
ISL6228HRTZ-T_QFN28_4X4
PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2
1 2
3 6
241
D6D5D7D
G
S
S
S
3
2
PR110
0_0402_5%~D
PR116
90.9K_0402_1%~D
578
PQ29 FDS8884_SO8
PQ31 FDS6670AS_NL_SO8
4
12
PC118
0.1U_0402_16V7K~D
12
PC106
1 2
PR127
4.7_1206_5%~D
SUSP#28,29,33,36,40
12
1 2
PR118
68K_0402_1%~D
ISL6228_B+
12
12
PC109
4.7U_1206_25V6K~D
12
12
PC117
681_0402_1%~D PR117
12
PC110
4.7U_1206_25V6K~D
8
1
680P_0603_50V8J~D
PJP19 JUMP_43X118@
B+
12
C C
+VCCPP
B B
2
112
PC102
470P_0402_50V8J~D
@
1
1
+
+
220U_D2_4VM
PC115
2
2
ISL6228_B+
12
PC103
680P_0402_50K X7R~D
PR119
1 2
12.1K_0402_1%~D
PC108
.01U_0402_16V7K~D
1 2
PR125
12.1K_0402_1%~D
PL8
1 2
1.8U_D104C-919AS-1R8N_9.5A_30%
220U_D2_4VM
PC116
1000P_0402_50V7K~D
1 2
0_0603_5%~D
PR113
1K_0402_1%~D
@
LX_VCCPP
UG_VCCPP
BST_VCCPP
12
PR129
PC99
0.01U_0402_25V7K~D
1 2
@
+5VALWP
DCR 7.6m ohm(max)
+VCCPP
Imax=6A
Iocp=9A
1U_0402_6.3V6K~D
LG_VCCPP
Fsw=366kHz
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/10/1 2007/5/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
VCCPP/1.8VP
Monday, December 15, 2008
KFW11
1
41 45
1.0
of
5
4
3
2
1
www.sp860.com QQ:453100829
D D
+1.8V
1
PJP21
1
JUMP_43X118@
2
2
12
PC128
C C
PR136
0_0402_5%~D
SUSP27,36
1 2
@
0.1U_0402_16V7K~D
PC132
4.7U_0805_6.3V6K~D
13
2
G
12
PQ33
RHU002N06_SOT323-3
D
S
PR134
PR137
12
1K_0402_1%~D
12
PC131
1K_0402_1%~D
12
0.1U_0402_16V7K~D
PU10
VIN1VCNTL
2
GND
3
VREF
4
VOUT
APL5331KAC-TRL_SO8~N
+0.9VSP
12
PC133
10U_0805_6.3V6M~D
6 5
NC
7
NC
8
NC
9
TP
+3VALW
12
PC129
4.7U_0805_6.3V6K~D
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/1 2007/05/30
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Monday, December 15, 2008
2
Date: Sheet
KFW11
+0.9VSP
1
42 45
1.0Custom
of
5
4
3
2
1
12
PC139
+5VS
PR138 1_0603_5%~D
1 2
12
PC143
1U_0603_10V6K~D
0.01U_0402_25V7K~D
786
5
4
5
PQ39
4
+CPU_B+
1
12
12
12
PC140
PC135
PC141
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
PQ34 SI7686DP-T1-E3_SO8
3 5
241
786
5
4
123
786
123
3 5
241 786
5
4
123
12
PQ36 SI4634DY-T1-E3_SO8
PR154
12
PC147
PQ37 SI7686DP-T1-E3_SO8
12
PQ38
SI4634DY-T1-E3_SO8
12
123
4.7_1206_5%~D
680P_0603_50V8J~D
PR164
4.7_1206_5%~D
PC157 680P_0603_50V8J~D
PR155
PC149
10U_1206_25V6M~D
12
VSUM
12
12
PR166
VSUM
3.65K_1206_1%
1
+
+
PC136
2
PR156
3.65K_1206_1%
PC142
2
100U_25V_M
100U_25V_M
PL11 0.36UH_ETQP4LR36WFC_24A_20%
4 3
12
PR158 0_0402_5%~D@
1 2
10K_0402_1%~D
PC148
1 2
ISEN1
0.22U_0603_16V7K~D
12
12
PC152
PC150
10U_1206_25V6M~D
PR167
10K_0402_1%~D
10U_1206_25V6M~D
PL12 0.36UH_ETQP4LR36WFC_24A_20%
4 3
12
PR169 0_0402_5%~D@
1 2
PC160
1 2
0.22U_0603_16V7K~D
ISEN2
PL10
FBMA-L18-453215-900LMA90T_1812
1 2
1 2
12
PR157
1_0402_5%~D
VCC_PRM
+CPU_B+
1 2
12
PR168 1_0402_5%~D
VCC_PRM
B+
+CPU_CORE
Fsw=300kHz
www.sp860.com QQ:453100829
5
5
CPU_VID45CPU_VID3
CPU_VID5
12
12
PR1490_0402_5%~D
PR1420_0402_5%~D
VID4
Vin_CPU
12
VSUM
12
PR179
5
29
CPU_VID25CPU_VID15CPU_VID0
12
12
12
12
PR1460_0402_5%~D
PR1500_0402_5%~D
PR1430_0402_5%~D
VID0
VID1
VID2
VID3
VID037VID138VID239VID340VID441VID542VID6
BOOT1 UGATE1 PHASE1
PGND1
LGATE1
PVCC
LGATE2
PGND2 PHASE2 UGATE2
BOOT2
24
1 2
VDD_CPU
12
PR170 1_0603_5%~D PC159 1U_0603_10V6K~D
PR174
1 2
PC163
10_0603_5%~D
0.1U_0603_25V7K~D
12
PR177
2.61K_0402_1%~D
PH2 10KB_0603_5%_ERTJ1VR103J
11K_0402_1%~D
1 2
PR1440_0402_5%~D
NC
PC134
12
@
D D
DPRSLPVR7,20
H_DPRSTP#5,7,19
CLK_EN#
12
PC144
PR151
1U_0603_10V6K~D
1.91K_0402_1%~D
12
PC165
0.022U_0603_25V7K
@
PR180 1K_0402_1%~D
0.22U_0603_16V7K~D
PR147 0_0402_5%~D
1 2
12
PMON
RBIAS
NTC SOFT OCSET
VW COMP FB_CPU
12
PC164 0.022U_0603_25V7K
1 2
PR178 0_0402_5%~D
1 2
+3VS
+3VS
PR153
499_0402_1%~D
VGATE7,20,29
H_PSI#5
POW_MON
C C
VR_TT#
PR161 4.22K_0402_1%@
B B
A A
VCCSENSE5
1 2
100K_0603_1%_TH11-4H104FT@
1 2
PC154
1000P_0402_50V7K~D
PR171 97.6K_0402_1%~D
PC161 220P_0402_50V7K~D
1 2
PC1461U_0603_10V6K~D
PR160 147K_0402_1%~D
PH1
1 2
PC1510.015U_0402_16V7K@
PR162 11.5K_0402_1%~D
PC156 1000P_0402_50V7K~D
1 2
1 2
PR173
1 2
PR175 1K_0402_1%~D
VSSSENSE5
PR159 10K_0402_1%~D
1 2
1 2
1 2
1 2 1 2
PR165 6.81K_0402_1%~D
1 2
1 2
PC158 470P_0402_50V7K~D
PC162 1000P_0402_50V7K~D
255_0402_1%~D
1 2
1 2
PR176 0_0402_5%~D
VCC_PRM
1 2
PC1530.068U_0603_50V7K~N
12
1 2
5600P_0402_25V7K
PR139 499_0402_1%~D
1 2
PR140 0_0402_5%~D
1 2
PR141 0_0402_5%~D
1 2
3V3_CPU
48
49
3V3
GND
1
PGOOD
2
PSI#
3
PMON
4
RBIAS
5
VR_TT#
6
NTC
7
SOFT
8
OCSET
9
VW
10
COMP
11
FB
12
FB2
VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1
FB2_CPU
VDIFF
PR172 1K_0402_1%~D
1 2
PC167 180P_0402_50V8J~D
1 2
1 2
PR181 3.57K_0402_1%~D
PC169
DPRSTP#_CPU
CLK_EN#_CPU
46
47
CLK_EN#
DPRSTP#
RTN
VSEN_CPU
12
PC166
0.022U_0603_25V7K
12
CPU_VID6
VR_ON
12
12
PR145
0_0402_5%~D
PR1480_0402_5%~D
VID5
VID6
VR_ON_CPU
DPRSLPVR_CPU
45
44
43
VR_ON
DPRSLPVR
ISL6262ACRZ-T_QFN48_7X7
DFB
DROOP
PC168 0.068U_0603_50V7K~N
1 2
PC170 0.22U_0603_10V7K~D
12
36 35 34 33 32 31 30 29 28 27 26 25
PU11
29.1
ISEN1 ISEN2
5
BOOT_CPU1
UGATE_CPU1 PHASE_CPU1
LGATE_CPU1
BOOT_CPU2
2.2_0603_5%~D
+5VS
+CPU_B+
2.2_0603_5%~D
PVCC_CPU
LGATE_CPU2
PHASE_CPU2
PR163
1 2
12
PC138
PC137
1U_0603_10V6K~D
0.01U_0402_25V7K~D
PC145
PR152
1 2
1 2
0.22U_0603_10V7K~D
SI4634DY-T1-E3_SO8
UGATE_CPU2
PC155
1 2
0.22U_0603_10V7K~D
SI4634DY-T1-E3_SO8
12
PQ35
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
+CPU_CORE
KFW11
1.0
43 45Monday, December 15, 2008
1
of
5
4
3
2
1
@
12
1 2
100_0402_5%~D
1 2
100_0402_5%~D
PC177
0.01U_0402_25V7K~D
BATT_IN
PD12
PR186
PR187
BATT+
12
12
12
+3VALWP
2
3
DA204U_SOT323~D
1
BATT_B/I
BATT_SMD
EC_SMB_DA1 29
EC_SMB_CK1 29
PR188 340K_0402_1%~D
PR190
499K_0402_1%~D
PR196
105K_0402_1%~D
PD13
DA204U_SOT323~D
@
BATT_SMC
PR184
1K_0402_5%~D
2
2
3
1
PD14
DA204U_SOT323~D
@
2
3
1
PD15
DA204U_SOT323~D
3
1
@
Battery Connect/OTP
Place clsoe to EC pin
BATT_TEMP
1 2
PR183
1K_0402_5%~D
12
1 2
PR185
6.49K_0402_1%~D
PC175
0.1U_0402_16V7K~D
1 2
@
+3VALWP
BATT_TEMP 29
CPU
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C
VL VS
PC178
1000P_0402_50V7K~D
CPU
12
12
PR189
10.7K_0402_1%~D
PR193
61.9K_0402_1%~D
1 2
1 2
VL
12
PH3 100K_0603_1%_TH11-4H104FT
PR195
150K_0402_1%~D
150K_0402_1%~D
OTP_IN+
PR197
PR191
147K_0402_1%~D
1 2
OTP_IN-
12
12
3 2
PC179 1U_0603_10V6K~D
8
P
+
-
G
PU12A
4
LM358ADR_SO8
PC176
0.1U_0603_25V7K~D
1 2
OTP_OUT
1
0
PD16
1 2
1SS355_SOD323-2
VL
PR192 205K_0402_1%~D
1 2
MAINPWON 39
www.sp860.com QQ:453100829
D D
BATT+
PL13
SMB3025500YA_2P
BATT+
1 2
12
12
PC172
0.01U_0402_25V7K~D
PC171
100P_0402_50V8J~D
PJPB1 battery connector
SMART Battery:
1.BAT+
2.BAT+
C C
B B
3.ID
4.B/I
5.SMC
6.SMD
7.TS
8.GND
9.GND
BATT++
12
PC173 1000P_0402_50V7K~D
PJP22
1 2 3 4 5
@
6 7
10
8
GND
11
9
GND
SUYIN_200275MR009G186ZL
PR194
10K_0402_1%~D
1 2
BATT_OVP29
BATT++
100P_0402_50V8J~D
+3VALWP
1 2
@
PR182 47K_0402_5%~D
PR198
1K_0402_5%~D
12
PC174
1 2 3 4 5 6 7 8 9
VS
12
8
LM358ADR_SO8
5
P
7
PU12B
+
0
6
-
G
4
BATT_OUT
OVP voltage :
LI-3S :13.50V--BATT-OVP=1.5V
A A
5
BATT-OVP=0.111*BATT+
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/1 2007/05/30
Deciphered Date
2
Compal Electronics, Inc.
Title
BATTERY CONN
Size Document Number Rev
Date: Sheet
KFW11
Monday, December 15, 2008
of
1
44 45
1.0Custom
5
4
3
2
1
www.sp860.com QQ:453100829
Version Change List ( P. I. R. List )
Page 1/1
Request
Item Issue DescriptionDate
1
D D
2
3
4
5
6
7
8
9
10
11
12
C C
13
14
15
16
17
18
19
20
21
22
Owner
Solution Description Rev.Page# Title
B B
23
24
25
26
27
28
29
30
31
32
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
PW PIR-1
KFW11
1.0
of
45 45Monday, December 15, 2008
1
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