Dell 1427 KFW11 Schematics
A
B
C
D
E
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A-PDF Watermark DEMO: Purchase from www.A-PDF.com to remove the watermark
1 1
2 2
Compal Confidential
Schematic Document
Cantiga + ICH9
2008 / 12 / 10
3 3
Rev:1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4841P
E
145Monday, December 15, 2008
1.0
of
A
B
C
D
E
Compal confidential
www.sp860.com QQ:453100829
MLK 14
File Name : LA-4841P
ZZZ1
PCB
1 1
CRT
P.17
Thermal Sensor
ADT7421ARMZ
P.4
Fan conn
P.4
LVDS Panel Interface
P.16
2 2
CardBus Controller
MXM II VGA/B
NB9M-GS 512M
P.33
PCI
DMI X4
Penryn -4MB (Socket P)
uFCPGA-478 CPU
P.4,5,6
H_A#(3..35)
H_D#(0..63)
FSB
667/800MHz 1.05V
Intel Cantiga MCH
1329pin BGA
P.7,8,9,10,11,12
C-Link
DDR2 667/800MHz 1.8V
Dual Channel
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
P.13,14
USB conn x 4
CK505
TSSOP-64
Clock Generator
ICS9LPRS397AKLFT
P.15
P.30
O2MICRO OZH24
1394
P.26
Media Card
PCI-E BUS
Intel ICH9-M
676pin BGA
P.18,19,20,21
USB2.0
Azalia
SATA Master
SATA Slave
BT Conn
Camera
P.30
P.30
10/100/1000 LAN
REALTEK
RTL8111C-GR
3 3
P.22
Mini-CardX1
(WLAN)
P.24
Mini-CardX1
P.24
Express Card
P.27
Express Card
Mini-Card-3
P.27
P.23
RJ45/11 CONN
LPC BUS
Audio CODEC
ALC272
P.25 P.25
AMP & Audio Jack
ENE KB926
P.28
Power On/Off CKT.
4 4
DC/DC Interface CKT.
Power Circuit DC/DC
A
RTC CKT.
Power OK CKT.
Touch Pad CONN. Int.KBD
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BIOS(System/EC)
2007/1/15 2008/1/15
C
P.28P.29P.29
Compal Secret Data
Deciphered Date
SATA HDD Connector
P.23
CDROM Conn.
P.23
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Block diagram
LA-4841P
E
of
245Monday, December 15, 2008
1.0
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
O MEANS ON X MEANS OFF
power
plane
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+5VS
+3VS
+1.5VS
+0.9V
+B
O
O
O
O
O
X
+5VALW
+3VALW
O
O
O
O
X
XX X
+1.8V
O
XX
X
+VCCP
+CPU_CORE
+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA
OO
OO
X
X
SMBUS Control Table
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
DEBUG@ : means just reserve for debug.
SOURCE
INVERTER BATT EEPROM
SERIAL SENSOR
THERMAL
(CPU)
SODIMM CLK CHIP
MINI CARD
LCD
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1 ICH9
LCD_CLK
LCD_DAT
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
KB926
KB926
Cantiga
2005/03/10 2006/03/10
X
X
X
XX
Compal Secret Data
Deciphered Date
VV
XX
X
X
XX
XX
V
X
X
X
X
VVV
XX
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
LA-4841P
XX
X
X
X
X
Notes List
V
345Monday, December 15, 2008
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D D
H_A#[3..16]7
H_ADSTB#07
H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
C C
B B
A A
H_A#[17..35]7
H_ADSTB#17
H_A20M#19
H_FERR#19
H_IGNNE#19
H_STPCLK#19
H_INTR19
H_NMI19
H_SMI#19
+VCCP
B
H_PROCHOT# OCP#
H_IERR#
E
3 1
Q2
@
MMBT3904_SOT23
+VCCP
12
@
R17
56_0402_5%
2
C
R18
56_0402_5%
1 2
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
CONN@
JCPU1A
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
Penryn
OCP# 20
ADDR GROUP_0
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
ADDR GROUP_1
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
XDP/ITP SIGNALS
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
THERMTRIP#
H CLK
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
BCLK[0]
BCLK[1]
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
H_THERMDC_R
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
4
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0# 7
H_INIT# 19
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
XDP_DBRESET# 20
R146 56_0402_5%
R57 100_0402_5%
R53 100_0402_5%
H_THERMTRIP# 7,19
CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15
12
1 2
1 2
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
+3VS
1
C13
2
0.1U_0402_16V4Z
+VCCP
H_THERMDAH_THERMDA_R
H_THERMDC
+3VS
C5
1 2
R16
1 2
10K_0402_5%
H_THERMDA
H_THERMDC
2200P_0402_50V7K
L_THERM#
FAN Control circuit
C94
2
EN_DFAN1
+3VS
12
10K_0402_5%
2
1
EN_DFAN129
FAN_SPEED129
0.01U_0402_16V7K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Thermal Sensor EMC1402-1-ACZL-TR
U2
1
VDD
2
3
EMC1402-2-ACZL-TR MSOP 8P
Address:100_1100
R61
SCLK
D+
SDATA
ALERT#
DÂTHERM#4GND
C76
10U_1206_16V4Z~N
C88
1000P_0402_50V7K~N
FAN1_POWER
Title
Size Document Number Rev
Custom
Date: Sheet
No need in check list
XDP_DBRESET#
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
1 2
R51
@
R5 54.9_0402_1%
1 2
R4 54.9_0402_1%
1 2
R11 54.9_0402_1%
1 2
R35 54.9_0402_1%
1 2
This shall place near CPU
EC_SMB_CK2
8
EC_SMB_DA2
7
6
5
12
+5VS
1 2
12
40mil
C77 10U_1206_16V4Z~N
U3
1
VEN
2
VIN
3
VO
4
VSET
RT9027BPS SO 8P
JFAN1
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
CONN@
FAN1
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
LA-4841P
GND
GND
GND
GND
1
+3VS
1K_0402_5%
+VCCP
EC_SMB_CK2 29,33
EC_SMB_DA2 29,33
8
7
6
5
445Monday, December 15, 2008
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H_D#[0..15]7
D D
H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7
C C
R52 1K_0402_5%@
1 2
R22 1K_0402_5%@
1 2
No need in
check list
CPU_BSEL015
CPU_BSEL115
CPU_BSEL215
H_DSTBN#17
H_DSTBP#17
H_DINV#17
T2
T3
T4
T5
T6
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL CPU_BSEL2 CPU_BSEL1
B B
166
200
01
0
1
266 0 0 0
CONN@
JCPU1B
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
Penryn
CPU_BSEL0
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
1
0
DATA GRP 0
DATA GRP 1
MISC
PWRGOOD
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
V_CPU_GTLREF
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
+VCCP
12
R27
1K_0402_1%
12
R29
2K_0402_1%
H_D#[32..47] 7
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
H_DPRSTP# 7,19,43
H_DPSLP# 19
H_DPWR# 7
H_PWRGOOD 19
H_CPUSLP# 7
H_PSI# 43
To IMVP
R23
12
54.9_0402_1%
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4
R24
12
54.9_0402_1%
27.4_0402_1%
R25
12
27.4_0402_1%
For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.
+CPU_CORE +CPU_CORE
R26
12
CONN@
JCPU1C
A7
VCC[001]
VCC[068]
VCC[002]
VCC[069]
VCC[003]
VCC[070]
VCC[004]
VCC[071]
VCC[005]
VCC[072]
VCC[006]
VCC[073]
VCC[007]
VCC[074]
VCC[008]
VCC[075]
VCC[009]
VCC[076]
VCC[010]
VCC[077]
VCC[011]
VCC[078]
VCC[012]
VCC[079]
VCC[013]
VCC[080]
VCC[014]
VCC[081]
VCC[015]
VCC[082]
VCC[016]
VCC[083]
VCC[017]
VCC[084]
VCC[018]
VCC[085]
VCC[019]
VCC[086]
VCC[020]
VCC[087]
VCC[021]
VCC[088]
VCC[022]
VCC[089]
VCC[023]
VCC[090]
VCC[024]
VCC[091]
VCC[025]
VCC[092]
VCC[026]
VCC[093]
VCC[027]
VCC[094]
VCC[028]
VCC[095]
VCC[029]
VCC[096]
VCC[030]
VCC[097]
VCC[031]
VCC[098]
VCC[032]
VCC[099]
VCC[033]
VCC[100]
VCC[034]
VCC[035]
VCCP[01]
VCC[036]
VCCP[02]
VCC[037]
VCCP[03]
VCC[038]
VCCP[04]
VCC[039]
VCCP[05]
VCC[040]
VCCP[06]
VCC[041]
VCCP[07]
VCC[042]
VCCP[08]
VCC[043]
VCCP[09]
VCC[044]
VCCP[10]
VCC[045]
VCCP[11]
VCC[046]
VCCP[12]
VCC[047]
VCCP[13]
VCC[048]
VCCP[14]
VCC[049]
VCCP[15]
VCC[050]
VCCP[16]
VCC[051]
VCC[052]
VCCA[01]
VCC[053]
VCCA[02]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCCSENSE
VCC[065]
VCC[066]
VCC[067]
VSSSENSE
Penryn
For 8 layer condition
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VSSSENSE
AE7
.
Length match within 25 mils.
CPU_VID0 43
CPU_VID1 43
CPU_VID2 43
CPU_VID3 43
CPU_VID4 43
CPU_VID5 43
CPU_VID6 43
VCCSENSE 43
No stuff 27.4 pull down near IMVP for testing
VSSSENSE 43
+VCCP
1
Check 220u?
+
C10
330U_D2E_2.5VM_R7
2
0814 Change to 220uF
0819 Change to C_D2E
1
2
10U_0805_6.3V6M
1
C12
C11
2
0.01U_0402_16V7K
Near pin B26
+1.5VS
The trace width/space/other is
20/7/25.
+CPU_CORE
R28 100_0402_1%
1 2
R30 100_0402_1%
1 2
VCCSENSE
VSSSENSE
Close to CPU pin AD26
within 500mils.
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Close to CPU pin
within 500mils.
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-4841P
1
of
545Monday, December 15, 2008
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
High Frequence Decoupling
10uF 0805 X5R -> 85 degree.
+CPU_CORE
D D
C C
B B
A A
CONN@
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
Place these caps inside
the CPU socket cavity.
( Left side on Top ).
Place these caps inside
the CPU socket cavity.
( Right side on Top side).
Place these caps inside
the CPU socket cavity.
( Left side on Bottom ).
Place these caps inside
the CPU socket cavity.
( Right side on Bottom ).
Place these caps inside
the CPU socket.
+VCCP
1
C213
0.1U_0402_10V6K
2
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
330U_D2E_2.5VM_R9
1
C196
+
2
1
C209
0.1U_0402_10V6K
2
C202
10U_0805_6.3V6M
C162
10U_0805_6.3V6M
C501
10U_0805_6.3V6M
C502
10U_0805_6.3V6M
330U_D2E_2.5VM_R9
1
C198
+
2
1
C197
10U_0805_6.3V6M
2
1
C508
10U_0805_6.3V6M
2
1
C510
10U_0805_6.3V6M
2
C258
1
C212
0.1U_0402_10V6K
2
1
C529
10U_0805_6.3V6M
2
1
C252
10U_0805_6.3V6M
2
1
C514
10U_0805_6.3V6M
2
1
C515
10U_0805_6.3V6M
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
Place these caps inside
1
1
C250
the CPU socket.
+
+
2
( Right side on Top side).( Left side on Top ).
2
1
C185
0.1U_0402_10V6K
2
1
C232
10U_0805_6.3V6M
2
1
C190
10U_0805_6.3V6M
2
1
C519
10U_0805_6.3V6M
2
1
C520
10U_0805_6.3V6M
2
1
C183
0.1U_0402_10V6K
2
1
C255
10U_0805_6.3V6M
2
1
C203
10U_0805_6.3V6M
2
1
C522
10U_0805_6.3V6M
2
1
C526
10U_0805_6.3V6M
2
1
C505
10U_0805_6.3V6M
2
1
C200
10U_0805_6.3V6M
2
1
C533
10U_0805_6.3V6M
2
1
C532
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 880 uF
Place these inside
socket cavity on L8
(North side
Secondary)
1
C184
0.1U_0402_10V6K
2
1
C504
10U_0805_6.3V6M
2
1
C161
10U_0805_6.3V6M
2
1
C254
10U_0805_6.3V6M
2
1
C199
10U_0805_6.3V6M
2
1
C257
10U_0805_6.3V6M
2
1
C208
10U_0805_6.3V6M
2
Place these caps inside
the CPU socket.
1
( Left side on Top ).
C214
10U_0805_6.3V6M
2
Place these caps inside
the CPU socket.
1
( Right side on Top ).
C226
10U_0805_6.3V6M
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
LA-4841P
1
1.0
of
645Monday, December 15, 2008
5
H_D#[0..63]5
D D
C C
H_RESET#4
H_CPUSLP#5
B B
H_RCOMP Dual core 24.9 ohm_1% pull down
Quad core 16.9 ohm_1% pull down
H_SWNG Dual core 100 ohm_1% pull down
Quad core 75 ohm_1% pull down
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R45
1K_0402_1%
A A
12
R46
2K_0402_1%
0.1U_0402_16V4Z
H_SWNG
H_RCOMP
H_RESET#
H_CPUSLP#
H_VREF
H_VREF
1
C391
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
U4A
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3
C12
E11
A11
B11
CANTIGA_1p0
H_RCOMP
12
R324
24.9_0402_1%
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
www.sp860.com QQ:453100829
H_ADSTB#_0
H_ADSTB#_1
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
+VCCP
12
R322
221_0603_1%
100_0402_1%
H_SWNG
12
1
C386
R323
2
0.1U_0402_16V4Z
Near B3 pinwithin 100 mils from NB
5
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
4
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
ICH_PWROK20,29
VGATE20,29,43
H_A#[3..35] 4
SMRCOMP_VOH
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5
H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5
H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
PLT_RST#18,22,24,28,29,33
H_THERMTRIP#4,19
DPRSLPVR20,43
1 2
R408 0_0402_5%
1 2
R407 0_0402_5%@
C398
2.2U_0603_6.3V4Z
C403
2.2U_0603_6.3V4Z
1
1
C400
2
2
1
1
C404
2
2
1 2
R56 0_0402_5%
+1.8V
0.01U_0402_25V7K
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
0913 Delete V_DDR_MCH_REF from POWER circuit
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
V_DDR_MCH_REF13,14
4
V_DDR_MCH_REF
1
2
0.1U_0402_16V4Z
+1.8V
12
12
C121
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R331
1K_0402_1%
12
R332
3.01K_0402_1%
NA lead free
12
R333
1K_0402_1%
R42
1K_0402_1%
R43
1K_0402_1%
3
R82
1 2
10K_0402_5%
R83
1 2
10K_0402_5%
MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215
CFG59
CFG69
CFG79
T37PAD
CFG99
CFG169
CFG199
CFG209
PM_BMBUSY#20
H_DPRSTP#5,19,43
PM_EXTTS#013
PM_EXTTS#114
1 2
R523 100_0402_5%
1
2
3
U4B
@
Compal Secret Data
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
AL34
RSVD10
AK34
RSVD11
AN35
RSVD12
AM35
RSVD13
T24
RSVD14
B31
RSVD15
B2
RSVD16
M1
RSVD17
AY21
RSVD20
BG23
RSVD22
BF23
RSVD23
BH18
RSVD24
BF18
RSVD25
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC_1
BF48
NC_2
BD48
NC_3
BC48
NC_4
BH47
NC_5
BG47
NC_6
BE47
NC_7
BH46
NC_8
BF46
NC_9
BG45
NC_10
BH44
NC_11
BH43
NC_12
BH6
NC_13
BH5
NC_14
BG4
NC_15
BH3
NC_16
BF3
NC_17
BH2
NC_18
BG2
NC_19
BE2
NC_20
BG1
NC_21
BF1
NC_22
BD1
NC_23
BC1
NC_24
F1
NC_25
A47
NC_26
CANTIGA_1p0
Deciphered Date
T7
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T24
T25
T26
T27
T28
T41
T44
T73
T74
+3VS
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T8PAD
T9PAD
CFG5
CFG6
CFG7
CFG9
T65PAD
T40PAD
CFG12
T67PAD
CFG13
T47PAD
T10PAD
T66PAD
CFG16
T68PAD
T39PAD
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
PLT_RST#_NBPLT_RST#
THERMTRIP#
DPRSLPVR
H_DPRSTP#
1
C53
C55
@
10P_0402_50V8J
2
10P_0402_50V8J
2006/02/13 2006/03/10
2
RSVD
CFG
DMI
PM
NC
MISC
2
1
M_CLK_DDR0
AP24
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VID
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
M_CLK_DDR1
AT21
M_CLK_DDR2
AV24
M_CLK_DDR3
AU20
M_CLK_DDR#0
AR24
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#SMRCOMP_VOL
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
SMRCOMP_VOH
BF28
SMRCOMP_VOL
BH28
V_DDR_MCH_REF
AV42
AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_DREFCLK
B38
CLK_MCH_DREFCLK#
A38
MCH_SSCDREFCLK
E41
MCH_SSCDREFCLK#
F41
CLK_MCH_3GPLL
F43
CLK_MCH_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
N28
M28
G36
E36
K36
H36
B12
B28
B30
B29
C29
A28
T30
T31
T32
T33
T34
T35
CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF CL_VREF
CLKREQ#_7
MCH_ICH_SYNC#
TSATN#
T99
T100
T101
T102
T103
0905 Add test point
Title
Cantiga(1/6)-AGTL/DMI/DDR
Size Document Number Rev
Custom
LA-4841P
Date: Sheet
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14
DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14
DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14
M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14
R328 80.6_0402_1%
1 2
R329 80.6_0402_1%
1 2
R39 10K_0402_1%
1 2
R40 499_0402_1%
1 2
T29 PAD
CLK_MCH_DREFCLK 15
CLK_MCH_DREFCLK# 15
MCH_SSCDREFCLK 15
MCH_SSCDREFCLK# 15
CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15
DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20
DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20
DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20
CL_CLK0 20
CL_DATA0 20
M_PWROK 20
CL_RST# 20
0.1U_0402_16V4Z
T36
T48
T63
T64
CLKREQ#_7 15
MCH_ICH_SYNC# 20
TSATN#
R521 56_0402_5%
DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20
C181
12
0814 Add pull up R
Compal Electronics, Inc.
1
1
2
+VCCP
+VCCP
12
12
745Monday, December 15, 2008
+1.8V
R100
1K_0402_1%
R99
511_0402_1%
of
1.0
5
4
3
2
1
www.sp860.com QQ:453100829
D D
DDR_A_D[0..63]13
C C
B B
DDR_A_D0 DDR_B_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
AU10
BA11
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
BB9
BA9
AV9
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AJ9
AJ8
U4D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p0
DDR_A_BS0
BD21
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13
DDR_A_RAS# 13
DDR_A_CAS# 13
DDR_A_WE# 13
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..14] 13
DDR_B_D[0..63]14
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BH12
BF11
BG8
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AH1
AM2
AM3
AH3
AL1
AL2
AJ1
AJ3
U4E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_1p0
DDR_B_BS0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14
DDR_B_RAS# 14
DDR_B_CAS# 14
DDR_B_WE# 14
DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
DDR_B_MA[0..14] 14
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
LA-4841P
1
1.0
of
845Monday, December 15, 2008
5
1 2
1 2
T38
T46
3VDDCCL
3VDDCDA
CRT_HSYNC
CRT_VSYNC
0_0402_5%
BIA_PWM
www.sp860.com QQ:453100829
GMCH_ENBKL
GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD
GMCH_LVDDEN
GMCH_LVDSACÂGMCH_LVDSAC+
GMCH_LVDSA0ÂGMCH_LVDSA1ÂGMCH_LVDSA2ÂGMCH_LVDSA3-
GMCH_LVDSA0+
GMCH_LVDSA1+
GMCH_LVDSA2+
GMCH_LVDSA3+
0_0402_5%
R143
1 2
CRT_B
CRT_G
CRT_R
R74
1 2
R676
VGA@
CTRL_CLK
CTRL_DATA
2.4K for check list
1 2
R94 2.37K_0402_1%~D
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
0_0402_5%
R144
1 2
R76
R75
UMA@
UMA@
1 2
1 2
VGA@
150_0402_1%
0_0402_5%
R675
1 2
150_0402_1%
150_0402_1%
1 2
UMA@
R334
1.02K_0402_1%
UMA@
1 2
BIA_PWM16
GMCH_ENBKL16
+3VS
D D
For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm
R81 10K_0402_5%UMA@
R80 10K_0402_5%UMA@
GMCH_EDID_CLK_LCD16
GMCH_EDID_DAT_LCD16
GMCH_LVDDEN16
GMCH_LVDSAC-16
GMCH_LVDSAC+16
GMCH_LVDSA0-16
GMCH_LVDSA1-16
GMCH_LVDSA2-16
GMCH_LVDSA0+16
GMCH_LVDSA1+16
GMCH_LVDSA2+16
UMA place 75 ohm
0_0402_5%
R142
C C
+3VS
UMA@
R483 2.2K_0402_5%
UMA@
R484 2.2K_0402_5%
B B
R74
0_0402_5%
VGA@
R76
1 2
1 2
GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD
R75
0_0402_5%
VGA@
1 2
CRT_B17
CRT_G17
CRT_R17
3VDDCCL17
3VDDCDA17
CRT_HSYNC17
CRT_VSYNC17
L32
G32
M32
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
B37
A37
H47
E46
G40
A40
H48
D45
F40
B40
A41
H38
G37
J37
B42
G38
F37
K37
F25
H25
K25
H24
C31
E32
E28
G28
J28
G29
H32
J32
J29
E29
L29
4
U4C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CANTIGA_1p0
R56 within 500 mils from
pin T37,T36
T37
PEG_COMPI
T36
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
LVDS
TV
R334
0_0402_5%
VGA@
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
VGA
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
PEG_NRX_GTX_N0
H44
PEG_NRX_GTX_N1
J46
PEG_NRX_GTX_N2
L44
PEG_NRX_GTX_N3
L40
PEG_NRX_GTX_N4
N41
PEG_NRX_GTX_N5
P48
PEG_NRX_GTX_N6
N44
PEG_NRX_GTX_N7
T43
PEG_NRX_GTX_N8
U43
PEG_NRX_GTX_N9
Y43
PEG_NRX_GTX_N10
Y48
PEG_NRX_GTX_N11
Y36
PEG_NRX_GTX_N12
AA43
PEG_NRX_GTX_N13
AD37
PEG_NRX_GTX_N14
AC47
PEG_NRX_GTX_N15
AD39
PEG_NRX_GTX_P0
H43
PEG_NRX_GTX_P1
J44
PEG_NRX_GTX_P2
L43
PEG_NRX_GTX_P3
L41
PEG_NRX_GTX_P4
N40
PEG_NRX_GTX_P5
P47
PEG_NRX_GTX_P6
N43
PEG_NRX_GTX_P7
T42
PEG_NRX_GTX_P8
U42
PEG_NRX_GTX_P9
Y42
PEG_NRX_GTX_P10
W47
PEG_NRX_GTX_P11
Y37
PEG_NRX_GTX_P12
AA42
PEG_NRX_GTX_P13
AD36
PEG_NRX_GTX_P14
AC48
PEG_NRX_GTX_P15
AD40
PEG_TXN0
J41
PEG_TXN1
M46
PEG_TXN2
M47
PEG_TXN3
M40
PEG_TXN4
M42
PEG_TXN5 PEG_NTX_GRX_N5
R48
PEG_TXN6
N38
PEG_TXN7
T40
PEG_TXN8
U37
PEG_TXN9
U40
PEG_TXN10
Y40
AA46
PEG_TXN12
AA37
PEG_TXN13
AA40
PEG_TXN14
AD43
PEG_TXN15
AC46
PEG_TXP0
J42
PEG_TXP1
L46
PEG_TXP2
M48
PEG_TXP3
M39
PEG_TXP4
M43
PEG_TXP5
R47
PEG_TXP6
N37
PEG_TXP7
T39
PEG_TXP8
U36
PEG_TXP9
U39
PEG_TXP10
Y39
PEG_TXP11
Y46
PEG_TXP12
AA36
PEG_TXP13
AA39
PEG_TXP14
AD42
PEG_TXP15
AD46
3
R95
1 2
49.9_0402_1%
C568 0.1U_0402_16V7KVGA@
1 2
C537 0.1U_0402_16V7KVGA@
1 2
C538 0.1U_0402_16V7KVGA@
1 2
C539 0.1U_0402_16V7KVGA@
1 2
C540 0.1U_0402_16V7KVGA@
1 2
C541 0.1U_0402_16V7KVGA@
1 2
C542 0.1U_0402_16V7KVGA@
1 2
C543 0.1U_0402_16V7KVGA@
1 2
C544 0.1U_0402_16V7KVGA@
1 2
C545 0.1U_0402_16V7KVGA@
1 2
C546 0.1U_0402_16V7KVGA@
1 2
C547 0.1U_0402_16V7KVGA@
1 2
C548 0.1U_0402_16V7KVGA@
1 2
C549 0.1U_0402_16V7KVGA@
1 2
C550 0.1U_0402_16V7KVGA@
1 2
C551 0.1U_0402_16V7KVGA@
1 2
C552 0.1U_0402_16V7KVGA@
1 2
C553 0.1U_0402_16V7KVGA@
1 2
C554 0.1U_0402_16V7KVGA@
1 2
C555 0.1U_0402_16V7KVGA@
1 2
C556 0.1U_0402_16V7KVGA@
1 2
C557 0.1U_0402_16V7KVGA@
1 2
C558 0.1U_0402_16V7KVGA@
1 2
C559 0.1U_0402_16V7KVGA@
1 2
C560 0.1U_0402_16V7KVGA@
1 2
C561 0.1U_0402_16V7KVGA@
1 2
C562 0.1U_0402_16V7KVGA@
1 2
C563 0.1U_0402_16V7KVGA@
1 2
C564 0.1U_0402_16V7KVGA@
1 2
C565 0.1U_0402_16V7KVGA@
1 2
C566 0.1U_0402_16V7KVGA@
1 2
C567 0.1U_0402_16V7KVGA@
1 2
+VCC_PEG
PEG_NRX_GTX_N[0..15]
PEG_NRX_GTX_P[0..15]
PEGCOMP trace width
and spacing is 20/25 mils.
PEG_NRX_GTX_N[0..15] 33
PEG_NRX_GTX_P[0..15] 33
PEG_NTX_GRX_N[0..15] 33
PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4
PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
PEG_NTX_GRX_N11PEG_TXN11
PEG_NTX_GRX_N12
PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15
PEG_NTX_GRX_P0
PEG_NTX_GRX_P1
PEG_NTX_GRX_P2
PEG_NTX_GRX_P3
PEG_NTX_GRX_P4
PEG_NTX_GRX_P5
PEG_NTX_GRX_P6
PEG_NTX_GRX_P7
PEG_NTX_GRX_P8
PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15
PEG_NTX_GRX_P[0..15] 33
2
1
Strap Pin Table
CFG[2:0] FSB Freq select
CFG[4:3] Reserved
CFG5 (DMI select)
CFG6
CFG6
CFG7 (Intel Management
Engine Crypto strap)
CFG8
CFG9
(PCIE Graphics Lane Reversal)
CFG10 (PCIE Lookback enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
CFG57
CFG67
CFG77
CFG97
CFG167
CFG197
CFG207
CFG[19:20] have internal pulldown
000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
*
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order
0 = Enable
1 = Disable
*
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
ReservedCFG[15:14]
0 = Disabled
1 = Enabled
*
ReservedCFG[18:17]
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
R66 2.21K_0402_1%~D@
1 2
R58 2.21K_0402_1%~D@
1 2
R59 2.21K_0402_1%~D@
1 2
R55 2.21K_0402_1%~D@
1 2
R70 2.21K_0402_1%~D@
1 2
CFG[5:16] have internal pullup
R72 2.21K_0402_1%~D@
R73 2.21K_0402_1%~D@
1 2
1 2
+3VS
*
*
*
(Default)11 = Normal Operation
*
*
*
0_0402_5%
VGA@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Custom
LA-4841P
2
Date: Sheet
1
945Monday, December 15, 2008
1.0
of
5
+3VS_DAC_CRT
C407
UMA@
D D
+3VS_DAC_BG
C405
UMA@
C C
+3VS_DAC_CRT
0.01U_0402_25V7K~N
C401
1
UMA@
2
B B
L11
1 2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
0.01U_0402_25V7K~N
C411
1
1
UMA@
2
2
R836 0_0402_5%~D
0.1U_0402_16V4Z
0.01U_0402_25V7K~N
C408
1
1
UMA@
2
2
R97
1 2
+1.5VS
0_0603_5%
+VCCP
R71
1 2
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
C402
1
UMA@
2
UMA@
1 2
UMA@
220U_D2_4VY_R15M
1
+
C68
2
C103
+3VS
+3VS_DAC_CRT
1
C175
0.1U_0402_16V4Z
2
R50
1 2
0_0805_5%
C82
1
2
+1.05VS_A_SM_CK
C104
1
1
2
2
HDMI disable connected to GND
www.sp860.com QQ:453100829
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
+1.8V_TXLVDS
+1.5VS_PEG_BG
10U_0805_10V4Z
C83
4.7U_0805_10V4Z
10U_0805_10V4Z
C122
1
2
+1.05VS_PEGPLL
+1.05VS_A_SM
1
2
1U_0603_10V4Z
C123
1
2
+3VS_DAC_CRT
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_HPLL
+1.05VS_PEGPLL
+1.8V_LVDS
1
C413
UMA@
1000P_0402_50V7K
2
1
C72
2
1U_0603_10V4Z
0.1U_0402_16V4Z
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
60.31mA
58.67mA
48.363mA
157.2mA
4
U4H
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
DMI
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
VTTLF
73mA
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
64.8mA
F47
64.8mA
139.2mA
13.2mA
720mA
50mA
VCCA_DPLLA
L48
VCCA_DPLLB
24mA
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
26mA 321.35mA
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
CRTPLLA PEGA SM
A LVDS
POWER
A CK
TV
HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
AA47
M38
L37
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
D TV/CRT
50mA
LVDS
CANTIGA_1p0
852mA
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
124mA
BF21
BH20
BG20
BF20
118.8mA
K47
C35
B35
A35
1732mA
V48
U48
V47
U47
U46
456mA
AH48
AF48
AH47
AG47
20mils
A8
L1
AB2
C382
3
+VCCP
+V1.05VS_AXF
+1.8V_SM_CK
105.3mA
0.47U_0603_10V7K
C385
1
2
220U_D2_4VY_R15M
1
+
C370
2
0.47U_0603_10V7K
1
C383
2
+1.8V_TXLVDS
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
0.47U_0603_10V7K
C65
1
2
C373
+3VS_HV
1
2
C384
1
2
C410
4.7U_0805_10V4Z
1
2
4.7U_0805_10V4Z
C56
0.1U_0402_16V4Z
1
2
2.2U_0805_16V4Z
1
2
+1.5VS_QDAC
C97
1
2
+1.05VS_DPLLA
220U_D2_4VY_R15M
1
C191
2
UMA@
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.01U_0402_25V7K~N
C98
1
2
C173
+
UMA@
C174
C178
UMA@
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
10U_0805_10V4Z
C182
1
1
2
2
UMA@
L14
1 2
10U_FLC-453232-100K_0.25A_10%
10U_0805_10V4Z
1
UMA@
UMA@
2
+1.05VS_HPLL
0.1U_0402_16V4Z
C388
C387
1
2
+1.05VS_MPLL
1
C63
2
+1.05VS_PEGPLL
0.1U_0402_16V4Z
C176
1
2
R69
1 2
100_0603_1%
+VCCP
1 2
L13
10U_FLC-453232-100K_0.25A_10%
UMA@
+VCCP+1.05VS_DPLLB
L29
1 2
MBK2012121YZF_0805
10U_0805_10V4Z
1
2
L9
1 2
MBK2012121YZF_0805
1
C62
10U_0805_10V4Z
2
2 1
+3VS
+VCCP
D3
@
CH751H-40PT_SOD323-2
L12
1 2
BLM18PG121SN1D_0603
10U_0805_10V4Z
C179
1
2
+1.5VS
+VCCP
+VCCP
+VCCP
+VCCP_D
1
C204
2
@
1 2
10_0402_5%
10U_0805_10V4Z
1
@
C87
2
+1.5VS_TVDAC
1
2
10U_0805_10V4Z
R113
+V1.05VS_AXF
10U_0805_10V4Z
1
2
+1.8V_SM_CK
C96
1
2
UMA@
1
C115
2
+VCC_PEG
1
+
C95
2
+1.05VS_DMI
1
C66
2
10U_0805_10V4Z
R114
1 2
0_0402_5%
1
C113
10U_0805_10V4Z
UMA@
0.022U_0402_16V7K
C114
220U_D2_4VY_R15M
C117
R112
1 2
0_0603_5%
0.1U_0402_16V4Z
C116
1U_0603_10V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
2
1
R101
1 2
0_0603_5%
C69
R102
1 2
0_0805_5%
C102
R64
1 2
0_0805_5% UMA@
R109
1 2
0_0805_5%
+VCC_PEG
+3VS_HV
+VCCP
+1.8V
+1.5VS
+VCCP
UMA@
2
+1.8V_LVDS
10U_0805_10V4Z
1
2
C187
UMA@
R110
UMA@
1
2
1 2
0_0603_5%
C186
1U_0603_10V4Z
+1.8V
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Cantiga(4/6)-PWR
LA-4841P
C401
0_0402_5%
VGA@
A A
5
C405
0_0402_5%
VGA@
C407
0_0402_5%
VGA@
C413
0_0402_5%
VGA@
C173
0_0402_5%
VGA@
C174
0_0402_5%
VGA@
C115
0_0402_5%
VGA@
U4
CRESTLINE_1p0
VGA@
C186
0_0603_5%
VGA@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
40 mils
1000P_0402_50V7K
+1.8V_TXLVDS
C414
1
2
UMA@
R350
1 2
0_0603_5%
10U_0805_10V4Z
C418
1
2
UMA@
1
10 45Monday, December 15, 2008
UMA@
+1.8V
1.0
of
5
4
3
2
1
www.sp860.com QQ:453100829
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
+1.8V
1
1U_0603_10V4Z VGA@
C78
2
330U_V_2.5VM
C148
330U_V_2.5VM
1
+
2
10U_0805_10V4Z
1
C165
1
+
2
2
0317 change value
10U_0805_10V4Z
1
C100
C57
VGA@
VGA@
2
10U_0805_10V4Z
0.01U_0402_16V7K
10U_0805_10V4Z
C147
1
2
+VCCP
0.1U_0402_16V4Z
1
C79
VGA@
2
T42PAD
T43PAD
1
2
2
1
C80
VGA@
C164
AG34
AC34
AB34
AA34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
W33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
Y34
V34
U34
Y33
V33
U33
T32
U4F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_1p0
VCC CORE
POWER
VCC NCTF
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
+VCCP
+VCCP
D D
0.22U_0402_10V4Z
10U_0805_10V4Z
220U_D2_4VY_R15M
1
C118
1
+
C374
2
2
C C
B B
0.1U_0402_16V4Z
0.22U_0402_10V4Z
C143
1
2
C120
C119
1
1
2
2
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
U4G
3000mA
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
6326.84mA
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
POWER
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC SMVCC GFX
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC GFX NCTF
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+VCCP
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
0.1U_0402_16V4Z
1
C99
VGA@
2
0.22U_0402_10V4Z
C70 0.1U_0402_16V4Z
1
2
4.7U_0603_6.3V6M
1
1
C86
VGA@
2
C67 0.22U_0603_10V7K
C71 0.1U_0402_16V4Z
1
1
2
2
C101
VGA@
2
C163 1U_0603_10V4Z
C145 1U_0603_10V4Z
C81 0.22U_0603_10V7K
C146 0.47U_0402_6.3V6K
1
1
1
1
2
2
2
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
CANTIGA_1p0
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
LA-4841P
1
1.0
of
11 45Monday, December 15, 2008
5
4
3
2
1
www.sp860.com QQ:453100829
U4I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
D D
C C
B B
A A
AD47
AB47
BD46
BA46
AY46
AV46
AR46
AM46
BF44
AH44
AD44
AA44
BC43
AV43
AU43
AM43
BG42
AY42
AT42
AN42
AJ42
AE42
BD41
AU41
AM41
AH41
AD41
AA41
BG40
BB40
AV40
AN40
AT39
AM39
AJ39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AW37
AT37
AN37
AJ37
BG36
BD36
AK15
AU36
N47
G47
R46
H46
U44
M44
C43
N42
U41
M41
G41
H40
N39
U38
C38
H37
C37
Y47
T47
L47
V46
P46
F46
Y44
T44
F44
J43
L42
Y41
T41
B41
E40
L39
B39
Y38
T38
J38
F38
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
AW21
AU21
AP21
AN21
AH21
AF21
AB21
BC20
BA20
AW20
AT20
AJ20
AG20
BG19
BG17
BC17
AW17
AT17
BA16
AU16
AN16
BG15
AC15
W15
BG14
AA14
BG13
BC13
BA13
AN13
AJ13
AE13
BF12
AV12
AT12
AM12
AA12
BD11
BB11
AY11
AN11
AH11
BG10
AV10
AT10
AJ10
AE10
AA10
AM9
L12
R21
M21
G21
Y20
N20
K20
F20
C20
A20
A18
R17
M17
H17
C17
N16
K16
G16
E16
A15
C14
N13
L13
G13
E13
A12
Y11
N11
G11
C11
M10
BF9
BC9
AN9
AD9
BH8
BB8
AV8
AT8
J21
J12
G9
B9
U4J
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
CANTIGA_1p0
VSS
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS NCTF
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS SCB
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
LA-4841P
1
1.0
of
12 45Monday, December 15, 2008
5
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8
D D
Layout Note:
Place near JDIM1
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C C
B B
A A
C124
C105
1
1
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C106
C125
DDR_A_MA5
DDR_A_MA8
DDR_A_MA1
DDR_A_MA3
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_BS#0
DDR_A_MA10
DDR_A_CAS#
DDR_A_WE#
DDR_CS1_DIMMA#
M_ODT1
DDR_CKE1_DIMMA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C149
1
2
DDR_A_V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C126
RP14
1 4
2 3
RP13
56_0404_4P2R_5%
1 4
2 3
RP7
56_0404_4P2R_5%
1 4
2 3
RP6
56_0404_4P2R_5%
1 4
2 3
RP5
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
RP1
2 3
1 4
56_0404_4P2R_5%
1 2
R96 56_0402_5%
5
1
2
C127
C166
1
2
0.1U_0402_16V4Z
DDR_A_V
1
2
C150
www.sp860.com QQ:453100829
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C169
C154
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C167
C151
RP22 56_0404_4P2R_5%
DDR_CKE0_DIMMA
14
DDR_A_MA12
23
RP17 56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
RP15 56_0404_4P2R_5%
DDR_A_MA9
14
DDR_A_BS#2
23
RP16 56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
RP8 56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS#1
23
RP2 56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
RP23 56_0404_4P2R_5%
DDR_A_MA14
14
DDR_A_MA11
23
0.1U_0402_16V4Z
C131
C130
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C128
C107
4
0.1U_0402_16V4Z
330U 2.5V Y D2
C108
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C152
C129
Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"
4
3
+1.8V
JDIM2
1
VREF
3
DDR_A_D4
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D14
DDR_A_D16
DDR_A_D17
+3VS
C58
0.1U_0402_16V4Z
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D34
DDR_A_D40
DDR_A_D44
DDR_A_DM5
DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D58
CLK_SMBDATA
CLK_SMBCLK
1
1
2
2
C59
2.2U_0603_6.3V6K
1
C84
+
@
2
DDR_CKE0_DIMMA7
DDR_A_BS#28
DDR_A_BS#08
DDR_A_WE#8
DDR_A_CAS#8
0.1U_0402_16V4Z
1
1
2
2
C153
C168
DDR_CS1_DIMMA#7
M_ODT17
ICH_SM_DA14,15,20,24
ICH_SM_CLK14,15,20,24
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
SO-DIMM A
REVERSE
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
DDR_A_D5
DDR_A_D0
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D11
DDR_A_D10DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7DDR_A_MA9
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#
M_ODT0
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DM4
DDR_A_D39
DDR_A_D38
DDR_A_D45
DDR_A_D47
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
12
R32
R31
10K_0402_5%
10K_0402_5%
Close to VREF pins of SO-DIMM
2.2U_0805_16V4Z
C201
1
2
M_CLK_DDR0 7
M_CLK_DDR#0 7
PM_EXTTS#0 7
DDR_CKE1_DIMMA 7
DDR_A_MA14 8
DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7
M_ODT0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
12
1
0.1U_0402_16V4Z
C220
1
2
V_DDR_MCH_REF 7,14
Bottom side
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
DDR2 SO-DIMM I
LA-4841P
1.0
of
13 45Monday, December 15, 2008
1
5
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..13]8
D D
Layout Note:
Place near JDIM2
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C112
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
C C
+0.9VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C134
C110
B B
A A
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA0
DDR_B_BS#1
DDR_CS2_DIMMB#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
M_ODT3
DDR_CS3_DIMMB#
DDR_CKE3_DIMMB
C160
C139
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C135
RP18
1 4
2 3
RP10
56_0404_4P2R_5%
1 4
2 3
RP12
56_0404_4P2R_5%
1 4
2 3
RP11
56_0404_4P2R_5%
1 4
2 3
RP9
56_0404_4P2R_5%
1 4
2 3
RP3
56_0404_4P2R_5%
2 3
1 4
56_0404_4P2R_5%
1 2
R335 56_0402_5%
5
1
2
C156
www.sp860.com QQ:453100829
0.1U_0402_16V4Z
C109
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C171
DDR_B_MA12
DDR_B_MA9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA13
M_ODT2
DDR_B_BS#2
DDR_CKE2_DIMMB
0.1U_0402_16V4Z
C111
0.1U_0402_16V4Z
C132
1
2
0.1U_0402_16V4Z
1
2
C136
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C138
1
2
DDR_B_V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C157
DDR_B_V
RP24 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP20 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP25
56_0404_4P2R_5%
C177
1
2
1
2
C170
14
23
14
23
14
23
14
23
14
23
14
23
14
23
0.1U_0402_16V4Z
C133
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C158
Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"
4
1
2
1
2
4
C137
C155
3
+1.8V
JDIM1
1
VREF
3
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
330U 2.5V Y D2
1
C189
+
@
2
DDR_CKE2_DIMMB7
DDR_B_BS#28
DDR_B_BS#08
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C159
C172
DDR_B_CAS#8
DDR_CS3_DIMMB#7
M_ODT37
ICH_SM_DA13,15,20,24
ICH_SM_CLK13,15,20,24
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_B_D17
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58
CLK_SMBDATA
CLK_SMBCLK
+3VS
1
2
1
C60
2.2U_0603_6.3V6K
2
C61
0.1U_0402_16V4Z
2007/1/15 2008/1/15
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692A-A0G16-N
SO-DIMM B
REVERSE
Bottom side
Compal Secret Data
Deciphered Date
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
NC
A11
A7
A6
A4
A2
A0
BA1
S0#
NC
SA1
2
1
Close to VREF pins of SO-DIMM
+DDR_MCH_REF1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D5
DDR_B_D4
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D14
DDR_B_D15
DDR_B_D21
DDR_B_D16
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_CKE3_DIMMB
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
10K_0402_5%
2
12
R34
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
1
C221
C222
2
2
M_CLK_DDR2 7
M_CLK_DDR#2 7
PM_EXTTS#1 7
DDR_CKE3_DIMMB 7
DDR_B_MA14 8
DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7DDR_B_WE#8
M_ODT2 7
M_CLK_DDR3 7
M_CLK_DDR#3 7
R33
1 2
10K_0402_5%
Title
Size Document Number Rev
Custom
Date: Sheet
+3VS
Compal Electronics, Inc.
DDR2 SO-DIMM II
LA-4841P
V_DDR_MCH_REF 7,13
of
14 45Monday, December 15, 2008
1
1.0
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