Dell 1420 LANAI DIS Schematic

A

ASUS CONFIDENTIAL

B

C

D

E

MODEL NAME :

1 1

PCB NO :

???

ASUS P/N :

2 2

Elsa

???

Lanai Discrete VGA nVidia NB8M Schematics Document

uFCPGA Mobile Merom

Intel Crestline-PM + ICH8M

3 3

2007-03-19

REV : 1.2(DELL: X02)

4 4

<Variant Name>

MB PCB

Part Number Description

PCB 00B LA-3071P REV0 M/B

DA800004H0L

PROJECT:

BOM NO. ???
PCB P/N: ???

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

1 69

B

DESCRIPTION:

Cover Page

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

5 5

5

4

3

2

1

LANAI: DISCRETE

POWER

D D

POWER
CON.

Panel Connector

PG 28

C C

IO Board

CRT CONN.

TV CONN.

USB CONN.x2

MINI-CARD

WLAN

MINI-CARD

WWAN

B B

SIM
CARD

PCIEx1 (Lane2)

SIM CARD Board

S/PDIF

TO TV
CONN.

PG 30

A A

<Variant Name>

DIGITAL
MIC.

PG 28

PROJECT:

5

POWER SEQUENCE
LOGIC

POWER
CHARGER

POWER CONTROL
SWITCH

DISCHARGE PATH

+3.3V_SUS/+5V_SUS/+3.3V_RUN
+5V/+3.3V/+1.8V/+1.25_RUN

LVDS

VGA

TVOUT

USB2.0(P2,3)

USB2.0(P9)

AUDIO/AMP

PG 44,45,46

Speaker
CON

PG 46

WtoB
CON

PG 46

Audio
Jacks
*3

JACK Board

Lanai

REVISION

PG 51

PG 57

PG 49PG 59

PG 49

nVIDIA G86M

PCI EXPRESS GFX

PG 22,23,24,25,26,27

VGA

TVOUT

D.B
CON

PG 50

MDC

PG 36

RJ11

RJ11 Board

1.2

USB2.0(P2,3)

PCIEx1 (Lane2)

USB2.0(P9)

Monday, March 19, 2007

DATE:
SHEET OF

4

XDP

PG 52

PCIEx16

IHDA

CIR

PG 41

2 69

Merom

(478 Micro-FCPGA)

PG 7,8

(Symbol Rev.09)

Crestline

1299 uFCBGA

PG 9,10,11,12,13,14

(Symbol Rev.09)

DMI INTERFACE

ICH8-M

676 BGA

PG 15,16,17,18

(Symbol Rev.09)

SPI

LPC

SIO

MEC5025
128KB Flash
TMKBC

128 Pins VTQFP

PG 37

SPI

FLASH

PG 40

DESCRIPTION:

Touchpad
CON.

BLOCK DIAGRAM

PS/2

PG 41

ECE5011
Expander

BC

USB 2.0 Hub(4)

128 Pins VTQFP

FAN &THERMAL

3

USB2.0(P0,P1)

PCIE (Lane6)

PCI

PCIE (Lane4)
USB2.0(P6)
USB2.0(P7)

USB2.0(P5)

SATA

SATA-HDD

IDE

SIO

PG 38

EMC4001

PG 43

POWER

POWER I/O

+1.5V_RUN/+1.05V_VCCP

REGULATOR

+VCC_GFX_CORE/+1.25V_RUN

533/667 MHZ DDR II

533/667 MHZ DDR II

CAMERA

PG 28

PG 31

CD-ROM

PG 31

USER
INTERFACE

PG 42

RELEASE DATE :

PG 55

PG 58

USB CONN.

PG 39

USB Board

CARD READER
1394/R5C833

EXPRESS-CARD
R5538

Bluetooth

PG 41

SNIFFER

PG 42

2

POWER VCORE

POWER SYSTEM

5V_ALW & 3.3V_ALW

REGULATOR

+1.8V_SUS/+0.9V_DDR_VTT

DDR2-SODIMM1

PG 19

DDR2-SODIMM2

PG 19

PG 32,33,34

PG 35

CAPBTN
CON.

PG 40

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

PG 53

PG 54

PG 56

BCM5906KMLG

QFN-68

RJ45/Magnetic

PG 48

CLOCK

CK410M+LP

PG 21

PG 47

1

A

B

C

D

E

INDEX

Pg# Description DNI LIST

01

1 1

02

03

04

05

06

07-08

09-14

15-18

2 2

19-20

21

22-27

28

29

30

31

32-34

35

3 3

36

37

38

39

40

41

42

43

44-46

4 4

47

48

49

50

51

52

53-59

60

5 5

61 Change list (1)

Cover Page

Schematic Block Diagram

INDEX

Bus connection

SMBUS BLOCK

Power Rail

CPU ( Merom 、 Penryn )

Crestline

ICH8M

DDRII SO-DIMM( 533MHz 667MHz )

、

Clock Generator ( CK410M+LP )

VGA ( nVIADA - G86M & GDDR3)

LVDS CON & Camera & DMIC

RGB CON

TV OUT CON

SATA(HDD & CD_ROM)

MEDIA CARD READER / 1394 ( R5C833 )

PCI-Express Card

MDC CONN

EC ( MEC5025 )

SIO ( ECE5011 )

USB PORT x 2

FLASH & RTC & CAPBTN CONN

TOUCH PAD & BT & CIR & LID

SWITCH & LED

HARDWARE MONITOR ( EMC4001 )

AUDIO CODEC & AMP

LOM BCM5906

Magnetics and RJ-45

Power Control Switch

BtoB CON

Power Sequence Logic

XDP

Power Circuit

SCREW PAD

64

R01

R02

R03

U01

Power circuit Change list

Modem board cover page

RJ-11 CONN

Modem board Change list

USB board cover page

U02 USB PORT ( SINGLE * 2 )

Description DNI LISTPg#

Change list (2)62

<Variant Name>

63 Change list (3)

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

3 69

B

DESCRIPTION:

INDEX

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

A

B

C

D

E

Footprint Definition

Footprint is 0402 if there is no descriptionResistor

1 1

Capacitor Footprint is 0402 if there is no description

Ferrite Bead

Footprint is 0603 if there is no description

PCI
DEVICE

R5C833

PCI TABLE

IDSEL REQ#/GNT# PIRQ

PCI_AD17

PCI_REQ1#
PCI_GNT1#

PCI_PIRQC#
PCI_PIRQD#

Layout Note

For all of ESD diode, they should be placed as close as
possible to connectors and the signals from connectors
should be routed to ESD diodes first. There is no branch
or via before diodes

Lane 2

2 2

Lane 3

Lane 4

PCI Express TABLE

WWAN / Mini CardLane 1

WLAN / Mini Card

ExpressCard

Lane 5

Lane 6

LAN BCM5906KMLG

USB TABLE

3 3

4 4

5 5

ICH8-0
(EHCI#1)

ICH8-1
(EHCI#1)

ICH8-2
(EHCI#1)

ICH8-3
(EHCI#1)

ICH8-4
(EHCI#1)

ICH8-5
(EHCI#1)

ICH8-6
(EHCI#2)

ICH8-7
(EHCI#2)

ICH8-8
(EHCI#2)

ICH8-9
(EHCI#2)

User1
(Single port , in USB BD)

User2
(Single port , in USB BD)

User3
(Dual port-bottom , in I/O BD)

User4
(Dual port-top , in I/O BD)

Camera

ExpressCard

BT Module

WWAN / Mini Card

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

B

4 69

DESCRIPTION:

Bus Connection

C

RELEASE DATE :

D

Note : No USB for WLAN

<OrgName>

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

5

4

+3.3V_SUS

3

+3.3V_SUS

+3.3V_RUN

2

1

MEM_SCLK 197

10K 10K

2.2K2.2K

ICH8-M

D D

AD19 ICH_SMBDATA

AC17 AMT_SMBCLK
AE19 AMT_SMBDAT

+5V_MEDIA

8.2K8.2K

2.2K 2.2K

+3.3V_RUN

7002
7002

MEM_SDATA 195

MEM_SCLK 197AJ26 ICH_SMBCLK
MEM_SDATA 195

7

Express Card WWAN

8

I/O Board

30
32

DIMM 0

DIMM 1

30
32

WLAN

6 DOCK_SMBCLK
5 DOCK_SMBDAT

+3.3V_ALW

CAPBTN Board

+3.3V_RUN

C C

2.2K

13 CKG_SMBCLK
12 CKG_SMBDAT

+3.3V_ALW

4.7K

2.2K
+3.3V_RUN

7002
7002

4.7K

2.2K

100 THRM_SMBCLK
99 THRM_SMBDAT

SIO

B B

MEC5025

+3.3V_ALW

2.2K

2.2K

+3.3V_ALW

112 PBAT_SMBCLK
111 PBAT_SMBDAT

+3.3V_ALW

8.2K

8.2K

+3.3V_ALW

8 LCD_SMBCLK
7 LCD_SMDDAT

+3.3V_RUN

2.2K2.2K

A A

+3.3V_ALW

2.2K

100

100

47pF

CLK_SCLK 16
CLK_SDATA 17

12
11

10
9

SMB_CLK 3
SMB_DAT 4

34
35

47pF

ECE4001

CHARGER

Battery
CONN.

LVDS
Connector

CLK GEN.

LCD_DDCCLK 43

VGA

LCD_DDCDAT

+3.3V_RUN

44

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

5 69

4

DESCRIPTION:

SMBUS BLOCK

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

A

B

C

OPTIONAL

D

E

ADAPTER

1 1

+PWR_SRC

BATTERY

2 2

TPS51120

ALWON

ALWON

THERM_STP#

3 3

+5V_
ALW2

+3.3V_RTC
_LDO

THERM_STP#

+5V_ALW

+RTC_CELL

SN0508073

ALWON

+3.3V_ALW

1.25V_RUN_ON

GFX_RUN_ON
RUN_ON

THERM_STP#

+1.25V_RUN

+VCC_GFX_CORE

ISL6260C
ISL6208

RUNPWROK

IMVP_VR_ON

+VCC_CORE

SN0508073

1.5V_RUN_ON

+1.5V_RUN

GFX_CORE_PWRGD

FDS8880

1.05_RUN_ON

+1.05V_VCCP

+1.25V_GFX_PCIE

TPS51116

DDR_ON

+1.8V_SUS

0.9V_DDR_VTT_ON

+0.9V_DDR_VTT

FDC653N

RUN_ON

4 4

5 5

<Variant Name>

PROJECT:

+5V_RUN

Lanai

A

BAT54S

+15V_ALW

REVISION

1.2

SI4800BDY

Monday, March 19, 2007

DATE:
SHEET OF

6 69

B

EE
SIDE

SUS_ON

FDS6612A

3.3V_RUN_ON

+3.3V_RUN+5V_SUS

EMC4001

+2.5V_RUN

DESCRIPTION:

SI4800BDY

3.3V_SUS_ON

+3.3V_SUS

Power Rail

C

RELEASE DATE :

FDS6612A

1.8V_RUN_ON

+1.8V_RUN

DESIGN ENGINEER :SCHEMATIC FILE NAME :

D

Eric_Ko

E

5

H_A#[3..16]9

D D

C C

B B

H_ADSTB#09

H_REQ#[0..4]9

H_A#[17..35]9

H_ADSTB#19

H_A20M#15

H_FERR#15

H_IGNNE#15
H_STPCLK#15

H_INTR15
H_NMI15
H_SMI#15

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

U24A

MOLEX/47387-4781

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD10

SOCKET478

ADDR GROUP

0

ADDR GROUP

1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS0#
RS1#
RS2#

TRDY#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#

PREQ#

TRST#

DBR#

BCLK0
BCLK1

HIT#

TCK
TDO

TMS

TDI

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

4

H_IERR#

12

R196 56Ohm 5%

H_RESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

12

R197 56Ohm 5%

CPU_PROCHOT#

H_THERMDA
H_THERMDC

H_THERMTRIP#

12

R474 56Ohm 5%

C642 2200PF/50V MLCC/+/-10% /*

XDP_BPM#0 52
XDP_BPM#1 52
XDP_BPM#2 52

XDP_BPM#3 52
XDP_BPM#4 52
XDP_BPM#5 52
XDP_TCK 52
XDP_TDI 52
XDP_TDO 52
XDP_TMS 52
XDP_TRST# 52
XDP_DBRESET# 17,38,52

H_THERMDCH_THERMDA

12

Voltage Level Shift

H_ADS# 9
H_BNR# 9

H_BPRI# 9
H_DEFER# 9

H_DRDY# 9
H_DBSY# 9
H_BR0# 9

H_INIT# 15

H_LOCK# 9

H_RESET# 9,52
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9

H_HIT# 9
H_HITM# 9

+1.05V_VCCP

+1.05V_VCCP

CLK_CPU_BCLK 21
CLK_CPU_BCLK# 21

+1.05V_VCCP +3.3V_ALW

+1.05V_VCCP

H_THERMDA 43
H_THERMDC 43

H_THERMTRIP# 43

3

H_DSTBN#09
H_DSTBP#09
H_DINV#09

H_D#[0..63]9 H_D#[0..63] 9

Layout note:
Place voltage
divider within

0.5" of GTLREF
pin

+1.05V_VCCP

R201
1KOhm

1%

12

R202
2KOhm

1%

12

R503 1KOhm /*1%
R500 1KOhm /*1%

C643 0.1UF/10V /*MLCC/+/-10%
R496 0Ohm /*5%

12
12

12

12

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

2

H_D#[0..63]9

H_DSTBN#19
H_DSTBP#19
H_DINV#19

CPU_MCH_BSEL010,21
CPU_MCH_BSEL110,21
CPU_MCH_BSEL210,21

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

CPU_TEST1
CPU_TEST2

CPU_TEST4
CPU_TEST6

For the purpose of testability, route these signals
through a ground referenced Zo= 55 ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB BCLK BSEL2 BSEL1 BSEL0

533 133 0 0 1

U24B

MOLEX/47387-4781

H_D#0

E22

AD26

AF26

F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

B22
B23
C21

T42

T31

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

SOCKET478

1

1

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5 H_D#37
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

DATA GRP 0

DATA GRP 1

MISC

CPU_TEST3

CPU_TEST5

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#

DATA GRP 2DATA GRP 3

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#
COMP0

COMP1
COMP2
COMP3

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36

H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

667 166 0 1 1

800 200 0 1 0

12

1

H_D#[0..63] 9

H_DSTBN#2 9
H_DSTBP#2 9

H_D#[0..63]

R167

54.9Ohm

1%

H_DINV#2 9

H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_DPRSTP# 10,15,53
H_DPSLP# 15
H_DPWR# 9
H_PWRGOOD 15
H_CPUSLP# 9
H_PSI# 53

12

R165 1KOhm 5%

R168

R498

27.4Ohm

54.9Ohm

1%

12

1%

12

H_PWRGD_XDP 52

R497

27.4Ohm

1%

12

+1.05V_VCCP

XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TCK
XDP_TRST#

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

12

R172 54.9Ohm 1%

12

R171 54.9Ohm 1%

12

R173 54.9Ohm 1%

12

R170 54.9Ohm 1%

12

R169 649Ohm 1%

1.2

Monday, March 19, 2007

DATE:
SHEET OF

7 69

4

CPU_PROCHOT#

1

G

2

S

Q61
2N7002

Id=180mA/Pd=300mW
/*

DESCRIPTION:

3

D

R495

2.2KOhm

/*

12

EC_CPU_PROCHOT# 37

MEROM CPU (1)

3

RELEASE DATE :

<OrgName>

2

Comp0,2 connect with Zo=27.4ohm, Comp1,3
connect with Zo=55 ohm, make those traces
length shorter than 0.5". Trace should be
at least 25 mils away from any other
toggling signal.

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

+VCC_CORE

D D

+VCC_CORE

All use 10U 4V (+-20% , X6S , 0805)Pb-Free.

12

C629

12

C353

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C604

12

C339

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C311

12

C627

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C318

12

C615

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

8 inside cavity, north side, secondary layer.

+VCC_CORE

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C352

12

C330

12

C336

C C

+VCC_CORE

12

C310

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C334

12

C605

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C599

12

C613

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

8 inside cavity, south side, secondary layer.

+VCC_CORE

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C625

12

C345

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C623

12

C313

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C308

B B

6 inside cavity, north side, primary layer.

+VCC_CORE

12

C350

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C351

12

C312

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C626

12

C621

6 inside cavity, south side, primary layer.

+1.05V_VCCP

12

C596

0.1UF/10V

A A

MLCC/+/-10%

Layout out:
Place these inside socket cavity on North side secondary.

12

C595

0.1UF/10V

MLCC/+/-10%

12

C632

0.1UF/10V

MLCC/+/-10%

12

C362

0.1UF/10V

MLCC/+/-10%

12

C633

0.1UF/10V

MLCC/+/-10%

4

12

C322

10UF/4V

MLCC/+/-20%
pt_c0805

12

C335

10UF/4V

MLCC/+/-20%
pt_c0805

12

C307

0.1UF/10V

MLCC/+/-10%

12

C611

12

C349

12

C357

12

C628

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

3

100U/25V *4 Remove to POWER CIRCUIT .

+VCC_CORE

12

+

CE4

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

12

+

CE3

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

12

+

CE6

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

U24C

MOLEX/47387-4781
A7
A9

A10
A12
A13
A15
A17
A18
A20

B7
B9

B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

AC10
AB10
AB12
AB14
AB15
AB17
AB18

SOCKET478

12

VCC001
VCC002
VCC003
VCC004
VCC005
VCC006
VCC007
VCC008
VCC009
VCC010
VCC011
VCC012
VCC013
VCC014
VCC015
VCC016
VCC017
VCC018
VCC019
VCC020
VCC021
VCC022
VCC023
VCC024
VCC025
VCC026
VCC027
VCC028
VCC029
VCC030
VCC031
VCC032
VCC033
VCC034
VCC035
VCC036
VCC037
VCC038
VCC039
VCC040
VCC041
VCC042
VCC043
VCC044
VCC045
VCC046
VCC047
VCC048
VCC049
VCC050
VCC051
VCC052
VCC053
VCC054
VCC055
VCC056
VCC057
VCC058
VCC059
VCC060
VCC061
VCC062
VCC063

VCCSENSE

VCC064
VCC065
VCC066

VSSSENSE

VCC067

+

CE8

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

/*

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA01
VCCA02

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

12

+

CE12

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

/*

+VCC_CORE+VCC_CORE

+1.05V_VCCP

12

+

CE2
220UF/4V

pt_c7343d_h79
+/-20%

VID0 53
VID1 53
VID2 53
VID3 53
VID4 53
VID5 53
VID6 53

VCCSENSE 53

VSSSENSE 53

NO.41

12

+

CE5

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

2

12

C644

0.01UF/25V

MLCC/+/-10%
pt_c0603

Layout Note:
Place 0.01U/25V near PIN
B26.

VCCSENSE
VSSSENSE

Route VCCSENSE and VSSSENSE
traces at 27.4ohms with 50
mils spacing and length
matched to within 25 mil.
Place PU and PD within
1 inch of CPU.

+1.5V_RUN

12

C645

10UF/4V

MLCC/+/-20%
pt_c0805

+VCC_CORE

R177
100Ohm

1%

12

R176
100Ohm

1%

12

1

U24D

MOLEX/47387-4781

A4

VSS001

A8

VSS002

A11

VSS003

A14

VSS004

A16

VSS005

A19

VSS006

A23

VSS007

AF2

VSS008

B6

VSS009

B8

VSS010

B11

VSS011

B13

VSS012

B16

VSS013

B19

VSS014

B21

VSS015

B24

VSS016

C5

VSS017

C8

VSS018

C11

VSS019

C14

VSS020

C16

VSS021

C19

VSS022

C2

VSS023

C22

VSS024

C25

VSS025

D1

VSS026

D4

VSS027

D8

VSS028

D11

VSS029

D13

VSS030

D16

VSS031

D19

VSS032

D23

VSS033

D26

VSS034

E3

VSS035

E6

VSS036

E8

VSS037

E11

VSS038

E14

VSS039

E16

VSS040

E19

VSS041

E21

VSS042

E24

VSS043

F5

VSS044

F8

VSS045

F11

VSS046

F13

VSS047

F16

VSS048

F19

VSS049

F2

VSS050

F22

VSS051

F25

VSS052

G4

VSS053

G1

VSS054

G23

VSS055

G26

VSS056

H3

VSS057

H6

VSS058

H21

VSS059

H24

VSS060

J2

VSS061

J5

VSS062

J22

VSS063

J25

VSS064

K1

VSS065

K4

VSS066

K23

VSS067

K26

VSS068

L3

VSS069

L6

VSS070

L21

VSS071

L24

VSS072

M2

VSS073

M5

VSS074

M22

VSS075

M25

VSS076

N1

VSS077

N4

VSS078

N23

VSS079

N26

VSS080

P3

VSS081

SOCKET478

VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

8 69

4

DESCRIPTION:

Merom CPU (2)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

4

3

2

1

H_D#[0..63]7

D D

+1.05V_VCCP

12

R492

221Ohm

1%

H_SWING

12

12

C630

R493

0.1UF/10V

100Ohm

MLCC/+/-10%

1%

C C

+1.05V_VCCP

12

12

R199

R198

54.9Ohm

54.9Ohm

1%

1%

H_SCOMP
H_SCOMP#

H_RCOMP

12

R494

24.9Ohm

1%

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing

B B

+1.05V_VCCP

12

12

R482
1KOhm

1%

R484
2KOhm

1%

H_D#[0..63]

12

C617

0.1UF/10V

MLCC/+/-10%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#7,52
H_CPUSLP#7

H_REF

U11A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE_965PM

HOST

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#[3..35]

H_A#[3..35] 7

H_ADS# 7
H_ADSTB#0 7
H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7

CLK_MCH_BCLK 21

CLK_MCH_BCLK# 21
H_DPWR# 7
H_DRDY# 7
H_HIT# 7
H_HITM# 7
H_LOCK# 7
H_TRDY# 7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7

H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7
H_RS#1 7
H_RS#2 7

Layout Note:
Place the 0.1uF
decoupling capacitor
within 100 mils from
GMCH pins.

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

9 69

4

DESCRIPTION:

Crestline(HOST)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

+1.8V_SUS

12

R183
1KOhm

SM_RCOMP_VOH

12

12

D D

SM_RCOMP_VOL

12

+3.3V_RUN

R469 10KOhm 5%
R468 10KOhm 5%

+1.05V_VCCP

C C

B B

A A

<Variant Name>

C579

C586

2.2UF/10V

0.01UF/25V

MLCC/+/-10%

MLCC/+/-10%

c0603,pt_c0603

12

C585

C580

0.01UF/25V

2.2UF/10V

MLCC/+/-10%

MLCC/+/-10%
c0603,pt_c0603

12
12

R476

12

56Ohm 5%

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

CPU_MCH_BSEL07,21

CPU_MCH_BSEL17,21
CPU_MCH_BSEL27,21

+3.3V_RUN

PROJECT:

0.1%

12

R185

3.01KOhm

1%

12

R184
1KOhm

0.1%

PM_EXTTS#0
PM_EXTTS#1

DDR_A_MA1419,20
DDR_B_MA1419,20

THERMTRIP_MCH#

R475 4.02KOhm /*1%

R477 4.02KOhm 1%

R479 4.02KOhm /*1%

R471 4.02KOhm /*1%
R467 4.02KOhm /*1%

PM_BMBUSY#17

H_DPRSTP#7,15,53
PM_EXTTS#019
PM_EXTTS#119

ICH_PWRGD17,51

THERMTRIP_MCH#43

DPRSLPVR17,53

SB_NB_PCIE_RST#16

PLTRST#16,35,37

5

T137

1

T32

1

12

T135

1

T128

1

T138

1

12

T33

1

T132

1

T130

1

T131

1

T133

1

T34

1

12

T129

1

T30

1
12
12

THERMTRIP_MCH#

12

R487 0Ohm 5% /*

12

R486 0Ohm 5%

Lanai

DDR_A_MA14
DDR_B_MA14

PM_EXTTS#0
PM_EXTTS#1

PLTRST#_R

12

R151 0Ohm 5%

T18
T19
T21
T25
T23
T35
T37
T40
T38
T39
T36
T20
T24
T22
T26
T41

REVISION

U11B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

CFG3

C21

CFG_3

CFG4

C23

CFG_4

CFG5

F23

CFG_5

CFG6

N23

CFG_6

CFG7

G23

CFG_7

CFG8

J20

CFG_8

CFG9

C20

CFG_9

CFG10

R24

CFG_10

CFG11

L23

CFG_11

CFG12

J23

CFG_12

CFG13

E23

CFG_13

CFG14

E20

CFG_14

CFG15

K23

CFG_15

CFG16

M20

CFG_16

CFG17

M24

CFG_17

CFG18

L32

CFG_18

CFG19

N33

CFG_19

CFG20

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

1

NC_1

BK51

1

NC_2

BK50

1

NC_3

BL50

1

NC_4

BL49

1

NC_5

1

BL3

NC_6

1

BL2

NC_7

BK1

1

NC_8

BJ1

1

NC_9

E1

1

NC_10

A5

1

NC_11

C51

1

NC_12

B50

1

NC_13

A50

1

NC_14

A49

1

NC_15

BK2 R32

1

NC_16 TEST_2

CRESTLINE_965PM

R483 100Ohm 5%

12

PLTRST#_R

DATE:

1.2

SHEET OF

4

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DDR MUXINGCLKDMI

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2

CFGRSVD

PM

DMI_TXN_3
DMI_TXP_0

DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

ME

CL_VREF

NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

TEST_1

Monday, March 19, 2007

10 69

4

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

SMRCOMPP

BL15

SMRCOMPN

BK14

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31
AR49

AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35

1

A39

1

C38

1

B39

1

E36

1

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37

M_CLK_DDR0 19
M_CLK_DDR1 19
M_CLK_DDR2 19
M_CLK_DDR3 19

M_CLK_DDR#0 19
M_CLK_DDR#1 19
M_CLK_DDR#2 19
M_CLK_DDR#3 19

DDR_CKE0_DIMMA 19,20
DDR_CKE1_DIMMA 19,20
DDR_CKE2_DIMMB 19,20
DDR_CKE3_DIMMB 19,20

DDR_CS0_DIMMA# 19,20
DDR_CS1_DIMMA# 19,20
DDR_CS2_DIMMB# 19,20
DDR_CS3_DIMMB# 19,20

M_ODT0 19,20
M_ODT1 19,20
M_ODT2 19,20
M_ODT3 19,20

V_DDR_MCH_REF

CLK_MCH_3GPLL 21
CLK_MCH_3GPLL# 21

DMI_MRX_ITX_N0 16
DMI_MRX_ITX_N1 16
DMI_MRX_ITX_N2 16
DMI_MRX_ITX_N3 16

DMI_MRX_ITX_P0 16
DMI_MRX_ITX_P1 16
DMI_MRX_ITX_P2 16
DMI_MRX_ITX_P3 16

DMI_MTX_IRX_N0 16
DMI_MTX_IRX_N1 16
DMI_MTX_IRX_N2 16
DMI_MTX_IRX_N3 16

DMI_MTX_IRX_P0 16
DMI_MTX_IRX_P1 16
DMI_MTX_IRX_P2 16
DMI_MTX_IRX_P3 16

T127
T27
T29
T28
T126

CL_CLK0 17
CL_DATA0 17
ICH_CL_PWROK 17,37
ICH_CL_RST0# 17

MCH_CLVREF

CLK_3GPLLREQ# 21
MCH_ICH_SYNC# 17

R470
20KOhm

5%

12

DESCRIPTION:

3

Connect to
XDP CONN.

LCTLA_CLK52
LCTLB_DATA52

+1.8V_SUS

12

R480
20Ohm

1%

SMRCOMPP
SMRCOMPN

12

R481
20Ohm

1%

+1.25V_RUN

MCH_CLVREF

12

C293

0.1UF/10V

MLCC/+/-10%

12

R162
1KOhm

1%

12

R161
392Ohm

1%
pt_r0603

+3.3V_RUN

Non-iAMT

R465
0Ohm

5%

12

Crestline(VGA,DMI)

3

U11C

J40

L_BKLT_CTRL

H39

LCTLA_CLK
LCTLB_DATA

R464 10KOhm 5% /*

12

R463 10KOhm 5% /*

12

CFG5
CFG9
CFG16
CFG19

CFG20

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_965PM

DMI X2 Select
PCI Express

Graphic Lane
FSB Dynamic
ODT
DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

SDVO Present.SDVO_CRTL_DATA

RELEASE DATE :

2

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

LCTLA_CLK

NO.2

LCTLB_DATA

R462

R466

0Ohm

0Ohm

5%

5%

12

12

Low=DMIx2
High=DMIx4 (Default)
Low=Reverse Lane
High=Normal operation
Low=Dynamic ODT Disable
High=Dynamic ODT Enable (default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and PCIEx1 are operating
sumultaneously via PEG port

Low=No SDVO Device Present
(defaults)
High=SDVO Device Prsent

<OrgName>

2

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

1

+VCC_PEG

R461

VCC3G_PCIE_R

N43
M43

PCIE_MRX_GTX_N0

J51

PCIE_MRX_GTX_N1

L51

PCIE_MRX_GTX_N2

N47

PCIE_MRX_GTX_N3

T45

PCIE_MRX_GTX_N4

T50

PCIE_MRX_GTX_N5

U40

PCIE_MRX_GTX_N6

Y44

PCIE_MRX_GTX_N7

Y40

PCIE_MRX_GTX_N8

AB51

PCIE_MRX_GTX_N9

W49

PCIE_MRX_GTX_N10

AD44

PCIE_MRX_GTX_N11

AD40

PCIE_MRX_GTX_N12

AG46

PCIE_MRX_GTX_N13

AH49

PCIE_MRX_GTX_N14

AG45

PCIE_MRX_GTX_N15

AG41

PCIE_MRX_GTX_P0

J50

PCIE_MRX_GTX_P1

L50

PCIE_MRX_GTX_P2

M47

PCIE_MRX_GTX_P3

U44

PCIE_MRX_GTX_P4

T49

PCIE_MRX_GTX_P5

T41

PCIE_MRX_GTX_P6

W45

PCIE_MRX_GTX_P7

W41

PCIE_MRX_GTX_P8

AB50

PCIE_MRX_GTX_P9

Y48

PCIE_MRX_GTX_P10

AC45

PCIE_MRX_GTX_P11

AC41

PCIE_MRX_GTX_P12

AH47

PCIE_MRX_GTX_P13

AG49

PCIE_MRX_GTX_P14

AH45

PCIE_MRX_GTX_P15

AG42

PCIE_MTX_GRX_C_N0

N45

PCIE_MTX_GRX_C_N1

U39

PCIE_MTX_GRX_C_N2

U47

PCIE_MTX_GRX_C_N3

N51

PCIE_MTX_GRX_C_N4

R50

PCIE_MTX_GRX_C_N5

T42

PCIE_MTX_GRX_C_N6

Y43

PCIE_MTX_GRX_C_N7

W46

PCIE_MTX_GRX_C_N8

W38

PCIE_MTX_GRX_C_N9

AD39

PCIE_MTX_GRX_C_N10

AC46

PCIE_MTX_GRX_C_N11

AC49

PCIE_MTX_GRX_C_N12

AC42

PCIE_MTX_GRX_C_N13

AH39

PCIE_MTX_GRX_C_N14

AE49

PCIE_MTX_GRX_C_N15

AH44

PCIE_MTX_GRX_C_P0

M45

PCIE_MTX_GRX_C_P1

T38

PCIE_MTX_GRX_C_P2

T46

PCIE_MTX_GRX_C_P3

N50

PCIE_MTX_GRX_C_P4

R51

PCIE_MTX_GRX_C_P5

U43

PCIE_MTX_GRX_C_P6

W42

PCIE_MTX_GRX_C_P7

Y47

PCIE_MTX_GRX_C_P8

Y39

PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_P9

AC38

PCIE_MTX_GRX_C_P10

AD47

PCIE_MTX_GRX_C_P11

AC50

PCIE_MTX_GRX_C_P12

AD43

PCIE_MTX_GRX_C_P13

AG39

PCIE_MTX_GRX_C_P14

AE50

PCIE_MTX_GRX_C_P15 PCIE_MTX_GRX_P15

AH43

24.9Ohm 1%

12

PCIE_MRX_GTX_N[0..15] 22

PCIE_MRX_GTX_P[0..15] 22

C547 0.1UF/10V

12

C563 0.1UF/10V

12

C545 0.1UF/10V

12

C543 0.1UF/10V

12

C551 0.1UF/10V

12

C536 0.1UF/10V

12

C553 0.1UF/10V

12

C538 0.1UF/10V

12

C555 0.1UF/10V

12

C541 0.1UF/10V

12

C557 0.1UF/10V

12

C533 0.1UF/10V

12

C561 0.1UF/10V

12

C534 0.1UF/10V

12

C559 0.1UF/10V

12

C549 0.1UF/10V

12

C548 0.1UF/10V

12

C564 0.1UF/10V

12

C546 0.1UF/10V

12

C544 0.1UF/10V

12

C552 0.1UF/10V

12

C537 0.1UF/10V

12

C554 0.1UF/10V

12

C539 0.1UF/10V

12

C556 0.1UF/10V

12

C542 0.1UF/10V

12

C558 0.1UF/10V

12

C535 0.1UF/10V

12

C562 0.1UF/10V

12

C540 0.1UF/10V

12

C560 0.1UF/10V

12

C565 0.1UF/10V

12

Tolerence:
X7R +/-10%

PCIE_MTX_GRX_N[0..15] 22
PCIE_MTX_GRX_P[0..15] 22

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14

5

D D

4

3

2

1

DDR_A_D[0..63]19

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38 DDR_A_MA6
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U11D

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AM8
AN10

AT9
AN9

AM9
AN11

CRESTLINE_965PM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_BS0

BB19

SA_BS_0
SA_BS_1

SA_BS_2
SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

DDR SYSTEM MEMORY A

SA_RCVEN#

SA_WE#

BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1

DDR_A_BS2
DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

1

DDR_A_WE#

DDR_A_RAS# 19,20

T134

DDR_A_WE# 19,20

DDR_A_BS0 19,20
DDR_A_BS1 19,20
DDR_A_BS2 19,20

DDR_A_CAS# 19,20
DDR_A_DM[0..7] 19

DDR_A_DQS[0..7] 19

DDR_A_DQS#[0..7] 19

DDR_A_MA[0..13] 19,20

DDR_B_D[0..63]19

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15 DDR_B_DQS0
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20 DDR_B_DQS5
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U11E

AP49
AR51

AW50
AW51

AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4

BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

CRESTLINE_965PM

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

DDR SYSTEM MEMORY B

SB_WE#

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1

DDR_B_BS2
DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4

DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

1

DDR_B_WE#

DDR_B_RAS# 19,20

T136

DDR_B_WE# 19,20

DDR_B_BS0 19,20
DDR_B_BS1 19,20
DDR_B_BS2 19,20

DDR_B_CAS# 19,20
DDR_B_DM[0..7] 19

DDR_B_DQS[0..7] 19

DDR_B_DQS#[0..7] 19

DDR_B_MA[0..13] 19,20

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

11 69

4

DESCRIPTION:

Crestline(DDR2)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

4

3

2

1

+3.3V_RUN

12

C290
1UF/10V

MLCC/+/-10%
pt_c0603

R473 10Ohm 5%

12

C614
22UF/4V

MLCC/+/-20%
pt_c0805_h53

+1.05V_VCCP

Non-iAMT

+VCC_GMCH

D D

+1.8V_SUS

C C

B B

A A

U11G

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20

AN14

CRESTLINE_965PM

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

12

C622

0.1UF/10V

MLCC/+/-10%

12

C631

0.1UF/10V

MLCC/+/-10%

12

C638

0.22UF/10V

MLCC/+/-10%
pt_c0603

+1.05V_VCCP

Layout Note:
370 mils form edge.

12

C600

0.22UF/10V

MLCC/+/-10%
pt_c0603

12

C292

0.47UF/10V

MLCC/+/-10%
pt_c0603

12

C291
1UF/10V

MLCC/+/-10%
pt_c0603

12

+

CE11
220UF/4V

pt_c7343d_h79
+/-20%

+VCC_GMCH_L

12

12

C576

0.22UF/10V

MLCC/+/-10%

pt_c0603

Layout Note:
Inside GMCH cavity

+VCC_AXM

12

C583

0.1UF/10V

MLCC/+/-10%

12

C572

22UF/4V

MLCC/+/-20%
pt_c0805_h53

Layout Note:
Place close to GMCH edge.

D18

21

RB751V_40

+VCC_GMCH

12

12

C575

C581

0.22UF/10V

MLCC/+/-10%

Layout Note:
Inside GMCH cavity

12

C584

0.1UF/10V

MLCC/+/-10%

12

C620

0.22UF/10V

MLCC/+/-10%

pt_c0603

0.1UF/10V

MLCC/+/-10%

pt_c0603

12

C582

0.1UF/10V

MLCC/+/-10%

12

C574

0.22UF/10V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

Layout Note:
Place C577 where LVDS
andDDR2 taps

12

C577

0.1UF/10V

MLCC/+/-10%

U11F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37 A3

VCC_NCTF_37 VSS_SCB1

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_965PM

12

+

CE1
330UF/6.3V

pt_c7343d_h110
+/-20%

POWER

12

C302
22UF/4V

MLCC/+/-20%
pt_c0805_h53

Layout Note:
Place on the edge

VCC NCTF

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

12

C296
22UF/4V

MLCC/+/-20%
pt_c0805_h53

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCC_AXM

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

12 69

4

DESCRIPTION:

Crestline(VCC,NCTF)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

4

3

2

1

+1.05V_VCCP

Place caps close to
VCC_AXF

+1.05V_VCCP

21

D17

RB751V_40

/*

+VCC_HV_L

21
12

R472
10Ohm 5%

/*

+3.3V_RUN

+1.25V_RUN

+VCC_AXF

12

12

C598
1UF/10V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

1uH+-20%_300mA

C592
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

45mA MAX.

Non-iAMT

D D

+1.25V_RUN

C C

B B

+1.25V_RUN

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

A A

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

L45

120Ohm/100Mhz

21

BLM18AG121SN1D

L22

120Ohm/100Mhz

21

BLM18AG121SN1D

R200

12

0.5Ohm 1%

pt_r0603

+VCC_MPLL_L

12

C641
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

220Ohm/100Mhz

BLM21PG221SN1D

pt_l0805_h41

12

L39

+VCCA_HPLL

C640
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

+VCCA_MPLL

+VCCA_PEG_PLL

21

12

12

12

C637

0.1UF/10V

MLCC/+/-10%

12

C364

0.1UF/10V

MLCC/+/-10%

R478
1Ohm

1%
pt_r0603

C608
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+1.25V_RUN

12

C569

0.1UF/10V

MLCC/+/-10%

+1.25V_RUN

Non-iAMT

12

12

CE10

+

100UF/6.3V

+/-20%
pt_c3528_h79

JP2

12

0Ohm

12

C363

JUMP

22UF/4V

MLCC/+/-20%
pt_c0805_h53

JUMP

JP3
0Ohm

+1.5V_RUN

12

C607

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C589
1UF/10V

MLCC/+/-10%
pt_c0603

12

10UF/6.3V

MLCC/+/-20%

pt_c0805_h53

C593

12

C602
22UF/4V

MLCC/+/-20%
pt_c0805_h53

12

C590
1UF/10V

MLCC/+/-10%
pt_c0603

12

0.1UF/10V

MLCC/+/-10%

+1.25V_RUN

Non-iAMT

+3.3V_RUN

C588

12

C566

0.1UF/10V

MLCC/+/-10%

12

C603
22UF/4V

MLCC/+/-20%
pt_c0805_h53

12

C578

0.1UF/10V

MLCC/+/-10%

12

+VCCA_SM

C587

0.022UF/16V

MLCC/+/-10%

12

C365

0.1UF/10V

MLCC/+/-10%

+VCCA_HPLL
+VCCA_MPLL

+VCCA_PEG_PLL

12

C606
1UF/10V

MLCC/+/-10%
pt_c0603

+VCCA_SM_CK

+VCCA_PEG_PLL

12

C571

0.1UF/10V

MLCC/+/-10%

U11H

J32

A33
B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32

L29
N28
AN2
U48

J41
H42

CRESTLINE_965PM

+VTTLF1
+VTTLF2
+VTTLF3

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

12

POWER

D TV/CRTLVDS

C366

0.47UF/10V

MLCC/+/-10%
pt_c0603

CRTPLLA PEGA SMTV

A CK A LVDS

12

C634

0.47UF/10V

MLCC/+/-10%
pt_c0603

VTT

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VTTLF1
VTTLF2
VTTLF3

12

C624

0.47UF/10V

MLCC/+/-10%
pt_c0603

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

+VTTLF1
+VTTLF2
+VTTLF3

+VCC_AXF

+VCC_SM_CK

+VCC_RXR_DMI

12

C636

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Place on the edge

12

C618

0.47UF/6.3V

MLCC/+/-10%

Place on the edge

+VCC_AXD_L

12

12

C597
1UF/10V

MLCC/+/-10%
pt_c0603

Place caps
close to
VCC_AXD

+3.3V_RUN

C573

12

0.1UF/10V

MLCC/+/-10%

12

C635

4.7UF/10V

MLCC/+/-10%
pt_c0805_h37

12

C639

4.7UF/10V

MLCC/+/-10%
pt_c0805_h37

12

0Ohm
C594
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

12

+VCC_PEG

12

+

CE9
220UF/4V

pt_c7343d_h79
+/-20%

12

+

CE7
220UF/4V

pt_c7343d_h79
+/-20%

12

+1.05V_VCCP

12

+

220UF/4V

pt_c7343d_h79
+/-20%

L42

+VCC_AXD_R

5%

pt_r0603

+1.25V_RUN

C570

0.1UF/10V

MLCC/+/-10%

12

C567
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

12

C294
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+VCC_SM_CK

C329
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

CE13

JUMP

JP4

12

0Ohm

Reserved L1202 pad
for inductor

L41

21

91nH+-20%_1.5A

91NH/1.5A

L40

21

91NH/1.5A

91nH+-20%_1.5A

12

C301

0.1UF/10V

MLCC/+/-10%

Non­iAMT

+1.25V_RUN

L21

1UH/300mA

12

pt_l0805_h53

R187
1Ohm 1%

pt_r0603

+VCC_SM_CK_L

12

C346
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+1.05V_VCCP

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

13 69

4

DESCRIPTION:

Crestline(POWER)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

U11I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

D D

C C

B B

A A

<Variant Name>

PROJECT:

AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

5

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AL1

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_965PM

VSS

Lanai

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

REVISION

1.2

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

4

Monday, March 19, 2007

DATE:
SHEET OF

4

14 69

U11J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_965PM

VSS

DESCRIPTION:

3

W11

VSS_287

W39

VSS_288

W43

VSS_289

W47

VSS_290

W5

VSS_291

W7

VSS_292

Y13

VSS_293

Y2

VSS_294

Y41

VSS_295

Y45

VSS_296

Y49

VSS_297

Y5

VSS_298

Y50

VSS_299

Y11

VSS_300

P29

VSS_301

T29

VSS_302

T31

VSS_303

T33

VSS_304

R28

VSS_305

AA32

VSS_306

AB32

VSS_307

AD32

VSS_308

AF28

VSS_309

AF29

VSS_310

AT27

VSS_311

AV25

VSS_312

H50

VSS_313

Crestline(VSS)

3

2

RELEASE DATE :

2

<OrgName>

1

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

12

R217 10MOhm 5%

X3

32.768KHZ

ICH_RTCX2 ICH_RTCX1

D D

C C

ICH_AZ_MDC_BITCLK36

ICH_AZ_CODEC_BITCLK44

NO.52

ICH_AZ_MDC_SYNC36

ICH_AZ_CODEC_SYNC44

ICH_AZ_MDC_RST#36

ICH_AZ_CODEC_RST#44

ICH_AZ_MDC_SDOUT36

ICH_AZ_CODEC_SDOUT44

Place all series terms close to ICH8 except for SDIN input lines, which
should be close to source. Placement of R235, R264, R265, R258 should
equal distance to the T split trace point as R236, R268, R270, R275
respective. Basically, keep the same distance from T for all series
termination resistors.

B B

SATA_TX0-31

SATA_TX0+31

Distance between the ICH-8 M and cap on the "P" signal
should be identical distance between the ICH-8 M and cap on
the "N" signal for same pair.

The circuit is only
needed if the
platform has the
SNIFFER.

A A

SATA_ACT#_R42

LED_MASK#38,41

C648 3900PF/50VMLCC/+/-10%
C650 3900PF/50VMLCC/+/-10%

Q43 2N7002

Id=180mA/Pd=300mW

R246 0Ohm 5% /*

12

NO.24

+RTC_CELL

R235 33Ohm 5%
R236 33Ohm 5%

12

C388
27PF/50V

MLCC/+/-5%

R264 33Ohm 5%
R268 33Ohm 5%

R265 33Ohm 5%
R270 33Ohm 5%

R258 33Ohm 5%
R275 33Ohm 5%

+3.3V_RUN

1

G

3

2

D

S

12

C377

15PF/50V

MLCC/+/-5%
/*

R295
1MOhm

5%

12

12

C389
27PF/50V

MLCC/+/-5%
/*

12
12

R247
10KOhm

5%

12

+/-10ppm/6PF

14

2

3

NO.24

R232

20KOhm

5%

ICH_RTCRST#

12

ICH_INTRUDER#

12

C391
1UF/10V/X7R

MLCC/+/-10%
pt_c0603

12
12

12
12

12
12

12
12

SATA_ACT#

ACZ_BIT_CLK

HD damping resistors will be
moved to daughter board

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

SATA_TX0-_C
SATA_TX0+_C

4

12

R213 0Ohm 5%

ICH _RSVD

0

0

1

1

NO.24

12

C375

15PF/50V

MLCC/+/-5%
/*

Place within 500 mils
of ICH8 ball

XOR Chain Entrance strap

ACZ_SDOUT

Description

0

RSVD

Enter XOR chain

1

0

Normal operation (Default)

Set PCIE port config bit 1

1

3

+RTC_CELL

R233
332KOhm

1%

ICH_INTVRMEN ICH_LAN100_SLP

12

R259
0Ohm 5%

/*

12

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5 and VccCL1.5)

ICH_INTVRMEN

+1.5V_PCIE_ICH

ICH_AZ_CODEC_SDIN044

ICH_AZ_MDC_SDIN136

CLK_PCIE_SATA#21
CLK_PCIE_SATA21

SPEAKER_DET#46
RTC_BAT_DET#40

SATA_RX0-31
SATA_RX0+31

Low = Internal VR Disabled
High = Internal VR Enable(Default)

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
ICH_INTRUDER#
ICH_INTVRMEN

ICH_LAN100_SLP
GLAN_CLK

T92

1

LAN_RXD0

T91

1

LAN_RXD1

T93

1

LAN_RXD2

T84

1

LAN_TXD0

T85

1

LAN_TXD1

T80

1

LAN_TXD2

T90

1

T145

1

GLAN_COMP

12

R344 24.9Ohm 1%

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#

T143

1

T54

1

ACZ_SDOUT
SPEAKER_DET#

RTC_BAT_DET#
SATA_ACT#

SATA_TX0-_C
SATA_TX0+_C

12

R301
1KOhm

5%
/*

ACZ_SDOUT

12

R517
1KOhm

5%
/*

SATABIAS

ICH_RSVD 17

12

R261 24.9Ohm 1%

+3.3V_RUN

U28A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8-M

Pull up for each detect line

ICH8M LAN100SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLANIHDASATA

CPUPWRGD/GPIO49

IDE LPCCPU

R257

100KOhm

5%

12

+RTC_CELL

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0

DA1

DA2

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

+3.3V_RUN+3.3V_RUN

R277

12

RTC_BAT_DET#SPEAKER_DET#

2

R300
332KOhm

1%

12

R298
0Ohm 5%

/*

12

High = Internal VR Enable(Default)

E5
F5
G8
F6

C4

LPC_LDRQ0#

G9

LPC_LDRQ1#

E6

SIO_A20GATE

AF13
AG26

H_DPRSTP#

AF26

H_DPSLP#

AE26

H_FERR#

AD24
AG29
AF27
AE24

AC20

SIO_RCIN#

AH14
AD23

AG28
AA24

THERMTRIP#_ICH

AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

100KOhm

5%

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

1

IDE_DD[0..15]

T53

LPC_LAD0 37
LPC_LAD1 37
LPC_LAD2 37
LPC_LAD3 37

LPC_LFRAME# 37

T71

1

T82

1

SIO_A20GATE 37
H_A20M# 7

H_DPRSTP# 7,10,53
H_DPSLP# 7

H_FERR# 7
H_PWRGOOD 7
H_IGNNE# 7
H_INIT# 7

H_INTR 7
SIO_RCIN# 37

H_NMI 7
H_SMI# 7

H_STPCLK# 7

IDE_DD[0..15] 31

IDE_DA0 31
IDE_DA1 31
IDE_DA2 31

IDE_DCS1# 31
IDE_DCS3# 31

IDE_DIOR# 31
IDE_DIOW# 31
IDE_DDACK# 31
IDE_IRQ 31
IDE_DIORDY 31
IDE_DDREQ 31

1

H_DPRSTP#
H_DPSLP#
H_FERR#

SIO_A20GATE
SIO_RCIN#

THERMTRIP#_ICH

12

R263
56Ohm

5%
/*

+1.05V_VCCP

12

+3.3V_RUN

12

R254
10KOhm

5%

+1.05V_VCCP

12

R271
56Ohm

5%
/*

R269
56Ohm

5%

12

12

R509
10KOhm

5%

R278
56Ohm

5%

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

15 69

4

DESCRIPTION:

ICH8: IDE/AC97/LPC/RTC

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

Place TX DC blocking caps close ICH8.

5

C434 0.1UF/10V MLCC/+/-10%

PCIE_TX1-50
PCIE_TX1+50

PCIE_TX2-50
PCIE_TX2+50

D D

C C

PCIE_TX4-35
PCIE_TX4+35

PCIE_TX6-/GLAN_TX-47
PCIE_TX6+/GLAN_TX+47

SPI_CS0#40

12

R595 15Ohm5% /*

12

R594 0Ohm 5%

12

C436 0.1UF/10V MLCC/+/-10%

12

C443 0.1UF/10V MLCC/+/-10%

12

C439 0.1UF/10V MLCC/+/-10%

12

C458 0.1UF/10V MLCC/+/-10%

12

C461 0.1UF/10V MLCC/+/-10%

12

C714 0.1UF/10V MLCC/+/-10%

12

C713 0.1UF/10V MLCC/+/-10%

12

Layout Note:
Place 15 ohm within
500 mils from ICH.

+3.3V_ALW

U33

5

VCC

ICH_SPI_CS#_R

2

4

A

Y

1

B

GND

3

74AHC1G08GW

/*

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

ICH_EC_SPI_CLK37

ICH_EC_SPI_DO37
ICH_EC_SPI_DIN37

R596 15Ohm 5%

12

R353 15Ohm 5%

R343 15Ohm 5%

ICH_SPI_CS#

SIO_SPI_CS# 37

Non-iAMT

OC4#

OC7#

OC6#

OC9#

B B

A A

<Variant Name>

PCI_AD[0..31]32

PCI_PIRQB#
PCI_PIRQC#32
PCI_PIRQD#32

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

T95

PCI_PIRQA#

1

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PROJECT:

5

U28B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10 B3

PIRQD# PIRQH#/GPIO5

ICH8-M

Lanai

PCI

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

REVISION

1.2

PAR

PME#

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18

PCI_GNT1#

C18

SB_WWAN_PCIE_RST#

B19

PCI_GNT2#

F18

SB_LOM_PCIE_RST#

A11

PCI_GNT3#

C10
C17

E15
F16
E17

PCI_IRDY#

C8
D9

PCI_RST#_G

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10
G7

ICH_GPIO2_PIRQE#

F8

SB_WLAN_PCIE_RST#

G11

SB_NB_PCIE_RST#

F12

DATE:
SHEET OF

4

PCIE_RX1-50

PCIE_RX1+50

MiniWWAN

PCIE_RX2-50

PCIE_RX2+50

MiniWLAN

PCIE_RX4-35

PCIE_RX4+35

ExpressCard

PCIE_RX6-/GLAN_RX-47
PCIE_RX6+/GLAN_RX+47

12

T78

1

12

USB_OC0_1#39
USB_OC2_3#50

RP1E

65

10KOhm 5%

RP1F

75

10KOhm 5%

RP1G

85

10KOhm 5%

RP1H

95

10KOhm 5%

PCI_REQ0#
PCI_GNT0#
PCI_REQ1# 32
PCI_GNT1# 32
SB_WWAN_PCIE_RST# 50

SB_LOM_PCIE_RST# 47

CLK_PCI_ICH 21

SB_WLAN_PCIE_RST# 50
SB_NB_PCIE_RST# 10
PCIE_MCARD2_DET# 50

Monday, March 19, 2007

16 69

4

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

ICH_EC_SPI_CLK_R
ICH_SPI_CS#
ICH_SPI_CS1#_R

ICH_EC_SPI_DO_R

USB_OC0_1#
USB_OC2_3#
OC4#

OC5#
OC6#
OC7#
OC8#
OC9#

10

RP1D

10

10

RP1C

10

10

RP1B

10

10

RP1A

10

PCI_C_BE0# 32
PCI_C_BE1# 32
PCI_C_BE2# 32
PCI_C_BE3# 32

PCI_IRDY# 32
PCI_PAR 32

PCI_DEVSEL# 32
PCI_PERR# 32

PCI_SERR# 32
PCI_STOP# 32
PCI_TRDY# 32
PCI_FRAME# 32

ICH_PME# 38

45

10KOhm 5%

35

10KOhm 5%

25

10KOhm 5%

15

10KOhm 5%

1
1

NO.13

DESCRIPTION:

U28D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

ICH8-M

+3.3V_SUS

USB_OC2_3#

OC8#

OC5#

USB_OC0_1#

T77
T89

R5C833

ICH8: PCI/INT/DMI/USB

3

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

PCI-Express

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P
USBP6N

USB

USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

ICH_SPI_CS1#_R
PCI_GNT0#

REQ1 GNT1 PIRQC

3

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

12

ICH_USBP4­ICH_USBP4+

ICH_USBP8­ICH_USBP8+

R347
1KOhm

5%

DMI_COMP

USBRBIAS

DMI_MTX_IRX_N0 10
DMI_MTX_IRX_P0 10
DMI_MRX_ITX_N0 10
DMI_MRX_ITX_P0 10

DMI_MTX_IRX_N1 10
DMI_MTX_IRX_P1 10
DMI_MRX_ITX_N1 10
DMI_MRX_ITX_P1 10

DMI_MTX_IRX_N2 10
DMI_MTX_IRX_P2 10
DMI_MRX_ITX_N2 10
DMI_MRX_ITX_P2 10

DMI_MTX_IRX_N3 10
DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N3 10
DMI_MRX_ITX_P3 10

CLK_PCIE_ICH# 21
CLK_PCIE_ICH 21

12

R286 24.9Ohm 1%

ICH_USBP0- 39
ICH_USBP0+ 39
ICH_USBP1- 39
ICH_USBP1+ 39
ICH_USBP2- 50
ICH_USBP2+ 50
ICH_USBP3- 50
ICH_USBP3+ 50

ICH_USBP5- 28
ICH_USBP5+ 28
ICH_USBP6- 35
ICH_USBP6+ 35
ICH_USBP7- 41
ICH_USBP7+ 41

ICH_USBP9- 50
ICH_USBP9+ 50

USER1 Left side pair top/left

USER2 Left side pair bottom/right

USER3 Right side pair top/left

USER3 Right side pair bottom/right

1
1

CCD

Express Card

BlueTooth

1
1

WWAN

12

R561

22.6Ohm

1%
pt_r0603

Boot BIOS Strap

LPC 11 No stuff No stuff

R337
1KOhm

PCI 10 No stuff Stuff

5%
/*

12

SPI 01 Stuff No stuff

PCI_GNT3#

T63
T68

NO.5

T59
T62

GNT0# SPI_CS1#

R346
1KOhm/*5%

12

A16 away override strap.

PCI_GNT3# Low = A16 swap override enabled.

PIRQD

High = Default.

CLK_PCI_ICH

Reserved for EMI.
Place resister and cap
close to ICH.

R355
10Ohm

5%
/*

12

12

C475

8.2PF/50V

MLCC/+/-0.25PF
/*

RELEASE DATE :

2

+1.5V_PCIE_ICH

<OrgName>

2

BIOS should not enable the internal GPIO pull up
resistor

SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#

SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#
SB_WWAN_PCIE_RST#

R338 10KOhm 5%
R147 10KOhm 5%

R491 100KOhm 5%
R334 100KOhm 5%
R354 20KOhm 5%
R356 20KOhm 5%

1

12
12

12
12
12
12

+3.3V_RUN

Place within 500 mils of ICH8

PCI Pullups

PCI_STOP#
PCIE_MCARD2_DET#

PCI_DEVSEL#

PCI_FRAME#

ICH_GPIO2_PIRQE#

PCI_SERR#

PCI_REQ0#

PCI_PLOCK#

Non-iAMT

PCI_RST#_G

PCI_PLTRST#

PCI_PLTRST#

DESIGN ENGINEER :SCHEMATIC FILE NAME :

R350 8.2KOhm 5%

12

R613 100KOhm 5%

12

RP4E

65

8.2KOhm 5%
RP4F

75

8.2KOhm 5%
RP4G

85

8.2KOhm 5%
RP4H

95

8.2KOhm 5%

RP3E

65

8.2KOhm 5%
RP3F

75

8.2KOhm 5%
RP3G

85

8.2KOhm 5%
RP3H

95

8.2KOhm 5%

C689 0.047UF/10V

12

MLCC/+/-10%

U30

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

C382 0.047UF/10V

12

MLCC/+/-10%

U14

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

C747 0.047UF/10V

12

MLCC/+/-10%

U37

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

Terry_Lin

10

10

10

10

10

10

10

10

5

5

5

RP4D

10

10

10

10

10

10

10

10

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

PCI_REQ1#

45

8.2KOhm 5%

RP4C

PCI_PIRQD#

35

8.2KOhm 5%

RP4B

25

8.2KOhm 5%

RP4A

PCI_TRDY#

15

8.2KOhm 5%

RP3D

45

8.2KOhm 5%

RP3C

35

8.2KOhm 5%

RP3B

25

8.2KOhm 5%

RP3A

15

8.2KOhm 5%

Add Buffers as needed for
Loading and fanout
concerns.

PCI_RST# 32

PLTRST# 10,35,37

PLTRST_LAN_MINICARD# 47,50

12

C758
47PF/50V

MLCC/+/-5%

1

+3.3V_RUN
+3.3V_RUN
+3.3V_RUN

+3.3V_RUN

PCI_PIRQC#

PCI_PIRQB#

PCI_PIRQA#PCI_PERR#

PCI_IRDY#

NO.51

NO.13

NO.36

5

+3.3V_SUS

R253 10KOhm 5% /*

+3.3V_SUS

RN36A

12

2.2KOhm

RN36B

34

2.2KOhm

D D

+3.3V_RUN

R512

8.2KOhm

5%

12

R507
10Ohm

5%
/*

12

Option to "Disable "
clkrun. Pulling it down

C C

will keep the clks
running.

USB_IDE#

R506 8.2KOhm 5%

SIO_EXT_SCI#

12

R297 10KOhm 5%

12

CLKRUN#

Non-iAMT

5%
5%

ICH_SMBDATA
ICH_SMBCLK

T45

LOM_SMB_ALERT#37

NO.14

+3.3V_RUN
+3.3V_SUS

12

R307 10KOhm 5%

12

R283 10KOhm 5%

12

R282 10KOhm 5%

12

R281 10KOhm 5%

12

R315 1KOhm 5%

12

ICH_SMBCLK35,50

ICH_SMBDATA35,50

1

XDP_DBRESET#7,38,52

R520 0Ohm 5% /*

ICH_PCIE_WAKE#38

IRQ_SERIRQ32,37

SIO_EXT_W AKE#38

PCIE_MCARD1_DET#50
USB_MCARD1_DET#50

USB_MCARD2_DET#50

IDE_RST_MOD31

SATA_CLKREQ#21

PLTRST_DELAY#22

CCD_VDD_ON28

NO.8

MCH_ICH_SYNC#10

ICH_RSVD15

T74

PM_BMBUSY#10

12

H_STP_PCI#21

H_STP_CPU#21

CLKRUN#32,37

T56

IMVP_PWRGD37,51,53

T139

T144

SIO_EXT_SMI#37

SIO_EXT_SCI#37

NO.13

SPKR44

12

R508 0Ohm 5%

1

1

1

1

R608 4.7KOhm 5%
T157

1

T142

1

T148

1

4

Non-iAMT

RSV_ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
LOM_ICH_SMBALERT#
ICH_PCIE_WAKE#

ICH_SMBCLK
ICH_SMBDATA
RSV_ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT

ICH_RI#

LOM_ICH_SMBALERT#

CLKRUN#
ICH_PCIE_WAKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD

USB_IDE#
RSVD_GPIO6
SIO_EXT_W AKE#
SIO_EXT_SMI#
SIO_EXT_SCI#
PCIE_MCARD1_DET#

12

RSVD_GPIO20
USB_MCARD2_DET#
USB_MCARD3_DET#

PLTRST_DELAY#

RSVD_GPIO39

CCD_VDD_ON

SPKR

MCH_ICH_SYNC#_R

U28C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8-M

SYS

SMB

GPIO

GPIO

MISC

SATA

GPIO

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

CLGPIO0/GPIO24
CLGPIO1/GPIO10
CLGPIO2/GPIO14

WOL_EN/GPIO9

AJ12
AJ10
AF11
AG11

CLK_ICH_14M

AG9

CLK_ICH_48M

G5

ICH_SUSCLK

D3
AG23

SIO_SLP_S4#

AF21
AD18

SIO_S4_STATE#

AH27

ICH_PWRGD

AE23

DPRSLPVR

AJ14

ICH_BATLOW#

AE21
C2

ICH_LAN_RST#

AH20

12

R252 0Ohm 5%

12

AG27

R251 0Ohm 5% /*

E1

ICH_CL_PWROK

E3

RSV_SIO_SLP_M#

AJ25
F23

RSV_ICH_CL_CLK1

AE18
F22

RSV_ICH_CL_DATA1

AF19

CL_VREF0

D24

CL_VREF1

AH23
AJ23

PCIE_MCARD3_DET#

AJ27

ME_EC_ALERT

AJ24

EC_ME_ALERT

AF22

WOL_EN

AG19

+3.3V_RUN

R513

8.2KOhm

5%

12

1

12

R299 8.2KOhm5%

T146

1

T48

1

T47

1

T140

1

T50

1

T141

1

T46

1

CLK_ICH_14M 21
CLK_ICH_48M 21

T156

SIO_SLP_S3# 37
SIO_SLP_S5# 37

T147

1

ICH_PWRGD 10,51
DPRSLPVR 10,53

SIO_PWRBTN# 37

ICH_RSMRST# 37
SUSPWROK 43, 51

CLK_PWRGD 21
ICH_CL_PWROK 10,37

CL_CLK0 10

CL_DATA0 10

ICH_CL_RST0# 10

1

+3.3V_SUS

2

1

Place these close to ICH8

CLK_ICH_48M

CLK_ICH_14M

T49

ICH_PWRGD
DPRSLPVR
WOL_EN
SUSPWROK
ICH_LAN_RST#
ICH_CL_PWROK

R266 10KOhm 5%

12

R515 100KOhm 5%

12

R256 100KOhm 5%

12

R249 10KOhm 5% /*

12

R516 1MOhm 5%

12

R340 1MOhm 5%

12

NO.31

12

R339
10Ohm

5%

12

C456

4.7PF/50V

MLCC/+/-0.25PF

12

R272
10Ohm

/*
5%

12

C395

4.7PF/50V

/*
MLCC/+/-0.25PF

Non-iAMT

+3.3V_SUS

EC_ME_ALERT

R231 8.2KOhm 5%

12

+3.3V_RUN

B B

+3.3V_RUN

R620 100KOhm 5%
R303 10KOhm 5%

R514 10KOhm 5% /*
R276 10KOhm 5%
R511 10KOhm 5%
R510 10KOhm 5%

R262 10KOhm 5%

R609 100KOhm 5%

12
12

12
12
12
12

12

12

NO.13

RSVD_GPIO20
RSV_THRM#

MCH_ICH_SYNC#_R
IRQ_SERIRQ
RSVD_GPIO6
RSVD_GPIO39

PLTRST_DELAY#

CCD_VDD_ON

R280
1KOhm 5%

/*

12

SPKR

No Reboot strap.

SPKR Low=Default
High=No Reboot

NO.8

+3.3V_SUS

A A

SIO_EXT_SMI#

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

17 69

4

<Variant Name>

R309 10KOhm 5%

12

PROJECT:

5

Non-iAMT

+3.3V_RUN

SMBus address D2

These are for
backdrive issue

1

ICH_SMBDATA35,50

ICH_SMBCLK35,50

DESCRIPTION:

ICH8: SMB/PWR/CLK/GPIO

3

D

Q40 2N7002

Id=180mA/Pd=300mW

+3.3V_RUN

1

3

D

Q41 2N7002

Id=180mA/Pd=300mW

3

G

2

S

G

2

S

RN35A

2.2KOhm

5%

RN35B

2.2KOhm

5%

12

34

MEM_SDATA 19

MEM_SCLK 19

RELEASE DATE :

Pull up for each detect line

RP2E

10

65

100KOhm 5%

RP2F

75

100KOhm 5%

100KOhm 5%

100KOhm 5%

RP2G

85

RP2H

95

USB_MCARD3_DET# PCIE_MCARD3_DET#

USB_MCARD2_DET#

Non-iAMT

CL_VREF0

12

C466

0.1UF/10V

MLCC/+80-20%

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

RP2D

10

10

RP2C

10

10

RP2B

10

10

RP2A

10

+3.3V_RUN +3.3V_SUS

12

R352

3.24KOhm

1%

CL_VREF1

12

12

R351
453Ohm

1%

Terry_Lin

+3.3V_RUN

45

100KOhm 5%

35

100KOhm 5%

25

100KOhm 5%

15

100KOhm 5%

C378

0.1UF/10V

MLCC/+80-20%
/*

USB_MCARD1_DET#

PCIE_MCARD1_DET#

12

R218

3.24KOhm

1%
/*

12

R219
453Ohm

1%
/*

1

NO.13

5

+RTC_CELL

R366 100Ohm 5%

12

+5V_RUN

D D

+3.3V_RUN

Non-iAMT

+3.3V_SUS

+1.5V_RUN

C C

+1.5V_RUN

12

R210
0Ohm 5%

+VCCSATPLL_L

L23

21

+VCCSATPLL

+VCCGLANPLL

12

C418
1UF/10V

MLCC/+/-10%
pt_c0603

12

C649
1UF/10V

MLCC/+/-10%
pt_c0603

B B

Non-iAMT

Place CAP
close to A24

+1.5V_RUN

A A

RB751V_40

12

+5V_SUS

R314 10Ohm5%

FB_330ohm+-25%_100mHz_

1.5A_0.09_ohm DC

L53
330Ohm/100Mhz

MURATA/BLM21PG331SN1D
pt_l0805_h41

21
12

+

CE14
220UF/4V

pt_c7343d_h79
+/-20%

10uH

Irat=100mA
pt_l0805

12

C646
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

D14

D12

RB751V_40

21

21

12

C470
22UF/10V

MLCC/+/-20%
pt_c1206_h75

+ICH_V5REF_RUN

12

C477

0.1UF/10V

MLCC/+/-10%

+ICH_V5REF_SUS

12

C445

0.1UF/10V

MLCC/+/-10%

+1.5V_RUN

+1.5V_PCIE_ICH

12

12

C412
22UF/10V

MLCC/+/-20%
pt_c1206_h75

12

C462

0.1UF/10V

MLCC/+/-10%

+3.3V_RUN

Non-iAMT

C403
1UF/10V

MLCC/+/-10%
pt_c0603

+1.5V_PCIE_ICH

12

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

12

C473

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C401

0.1UF/10V

MLCC/+/-10%

C428

2.2UF/10V

MLCC/+/-10%
pt_c0805_h53

T61
T67

12

C451

0.1UF/10V

MLCC/+/-10%

12

C402

0.1UF/10V

MLCC/+/-10%

+VCCSATPLL

12

C435

0.1UF/10V

MLCC/+/-10%

12

C411

0.1UF/10V

MLCC/+/-10%

12

C398

0.1UF/10V

MLCC/+/-10%

TP_VCCSUSLAN1

1

TP_VCCSUSLAN2

1

+3.3V_RUN

4

+VCCGLANPLL

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27
F24
F25
G24
H23
H24

J23

J24
K24
K25

L23
L24

L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25

Y25
AJ6
AE7

AF7
AG7
AH7
AJ7

AC1
AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17
G18

F19
G20

A24
A26

A27
B26
B27
B28

B25

U28F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8-M

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

3

12

C455

0.1UF/10V

MLCC/+/-10%

+VCC_DMI

+V_CPU_IO

12

C419

0.1UF/10V

MLCC/+/-10%

12

C450

0.1UF/10V

MLCC/+/-10%

12

C467

0.1UF/10V

MLCC/+/-10%

+TP_VCCSUS1.05_1
+TP_VCCSUS1.05_2

+TP_VCCSUS1.5_1
+TP_VCCSUS1.5_2
+VCCSUS3_3[0~6]

+VCCSUS3_3[7~19]

TP_VCCCL1.05
VCCCL1_5

+3.3V_RUN

Non-iAMT

+1.5V_DMIPLL

12

C432

0.01UF/25V

MLCC/+/-10%

12

C390

0.1UF/10V

MLCC/+/-10%

12

C460

0.1UF/10V

MLCC/+/-10%

T75

1

T51

1

T52

1

T72

1

T70

1

+1.05V_VCCP

12

C465

0.1UF/10V

MLCC/+/-10%

L49 0.1Ohm/100Mhz

pt_inductor_2p_126x98_tdk

21

12

C695
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

12

C397

0.1UF/10V

MLCC/+/-10%

Intel 20%

12

C410

12

C424

0.1UF/10V

MLCC/+/-10%

12

C396

0.1UF/10V

MLCC/+/-10%

0.1UF/10V

MLCC/+/-10%

12

C476

0.1UF/10V

MLCC/+/-10%
/*

+3.3V_RUN

Non-iAMT

+3.3V_SUS

+1.5V_DMIPLL_R

12

C392
22UF/10V

MLCC/+/-20%
pt_c1206_h75

12

C409

0.1UF/10V

MLCC/+/-10%

+3.3V_RUN

R285

0Ohm

5%

12

12

C407

0.1UF/10V

MLCC/+/-10%

12

C474
1UF/10V

MLCC/+/-10%
pt_c0603
/*

D13

1
2

BAT54C

+1.5V_RUN

12

R572 1Ohm 5%

pt_r0603

+1.25V_RUN

12

C440

4.7UF/10V

MLCC/+/-10%
pt_c1206_h71

Non-iAMT

12

2

3

+1.05V_VCCP

VCCHDA

C433

0.022UF/16V

MLCC/+/-10%

+1.5V_RUN+1.05V_VCCP

12

R332 10Ohm

pt_r0805_h24

+3.3V_SUS

12

C464

0.022UF/16V

MLCC/+/-10%

12

C427

0.1UF/10V

MLCC/+/-10%

1

U28E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

5%

AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AE12
AE22
AE25

AF14
AF16
AF18

AH10
AH13
AH16
AH19

AF28
AH22
AH24
AH26

VSS[004]

A25

VSS[005]

AB1

VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]
VSS[021]

AE2

VSS[022]
VSS[023]

AD1

VSS[024]
VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]
VSS[029]
VSS[030]
VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]

AH2

VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

ICH8-M

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

J25
J26
J27

J4

J5
K23
K28
K29

K3
K6

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

18 69

4

DESCRIPTION:

ICH8-M(POWER,GND)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

A is required to route to Top
S0DIMM for AMT to function
Ch.A SODIMM needs to be
populated for Intel AMT support.

D D

C C

DDR_CKE0_DIMMA10,20

DDR_A_BS211,20

DDR_A_BS011,20
DDR_A_WE#11,20

DDR_A_CAS#11,20
DDR_CS1_DIMMA#10,20

M_ODT110,20

B B

MEM_SDATA17
MEM_SCLK17

+3.3V_RUN

A A

Non-iAMT

<Variant Name>

SMbus address A0

PROJECT:

+1.8V_SUS +1.8V_SUS

DDR_A_D5
DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D1
DDR_A_D3

DDR_A_D15
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11
DDR_A_D10

DDR_A_D16
DDR_A_D21

DDR_A_DQS#2

DDR_A_D19
DDR_A_D22

DDR_A_D25
DDR_A_D27

DDR_A_DM3

DDR_A_D31
DDR_A_D24

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_WE#
DDR_A_CAS#

M_ODT1

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D40

DDR_A_D47
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D54

DDR_A_D56
DDR_A_D60

DDR_A_DM7
DDR_A_D61

DDR_A_D59

MEM_SDATA
MEM_SCLK

5

V_DDR_MCH_REF

Lanai

TOP

CON14

1

VREF

VSS46

3

VSS47

DQ4

5

DQ0

DQ5

7

DQ1

VSS15

9

VSS37

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201 202

DM0

DQS#0

VSS5

DQS0

DQ6

VSS48

DQ7

DQ2

VSS16

DQ3

DQ12

VSS38

DQ13

DQ8

VSS17

DQ9

DM1

VSS49

VSS53

DQS#1

CK0

DQS1

CK0#

VSS39

VSS41

DQ10

DQ14

DQ11

DQ15

VSS50

VSS54

VSS18

VSS20

DQ16

DQ20

DQ17

DQ21

VSS1

VSS6

DQS#2

NC3

DQS2

DM2

VSS19

VSS21

DQ18

DQ22

DQ19

DQ23

VSS22

VSS24

DQ24

DQ28

DQ25

DQ29

VSS23

VSS25

DM3

DQS#3

NC4

DQS3

VSS9

VSS10

DQ26

DQ30

DQ27

DQ31

VSS4

VSS8

CKE0

CKE1

VDD7

VDD8

NC1

A15

A16_BA2

A14

VDD9

VDD11

A12

A11

A9

A7

A8

A6

VDD5

VDD4

A5

A4

A3

A2

A1

A0

VDD10

VDD12

A10/AP

BA1

BA0

RAS#

WE#

S0#

VDD2

VDD1

CAS#

ODT0

S1#

A13

VDD3

VDD6

ODT1

NC2

VSS11

VSS12

DQ32

DQ36

DQ33

DQ37

VSS26

VSS28

DQS#4

DM4

DQS4

VSS42

VSS2

DQ38

DQ34

DQ39

DQ35

VSS55

VSS27

DQ44

DQ40

DQ45

DQ41

VSS43

VSS29

DQS#5

DM5

DQS5

VSS51

VSS56

DQ42

DQ46

DQ43

DQ47

VSS40

VSS44

DQ48

DQ52

DQ49

DQ53

VSS52

VSS57

NCTEST

CK1

VSS30

CK1#

DQS#6

VSS45

DQS6

DM6

VSS31

VSS32

DQ50

DQ54

DQ51

DQ55

VSS33

VSS35

DQ56

DQ60

DQ57

DQ61

VSS3

VSS7

DM7

DQS#7

VSS34

DQS7

DQ58

VSS36

DQ59

DQ62

VSS14

DQ63

SDA

VSS13

SCL

SA0

VDDSPD

SA1

GND0 GND1

NP_NC2NP_NC1

STD

FOXCONN/AS0A426-N2SN-7F

CLOCK 0 , 1
CKE 0 , 1

REVISION

1.2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

204203

DATE:
SHEET OF

4

+1.8V_SUS

DDR_A_D4
DDR_A_D6

DDR_A_DM0
DDR_A_D2

DDR_A_D7
DDR_A_D8

DDR_A_D12
DDR_A_DM1

M_CLK_DDR0 10
M_CLK_DDR#0 10

DDR_A_D14
DDR_A_D13

DDR_A_D17
DDR_A_D20

PM_EXTTS#0
DDR_A_DM2DDR_A_DQS2

DDR_A_D18
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D26

DDR_A_MA14 DDR_B_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1

DDR_A_RAS#DDR_A_BS0

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D38

DDR_A_DM4
DDR_A_D37

DDR_A_D35DDR_A_D39
DDR_A_D45

DDR_A_D44

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D41
DDR_A_D46

DDR_A_D53
DDR_A_D52

DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D58

DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D63
DDR_A_D62

R505
10KOhm

5%

12

PM_EXTTS#0 10

DDR_CKE1_DIMMA 10,20

DDR_A_BS1 11,20
DDR_A_RAS# 11,20

DDR_CS0_DIMMA# 10,20

M_ODT0 10,20

M_CLK_DDR1 10
M_CLK_DDR#1 10

R501
10KOhm

5%

12

Monday, March 19, 2007

19 69

4

DDR_A_DM[0..7] 11
DDR_A_D[0..63] 11
DDR_A_DQS[0..7] 11
DDR_A_DQS#[0..7] 11
DDR_A_MA[0..14] 10,11,20

V_DDR_MCH_REF

MLCC/+80-20%

12

C280

0.1UF/10V

+3.3V_RUN

MLCC/+/-10%

12

C373

2.2UF/6.3V

pt_c0805_h53

MLCC/+/-10%

12

C278

2.2UF/6.3V

pt_c0805_h53

Non-iAMT

MLCC/+80-20%

12

C374

0.1UF/10V

Non-iAMT

DESCRIPTION:

DDR_CKE2_DIMMB10,20

DDR_B_BS211,20

DDR_B_BS011,20
DDR_B_WE#11,20

DDR_B_CAS#11,20 M_ODT2 10,20
DDR_CS3_DIMMB#10,20

M_ODT310,20

DDR2 SO-DIMM (0)

3

V_DDR_MCH_REF

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D2

DDR_B_D9
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D14

DDR_B_D20
DDR_B_D16

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D25
DDR_B_D28

DDR_B_DM3

DDR_B_D27
DDR_B_D30

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#

M_ODT3

DDR_B_D38
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D33

DDR_B_D45
DDR_B_D46

DDR_B_DM5
DDR_B_D44

DDR_B_D42 DDR_B_D43
DDR_B_D53

DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D54

DDR_B_D56
DDR_B_D62

DDR_B_DM7
DDR_B_D63

DDR_B_D60
MEM_SDATA

MEM_SCLK

+3.3V_RUN

SMbus address A4

3

BOT

CON15

1

VREF

VSS46

3

VSS47

DQ4

5

DQ0

DQ5

7

DQ1

VSS15

9

VSS37

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201 202

DM0

DQS#0

VSS5

DQS0

DQ6

VSS48

DQ7

DQ2

VSS16

DQ3

DQ12

VSS38

DQ13

DQ8

VSS17

DQ9

DM1

VSS49

VSS53

DQS#1

CK0

DQS1

CK0#

VSS39

VSS41

DQ10

DQ14

DQ11

DQ15

VSS50

VSS54

VSS18

VSS20

DQ16

DQ20

DQ17

DQ21

VSS1

VSS6

DQS#2

NC3

DQS2

DM2

VSS19

VSS21

DQ18

DQ22

DQ19

DQ23

VSS22

VSS24

DQ24

DQ28

DQ25

DQ29

VSS23

VSS25

DM3

DQS#3

NC4

DQS3

VSS9

VSS10

DQ26

DQ30

DQ27

DQ31

VSS4

VSS8

CKE0

CKE1

VDD7

VDD8

NC1

A15

A16_BA2

A14

VDD9

VDD11

A12

A11

A9

A7

A8

A6

VDD5

VDD4

A5

A4

A3

A2

A1

A0

VDD10

VDD12

A10/AP

BA1

BA0

RAS#

WE#

S0#

VDD2

VDD1

CAS#

ODT0

S1#

A13

VDD3

VDD6

ODT1

NC2

VSS11

VSS12

DQ32

DQ36

DQ33

DQ37

VSS26

VSS28

DQS#4

DM4

DQS4

VSS42

VSS2

DQ38

DQ34

DQ39

DQ35

VSS55

VSS27

DQ44

DQ40

DQ45

DQ41

VSS43

VSS29

DQS#5

DM5

DQS5

VSS51

VSS56

DQ42

DQ46

DQ43

DQ47

VSS40

VSS44

DQ48

DQ52

DQ49

DQ53

VSS52

VSS57

NCTEST

CK1

VSS30

CK1#

DQS#6

VSS45

DQS6

DM6

VSS31

VSS32

DQ50

DQ54

DQ51

DQ55

VSS33

VSS35

DQ56

DQ60

DQ57

DQ61

VSS3

VSS7

DM7

DQS#7

VSS34

DQS7

DQ58

VSS36

DQ59

DQ62

VSS14

DQ63

SDA

VSS13

SCL

SA0

VDDSPD

SA1

GND0 GND1

NP_NC2NP_NC1

STD

FOXCONN/AS0A426-NASN-7F

CLOCK 2 , 3
CKE 2 , 3

RELEASE DATE :

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

204203

2

+1.8V_SUS

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D12
DDR_B_DM1

DDR_B_D11
DDR_B_D15

DDR_B_D21
DDR_B_D23

PM_EXTTS#1
DDR_B_DM2

DDR_B_D22
DDR_B_D17

DDR_B_D29
DDR_B_D31

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D24
DDR_B_D26

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#

M_ODT2
DDR_B_MA13

DDR_B_D35
DDR_B_D32

DDR_B_DM4
DDR_B_D39

DDR_B_D37
DDR_B_D40

DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47

DDR_B_D52
DDR_B_D49

DDR_B_DM6
DDR_B_D55

DDR_B_D50
DDR_B_D57

DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D58
DDR_B_D59

<OrgName>

2

M_CLK_DDR2 10
M_CLK_DDR#2 10

PM_EXTTS#1 10

DDR_CKE3_DIMMB 10,20

DDR_B_BS1 11,20
DDR_B_RAS# 11,20

DDR_CS2_DIMMB# 10,20

M_CLK_DDR3 10
M_CLK_DDR#3 10

R212
10KOhm

5%

12

DDR_B_DM[0..7] 11
DDR_B_D[0..63] 11
DDR_B_DQS[0..7] 11
DDR_B_DQS#[0..7] 11
DDR_B_MA[0..14] 10,11,20

V_DDR_MCH_REF

Non-iAMT

+3.3V_RUN

R211

12

10KOhm

5%

DESIGN ENGINEER :SCHEMATIC FILE NAME :

MLCC/+80-20%

12

C281

0.1UF/10V

+1.8V_SUS

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

0.1UF/10V

MLCC/+80-20%

+1.8V_SUS

0.1UF/10V

MLCC/+80-20%

+3.3V_RUN

MLCC/+/-10%

2.2UF/6.3V

pt_c0805_h53

12

C651

12

C327

12

C321

12

C315

12

C340

MLCC/+/-10%

STANLY_HSU

1

12

C275

2.2UF/6.3V

pt_c0805_h53

Please these Caps near So-Dimm1.

12

C300

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C333

12

C341

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Please these Caps near So-Dimm2.

12

C591

12

C331

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C619

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Please these Caps near So-Dimm1.

12

C325

0.1UF/10V

MLCC/+80-20%

0.1UF/10V

MLCC/+80-20%

C319

C323

0.1UF/10V

MLCC/+80-20%

12

12

Please these Caps near So-Dimm2.

12

C609

12

C616

0.1UF/10V

MLCC/+80-20%

12

C601

0.1UF/10V

MLCC/+80-20%

0.1UF/10V

MLCC/+80-20%

Non-iAMT

MLCC/+80-20%

12

C647

0.1UF/10V

1

12

C342

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C317

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

5

4

3

2

1

D D

+0.9V_DDR_VTT

12

C326

0.1UF/10V

MLCC/+80-20%

+0.9V_DDR_VTT

12

C332

0.1UF/10V

MLCC/+80-20%

C C

DDR_A_BS111,19

DDR_A_RAS#11,19

B B

Please these resistor
closely DIMMA, all
trace length<750 mil.

A A

DDR_A_BS211,19

DDR_A_BS011,19

DDR_A_WE#11,19
DDR_A_CAS#11,19

M_ODT010,19 M_ODT2 10,19
M_ODT110,19

DDR_CS0_DIMMA#10,19
DDR_CS1_DIMMA#10,19
DDR_CKE0_DIMMA10,19
DDR_CKE1_DIMMA10,19

Layout note : Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

12

12

12

12

DDR_A_MA[0..14]10,11,19 DDR_B_MA[0..14] 10,11,19

C305

C361

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

12

C355

C309

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

DDR_A_MA6
DDR_A_MA7

DDR_A_MA0
DDR_A_BS1

DDR_A_RAS#
DDR_A_MA13

DDR_A_MA4
DDR_A_MA2

DDR_A_MA3
DDR_A_MA5

DDR_A_MA9
DDR_A_MA12

DDR_A_BS2
DDR_A_MA8

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_B_MA4
DDR_B_MA5

M_ODT0 M_ODT2
DDR_A_MA1

C344

0.1UF/10V

MLCC/+80-20%

12

C338

0.1UF/10V

MLCC/+80-20%

RN21A
RN21B

RN25A
RN25B

RN27A
RN27B

RN23A
RN23B

RN18A
RN18B

RN16A
RN16B

RN17A
RN17B

RN32A
RN32B

RN31A
RN31B

RN26A
RN26B

R186 56Ohm5%
R194 56Ohm5%
R190 56Ohm5%
R188 56Ohm5%
R195 56Ohm5%
R181 56Ohm5%
R175 56Ohm5%

12

C359

0.1UF/10V

MLCC/+80-20%

12

C299

0.1UF/10V

MLCC/+80-20%

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

56Ohm

5%

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12
12
12
12
12
12
12

12

C314

0.1UF/10V

MLCC/+80-20%

12

C303

0.1UF/10V

MLCC/+80-20%

+0.9V_DDR_VTT

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

TOP

12

12

C358

C356

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

BOT

12

12

C306

C347

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

RN20A

12

56Ohm

RN20B

34

5%

56Ohm

RN15A

12

56Ohm

RN15B

34

5%

56Ohm

RN34A

12

56Ohm

RN34B

34

5%

56Ohm

RN29A

12

56Ohm

RN29B

34

56Ohm

5%

RN19A

12

56Ohm

RN19B

34

5%

56Ohm

RN28A

12

56Ohm

RN28B

34

5%

56Ohm

RN33A

12

56Ohm

RN33B

34

5%

56Ohm

RN22A

12

56Ohm

RN22B

34

5%

56Ohm

RN30A

12

56Ohm

RN30B

34

5%

56Ohm

RN24A

12

56Ohm

RN24B

34

56Ohm

5%

R191 56Ohm5%

12

R189 56Ohm5%

12

R182 56Ohm5%

12

R192 56Ohm5%

12

R193 56Ohm

12

R174 56Ohm

12

R178 56Ohm5%

12

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%
5%

12

C316

0.1UF/10V

MLCC/+80-20%

12

C360

0.1UF/10V

MLCC/+80-20%

DDR_B_MA6
DDR_B_MA7

DDR_B_MA14
DDR_B_MA11

DDR_B_BS1
DDR_B_MA0

DDR_B_MA13
DDR_B_RAS#

DDR_A_MA11
DDR_A_MA14

DDR_B_MA3
DDR_B_MA1

DDR_B_WE#
DDR_B_BS0

DDR_B_MA9
DDR_B_MA12

DDR_B_MA10
DDR_B_CAS#

DDR_B_MA2
DDR_B_MA8

12

C324

0.1UF/10V

MLCC/+80-20%

12

C320

0.1UF/10V

MLCC/+80-20%

DDR_B_BS1 11,19

DDR_B_RAS# 11,19

DDR_B_WE# 11,19
DDR_B_BS0 11,19

DDR_B_CAS# 11,19

M_ODT3 10,19
DDR_B_BS2 11,19
DDR_CS2_DIMMB# 10,19
DDR_CS3_DIMMB# 10,19
DDR_CKE2_DIMMB 10,19
DDR_CKE3_DIMMB 10,19

12

C328

0.1UF/10V

MLCC/+80-20%

12

C343

0.1UF/10V

MLCC/+80-20%

12

12

C348

C304

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

12

12

C354

C337

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

Please these resistor
closely DIMMB, all
trace length<750 mil.

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

20 69

4

DESCRIPTION:

DDR2 SO-DIMM (1)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

1

5

Non-iAMT

D D

C C

+3.3V_RUN+3.3V_RUN

R107

R122

10KOhm

10KOhm

5%

5%

/*

12

12

PCI_LOM

FSA

R118

R108

10KOhm

10KOhm

5%

5%

/*

/*

12

12

0=UMA
1=Disc. GRFX down

CLK_VGA_27M_NSS (VGA XTALIN) OPTION

+3.3V_RUN

R92

12

5%

+3.3V_RUN

Non-iAMT

PCI_PCCARD

10KOhm

Non-iAMT

Enable ITP

R112
10KOhm

5%

12

PCI_ICH

G7X NB8X

R97 147ohm 33 ohm
R105 84.5 ohm no-stuf
clk. voltage 1.2V 3.3V

+3.3V_RUN

B B

L16

21

330Ohm/100Mhz

MURATA/BLM21PG331SN1D

120 OHM@100MHz

L17

21

330Ohm/100Mhz

MURATA/BLM21PG331SN1D

12

C160

0.1UF/10V

MLCC/+80-20%

R65 2.2Ohm 5%

12

pt_r0603

120 OHM@100MHz

R117 2.2Ohm 5%

12

pt_r0603

R72 1Ohm 5%

12

A A

<Variant Name>

pt_r0603

PROJECT:

5

Discrest with Non-iAMT

+CK_VDD_MAIN

12

12

12

C78

C157

0.1UF/10V

MLCC/+80-20%

+CK_VDD_A

12

C130

0.1UF/10V

MLCC/+80-20%

+CK_VDD_48

12

C158

0.047UF/10V

MLCC/+/-10%

+CK_VDD_REF

0.1UF/10V

MLCC/+80-20%

12

C79

0.047UF/10V

MLCC/+/-10%

+CK_VDD_MAIN2

12

C161

0.1UF/10V

MLCC/+80-20%

C80

0.1UF/10V

MLCC/+80-20%

12

C84

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

10UF/10V

MLCC/+80-20%
pt_c0805_h53

12

C187

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C93

0.047UF/10V

MLCC/+/-10%

Lanai

12

C109

0.1UF/10V

MLCC/+80-20%

C202

REVISION

1.2

12

C204

10UF/10V

MLCC/+80-20%
pt_c0805_h53

DATE:
SHEET OF

4

CLK_ICH_48M17
CPU_MCH_BSEL07,10
CPU_MCH_BSEL17,10
CPU_MCH_BSEL27,10

CLK_ICH_14M17
CLK_PCI_502537

CLK_PCI_PCCARD32

NO.23

R105 84.5Ohm1% /*

12

CLK_VGA_27M_NSS22

CLK_PCI_ICH16

CLK_PWRGD17

NO.52

12

C172

C159

10PF/50V

10PF/50V

MLCC/+/-0.5PF

MLCC/+/-0.5PF

12

C194

10PF/50V

MLCC/+/-0.5PF

Monday, March 19, 2007

21 69

4

NO.6

R96 33Ohm 5%

12

R109 2.2KOhm 5%

12

R101 2.2KOhm 5%

12

NO.42

R74 33Ohm 5%

12

R82 33Ohm 5%

12

R93 33Ohm 5%

12

R97 33Ohm 5%

12

R98 33Ohm 5%

12

12

Place close to Clock Gen.

12

12

C115

C108

10PF/50V

10PF/50V

MLCC/+/-0.5PF

MLCC/+/-0.5PF

12

C177

10PF/50V

MLCC/+/-0.5PF

DESCRIPTION:

NO.23

R9533Ohm5%

CLK_ICH_48M
CLK_PCI_ICH
CLK_ICH_14M
CLK_PCI_5025

12

CLK_PCI_PCCARD

CLK_VGA_27M_NSS

3

X2

NO.24

C135
27PF/50V

MLCC/+/-5%

U7

1

VDDSRC1

49

VDDSRC2

54

VDDSRC3

65

VDDSRC4

30

VDDPCI1

36

VDDPCI2

12

VDDCPU

40

VDD48

18

VDDREF

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE

23

REF0/FSLC/TEST_SEL

22

REF1

27

PCI1

32

*PCI2/TME

33

PCI3

34

PCI4/FCTSEL1

43

DOTT_96/27MHz_NS

44

DOTC_96/27MHz_SS

37

PCI_F0/ITP_EN

39

CK_PWRGD/PD#

16

SMBCLK

17

SMBDAT

15

GNDCPU

31

GNDPCI1

35

GNDPCI2

21

GNDREF

4

GNDSRC1

42

GND48

68

GNDSRC2

73

GND

ICS9LPR333CKLFT

+3.3V_ALW

12

14.31818Mhz

+/-30ppm/20PF

CLK_XTAL_IN

12

+CK_VDD_MAIN2

+CK_VDD_MAIN
+CK_VDD_48
+CK_VDD_REF CPU_XTP
CLK_XTAL_IN

CLK_XTAL_OUT
FSA

FSB
FSC

CLKREF
PCI_SIO

PCI_PCCARD
PCI_LOM

27M_NSS
27M_SS

PCI_ICH

CLK_SCLK
CLK_SDATA

R71 0Ohm 5%

12

12

C126
27PF/50V

MLCC/+/-5%

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#
CPUT1_MCH

CPUC1_MCH

CPUT0
CPUC0

CPUT2_ITP/SRCT10

CPUC2_ITP/SRCC10

*PG_MODE

SRCT9
SRCC9

CLKREQ9#

SRCT8
SRCC8

CLKREQ8#

SRCT7
SRCC7

CLKREQ7#

SRCT6
SRCC6

CLKREQ6#

SRCT5
SRCC5

CLKREQ5#

SRCT4
SRCC4

CLKREQ4#

SRCT3
SRCC3

CLKREQ3#

SRCT2
SRCC2

CLKREQ2#

SRCT1/SATAT

SRCC1/SATAC

CLKREQ1#

LCD100/SRCT0

LCD100/SRCC0

NO.27

+3.3V_RUN

7
8

25
24

11
10

14
13

6
5

9
3

2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46

47
48

SMBus address D2

These are for
backdrive issue.

RN13A
RN13B

1

G

Q33

3

2

D

S

2N7002

12

+3.3V_RUN

1

G

Q32

3

2

D

S

2N7002

12

RELEASE DATE :

CKG_SMBDAT37

CKG_SMBCLK37

CLK GEN. CY28547

3

12

+3.3V_ALW

12

R124

2.2KOhm

5%

R134 0Ohm /*5%

R133

2.2KOhm

5%

R123 0Ohm /*5%

2

CLK_XTAL_OUT

14.318MHz

+CK_VDD_A

MCH_BCLK
MCH_BCLK#

CPU_BCLK
CPU_BCLK#

CPU_XTP#
PGMODE
PCIE_MINI1

PCIE_MINI1#
PCIE_MINI2

PCIE_MINI2#
PCIE_ICH

PCIE_ICH#
PCIE_VGA

PCIE_VGA#
PCIE_EXPCARD

PCIE_EXPCARD#
PCIE_LOM

PCIE_LOM#
MCH_3GPLL

MCH_3GPLL#
XDP_3GPLL

XDP_3GPLL#
PCIE_SATA

PCIE_SATA#

Non-iAMT

2.2KOhm 5%

2.2KOhm 5%

12

34

CLK_SDATA

CLK_SCLK

<OrgName>

2

1

PCIE_LOM_CLKREQ#

CLK_3GPLLREQ#
SATA_CLKREQ#
CARD_CLK_REQ#
MINI1CLK_REQ#
MINI2CLK_REQ#

PGMODE

R110 10KOhm 5%

12

R99 10KOhm 5%

12

R106 10KOhm 5%

12

R104 10KOhm 5%

12

R59 10KOhm 5%

12

R66 10KOhm 5%

12

R58 10KOhm

12

+3.3V_RUN

/*

5%

Populate for Napa platforms only

H_STP_PCI# 17

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

R10310KOhm5% /*

12

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

5%

34

33Ohm

5%

12

33Ohm

12

5%

34

33Ohm

5%

12

33Ohm

5%

34

22Ohm

5%

12

22Ohm

NO.40

RN2A
RN2B

RN3A
RN3B

RN4A
RN4B

RN5A
RN5B

RN1A
RN1B

RN6B
RN6A

RN7B
RN7A

RN8B
RN8A

RN9B
RN9A

RN10B
RN10A

R91475Ohm1%
RN12B
RN12A

RN11B

RN11A

FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RSVD 100 33

H_STP_CPU# 17
CLK_MCH_BCLK 9

CLK_MCH_BCLK# 9
CLK_CPU_BCLK 7

CLK_CPU_BCLK# 7
CLK_XDP 52

CLK_XDP# 52

+3.3V_RUN

CLK_PCIE_MINI1 50
CLK_PCIE_MINI1# 50
MINI1CLK_REQ# 50
CLK_PCIE_MINI2 50
CLK_PCIE_MINI2# 50
MINI2CLK_REQ# 50
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

CLK_PCIE_VGA 22
CLK_PCIE_VGA# 22

CLK_PCIE_EXPCARD 35
CLK_PCIE_EXPCARD# 35CLK_VGA_27M_SS22
CARD_CLK_REQ# 35
CLK_PCIE_LOM 47
CLK_PCIE_LOM# 47
PCIE_LOM_CLKREQ# 47
CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10
CLK_3GPLLREQ# 10
CLK_PCIE_XDP_3GPLL 52
CLK_PCIE_XDP_3GPLL# 52

CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15
SATA_CLKREQ# 17

Non-iAMT

Discrete

connect to XDP

PCI_LOM=FCTSEL1

FCTSEL1(PIN 34) Pin43 Pin44 Pin47 Pin48
0 = UMA DOT96T DOT96C 96/100M_T 96/100M_C
1 = Disc. 27Mout 27M_SSout SRCT0 SRCC0
GRFX down

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

1

5

PCIE_MTX_GRX_P[0:15]10

PCIE_MTX_GRX_N[0:15]10

PCIE_MRX_GTX_P[0:15]10

D D

C C

B B

PCIE_MRX_GTX_N[0:15]10

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0

PLTRST_DLEAY# connects to ICH8 GPO pin.

PCIE_MTX_GRX_P[0:15]

PCIE_MTX_GRX_N[0:15]

PCIE_MRX_GTX_P[0:15]

PCIE_MRX_GTX_N[0:15]

C219 0.1UF/10V

12

MLCC/+/-10%

C223 0.1UF/10V

12

MLCC/+/-10%

C210 0.1UF/10V

12

MLCC/+/-10%

C226 0.1UF/10V

12

MLCC/+/-10%

C222 0.1UF/10V

12

MLCC/+/-10%

C228 0.1UF/10V

12

MLCC/+/-10%

C216 0.1UF/10V

12

MLCC/+/-10%

C231 0.1UF/10V

12

MLCC/+/-10%

C255 0.1UF/10V

12

MLCC/+/-10%

C259 0.1UF/10V

12

MLCC/+/-10%

C233 0.1UF/10V

12

MLCC/+/-10%

C257 0.1UF/10V

12

MLCC/+/-10%

C238 0.1UF/10V

12

MLCC/+/-10%

C236 0.1UF/10V

12

MLCC/+/-10%

C234 0.1UF/10V

12

MLCC/+/-10%

C250 0.1UF/10V

12

MLCC/+/-10%

CLK_PCIE_VGA21
CLK_PCIE_VGA#21

PLTRST_DELAY#17

CLK_VGA_27M_NSS21

BXTALOUT25

SSFOUT25

CLK_VGA_27M_SS21

C220 0.1UF/10V

12

C224 0.1UF/10V

12

C209 0.1UF/10V

12

C227 0.1UF/10V

12

C221 0.1UF/10V

12

C229 0.1UF/10V

12

C215 0.1UF/10V

12

C230 0.1UF/10V

12

C256 0.1UF/10V

12

C260 0.1UF/10V

12

C232 0.1UF/10V

12

C258 0.1UF/10V

12

C239 0.1UF/10V

12

C237 0.1UF/10V

12

C235 0.1UF/10V

12

C249 0.1UF/10V

12

CLK_PCIE_VGA
CLK_PCIE_VGA#

PLTRST_DELAY#

NO_STUFF

NO_STUFF

12

NO.52

GND

C759
10PF/50V

MLCC/+/-0.5PF

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_MRX_GTX_R_P15
PCIE_MRX_GTX_R_N15

MLCC/+/-10%

PCIE_MRX_GTX_R_P14
PCIE_MRX_GTX_R_N14

MLCC/+/-10%

PCIE_MRX_GTX_R_P13
PCIE_MRX_GTX_R_N13

MLCC/+/-10%

PCIE_MRX_GTX_R_P12
PCIE_MRX_GTX_R_N12

MLCC/+/-10%

PCIE_MRX_GTX_R_P11
PCIE_MRX_GTX_R_N11

MLCC/+/-10%

PCIE_MRX_GTX_R_P10
PCIE_MRX_GTX_R_N10

MLCC/+/-10%

PCIE_MRX_GTX_R_P9
PCIE_MRX_GTX_R_N9

MLCC/+/-10%

PCIE_MRX_GTX_R_P8
PCIE_MRX_GTX_R_N8

MLCC/+/-10%

PCIE_MRX_GTX_R_P7
PCIE_MRX_GTX_R_N7

MLCC/+/-10%

PCIE_MRX_GTX_R_P6
PCIE_MRX_GTX_R_N6

MLCC/+/-10%

PCIE_MRX_GTX_R_P5
PCIE_MRX_GTX_R_N5

MLCC/+/-10%

PCIE_MRX_GTX_R_P4
PCIE_MRX_GTX_R_N4

MLCC/+/-10%

PCIE_MRX_GTX_R_P3
PCIE_MRX_GTX_R_N3

MLCC/+/-10%

PCIE_MRX_GTX_R_P2
PCIE_MRX_GTX_R_N2

MLCC/+/-10%

PCIE_MRX_GTX_R_P1
PCIE_MRX_GTX_R_N1

MLCC/+/-10%

PCIE_MRX_GTX_R_P0
PCIE_MRX_GTX_R_N0

MLCC/+/-10%

R423 22Ohm/* 5%

12

R417 0Ohm 5%/*

12

R414 0Ohm 5%

12

T101

12

GND

POPULATION OPTIONS

CY28547+SS

R414,R419,

Pop

A A

De-pop

R98

U5,R423,
R417,R416

CY28547+U5

R423,R417,
U5

R414,R416,
R419,R98

CY28547 wo/SS

R416,R419

U5,R98,
R414,R417,
R423

4

U21A

AF1

PEX_RX0

AG2

PEX_RX0_N

AG3

PEX_RX1

AG4

PEX_RX1_N

AF4

PEX_RX2

AF5

PEX_RX2_N

AG6

PEX_RX3

AG7

PEX_RX3_N

AF7

PEX_RX4

AF8

PEX_RX4_N

AG9

PEX_RX5

AG10

PEX_RX5_N

AF10

PEX_RX6

AF11

PEX_RX6_N

AG12

PEX_RX7

AG13

PEX_RX7_N

AG15

PEX_RX8

AG16

PEX_RX8_N

AF16

PEX_RX9

AF17

PEX_RX9_N

AG18

PEX_RX10

AG19

PEX_RX10_N

AF19

PEX_RX11

AF20

PEX_RX11_N

AG21

PEX_RX12

AG22

PEX_RX12_N

AF22

PEX_RX13

AF23

PEX_RX13_N

AG24

PEX_RX14

AG25

PEX_RX14_N

AG26

PEX_RX15

AF27

PEX_RX15_N

AD5

PEX_TX0

AD6

PEX_TX0_N

AE6

PEX_TX1

AE7

PEX_TX1_N

AD7

PEX_TX2

AC7

PEX_TX2_N

AE9

PEX_TX3

AE10

PEX_TX3_N

AD10

PEX_TX4

AC10

PEX_TX4_N

AE12

PEX_TX5

AE13

PEX_TX5_N

AD13

PEX_TX6

AC13

PEX_TX6_N

AC15

PEX_TX7

AD15

PEX_TX7_N

AE15

PEX_TX8

AE16

PEX_TX8_N

AC18

PEX_TX9

AD18

PEX_TX9_N

AE18

PEX_TX10

AE19

PEX_TX10_N

AC21

PEX_TX11

AD21

PEX_TX11_N

AE21

PEX_TX12

AE22

PEX_TX12_N

AD22

PEX_TX13

AD23

PEX_TX13_N

AF25

PEX_TX14

AE25

PEX_TX14_N

AE24

PEX_TX15

AD24

PEX_TX15_N

AE3

PEX_REFCLK

AE4

PEX_REFCLK_N

AC6

PEX_RST_N

B1

XTALIN

C2

1

BXTALOUT_R

SSFOUT_R

R419
10KOhm

5%

XTALOUT

C3

XTALOUTBUFF

C1

XTALSSIN

GF-GO7400-N-A3

R416
10KOhm

5% /*

12

NO_STUFF

GND

Layout comments: Place R423,R419 as close as
possible to C3. . Place R414,R416and R417 as close
as posisble to pin C1.

DVO/GPIO

PCI EXPRESS

DACsI2C

CLK

TEST

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

MIOB_CLKOUT

MIOB_CLKOUT_N

IFPAB_VPROBE

IFPCD_VPROBE

JTAG_TRST_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC

MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET
DACA_VREF

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CH_SCL

I2CH_SDA

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

TESTMODE

A9
D9
A10
B10
C10
C12
B12
A12
A13
B13
B15
A15
B16

G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3

G4
F1
G1
F2

R2
K2
K3

J4

AD4
AC4
AE1
AD2
AD1
U9
AD3

AB4

E6
F5
F4
D5
E4
L9
D6

E7

D10
E10
F9
F10
E9
D8
C7
B7

N6
M5

AE27
AD27
AE26
AD26
AD25
D7

AF13
AF14

3

1
1

GFX_BIA_PWM
ENVDD
PANEL_BKEN
GFX_CORE_CNTRL

1

THERM

R120 10KOhm 5%

R115 10KOhm 5%
R426 10KOhm 5%

1

R407 0Ohm 5%

12

R421 0Ohm 5%/*

12

SW_VREF

1

RAM_CFG0
RAM_CFG1

T104

1

12

DEVID2

R437 0Ohm 5%

DEVID0
DEVID1

1

PCI_IOBAR
RAM_CFG2
RAM_CFG3

1

DEVID3

3GIO_PADFG3

1

BAR2_SIZE
DEVID4

12

R443 10KOhm 5%

1

VGA_HSYNC
VGA_VSYNC
VGA_RED
VGA_BLU
VGA_GRN

DACA_RSET

R449 124Ohm 1%

DACAVREF

C524 0.01UF/16V

TV_C
TV_CVBS
TV_Y

DACB_RSET

R402 124Ohm 1%

DACBVREF

C100 0.01UF/16V

VGADDCCLK
VGADDCDAT
DVI_SCLK
DVI_SDATA
LCD_DDCCLK
LCD_DDCDAT
I2CH_SCL
I2CH_SDA

T11

1

T12

1

12

T110

1

T111

1

T109

1
12
12

T15

1

T14

1

T99
T4

T97
T1

T96

/*

T105

T107

T103

GND

T6

12

MLCC/+/-10%

12

MLCC/+/-10%

BIA_PWM 28
ENVDD 28
PANEL_BKEN 38
GFX_CORE_CNTRL 58

NO.56

THERMTRIP_VGA#

SW_VREF 26,27
YPRPB_DET# 50

RAM_CFG0 25
RAM_CFG1 25
GFX_DEVID2 38
DEVID2 25
DEVID0 25
DEVID1 25

PCI_IOBAR
RAM_CFG2 25
RAM_CFG3 25

DEVID3 25

3GIO_PADFG3 25

DEVID4 25

12

GND

GND

12

GND

GND

GND

GND

GND

GFX_CORE_CNTRL:
PU on page55

THERMTRIP_VGA# 43

NO.23

MIOB2

MIOB6

MIOB_HSYNC

MIOBD7

MIOB_DE

Place near GPU

Place near GPU

Note:Populate R421 for the platform
that use internal G72 Thermal Sensor

G72M

G8XM

CRYSTALA0 CRYSTAL

CRYSTALA1 TVMODE2

- 3GIO_PADFG3

MIOBLE_GPIO0PC_IOBAR

BAR2_SIZE

-

VGAHSYNC 50
VGAVSYNC 50
VGA_RED 50
VGA_BLU 50
VGA_GRN 50

G_CLK_DDC2 50
G_DAT_DDC2 50
DVI_SCLK
DVI_SDATA
LCD_DDCCLK 28
LCD_DDCDAT 28

VGA_RED
VGA_BLU
VGA_GRN

TV_C
TV_CVBS
TV_Y

R452

150Ohm

12

1%

GND GND GND

R76

150Ohm

12

1%

2

THERMTRIP_VGA# OPTIONS

G86

R407

R421,R405

G72GLM

G72M

G72MV

G86M 0 111

VGA_RED 50
VGA_BLU 50
VGA_GRN 50

TV_C 50
TV_CVBS 50
TV_Y 50

R421,R405Pop

De-pop

DEFAULT

0
0

1
0

R451

150Ohm

12

1%

R69

150Ohm

12

1%

GNDGND GND

G72M

R407

STRAP

NOT REQUIRED

NOT REQUIRED

NOT REQUIRED

NOT REQUIRED

NOT REQUIRED

R450

150Ohm

12

1%

R75

150Ohm

12

1%

1

SW_VREF

GFX_BIA_PWM

PCI_IOBAR

R415

12

2KOHM

5%

GND

R420

12

10KOhm

5%

GND

R440

/*

12

2KOHM

5%

GND

G72xx/ G8x

MIOBD11 MIOBD3 MIOBD5 MIOBD4

DEVID0DEVID1DEVID2DEVID3

1

1

1

0

00

00

11 10

DVI PULL HIGH CLOSE TO GPU

LCD_DDCCLK

LCD_DDCDAT

DVI_SCLK

DVI_SDATA

I2CH_SCL

I2CH_SDA

THERM

BAR2_SIZE

R408

12

2.2KOhm 5%
R412

12

2.2KOhm 5%
R411

12

2.2KOhm 5%
R48

12

2.2KOhm 5%
R404

12

10KOhm 5% /*
R403

12

10KOhm 5% /*

NO.56

R405

12

2.2KOhm 5% /*
R431

12

2.2KOhm 5% /*

+3.3V_RUN

'U5'indicate all ckt.related to U5 in Page.25

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

22 69

4

DESCRIPTION:

G72M/G8X CORE PCIE

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

Sean Kuo

1

5

+VCC_GFX_CORE

12

C116

0.022UF/16V

MLCC/+/-10%

12

C128

0.1UF/10V

MLCC/+/-10%

12

C140

0.022UF/16V

MLCC/+/-10%

12

C112

0.1UF/10V

MLCC/+/-10%

12

REVISION

12

C133

0.022UF/16V

MLCC/+/-10%

12

C184

0.1UF/10V

MLCC/+/-10%

12

C146

0.1UF/10V

MLCC/+/-10%

12

12

C101

0.1UF/10V

MLCC/+/-10%

1.2

12

C171
220PF/50V

MLCC/+/-10%

C110

0.1UF/10V

MLCC/+/-10%

12

C190

0.1UF/10V

MLCC/+/-10%

12

C156

0.1UF/10V

MLCC/+/-10%

GND

DATE:
SHEET OF

12

C515
10UF/4V

MLCC/+/-20%
pt_c0805

D D

GND

12

C166

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

GND

C139

C131

GND

+3.3V_RUN

12

C167
4700PF/25V

MLCC/+/-10%

12

C179
4700PF/25V

MLCC/+/-10%

12

GND

C C

+1.8V_RUN

12

4700PF/25V

MLCC/+/-10%

+1.8V_RUN

12

B B

4700PF/25V

MLCC/+/-10%

A A

<Variant Name>

12

C514
10UF/4V

MLCC/+/-20%
pt_c0805

12

C117
10UF/4V

MLCC/+/-20%
pt_c0805

C123
4700PF/25V

MLCC/+/-10%

12

C151

0.022UF/16V

MLCC/+/-10%

GND

12

C120

0.022UF/16V

MLCC/+/-10%

12

C150

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

GND

12

C138

0.1UF/10V

MLCC/+/-10%

12

C141

0.1UF/10V

MLCC/+/-10%

C113
4700PF/25V

MLCC/+/-10%

12

C148

0.022UF/16V

MLCC/+/-10%

12

C147

0.1UF/10V

MLCC/+/-10%

IFPC_IOVDD

PROJECT:

5

12

C186

0.1UF/10V

MLCC/+/-10%

12

C144

0.1UF/10V

MLCC/+/-10%

12

C185
2200PF/50V

MLCC/+/-10%

12

C155

0.1UF/16V

MLCC/+/-10%

12

C104
4700PF/25V

MLCC/+/-10%

12

C121

0.022UF/16V

MLCC/+/-10%

12

C111

0.022UF/16V

MLCC/+/-10%

R87
10KOhm 5%

Lanai

4

12

12

12

12

C183
2200PF/50V

MLCC/+/-10%

C173

0.022UF/16V

MLCC/+/-10%

C162

0.022UF/16V

MLCC/+/-10%

C91

0.1UF/10V

MLCC/+/-10%

12

C129

0.1UF/10V

MLCC/+/-10%

12

MLCC/+/-10%

12

C168

0.1UF/10V

12

C154

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

G72_PLLVDD

C506

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C92

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

FBVDD_Q

12

C90

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

Stuff for G72 ; L10 No-Stuff for G8X

+1.25V_GFX_PCIE

NO.23

L10

120Ohm/100Mhz

pt_l0603
/*

G72_PLLVDD

21

12

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

GND

Monday, March 19, 2007

23 69

4

C137

U21D

J9

VDD_0

J10

VDD_1

J11

VDD_2

L12

VDD_3

L13

VDD_4

L15

VDD_5

L16

VDD_6

M9

VDD_7

M11

VDD_8

M12

VDD_9

M13

VDD_10

M14

VDD_11

M15

VDD_12

M16

VDD_13

M17

VDD_14

N9

NV_PLLAVDD

N11

VDD_16

N17

VDD_17

R9

VDD_18

R11

VDD_19

R17

VDD_20

T9

VDD_21

T11

VDD_22

T12

VDD_23

T13

VDD_24

T14

VDD_25

T15

VDD_26

T16

VDD_27

T17

VDD_28

U12

VDD_29

U13

VDD_30

U15

VDD_31

U16

VDD_32

W13

VDD_33

W15

VDD_34

W16

VDD_35

W9

VDD_LP_0

W10

VDD_LP_1

W11

VDD_LP_2

W12

VDD_LP_3

F13

VDD33_0

F14

VDD33_1

J12

VDD33_2

J13

VDD33_3

J15

VDD33_4

J16

VDD33_5

E15

FBVTT_0

F15

FBVTT_1

F16

FBVTT_2

J17

FBVTT_3

J18

FBVTT_4

L19

FBVTT_5

N19

FBVTT_6

R19

FBVTT_7

U19

FBVTT_8

W19

FBVTT_9

F17

FBVDDQ_0

F19

FBVDDQ_1

J19

FBVDDQ_2

J22

FBVDDQ_3

L22

FBVDDQ_4

M19

FBVDDQ_5

P22

FBVDDQ_6

T19

FBVDDQ_7

U22

FBVDDQ_8

Y22

FBVDDQ_9

GF-GO7400-N-A3

12

C145

0.1UF/10V

MLCC/+/-10%

GND

DESCRIPTION:

3

W17

PEX_IOVDD_0

W18

PEX_IOVDD_1

AB10

PEX_IOVDD_2

AB11

PEX_IOVDD_3

AB14

PEX_IOVDD_4

AB15

PEX_IOVDD_5

AB20

PEX_IOVDD_6

AB21

PEX_IOVDD_7

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD

DACA_VDD
DACB_VDD

PLLVDD

NC_5

NC_4

NO.23

21

21

AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20

Y6
AA5

K5
K6
L6

J5

F6
G6
J6

W4
Y4
L4

V5
M4
AE2

F8

H4
D13
D14
D15

D11

L12

120Ohm/100Mhz

pt_l0603 /*

L11

120Ohm/100Mhz

pt_l0603

L34

21

120Ohm/100Mhz

pt_l0603

3

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18

PEX_PLLAVDD
PEX_PLLDVDD

POWER

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2

MIOBCAL_PD_VDDQ

MIO_A_VDDQ_0

MIO_A_VDDQ_1

MIO_A_VDDQ_2

IFPAB_PLLVDD
IFPCD_PLLVDD

FBA_PLLAVDD

FBCAL_PD_VDDQ

+2.5V_RUN

+1.25V_GFX_PCIE

+1.25V_GFX_PCIE

G72M/G8X POWER

PEX_IOVDD_Q

12

12

PEX_PLL_AVDD
PEX_PLL_DVDD

+3.3V_RUN

12

C127

0.1UF/10V

T7

1

MLCC/+/-10%

+3.3V_RUN

GND

12

C122

0.1UF/10V

MLCC/+/-10%

IFPA_IOVDD

GND GN D

IFPB_IOVDD
IFPC_IOVDD

IFPAB_PLLVDD
IFPCD_PLLVDD
DACA_VDD

DACB_VDD

G7XM G8XM G3-64 BALL

PLLVDD
FBA_PLLAVDD
H_PLLVDD

R68 45.3Ohm 1%

PLLVDD/2.5V PLLVDD/1.2V H4

FBA_PLLVDD H_PLLVDD D14

NO.23

12

1

12

C134

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C512

1000PF/50V

MLCC/+/-10%

+1.8V_RUN

Nvidia Document
PUN-02005-001_v08
FOR DDR3 FBCAL_PD_VDDQ:

T5

50 ohm

For G86: 40ohm for GDDR3
per PUN-02737-001_v02
For G86 A2: 01/05 change
to 45.3 ohm.

Pop L12 de-pop L11 for NV G72

Pop L11 de-pop L12 for G8XM

12

C119

1UF/6.3V

MLCC/+/-10%

12

C513

0.1UF/10V

MLCC/+/-10%

12

C199

C188

0.1UF/10V

0.1UF/10V

MLCC/+/-10%

MLCC/+/-10%

12

C203

C181

0.022UF/16V

0.022UF/16V

MLCC/+/-10%

MLCC/+/-10%

12

C527

0.01UF/16V

MLCC/+/-10%

12

C170

470PF/50V

MLCC/+/-10%

GND

NO.43

12

C118

470PF/50V

MLCC/+/-10%

GND

12

C510

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

GND

RELEASE DATE :

12

12

12

C520

0.01UF/16V

MLCC/+/-10%

GND

12

C528

0.1UF/10V

MLCC/+/-10%

12

C169

1UF/6.3V

MLCC/+/-10%

PLLVDD

40 mA

FBA_PLLAVDD

C213

0.1UF/10V

MLCC/+/-10%

C195

0.1UF/10V

MLCC/+/-10%

12

1UF/6.3V

MLCC/+/-10%

12

NO.23

2

12

C191

0.1UF/10V

MLCC/+/-10%

12

C180

0.1UF/10V

MLCC/+/-10%

12

C523

0.1UF/10V

MLCC/+/-10%

C526

C175

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

H_PLLVDD

2

12

C525

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

12

C205

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C208

0.1UF/10V

MLCC/+/-10%

12

C522

1UF/6.3V

MLCC/+/-10%

+1.25V_GFX_PCIE

L37

21

10NH

pt_l0603

+1.8V_RUN

L14

21

220Ohm/100Mhz

pt_l0603

12

C508

0.1UF/10V

MLCC/+/-10%

GND

Pop L13 de-pop L15 for
NV G72

Pop L15 de-pop L13 for
NV G8X

IFPAB_PLLVDD

IFPCD_PLLVDD

DESIGN ENGINEER :SCHEMATIC FILE NAME :

12

C189
10UF/10V

MLCC/+80-20%
pt_c0805_h53

GND

12

C174

0.1UF/10V

MLCC/+/-10%

12

C521

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

The update mainly baes
on the Nvidia document
"PUN-02005-001_v06(G72)"

L32

21

220Ohm/100Mhz

pt_l0603

C507

4.7UF/6.3V

MLCC/+/-10%

L/C CIRCUIT POWER RAIL

pt_c0603

FOR G8XM DESIGN

12

C149

470PF/50V

MLCC/+/-10%

R90
10KOhm 5%

12

C132

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

+1.25V_GFX_PCIE

L36

21

10NH

pt_l0603

+3.3V_RUN

L38

120Ohm/100Mhz

pt_l0603

L33

120Ohm/100Mhz

pt_l0603

+1.25V_GFX_PCIE

12

C165
1UF/6.3V

MLCC/+/-10%

12

GND

Sean Kuo

+1.25V_GFX_PCIE

12

C212
10UF/10V

MLCC/+80-20%
pt_c0805_h53

GNDGND

21

12

C531

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

21

12

C509

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C142

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

GND

1

12

C530

1UF/6.3V

MLCC/+/-10%

12

C95
1UF/6.3V

MLCC/+/-10%

NO.23

L15

21

120Ohm/100Mhz

pt_l0603

L13

21

120Ohm/100Mhz

pt_l0603 /*

1

DACA_VDD

12

C529

470PF/50V

MLCC/+/-10%

GND

DACB_VDD

12

C103

470PF/50V

MLCC/+/-10%

GND

+1.8V_RUN

+2.5V_RUN

5

D D

4

3

2

1

U21E

B2

GND_0

B5

GND_1

B8

GND_2

B11

GND_3

B14

GND_4

B17

GND_5

G7XM G8XM G3-64 BALL

GND I2SC_SDA F11

+3.3V_RUN

NO.23

R47

I2CS_SDA

12

2.2KOhm

GND

5%

R50 0Ohm 5%

12

/*

I2CS_SDAI2CS_SDA

GND GND

C C

B B

B20
B23
B26

E2
E5

E8
E11
E14
E17
E20
E23
E26
F11

H2

H6
H23
H26

J14

K9

K19

L2

L5
L11
L14
L17
L23
L26

N12
N13
N14
N15
N16

P2

P5

P9
P11
P12
P13
P14
P15
P16
P17
P19
P23
P26

R12
R13
R14
R15
R16

U2

U5
U11
U14

GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59

GF-GO7400-N-A3

GND

IFPAB_PLLGND
IFPCD_PLLGND

MIOBCAL_PU_GND

PEX_PLLGND

FBA_PLLGND

FBCAL_PU_GND

FBCAL_TERM_GND

GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94

PLLGND

U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26

V6
M6

M3
AA6
H5

C15

E13
H22

T106

1

NO.43

R410 24.9Ohm 1%

12

R413 40.2Ohm 1%

12

GND

UPDATE FROM NVIDIA UPDATED NOTIFICATION
PUN-02005-001_v08(G72)
FBCAL_PU_GND: 30 OHM
FBCAL_TERM_GND: 40 OHM

01/05 for G86 A2: change R410 to 24.9
ohm from 30 ohm

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

24 69

4

DESCRIPTION:

G7XM/G8X CORE GND

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Sean Kuo

1

A

B

C

D

E

NV44M

1 1

+3.3V_RUN

NO.23

R89

R432

R430

10KOhm

10KOhm

5%

5%

12

12

RAM_CFG022
RAM_CFG122
RAM_CFG222
RAM_CFG322
SUB_VENDOR26
3GIO_ADR_026
3GIO_ADR_126
3GIO_ADR_226

2 2

3GIO_PADFG322

PEX_PLL_EN_TERM10026
DEVID422

DEVID322
DEVID222
DEVID122
DEVID022

3 3

Internal Pull-down
MIOAD0, MIOAD6,
MIOAD8, MIOAD9

MIOAD1----SUB_VENDOR

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
SUB_VENDOR
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2

3GIO_PADFG3

NEW STRAP FOR G8XM

PEX_PLL_EN_TERM100
DEVID4

DEVID3
DEVID2
DEVID1
DEVID0

NO STUFF

NO STUFF

R436

/*

10KOhm

5%

12

12

0, SYSTEM BIOS

R433
10KOhm

5%

MIOAD0----PEX_PLL_EN_TERM

MIOAD6----3GIO_ADR_0
MIOAD8----3GIO_ADR_1

4 4

MIOAD9----3GIO_ADR_2

[2:0] 001 for NV43/NV44
010 for G7x, NV42

R444

N/A

R445

/*

10KOhm

10KOhm

5%

5%

12

12

NO STUFF

NO STUFF

/*

R448

R442

10KOhm

10KOhm

5%

5%

12

12

/*

12

R422
2KOHM

5%

12

GND

MIOBD4----PCI_DEVID0
MIOBD5----PCI_DEVID1
MIOBD3----PCI_DEVID2
MIOBD11---PCI_DEVID3

R86

R83
2KOHM

2KOHM

5%

5%

12

NO STUFF

1000,G72M
0111,G72MV

/*

/*

NO STUFF

R77

2KOHM

2KOHM

5%

5%
12

12

NO STUFF

/*

R429

/*

2KOHM

5%

12

NO STUFF

NO STUFF

R447

R438

2KOHM

2KOHM

5%

5%

12

12

/*

R439

R441

2KOHM

2KOHM

5%

5%

12

12

BXTALOUT22

SSFOUT22

R44

/*

10KOhm

12

5%

GND

R428

/*

2KOHM

5%

12

NO STUFF

SS OPTIONS for GFX Memory

BXTALOUT

12

R49 22Ohm

STRAPS PIN DESCRIPTION Value

Parallel=00, SERIAL AT25F=01
DEFAULT,Serial SST45VF=10, LPC=11

8Mx32 DDR monolithic (32bit)
300MHz,1.8V
4Mx32 DDR generic (64bit)

FOR

1.8V I/O

GDDR1

4Mx32 DDR generic (32bit)

1.8V I/O

Infineon 8Mx32
500MHz, 1.8V

Hynix 8Mx32
500MHz, 1.8V

FOR

Samsung 8Mx32

GDDR3

500MHz, 1.8V

Infineon 16Mx32 GDDR3 ,1.8V

Hynix 16Mx32 GDDR3 1.8V

Samsung 16Mx32 GDDR3 1.8V

+3.3V_RUN

12

R36

R37

10KOhm

12

5%

/*

/*

10KOhm

12

5%

C46

/*

10UF/10V

MLCC/+80-20%
pt_c0805_h53

-1.75% (DOWN)

0.875% (CENTER)

SO Internal pull up

/*5%

ROM_TYPE[1:0]

SUB_VENDOR

PEX_PLL_TERM

RAM_CFG[3:0]

U5

/*

1

XIN/CLKIN
VSS
SRS
ModOUT REF

P1819B-08SR

XOUT

VDD
PD#

2
3
45

GND

MIOBD10
MIOB_VSYNC

MIOAD1

MIOAD0

MIOBD0
MIOBD1
MIOBD8
MIOBD9

8
7
6

12

C45

0.1UF/10V

MLCC/+/-10%

GND

L6

/*

21

120Ohm/100Mhz

pt_l0603
/*

01

0

0

1001

0100

1100

0101

0111

0110

0001

0010

0011

+3.3V_RUN

S0

0

1

M08 HAS REMOVED THIS PORTION
INSTALL OR NOT?

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

25 69

B

DESCRIPTION:

G72M/G8X STRAPPING PAGE

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Sean Kuo

E

5

D D

FBAD[0..63]27

C C

B B

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

AB23
AB24

AB22
AC24
AC22
AA23
AA22

AA24
AA27
AA26
AB25
AB26
AB27
AA25

W25

A26
C24
B24
A24
C22
A25
B25
D23
G22

J23
E24
F23

J24
F24
G23
H24
D16
E16
D17
F18
E19
E18
D20
D19
A18
B18
A19
B19
D18
C19
C16
C18
N26
N25
R25
R26
R27
T25
T27
T26

Y24

T24
T23
R24
R23
R22
T22
N23
P24

U21B

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

GF-GO7400-N-A3

MEMORY INTERFACE

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1
FBA_CLK1_N
FBA_REFCLK

FBA_REFCLK_N

FBA_DEBUG

G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24

D21
F22
F20
A21
V27
W22
V22
V24

A22
E22
F21
B21
V26
W23
V23
W27

B22
D22
E21
C21
V25
W24
U24
W26

A16
L24

K23
M22
N22
M23
M24
K22

4

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQSR#0
FBADQSR#1
FBADQSR#2
FBADQSR#3
FBADQSR#4
FBADQSR#5
FBADQSR#6
FBADQSR#7

FBADQSW0
FBADQSW1
FBADQSW2
FBADQSW3
FBADQSW4
FBADQSW5
FBADQSW6
FBADQSW7

FB_VREF1
FBA_CLK0

FBA_CLK0#
FBA_CLK1
FBA_CLK1#

15 mil

1

T10

1

T8

G7XM G8XM G3-64 BALL

FBA_REFCLK FBA_CMD27 M23

1

FBA_REFCLK_N N/A M24

T2

SW_VREF22,27

FBA_CMD[0..26] 27

FBADQM[0..7] 27

FBADQSR#[0..7] 27

FBADQSW[0..7] 27

FBA_CLK0 27
FBA_CLK0# 27
FBA_CLK1 27
FBA_CLK1# 27

NO.43

R418
475Ohm

1%

12

3

D

Q57

1

2N7002

G

S

2

3

VREF=VDDQ x Rb (Ra+Rb)

VREF=1.26V=0.7 x VDDQ

+1.8V_RUN

R424

Ra

511Ohm

12

1%

15mil

12

12

C511

Rb

0.022UF/16V

1.18KOhm

MLCC/+/-10%

1%

GND

R425

2

U21C

T4

IFPA_TXC

U4

IFPA_TXC_N

N4

IFPA_TXD0

N5

IFPA_TXD0_N

R5

IFPA_TXD1

R4

IFPA_TXD1_N

T5

IFPA_TXD2

T6

IFPA_TXD2_N

R6

IFPA_TXD3

P6

IFPA_TXD3_N

W5

IFPB_TXC

W6

IFPB_TXC_N

W3

IFPB_TXD4

W2

IFPB_TXD4_N

AA2

IFPB_TXD5

AA3

IFPB_TXD5_N

AB1

IFPB_TXD6

AA1

IFPB_TXD6_N

AB3

IFPB_TXD7

AB2

IFPB_TXD7_N

U6

IFPAB_RSET

V1

IFPC_TXC

W1

IFPC_TXC_N

T1

IFPC_TXD0

R1

IFPC_TXD0_N

T3

IFPC_TXD1

T2

IFPC_TXD1_N

V2

IFPC_TXD2

V3

IFPC_TXD2_N

J3

IFPCD_RSET

R435

/*

GF-GO7400-N-A3

1KOhm

5%

12

LVDS/TMDS

MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9

MIO_A_D10

NC

MIO_A_HSYNC

NC_0
NC_1
NC_2
NC_3

BUFRST_N

STEREO

SWAPRDY

GENERALSERIAL

THERMDN
THERMDP

ROM_SCLK

ROM_SI

ROM_SO

ROMCS_N

PEX_PLL_EN_TERM100

A2

SUB_VENDOR

B3
A3
D4
A4
B4

3GIO_ADR_0

B6
P4

3GIO_ADR_1

C6

3GIO_ADR_2

G5
V4

MIOA_HSYNC

C4

D12
E12

I2CS_SCL

F12
C13

A6

F7
A7

C9
B9

D2
F3
D3
D1

T3

1

T102

1

T98

1

T100

1

T9

1

T108

1

+3.3V_RUN R78

R406

12

2.2KOhm

5%

12

NO.23

R409

10KOhm

5%

G7XM G8XM G3-64 BALL

NC I2SC_SCL F12

STEREO DACB_CSYNC F7

NC GPIO13 C13

NC GPIO14 E12

GND

LCD_ACLK+
LCD_ACLK-

LCD_A0+
LCD_A0­LCD_A1+
LCD_A1­LCD_A2+
LCD_A2-

LCD_BCLK+
LCD_BCLK-

LCD_B0+
LCD_B0­LCD_B1+
LCD_B1­LCD_B2+
LCD_B2-

12

R446 1KOhm

/*

5%

LCD_ACLK+28
LCD_ACLK-28
LCD_A0+28
LCD_A0-28
LCD_A1+28
LCD_A1-28
LCD_A2+28
LCD_A2-28

LCD_BCLK+28
LCD_BCLK-28
LCD_B0+28
LCD_B0-28
LCD_B1+28
LCD_B1-28
LCD_B2+28
LCD_B2-28

DVI NO STUFF

GND

1

PEX_PLL_EN_TERM100 25
SUB_VENDOR 25

3GIO_ADR_0 25
3GIO_ADR_1 25

3GIO_ADR_2 25

10KOhm5%/*

R78:Confirm need to

12

no stuff not for G72

GND

and G86.

VGA_THERMDN 43
VGA_THERMDP 43

GND

STUFF FOR G74

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

26 69

4

DESCRIPTION:

G72M/G8X FBA/LVDS

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

Sean Kuo

1

5

FBAD[0..63]26

NO.43 NO.43

R67

12

243Ohm

1%

D D

+1.8V_RUN

GND

C C

GND

GND

B B

A A

<Variant Name>

3

1

G

2

GND

Close to memory
VREFA1=0.7*VDDQ

for 136pin

FBA_CLK0
FBA_CLK0#

12

12

C102

C63

100PF/50V

100PF/50V

MLCC/+/-5%

MLCC/+/-5%

GND

12

12

12

12

12

GND GND

SW_VREF 22,26

VREF_SW_A1

D

S

VREF_SW_A1

C106

C99

0.1UF/10V

0.1UF/10V

MLCC/+/-10%

MLCC/+/-10%

12

C59

C58

0.01UF/16V

0.01UF/16V

MLCC/+/-10%

MLCC/+/-10%

12

C52

C105

1000PF/50V

470PF/50V

MLCC/+/-10%

MLCC/+/-10%

12

C88

C96

100PF/50V

470PF/50V

MLCC/+/-5%

MLCC/+/-10%

+1.8V_RUN

NO.43

R64

12

475Ohm

1%

Q19
2N7002

Close to memory
VREFA1=0.7*VDDQ
for 136pin

NO.43 NO.43

R79

12

475Ohm

1%

STUFF FOR G74

+1.8V_RUN

12

C97

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C57

0.1UF/10V

MLCC/+/-10%

PROJECT:

5

12

12

12

12

1000PF/50V

MLCC/+/-10%

12

GND

C89

C48

4.7UF/6.3V

0.1UF/10V

MLCC/+/-10%

MLCC/+/-10%

pt_c0603

12

C65

C74

4.7UF/6.3V

0.01UF/16V

MLCC/+/-10%

MLCC/+/-10%

pt_c0603

12

C62

C107

0.01UF/16V

MLCC/+/-10%

C85
470PF/50V

MLCC/+/-10%

R61

511Ohm

12

1%

NO.56

12

12

R57

C49

0.01UF/16V

1.18KOhm

MLCC/+/-10%

1%

+1.8V_RUN

R80

511Ohm

12

1%

12

R81

1.18KOhm

1%

GND

Place below decoupling caps close VDD pin.

12

C76

0.1UF/10V

MLCC/+/-10%

Lanai

NO.56

12

C114

0.01UF/16V

MLCC/+/-10%

FBAD26
FBAD27
FBAD29
FBAD28
FBAD24
FBAD30
FBAD31
FBAD25
FBAD5
FBAD1
FBAD3
FBAD2
FBAD0
FBAD4
FBAD6
FBAD7
FBAD9
FBAD14
FBAD15
FBAD11
FBAD13
FBAD12
FBAD10
FBAD8
FBAD20
FBAD18
FBAD23
FBAD21
FBAD17
FBAD16
FBAD22
FBAD19

GND

VREFA0
VREFA2

12

C64

0.1UF/10V

MLCC/+/-10%

REVISION

1.2

U20

T3

DQ31

T2

DQ30

R3

DQ29

R2

DQ28

M3

DQ27

N2

DQ26

L3

DQ25

M2

DQ24

T10

DQ23

T11

DQ22

R10

DQ21

R11

DQ20

M10

DQ19

N11

DQ18

L10

DQ17

M11

DQ16

G10

DQ15

F11

DQ14

F10

DQ13

E11

DQ12

C10

DQ11

C11

DQ10

B10

DQ9

B11

DQ8

G3

DQ7

F2

DQ6

F3

DQ5

E2

DQ4

C3

DQ3

C2

DQ2

B3

DQ1

B2

DQ0

A1

VDDQ1

C1

VDDQ2

E1

VDDQ3

N1

VDDQ4

R1

VDDQ5

U1

VDDQ6

C4

VDDQ7

E4

VDDQ8

J4

VDDQ9

N4

VDDQ10

R4

VDDQ11

C9

VDDQ12

E9

VDDQ13

J9

VDDQ14

N9

VDDQ15

R9

VDDQ16

A12

VDDQ17

C12

VDDQ18

E12

VDDQ19

N12

VDDQ20

R12

VDDQ21

U12

VDDQ22

B1

VSSQ1

D1

VSSQ2

P1

VSSQ3

T1

VSSQ4

G2

VSSQ5

L2

VSSQ6

B4

VSSQ7

D4

VSSQ8

P4

VSSQ9

T4

VSSQ10

B9

VSSQ11

D9

VSSQ12

P9

VSSQ13

T9

VSSQ14

G11

VSSQ15

L11

VSSQ16

B12

VSSQ17

D12

VSSQ18

P12

VSSQ19

T12

VSSQ20

G1

VSS1

L1

VSS2

A3

VSS3

U3

VSS4

A10

VSS5

U10

VSS6

G12

VSS7

L12

VSS8

H1

VREF1

H12

VREF2

K4J52324QE-BC14

12

C83

0.01UF/16V

MLCC/+/-10%

DATE:
SHEET OF

4

FBA_CMD1

H3

BA2

RAS#

FBA_CMD10

F4

CS

CAS#

FBA_CMD11

H9

CKE

WE#

FBA_CMD8

F9

CAS

CS#

MF= 0MF= 1

FBA_CMD19

K4

A4

A0

FBA_CMD25

H2

A5

A1

FBA_CMD22

K3

A6

A2

FBA_CMD24

M4

A9

A3

FBA_CMD0

K9

A0

A4

FBA_CMD2

H11

A1

A5

FBA_CMD21

K10

A2

A6

FBA_CMD16

L9

A11

A7

FBA_CMD23

K11

A10

A8/AP

FBA_CMD20 FBA_CMD6

M9

A9

A3

A8/AP

A7

BA1
BA0
RAS

WE

RESET

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

VDDA1
VDDA2

VSSA1
VSSA2

12

C77

0.01UF/16V

MLCC/+/-10%

RFU1
RFU2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

CKE

SEN

DM3
DM2
DM1
DM0

FBA_CMD17

K2

A10

FBA_CMD9

L4

A11

FBA_CMD12

G4

BA0

FBA_CMD3

G9

BA1

FBA_CMD7

H10

BA2

FBA_CMD18

H4

FBA_CLK0

J11

CK

FBA_CLK0#

J10

CK#

J2
J3
U4

FBA_CMD15

U9
A9

MF

A4

ZQ

FBADQSW3

P2

FBADQSW0

P11

FBADQSW1

D11

FBADQSW2

D2

FBADQSR#3

P3

FBADQSR#0

P10

FBADQSR#1

D10

FBADQSR#2

D3

FBADQM3

N3

FBADQM0

N10

FBADQM1

E10

FBADQM2

E3

F1
M1
A2
U2
A11
U11
F12
M12

K1
K12

J1
J12

GND

12

C87

1000PF/50V

MLCC/+/-10%

Monday, March 19, 2007

27 69

4

12

R56 240Ohm 1%

pt_r0603

+1.8V_RUN

FBA_VDDA0
FBA_VDDA1

12

C98

0.047UF/16V

MLCC/+/-10%

12

470PF/50V

MLCC/+/-10%

3

FBAD[0..63]26FBA_CMD[0..26] 26

FBA_CMD18

R63

10KOhm

12

GND

FBA_CMD15

R62

10KOhm

12

GND

FBA_CLK0 26
FBA_CLK0# 26

GND

GND

GND

FBADQSW[0..7] 26 FBADQSW[0..7] 26

GND

FBADQSR#[0..7] 26

GND

FBADQM[0..7] 26

L7 180Ohm

L9 180Ohm

12

C51

0.047UF/16V

MLCC/+/-10%

C66

+1.8V_RUN

pt_l0603

21
21

pt_l0603

12

C86

100PF/50V

MLCC/+/-5%

GND

DESCRIPTION:

VGA GDDR3 16MX32

3

Place Close to VRAMPlace Close to VRAM

R142
243Ohm

1%

+1.8V_RUN

12

GND

12

12

0.01UF/16V

MLCC/+/-10%

12

12

VREF=VDDQ x Rb(Ra+Rb)
VREF=1.26V=0.7 x VDDQ

3

1

G

2

GND

12

C268
100PF/50V

MLCC/+/-5%

12

C270

0.1UF/10V

MLCC/+/-10%

12

C253

12

C263
470PF/50V

1000PF/50V

MLCC/+/-10%

MLCC/+/-10%

12

C196
100PF/50V

MLCC/+/-5%

SW_VREF 22,26

VREF_SW_A2

D

Q22

NO.43

2N7002

S

Close to memory
VREFA2=0.7*VDDQ
for 136pin

VREF_SW_A2

Close to memory
VREFA2=0.7*VDDQ
for 136pin

+1.8V_RUN

12

C207

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

RELEASE DATE :

12

FBA_CLK1
FBA_CLK1#

C242
100PF/50V

MLCC/+/-5%

C241

0.1UF/10V

MLCC/+/-10%

C200

0.01UF/16V

MLCC/+/-10%

C516

C192
470PF/50V

MLCC/+/-10%

R84

475Ohm

1%

R132

475Ohm

1%

12

0.1UF/10V

MLCC/+/-10%

+1.8V_RUN

Ra

12

Rb

12

12

1.18KOhm

1%

GND

C248

12

12

12

1000PF/50V

MLCC/+/-10%

12

R143

2

VREFA1

VREFA3

U22

T3

DQ31

T2

DQ30

R3

DQ29

R2

DQ28

M3

DQ27

N2

DQ26

L3

DQ25

M2

DQ24

T10

DQ23

T11

DQ22

R10

DQ21

R11

DQ20

M10

DQ19

N11

DQ18

L10

DQ17

M11

DQ16

G10

DQ15

F11

DQ14

F10

DQ13

E11

DQ12

C10

DQ11

C11

DQ10

B10

DQ9

B11

DQ8

G3

DQ7

F2

DQ6

F3

DQ5

E2

DQ4

C3

DQ3

C2

DQ2

B3

DQ1

B2

DQ0

A1

VDDQ1

C1

VDDQ2

E1

VDDQ3

N1

VDDQ4

R1

VDDQ5

U1

VDDQ6

C4

VDDQ7

E4

VDDQ8

J4

VDDQ9

N4

VDDQ10

R4

VDDQ11

C9

VDDQ12

E9

VDDQ13

J9

VDDQ14

N9

VDDQ15

R9

VDDQ16

A12

VDDQ17

C12

VDDQ18

E12

VDDQ19

N12

VDDQ20

R12

VDDQ21

U12

VDDQ22

B1

VSSQ1

D1

VSSQ2

P1

VSSQ3

T1

VSSQ4

G2

VSSQ5

L2

VSSQ6

B4

VSSQ7

D4

VSSQ8

P4

VSSQ9

T4

VSSQ10

B9

VSSQ11

D9

VSSQ12

P9

VSSQ13

T9

VSSQ14

G11

VSSQ15

L11

VSSQ16

B12

VSSQ17

D12

VSSQ18

P12

VSSQ19

T12

VSSQ20

G1

VSS1

L1

VSS2

A3

VSS3

U3

VSS4

A10

VSS5

U10

VSS6

G12

VSS7

L12

VSS8

H1

VREF1

H12

VREF2

K4J52324QE-BC14

12

C264

C193

0.1UF/10V

4.7UF/6.3V

MLCC/+/-10%

MLCC/+/-10%
pt_c0603

12

C254

C211

0.01UF/16V

4.7UF/6.3V

MLCC/+/-10%

MLCC/+/-10%
pt_c0603

12

C178

C518

0.01UF/16V

MLCC/+/-10%

C201
470PF/50V

MLCC/+/-10%

R85

511Ohm

12

1%

NO.56

12

12

C517

R434

0.01UF/16V

MLCC/+/-10%

1.18KOhm

1%

+1.8V_RUN

GND

R140

511Ohm

12

1%

NO.56

12

C267

0.01UF/16V

MLCC/+/-10%

GND

FBAD49
FBAD48
FBAD51
FBAD50
FBAD55
FBAD53
FBAD54
FBAD52
FBAD44
FBAD45
FBAD40
FBAD43
FBAD47
FBAD46
FBAD42
FBAD41
FBAD59
FBAD61
FBAD60
FBAD58
FBAD63
FBAD57
FBAD56
FBAD62
FBAD38
FBAD33
FBAD39
FBAD35
FBAD37
FBAD32
FBAD36
FBAD34

Place below decoupling caps close VDD pin.

12

C225

0.1UF/10V

MLCC/+/-10%

12

0.1UF/10V

MLCC/+/-10%

C240

12

C251

0.01UF/16V

MLCC/+/-10%

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

BA2

RAS#

CS

CAS#

CKE

WE#

CAS

MF= 0MF= 1
A4
A5
A6
A9
A0
A1
A2

A11
A10

A8/AP

A3

A8/AP

A7

BA1
BA0
RAS

WE

CKE

RFU1

RFU2

SEN

RESET

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

DM3
DM2
DM1
DM0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDDA1
VDDA2

VSSA1
VSSA2

12

C218

0.01UF/16V

MLCC/+/-10%

H3
F4
H9
F9

CS#

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11
M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

H10

BA2

H4
J11

CK

J10

CK#

J2
J3
U4

U9
A9

MF

A4

ZQ

P2
P11
D11
D2

P3
P10
D10
D3

N3
N10
E10
E3

F1
M1
A2
U2
A11
U11
F12
M12

K1
K12

J1
J12

12

C262

1000PF/50V

MLCC/+/-10%

Sean Kuo

FBA_CMD7
FBA_CMD8
FBA_CMD18
FBA_CMD10

FBA_CMD5
FBA_CMD13
FBA_CMD21
FBA_CMD20
FBA_CMD19
FBA_CMD25
FBA_CMD4
FBA_CMD9
FBA_CMD17

FBA_CMD23
FBA_CMD16

FBA_CMD3
FBA_CMD12
FBA_CMD1

FBA_CMD11
FBA_CLK1
FBA_CLK1#

FBA_CMD15

12

R121 240Ohm 1%

FBADQSW6
FBADQSW5
FBADQSW7
FBADQSW4

FBADQSR#6
FBADQSR#5
FBADQSR#7
FBADQSR#4

FBADQM6
FBADQM5

FBADQM7

FBADQM4

FBA_VDDA2

FBA_VDDA3

12

C271

0.047UF/16V

MLCC/+/-10%

GND

12

470PF/50V

MLCC/+/-10%

1

pt_r0603

+1.8V_RUN

C217

1

L35 180Ohm

L18 180Ohm

12

C519

0.047UF/16V

MLCC/+/-10%

+1.8V_RUN

12

C247

100PF/50V

MLCC/+/-5%

GND

FBA_CMD[0..26] 26

FBA_CLK1 26
FBA_CLK1# 26

GND

FBADQSR#[0..7] 26

FBADQM[0..7] 26

+1.8V_RUN

pt_l0603

21
21

pt_l0603

5

CON1

68

NP_NC2

66

ICH_USBP5-16

ICH_USBP5+16

64

63

62

61

60

59

58

57

65

67

NO.8
NO.46

SIDE_10

SIDE_8

SIDE_7

SIDE_6

SIDE_5

SIDE_4

SIDE_3

SIDE_2

SIDE_1

SIDE_9

NP_NC1

WTOB_CON_56P

JAE/FI-M56SB1

+5V_RUN

C744

1UF/10V

pt_c0603
/*

D D

C C

B B

A A

<Variant Name>

12

CCD_VDD_ON17

56

56

55

55

54

54

53

53

52

52

51

51

50

50

49

49

48

48

47

47

46

46

45

45

44

44

43

43

42

42

41

41

40

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

Q74
SI2301BDS

23

S

2

12

R605
10KOhm

5% /*

NO.52

PROJECT:

5

USBP5_D­USBP5_D+

AUX_LCD_CBL_DET#
+5V_CCD
+3V_DMIC

AUD_DMIC_CLK_L
LCD_CBL_DET_R

INVERTER_CBL_DET#
LAMP_STAT#

BACKLITEON

LCD_B2­LCD_B2+

LCD_B1­LCD_B1+

LCD_B0­LCD_B0+

LCD_BCLK­LCD_BCLK+

LCD_ACLK­LCD_ACLK+

LCD_A2­LCD_A2+

LCD_A1­LCD_A1+

LCD_A0­LCD_A0+

GND

R604 0Ohm

12

pt_r0603

/*

D

3

G

1

1

C745 1UF/10V/X7R

12

MLCC/+/-10% /*

Q75
DTC114EKA /*

C

3

B

R1

2

R1 0Ohm 5%

R3 0Ohm 5%

pt_c0603

1

E

R2

12

14

23

12

12

L1

90OHM/100MHz

MURATA/DLW21SN900SQ2L

Lanai

1

+5V_CCD

C501
10UF/10V

MLCC/+80-20%
pt_c0805_h53

/*

/*

REVISION

1.2

NO.8

T158

AUX_LCD_CBL_DET# 37

AUD_DMIC_IN0 44

LCD_CBL_DET_R 37
INVERTER_CBL_DET# 37

NO.8

+5V_ALW

GFX_PWR_SRC

LCD_TST 38

+LCDVCC

+3.3V_RUN

LCD_DDCDAT 22
LCD_DDCCLK 22

LCD_B2- 26
LCD_B2+ 26

LCD_B1- 26
LCD_B1+ 26

LCD_B0- 26
LCD_B0+ 26

LCD_BCLK- 26
LCD_BCLK+ 26

LCD_ACLK- 26
LCD_ACLK+ 26

LCD_A2- 26
LCD_A2+ 26

LCD_A1- 26
LCD_A1+ 26

LCD_A0- 26
LCD_A0+ 26

DATE:
SHEET OF

4

GND

AUD_DMIC_CLK44

USBP5_D­USBP5_D+

Monday, March 19, 2007

4

3

Adress: A9H --Contrast
AAH --Backlight

12

C12
47PF/50V

MLCC/+/-5%
/*

GND

LCD_ACLK+

LCD_ACLK­LCD_A2+

LCD_A2­LCD_A1+

LCD_A1­LCD_A0+

LCD_A0-

BIA_PWM22

12

C5
47PF/50V

MLCC/+/-5%
/*

LCD_SMBCLK 37
LCD_SMBDAT 37

+3.3V_RUN

12

LCD_BCLK+

LCD_BCLK­LCD_B2+

LCD_B2­LCD_B1+

LCD_B1­LCD_B0+

LCD_B0-

R397

10KOhm

5%

BACKLITEON

+3.3V_RUN

NO STUFF NO STUFF

12

C153

/*

3.3PF/50V

12

C163

/*

3.3PF/50V

12

C143

/*

3.3PF/50V

12

C136

/*

3.3PF/50V

12

R396 0Ohm 5%/*

12

C176

3.3PF/50V

12

C152

3.3PF/50V

12

C182

3.3PF/50V

12

C164

3.3PF/50V

Populate R396 for
DPST implementation
only.

NO.18

R616 0Ohm 5%

12

U1

1

5

OE#

Vcc

2

A

12

3

4

GND

R6
10KOhm

5%
/*

V_DMIC IS DEPENDENT ON MIC SELECTION (1.8V - 3.3V TYP)
Verify to ensure operability with chosen mic supplier.

Y

SN74LVC1G125DBVR

/*

L55
80Ohm

pt_l0603

21

12

R617
47Ohm

5%

Note1: If only 1 digital mic, use AUD_DMIC_IN0.
Note2: If using 2 dig mics, also use AUD_DMIC_IN0.

This input supports 2 digimics. AUD_DMIC_IN1 is only
used to support 4 dig mics.

DESCRIPTION:

28 69

LVDS CON

3

/*

ENVDD22

/*

LCDVCC_TST_EN37

/*

/*

Populate R397 for
platform without DPST
support. No Stuff for
Discrete DSPT support
due to back up plan.

NO.18

AUD_DMIC_CLK_L

12

C748
33PF/50V

MLCC/+/-5%
/*

R45 0Ohm 5%/*

12

D8

RB751S40T1G
D15

RB751S40T1G

RELEASE DATE :

21

21

Q55

R1

2

DDTC124EUA-7-F

+3.3V_RUN

2

+3.3V_RUN

R20

/*

47KOhm

12

5%

3
C

B

E

R2

1

GND

RUN_ON37,49,51,54,58

2

+15V_ALW

R17

330KOhm

12

5%

LCDVCC_ON

+3.3V_ALW

600Ohm Irat=200mA

3

D

Q8
2N7002

1

G

S

2

R29

47KOhm

12

GND GND

5%

12

C502
10UF/10V

MLCC/+/-20%
pt_c0805_h57

NO.8

+3V_DMIC

L31

+PWR_SRC

21

40mils

12

C1

R2

0.1UF/50V

100KOhm

12

MLCC/+/-10%

5%

pt_c0603

12

R4
100KOhm

5%

3

D

Q4

1

2N7002

G

S

2

GND

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Q5

6
5
2
1

FDC653N_NL

3

12

R9

100KOhm

12

5%

C11

/*

0.01UF/25V

MLCC/+/-10%

GNDGND

+3.3V_RUN

12

+5V_ALW

12

GND

5

2

34

Sean Kuo

4

150Ohm

pt_r0603_h22
12

3

D

1

G

S

2

C504

0.1UF/10V

MLCC/+80-20%

C4

0.1UF/10V

MLCC/+/-10%

40mils

6

Q1
FDC658P_NL

1

1

R26

5%

NO.54

Q9
2N7002

GFX_PWR_SRC

1

12

C8

22UF/10V

MLCC/+80%-20%
pt_c1206_h71

+LCDVCC

12

C2

0.1UF/10V

MLCC/+80-20%

GNDGND

12

C9

0.1UF/50V

MLCC/+/-10%
pt_c0603

GND

+LCDVCC+3.3V_RUN

GND

12

12

12

C6

0.1UF/16V

MLCC/+/-10%

C3

0.047UF/10V

MLCC/+/-10%

NO.52

C10

2.2UF/25V

MLCC/+80%-20%
pt_c0805_h53

5

D D

C C

4

3

2

1

B B

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

29 69

4

DESCRIPTION:

VGA CRT CON

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

Sean Kuo

1

5

D D

C C

4

3

2

1

B B

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

30 69

4

DESCRIPTION:

TV OUT CON

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

Sean Kuo

1

A

1 1

CON12

SATA Connector ODD Connector

+5V_HDD

25
23

NP_NC3
NP_NC1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

B

SATA_TX0+ 15

SATA_RXN0_C
SATA_RXP0_C

SATA_TX0- 15

C

+5V_MOD

D

E

8

C81

/*

0.1UF/10V/Y5V

MLCC/+80-20%

2 2

3 3

4 4

5 5

HDDC_EN38

Place caps close to
connector.

12

1

R7

100KOhm

5%

12

C75

12

1000PF/50V

MLCC/+/-10%

+15V_ALW

+5V_ALW2

R399

100KOhm

5%

12

3

D

Q2
2N7002

G

S

2

/*

SATA_RXN0_C
SATA_RXP0_C

+5V_ALW

R5

100KOhm 5%

24
26

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

NP_NC2

21

21

22

22

NP_NC4

SATA_CON_22P

FOXCONN/LD2822H-SA3L6

Q3

1

D

2
3

G

SI3456BDV-T1-E3

12

3

D

Q56

1

2N7002

G

S

2

6
5

S

4

HDD_EN_5V

pt_c0805_h57

10UF/10V/X5R

pt_c0603

0.1UF/25V

12
12

+5V_HDD

12

12

C16

MLCC/+/-20%

C13

MLCC/+/-10%

+3.3V_RUN

+5V_HDD

C1973900PF/50V/X7RMLCC/+/-10%
C1983900PF/50V/X7RMLCC/+/-10%

R31

12

0Ohm

pt_r0805_h24

R400

100KOhm

5%

12

SATA_RX0- 15
SATA_RX0+ 15

+5V_RUN

/*

+5V_MOD

C449

12

pt_c0805_h57

MLCC/+/-20%

10UF/10V/X5R

Place caps close to
connector.

IDE_DD[0:15]15

IDE_DDREQ15
IDE_DIOW#15
IDE_DIOR#15
IDE_DIORDY15
IDE_DDACK#15
IDE_IRQ15
IDE_DA115
IDE_DA015
IDE_DCS1#15
IDE_DA215
IDE_DCS3#15

MODC_EN38

12

0.1UF/10V/Y5V

C677

C673

12

MLCC/+80-20%

0.1UF/10V/Y5V

MLCC/+80-20%

IDE_DD[0:15]
IDE_DDREQ

IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DA2
IDE_DCS3#

R524

100KOhm

5%

12

R562

100KOhm

5%
/*

12

IDE_RST_MOD17

+3.3V_RUN
+3.3V_RUN

1

R370
R372

+5V_ALW2

R525
100KOhm

5%

12

+15V_ALW

3

D

Q63

2N7002

G

S

2

12

4.7KOhm 5%

8.2KOhm 5%

DASP#

R293

470Ohm 5%

+5V_ALW

C715

pt_c0603

MLCC+/-10%

1UF/16V/X5R

R373
56Ohm 5%

12
12

12

Q51

8
7
6
5

SI4800BDY

R526

100KOhm 5%

12

SD

G

12

IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#

CSEL2

1
2
3
4

3

D

1

G

S

2

+5V_MOD

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

SUYIN/800194MR050S520ZL

MODPRES# and USB_IDE#
are removed.

Q64
2N7002

1
3
5
7
9

+5V_MOD

pt_c0805_h57

10UF/10V/X5R

pt_c0603

0.1UF/25V

CON19

+5V_MOD

BtoB_CON_50P

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

C430

12

MLCC/+/-20%

12

2

2

4

4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

NP_NC1 NP_NC2

NP_NC3 NP_NC4

51 52

53 54

C452

MLCC/+/-10%

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

12

12

C684

0.01UF/25V/X7R

MLCC/+/-10%

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#

22Ohm

IDE_DDACK#

R369

12

IDE_DA2
IDE_DCS3#

+5V_RUN

R586
0Ohm

pt_r0805_h24

/*

PDIAG#

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

31 69

B

DESCRIPTION:

SATA(HDD & CD_ROM)

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Yihao Yeh

E

A

B

C

D

E

+3.3V_R5C832

1 1

2 2

3 3

4 4

5 5

<Variant Name>

Place these caps as close as
possible to the device pins.

+3.3V_R5C832

12

Route to CLK GEN .

CLK_PCI_PCCARD21

Reserve for EMI

PROJECT:

Lanai

A

C670

10UF/10V

MLCC/+80-20%
pt_c0805_h53

12

C414

+3.3V_R5C832

R294
100KOhm

5%

12

12

C423
1UF/10V/X7R

MLCC/+/-10%
pt_c0603

12

12

REVISION

0.1UF/10V

MLCC/+80-20%

R361

10Ohm

5%
/*

C471

10PF/50V

MLCC/+/-0.5PF
/*

1.2

12

C669

12

C431

0.01UF/16V

MLCC/+/-10%

12

C437
10UF/10V

MLCC/+80-20%
pt_c0805_h53

0.01UF/16V

MLCC/+/-10%

12

C420

0.01UF/16V

MLCC/+/-10%

PCI_AD1716

Pull-up

resistors to

+3.3V_RUN are

required on

the ICH

schematics.

Pull-up to
+3.3V_ALW
is required on
SYS_PME#
on SIO
schematics.
(From SIO).
0 ohm of PME#
is no-stuff
to prevent
backdrive
from this
signal
since the
controller
is powered of
the
RUN rail

Monday, March 19, 2007

DATE:
SHEET OF

32 69

B

12

12

C413

0.47UF/10V

MLCC/+/-10%
pt_c0603

PCI_AD[0..31]16

PCI_AD17

C415

0.01UF/16V

MLCC/+/-10%

12

C446

0.01UF/16V

MLCC/+/-10%

12

C680

0.01UF/16V

MLCC/+/-10%

PCI_PAR16
PCI_C_BE3#16
PCI_C_BE2#16
PCI_C_BE1#16
PCI_C_BE0#16

12

R580 100Ohm 5%

PCI_REQ1#16

PCI_GNT1#16
PCI_FRAME#16
PCI_IRDY#16
PCI_TRDY#16
PCI_DEVSEL#16
PCI_STOP#16 PCI_PIRQD# 16
PCI_PERR#16
PCI_SERR#16

PCI_RST#16

R308 0Ohm 5% /*

SYS_PME#38

R566 0Ohm 5%

CLKRUN#17,37

The ICH schematics need to
include a pull-up resistor
to implement CLKRUN#, and
the ICH schematics must
have a pull-down, or
constantly drive the
signal low, in order to
disable CLKRUN#.

DESCRIPTION:

C472

C694

0.01UF/16V

0.01UF/16V

MLCC/+/-10%

MLCC/+/-10%

U16B

10

VCC_PCI3V_1

20

VCC_PCI3V_2

27

VCC_PCI3V_3

32

VCC_PCI3V_4

41

VCC_PCI3V_5

128

VCC_PCI3V_6

61

VCC_RIN

16

VCC_ROUT1

12

R571

10KOhm

5%
/*

34

VCC_ROUT2

64

VCC_ROUT3

114

VCC_ROUT4

120

VCC_ROUT5

125

AD31

126

AD30

127

AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23

11

AD22

12

AD21

14

AD20

15

AD19

17

AD18

18

AD17

19

AD16

36

AD15

37

AD14

38

AD13

39

AD12

40

AD11

42

AD10

43

AD9

44

AD8

46

AD7

47

AD6

48

AD5

49

AD4

50

AD3

51

AD2

52

AD1

53

AD0

33

PAR

7

C/BE3#

21

C/BE2#

35

C/BE1#

45

C/BE0#

8

IDSEL

124

REQ#

123

GNT#

23

FRAME#

24

IRDY#

25

TRDY#

26

DEVSEL#

29

STOP#

30

PERR#

31

SERR#

71

GBRST#

119

PCIRST#

121

PCICLK

70

PME#

117

CLKRUN#

R5C833_TQFP128

C.S R5C833 TQFP128

NO.22

12

C707

0.47UF/10V

MLCC/+/-10%
pt_c0603

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

R5C832_IDSEL

12
12

12

C416

0.01UF/16V

MLCC/+/-10%

Ricoh R5C832 Package Type : TQFP-128-P1 (1414)

R5C833 - PCI INTERFACE

C

PCI / OTHER

VCC_3V

VCC_MD

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

GND10

AGND1
AGND3
AGND2
AGND4
AGND5

HWSPND#

MSEN

XDEN

UDIO5

UDIO3
UDIO4

UDIO2
UDIO1

UDIO0/SRIRQ#

INTA#
INTB#

TEST

RELEASE DATE :

67

86

4
13
22
28
54
62
63
68
118
122

99
102
103
107
111

69

58
55

57

65
59

56
60
72

115
116

66

+3.3V_R5C832

12

12

R288 10KOhm 5%

R289 100KOhm 5%

R292

100KOhm

5%

12

12

12

12

C425

0.01UF/16V

MLCC/+/-10%

R287
10KOhm

5%

12

IRQ_SERIRQ 17,37

PCI_PIRQC# 16

T55

1

<OrgName>

D

R363 0Ohm 5% pt_r0603

+3.3V_R5C832

12

C468

10UF/10V

MLCC/+80-20%
pt_c0805_h53

+3.3V_R5C832

+3.3V_R5C832

1394 : INTA#

4in1 : INTB#

DESIGN ENGINEER :SCHEMATIC FILE NAME :

12

Memory Stick Enable

XD Card Enable

Serial ROM disable

SD Card Enable
MMC Card Enable

Pull-up resistors
to +3.3V_RUN are
required on the ICH
schematics.

Terry_Lin

+3.3V_R5C832+3.3V_RUN

E

A

B

C

D

E

For SD/MS Card Power

12

C660

0.1UF/10V

MLCC/+80-20%

+3.3V_RUN_CARD+3.3V_R5C832

12

C659
1UF/10V

MLCC/+80%-20%
pt_c0603

+3.3V_RUN_CARD

SD/XD/MS_DATA1
SD/XD/MS_DATA0
SD/XD/MS_DATA2
MS_INS#
SD/XD/MS_DATA3
SD/XD/MS_CLKXD_CLE

SD/XD/MS_DATA3
SD/XD/MS_CMD

SD/XD/MS_CLK
SD/XD/MS_DATA0

SD/XD/MS_DATA1
SD/XD/MS_DATA2

SD_CD#

XD_CDSW#

NO.45

S

D

SD_WP#(XDR/B#)SD_WP#

3

2

G

1

Q76

2N7002

NO.22

U26

2

NP_NC1

43

P_GND1

P_GND2

NP_NC2

444542

GND

3

OC#

4

EN

TPS2051BDBVR

SD(CD2/WP2/GND)

1 1

Recommended Crystal Specs from Data Sheet:

Normal Frequency : 24.576 MHz
Frequency Tolerance : +/- 50ppm @ 25C
Driver Level : .1 mW
Load capacitance : 10pF
Equ. Resistance : 50 Ohm Max
Shunt Capacitance : 7.0pF Max

NO.24

C454

12

15PF/50V

2 2

3 3

4 4

5 5

MLCC/+/-5%

C453

12

10PF/50V MLCC/+/-0.5PF

R5C832 : 0.01uF => stuff
R5C833 : 0.01uF => No stuff

NO.22

C463 0.01UF/16V MLCC/+/-10% /*

12

R576 10KOhm 1%

C469 0.01UF/16V MLCC/+/-10%

Place as close to
R5C832 as possible.

12

12

1394_XI

NO.24

12

X4

24.576Mhz

+/-50ppm/10PF

1394_XO

12

R342 0Ohm 5%

RICHO_FILO

RICHO_REXT

RICHO_VREF

U16A

94

XI

95

XO

96

FIL0

101

REXT

100

VREF

97

RSV

R5C833_TQFP128

C.S R5C833 TQFP128

NO.22

IEEE1394/SD

AVCC_PHY3V_1
AVCC_PHY3V_2
AVCC_PHY3V_3
AVCC_PHY3V_4

TPBIAS0

TPBN0
TPBP0

TPAN0
TPAP0

MDIO17
MDIO16
MDIO15
MDIO14
MDIO13
MDIO12
MDIO11
MDIO10

MDIO05
MDIO08
MDIO19
MDIO18
MDIO02

MDIO03
MDIO00

MDIO01

MDIO09

MDIO04
MDIO06

MDIO07

+3.3V_RUN_PHY

98
106
110
112

113

104
105

108
109

87
92
89
91
90
93
81
82

75
88
83
85
78

77
80

79

12

84

R545 0Ohm 5%

76
74

73

TPBIAS0

TPB0N
TPB0P

TPA0N
TPA0P

XD_DATA7
XD_DATA6
XD_DATA5
XD_DATA4
SD/XD/MS_DATA3
SD/XD/MS_DATA2
SD/XD/MS_DATA1
SD/XD/MS_DATA0

XD_WP#
SD/XD/MS_CMD
XD_ALE
XD_CLE
XD_CE#

SD_WP#(XDR/B#)

MC_PWR_CTRL_0
MS_LED#

TPBIAS0 34

TPB0N 34
TPB0P 34

TPA0N 34
TPA0P 34

SD/XD/MS_CLK

+3.3V_RUN_CARD

12

D20 1N4148W -7-F

12

D19 1N4148W -7-F

12

1

12

C662

0.01UF/16V

MLCC/+/-10%

T153TPC26T

C661

0.01UF/16V

MLCC/+/-10%

Place these components close to
the flash memory card connector

SD_CD#

XD_CDSW#

MS_INS#

12

C757

10PF/50V

MLCC/+/-0.5PF

NO.49

12

C663

0.01UF/16V

MLCC/+/-10%

R530

150KOhm

5%

12

+3.3V_RUN_CARD

12

C668

2.2UF/16V

MLCC/+/-10%
pt_c0603

XD_CDSW#
SD_WP#(XDR/B#)
SD/XD/MS_CLK
XD_CE#

XD_ALE
SD/XD/MS_CMD
XD_WP#

SD/XD/MS_DATA0
SD/XD/MS_DATA1
SD/XD/MS_DATA2
SD/XD/MS_DATA3
XD_DATA4
XD_DATA5
XD_DATA6
XD_DATA7

SD/XD/MS_CMD

MC_PWR_CTRL_0

CON20

TAISOL/144-2420000900

41 18

XD_0(GND) MS_3(DATA1)

40

XD_1(CD)

39

XD_2(R/-B)

38

XD_3(-RE)

37

XD_4(-CE)

36

XD_5(CLE)

34

XD_6(ALE)

31

XD_7(-WE)

23

XD_9(GND)

19

XD_10(D0)

15

XD_11(D1)

12

XD_12(D2)

11

XD_13(D3)

9

XD_14(D4)

7

XD_15(D5)

6

XD_16(D6)

5

XD_17(D7)

4

XD_18(VCC)

16

MS_2(BS)

CARD_READER_41P

IN

OUT

MS_4(DATA0)
MS_5(DATA2)

MS_6(INS)

MS_7(DATA3)

MS_8(SCLK)

MS_9(VCC)
MS_10(VSS)
SD_1(DAT3)XD_8(-WP)

SD_2(CMD)

SD_3(VSS)

SD_4(VDD)

SD_5(CLK)

SD_6(VSS)
SD_7(DAT0)
SD_8(DAT1)
SD_9(DAT2)

SD(CD1)

SD(WP1)MS_1(VSS)

5
1

20
22
24
26
28
30
32
3327
29
25
21
17
13
10
8
35
1
2
314

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

33 69

B

DESCRIPTION:

R5C833 - FLASH MEMORY PART

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

A

1 1

B

C

D

E

Place these caps as close to the R5C832 as possible.

+3.3V_RUN_PHY +3.3V_R5C832

12

C709

2 2

Place as close as possible to 1394 connector.
Also, place 0 ohm close to the

3 3

CON13

FOXCONN/UV31413-W R56P-7F

SIDE_G2

TPXA1+

4
3

TPXA1-

TPXB1+

2
1

TPXB1-

SIDE_G1

56

IEEE_1394_CON_4P

4 4

chokes to minimize stubs

Common mode chokes should
be 110- ohms impedance.They
are reserved for EMI

1394 pairs should be
routed as 110-ohm
differential

1000PF/50V

MLCC/+/-10%
pt_c0603

LTPA0+

LTPA0-

LTPB0+

LTPB0-

12

C688

10UF/10V

MLCC/+80-20%
pt_c0805_h53

R490 0Ohm 5%

R485 0Ohm 5%

R488 0Ohm 5%

R489 0Ohm 5%

12

12

14

23

L43

120OHM

/*
MURATA/DLW21HN121SQ2L

12

12

L44

120OHM

/*

14

23

MURATA/DLW21HN121SQ2L

12

C699

0.1UF/10V

MLCC/+80-20%

12

C703

0.01UF/16V

MLCC/+/-10%

12

L48

21

MURATA/BLM15HD601SN1D

600Ohm/100MHz

Irat=0.3A

Place as close as possible to R5C832

0.01UF/16V

MLCC/+/-10%

12

C480

0.33UF/25V

MLCC/+80%-20%
pt_c0603

12

R359 56Ohm 1%

12

R360 56Ohm 1%

R357

R358

56Ohm

56Ohm

1%

1%

12

12

R365 5.1kOhm 1%

1394_TPB1_R

C478

C479

TPBIAS0
TPA0P
TPA0N
TPB0P

12

TPB0N

12

270PF/50V MLCC/+/-10%

TPBIAS0 33
TPA0P 33
TPA0N 33
TPB0P 33
TPB0N 33

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

34 69

B

DESCRIPTION:

R5C833 - IEEE1394 PART

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

5

4

3

2

1

ICH_USBP6-16

ICH_USBP6+16

R499 0Ohm 5%
R502 0Ohm 5%

D D

+3.3V_CARD

12

C657

0.1UF/10V

MLCC/+80-20%

C C

12

C656

0.1UF/10V

MLCC/+80-20%

L46
90OHM/100MHz

/*

14

23

MURATA/DLW21SN900SQ2L

12
12

12

C658

10UF/10V

MLCC/+80-20%
pt_c0805_h53

Please the cap
near connector.

+1.5V_CARD

+3.3V_CARDAUX

+3.3V_CARD

CLK_PCIE_EXPCARD#21
CLK_PCIE_EXPCARD21

USBP6_D-

USBP6_D+

ICH_SMBCLK17,50
ICH_SMBDATA17,50

PCIE_WAKE#38,47,50

CARD_CLK_REQ#21

EXPRCRD_PWREN#38

PCIE_RX4-16
PCIE_RX4+16

PCIE_TX4-16
PCIE_TX4+16

PCI-Express TX and RX direct to connector .

+1.5V_CARD

12

C379

0.1UF/10V

MLCC/+80-20%

Please the cap
near connector.

USBP6_D­USBP6_D+

CPUSB#

CARD_RESET#

EXPRCRD_PWREN#

12

C381

0.1UF/10V

MLCC/+80-20%

CON8

JAE/PX10ABSB00G-1

129

1P_GND1

2

2

NP_NC1

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

NP_NC2

25

26

P_GND2

26

EXPRESS_CARD_26P

Express Card

27

28
30

Please the cap
near pin 12 &
14 (1.5VIN).

+1.5V_CARD Max. 650mA, Average 500mA.
+3V_CARD Max. 1300mA, Average 1000mA.

+3.3V_SUS+3.3V_RUN+1.5V_RUN +3.3V_CARDAUX +1.5V_CARD+3.3V_CARD

U13

17

AUX_IN

2

3.3VIN_1

45

3.3VIN_2 3.3VOUT_2

12

1.5VIN_2

14

12

C376

0.1UF/10V

MLCC/+80-20%

1.5VIN_1

20

SHDN#

1

STBY#

6

SYSRST#

16

NC

7

GND1

R5538D001_TR_F

+3.3V_SUS

R221 100KOhm 5%

12

R230 0Ohm 5% /*

EXPRCRD_STDBY#38

PLTRST#10,16,37

+1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +1.5V_CARD+3.3V_CARD

12

C371

0.1UF/10V

MLCC/+80-20%

12

12

C385

0.1UF/10V

MLCC/+80-20%

Please the cap
near pin 2 & 4
(3.3VIN).

Please the cap
near pin 17
(AUXIN).

AUX_OUT

3.3VOUT_1

1.5VOUT_1

1.5VOUT_2

PERST#

CPPE#

CPUSB#

OC#

GND2

RCLKEN

15
3

11
13

CARD_RESET#

8

EXPRCRD_PWREN#

10

CPUSB#

9
19

21
18

12

C370

0.1UF/10V

MLCC/+80-20%

Please the cap
near pin 15
(AUXOUT).

R216 100KOhm 5%
R220 100KOhm 5%

12

C384

Please the cap
near pin 3 & 5
(3.3VOUT).

12
12

0.1UF/10V

MLCC/+80-20%

+3.3V_SUS

12

C372

0.1UF/10V

MLCC/+80-20%

Please the cap
near pin 11 &
13 (1.5VOUT).

B B

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

35 69

4

DESCRIPTION:

PCI-Express Card

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

A

B

C

D

E

1 1

2 2

3 3

ICH_AZ_MDC_SDOUT

R312

/*

10Ohm

5%

12

12

C422

10PF/50V

MLCC/+/-0.5PF
/*

ICH_AZ_MDC_SDOUT15
ICH_AZ_MDC_SYNC15

ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SYNC

MDC_SDIN

ICH_AZ_MDC_RST1#

MDC

CON18

1314

1920

1516

1718

12

12

34

GND1GND2

GND3GND4

GND5GND6

34

56
78
910

11 12

MDC_CONN_12P

TYCO/1-1775844-2

NP_NC1NP_NC2

56
78
910
11 12

No Nut and hole

+3.3V_SUS

ICH_AZ_MDC_BITCLK

ICH_AZ_MDC_BITCLK 15

12

Note: MDC DISABLE.

ICH_AZ_MDC_RST#15

MDC_RST_DIS#43

+5V_SUS

R322

10KOhm

5%
/*

12

If platform requires MDC disable, populate this circuit.

R320

0Ohm 5%

Q49
BSS138

/*

S

D

3

2

G

1

ICH_AZ_MDC_RST1#

R323

100KOhm

5%
/*

12

If MDC disable isn't required, connect ICH_A2_MDC_RST# directly to JMDC connector.

ICH_AZ_MDC_SDIN115

4 4

12

33Ohm 5%

MDC_SDIN

R319

ICH_AZ_MDC_BITCLK

R321

/*

10Ohm

5%

12

12

C429

10PF/50V

MLCC/+/-0.5PF
/*

+3.3V_SUS

C4260.1UF/10V

12

C4174.7UF/10V

12

MLCC/+80-20%pt_c0805_h53

MLCC/+80-20%

Place these caps near
MDC module.

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

36 69

B

DESCRIPTION:

MDC CONN

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Yihao_Yeh

E

5

(GPIO4) (GPIO5) CHIPSET
CHIPSET_ID1 CHIPSET_ID0 Common Boot block sequence

R255 2.7KOhm

12

R260 2.7KOhm

12

R267 2.7KOhm

12

D D

+5V_RUN

12
34
56
78

+3.3V_ALW

12

12

R304

R290

100KOhm

100KOhm

5%

5%

/*

/*

CLK_PCI_5025

C C

R305
10Ohm

/*

12

5%

12

C421

4.7PF/50V

/*
MLCC/+/-0.25PF

32KHz Clock

R529
0Ohm

5%

12

MEC5025_XTAL2_R

12

C667
12PF/50V

MLCC/+/-5%

NO.24

B B

/*

4.7KOhm

4.7KOhm

4.7KOhm

4.7KOhm

12

R325

100KOhm

5%

Place close to
pin 58

SUS_ON

5%

RUN_ON

5%

AC_OFF

5%

CLK_KBD

RN37A

DAT_KBD

RN37B

CLK_DOCK

RN37C

DAT_DOCK

RN37D

12

R324

100KOhm

5%

AUX_LCD_CBL_DET#
INVERTER_CBL_DET#
SNIFFER_GREEN#
SNIFFER_YELLOW#

MEC5025_XTAL2

NO.24

X5

2

3

------------------------------------------------------­ 0 0 Intel-SR
0 1 ATI-RR
1 0 TBD
1 1 Parke r(Intel/ATI)

Non
iAMT

T149TPC26T

Non
iAMT

T154TPC26T
T152TPC26T

MEC5025_XTAL1

14

12

32.768KHZ

+/-10ppm/6PF

C654
12PF/50V

MLCC/+/-5%

NO.24

EC_CPU_PROCHOT#7

ALW_PWRGD_3V_5V54

1

1
1

EC_FLASH_SPI_CLK40
EC_FLASH_SPI_DIN40
EC_FLASH_SPI_DO40

SNIFFER_YELLOW#42

R521 10KOhm

C652 4.7UF/10V

pt_c0805_h37 MLCC/+/-10%

L24

L25

+3.3V_ALW

CKG_SMBDAT21
CKG_SMBCLK21

1.8V_SUS_PWRGD56

ICH_CL_PWROK10,17

ICH_RSMRST#17

BC_A_DAT41
BC_A_CLK41

SNIFFER_GREEN#42

CLK_TP_SIO41
DAT_TP_SIO41

IRQ_SERIRQ17,32

ICH_EC_SPI_CLK16
ICH_EC_SPI_DIN16

ICH_EC_SPI_DO16

12

120Ohm/100Mhz

120Ohm/100Mhz

L26
120Ohm/100Mhz

NO.34

T151TPC26T

DDR_ON56
TP_DET#41

SIO_SLP_S3#17
SIO_SLP_S5#17

3.3V_RUN_ON49
SUS_ON49,51

RUN_ON28, 49,51,54,58
AC_OFF59

BC_A_INT#41

SIO_A20GATE15

8051_RX50

8051_TX50

PLTRST#10,16,35

CLK_PCI_502521
LPC_LFRAME#15
LPC_LAD015

LPC_LAD115
LPC_LAD215
LPC_LAD315

CLKRUN#17,32

SIO_PWRBTN#17

BC_CLK38
BC_DAT38

BC_INT#38

12

21

21

21

5%

CHIPSET_ID0
CHIPSET_ID1

1

ICH_RSMRST#

AUX_ON
SUS_ON
RUN_ON

SNIFFER_GREEN#

CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051_RX
8051_TX

CLK_PCI_5025

SNIFFER_YELLOW#

MEC5025_XTAL1
MEC5025_XTAL2
MEC5025_XOSEL

VR_CAP
MEC_AGND

MEC_VCC_PLL

12

C438

0.1UF/10V

MLCC/+/-10%

4

U15

12

KSO17/GPIOA1/AB1H_DATA

13

KSO16/GPIOA0/AB1H_CLK

14

GPIO5/KSO15

15

GPIO4/KSO14

16

KSO13/GPIO18

17

KSO12/OUT8

18

KSO11/GPIOC7

19

KSO10/GPIOC6

20

KSO9/GPIOC5

23

KSO8/GPIOC4

24

KSO7/GPIO3

25

KSO6/GPIO2

27

KSO5/GPIO1

28

KSO4/GPIO0

29

KSO3/GPIOC3

30

KSO2/GPIOC2

31

KSO1/GPIOC1

32

KSO0/GPIOC0

33

KSI7/GPIO19

34

KSI6/GPIO17

35

KSI5/GPIO10

36

KSI4/GPIO9

37

KSI3/GPIO8

38

KSI2/GPIO7/BC_A_INT#

39

KSI1/GPIO6/BC_A_DAT

40

KSI0/SGPIO30/BC_A_CLK

92

SGPIO34/A20M

50

OUT5/KBRST

75

GPIO94/IMCLK

76

GPIO95/IMDAT

77

KCLK

78

KDAT

79

GPIOA6/EMCLK

80

GPIOA7/EMDAT

81

GPIO20/PS2CLK/8051RX

82

GPIO21/PS2DAT/8051TX

57

LRESET#

58

PCICLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

56

SER_IRQ

102

HSTCLK

105

HSTDATAIN

107

HSTDATAOUT

103

FLCLK

106

FLDATAIN

108

FLDATAOUT

109

GPIO80

110

GPIO81

87

BC_CLK

86

BC_DAT

85

BC_INT#

122

XTAL1

124

XTAL2

123

XOSEL

22

VR_CAP

125

AGND

104

VCC_PLL

101

VSS_PLL

MEC5025-NU

KEYBOARD/MOUSE

PCI POWER/LPC BUS

HOST/8051 SPI

BC

CLOCK

POWER PLANES

POWER PLANES

POWER_SW_IN2#/GPIO23
POWER_SW_IN1#/GPIO22

POWER SWITCH

ACCESS BUS

SGPIO45/MSDATA/SPDOUT2

SGPIO44/MSCLK/SPCLK2

SGPIO31/TIN1/SPCLK1

GPIO

SYSOPT0/SGPIO32/LPC_TX

SYSOPT1/SGPIO33/LPC_RX

MISCELLANEOUS

VCC0

VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5

ALWON

POWER_SW_IN0#

ACAV_IN

BGPO0/GPIOA5

AB1B_CLK/GPIOA4

AB1B_DATA/GPIOA2

AB1A_CLK

AB1A_DATA

GPIO11/AB2_DATA

GPIO12/AB2_CLK

GPIO13/AB1G_DATA

GPIO14/AB1G_CLK

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

GPIO85/AB1D_DATA

GPIO84/AB1D_CLK

GPIO93/AB1F_DATA

GPIO92/AB1F_CLK

GPIO91/AB1E_DATA

GPIO90/AB1E_CLK

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

OUT2/PWM3

OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

nEC_SCI/SPDIN2

SGPIO46/SPDIN1

SGPIO47/SPDOUT1

SGPIO40
SGPIO41
SGPIO42
SGPIO43

SGPIO35

SGPIO36(SFPI_EN)

SGPIO37

GPIO96/TOUT1

OUT7/nSMI

nPWR_LED

nBAT_LED

nFWP

GPIOA3/WINDM ON

GPIO83/32KHZ_OUT

PWRGD

nRESET_OUT/OUT6

TEST_PIN

VSS1
VSS2
VSS3
VSS4
VSS5

3

121
21

44
65
83
116

120
119
126
127
128
118

8
7
6
5

93
94
95
96
111
112
9
10
97
98
99
100

43
42
41

48
47
46
45

66
55
54
69
68
67

70
71

91
90
89
4

1
2
3
52
11

115
114
84
73
117
49
53
72

113
88
74
51
26

MEC5025_VCC0

+3.3V_ALW

ALWON

INSTANT_ON_SW#

SNIFFER_RTC_GPO
LCD_SMBCLK

LCD_SMBDAT
DOCK_SMBCLK
DOCK_SMBDAT

LCDVCC_TST_EN

PBAT_SMBDAT
PBAT_SMBCLK
SBAT_DH_SMBDAT
SBAT_DH_SMBCLK

THRM_SMBDAT
THRM_SMBCLK

R279

2.2KOhm /*5%

AUX_EN_WOWL_1

3.3V_SUS_ON

SIO_EXT_SCI#

1.25V_GFX_PCIE_ON
DEBUG_ENABLE#

R203 1MOhm

LCD_CBL_DET
INVERTER_CBL_DET#
AUX_LCD_CBL_DET#

LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#

FWP#

MEC_TEST_PIN

Place cap close to pin 121.

R274 0Ohm

12

5% pt_r0 603

12

C399

0.1UF/10V

MLCC/+/-10%

ALWON 54

12

1
1

1
1

12

12

5%

1

12

Populate

R328

for flash

0Ohm

corruption

5%

issue.

SNIFFER_PWR_SW# 42
MAIN_PWR_SW# 42

ACAV_IN 43,57

LCD_SMBCLK 28
LCD_SMBDAT 28

T43 TPC26T
T44 TPC26T

1.8V_RUN_ON 49
LCDVCC_TST_EN 28

T155
T66

PBAT_SMBDAT 57,59
PBAT_SMBCLK 57,59

1.5V_RUN_ON 55

1.25V_RUN_ON 58
THRM_SMBDAT 43
THRM_SMBCLK 43

IMVP_PWRGD 17,51,53

+3.3V_RUN

FAN1_TACH 43
IMVP_VR_ON 53

3.3V_SUS_ON 49
BREATH_LED# 42

PS_ID 59
SIO_RCIN# 15

BEEP 44

+3.3V_ALW

SIO_SPI_CS# 16

LOM_SMB_ALERT# 17

0.9V_DDR_VTT_ON 56
SIO_EXT_SMI# 17

BAT2_LED# 42
BAT1_LED# 42

T159

TPC26T

RUNPWROK 38,51,53
RESET_OUT# 51

R245
10KOhm5%

+RTC_CELL

INSTANT_POWER_SW# 41

TPC26T
TPC26T

R179 0Ohm 5%

R614 0Ohm 5%
R615 0Ohm 5%

2

+RTC_CELL

T150 TPC26T

1

12

SIO_EXT_SCI# 17

1.25V_GFX_PCIE_ON 58

INVERTER_CBL_DET# 28
AUX_LCD_CBL_DET# 28

NO.32

12
12

T65 TPC26T

1

+3.3V_ALW

12

R234

100KOhm

5%

12

12

C383
1UF/10V

MLCC/+/-10%
pt_c0603

AUX_EN_WOWL 50

HOST_DEBUG_TX 50

HOST_DEBUG_RX 50

EC_PWM_2 54
EC_32KHZ 38

12

C386

C408

0.1UF/10V

MLCC/+/-10%

10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

Place these caps close to MEC5025

MLX_53398-0371

HOLD2

CON5

3
2

WTOB_CON_3P

1

HOLD1

/*

45

Pin 1
Pin 3

12

C441

0.1UF/10V

MLCC/+/-10%

DOCK_SMBCLK

DOCK_SMBDAT

LCD_SMBCLK

LCD_SMBDAT

PBAT_SMBDAT

PBAT_SMBCLK

THRM_SMBCLK
THRM_SMBDAT

Flash Recovery

12

C405

0.1UF/10V

MLCC/+/-10%

1 = Enabled.
0 = Disabled

1

12

C442

0.1UF/10V

MLCC/+/-10%

+5V_ALW

R228 8.2KOhm

12
5%

R239 8.2KOhm

12
5%

+3.3V_ALW

R227 8.2KOhm

12
5%

R238 8.2KOhm

12

5%

R306 2.2KOhm

12

5%

R318 2.2KOhm

12

5%

+3.3V_ALW

RN38A

RN38B

4.7KOhm

4.7KOhm

5%

5%

pt_2r4p0402_h18

pt_2r4p0402_h18
34

12

+3.3V_ALW

12

R229

1KOhm

SFPI_EN

12

R226
1KOhm

5%

/*5%

External Work Around
Circuit.

R311

100KOhm

/*5%

12

M08 : CH501H / CHENMKO

D11

R313

ALWON

21

RB500V-40 /*

A A

<Variant Name>

PROJECT:

10KOhm /*

5%

5

12

Q42

1

PMBS3906 /*

Lanai

For MEC5025 Rev. C : C4519= 22uF and
populate workaround circuit.
For MEC5025 Rev. D : C4519= 4.7uF and

+3.3V_ALW

depopulate workaround circuit.

R215

10KOhm

/*5%

C380

12

4.7UF/6.3V /*

2
E

B

C
3

Q45 2N7002 /*

R237

100KOhm

/*5%

REVISION

12

MLCC/+/-10%pt_c0603

3

D

1

G

S

2

12

1.2

R224 0Ohm

12

/*5%

DATE:
SHEET OF

VR_CAP

Monday, March 19, 2007

37 69

4

MLX_53398-0571

CON6

7

5

SIDE2

4
3
2

6

1

SIDE1

WTOB_CON_5P

/*

DESCRIPTION:

Pin 1

Pin 5

+3.3V_ALW

1

FWP#

12

R327

100KOhm

5%

12

R326

100KOhm

/*5%

12

R330
100KOhm

5%

R331
200KOhm

5%

12

Low=
Write Protected.

Flash Write
Protect bottom

+3.3V_ALW

5
4
3
2
1

Debug Serial Port
Flash Recovery
Port.

R205
1MOhm

5%

12

R207 0Ohm

12

5%

Not Stuff 0 ohm when doing
Flash recovery.

R208
10KOhm

5%

12

MEC5025

R206
10KOhm

5%

12

8051_RX
8051_TX

DEBUG_ENABLE#

3

RELEASE DATE :

LOM_SMB_ALERT#
DOCK_SMB_ALERT#
SIO_SPI_CS#
SBAT_DH_SMBDAT
SBAT_DH_SMBCLK
TP_DET#
BC_DAT
BC_A_DAT

DDR_ON
ICH_RSMRST#
CHIPSET_ID0
CHIPSET_ID1

NO.34, NO.35

R244 100KOhm 5%

12

R241 10KOhm 5%

12

R523 10KOhm 5% /*

12

R243 10KOhm 5%

12

R225 10KOhm 5%

12

R242 100KOhm5%

12

R329 100KOhm5%

12

R273 100KOhm5% /*

12

R618 100KOhm 5%

12

R222 100KOhm 5%

12

R240 0Ohm 5%

12

R619 0Ohm 5% /*

12

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

+3.3V_ALW

NO.17

STANLY_HSU

4K of internal
bootblock flash

LCD_CBL_DET_R28

LCD_CBL_DET

+3.3V_ALW

+5V_ALW

5

10kOhm
10kOhm
10kOhm
10kOhm

R610 10KOhm 5%

12

4

RN39A

12

PCIE_WAKE#

RN39B

34

SYS_PME#

RN39C

56

RN39D

78

DOCK_SMB_PME#

NO.15

3

2

+3.3V_ALW

1

D D

Discrete

12

12

R541

10KOhm

12

R542

10KOhm

/*

UMA

BID2 BID1 BID0 M08 M08B
0 0 0 ENG1(X00) ENG1(X00)

C C

0 0 1 ENG2(X01) ENG2(X01)
0 1 0 ENG3(X02) ENG3(X02)
0 1 1 ENG4(X03) ENG4(X03)
1 0 0 QT(X04) QT(X04)
1 0 1 RAMP(A00) RAMP(A00)
1 1 0

12

R539

10KOhm

5%

5%

/*

12

12

R538

10KOhm

5%

5%

24MHz Clock

R544

/*

12

1MOhm 5%

X6

C697
30PF/50V

MLCC/+/-5%
/*

12

C683

0.1UF/10V

MLCC/+/-10%

12

24Mhz

/*

L47

21

BLM18PG181SN1

pt_l0603

Use BLM18PG if
SIO USB Hub is
utilized.

12

C679

0.1UF/10V

MLCC/+/-10%

ECE5011_XTAL2_R

180Ohm

12

C665

0.1UF/10V

MLCC/+/-10%

12

C726

0.1UF/10V

MLCC/+/-10%

ECE5011_XTAL1_R

12

B B

+3.3V_ALW

Board ID Straps

+3.3V_ALW

12

NO.26

R535

R537

10KOhm

10KOhm

5%

/* 5%

BID0
BID1
BID2
VGA_IDENTIFY

12

R534

R536

10KOhm

10KOhm

5%

5%

/*

VGA_IDENTIFY
1 = Discrete Gfx.
0 = UMA

ECE5011_XTAL1

R546

ECE5011_XTAL2

12

0Ohm 5%

/*

12

C676
30PF/50V

MLCC/+/-5%
/*

Crystal and surrounding
components not needed unless
SIO USB Hub is utilized

EC_VDDA

12

12

C666

0.1UF/10V

MLCC/+/-10%

12

12

C686

0.1UF/10V

MLCC/+/-10%

C664

0.1UF/10V

MLCC/+/-10%

C698

0.1UF/10V

MLCC/+/-10%

12

C675

0.1UF/10V

MLCC/+/-10%

12

C702

0.1UF/10V

MLCC/+/-10%

R540 R585 , ECE5011 is suff ,
ECE5021 is not stuff

Note : for ECE5011 only
ECE5021 will be non_stuff

R532 R548 R543 , ECE5011 is
suff , ECE5021 is not stuff

12

C674

4.7UF/6.3V

pt_c0603
MLCC/+/-10%
/*

R569 R570 R533 ,ECE5011 is
suff , ECE5021 is not stuff

R560 R552 R574,ECE5011 is
suff , ECE5021 is not stuff

12

C678

4.7UF/6.3V

MLCC/+/-10%
pt_c0603
/*

12

Place these caps near ECE5011

A A

5V_3V_1.8V_1.25V_RUN_PWRGD51

+3.3V_ALW

C681

0.1UF/10V

MLCC/+80-20%
/*

PBAT_PRES#59

T88

SYS_PME#32

PCIE_WAKE#35,47,50

USB_BACK_EN#50

LOM_LOW_PWR47

LED_MASK#15,41

GFX_DEVID222

SIO_EXT_WAKE#17

ICH_PME#16

ICH_PCIE_WAKE#17

WLAN_RADIO_DIS#50

EXPRCRD_PWREN#35
EXPRCRD_STDBY#35

IMVP6_PROCHOT#53

LCD_TST28

R540 10KOhm 5%
R585 10KOhm 5%

R547 10KOhm

12

T86
T87
T69
T81
T57
T60
T83
T64
T73
T76

GFX_CORE_ON58

HDDC_EN31

MODC_EN31

EC_VDDA

12

12

C671

C672

4.7UF/6.3V

0.1UF/10V

pt_c0603

MLCC/+80-20%

MLCC/+/-10%

EC_32KHZ37

+3.3V_ALW

12

C727

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

SBAT_PRES#
PWRUSB_OC#
MODPRES#
SC_DET#
DBAY_MODPRES#

LOM_CABLE_DETECT
DOCKED
LCD_TST

SBAT_PRES#

1

SYS_PME#
PCIE_WAKE#

BID2
VGA_IDENTIFY

LOM_LOW_PWR
SC_DET#

R589 0Ohm

IMVP6_PROCHOT#

LCD_TST

12
12

/*
/*

ECE5011_XTAL2
ECE5011_XTAL1

5%
/*
1
1
1
1
1
1
1
1
1
1

MODPRES#
DBAY_MODPRES#

R532
R548

R543
R569

R570

EC_32KHZ

12

R533

R560

R552
R574

12

C712

C705

0.1UF/10V

4.7UF/6.3V

MLCC/+80-20%

MLCC/+/-10%

/*

pt_c0603
/*

R584 10KOhm 5%

12

R587 10KOhm 5%

12

R564 100KOhm 5%

12

R588 10KOhm 5% /*

12

R565 10KOhm 5%

12

R563 10KOhm 5%

12

R592 100KOhm 5%

12

R568 100KOhm 5%

12

0Ohm

/*

0Ohm
0Ohm
0Ohm

/*
/*

0Ohm

/*
/*

0Ohm

/*

12

RBIAS

0Ohm

/*

0Ohm

/*

0Ohm

/*

5%

U29

97

GPIOA[0]

98

GPIOA[1]

99

GPIOA[2]

100

GPIOA[3]

101

GPIOA[4]

102

GPIOA[5]

103

GPIOA[6]

104

GPIOA[7]

112

GPIOF[4]

111

GPIOF[5]

110

GPIOF[6]

109

GPIOF[7]

88

GPIOG[0]

89

GPIOG[1]

90

GPIOG[2]

91

GPIOG[3]

92

GPIOG[4]

93

GPIOG[5]

94

GPIOG[6]

95

GPIOG[7]

26

GPIOH[4]

27

GPIOH[5]

32

GPIOH[6]

33

GPIOH[7]

105

OUT65

127

GPIOJ[0]

126

GPIOI[7]

122

GPIOI[3]

123

GPIOI[4]

9

GPIOJ[2]

10

GPIOJ[3]

13

GPIOJ[6]

12

GPIOJ[5]

15

GPIOK[0]

16

GPIOK[1]

19

GPIOK[3]

18

GPIOK[2]

21

GPIOK[5]

22

GPIOK[6]

63

GPIOD[3]

28

GPIOD[4]

29

GPIOD[5]

30

GPIOD[6]

31

GPIOD[7]

5%

12

125

GPIOI[6]

8

VCC1_1

5%

14

12

GPIOJ[7]

5%

20

12

GPIOK[4]

5%

11

12

GPIOJ[4]

17

VSS1

5%

12

23

GPIOK[7]

36

VSS2

51

VSS3

72

VSS4

87

VSS5

96

KHz_32

121

VSS6

5%

12

128

GPIOJ[1]

34

VCC1_2

57

VCC1_3

85

VCC1_4

108

VCC1_5

5%

12

119

GPIOI[1]

5%

120

12

GPIOI[2]

86

CAP_LDO

5%

124

12

GPIOI[5]

ECE5021-NU

+3.3V_ALW

VSS7
VSS8
VSS9

VSS10
VSS11
VSS12
VSS13

VCC1_6

VSS14
VSS15

VSS16
VSS17
VSS18
VSS19

VCC1_7

VSS20
VSS21
VSS22

BC_CLK
BC_DAT

BC_INT#

GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]

GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]

GPIOD[0]

GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]

CIRTX
CIRRX

GPIOD[1]/CIR TX

GPIOD[2]/CIRRX

GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]

GPIOH[0]
GPIOH[1]
GPIOH[2]
GPIOH[3]

VSS23

TEST_PIN

PWRGD_PS

IMVP6_PROCHOT#
HP_NB_SENSE

37
56
39

54
52
49
47
42
41
46

NC

44

55
53
50
48
43
38
45
40

60
59
58

65
66
82
81
80
79
78
77

76
75
67
68
69
70
71
73

74

1
2
3
4
5
84
83
6

113
114
61
62
118
117
116
115

24
25
106
107

64

35
7

PWRUSB_OC#
HP_NB_SENSE

DOCK_SMB_PME#

DOCKED

R590 100KOhm

LOM_CABLE_DETECT

RSV_TEST_PIN

5%

12

BID0
BID1

1

1

No.44

R554 100KOhm 5%

12

R583 100KOhm 5%

12

BC_CLK 37

BC_DAT 37

BC_INT# 37

USB_SIDE_EN# 39

NB_MUTE# 45,46

ADAPT_OC 57
ADAPT_TRIP_SEL 57

XDP_DBRESET# 7,17,52

PS_ID_DISABLE# 59
PANEL_BKEN 22

M_LED_BK# 42

NO.12

FREE_CIRRX 41
LID_CL_SIO# 42

1.05V_RUN_ON 55
ATF_INT# 43

WIRELESS_ON/OFF# 42
BT_RADIO_DIS# 41
WWAN_RADIO_DIS# 50

T79

Reserved for Broadcom
LOM solution

T58

+3.3V_RUN

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

38 69

DESCRIPTION:

4

ECE5021

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

STANLY_HSU

1

A

1 1

B

C

D

E

2 2

USB_SIDE_EN#38

3 3

+5V_ALW

12

C653

0.1UF/10V

MLCC/+/-10%

F1

PTTC. 1.6A

12

1.6A/6V

J1

12

12

2MM_OPEN_5mil

12

C655

10UF/10V

MLCC/+/-10%
/*
pt_c1206_h75

Place one 150uF cap by each

12

7
8

6
5

USB connector

+USB_SIDE_PWR

+USB_SIDE_PWR

USB_OC0_1# 16

ICH_USBP1-16
ICH_USBP1+16

ICH_USBP0-16
ICH_USBP0+16

/*

U25

GNDIN

3

EN1#

OUT1
OC1#

4

EN2#

OUT2
OC2#

TPS2062DR

USB daughter board connectorNO.53

ICH_USBP1­ICH_USBP1+

ICH_USBP0­ICH_USBP0+

CON17

SUYIN/127153MA010G521ZR

11

NP_NC1

1

2

1

2

3

4

3

4

5

6

5

6

7

8

7

8

9

10

9

10

12

NP_NC2

BTOB_CON_10P

+USB_SIDE_PWR

Each channel is 1A

4 4

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

39 69

B

DESCRIPTION:

USB PORT x 2

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

A

1 1

B

C

D

E

RTC BATTERY

Layout Note:
Place R317 within 500 mils from
SPI flash. Place R316 & R310
within 500 mils of the MEC5025.

SPI_CS0#16

2 2

EC_FLASH_SPI_DIN37

R317 15Ohm5%

12

SPI_SO

+3.3V_SUS

12

R531

10KOhm

5%

U27

1

CE#

2

SO

3

WP#

45

VSS SI

SST25VF016B

HOLD#

D10

21

C368

12

pt_c0805_h57

RB751V_40

D9

21

RB751V_40

MLCC/+/-10%

12

R549

10KOhm

5%

8

VDD

7

SPI_CLK

R316 15Ohm

6

SCK

SPI_SI

12

R310 15Ohm

12

EC_FLASH_SPI_CLK 37
EC_FLASH_SPI_DO 37

12

C682

0.1UF/10V

MLCC/+80-20%

1UF/25V

12

pt_c0603

+RTC_1

C369

2.2UF/6.3V/X5R

MLCC/+/-10%

U12

1

IN

SHDN#

2

GND

34

OUT 5/3#

MAX1615EUK

/*

+RTC

12

R204
1KOhm

5%

RTC_BAT_DET#15

Pin 1
Pin 3

MLX_53398-0371

3 3

+PWR_SRC+3.3V_RTC_LDO+RTC_CELL

5

/*

C367

12

1UF/25V

pt_c0805_h57

CON16

45

HOLD1

1
2

WTOB_CON_3P

3

MOLEX/53398-0371(P6497)

HOLD2

MLCC/+/-10%

4 4

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

40 69

B

DESCRIPTION:

FLASH & RTC

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

C.L. Ho

E

5

4

+3.3V_ALW

3

2

1

MEDIA_LED_R42
POWER_SW#42,43

INSTANT_POWER_SW#37

NO.19

Bluetooth

CON21

MOLEX/48226-1011

WTOB_CON_10P

Touch Pad

TP_DET#37

12

C749 22PF/50V MLCC/+/-5%

1

1

3

3

5

5

7

7

9

9

12

12

12

C752 22PF/50V MLCC/+/-5% /*

C751 22PF/50V MLCC/+/-5%

C750 22PF/50V MLCC/+/-5%

1112

2

2

4

4

6

SIDE1SIDE2

6

8

8

10

10

CON3

MOLEX/48227-1511

WTOB_CON_15P

+3.3V_ALW
+5V_ALW

NO.16

12

12

12

12

C755 22PF/50V MLCC/+/-5% /*

C754 22PF/50V MLCC/+/-5% /*

C753 22PF/50V MLCC/+/-5% /*

C756 22PF/50V MLCC/+/-5% /*

This circuit is only needed if
the platform has the SNIFFER.

R597

12

1617

1

1

2

2

3

SIDE1SIDE2

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

NO.21, NO.39

12

R598
10KOhm

5%

10KOhm

5%

12

R591

10KOhm

5%

Please refer to item 191 of issue_list_0517_TDC ,
"Lanai plan to use 3V TP controller. No need
TP_VCC " . So we delete this circuit which
supply TP_VCC power.

D

S

Q70
BSS138N

BT_ACTIVE#_R 42

2
E

C
3

12

Q71

B

1

C731

33PF/50V

MLCC/+/-5%

MMBT3906LT1G

BT_ACTIVE

1

G

LED_MASK# 15,38

COEX2_WLAN_ACTIVE 50
COEX1_BT_ACTIVE 50

ICH_USBP7- 16

3

2

RN14A

RN14B

4.7KOhm

4.7KOhm

12

D D

DAT_TP_SIO37
CLK_TP_SIO37

C295

0.1UF/10V

MLCC/+80-20%

NO.16

T94

12

BT_RADIO_DIS#38

1

ICH_USBP7+16

Lid Switch(Hall) BIO

+3.3V_ALW +5V_ALW

12

C297

0.1UF/10V

MLCC/+/-10%

C C

B B

34

L20 600Ohm Irat=200mA pt_l0603

21

L19 600Ohm Irat=200mA pt_l0603

21

10PF/50V

10PF/50V

10PF/50V

10PF/50V

56

78

12

34

pt_c_array_8p_79x49_h39

CN2C

CN2D

CN2A

CN2B

+3.3V_RUN

0.1UF/10V

MLCC/+80-20%

12

C730

100PF/50V

MLCC/+/-5%

12

C737

BC_A_DAT37
BC_A_CLK37

BC_A_INT#37

Vendor suggest :
Pin 7 of RC-Rxd is

+3.3V_RUN +3.3V_ALW

R380

R389

0Ohm

0Ohm

5%

5%

/*

12

12

A A

<Variant Name>

PROJECT:

5

+3.3V_CIR

Lanai

open collector
output.it should be
add external pullup
resister

12

R382 100Ohm 5%

REVISION

1.2

FREE_CIRRX38

12

C743

0.1UF/16V

MLCC/+/-10%

DATE:
SHEET OF

+3.3V_RUN

R602

10KOhm

5%
/*

12

12

C498

4.7UF/10V

MLCC/+/-10%
pt_c1206_h71

Monday, March 19, 2007

41 69

4

CIR

U36

4

OUT

3

VS

2

GND2

1

GND1

TSOP36136TR

DESCRIPTION:

TOUCH PAD & BT & CIR & LID

3

RELEASE DATE :

HALL SENSOR

+3.3V_ALW

CON4

MOLEX/48227-0311

1

LID_CL#42

2
3

<OrgName>

2

1

SIDE1
2
3

SIDE2

WTOB_CON_3P

4

5

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

R1

GND

OUT

BT_LED

R2

+3.3V_RUN

1

GND

3

OUT

HDD_LED

Q72

R1

2

DTC114EKA

B

HDD activity LED

12

R214

100KOhm/*5%

SATA_ACT#_R15

D D

R223 0Ohm

pt_r0603

BT activity LED

Q73

BT_ACTIVE#_R41

2

IN

DDTA114YUA_7_F

Q44

5%

2

12

IN

DDTA114YUA_7_F

+3.3V_RUN

1

R2

R1

3

Power&Suspend

U35

NC

1

A

C C

BREATH_LED#37

2
34

GND

74AHC1G04GW

VCC

Y

+3.3V_SUS

5

BREATH_PWRLED

R383 10KOhm

12

Sniffer LED driver circuit

+3.3V_SUS+3.3V_SUS

LED6

2
3

G&Y

REVISION

1.2

Q53

1

GND

3

OUT

DDTA114YUA_7_F

Y

SG

R2

R1

SNIFFER_G_RSNIFFER_Y_R

+5V_RUN

+5V_SUS

+5V_RUN

+5V_RUN

1

DATE:
SHEET OF

Q52

1

GND

R2

2

IN

3

OUT

B B

A A

SNIFFER_Y_R SNIFFER_G_R

LED_WLAN_OUT_R#

BREATH_PWRLED#

HDD_LED#

BT_LED#

SNIFFER_Y_R

SNIFFER_G_R

<Variant Name>

R1

DDTA114YUA_7_F

LED4 BLUELITE-ON/LTST-C192TBKT-5A

LED2 BLUELITE-ON/LTST-C192TBKT-5A

LED3 BLUELITE-ON/LTST-C192TBKT-5A

LED5 BLUELITE-ON/LTST-C192TBKT-5A

SNIFFER_Y_R

SNIFFER_G_R

12

+

12

+

12

+

12

+

R599 220Ohm

12

R371 220Ohm

12

PROJECT:

5

NO.50

R387 750Ohm 5%

R384 750Ohm 5%

R385 750Ohm 5%

R388 750Ohm 5%

12

12

12

12

5%

pt_r0603

5%

pt_r0603

Lanai

4

Q46

R1

2

DTC114EKA

BT_LED#

3
C

E

R2

1

Q54

1

PMBS3904

5%

12

C497
1UF/10V

MLCC/+/-10%
pt_c0603

2

SNIFFER_GREEN# 37SNIFFER_YELLOW# 37

IN

BAT2_LED

R386

220Ohm

BAT1_LED_BLUE#

Monday, March 19, 2007

4

HDD_LED#

3
C

B

E

R2

1

BREATH_PWRLED#

3

C

B

E
2

+5V_ALW

NO.50

12

12

R381
750Ohm

5%

Orange

5%

1

2

Blue

LED1

+

+

3

4

42 69

LED_WLAN_OUT#50

MAIN_PWR_SW#37 POW ER_SW# 41,43

BLUE&ORANGE

LITEON/LTST-C195TBKFKT

NO.37

DESCRIPTION:

Battery status

BAT1_LED#37

BAT2_LED#37

NO.7

WLAN

R607 10KOhm 5%

12

+RTC_CELL

12

R250

100KOhm 5%

R248 10KOhm

12

12

C393
1UF/10V

MLCC/+/-10%
pt_c0603

SWITCH & LED

3

Q47

2

IN

Q48

2

IN

DDTA114YUA_7_F

+3.3V_WLAN

12

5%

3

+3.3V_ALW

1

R2

R1

R2

+3.3V_RUN

1

B

POWER_SW#

3

+3.3V_ALW

1

GND

3

OUT

2
E

Q36
MMBT3906LT1G

C
3

LED_WLAN_OUT_R

12

C298
1UF/10V

MLCC/+/-10%
pt_c0603 /*

DDTA114YUA_7_F

R1

R606
10KOhm

5%

Layout Note: C pad is used
as a Provision For External
Power Cycling, Must place C
on top to be accessed when
Keyboard is removed.

GND

BAT1_LED

OUT

BAT2_LED

Package 0603

RELEASE DATE :

Q62

R1

2

DTC114EKA

Q38

R1

2

DTC114EKA

NO.12 NO.33

2

BAT1_LED_BLUE#

3
C

B

E

R2

1

LED_WLAN_OUT_R#

3
C

B

E

R2

1

<OrgName>

2

1

Sniffer Switch

SNIFFER1

SNIFFER2

WIRELESS_ON/OFF#38

SNIFFER_PWR_SW#37

CON22

1
2
3
4

SLIDE_SWITCH_4P

FOXCONN/1BS008-13130-042-7F

+3.3V_RUN

+RTC_CELL

1

GND1

2

NP_NC1

3

NP_NC2

4

GND2

12

R551

100KOhm

pt_r0603

12

C739
1UF/10V

MLCC/+/-10%
pt_c0603
/*

12

R522

100KOhm 5%

12

C406
1UF/10V

MLCC/+/-10%
pt_c0603
/*

5
7
8
6

5%

R600 0Ohm 5%

12

R284 0Ohm 5%

12

Hall Switch

+3.3V_ALW

12

R581
100KOhm

5%

R575 10Ohm

5%

12

12

C711

0.047UF/10V

MLCC/+/-10%

Media Bottom Board LED drive circuit

+5V_RUN

OUT

GND

1

3

Q65

R2

R1

IN

2

M_LED_BK#38

M_LED_BK#

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

M_LED_BK_O

DDTA114YUA_7_F

R611 0Ohm

1

12

5%pt_r0805_h24

SNIFFER1

SNIFFER2

LID_CL# 41LID_CL_SIO#38

MEDIA_LED_R 41

5

+3.3V_RUN

THERM_B1

THERM_B2

5

NO.9

R401

10KOhm 5%

12

R398

0Ohm

pt_r0805_h24
5%

12

FAN1_VOUT
FAN1_VOUT_FB

12

C274

0.1UF/10V

MLCC/+80-20%

+3.3V_SUS

R128

8.2KOhm

5%

THERMATRIP1#

12

3

Q31

C

B

2

E

1

MMST3904_7_F

+3.3V_SUS

R127

8.2KOhm

5%

12

3

Q30

C

B

2

E

1

MMST3904_7_F

Lanai

1
2
3

+RTC_CELL

12

THERMATRIP2#

REVISION

FAN1_TACH 37

45

HOLD1

CON11

WTOB_CON_3P

MOLEX/53398-0371(P6497)

HOLD2

Put C283 close to
Guardian.

H_THERMDA7

H_THERMDC7

C243

0.1UF/10V

MLCC/+/-10%

12

C246

0.1UF/10V

MLCC/+80-20%

12

C245

0.1UF/10V

MLCC/+80-20%

1.2

C244 needs to be placed
near Guardian IC.

THERMTRIP_VGA#22

DATE:
SHEET OF

Pin 1
Pin 3

MLX_53398-0371

D D

21

D16

/*

RB751S40T1G

C C

+3.3V_SUS

C246 needs to be placed near
Guardian IC.

B B

+1.05V_VCCP

H_THERMTRIP#7

C245 needs to be placed near
Guardian IC.

A A

+1.05V_VCCP

THERMTRIP_MCH#10

<Variant Name>

12

C505
22UF/10V

MLCC/+/-20%
pt_c1206_h75

R149

+3VSUS_THRM

12

49.9Ohm

1%

12

R139 2.2KOhm 5%

12

R138 2.2KOhm 5%

PROJECT:

4

REM_DIODE1_N

12

C282
2200PF/50V

MLCC/+/-10%

REM_DIODE1_P

Put C282 close to Guardian.
Put C610 close Diode

Place under CPU.

12

C283
470PF/50V

MLCC/+/-10%

SUSPWROK17,51

ICH_PWRGD#51 ACAV_IN 37,57

+3.3V_SUS

R141 10KOhm /*
R137 10KOhm /*

+3.3V_RUN

NO.56

+3.3V_SUS

R159

12

332KOhm

12

1%

C287

0.1UF/10V

MLCC/+80-20%

Monday, March 19, 2007

43 69

4

1

E

Q59

B

2

C

MMST3904

3

THRM_SMBDAT37
THRM_SMBCLK37

R125 1KOhm 5%

12

R135 1KOhm 5%

12

R145 1KOhm 5%

12
12

MDC_RST_DIS#36
SIO_GFX_PWR

AUDIO_AVDD_ON45

R119

8.2KOhm

5%

12

THERM_VEST

R155
118KOhm

1%

12

REM_DIODE1_P
REM_DIODE1_N

H_THERMDA
H_THERMDC

+3VSUS_THRM

+RTC_CELL

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

THERM_VEST

12

FAN1_VOUT

5V_CAL_SIO1#
5V_CAL_SIO2#

+3.3V_SUS

R116

2.2KOhm

5%

12

Q28

THERM_B3

B

2

MMST3904_7_F

NO.56

12

C286
2200PF/50V

MLCC/+/-10%

DESCRIPTION:

12

12

C610
2200PF/50V

/*
MLCC/+/-10%

C284
2200PF/50V

MLCC/+/-10%

Put C284 close to Guardian.
Put C568 close Diode

Place under DIMM.

THERM_PWRGO
+3V_PWROK#

T17

1

T16

1

R102

8.2KOhm

5%

12

THERMATRIP3#

3
C

12

C244

E

0.1UF/10V

1

MLCC/+80-20%

Note:
VSET = (Tp-70)/21, where Tp = 70
to 101 degree C.
Tp set at 88 degrees C.
Guardian temp tolerance = +-3
degrees C.

EMC4001

3

REM_DIODE3_N

REM_DIODE3_P

Guardian

U8

11

SMDATA

12

SMCLK

38

DP1

37

DN1

41

DP2

40

DN2

35

3V_SUS

21

RTC_PWR3V

23

VSUS_PWRGD

16

3V_PWROK#

17

THERMTRIP1#

18

THERMTRIP2#

19

THERMTRIP3#

42

VSET

26

XEN

34

VSS

7

FAN_OUT1

8

FAN_OUT2

39

FAN_DAC1

10

GPIO1

13

GPIO2

14

GPIO3

15

GPIO4

22

GPIO5

36

GPIO6/FAN_DAC2

EMC4001_HZH

3

1

E

Q58

B

2

C

MMST3904

3

49

VCP1
VCP2

GND

ATF_INT#
POWER_SW#
ACAVAIL_CLR

THERMTRIP_SIO

SYS_SHDN#

LDO_SHDN#/ADDR

LDO_POK

LDO_SET

LDO_OUT2
LDO_OUT1

LDO_IN2
LDO_IN1

VDD_3V

VDD_5V_1
VDD_5V_2

DP3
DN3

DP4
DN4

DP5
DN5

12

C568
2200PF/50V

/*
MLCC/+/-10%

43

VCP2

46
45

44
48

47
2

1
20

3
4
25
24

LDO_SHDN#_ADDR

27
33

THERM_LDO_SET

28
32

31

THERM_LDO_IN

30
29

9
5

6

+3.3V_RUN

12

C261

0.1UF/10V

MLCC/+80-20%

+5V_RUN

12

C272

0.1UF/10V

MLCC/+80-20%

REM_DIODE4_N

12

C285
2200PF/50V

MLCC/+/-10%

REM_DIODE4_P

Put C285 close to Guardian.
Put C612 close Diode

Place under Skin.

Note:
150K input impedance on VCP1 (Pin 43)

REM_DIODE3_P
REM_DIODE3_N

REM_DIODE4_P
REM_DIODE4_N

REM_DIODE5_P
REM_DIODE5_N

+RTC_CELL

R146 7.5KOhm

+2.5V_RUN

+3.3V_RUN
+5V_RUN

12

C265

10UF/10V

MLCC/+80-20%
pt_c0805_h53

12

C273
10UF/10V

MLCC/+/-20%
pt_c0805_h57

RELEASE DATE :

2

1
E

Q60

B

2

+3.3V_SUS

R136
10KOhm

5%

12

/*

1

12

Layout Note:
Place those capacitors close to
EMC4001.

+2.5V_RUN

12

C269

0.1UF/10V

MLCC/+80-20%
/*

2

12

C

MMST3904

3

PWR_MON 53

R129

10KOhm

5%

12

ATF_INT# 38
POWER_SW# 41,42

T13

THERM_STP# 54

+3.3V_SUS

1%

2.5V_RUN_PWRGD 51

12

C276
10UF/4V

MLCC/+/-20%
pt_c0805
/*

C612
2200PF/50V

/*
MLCC/+/-10%

REM_DIODE5_N

REM_DIODE5_P

Layout Note:
R4747 is put on BOT DIMM
sockett

VCP2

5V_CAL_SIO2#

Voltage margining
circuit for LDO output.
For Vmargin stuff R152
and R4707=30K. R158=1K
for production.

12

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

Put C279 close to GuardianDiscrete

12

C279

12

R209

10KOHM

5%
THERMISTOR 10K OHM

31

Q37

3

D

2

2

G

S

1

RHU002N06

R131 10KOhm 5% /*

THERM_LDO_IN

C266

0.1UF/10V

MLCC/+80-20%

1

VGA_THERMDN 26

470PF/50V

12

12

VGA_THERMDP 26

+3.3V_SUS+5V_SUS

R156

2.2KOhm

1%

12

12

THERM_LDO_SET

C252
1UF/10V

MLCC/+80%-20%

This Value of R144 can
be 0.27 or 0 ohm and the
package is 1210

C288

0.1UF/10V

MLCC/+/-10%

0603
Package.

0Ohm

pt_r1210_h24
pt_c0603

1

R144

R160

10KOhm

1%

12

5V_CAL_SIO1#

+2.5V_RUN

12

+3.3V_RUN

+3.3V_SUS

12

R152

31.6KOhm

1%
/*

R158
1KOhm

5%

12

pt_r0603

A

VDDA

FROM ICH

SPKR17
BEEP37

FROM EC

1 1

2 2

3 3

U17

A

1

VCC

B

2
34

GND

Y

SN74AHCT1G86DCKR

PLACE CLOSE TO U18 PIN13

If SENSE_A total length >6"
change C459 to 0.1uF

AUD_HP1_NB_SENSE45,46

4 4

1

G

C457 0.1UF/16V/X7R

5

12

3

D

S

2

R335

AUD_SENSE_A

R345

39.2KOhm

1%

Q50
2N7002

12

12

MLCC/+/-10%

10KOhm 5%

NO.38

AVDD_CODEC

R341

5.1kOhm

1%

12

12

C459

1000PF/50V

MLCC/+/-10%

C448

12

0.1UF/16V/X7R

MLCC/+/-10%

R336

2.2KOhm

5%

12

PLACE CLOSE TO U18 PIN6 PLACE CLOSE TO U18 PIN5

ICH_AZ_CODEC_BITCLK

R550

/*

47Ohm

5%

12

12

5 5

<Variant Name>

C692

0.1UF/16V

MLCC/+/-10%
/*

PROJECT:

A

Lanai

ICH_AZ_CODEC_SDOUT

R555

/*

47Ohm

5%

12

12

C691

/*

0.1UF/16V

MLCC/+/-10%

REVISION

1.2

DATE:
SHEET OF

B

AUD_PC_BEEP

+3.3V_RUN

PLACE CLOSE TO U18 PIN34

If SENSE_B total length >6"
change C719 to 0.1uF

AUD_MIC_SWITCH46

1

G

AUD_HP2_NB_SENSE46

Monday, March 19, 2007

44 69

B

ICH_AZ_CODEC_BITCLK15

ICH_AZ_CODEC_SDIN015

ICH_AZ_CODEC_SDOUT15
ICH_AZ_CODEC_SYNC15
ICH_AZ_CODEC_RST#15

AUD_DMIC_IN028

AUD_DMIC_CLK28
AUD_SPDIF_OUT50

For TV port

R553

39.2KOhm

1%

12

3

D

Q66
2N7002

S

2

DESCRIPTION:

DVDD_CORE

NO.4

AUD_EAPD#45

AUD_EAPD#45

AUD_SENSE_B

R559

20KOhm

1%

12

3

D

Q67

1

2N7002

G

S

2

+3.3V_RUN

21

L50

600Ohm/100Mhz

Irat=500mA
MURATA/BLM18EG601SN1D

NO.4

12

1000PF/50V

MLCC/+/-10%
12
12

5% /*

12

12

12
12

NO.38

AVDD_CODEC

R558

5.1kOhm

1%

12

12

C719

1000PF/50V

MLCC/+/-10%

STAC9228

pt_c0805_h57

C746

R5560Ohm5%
R567100KOhm 5%
R5780Ohm

R55733Ohm5%

R5770Ohm5%
R5730Ohm5% /*

C

/*

12

10UF/10V/X5R

C

C685

pt_c0603

1UF/10V/X7R

MLCC/+/-20%

pt_c0805_h57

MLCC/+/-20%

10UF/10V/X5R

DVDD_CORE1
DVDD_CORE3

HDA_SDI

EAPD#_CODEC

12

12

12

C693

C687

0.1UF/16V/X7R

MLCC/+/-10%

MLCC/+/-10%

C444

U18

1

DVDD_CORE1

9

DVDD_CORE2

40

DVDD_CORE3

6

BITCLK

8

SDI

5

SDO

10

SYNC

11

RESET#

2

VOLUME_UP/DMIC_0/GPIO1

3

VOLUME_DOWN/DMIC_1/GPIO2

47

SPDIF_IN/GPIO0/EAPD/DMIC_CLK

48

SPDIF_OUT/ADAT_OUT

4

DVSS1

7

DVSS2

STAC9228

PLACE BETWEEN U18 and
U19

JP5

12

SHORTPIN

/*

RELEASE DATE :

AVDD1
AVDD2

SENSE_A
SENSE_B

PORTA_L
PORTA_R

VREFOUT_A

PORTB_L
PORTB_R

VREFOUT_B

PORTC_L
PORTC_R

VREFOUT_C

PORTD_L
PORTD_R

VREFOUT_D

PORTE_L
PORTE_R

VREFOUT_E

PORTF_L
PORTF_R

VREFOUT_F

PORTG_L

PORTG_R

PORTH_L
PORTH_R

CD_L

CD_GND

CD_R

PCBEEP

CAP2

VREFFILT

AVSS1
AVSS2

D

25
38

13
34

39
41
37

21
22
28

23
24
29

35
36
32

14
15
31

16
17
30

43
44

45
46

18
19
20

12
33

27

26
42

D

AVDD_CODEC

AUD_SENSE_A
AUD_SENSE_B

AUD_EXT_MIC_L3

AUD_PC_BEEP

NO.48

VDDA

L51

21

12

C724

10UF/10V

pt_c0805_h57

MLCC/+/-20%

/*

12

C717

1000PF/50V

1000PF/50V

MLCC/+/-10%

AUD_VREFOUT_E 46

/*

12

C696

1000PF/50V

MLCC/+/-10%

R3480Ohm5%

12

R6030Ohm5% /*

12

R3330Ohm5% /*

12

DESIGN ENGINEER :SCHEMATIC FILE NA ME :

PORT C : LEAVE NC

Port A---> HP1
Port D---> Speaker
Port E---> ext Mic
Port F---> HP2

600Ohm/100Mhz

Irat=500mA
MURATA/BLM18EG601SN1D

12

pt_c0603

1UF/10V/X7R

/*

12

C708

MLCC/+/-10%

AUD_LINE_OUT_L 45
AUD_LINE_OUT_R 45

R582

pt_r0603

12

5.1Ohm

1%

R579

12

5.1Ohm

1%

pt_r0603

AUD_HP2_OUT_L 46
AUD_HP2_OUT_R 46

/*

12

C701

1000PF/50V

MLCC/+/-10%

12

C729

pt_c0805_h57

10UF/10V/X5R

pt_c0805_h57

MLCC/+/-20%

Yihao Yeh

E

IF NO INTERNAL MICS.

12

C722

C723

0.1UF/16V/X7R

MLCC/+/-10%

MLCC/+/-10%

AUD_HP1_OUT_L 45
AUD_HP1_OUT_R 45

1UF/10V/X7R

MLCC/+/-10%

AUD_EXT_MIC_L4
AUD_EXT_MIC_R4AUD_EXT_MIC_R3

10UF/10V/X5R

DOCK_HP_MUTE# and
AUD_SPDIF_SHDN are
removed.

12

pt_c0603
pt_c0603

MLCC/+/-10%

C721

MLCC/+/-20%

12

C716

12

C706
1UF/10V/X7R

E

AUD_EXT_MIC_L 46
AUD_EXT_MIC_R 46

Signal Inveter for Speaker Shutdown

A

Allow speakers to work while class driver is
installed

+5V_SPK_AMP

1 1

AUD_SPK_ENABLE#

AUD_EAPD#44

FROM EC

NB_MUTE#38,46

2 2

PLACE JUST BEFORE
+5V_MAX9789 CROSSES
MOAT

L52

21

60Ohm Irat=3A

pt_l0805_h41

MURATA/BLM21PG600SN1(Y8220)<G>

3 3

+5V_SPK_AMP+5V_RUN

pt_c0805_h57

10UF/10V/X5R

1

G

1

G

12

C725

MLCC/+/-20%

R367

100KOhm

5%

12

3

D

Q69

2N7002

S

2

3

D

Q68

2N7002

S

2

+5V_SPK_AMP

R593

12

AUDIO_AVDD_ON43

FROM EC

NOTE:For TPA6040A,
pop C486 and no pop
R376

100KOhm

5%

TEMPORARY VALUES. FINAL
VALUES CHOSEN IN PT
PHASE.

AUD_LINE_OUT_R44

AUD_LINE_OUT_L44

R376

12

0Ohm5%

/*

MLCC/+/-10%

0.033UF/16V/X7R

NO.47

B

Place C490 close
to Pin 30

12

12

MLCC/+/-10%

0.1UF/16V/X7R

NOTE:For TPA6040A, pop
C487 and C486(0402
X5R) and no pop R601
and R376. C487 andC486
value should match
C494 and C493

12

12

/*

/*

C740

47PF/50V

C738

47PF/50V

MLCC/+/-5%

MLCC/+/-5%

pt_c1206_h59
MLCC/+/-10%

pt_c1206_h59
MLCC/+/-10%

12

C486

C494

12

0.033UF/100V

C493

12

0.033UF/100V

AUD_SPK_L146
AUD_SPK_L246

+5V_SPK_AMP

C490

MLCC/+/-10%

MLCC/+/-10%

12

0.033UF/16V/X7R

12

1UF/10V/X7R

MLCC/+/-10%

1UF/10V/X7R

C487

SPKR_INR_AMP1
SPKR_INL_AMP1

C483

pt_c0603

C495

pt_c0603

NO.47

R601

/*
12

0Ohm 5%

MLCC/+/-20%

C

+5V_SPK_AMP

+5V_AMP1

12

C491

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

AUD_AMP_GAIN1
AUD_AMP_GAIN2

32

U19

GAIN1

1

SPKR_RIN-

2

SPKR_RIN+

3

SPKR_LIN+

4

SPKR_LIN-

5

SPGND1

6

LOUT+

7

LOUT-

817

SPVDD1 HPVDD

C481

12

10UF/10V/X5R

TPA6040A4RHBR

pt_c0805_h57

NO.47

CPVDD1

9101112131415

VDDA Range = 1.21V ~ 4.85V
(SET =1.23V). If SET=0 V,
VDDA = 4.75V

VDDA

21

L28

600Ohm

Irat=200mA

30

31

VDD

GAIN0

C1P

CPGND2

MLCC/+/-10%

MURATA/BLM18AG601SN1(J5535)<G>

26

27

28

29

SGND

HP_INL

REG_OUT

C1N

CPVSS

HPVSS

1UF/10V/X7R

HP_INR

HP_OUTR

C741

12

pt_c0603

HP1_INL_AMP1

HP1_INR_AMP1

343536

25

GND2

GND3

REG_EN

BYPASS

SPKR_EN#

HP_EN

SPGND2

ROUT+
ROUT-

SPVDD2

GND1

HP_OUTL

16

C742

12

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

37

GND4

GND5

24
23
22
21
20
19
18

33

D

MLCC/+/-10%

1UF/25V/X7R

12

C496

pt_c1206_h49

C492

pt_c1206_h49

/*

/*

12

12

C489

47PF/50V

MLCC/+/-5%

C488

47PF/50V

MLCC/+/-5%

C735

12

MLCC/+/-20%

10UF/10V/X5R

pt_c0805_h57

pt_c0603

1UF/25V/X7R

MLCC/+/-10%

MUTE#_AMP1

MLCC/+/-10%

1UF/10V/X7R

12

C484

C485

12

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

12

AUD_SPK_ENABLE#

+5V_SPK_AMP

NO.47

R378

100KOhm 5%

/*

12

0Ohm

12

AUD_SPK_R1 46
AUD_SPK_R2 46

+5V_SPK_AMP

E

AUD_HP1_OUT_L 44

AUD_HP1_OUT_R 44

Note: For TPA6040A,
pop R378 and no pop
R375

R375

5%

+3.3V_CPVDD_HPVDD

U34

5

VCC

2

4

A

Y

1

B

GND

3

FROM EC

AUDIO_AVDD_ON 43

C732

12

74AHC1G08GW

AUD_HP1_NB_SENSE 44,46
NB_MUTE# 38,46

NO.25

0.1UF/16V

MLCC/+/-10%

10UF/10V/X5R

D

C733

12

pt_c0805_h57

AUD_HP1_JACK_L 46
AUD_HP1_JACK_R 46

DESIGN ENGINEER :SCHEMATIC FILE NAME :

ROUTE VIA TRACE BACK TO TIE POINT.

Yihao Yeh

E

ROUTE VIA TRACE BACK TO TIE POINT.

GAIN SETTING RESISTORS

+5V_SPK_AMP

4 4

R377

100KOhm 5%

R379

100KOhm 5%

5 5

<Variant Name>

+5V_SPK_AMP

100KOhm 5%

12

12

/*

100KOhm 5%

12

12

PROJECT:

R368

R374

A

/*

AUD_AMP_GAIN1
AUD_AMP_GAIN2

Lanai

Gain1

0

0

1

1

REVISION

1.2

Gain2

0

1

0

15.6

1

21.6

DATE:
SHEET OF

Gain

6

dB

10

dB

dB

dB

Monday, March 19, 2007

45 69

B

+3.3V_RUN

L54

21

600Ohm

MURATA/BLM18AG601SN1(J5535)<G>

Chang to 3.3V_RUN for
CPVDD and HPVDD with
bead.

DESCRIPTION:

AMP MAX9789

Irat=200mA

C736

12

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

C482

12

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

ROUTE VIA TRACE BACK TO TIE POINT.

C

Recommend a star

C734

12

connection for PVSS
and CPVSS at capacitor
C6613 of MAX9789A

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

RELEASE DATE :

+3.3V_CPVDD_HPVDD

MLCC/+/-20%

<OrgName>

A

B

C

D

E

Maxim:1.8V ~ 3.6V
TI:1.8V ~ 4.5V

1 1

AUD_HP2_NB_SENSE44

NO.30

AUD_HP2_OUT_R44

2 2

3 3

AUD_HP2_OUT_L44

pt_c1206_h75

MLCC/+/-10%
pt_c1206_h75

NOTE: MAKE SURE THERMAL PAD
(Pin21)UNDER MAX4411 IS NOT
CONNECTED TO GND

12

MLCC/+/-10%

0.1UF/16V/X7R

NB_MUTE#38,45

C720

12

2.2UF/16VMLCC/+/-10%

12

C728

2.2UF/16V

MLCC/+/-5%

C700

C710

12

12

47PF/50V

47PF/50V

MLCC/+/-5%

C718

U32

5

VCC

74AHC1G08GW

2

4

A

Y

1

B

GND

3

HP2_INR_AMP2
HP2_INL_AMP2

C1P

C704

12

C1N

MLCC/+/-10%

2.2UF/10V/X5R

pt_c0603

14
18

15
13

TPA4411MRTJR

NO.47

1
3

U31

SHDNR#
SHDNL#

INR
INL

C1P
C1N

2.2UF/10V/X5R

PVSS

567

PVSS

12

MLCC/+/-10%

+3.3V_AMP2

10

192021

SVDD

PVDD

PGND

SVSS

2

C690

pt_c0603

GND

SGND

17

L27

21

12

600Ohm

Irat=200mA

C447

MURATA/BLM18AG601SN1(J5535)<G>

1UF/10V/X7R

MLCC/+/-10%

pt_c0603

11

OUTR

9

OUTL

4

NC1
NC2

8

NC3

12

NC4

16

NC5
NC6

+3.3V_RUN

AUD_HP2_JACK_R
AUD_HP2_JACK_L

Speaker CON

CON7

17

1SIDE1

2

2

3

3

4

4

5

5

6

8

6

SIDE2

WTOB_CON_6P

MOLEX/48227-0611

/*

/*

/*

12

12

MLCC/+/-5%

MLCC/+/-5%

100PF/50V/NPO

MLCC/+/-5%

C404

C400

100PF/50V/NPO

100PF/50V/NPO

/*

12

12

MLCC/+/-5%

C387

C394

100PF/50V/NPO

Need to adjust EMI cap values as necessary.

AUD_SPK_L1 45
AUD_SPK_L2 45
AUD_SPK_R1 45
AUD_SPK_R2 45

SPEAKER_DET# 15

NO.48

4 4

AUD_MIC_SWITCH
AUD_HP2_NB_SENSE

AUD_HP1_NB_SENSE

5 5

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

12

R349 100KOhm 5%

12

R362 100KOhm 5%

12

R364 100KOhm 5%

Monday, March 19, 2007

DATE:
SHEET OF

46 69

B

+3.3V_RUN

DESCRIPTION:

AUD_MIC_SWITCH44

AUD_VREFOUT_E44

AUD_EXT_MIC_L44

AUD_EXT_MIC_R44

AUD_HP2_NB_SENSE44

AUD_HP2_JACK_L
AUD_HP2_JACK_R

AUD_HP1_NB_SENSE44,45

AUD_HP1_JACK_L45
AUD_HP1_JACK_R45

AMP MAX4411 & AUDIO JACK

C

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

1617

CON9

WTOB_CON_15P

SIDE1SIDE2

MOLEX/48227-1511

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Yihao Yeh

E

5

4

3

2

1

+1.2V_LOM +2.5V_LOM +3.3V_LAN

12

C35

C68

4.7UF/10V

pt_c0805_h37

D D

+1.2V_LOM

C C

B B

A A

<Variant Name>

+1.2V_LOM

PLTRST_LAN_MINICARD#16,50

SB_LOM_PCIE_RST#16

R51 200Ohm 1%

PROJECT:

L4 600Ohm

MURATA/BLM18AG601SN1

L5 600Ohm

21
21

MURATA/BLM18AG601SN1

PCIE_RX6+/GLAN_RX+16
PCIE_RX6-/GLAN_RX-16

NO.55

12

R32 47Ohm 5%

12

R30 0Ohm 5% /*

LOM_LOW_PWR38

12

Lanai

5

C47

27PF/50V

PCIE_LOM_CLKREQ#21

MLCC/+/-10%

L2 600Ohm

MURATA/BLM18AG601SN1

21

C7

4.7UF/10V

12

12

C25

C33

0.1UF/10V

4.7UF/10V

pt_c0805_h37

MLCC/+/-10%

MLCC/+80-20%

C38 0.1UF/10V MLCC/+/-10%

12

C41 0.1UF/10V MLCC/+/-10%

12

PCIE_TX6+/GLAN_TX+16
PCIE_TX6-/GLAN_TX-16

PCIE_WAKE#35,38,50

CLK_PCIE_LOM21
CLK_PCIE_LOM#21

+3.3V_RUN

+3.3V_LAN

R25 1KOhm 1%
R15 1KOhm 1%

NO.24

X1 25Mhz

12

+/-30ppm/18PF

12

MLCC/+/-5%

C55

27PF/50V

R126
10KOhm

5%
/*

REVISION

1.2

Core Power Decoupling

12

12

C67

C70

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

LAN_AVDDL

12

12

C18

0.1UF/10V

pt_c0805_h37

MLCC/+/-10%

MLCC/+80-20%

LAN_PCIE_PLLVDD
LAN_PCIE_VDD

12

C36

C22

4.7UF/10V

0.1UF/10V

pt_c0805_h37

MLCC/+/-10%

12
12

LOM_XOUT

LOM_XINLOM_XOUT_R

R16

12

MLCC/+/-5%

Layout note:
Place Close to LOM

R60

12

0Ohm 5%

12

DATE:

1KOhm

Monday, March 19, 2007

SHEET OF

12

12

C54

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

+1.2V_LOM

12

12

C34

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

LAN_PCIETXDP
LAN_PCIETXDN

LOM_PERST#

VAUX_PRSNT
VMAIN_PRSNT
LOM_LOW_PWR

1%

LAN_RDAC

12

NO.28

47 69

4

12

12

C32

C21

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

U4

5

VDDC1

13

VDDC2

20

VDDC3

34

VDDC4

55

VDDC5

60

VDDC6

39

AVDDL

44

DC3

46

DC5

51

DC10

35

DC1

30

PCIE_PLLVDD

27

PCIE_VDD1

33

PCIE_VDD2

24

VSS2

26

PCIE_TXD_P

25

PCIE_TXD_N

31

PCIE_RXD_P

32

PCIE_RXD_N

12

WAKE

10

PERST#

29

PCIE_REFCLK_P

28

PCIE_REFCLK_N

54

VAUX_PRSNT

53

VMAIN_PRSNT

3

LOW_PWR

58

NC2

57

NC1

22

XTALO

21

XTALI

37

RDAC

11

CLKREQ#

59

ENERGY_DET

BCM5906MKMLG

C.S BCM5906MKMLG A2 QFN68

DESCRIPTION:

12

C39

C60

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

+3.3V_LAN +2.5V_LOM

6

15

19

56

61

VDDIO1

VDDIO2

VDDIO3

VDDIO4

VDDIO5

GND

69

LAN BCM5906MKMLG(QFN-68)

VDDP Power Decoupling VDDIO Power Decoupling

BIASVDD

XTALVDD

DC11

LINK_LED#

SERIAL_DI

SERIAL_DO

GPIO_2
GPIO_0

GPIO_1

SCLK

REGCTL25

REGCTL12

VSS1

TDN

RDN
RDP

3

12

12

C50

C72

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

LAN_BIASVDD

36

LAN_XTALVDD

23

C44

38

DC2

45

DC4

52

49

DC8

50

DC9

48

DC7

47

DC6

42
43

TDP

41
40

2
1
66

67

62

8
4

7
65
64

SO

9
63

NC3

18

14

16

0.1UF/10V

NO.3

LINK_LED10#
LINK_LED100#
ACTLED#

EEPROM_WP
LAN_SCLK
LAN_SO

LAN_UART_MODE

LAN_REGCTL12PCIE_LOM_CLKREQ#_R

MLCC/+80-20%

12

C19

LINK_LED10# 48
LINK_LED100# 48
ACTLED# 48

R55

12

0Ohm

5% /*

NO.11

C42

4.7UF/10V

pt_c0805_h37

MLCC/+/-10%

L3 600Ohm

MURATA/BLM18AG601SN1

L8 600Ohm

MURATA/BLM18AG601SN1

12

0.1UF/10V

MLCC/+80-20%

+3.3V_LAN

3
E

Q16

BC1

MMJT9435T1G

24

RELEASE DATE :

12

17

68

VDDP1

VDDP2

SPD100_LED#

TRAFFIC_LED#

UART_MODE

12

12

C69

C43

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

+2.5V_LOM

21

21

12

12

R12

R11

49.9Ohm 1%

49.9Ohm 1%

12

C17

0.1UF/10V

MLCC/+/-10%

Layout note:
Place Close to LOM

R70 1.5Ohm

12

5%pt_r2512_h26

12

12

C71

0.1UF/10V

MLCC/+80-20%

12

12

R14

R13

49.9Ohm 1%

49.9Ohm 1%

12

C14

0.1UF/10V

MLCC/+/-10%

LAN_REGCTL25

C94

4.7UF/10V

MLCC/+/-10%

C61

0.1UF/10V

<OrgName>

2

+3.3V_LAN

LOM_RX- 48
LOM_RX+ 48

LOM_TX- 48
LOM_TX+ 48

+3.3V_LAN

12

C73

0.1UF/10V

pt_c0805_h37

+1.2V_LOM

12

MLCC/+80-20%

12

MLCC/+80-20%

R24

4.7KOhm

12

12

12

12

R21

NO.11

3

C53
10UF/10V

MLCC/+80-20%
pt_c0805_h53

DESIGN ENGINEER :SCHEMATIC FILE NAME :

R22

4.7KOhm

EEPROM_WP
LAN_SCLK
LAN_SO

4.7KOhm

E

Q23
MBT35200MT1G

B

C

24156

+3.3V_LAN

U2

8

VCC

7

WP

6

SCL

5

SDA

AT24C02BN

C214

4.7UF/10V

C124

Ivan_Chou

GND

12

C82

0.1UF/10V

MLCC/+80-20%

1

A0

2

A1

3

A2

4

+3.3V_LAN

12

12

C206

0.1UF/10V

pt_c0805_h37

MLCC/+/-10%

MLCC/+80-20%

+2.5V_LOM

12

12

C125
10UF/10V

0.1UF/10V

MLCC/+80-20%
pt_c0805_h53

MLCC/+80-20%

1

5

4

3

2

1

D D

Reserve Pull-up

No Stuff

R395 150Ohm 1%

ACTLED#

ACTLED#47

LOM_TX+

LOM_TX+47

LOM_TX-

LOM_TX-47

LOM_RX+

LOM_RX+47

LOM_RX-

LOM_RX-47

+2.5V_LOM

MURATA/BLM18AG601SN1

C C

LINK_LED100#47
LINK_LED10#47

+3.3V_LAN

LINK_LED100# LINK_LED100#_R

R393 150Ohm 1%

LINK_LED10#

R391 10KOhm /*5%
R390 10KOhm /*5%

12

R394 150Ohm 1%

12

No Stuff

12
12

No Stuff

ACTLED#_R

12

L29 600Ohm

21

Reserve Pull-up

+3.3V_LAN

12

R392

10KOhm

5% /*

LOM_CT

LINK_LED10#_R

12

12

C499

C500

0.1UF/16V

0.1UF/16V

MLCC/+/-10%

MLCC/+/-10%

Layout note:
C500 should be close to pin12
C499 should be close to pin6

CON10

14

YELLOW+

13

YELLOW-

11

TRD1+

12

TRCT1

10

TRD1-

4

TRD2+

6

TRDCT

5

TRD2-

3

NC_1

1

NC_2

2

NC_3

8

NC_4

7

NC_5

9

NC_6

15

ORANGE-

17

GREEN-

16

COMMON+

LAN_JACK_17P

TYCO/1840427-2

NP_NC1
NP_NC2

SHIELD1

18

20
21

SHIELD2

19

+3.3V_LAN Source Guideline:

1. Use +3.3V_SUS if Wake-on-LAN is
NOT required out of S4, S5

2. Use +3.3V_SRC if Wake-on_LAN is
required out of S4, S5

JP1

12

0Ohm

pt_r0603

JUMP

+3.3V_LAN+3.3V_SUS

Per EE schematic checklist item.87: Only support wake up from S3

B B

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

48 69

4

DESCRIPTION:

Magnetics and RJ-45

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

+15V_ALW

12

3

2

12

D

S

PR44
100KOhm

5%

PR180
100KOhm

5%

3

D

1

G

S

2

PQ13
2N7002

pt_sot23_philips

PQ44
2N7002

pt_sot23_philips

+15V_ALW

12

3

D

1

G

S

2

PR52
100KOhm

5%

PQ12
2N7002

pt_sot23_philips

RUN_ENABLE

12

PC179
4700PF/50V

MLCC/+/-10%
pt_c0603

PD9

RB751V_40

pt_sod323_h35

/*

12

PR56
0Ohm

+5V_ALW2

12

D D

RUN_ON

RUN_ON

,37,51,54,58

C C

PR198
100KOhm

5%

RUN_ON_5V#

3

D

PQ50

1

2N7002

pt_sot23_philips

G

S

2

+5V_ALW2

1.8V_RUN_ON37

1

G

4

+5V_ALW

PQ43

SD

1

8

2

7

3

6
5

4

G

SI4800BDY

+1.8V_SUS +1.8V_RUN

NO.29

PQ17

SD

1

8

2

7

3

6
5

4

G

FDS8884

12

12

PC58

0.047UF/25V

MLCC/+/-10%
/*

5%

+5V_RUN

12

PC180
10UF/16V

MLCC/+/-10%
pt_c1206_h71

For iAMT Support

PC59
10UF/10V

MLCC/+/-20%
pt_c0805_h57

12

12

PR61
20KOhm

5%

12

PR176
20KOhm

5%

3

+5V_ALW2

12

PR116
100KOhm

5%

SUS_ON_3.3V#

3

D

1

G

+5V_ALW2

1

G

2

3

2

S

12

PR183
100KOhm

5%

D

S

PQ30
2N7002

pt_sot23_philips

SUS_ON_5V#

PQ46
2N7002

pt_sot23_philips

3.3V_SUS_ON

3.3V_SUS_ON37

SUS_ON

SUS_ON37,51

2

+15V_ALW

3

1

G

2

+15V_ALW

3

1

G

2

12

PR115
100KOhm

5%

SUS_3.3V_ENABLE

D

PQ29
2N7002

S

pt_sot23_philips

12

PR181
100KOhm

5%

SUS_5V_ENABLE

D

PQ47
2N7002

S

pt_sot23_philips

+3.3V_ALW

12

PC186
4700PF/50V

pt_c0603
MLCC/+/-10%
/*

12

PC182
4700PF/50V

pt_c0603
MLCC/+/-10%
/*

PQ48

8
7
6
5

SI4800BDY

+5V_ALW

PQ42

8
7
6
5

SI4800BDY

1

+3.3V_SUS

SD

1
2

12

3
4

G

12

PR119
100KOhm

5%
/*

+5V_SUS

SD

1
2
3
4

G

12

PR178
100KOhm

5%
/*

PC185
10UF/10V

MLCC/+/-20%
pt_c0805_h57

12

PC181
10UF/10V

MLCC/+/-20%
pt_c0805_h57

12

PR179

20KOhm

5%

12

PR177
20KOhm

5%

SD

1
2
3
4

G

12

PC192
4700PF/50V

MLCC/+/-10%
pt_c0603

12

R88
1KOhm

/*5%

pt_r0603

3

D

Q21

2N7002

S

2

/*

49 69

4

+3.3V_RUN

12

NO.10

PC187
10UF/10V

MLCC/+/-20%
pt_c0805_h57

1

G

12

12

R114
1KOhm

/*5%

pt_r0603

3

D

Q26

2N7002

S

2

/*

DESCRIPTION:

PR182
20KOhm

5%

12

R100
1KOhm

/*5%

pt_r0603

3

D

Q27

1

2N7002

G

S

2

/*

Power Control Switch

3

Reserve discharge path

SUS_ON_5V#

12

R54

1KOhm

/*5%

pt_r0603

3

D

Q18

1

2N7002

G

S

2

/*

12

R130
30Ohm

1%
pt_r0603
/*

3

D

Q29

1

2N7002

G

S

2

/*

RELEASE DATE :

+5V_SUS +3.3V_SUS+1.8V_SUS

3

1

G

2

2

12

R113
1KOhm

/*5%

pt_r0603

D

Q25

2N7002

S

/*

For iAMT Support

12

R111
1KOhm

/*5%

pt_r0603

3

D

Q24

1

2N7002

G

S

2

/*

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Eric Ko

1

+3.3V_ALW

+15V_ALW

5%

PQ31
2N7002

pt_sot23_philips

/*5%

2N7002

/*

Lanai

12

PR118
100KOhm

5%

3

D

PQ32

1

2N7002

G

S

pt_sot23_philips

2

+3.3V_RUN +1.8V_RUN +0.9V_DDR_VTT+5V_RUN +1.5V_RUN +1.25V_RUN

12

R53
10Ohm

/*5%

pt_r0603

3

D

Q17

1

2N7002

G

S

2

/*

REVISION

1.2

+5V_ALW2

12

PR117

B B

3.3V_RUN_ON37

100KOhm

3

D

1

G

S

2

Reserve discharge path

12

R94
1KOhm

pt_r0603

3

D

A A

RUN_ON_5V#

<Variant Name>

PROJECT:

Q20

1

G

S

2

5

NO.29

PQ49

8
7
6
5

PD11

FDS8884

12

RB751V_40

pt_sod323_h35

/*

12

PR200
0Ohm

5%

1

G

Monday, March 19, 2007

DATE:
SHEET OF

5

4

3

2

1

D D

C C

B B

A A

NO.20

+PWR_SRC

567

8

R153

100KOhm

5%
/*

12

3

D

Q39

AUX_EN_WOWL37

CLK_PCIE_MINI221

G_DAT_DDC222
G_CLK_DDC222

VGA_RED22
VGA_BLU22
VGA_GRN22

TV_CVBS22

TV_Y22
TV_C22

+3.3V_RUN

+3.3V_RUN

USB_MCARD2_DET#17
PCIE_MCARD2_DET#16
PCIE_MCARD1_DET#17

WWAN_RADIO_DIS#38

AUD_SPDIF_OUT44

YPRPB_DET#22

PCIE_TX1-16

PCIE_TX1+16

PCIE_RX1-16

PCIE_RX1+16

ICH_USBP3-16

ICH_USBP3+16

ICH_USBP2-16

ICH_USBP2+16

HOST_DEBUG_RX37

HOST_DEBUG_TX37

1

2N7002

G

S

/*

2

R166

100KOhm

5%
/*

12

CON2A

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

717372

73

PCB_SCK_2X37P

SUYIN/127216FA074G500ZR

12

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72
74

74

R164
200KOhm

5%
/*

1

G

R154

100KOhm

5%
/*

12

3

D

Q35
2N7002

S

/*

2

R163

470KOhm

5%
/*

12

CLK_PCIE_MINI1# 21CLK_PCIE_MINI2#21
CLK_PCIE_MINI1 21

MINI2CLK_REQ# 21
VGAVSYNC 22
VGAHSYNC 22

+5V_ALW
+5V_RUN

+1.5V_RUN

USB_MCARD1_DET# 17
USB_BACK_EN# 38
USB_OC2_3# 16
PLTRST_LAN_MINICARD# 16,47
PCIE_WAKE# 35,38,47
COEX2_WLAN_ACTIVE 41
COEX1_BT_ACTIVE 41

ICH_SMBCLK 17,35

ICH_SMBDATA 17,35
WLAN_RADIO_DIS# 38
SB_WWAN_PCIE_RST# 16

LED_WLAN_OUT# 42
SB_WLAN_PCIE_RST# 16
MINI1CLK_REQ# 21

+3.3V_WLAN

ICH_USBP9- 16
ICH_USBP9+ 16

PCIE_TX2- 16
PCIE_TX2+ 16

PCIE_RX2- 16
PCIE_RX2+ 16
8051_RX 37
8051_TX 37

12

C289
4700PF/50V

MLCC/+/-10%
pt_c0603
/*

G

4

U10

SD

123

12

R148
0Ohm

5%
pt_r1206_h26

SI4800BDY

/*

114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150

CON2B

76

NP_NC2
NP_NC40
NP_NC41
NP_NC42
NP_NC43
NP_NC44
NP_NC45
NP_NC46
NP_NC47
NP_NC48
NP_NC49
NP_NC50
NP_NC51
NP_NC52
NP_NC53
NP_NC54
NP_NC55
NP_NC56
NP_NC57
NP_NC58
NP_NC59
NP_NC60
NP_NC61
NP_NC62
NP_NC63
NP_NC64
NP_NC65
NP_NC66
NP_NC67
NP_NC68
NP_NC69
NP_NC70
NP_NC71
NP_NC72
NP_NC73
NP_NC74
NP_NC75

NP_NC76

PCB_SCK_2X37P

SUYIN/127216FA074G500ZR

+3.3V_ALW

+3.3V_WLAN

+3.3V_RUN

NP_NC1
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7
NP_NC8

NP_NC9
NP_NC10
NP_NC11
NP_NC12
NP_NC13
NP_NC14
NP_NC15
NP_NC16
NP_NC17
NP_NC18
NP_NC19
NP_NC20
NP_NC21
NP_NC22
NP_NC23
NP_NC24
NP_NC25
NP_NC26
NP_NC27
NP_NC28
NP_NC29
NP_NC30
NP_NC31
NP_NC32
NP_NC33
NP_NC34
NP_NC35
NP_NC36
NP_NC37
NP_NC38
NP_NC39

75
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

50 69

4

DESCRIPTION:

BtoB CON

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

1

5

Discrete

12

+1.8V_RUN

12

12

12

D7

RB751V_40

C31

0.1UF/10V

MLCC/+80-20%

D6

C29

RB751V_40

0.1UF/10V

MLCC/+80-20%

D5

C27

RB751V_40

0.1UF/10V

MLCC/+80-20%

D4

RB751V_40

C20

0.1UF/10V

MLCC/+80-20%

D D

C C

B B

1.25V_RUN_PWRGD58
GFX_CORE_PWRGD58

1.5V_RUN_PWRGD55

1.05V_RUN_PWRGD55

2.5V_RUN_PWRGD43

12

12

12

12

R35
200KOhm

5%

R34
200KOhm

5%

R33
200KOhm

5%

R23
200KOhm

5%

R43 10KOhm

12

12

C30

2200PF/50V

MLCC/+/-10%

R40 10KOhm

12

12

C28

2200PF/50V

MLCC/+/-10%

R38 10KOhm

12

12

C26

2200PF/50V

MLCC/+/-10%

R27 10KOhm

12

12

C23

2200PF/50V

MLCC/+/-10%

21

21

21

21

+5V_ALW+5V_RUN

B

1

5%

+1.8V_SUS

B

1

5%

+3.3V_ALW+3.3V_RUN

B

1

5%

+3.3V_ALW+3.3V_SUS

B

1

5%

R73 0Ohm 5%

12

R427 0Ohm 5%

12

R504 0Ohm 5%

12

R519 0Ohm 5%

12

R52 0Ohm /*5%

12

2
E

Q10
PMBS3906

C

3

R42 4.7KOhm

12

2
E

Q13
PMBS3906

C

3

R41 4.7KOhm

12

2
E

Q11
PMBS3906

C

3

R39 4.7KOhm

12

2
E

Q6
PMBS3906

C

3

12

R10
200KOhm

5%

5%

5%

5%

D2

RB751V_40

4

3
C

Q15

B

1

PMBS3904

E
2

3
C

Q14

B

1

PMBS3904

E
2

3
C

Q12

B

1

PMBS3904

E
2

+3.3V_ALW

C37 0.1UF/10V

12

MLCC/+80-20%

U3

1

21

2
3

NC7SZ14P5X_NL

5

NC

VCC

A

4

GND

Y

IMVP_PWRGD17,37,53

RESET_OUT#37

Keep Away from high speed buses

+3.3V_SUS

5V_3V_1.8V_1.25V_RUN_PWRGD 38

+3.3V_ALW +3.3V_ALW

R46
20KOhm

U6A

5%

12

16

12

NC7WZ14P6X_NL

C56

0.01UF/25V

MLCC/+/-10%

MLCC/+80-20%

52

IMVP_PWRGD
RESET_OUT#

C40 0.1UF/10V

12

3

+3.3V_ALW

147

VCC

12
13

GND

52

U6B

34

NC7WZ14P6X_NL

RUN_ON28, 37,49,54,58

SUS_ON37 ,49
3V_5V_SUS_PWRGD

U9D

11

74AHC08PW

R150 0Ohm

12

2

+3.3V_SUS

12

R157
100KOhm

5%

ICH_PWRGD#

3

D

1

G

S

2

ICH_PWRGD

+3.3V_ALW

147

VCC

1
2

+3.3V_ALW

9

10

GND

147

VCC

GND

5%

Q34
2N7002

C277 0.1UF/10V

MLCC/+80-20%

U9A

74AHC08PW

U9C

74AHC08PW

12

3

8

ICH_PWRGD# 43

ICH_PWRGD 10,17

+3.3V_ALW

147

VCC

4

5

GND

U9B

74AHC08PW

6

RUNPWROK 37,38,53

SUSPWROK 17,43

1

+5V_ALW+5V_SUS

D3

21

12

RB751V_40

C15

0.1UF/10V

MLCC/+80-20%

A A

<Variant Name>

PROJECT:

Lanai

5

12

R19
200KOhm

5%

R18 10KOhm

12

12

C24

2200PF/50V

MLCC/+/-10%

REVISION

1.2

B

1

5%

DATE:
SHEET OF

2
E

Q7
PMBS3906

C

3

D1

12

RB751V_40

R8
200KOhm

5%

Monday, March 19, 2007

21

12

R28
200KOhm

5%

51 69

4

DESCRIPTION:

Power Sequence Logic

3

RELEASE DATE :

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

C.L. Ho

1

5

D D

4

3

2

1

C C

XDP

U23

SAMTEC/BSH-030-01-L-D-A-TR

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

61 62

NP_NC1 NP_NC2

BtoB_CON_60P

/*

CAD NOTE:
Place the XDP connector on the
primary side of the CRB and place
all components near the connector.

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

T115
T113

T112
T114

XDP_BPM#5
XDP_BPM#4

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3_RXDP_BPM#0

XDP_OBS4

1

XDP_OBS5

1

XDP_OBS6

1

XDP_OBS7

1

H_PWRGD_XDP
XDP_OBS20

XDP_TCK

XDP_BPM#57
XDP_BPM#47

XDP_BPM#37
XDP_BPM#27

XDP_BPM#07

B B

A A

XDP_BPM#17

+1.05V_VCCP

12

C532

0.1UF/10V

MLCC/+/-10%
/*

12

R453 0Ohm 5% /*

12

R454 0Ohm 5% /*

12

R455 0Ohm 5% /*

12

R456 0Ohm 5% /*

R457

54.9Ohm

1%
/*

12

H_PWRGD_XDP7

CLK_PCIE_XDP_3GPLL21
CLK_PCIE_XDP_3GPLL#21

LCTLB_DATA10

LCTLA_CLK10

XDP_TCK7

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

DBR#/HOOK7

GND15

TDO

TRSTN

TMS

GND17

2

XDP_OBS8

4

XDP_OBS9

6
8

XDP_OBS16

10

XDP_OBS17

12
14

XDP_OBS10

16

XDP_OBS11

18
20
22
24
26

XDP_OBS12

28

XDP_OBS13

30
32

XDP_OBS14

34

XDP_OBS15

36
38
40
42
44

RST_SNS1

46
48
50
52

XDP_TRST#

54

XDP_TDI

56

TDI

XDP_TMS

58
60

T118

1

T122

1

T119

1

T125

1

T117

1

T121

1

T120

1

T124

1

T116

1

T123

1

CLK_XDP 21
CLK_XDP# 21

12

R459 100Ohm 5%

/*

XDP_TRST# 7
XDP_TDI 7
XDP_TMS 7

+1.05V_VCCP +3.3V_RUN

C550

0.1UF/10V

12

MLCC/+/-10%
/*

H_RESET# 7,9

Layout note:R0583 should
connect to H_RESET# with
no stub

R458

R460

54.9Ohm

1KOhm

1%

5%

/*

12

12

XDP_DBRESET# 7,17,38
XDP_TDO 7

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

52 69

4

DESCRIPTION:

XDP

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

RUNPWROK37,38,51

D D

IMVP_VR_ON37

IMVP_PWRGD17,37,51

H_PSI#7

PWR_MON43

C C

Close to Phase 1
Inductor

VO_CORE

B B

A A

CGND

VDD_CORE

PC70
2200PF/50V

MLCC/+/-10%

/*

PR70

11.5KOhm

1%

PR76
226KOhm

1%
/*

12

IMVP6_PROCHOT#38

PR67
13KOhm

12

12

12

VO_CORE

PC66

0.015UF/16V

MLCC/+/-10%

1% /*

PR66

1%

6.34kOhm

12

PR63
1KOhm

12

1%

12

PR64
0Ohm

5% /*

PROJECT:

5

PWR_MON

PR157
0Ohm

5%
/*

12

12

PR156

470KOHM

12

/*

PC63

220PF/50V

MLCC/+/-10%

PC69

12

PR62

82.5KOhm

MLCC/+/-10%

1000PF/50V

1%

12

PC64

12

0.01UF/16V

MLCC/+/-10%

VCCSENSE8

VSSSENSE8

Close to Phase 1
Inductor

12

PC77

PC78

0.033UF/16V

0.01UF/25V

MLCC/+/-10%

Lanai

MLCC/+/-10%

PR77
147KOhm

1%

12

pt_r06035%

12

12

PC61

12

MLCC/+/-10%

1500PF/50V

MLCC/+/-10%

12

12

MLCC/+/-10%

PC68

12

1UF/10V

pt_c0603

CGND

PR71
10KOhm

5%

12

PR68

PR69

1%

332Ohm

1.69KOhm

1%

12

12

PC65

680PF/50V

PR72
0Ohm

pt_r0603 5%

PR80
0Ohm

pt_r0603 5%

12

PC72
330PF/50V

MLCC/+/-10%

12

PR85
1KOhm

1%

12

12

PC76

pt_c0603

0.33UF/16V

MLCC/+/-10%

REVISION

1.1

4

12

PMON

12

+3.3V_RUN

12

12

PR78

12

0Ohm

pt_r0603
5%

PSI#

1

PMON

2
3
4
5
6
7
8

PR75
0Ohm 5%

pt_r0603

PR158 10KOHM

CGNDCGND

PR91

4.53KOhm

9

10

5% /*

12

PR65

4.99KOhm 1% /*
PR74

12

0Ohm 5%

PC71

12

MLCC/+/-10%

1000PF/50V

PC73

12

1000PF/50V

MLCC/+/-10%

CGND

12

1%

12

DATE:
SHEET OF

4

Design Current:35.2A
Maximum current:44A

OCP point min.50A

PR81
0Ohm

5% /*

PR84
0Ohm

5%

12

PR83
0Ohm

5% /*

PR79

1.91KOhm

pt_r0603
1%

GND

PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB

12

PC208

1000PF/50V

PC209

1000PF/50V

PR88

PR90

15KOhm 1%

12

PR155

6.8KOHM

5% pt_r0603

PT1

TPC32T

CLK_ENABLE#

41

45

403938373635343332

3V3

GND

GND4

PGOOD

VDIFF

VSEN

RTN

GND1

42

111213141516171819

/*

12

MLCC/+/-10%

CGND

/*

12

MLCC/+/-10%

CGND

1%

10.5KOhm

12

H_DPRSTP#

DPRSLPVR

1

12

PR82

499Ohm 1%

VID6

VR_ON

CLK_EN#

DPRSTP#

DPRSLPVR

DROOP

DFBVOVSUM

VIN

CGND

CGND

PR92

2.43KOhm

1%

12

Monday, March 19, 2007

53 69

7,10,15

VID58VID6

VID3

VID4

PU4

31

ISL6260CCRZ_T

VID5

VID4

VID3
VID2
VID1

VID0
PWM1
PWM2
PWM3
FCCM
ISEN1
ISEN2
ISEN3
GND3
GND2

VSS

VDD

20

VDD_CORE

12

PC81
1UF/10V

pt_c0603
MLCC/+/-10%

VIN

12

12

CGND

12

PC75

0.1UF/16V

MLCC/+/-10%

10,17

8

8

8

30
29
28
27
26
25
24
23
22
21
44
43

GNDGND

PR102
10Ohm

pt_r0603
1%

12

PR98
0Ohm

pt_r0603

5%

12

PR97

+CPU_PWR_SRC

10Ohm

pt_r0603
1%

PC79

0.01UF/50V

MLCC/+/-10%

PR87
15KOhm

1%
/*

12

/*

PC74

0.1UF/10V

MLCC/+/-10%

CGND

DESCRIPTION:

3

12
12

8

8

VID08VID2

VID1

12

12

ISEN1

ISEN2

ISEN3

+5V_ALW

Intersil request to
change.

GND

12

12

PWR_MON 43

12

/*

PR86

5%

30KOhm

12

POWER_VCORE

3

PC146

0.22UF/10V

pt_c0603
MLCC/+/-10%

PR159
0Ohm

pt_r0603
5%

1
2

ISL6208CRZ

PC151

0.22UF/10V

pt_c0603
MLCC/+/-10%

PR160
0Ohm

pt_r0603
5%

1
2

ISL6208CRZ

PC155

0.22UF/10V

pt_c0603
MLCC/+/-10%

PR161
0Ohm

pt_r0603
5%

1
2

ISL6208CRZ

GND

GND

GND

BOOT
PWM

BOOT
PWM

BOOT
PWM

GND2

GND

GND2

GND

GND2

GND

789

PHASE

UGATE

GND1

LGATE

3

4

789

PHASE

UGATE

GND1

LGATE

3

4

789

PHASE

UGATE

GND1

LGATE

3

4

PC89

CORE_HG1

PU6

6

FCCM

5

VCC

PC145
1UF/10V

pt_c0603

MLCC/+/-10%

CORE_LG1

CORE_HG2

PU7

6

FCCM

5

VCC

PC147
1UF/10V

pt_c0603

MLCC/+/-10%

CORE_LG2

CORE_HG3

PU8

6

FCCM

5

VCC

PC152
1UF/10V

pt_c0603

MLCC/+/-10%

CORE_LG3

12

PR108

2.2Ohm

pt_r1206_h26
5%

12

1500PF/50V

pt_c0603

MLCC/+/-5%

+5V_ALW

12

GND

PC94

+5V_ALW

12

GND

PC99

+5V_ALW

12

GND

12

PR109

2.2Ohm

pt_r1206_h26
5%

12

12

PR111

2.2Ohm

pt_r1206_h26
5%

12

12

567

8

G

SD

PQ19

123

4

SI4386DY_T1_E3

4
3
2
1

GND

567

G

pt_c0603

MLCC/+/-5%

4

1500PF/50V

4
3
2
1

PQ22
FDS7088SN3

GND

567

G

pt_c0603

4

1500PF/50V

MLCC/+/-5%

4
3
2
1

GND

RELEASE DATE :

2

12

PC87

2200PF/50V

MLCC/+/-10%

9

D

G

S

PQ20
FDS7088SN3

+CPU_PWR_SRC

12

8

SD

PQ21

123

SI4386DY_T1_E3

9

D

G

S

12

8

SD

PQ23

123

SI4386DY_T1_E3

9

D

G

S

PQ24
FDS7088SN3

2

PC88

pt_c0603

0.1UF/50V

MLCC/+/-10%

5
6
7
8

12

PC91

2200PF/50V

MLCC/+/-10%

5
6
7
8

+CPU_PWR_SRC

12

PC96

2200PF/50V

MLCC/+/-10%

5
6
7
8

+CPU_PWR_SRC

12

12

PC143

10UF/25V

pt_c1206_h71 MLCC/+/-10%

+VCC_CORE_L1

12

PC86
1500PF/50V

pt_c0603
MLCC/+/-5%

12

PR107

2.2Ohm

pt_r1206_h26
5%

GND

+CPU_PWR_SRC

12

PC90

pt_c0603

0.1UF/50V

MLCC/+/-10%

+VCC_CORE_L2

12

PC150
1500PF/50V

pt_c0603
MLCC/+/-5%

12

PR110

2.2Ohm

pt_r1206_h26
5%

GND

12

PC95

0.1UF/50V

pt_c0603

MLCC/+/-10%

+VCC_CORE_L3

12

PC156
1500PF/50V

pt_c0603
MLCC/+/-5%

12

PR112

2.2Ohm

pt_r1206_h26
5%

GND

<OrgName>

1

12

PC84

PC85

10UF/25V

10UF/25V

pt_c1206_h71 MLCC/+/-10%

12

12

PC92

PC149

10UF/25V

10UF/25V

pt_c1206_h71 MLCC/+/-10%

12

PR93

7.68KOhm

pt_r0805_h24
1%

VSUM

12

PC98

PC154

10UF/25V

10UF/25V

pt_c1206_h71 MLCC/+/-10%

12

12

12

+

PC144

10UF/25V

pt_c1206_h71 MLCC/+/-10%

pt_c1206_h71 MLCC/+/-10%

GND

3

PL11

0.45UH

Irat=25A

pt_inductor_4p_453x394_spe

PR96
10KOhm

1%

12

PR89

7.68KOhm

pt_r0805_h24
1%

VSUM

12

12

PC148

10UF/25V

pt_c1206_h71 MLCC/+/-10%

pt_c1206_h71 MLCC/+/-10%

GND

3

PL12

0.45UH

Irat=25A

pt_inductor_4p_453x394_spe

PR99
10KOhm

1%

12

ISEN2

12

12

PC153

10UF/25V

pt_c1206_h71 MLCC/+/-10%

pt_c1206_h71 MLCC/+/-10%

GND

3

PL13

0.45UH

Irat=25A

pt_inductor_4p_453x394_spe

PR104
10KOhm

1%

12

PR103

7.68KOhm

pt_r0805_h24
1%

VSUMVSUM

PCE1

100uF/25V

EL/Lf_T=3000hrs_105c/+/-20%

4

12

PC80

0.22UF/10V

pt_c0603

MLCC/+/-10%

ISEN1

PC93

10UF/25V

pt_c1206_h71 MLCC/+/-10%

21

4

12

PC82

0.22UF/10V

pt_c0603

MLCC/+/-10%

PC97

10UF/25V

pt_c1206_h71 MLCC/+/-10%

21

4

PC83

0.22UF/10V

pt_c0603

MLCC/+/-10%

ISEN3

21

4MM_OPEN_5MIL

4MM_OPEN_5MIL

+VCC_CORE

+VCC_CORE

12

12

12

+

+

PCE3

100uF/25V

EL/Lf_T=3000hrs_105c/+/-20%

+VCC_CORE

12

PR95
10Ohm

pt_r0603
1%

12

PR94
0Ohm

pt_r0603

+PWR_SRC
5%

VO_CORE

PJP15

12

12

/*

PJP14

12

12

/*

12

PR101
10Ohm

pt_r0603
1%

12

PR100
0Ohm

pt_r0603
5%

VO_CORE

12

PR106
10Ohm

pt_r0603
1%

12

PR105
0Ohm

pt_r0603
5%

VO_CORE

PCE2

100uF/25V

EL/Lf_T=3000hrs_105c/+/-20%

DESIGN ENGINEER :SCHEMATIC FILE NAME :

JEFF

1

5

5 Volt +/-5%

Design Current:6.12A
Maximum current:8.74A

OCP point min. :8.82A

D D

+PWR_SRC

PJP7

12

12

4MM_OPEN_5MIL

/*

12

PC204

10UF/25V

pt_c1206_h71

MLCC/+/-10%

+5V_ALWP

C C

PC184

pt_c0603

0.1UF/25V

MLCC/+/-10%

+15V_ALWP +15V_ALW

B B

+3.3V_ALWP

A A

12

+

12

PC183

330UF/6.3V

pt_c7343d_h118

TAN/Lf_T=2000hrs_105C/+/-20%

GND

PJP20

12

12

2MM_OPEN_5mil

/*

PJP18

12

12

4MM_OPEN_5MIL

/*

PJP19

12

12

4MM_OPEN_5MIL

/*

GND

PROJECT:

+VCC_TPS51120

5%

PR185

0Ohm

pt_r0603

12

/*

+5V_ALW+5V_ALWP

+3.3V_ALW

THERM_STP#

PQ25
2N7002

/*

5

12

1%

PR186

40.2KOhm

12

/*

1%

PR184

10KOhm

pt_r0603

PC210

0.1UF/25V

GND

+3.3V_RTC_LDO +3.3V_ALW

12

PR114

4.7KOhm

5%

1

/*

G

3

2

D

S

Lanai

PLACE THESE CAPS CLOSE TO FETS

12

12

PC109

PC197

10UF/25V

pt_c1206_h71

MLCC/+/-10%

PL16

3.3UH

Irat=8.8A

pt_inductor_2p_453x394

12

MLCC/+/-10%

GND

PC101

12

0.01UF/25V

pt_c0603

MLCC/+/-10%

/*

ALWON37

THERM_STP#43

23

pt_c0603

REVISION

1.1

+DC1_PWR_SRC

0.1UF/50V

pt_c0603

21

PQ26

FDN340P_NL

S

2

PR113

2.2MOhm

5%
/*

4

12

PC195

MLCC/+/-10%

2200PF/50V

MLCC/+/-10%

8

SD

GND

+5V_ALWP_L

123

8

SD

123

GND

PR197
1KOhm

1%

12

PR202
0Ohm

5%

For debug

/*

D

3

G

1

1

12

3

PD10
BAT54

/*

2

1

DATE:
SHEET OF

4

3

/*

PD12

RB717F

pt_sot323

1

2

+5V_BS

12

12

0Ohm

PC194

567

G

4

567

G

4

12

12

GND

PR203

pt_c0603

0.1UF/25V

MLCC/+/-10%

PQ52

SI4800BDY

PQ54

FDS6690AS

+VCC_TPS51120

12

5%

PR194

200KOhm

GND

5%

0Ohm

PR196

12

GND

/*

PC102

4.7UF/10V

pt_c1206_h71

MLCC/+/-10%

Monday, March 19, 2007

54 69

+5V_ALW2

12

12

PC110

PC203

pt_c1206_h71

1UF/10V

pt_c0603

MLCC/+/-10%

10UF/16V

+3.3V_BS

PC200

pt_c0603

0.1UF/50V

5%

pt_r0603

+5V_DL
+5V_DH

+5V_VBST
3V_5V_POK

TONSEL

/*5%

PR192

0Ohm

+VCC_TPS51120

0Ohm

PR199

/* 5%

0Ohm

PR195

/* 5%

MLCC/+/-10%

GND

+3.3V_RTC_LDO

12

MLCC/+/-10%

GND GND

GND

+5V_VFB

12

12

TONSEL

12

CS1

24

25
26
27
28
29
30
31
32
33

PU10A

VIN

CS1

V5FILT

VREG5

PGND1
DRVL1
LL1
DRVH1

VBST1

TPS51120RHBR

EN1
PGOOD1
TONSEL
SKIPSEL
GND2

VO1

COMP1

VFB1

VREF2

GND1

1234567

12

5%

0Ohm

0Ohm

PR191

PR190

/* 5%

12

RUN_ON28,37,49,51,58

DESCRIPTION:

POWER_SYSTEM 5V_ALW&3.3V_ALW

3

PR211
47Ohm

pt_r0603

5%

12

PC111

10UF/16V

CS2

17181920212223

CS2

VREG3

PGND2
DRVL2

LL2
DRVH2
VBST2

EN2

PGOOD2

EN3
EN5

VFB2

COMP2

VO2

8

PC191

1000PF/50V

pt_c0603

MLCC/+/-10%

12

+VCC_TPS51120

3

+VCC_TPS51120

12

PC201

12

1UF/10V

pt_c1206_h71

MLCC/+/-10%

PR204

+3.3V_DL

16
15

+3.3V_DH

14

+3.3V_VBST

13
12

3V_5V_POK

11
10
9

GND

PR120

+3.3V_VFB

PR205
0Ohm

PR209
0Ohm

/*5%

PQ55
BSS84LT1G

/*

23

S

2

PR193
200KOhm

5%
/*

12

1

G

GND

PU10B TPS51120RHBR

GND3

GND4

343536373839404142

GND

12

pt_c0603

MLCC/+/-10%

PC196

12

0Ohm

12

1%

12.4KOhm

/*5%

12

12

G

1

1

3

D

S

2

0.1UF/25V

5%

pt_r0603

PQ51

PQ45

12

PC108

pt_c0603

MLCC/+/-10%

1000PF/50V

CS1 CS2

D

3

PR201

PQ53

100KOhm

2N7002

5%

/*

3V_5V_POK

GND5

GND6

GND7

GND8

GND9

GND10

GND11

PLACE THESE CAPS CLOSE TO FETS

12

PC188

8

SD

123

+3.3V_ALWP_L

8

SD

123

GND

12

1%

PC202

9.76KOhm

2200PF/50V

12

1000PF/50V

pt_c0603

MLCC/+/-10%

567

G

SI4392DY-T1-E3

4

567

G

FDS6676AS

4

PR206

+3.3V_ALWP

12

ALW_PWRGD_3V_5V 37

RELEASE DATE :

2

3.3 Volt +/-5%

Design Current:6.95A
Maximum current:9.93A

OCP point min. :13.14A

+DC1_PWR_SRC

12

PC190

PR189

23.2KOhm

pt_r0603
1%

PC211

12

10UF/25V

MLCC/+/-10%

pt_c1206_h71

GND

21

/*

12

pt_c0603

0.1UF/25V

MLCC/+/-10%

GND

PR215

0Ohm

5%

12

PC189

pt_c0603

0.1UF/50V

MLCC/+/-10%

MLCC/+/-10%

PL3

3.3UH

Irat=8.8A

pt_inductor_2p_453x394

+VCC_TPS51120

PR187
0Ohm

pt_r0603

pt_c0603

5%

12

/*

MLCC/+/-10%

12

12

1%

PR188

10KOhm

pt_r0603

GND

EC_PWM_237

2

PC106

10UF/25V

pt_c1206_h71

MLCC/+/-10%

PD20
BAT54S

pt_sot23_philips

+3.3V_ALWP

12

+

12

PC193

330UF/6.3V

pt_c7343d_h118

TAN/Lf_T=2000hrs_105C/+/-20%

GND

+5V_ALWP

5%

PR214

47KOhm

12

3

D

PQ56

1

12

2N7002

G

S

2

GND

<OrgName>

2

2

3

3

12

PC107

pt_c0603

0.1UF/25V

MLCC/+/-10%

PU11

A

1

B

2
34

GND

SN74LVC1G00DCKR

GND

+5V_DL

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

12

PC198
1UF/25V

pt_c0603
MLCC/+/-10%

+10V_ALWP

1

1

PC206
1UF/25V

pt_c0603
MLCC/+/-10%

+5V_PMP

+5V_ALW2

PC207

GND

VCC

Y

PR207

0Ohm

pt_r0603
5% /*

1

PR208
0Ohm

5%

12
2

2

3

PD21
BAT54

2

1

GND

12

PR213
0Ohm

5%
/*

12

1UF/25V

pt_c0603

MLCC/+/-10%

5

12

JEFF

+15V_ALWP

12

PC205
1UF/25V

pt_c0603
MLCC/+/-10%

GND

+5V_ALWP

1
pt_sot23_philips

3

3

12

PC199
1UF/25V

pt_c0603
MLCC/+/-10%

+5V_ALWP

12

N/A

PR210

120Ohm

5%

PD19
BAT54S

1

PR212

0Ohm

5%

12

5

D D

1.5 Volt +/-5%

Design Current:3.02A
Maximum current:4.31A

OCP point min.: 9.37A

+PWR_SRC

+1.5V_RUN

PJP17

12

12

4MM_OPEN_5MIL

C C

B B

/*

PJP5

12

4MM_OPEN_5MIL

/*

+1.5V_RUN_P

PC169

0.1UF/10V

12

MLCC/+/-10%

+DC2_PWR_SRC

12

12

PC177

PC103

10UF/25V

10UF/25V

pt_c1206_h71

MLCC/+/-10%

pt_c1206_h71

PL15

1UH

Irat=14.3A

pt_inductor_2p_453x394

+1.5V_RUN_P

12

12

+

12

PC171

PC178

330UF/2.5V

10UF/6.3V

pt_c1206_h35

1.5V_RUN_PWRGD51

pt_c7343d_h79

MLCC/+/-10%

TAN/Lf_T=2000hrs_105C/+/-20%

GND

+1.5V_PG1

MLCC/+/-10%

12

12

PC104

pt_c0603

0.1UF/50V

MLCC/+/-10%

+1.5V_RUN_P_L

21

PC105

2200PF/50V

PC173

MLCC/+/-10%

0.1UF/10V

8

SD

123

8

SD

123

GND

/*

MLCC/+/-10%

4

567

PQ27

G

FDS8880

4

567

PQ28

G

FDS6670AS

4

+1.5V_LG

+1.05V_VCCP_P

PR172

12

12

PR173

12

11.8KOhm

29.4KOhm

pt_r0603

pt_r0603

3

PR175
200KOhm

1%

28
27
26
25
24
23
22
21
20
19
18
17
16

+1.05V_BS+1.5V_BS

+1.5V_PG1

RUN_1.5VO
+1.05V_HG

12

PR167

5.6KOhm

1%

PC168

1UF/10V

12

PC176

GND

+1.05V_LG

12

pt_c0805_h33

MLCC/+/-10%

+1.5V_V5FILT

+5V_SUS

GND

PR162

10Ohm

12

12

PC161

12

PR168
0Ohm

12

1UF/10V

5%

pt_r0603

1UF/10V

pt_c0603

PC160

0.1UF/25V

pt_c0805_h53
MLCC/+/-10%

12

5%

pt_c0603

MLCC/+/-10%

+1.5V_V5FILT2_L

12

12

MLCC/+/-10%

GND

PR165

PR163

+1.05V_VBST

15KOhm

pt_r0603

15KOhm

pt_r0603

4
3
2
1

FDS7088SN3

+1.5V_RUN_P

12

PC163

1%

1%

100PF/50V

567

G

4

9

G

PQ41

MLCC/+/-5%

8

SD

123

PQ40
FDS8880

+1.05V_VCCP_P_L

D

5
6
7
8

S

12

PC162

0.1UF/10V

PR164
210KOhm

1%

PC170

1UF/10V

+5V_SUS

PR174

10Ohm

12

+1.5V_HG

RUN_1.05VO

12

5%

pt_r0603

+1.05V_V5FILT

12

PC174

1UF/10V

12

+5V_SUS

12

10
11
12

+1.05V_PG2

13
14 15

pt_c0603

MLCC/+/-10%

2

3

12

PR170

9.53KOhm

1%

PU9

1

PGND1

2

DRVL1

PGOOD1

3

V5DRV1

4

TRIP1

5

LL1

6

DRVH1

7

VBST1

EN_PSV1

8

EN_PSV2

9

TON2
VOUT2
V5FILT2
VFB2
PGOOD2
GND2 PGND2

SN0508073PWR

1

GND1

VFB1

V5FILT1

VOUT1

TON1

VBST2

DRVH2

TRIP2

V5DRV2

DRVL2

PD18

BAT54A

pt_sot23_philips

/*

GND

LL2

PC175

0.1UF/25V

pt_c0805_h53
MLCC/+/-10%

12

PR171
0Ohm

5%

+1.5V_VBST

pt_c0805_h33
MLCC/+/-10%

GND

+1.05V_V5FILT2_L

12

PC172

39PF/50V

MLCC/+/-5%

1%

1%

GND

+DC2_PWR_SRC

12

/*

MLCC/+/-10%

PC167

GND

2200PF/50V

2

12

PC166

MLCC/+/-10%

12

pt_c0603

PC164

pt_c1206_h71

10UF/25V

0.1UF/50V

MLCC/+/-10%

PL14

1UH

Irat=14.3A

pt_inductor_2p_453x394

+1.05V_VCCP_P

1

1.05 Volt +/-5%

Design Current:12.42A
Maximum current:17.75A

OCP point min.: 11.91A

12

PC165

10UF/25V

pt_c1206_h71

MLCC/+/-10%

MLCC/+/-10%

21

12

+

PC100

330UF/2.5V

pt_c7343d_h79

(OCP point typ.: 15.71A)

+1.05V_VCCP_P

12

+

12

12

PC159

PC157

330UF/2.5V

10UF/6.3V

pt_c1206_h35

MLCC/+/-10%

pt_c7343d_h79

TAN/Lf_T=2000hrs_105C/+/-20%

TAN/Lf_T=2000hrs_105C/+/-20%

GND

PC158

0.1UF/10V

MLCC/+/-10%

PJP6

12

12

4MM_OPEN_5MIL

/*

PJP16

12

12

4MM_OPEN_5MIL

/*

+1.05V_VCCP

1.05V_RUN_PWRGD51

1.5V_RUN_ON37

1.05V_RUN_ON38

A A

PROJECT:

5

Lanai

+1.05V_PG2

PR169

REVISION

1.1

PR166
0Ohm

5%

0Ohm

5%

12

12

For debug

RUN_1.5VO

RUN_1.05VO

Monday, March 19, 2007

DATE:
SHEET OF

55 69

DESCRIPTION:

4

POWER_I/O_1.5VS & 1.05VS

3

RELEASE DATE :

<OrgName>

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

JEFF

1

5

4

3

2

1

0.9 Volt +/-5%

Design Current:1.05A
Maximum current:1.5A

PR154

5%

0Ohm

pt_r0603

+0.9V_DDR_VTTP

12

PC53

10UF/6.3V

pt_c0805_h53

MLCC/+/-10%

12

PC57

pt_c0603

0.033UF/16V

MLCC/+/-10%

GND

+1.8V_SUSP

PC55

10UF/6.3V

12

+1.8V_SUSP

pt_c0805_h53

PR60
0Ohm

pt_r0603
5%

D D

C C

+5V_SUS

/*

5%

PR153

1MOhm

12

12

/*

PC54

pt_c0603

MLCC/+/-10%

GND

1000PF/50V

V_DDR_MCH_REF

B B

A A

12

MLCC/+/-10%

GND

PR59

pt_r0603

+5V_SUS

+5V_SUS

PC56

10UF/6.3V

pt_c0805_h53

MLCC/+/-10%

GND

12

0Ohm

5%

12

MBR0530T1G

pt_sod123_rd1

21

12

12

PC49
1UF/6.3V

MLCC/+/-10%
/*

GND

PR151
0Ohm

pt_r0603
5%

PR58
0Ohm

pt_r0603
5%

PD17

+1.8V_SUSP

PC51

GND

PU3

1

VTTGND

2

VTTSNS

3

GND1

4

MODE

5

VTTREF

6

COMP

TPS51116RGER

12

12

+DDR_PWR_SRC

12

12

PR57

pt_r0603

1UF/10V

pt_c0603

MLCC/+/-10%

PC48

0.1UF/10V

0Ohm

5%

12

VTT

GND2

NC1

7891011

12

/*

MLCC/+/-10%

GND

+1.8V_VBST

VLDOIN

VDDQSNS

VBST

DRVH

VDDQSETS3S5

PC46

pt_c0603

0.1UF/25V

+1.8V_DH
+1.8V_LL

SI4336DY-T1-E3

+1.8V_DL

19202122232425

30

GND6

LL

GND5

DRVL

GND7

PGND

CS_GND

CS

V5IN

V5FILT

PGOOD

GND4
GND3

NC2

12

MLCC/+/-10%

PQ16

GND

29
28
18
17
16
15
14
13
27
26

+1.8V_SUSP

PR152

1%

27.4KOhm

PR55

pt_r0603

17.4KOhm

567

G

4

567

G

4

+1.8V_V5FILT

GND

12

/*

12

1% /*

8

PQ15

SI4392DY-T1-E3

SD

123

8

SD

PR149

123

PR50

12

PC52

2200PF/50V

MLCC/+/-10%

12

/*

1%

pt_r0603

7.87KOhm

12

12

1%

pt_r0603

6.19KOhm

12

PC45

1UF/10V

pt_c0603

MLCC/+/-10%

GND

For debug

PR51

0Ohm 5%

PR54

0Ohm 5%

12

12

PC50

PC47

pt_c0603

0.1UF/50V

MLCC/+/-10%

GND

PL10

1UH

Irat=14.3A

pt_inductor_2p_453x394

PC43

pt_c0603

1000PF/50V

MLCC/+/-10%

12

PR150

4.99Ohm

pt_r0603
1%

12

12

12

PC139

10UF/25V

pt_c1206_h71

MLCC/+/-10%

21

PC140

330UF/2.5V

12

PC44

1UF/10V

GND

0.9V_DDR_VTT_ON

10UF/25V

pt_c1206_h71

MLCC/+/-10%

pt_c7343d_h79

TAN/Lf_T=2000hrs_105C/+/-20%

pt_c0603

MLCC/+/-10%

For debug

+1.8V_SUSP

12

+

+5V_SUS

PC141

PJP11

12

12

4MM_OPEN_5MIL

/*

12

+

330UF/2.5V

pt_c7343d_h79

TAN/Lf_T=2000hrs_105C/+/-20%

GND

+3.3V_SUS

PR49

100KOhm

12

+1.8V_SUSP +1.8V_SUS

+PWR_SRC

1.8Volt +/-5%

Design Current:10.3A
Maximum current:14.71A
OCP point min.: 12.56A

12

PC142

0.1UF/25V

pt_c0603

MLCC/+/-10%

1%

1.8V_SUS_PWRGD 37

DDR_ON 37

0.9V_DDR_VTT_ON 37

PJP12

12

12

4MM_OPEN_5MIL

/*

PJP13

12

12

4MM_OPEN_5MIL

/*

+0.9V_DDR_VTT+0.9V_DDR_VTTP

PJP3

12

12

2MM_OPEN_5mil

/*

PROJECT:

5

Lanai

REVISION

1.1

Monday, March 19, 2007

DATE:
SHEET OF

56 69

4

DESCRIPTION:

POWER_I/O_DDR & VTT

3

RELEASE DATE :

2

<OrgName>

DESIGN ENGINEER :SCHEMATIC FILE NAME :

JEFF

1

TOTAL POWER=90W

-->4.62A

D D

C C

0.01UF/25V

MLCC/+/-10%

B B

A A

TABLE2

MAXIM & INTERSIL BOM DIFFERENCES

REF DES

PR18

8.45K, 0402, 1%

0.01uF

PC22
PC32

0.1uF, 0402, 10V

PC26

1.0uF, 0603, 10V
365K, 0402, 1%

PR124

0, 0402, 5%

PR31

0, 0402, 5%

PR27
PC25

No Stuff

PC15

No Stuff

PC28

0.01uF

PC31

0.1uF, 0402, 10V

PC8

220pF, 0402, 50V
RB751V-40

PD3
PC7 3.3nF

1, 0603, 1%

PR16

100, 0402, 5%

PR33

4.7K, 0402, 5%

PR34
PC29

0.01uF

PC27

0.01uF

PD16

1SS355

PR134

1K, 0603, 5%

MAXIM

5

+DC_IN_SS

PR124

365KOhm

12

12

PC24

PROJECT:

GND_CHA

PR29

49.9KOhm

12

INTERSIL

16.0K, 0402, 1%
No Stuff
No Stuff
No Stuff
215K, 0402, 1%
10, 0402, 5%
10, 0402, 5%

0.22uF

0.22uF
No Stuff
No Stuff
No Stuff
No Stuff
No Stuff
0, 0603, 5%
0, 0402, 5%

4.7K, 0402, 5%

0.01uF

0.01uF
No stuff

No stuff

5

1%

1%

PC26
1UF/10V

pt_c0603

MLCC/+/-10%

Lanai

ADAPT_TRIP_SEL38

12

0.01UF/25V

MLCC/+/-10%

GND_CHA

PC27

8
7
6
5

SI4835BDY-T1-E3

31

3

D

S

1

GND

12

0.01UF/25V

MLCC/+/-10%

BAT_REF

REVISION

1.1

PQ35

SD

1
2
3
4

G

PR129
10KOhm

5%

12

2

ACAV_IN

2

G

PQ38

RHU002N06

12

PC28

PR32

51.1KOhm

1%

12

PR24

33.2KOhm

1%

+DC_IN_SS_X

12

PR34
10KOhm

5%

12

PC29

0.01UF/25V

MLCC/+/-10%

12

GND_CHA

DATE:
SHEET OF

4

12

PR127
100KOhm

5%

CHG_CSSP_L

MLCC/+/-10%

GND_CHA

BAT_REF

MAX8731AETI

12

PC31

0.1UF/10V

MLCC/+/-10%

PC32

0.1UF/10V

MLCC/+/-10%

PBAT_SMBDAT37,59

PBAT_SMBCLK37,59

Maxim request
to add

PR25

INP

12

0Ohm

5%

PC22

0.01UF/16V

MLCC/+/-10%

12

PR17

17.8KOhm

V=0.975V,I=3.25A

1%

12

PR12
348Ohm

1%

Monday, March 19, 2007

57 69

4

PR126
10mOhm

pt_r2512_4p_h33

1%

12

34

12

PR27
0Ohm

/*

PU1

GND1
ACIN
REF
CCS
CCI
CCV
DAC

INP

PR18

8.45KOhm

1%

12

29

GND3

IINP

891011121314

12

CSSP

SDA

12

MLCC/+/-5%

5%

CHG_CSSN_L

CHG_BST_L

BST

VCC

CSSN

SCL

VDD

GND2

+5V_ALW

12

PC33

0.1UF/10V

MLCC/+/-10%

FOR GPRS IMMUNITY
PLACE AS CLOSE TO THE
IC AS POSSIBLE

PR26
1MOhm

1%

12

PC16

100PF/50V

PC15

0.22UF/10V

pt_c0603

MLCC/+/-10%

12

PC6
1UF/10V

pt_c0603

12

1
2
3
4
5
6
7

12

12

GND_CHA

PC21

0.01UF/16V

MLCC/+/-10%

DESCRIPTION:

CHG_LX_L

22232425262728

LX

DHI

PGND

FBSB
FBSA

ACOK

BATSEL

MLCC/+/-5%

GND_CHA

+PWR_SRC

12

DCIN

LDO
DLO

CSIP
CSIN

PC37

100PF/50V

PJP1

12

12

4MM_OPEN_5MIL

/*

PR15
0Ohm

pt_r0603
5%

12

12

PC1

0.1UF/25V

PR16

pt_c0603

1Ohm

MLCC/+/-10%

pt_r0603
1%

12

CHG_VCC_L

PC9

PC8

1UF/25V

220PF/50V

pt_c0805_h57

MLCC/+/-10%

12

MLCC/+/-10%

GND

21
20
19
18
17
16
15

12

PR33
100Ohm

5%

12

PR37
0Ohm

5%

12

GND_CHA GND_CH A

PU2

1

VOUT1

2

VIN1-

3

VIN1+

45

GND VIN2+

LM393DR

12

PC17

100PF/50V

MLCC/+/-5%

FOR GPRS IMMUNITY PLACE
AS CLOSE TO THE IC AS
POSSIBLE

POWER_CHARGER

LDO

+VCHGR

12

PC36

0.01UF/16V

MLCC/+/-10%

VCC

VOUT2

VIN2-

PD3

RB751V_40

PR14
33Ohm

pt_r0603

5%

12

LDO

12

PR36
10KOhm

1%

ACAV_IN 37,43

12

PR35

15.8KOhm

1%

GND

+5V_ALW

8
7
6

3

2200PF/50V

MLCC/+/-10%

12

PC18
1UF/10V

pt_c0603

MLCC/+/-10%

12

CHG_CSIN_L

+3.3V_ALW

12

PR28

100KOhm

1%

1

G

12

/*

PC23

MLCC/+/-5%

100PF/50V

GND_CHA

3

12

PC122

MLCC/+/-10%

/*

GND

CHG_DHI_L

GND

12

PC7

MLCC/+/-10%

3300PF/50V

CHG_DLO_L

12

PR11
100KOhm

1%

OC TRIP

3

D

PQ3
2N7002

S

2

RELEASE DATE :

CHRG_IN

PC119

0.1UF/50V

pt_c0603
/*

CHG_CSIP_L

12

G

567

4

PR9

1KOhm

12

8

PQ7

SD

123

ADAPT_OC 38

/*

1%

567

8

G

SD

SI4800BDY

123

4

567

8

D

G

4

S

1

2

3

GND

GND_CHA

<OrgName>

12

PR131
470KOhm

5%

GND

12

PQ8

SI4800BDY

pt_inductor_2p_398x394

PQ4

SI4810BDY-T1-E3

PR38
0Ohm

pt_r0603
5%

2

PQ5

SD

1
2
356
4

G

SI4835BDY-T1-E3

12

PC11

MLCC/+/-10%

2200PF/50V

PL7

5.2UH

Irat=5.5A

12

GND

2

1

TABLE3

PIN NAME DIFFERENCES

PIN

+VCHGR

+PBATT

8
7

+DC_IN_SS

12

12

PC2

PC10

0.1UF/50V

pt_c0603

MLCC/+/-10%

+VCHGR_LX+VCHGR_L

21

ADAPTOR (W)

Note 1: PR24 is populated if ADAPT_TRIP_SET is
used to program for the next lower adaptor
ADAPT_TRIP_SET is floating for the higher
adaptor, grounded for the lower adaptor
Note 2: 24.9K at PR24 allows the 65W adaptor setting
to switch down to 45W. (now is 33.2K for 90W)
Note 3: PR126 must be 5m ohm instead of 10m ohm
for the 230W adaptor

PR31
0Ohm

10UF/25V

GND

5%

65
90
130
150
200
230

pt_c1206_h71

MLCC/+/-10%

12

PC120

10UF/25V

pt_c1206_h71

MLCC/+/-10%

Charge Current:4.68A
Discharge current:6.6A

PR133
10mOhm

pt_r2512_4p_h33

1%

12

34

PC25

0.22UF/10V

pt_c0603
MLCC/+/-10%

/*

12

3.17

4.43

6.43

7.43

9.75

11.28

TABLE1

PR32

57.6K

51.1K

32.4K

30.9K

19.1K

32.4K

TRIP CURRENT (A)

12

1
3
4
5
6
7
8
11
14
15
16
17
18
2023DLO
21

24
25

PC127

pt_c0603

0.1UF/25V

MLCC/+/-10%

PR17

13.0K

17.8K

20.5K

24.9K
28K

6.49K

12

MAXIM

GND
REF
CCS
CCI
CCV
DAC
IINP
VDD
BATSEL
FBSA
FBSB
CSIN
CSIP CSOP

LDO
LX
DHI
BST
"NC"

PC20

10UF/25V

PR12
105
348
100
432
301
115

means no-connect

+VCHGR

12

PC126

10UF/25V

pt_c1206_h71

MLCC/+/-10%

GND

ACAV_IN

PR24
N/A

33.2K

27.4K

88.7K

36.5K
N/A

pt_c1206_h71

MLCC/+/-10%

RHU002N06

INTERSIL

NC
VREF
ICOMP

ICM
VDDSMB
NC
VFB
NC
CSON

LGATE
VDDP
PHASE
UGATE
BOOT

DESIGN ENGINEER :SCHEMATIC FILE NAME :

JEFF

1

NC
VCOMP
NC

12

PQ57

2

PC19

10UF/25V

/*

2

G

+5V_ALW

12

PD16
1SS355

PR134
1KOhm

pt_r0603

12

PR216

1.8KOhm

pt_c1206_h71

5%

MLCC/+/-10%

pt_r1206_h26

12

31

3

D

S

1

GND

/*

5%
/*

/*

5

1.25Volt +/-5%

Design Current:2.26A
Maximum current:3.23A

OCP point min. : 9.59A

D D

+PWR_SRC

+1.25V_SRC_MP

C C

+1.25V_RUN

B B

A A

12

PC118

PC123

0.1UF/10V

MLCC/+/-10%

PJP2

12

12

4MM_OPEN_5MIL

/*

10UF/6.3V

PROJECT:

12

MLCC/+/-10%

pt_c1206_h35

GND

+1.25V_SRC_MP

1.25V_RUN_PWRGD51

GFX_CORE_PWRGD51

1.25V_GFX_PCIE_ON37

PJP8

12

12

4MM_OPEN_5MIL

/*

12

+

PC14

220UF/2.5V

pt_c7343d_h75

Lanai

5

TAN/Lf_T=2000hrs_105C/+/-20%

+1.25V_PG1

GFX_PG2

12

+3.3V_ALW

PR46

100KOhm

PC124

10UF/25V

12

1% /*

+DC3_PWR_SRC

12

PC5

pt_c1206_h71

MLCC/+/-10%

pt_inductor_2p_453x394

+1.25V_SRC_MP

PR146

1% /*

100KOhm

REVISION

1.1

10UF/25V

pt_c1206_h71

PL8

1UH

Irat=14.3A

12

12

PC4

MLCC/+/-10%

21

PR48
0Ohm

5%

/*

PR148
0Ohm

5%

/*

0.1UF/50V

pt_c0603

MLCC/+/-10%

GND

PR40

12

12

DATE:
SHEET OF

4

12

PC3

2200PF/50V

MLCC/+/-10%

+1.25V_DH

PQ6

FDS6982AS

Q2

5

4

D1

6

3

S1G1D1

Q1

7

2

D2 G2

81

D2

S2

+1.25V_L

+VCC_GFX_COREP

12

1%

PR145

pt_r0603

PC136

/*

4.99KOhm

0.1UF/10V

MLCC/+/-10%

PR43

1%

pt_r0603

9.31KOhm

GND

PR45

100KOhm

1

+5V_ALW2

5%

G

+3.3V_RUN

12

/*

5%

100KOhm

Monday, March 19, 2007

58 69

4

pt_c0805_h53
MLCC/+/-10%

12

+1.25V_VBST

GND

GFX_EN

12

PC137

GFX_VFB

39PF/50V

MLCC/+/-5%

12

12

12

PR53

100KOhm

/*

3

D

PQ11
2N7002

pt_sot23_philips

S

2

/*

GND

3

PR42
200KOhm

5%

2

3

PU5

PGND1

GND1

DRVL1

PGOOD1

V5DRV1

VFB1

TRIP1

V5FILT1

LL1

VOUT1

DRVH1

TON1

VBST1

EN_PSV1

EN_PSV2

VBST2

TON2

DRVH2
VOUT2
V5FILT2

TRIP2

VFB2

V5DRV2

PGOOD2

DRVL2
GND2 PGND2

SN0508073PWR

PR10

30.1KOhm

+1.25V_GFX_PCIe

+1.25V_RUN

12

GFX_BS

1

PD8

BAT54A

pt_sot23_philips

28

+1.25V_PG1

27
26
25
24
23

1.25V_EN +1.25V_V5FILT

22
21
20
19

LL2

18
17
16

12

1%

PR144

14KOhm

1%/*

PC40

pt_r0603

0.1UF/10V

12

PQ18
FDS8880

/*

SD

1

8

2

7

3

6
5

4

G

12

PC67

470PF/50V

MLCC/+/-10%

PC138

MLCC/+/-10%

/*

1UF/10V

MLCC/+/-10%

GND

PR138

12

12

PR141
150KOhm

1%

12

PC38

0.1UF/25V

+1.25V_BS

PR39
0Ohm

5%

+5V_SUS

12

12

GFX_PG2

12

GFX_V5FILT

12

PQ14
2N7002

pt_sot23_philips
/*

1
2
3
4
5
6
7
8

9
10
11
12
13
14 15

PR47

30.1KOhm

pt_r0603
1%

12

+1.25V_DL

PC131

1UF/10V

pt_c0805_h33
MLCC/+/-10%

+5V_SUS

PR41

5%

10Ohm

PC39

1UF/10V

pt_c0603

MLCC/+/-10%

+15V_ALW

12

/*

5%

3

D

1

G

S

2

GND GND

DESCRIPTION:

POWER_VGA_1.25V & VCC_GFX

3

12

PC42

1UF/10V

pt_c0603

MLCC/+/-10%

GND

GFX_DL

12

+5V_SUS

pt_c0805_h33

PR137

12

12

12

1%

15KOhm

PC133

1UF/10V

12

PR132

49.9KOhm

pt_r0603

1%

12

PR73

/*

5%

470KOhm

RELEASE DATE :

PC41

0.1UF/25V

pt_c0805_h53
MLCC/+/-10%

12

PR142
0Ohm

5%

12

567

8

12

PQ9
FDS8880

G

12

1%

pt_r0603

12

5%

PR130

100KOhm

12

+1.25V_RUN

PC60

10UF/16V

pt_c1206_h71

MLCC/+/-10%

SD

123

4

567

8

G

SD

123

4

PC130

100PF/50V

MLCC/+/-5%

PR136

1%

pt_r0603

22.6KOhm

PC125

0.01UF/16V

MLCC/+/-10%

GND

GND

GFX_VBST
GFX_DH

+1.25V_SRC_MP +VCC_GFX_COREP

12

5%

10Ohm

PR135

15KOhm

pt_c0603

MLCC/+/-10%

GND

PQ39

3

BSS138

D

pt_sot23_fair

1

G

S

2

PJP4

12

12

2MM_OPEN_5mil

/*

+1.25V_GFX_PCIE

12

PC62

10UF/16V

pt_c1206_h71

MLCC/+/-10%

GFX__LP

PQ10

FDS6676AS

/*MLCC/+/-10%

12

PC135

0.1UF/10V

PR8
10KOhm

pt_r0603

5%

12

12

PC35

pt_inductor_2p_453x394

GND

<OrgName>

2

+DC3_PWR_SRC

12

PC34

pt_c0603

MLCC/+/-10%

2200PF/50V

0.1UF/50V

PL9

0.88UH

Irat=17A

+3.3V_RUN

PR13
10KOhm

pt_r0603

5%

12

DESIGN ENGINEER :SCHEMATIC FILE NAME :

2

12

PC129

10UF/25V

MLCC/+/-10%

21

GFX_CORE_CNTRL 22

1.25V_EN

GFX_EN

JEFF

12

pt_c1206_h71

MLCC/+/-10%

PC134

PC30

10UF/25V

pt_c1206_h71

MLCC/+/-10%

12

+

PC132

330UF/2.5V

330UF/2.5V

pt_c7343d_h79

pt_c7343d_h79

TAN/Lf_T=2000hrs_105C/+/-20%

PR143
0Ohm

5%

12

PR147
0Ohm

5% /*

12

PR139
0Ohm

pt_r0603

5%

12

PR140
0Ohm

pt_r0603

/*

5%

12

1

Design specs. in default:

Design Current:8.19A
Maximum current:11.7A

OCP point min.:18.97A

+VCC_GFX_COREP

12

12

+

TAN/Lf_T=2000hrs_105C/+/-20%

GND

1.25V_RUN_ON 37

1.25V_GFX_PCIE_ON 37

GFX_CORE_ON 38

RUN_ON 28,37,49,51,54

PC128

0.1UF/10V

MLCC/+/-10%

PJP9

12

12

4MM_OPEN_5MIL

/*

PJP10

12

12

4MM_OPEN_5MIL

/*

1

+VCC_GFX_CORE

5

4

3

2

1

+3.3V_ALW

D D

TDC REQUSET TO CHANGE

PCON2

10

P_GND1

P_GND2

BATT_CON_9P

PCON1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

11

1

1

2

2

3

3

4

4

5

5

BATT+_IN
Z4304 SMB_CLK
Z4305 SMB_DAT
Z4306 BATT_PRES#

BATT_VOLT

GND

MBRS2040LT3G

PL4

21

1000Ohm/100MHz

pt_l0603

FERRITE BEAD(0603)1000OHM/0.1A

+DCIN_JACK

12

PC13

2200PF/50V

MLCC/+/-10%

C C

B B

A A

PC12

pt_c0603

0.1UF/50V

MLCC/+/-10%

10

11

DC_PWR_JACK_5P

pt_dc_pwr_jack_5p_6hold_lf2

GND

12

P_NC3

6

P_NC1

7

NP_NC1

8

NP_NC2

9

P_NC2
P_NC4

+PBATT

SYSPRES#

BATT1­BATT2-

PD15

pt_smb_h101

/*

MURATA/BLM41PG600SN1L

PD14

VZ0603M260APT

pt_varistor_0603
/*

12

GND

PR23
100Ohm

5%

12

12

PL6

21

60Ohm/100Mhz

pt_l1806

AC_OFF37

2

1

PD7

DA204U

pt_sot323_rohm

3

12

PR22
100Ohm

5%

PR4

5%

PQ1

15KOhm

pt_r0603

PMBS3904

12

100KOhm

pt_r0603

12

B

1

PR3

5%

32

3

D

12

PR6
33Ohm

5%
/*

12

PC117

0.1UF/25V

pt_c0603
MLCC/+/-10%

/*

GND

R1

2

2
E

C

3

12

1

1

G

B

R2

ESD DIODES

2

1

PD6

DA204U

pt_sot323_rohm

3

PR21
100Ohm

5%

12

12

PR19
100Ohm

5%

PR1

PR2

10KOhm

10KOhm

5%

5%
/*

12

PQ2

pt_sot23

FDV301N_NL

2

S

PR125
0Ohm

5%
/*

12

3
C

PQ33
DTC115EUA

pt_umt3_rohm_h39

E

/*

1

1

3

PBAT_SMBCLK 37,57
PBAT_SMBDAT 37,57

+5V_ALW

2

1

PD1

3

+DC_IN

PQ36
SI2301BDS

/*

23

S

2

1

1

CONFIRM JAY EE REQUEST TO
DE-POP

2

PD5

DA204U

pt_sot323_rohm

GND

DA204U

pt_sot323_rohm
/*

PC112

0.47UF/25V

pt_c0805_h53

D

3

G

1

3

12

PR5
33Ohm

5%

12

1%

PR122

MLCC/+/-10%

240KOhm

GND

2

PD4

GND

DA204U

pt_sot323_rohm
/*

PS_ID_DISABLE# 38

+5V_ALW

SD

1
2
3
4

G

PQ34
FDS6679_NL

12

PR121
47KOhm

5%

12

+3.3V_ALW

2

1

3

8
7
6
5

PR20

10KOhm

12

GND

PD2
DA204U

pt_sot323_rohm

+DC_IN_SS

PC114

0.01UF/25V

+3.3V_ALW

5%

+3.3V_ALW

12

PR123

MLCC/+/-10%

/*

PR30

5%

100KOhm

12

PR7

5%

2.2KOhm

12

5%

PC116

0.1UF/50V

4.7KOhm

pt_r0805_h24

12

GND

EE
request to
add

12

pt_c0603

MLCC/+/-10%

PBAT_PRES# 38

PBAT_ALARM#

PS_ID 37

12

PC115

pt_c0603

0.1UF/50V

MLCC/+/-10%

12

PC113

10UF/25V

pt_c1206_h71

MLCC/+/-10%

PROJECT:

5

Lanai

REVISION

1.1

Monday, March 19, 2007

DATE:
SHEET OF

59 69

4

GND

DESCRIPTION:

POWER_CONNECTOR

3

RELEASE DATE :

2

<OrgName>

DESIGN ENGINEER :SCHEMATIC FILE NAME :

JEFF

1

5

4

3

2

1

PM screw pad

D D

1

1

1

13G021049200DE

H7

ESA1-1A_NUT_M2_H2.5_2

H33
CT236B217D102

1

H36
CT315B394I158D138

1

H15
CT295B276I158D138

1

H29
crt413x394b394d138

1

H8
C98D98N

CPU

H30
CT295B276I162D142

1

H21
CT138B295D118

1

1

H31
CT295B276I162D142

1

H32
CT295B276DO138X154

1

13G021049200DE

H1
C256I138D118

1

H9
ESA1-1A_NUT_M2_H7_1

C C

B B

H24
CRT335X386B276D138

1

H2
CT315B295I158D118

1

H10
O47X31DO47X31N

1

H17
CT354B295I158D138

1

H3
CRT354X315B394D138

1

13G021052020DE13G021052020DE

H11

ESA1-1A_NUT_M2_H7_2

H37

CT354B295I177D157

1

Header2 13G021052030DE

H25
ESA1-1A_NUT_H0.4

H34
ESA1-1A_NUT_H0.4

H4
CRT337X413B394D138

1

H12
RT197X413D91

1

13G021052010DE

H18
ESA1-1A_NUT_M2_H8

H26
CRT394X413B394D138

1

H35
CRT394X413B394D138

1

H5

ESA1-1A_NUT_M2_H2.5_ 1

H13
CT315B394I158D138

1

SATA

Shielding case

H27
O43X98DO20X75

1

H6
O118X98DO118X98N

H14
CT315B394I158D138

H20
CT236B217D102

H28
CT315B394I158D138

1

H38
O43X98DO20X75

SPRING1
EMI_SPRING_PAD

/*

1

A A

1

5

PROJECT:

Lanai

REVISION

1.2

4

Monday, March 19, 2007

DATE:
SHEET OF

60 69

DESCRIPTION:

3

1

SCREW PAD

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

Sean Kuo

A

ASUS CONFIDENTIAL

B

C

D

E

MODEL NAME :

1 1

PCB NO :

???

ASUS P/N :

2 2

Elsa

???

Lanai USB Board

3 3

REV :1.1(DELL: X01)

4 4

5 5

MB PCB

Part Number Description

PCB 00B LA-3071P REV0 M/B

DA800004H0L

PROJECT:

BOM NO. ???
PCB P/N: ???

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

65 69

B

DESCRIPTION:

Cover Page

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

A

1 1

B

C

D

E

MCON2

3

12SIDE1

2 2

3 3

4 4

4

SIDE2

WTOB_CON_2P

MOLEX/53398-0271

RJ_TIP

1

RJ_RING

2

MH2
C276D165

1

MGND

RJ_TIP

RJ_RING

MH1
CT217BDO91X106

1

MGND

ML1 470OhmIrat=0.2A

21

MURATA/BLM18RK471SN1D

ML2 470OhmIrat=0.2A

21

MURATA/BLM18RK471SN1D

RJ_TIP_R
RJ_RING_R

12

MC1330PF/3KV

JOHANSON is
not in the QVL

12

MC2330PF/3KV

MLCC/+/-10%

pt_c1808_h65

MLCC/+/-10%

pt_c1808_h65

MCON1

P_GND1

3

NP_NC1

1

1

2

2

4

NP_NC2

P_GND2

MODULAR_JACK_2P

5

6

MGNDMGND

5 5

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

66 69

B

DESCRIPTION:

RJ-11 CONN

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Stanly_Hsu

E

5

ASUS CONFIDENTIAL

4

3

2

1

MODEL NAME :

D D

Elsa

Lanai Modem Board

C C

control signals

REV :1.1(DELL: X01)

RJ11 BOARD

WtoB
2P

Jack
2P

B B

A A

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

68 69

4

DESCRIPTION:

BLOCK DIAGRAM

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Stanly_Hsu

1

A

External USB PORT hookup reference. Your design may
need more or less external ports and may be mapped
differently .

B

C

D

E

1 1

2 2

3 3

UICH_USBP0-

UICH_USBP0+

UR3 0Ohm 5%

UICH_USBP1-

UICH_USBP1+ USBP1_D+

Platforms should put in PADS for the USB chokes if they
have the room. Chokes should be NOPOP.

USBP0_D+

USBP0_D-

UR4 0Ohm 5%

UR1 0Ohm 5%
UR2 0Ohm 5%

UGND

UL2

MURATA/DLW21SN900SQ2L

90OHM/100MHz

/*

14

23

12
12

UL1

MURATA/DLW21SN900SQ2L

90OHM/100MHz

/*

14

23

12
12

UU1

1

2

34

SRV05-4

/*

6

5

USBP0_D-

USBP0_D+

USBP1_D-

USBP1_D+

U+USB_SIDE_PWR

USBP1_D-

USB daughter board connector

UICH_USBP1­UICH_USBP1+

UICH_USBP0­UICH_USBP0+

UGND

UCON2

SUYIN/127150FA010G509ZR

11

NP_NC1

12

12

34

34

56

56

78

78

910

910

12

NP_NC2

BTOB_CON_10P

U+USB_SIDE_PWR

UGND

Place one 150uF cap by each
USB connector

U+USB_SIDE_PWR

UGND

12

+

UCE1

150UF/6.3V

pt_c7343d_h79
/*

UGND

12

+

UCE2

150UF/6.3V

pt_c7343d_h79

UH2

UH1

U+USB_SIDE_PWR
USBP0_D­USBP0_D+

U+USB_SIDE_PWR

USBP1_D­USBP1_D+

Screw hole

C244DO134X150

1

C244D134

1

12

UC2

0.1UF/10V

MLCC/+/-10%

UGND

12

UC1

0.1UF/10V

MLCC/+/-10%

UGND

UGND

UGND

UCON1

TYCO/1759528-1

1

V1+

2

DATA1_L

3

DATA1_H

4

GND1

USB_CON_1X4P

UCON3

TYCO/1759528-1

1

V1+

2

DATA1_L

3

DATA1_H

4

GND1

USB_CON_1X4P

P_GND1

5

UGND

P_GND1

5

UGND

P_GND2

6

P_GND2

6

4 4

Each channel is 1A

Place ESD diodes as close as USB connector. Semtech
SRV05-4 can also be used but the Philips IP42220CZ6 have
a lower input C ( 1pf vs 3pf ).

5 5

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

Consult you ESD Engineer if you think you may need to
add ESD Supression Components to your USB lines.
Add PADS ONLY until proven diodes are really needed.

69 69

B

DESCRIPTION:

USB PORT ( SINGLE * 2 )

C

RELEASE DATE :

<OrgName>

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E