Dell 1420 LANAI DIS Schematic

A

ASUS CONFIDENTIAL

B

C

D

E

MODEL NAME :

1 1

PCB NO :

???

ASUS P/N :

2 2

Elsa

???

Lanai Discrete VGA nVidia NB8M Schematics Document

uFCPGA Mobile Merom

Intel Crestline-PM + ICH8M

3 3

2007-03-19

REV : 1.2(DELL: X02)

4 4

<Variant Name>

MB PCB

Part Number Description

PCB 00B LA-3071P REV0 M/B

DA800004H0L

PROJECT:

BOM NO. ???
PCB P/N: ???

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

1 69

B

DESCRIPTION:

Cover Page

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

5 5

5

4

3

2

1

LANAI: DISCRETE

POWER

D D

POWER
CON.

Panel Connector

PG 28

C C

IO Board

CRT CONN.

TV CONN.

USB CONN.x2

MINI-CARD

WLAN

MINI-CARD

WWAN

B B

SIM
CARD

PCIEx1 (Lane2)

SIM CARD Board

S/PDIF

TO TV
CONN.

PG 30

A A

<Variant Name>

DIGITAL
MIC.

PG 28

PROJECT:

5

POWER SEQUENCE
LOGIC

POWER
CHARGER

POWER CONTROL
SWITCH

DISCHARGE PATH

+3.3V_SUS/+5V_SUS/+3.3V_RUN
+5V/+3.3V/+1.8V/+1.25_RUN

LVDS

VGA

TVOUT

USB2.0(P2,3)

USB2.0(P9)

AUDIO/AMP

PG 44,45,46

Speaker
CON

PG 46

WtoB
CON

PG 46

Audio
Jacks
*3

JACK Board

Lanai

REVISION

PG 51

PG 57

PG 49PG 59

PG 49

nVIDIA G86M

PCI EXPRESS GFX

PG 22,23,24,25,26,27

VGA

TVOUT

D.B
CON

PG 50

MDC

PG 36

RJ11

RJ11 Board

1.2

USB2.0(P2,3)

PCIEx1 (Lane2)

USB2.0(P9)

Monday, March 19, 2007

DATE:
SHEET OF

4

XDP

PG 52

PCIEx16

IHDA

CIR

PG 41

2 69

Merom

(478 Micro-FCPGA)

PG 7,8

(Symbol Rev.09)

Crestline

1299 uFCBGA

PG 9,10,11,12,13,14

(Symbol Rev.09)

DMI INTERFACE

ICH8-M

676 BGA

PG 15,16,17,18

(Symbol Rev.09)

SPI

LPC

SIO

MEC5025
128KB Flash
TMKBC

128 Pins VTQFP

PG 37

SPI

FLASH

PG 40

DESCRIPTION:

Touchpad
CON.

BLOCK DIAGRAM

PS/2

PG 41

ECE5011
Expander

BC

USB 2.0 Hub(4)

128 Pins VTQFP

FAN &THERMAL

3

USB2.0(P0,P1)

PCIE (Lane6)

PCI

PCIE (Lane4)
USB2.0(P6)
USB2.0(P7)

USB2.0(P5)

SATA

SATA-HDD

IDE

SIO

PG 38

EMC4001

PG 43

POWER

POWER I/O

+1.5V_RUN/+1.05V_VCCP

REGULATOR

+VCC_GFX_CORE/+1.25V_RUN

533/667 MHZ DDR II

533/667 MHZ DDR II

CAMERA

PG 28

PG 31

CD-ROM

PG 31

USER
INTERFACE

PG 42

RELEASE DATE :

PG 55

PG 58

USB CONN.

PG 39

USB Board

CARD READER
1394/R5C833

EXPRESS-CARD
R5538

Bluetooth

PG 41

SNIFFER

PG 42

2

POWER VCORE

POWER SYSTEM

5V_ALW & 3.3V_ALW

REGULATOR

+1.8V_SUS/+0.9V_DDR_VTT

DDR2-SODIMM1

PG 19

DDR2-SODIMM2

PG 19

PG 32,33,34

PG 35

CAPBTN
CON.

PG 40

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

PG 53

PG 54

PG 56

BCM5906KMLG

QFN-68

RJ45/Magnetic

PG 48

CLOCK

CK410M+LP

PG 21

PG 47

1

A

B

C

D

E

INDEX

Pg# Description DNI LIST

01

1 1

02

03

04

05

06

07-08

09-14

15-18

2 2

19-20

21

22-27

28

29

30

31

32-34

35

3 3

36

37

38

39

40

41

42

43

44-46

4 4

47

48

49

50

51

52

53-59

60

5 5

61 Change list (1)

Cover Page

Schematic Block Diagram

INDEX

Bus connection

SMBUS BLOCK

Power Rail

CPU ( Merom 、 Penryn )

Crestline

ICH8M

DDRII SO-DIMM( 533MHz 667MHz )

、

Clock Generator ( CK410M+LP )

VGA ( nVIADA - G86M & GDDR3)

LVDS CON & Camera & DMIC

RGB CON

TV OUT CON

SATA(HDD & CD_ROM)

MEDIA CARD READER / 1394 ( R5C833 )

PCI-Express Card

MDC CONN

EC ( MEC5025 )

SIO ( ECE5011 )

USB PORT x 2

FLASH & RTC & CAPBTN CONN

TOUCH PAD & BT & CIR & LID

SWITCH & LED

HARDWARE MONITOR ( EMC4001 )

AUDIO CODEC & AMP

LOM BCM5906

Magnetics and RJ-45

Power Control Switch

BtoB CON

Power Sequence Logic

XDP

Power Circuit

SCREW PAD

64

R01

R02

R03

U01

Power circuit Change list

Modem board cover page

RJ-11 CONN

Modem board Change list

USB board cover page

U02 USB PORT ( SINGLE * 2 )

Description DNI LISTPg#

Change list (2)62

<Variant Name>

63 Change list (3)

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

3 69

B

DESCRIPTION:

INDEX

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

A

B

C

D

E

Footprint Definition

Footprint is 0402 if there is no descriptionResistor

1 1

Capacitor Footprint is 0402 if there is no description

Ferrite Bead

Footprint is 0603 if there is no description

PCI
DEVICE

R5C833

PCI TABLE

IDSEL REQ#/GNT# PIRQ

PCI_AD17

PCI_REQ1#
PCI_GNT1#

PCI_PIRQC#
PCI_PIRQD#

Layout Note

For all of ESD diode, they should be placed as close as
possible to connectors and the signals from connectors
should be routed to ESD diodes first. There is no branch
or via before diodes

Lane 2

2 2

Lane 3

Lane 4

PCI Express TABLE

WWAN / Mini CardLane 1

WLAN / Mini Card

ExpressCard

Lane 5

Lane 6

LAN BCM5906KMLG

USB TABLE

3 3

4 4

5 5

ICH8-0
(EHCI#1)

ICH8-1
(EHCI#1)

ICH8-2
(EHCI#1)

ICH8-3
(EHCI#1)

ICH8-4
(EHCI#1)

ICH8-5
(EHCI#1)

ICH8-6
(EHCI#2)

ICH8-7
(EHCI#2)

ICH8-8
(EHCI#2)

ICH8-9
(EHCI#2)

User1
(Single port , in USB BD)

User2
(Single port , in USB BD)

User3
(Dual port-bottom , in I/O BD)

User4
(Dual port-top , in I/O BD)

Camera

ExpressCard

BT Module

WWAN / Mini Card

<Variant Name>

PROJECT:

A

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

B

4 69

DESCRIPTION:

Bus Connection

C

RELEASE DATE :

D

Note : No USB for WLAN

<OrgName>

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

E

5

4

+3.3V_SUS

3

+3.3V_SUS

+3.3V_RUN

2

1

MEM_SCLK 197

10K 10K

2.2K2.2K

ICH8-M

D D

AD19 ICH_SMBDATA

AC17 AMT_SMBCLK
AE19 AMT_SMBDAT

+5V_MEDIA

8.2K8.2K

2.2K 2.2K

+3.3V_RUN

7002
7002

MEM_SDATA 195

MEM_SCLK 197AJ26 ICH_SMBCLK
MEM_SDATA 195

7

Express Card WWAN

8

I/O Board

30
32

DIMM 0

DIMM 1

30
32

WLAN

6 DOCK_SMBCLK
5 DOCK_SMBDAT

+3.3V_ALW

CAPBTN Board

+3.3V_RUN

C C

2.2K

13 CKG_SMBCLK
12 CKG_SMBDAT

+3.3V_ALW

4.7K

2.2K
+3.3V_RUN

7002
7002

4.7K

2.2K

100 THRM_SMBCLK
99 THRM_SMBDAT

SIO

B B

MEC5025

+3.3V_ALW

2.2K

2.2K

+3.3V_ALW

112 PBAT_SMBCLK
111 PBAT_SMBDAT

+3.3V_ALW

8.2K

8.2K

+3.3V_ALW

8 LCD_SMBCLK
7 LCD_SMDDAT

+3.3V_RUN

2.2K2.2K

A A

+3.3V_ALW

2.2K

100

100

47pF

CLK_SCLK 16
CLK_SDATA 17

12
11

10
9

SMB_CLK 3
SMB_DAT 4

34
35

47pF

ECE4001

CHARGER

Battery
CONN.

LVDS
Connector

CLK GEN.

LCD_DDCCLK 43

VGA

LCD_DDCDAT

+3.3V_RUN

44

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

5 69

4

DESCRIPTION:

SMBUS BLOCK

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

A

B

C

OPTIONAL

D

E

ADAPTER

1 1

+PWR_SRC

BATTERY

2 2

TPS51120

ALWON

ALWON

THERM_STP#

3 3

+5V_
ALW2

+3.3V_RTC
_LDO

THERM_STP#

+5V_ALW

+RTC_CELL

SN0508073

ALWON

+3.3V_ALW

1.25V_RUN_ON

GFX_RUN_ON
RUN_ON

THERM_STP#

+1.25V_RUN

+VCC_GFX_CORE

ISL6260C
ISL6208

RUNPWROK

IMVP_VR_ON

+VCC_CORE

SN0508073

1.5V_RUN_ON

+1.5V_RUN

GFX_CORE_PWRGD

FDS8880

1.05_RUN_ON

+1.05V_VCCP

+1.25V_GFX_PCIE

TPS51116

DDR_ON

+1.8V_SUS

0.9V_DDR_VTT_ON

+0.9V_DDR_VTT

FDC653N

RUN_ON

4 4

5 5

<Variant Name>

PROJECT:

+5V_RUN

Lanai

A

BAT54S

+15V_ALW

REVISION

1.2

SI4800BDY

Monday, March 19, 2007

DATE:
SHEET OF

6 69

B

EE
SIDE

SUS_ON

FDS6612A

3.3V_RUN_ON

+3.3V_RUN+5V_SUS

EMC4001

+2.5V_RUN

DESCRIPTION:

SI4800BDY

3.3V_SUS_ON

+3.3V_SUS

Power Rail

C

RELEASE DATE :

FDS6612A

1.8V_RUN_ON

+1.8V_RUN

DESIGN ENGINEER :SCHEMATIC FILE NAME :

D

Eric_Ko

E

5

H_A#[3..16]9

D D

C C

B B

H_ADSTB#09

H_REQ#[0..4]9

H_A#[17..35]9

H_ADSTB#19

H_A20M#15

H_FERR#15

H_IGNNE#15
H_STPCLK#15

H_INTR15
H_NMI15
H_SMI#15

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

U24A

MOLEX/47387-4781

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD10

SOCKET478

ADDR GROUP

0

ADDR GROUP

1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS0#
RS1#
RS2#

TRDY#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#

PREQ#

TRST#

DBR#

BCLK0
BCLK1

HIT#

TCK
TDO

TMS

TDI

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

4

H_IERR#

12

R196 56Ohm 5%

H_RESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

12

R197 56Ohm 5%

CPU_PROCHOT#

H_THERMDA
H_THERMDC

H_THERMTRIP#

12

R474 56Ohm 5%

C642 2200PF/50V MLCC/+/-10% /*

XDP_BPM#0 52
XDP_BPM#1 52
XDP_BPM#2 52

XDP_BPM#3 52
XDP_BPM#4 52
XDP_BPM#5 52
XDP_TCK 52
XDP_TDI 52
XDP_TDO 52
XDP_TMS 52
XDP_TRST# 52
XDP_DBRESET# 17,38,52

H_THERMDCH_THERMDA

12

Voltage Level Shift

H_ADS# 9
H_BNR# 9

H_BPRI# 9
H_DEFER# 9

H_DRDY# 9
H_DBSY# 9
H_BR0# 9

H_INIT# 15

H_LOCK# 9

H_RESET# 9,52
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9

H_HIT# 9
H_HITM# 9

+1.05V_VCCP

+1.05V_VCCP

CLK_CPU_BCLK 21
CLK_CPU_BCLK# 21

+1.05V_VCCP +3.3V_ALW

+1.05V_VCCP

H_THERMDA 43
H_THERMDC 43

H_THERMTRIP# 43

3

H_DSTBN#09
H_DSTBP#09
H_DINV#09

H_D#[0..63]9 H_D#[0..63] 9

Layout note:
Place voltage
divider within

0.5" of GTLREF
pin

+1.05V_VCCP

R201
1KOhm

1%

12

R202
2KOhm

1%

12

R503 1KOhm /*1%
R500 1KOhm /*1%

C643 0.1UF/10V /*MLCC/+/-10%
R496 0Ohm /*5%

12
12

12

12

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

2

H_D#[0..63]9

H_DSTBN#19
H_DSTBP#19
H_DINV#19

CPU_MCH_BSEL010,21
CPU_MCH_BSEL110,21
CPU_MCH_BSEL210,21

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

CPU_TEST1
CPU_TEST2

CPU_TEST4
CPU_TEST6

For the purpose of testability, route these signals
through a ground referenced Zo= 55 ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB BCLK BSEL2 BSEL1 BSEL0

533 133 0 0 1

U24B

MOLEX/47387-4781

H_D#0

E22

AD26

AF26

F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

B22
B23
C21

T42

T31

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

SOCKET478

1

1

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5 H_D#37
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

DATA GRP 0

DATA GRP 1

MISC

CPU_TEST3

CPU_TEST5

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#

DATA GRP 2DATA GRP 3

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#
COMP0

COMP1
COMP2
COMP3

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36

H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

667 166 0 1 1

800 200 0 1 0

12

1

H_D#[0..63] 9

H_DSTBN#2 9
H_DSTBP#2 9

H_D#[0..63]

R167

54.9Ohm

1%

H_DINV#2 9

H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_DPRSTP# 10,15,53
H_DPSLP# 15
H_DPWR# 9
H_PWRGOOD 15
H_CPUSLP# 9
H_PSI# 53

12

R165 1KOhm 5%

R168

R498

27.4Ohm

54.9Ohm

1%

12

1%

12

H_PWRGD_XDP 52

R497

27.4Ohm

1%

12

+1.05V_VCCP

XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TCK
XDP_TRST#

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

12

R172 54.9Ohm 1%

12

R171 54.9Ohm 1%

12

R173 54.9Ohm 1%

12

R170 54.9Ohm 1%

12

R169 649Ohm 1%

1.2

Monday, March 19, 2007

DATE:
SHEET OF

7 69

4

CPU_PROCHOT#

1

G

2

S

Q61
2N7002

Id=180mA/Pd=300mW
/*

DESCRIPTION:

3

D

R495

2.2KOhm

/*

12

EC_CPU_PROCHOT# 37

MEROM CPU (1)

3

RELEASE DATE :

<OrgName>

2

Comp0,2 connect with Zo=27.4ohm, Comp1,3
connect with Zo=55 ohm, make those traces
length shorter than 0.5". Trace should be
at least 25 mils away from any other
toggling signal.

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

+VCC_CORE

D D

+VCC_CORE

All use 10U 4V (+-20% , X6S , 0805)Pb-Free.

12

C629

12

C353

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C604

12

C339

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C311

12

C627

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C318

12

C615

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

8 inside cavity, north side, secondary layer.

+VCC_CORE

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C352

12

C330

12

C336

C C

+VCC_CORE

12

C310

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C334

12

C605

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C599

12

C613

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

8 inside cavity, south side, secondary layer.

+VCC_CORE

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C625

12

C345

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C623

12

C313

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C308

B B

6 inside cavity, north side, primary layer.

+VCC_CORE

12

C350

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C351

12

C312

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

12

C626

12

C621

6 inside cavity, south side, primary layer.

+1.05V_VCCP

12

C596

0.1UF/10V

A A

MLCC/+/-10%

Layout out:
Place these inside socket cavity on North side secondary.

12

C595

0.1UF/10V

MLCC/+/-10%

12

C632

0.1UF/10V

MLCC/+/-10%

12

C362

0.1UF/10V

MLCC/+/-10%

12

C633

0.1UF/10V

MLCC/+/-10%

4

12

C322

10UF/4V

MLCC/+/-20%
pt_c0805

12

C335

10UF/4V

MLCC/+/-20%
pt_c0805

12

C307

0.1UF/10V

MLCC/+/-10%

12

C611

12

C349

12

C357

12

C628

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

10UF/4V

MLCC/+/-20%
pt_c0805

3

100U/25V *4 Remove to POWER CIRCUIT .

+VCC_CORE

12

+

CE4

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

12

+

CE3

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

12

+

CE6

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

U24C

MOLEX/47387-4781
A7
A9

A10
A12
A13
A15
A17
A18
A20

B7
B9

B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

AC10
AB10
AB12
AB14
AB15
AB17
AB18

SOCKET478

12

VCC001
VCC002
VCC003
VCC004
VCC005
VCC006
VCC007
VCC008
VCC009
VCC010
VCC011
VCC012
VCC013
VCC014
VCC015
VCC016
VCC017
VCC018
VCC019
VCC020
VCC021
VCC022
VCC023
VCC024
VCC025
VCC026
VCC027
VCC028
VCC029
VCC030
VCC031
VCC032
VCC033
VCC034
VCC035
VCC036
VCC037
VCC038
VCC039
VCC040
VCC041
VCC042
VCC043
VCC044
VCC045
VCC046
VCC047
VCC048
VCC049
VCC050
VCC051
VCC052
VCC053
VCC054
VCC055
VCC056
VCC057
VCC058
VCC059
VCC060
VCC061
VCC062
VCC063

VCCSENSE

VCC064
VCC065
VCC066

VSSSENSE

VCC067

+

CE8

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

/*

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA01
VCCA02

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

12

+

CE12

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

/*

+VCC_CORE+VCC_CORE

+1.05V_VCCP

12

+

CE2
220UF/4V

pt_c7343d_h79
+/-20%

VID0 53
VID1 53
VID2 53
VID3 53
VID4 53
VID5 53
VID6 53

VCCSENSE 53

VSSSENSE 53

NO.41

12

+

CE5

220UF/2V

pt_c7343d_h75
SANYO/2TPF220M7

2

12

C644

0.01UF/25V

MLCC/+/-10%
pt_c0603

Layout Note:
Place 0.01U/25V near PIN
B26.

VCCSENSE
VSSSENSE

Route VCCSENSE and VSSSENSE
traces at 27.4ohms with 50
mils spacing and length
matched to within 25 mil.
Place PU and PD within
1 inch of CPU.

+1.5V_RUN

12

C645

10UF/4V

MLCC/+/-20%
pt_c0805

+VCC_CORE

R177
100Ohm

1%

12

R176
100Ohm

1%

12

1

U24D

MOLEX/47387-4781

A4

VSS001

A8

VSS002

A11

VSS003

A14

VSS004

A16

VSS005

A19

VSS006

A23

VSS007

AF2

VSS008

B6

VSS009

B8

VSS010

B11

VSS011

B13

VSS012

B16

VSS013

B19

VSS014

B21

VSS015

B24

VSS016

C5

VSS017

C8

VSS018

C11

VSS019

C14

VSS020

C16

VSS021

C19

VSS022

C2

VSS023

C22

VSS024

C25

VSS025

D1

VSS026

D4

VSS027

D8

VSS028

D11

VSS029

D13

VSS030

D16

VSS031

D19

VSS032

D23

VSS033

D26

VSS034

E3

VSS035

E6

VSS036

E8

VSS037

E11

VSS038

E14

VSS039

E16

VSS040

E19

VSS041

E21

VSS042

E24

VSS043

F5

VSS044

F8

VSS045

F11

VSS046

F13

VSS047

F16

VSS048

F19

VSS049

F2

VSS050

F22

VSS051

F25

VSS052

G4

VSS053

G1

VSS054

G23

VSS055

G26

VSS056

H3

VSS057

H6

VSS058

H21

VSS059

H24

VSS060

J2

VSS061

J5

VSS062

J22

VSS063

J25

VSS064

K1

VSS065

K4

VSS066

K23

VSS067

K26

VSS068

L3

VSS069

L6

VSS070

L21

VSS071

L24

VSS072

M2

VSS073

M5

VSS074

M22

VSS075

M25

VSS076

N1

VSS077

N4

VSS078

N23

VSS079

N26

VSS080

P3

VSS081

SOCKET478

VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

8 69

4

DESCRIPTION:

Merom CPU (2)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

4

3

2

1

H_D#[0..63]7

D D

+1.05V_VCCP

12

R492

221Ohm

1%

H_SWING

12

12

C630

R493

0.1UF/10V

100Ohm

MLCC/+/-10%

1%

C C

+1.05V_VCCP

12

12

R199

R198

54.9Ohm

54.9Ohm

1%

1%

H_SCOMP
H_SCOMP#

H_RCOMP

12

R494

24.9Ohm

1%

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing

B B

+1.05V_VCCP

12

12

R482
1KOhm

1%

R484
2KOhm

1%

H_D#[0..63]

12

C617

0.1UF/10V

MLCC/+/-10%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#7,52
H_CPUSLP#7

H_REF

U11A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE_965PM

HOST

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#[3..35]

H_A#[3..35] 7

H_ADS# 7
H_ADSTB#0 7
H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7

CLK_MCH_BCLK 21

CLK_MCH_BCLK# 21
H_DPWR# 7
H_DRDY# 7
H_HIT# 7
H_HITM# 7
H_LOCK# 7
H_TRDY# 7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7

H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7
H_RS#1 7
H_RS#2 7

Layout Note:
Place the 0.1uF
decoupling capacitor
within 100 mils from
GMCH pins.

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

9 69

4

DESCRIPTION:

Crestline(HOST)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

+1.8V_SUS

12

R183
1KOhm

SM_RCOMP_VOH

12

12

D D

SM_RCOMP_VOL

12

+3.3V_RUN

R469 10KOhm 5%
R468 10KOhm 5%

+1.05V_VCCP

C C

B B

A A

<Variant Name>

C579

C586

2.2UF/10V

0.01UF/25V

MLCC/+/-10%

MLCC/+/-10%

c0603,pt_c0603

12

C585

C580

0.01UF/25V

2.2UF/10V

MLCC/+/-10%

MLCC/+/-10%
c0603,pt_c0603

12
12

R476

12

56Ohm 5%

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

CPU_MCH_BSEL07,21

CPU_MCH_BSEL17,21
CPU_MCH_BSEL27,21

+3.3V_RUN

PROJECT:

0.1%

12

R185

3.01KOhm

1%

12

R184
1KOhm

0.1%

PM_EXTTS#0
PM_EXTTS#1

DDR_A_MA1419,20
DDR_B_MA1419,20

THERMTRIP_MCH#

R475 4.02KOhm /*1%

R477 4.02KOhm 1%

R479 4.02KOhm /*1%

R471 4.02KOhm /*1%
R467 4.02KOhm /*1%

PM_BMBUSY#17

H_DPRSTP#7,15,53
PM_EXTTS#019
PM_EXTTS#119

ICH_PWRGD17,51

THERMTRIP_MCH#43

DPRSLPVR17,53

SB_NB_PCIE_RST#16

PLTRST#16,35,37

5

T137

1

T32

1

12

T135

1

T128

1

T138

1

12

T33

1

T132

1

T130

1

T131

1

T133

1

T34

1

12

T129

1

T30

1
12
12

THERMTRIP_MCH#

12

R487 0Ohm 5% /*

12

R486 0Ohm 5%

Lanai

DDR_A_MA14
DDR_B_MA14

PM_EXTTS#0
PM_EXTTS#1

PLTRST#_R

12

R151 0Ohm 5%

T18
T19
T21
T25
T23
T35
T37
T40
T38
T39
T36
T20
T24
T22
T26
T41

REVISION

U11B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

CFG3

C21

CFG_3

CFG4

C23

CFG_4

CFG5

F23

CFG_5

CFG6

N23

CFG_6

CFG7

G23

CFG_7

CFG8

J20

CFG_8

CFG9

C20

CFG_9

CFG10

R24

CFG_10

CFG11

L23

CFG_11

CFG12

J23

CFG_12

CFG13

E23

CFG_13

CFG14

E20

CFG_14

CFG15

K23

CFG_15

CFG16

M20

CFG_16

CFG17

M24

CFG_17

CFG18

L32

CFG_18

CFG19

N33

CFG_19

CFG20

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

1

NC_1

BK51

1

NC_2

BK50

1

NC_3

BL50

1

NC_4

BL49

1

NC_5

1

BL3

NC_6

1

BL2

NC_7

BK1

1

NC_8

BJ1

1

NC_9

E1

1

NC_10

A5

1

NC_11

C51

1

NC_12

B50

1

NC_13

A50

1

NC_14

A49

1

NC_15

BK2 R32

1

NC_16 TEST_2

CRESTLINE_965PM

R483 100Ohm 5%

12

PLTRST#_R

DATE:

1.2

SHEET OF

4

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DDR MUXINGCLKDMI

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2

CFGRSVD

PM

DMI_TXN_3
DMI_TXP_0

DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

ME

CL_VREF

NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

TEST_1

Monday, March 19, 2007

10 69

4

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

SMRCOMPP

BL15

SMRCOMPN

BK14

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31
AR49

AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35

1

A39

1

C38

1

B39

1

E36

1

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37

M_CLK_DDR0 19
M_CLK_DDR1 19
M_CLK_DDR2 19
M_CLK_DDR3 19

M_CLK_DDR#0 19
M_CLK_DDR#1 19
M_CLK_DDR#2 19
M_CLK_DDR#3 19

DDR_CKE0_DIMMA 19,20
DDR_CKE1_DIMMA 19,20
DDR_CKE2_DIMMB 19,20
DDR_CKE3_DIMMB 19,20

DDR_CS0_DIMMA# 19,20
DDR_CS1_DIMMA# 19,20
DDR_CS2_DIMMB# 19,20
DDR_CS3_DIMMB# 19,20

M_ODT0 19,20
M_ODT1 19,20
M_ODT2 19,20
M_ODT3 19,20

V_DDR_MCH_REF

CLK_MCH_3GPLL 21
CLK_MCH_3GPLL# 21

DMI_MRX_ITX_N0 16
DMI_MRX_ITX_N1 16
DMI_MRX_ITX_N2 16
DMI_MRX_ITX_N3 16

DMI_MRX_ITX_P0 16
DMI_MRX_ITX_P1 16
DMI_MRX_ITX_P2 16
DMI_MRX_ITX_P3 16

DMI_MTX_IRX_N0 16
DMI_MTX_IRX_N1 16
DMI_MTX_IRX_N2 16
DMI_MTX_IRX_N3 16

DMI_MTX_IRX_P0 16
DMI_MTX_IRX_P1 16
DMI_MTX_IRX_P2 16
DMI_MTX_IRX_P3 16

T127
T27
T29
T28
T126

CL_CLK0 17
CL_DATA0 17
ICH_CL_PWROK 17,37
ICH_CL_RST0# 17

MCH_CLVREF

CLK_3GPLLREQ# 21
MCH_ICH_SYNC# 17

R470
20KOhm

5%

12

DESCRIPTION:

3

Connect to
XDP CONN.

LCTLA_CLK52
LCTLB_DATA52

+1.8V_SUS

12

R480
20Ohm

1%

SMRCOMPP
SMRCOMPN

12

R481
20Ohm

1%

+1.25V_RUN

MCH_CLVREF

12

C293

0.1UF/10V

MLCC/+/-10%

12

R162
1KOhm

1%

12

R161
392Ohm

1%
pt_r0603

+3.3V_RUN

Non-iAMT

R465
0Ohm

5%

12

Crestline(VGA,DMI)

3

U11C

J40

L_BKLT_CTRL

H39

LCTLA_CLK
LCTLB_DATA

R464 10KOhm 5% /*

12

R463 10KOhm 5% /*

12

CFG5
CFG9
CFG16
CFG19

CFG20

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_965PM

DMI X2 Select
PCI Express

Graphic Lane
FSB Dynamic
ODT
DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

SDVO Present.SDVO_CRTL_DATA

RELEASE DATE :

2

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

LCTLA_CLK

NO.2

LCTLB_DATA

R462

R466

0Ohm

0Ohm

5%

5%

12

12

Low=DMIx2
High=DMIx4 (Default)
Low=Reverse Lane
High=Normal operation
Low=Dynamic ODT Disable
High=Dynamic ODT Enable (default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and PCIEx1 are operating
sumultaneously via PEG port

Low=No SDVO Device Present
(defaults)
High=SDVO Device Prsent

<OrgName>

2

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

1

+VCC_PEG

R461

VCC3G_PCIE_R

N43
M43

PCIE_MRX_GTX_N0

J51

PCIE_MRX_GTX_N1

L51

PCIE_MRX_GTX_N2

N47

PCIE_MRX_GTX_N3

T45

PCIE_MRX_GTX_N4

T50

PCIE_MRX_GTX_N5

U40

PCIE_MRX_GTX_N6

Y44

PCIE_MRX_GTX_N7

Y40

PCIE_MRX_GTX_N8

AB51

PCIE_MRX_GTX_N9

W49

PCIE_MRX_GTX_N10

AD44

PCIE_MRX_GTX_N11

AD40

PCIE_MRX_GTX_N12

AG46

PCIE_MRX_GTX_N13

AH49

PCIE_MRX_GTX_N14

AG45

PCIE_MRX_GTX_N15

AG41

PCIE_MRX_GTX_P0

J50

PCIE_MRX_GTX_P1

L50

PCIE_MRX_GTX_P2

M47

PCIE_MRX_GTX_P3

U44

PCIE_MRX_GTX_P4

T49

PCIE_MRX_GTX_P5

T41

PCIE_MRX_GTX_P6

W45

PCIE_MRX_GTX_P7

W41

PCIE_MRX_GTX_P8

AB50

PCIE_MRX_GTX_P9

Y48

PCIE_MRX_GTX_P10

AC45

PCIE_MRX_GTX_P11

AC41

PCIE_MRX_GTX_P12

AH47

PCIE_MRX_GTX_P13

AG49

PCIE_MRX_GTX_P14

AH45

PCIE_MRX_GTX_P15

AG42

PCIE_MTX_GRX_C_N0

N45

PCIE_MTX_GRX_C_N1

U39

PCIE_MTX_GRX_C_N2

U47

PCIE_MTX_GRX_C_N3

N51

PCIE_MTX_GRX_C_N4

R50

PCIE_MTX_GRX_C_N5

T42

PCIE_MTX_GRX_C_N6

Y43

PCIE_MTX_GRX_C_N7

W46

PCIE_MTX_GRX_C_N8

W38

PCIE_MTX_GRX_C_N9

AD39

PCIE_MTX_GRX_C_N10

AC46

PCIE_MTX_GRX_C_N11

AC49

PCIE_MTX_GRX_C_N12

AC42

PCIE_MTX_GRX_C_N13

AH39

PCIE_MTX_GRX_C_N14

AE49

PCIE_MTX_GRX_C_N15

AH44

PCIE_MTX_GRX_C_P0

M45

PCIE_MTX_GRX_C_P1

T38

PCIE_MTX_GRX_C_P2

T46

PCIE_MTX_GRX_C_P3

N50

PCIE_MTX_GRX_C_P4

R51

PCIE_MTX_GRX_C_P5

U43

PCIE_MTX_GRX_C_P6

W42

PCIE_MTX_GRX_C_P7

Y47

PCIE_MTX_GRX_C_P8

Y39

PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_P9

AC38

PCIE_MTX_GRX_C_P10

AD47

PCIE_MTX_GRX_C_P11

AC50

PCIE_MTX_GRX_C_P12

AD43

PCIE_MTX_GRX_C_P13

AG39

PCIE_MTX_GRX_C_P14

AE50

PCIE_MTX_GRX_C_P15 PCIE_MTX_GRX_P15

AH43

24.9Ohm 1%

12

PCIE_MRX_GTX_N[0..15] 22

PCIE_MRX_GTX_P[0..15] 22

C547 0.1UF/10V

12

C563 0.1UF/10V

12

C545 0.1UF/10V

12

C543 0.1UF/10V

12

C551 0.1UF/10V

12

C536 0.1UF/10V

12

C553 0.1UF/10V

12

C538 0.1UF/10V

12

C555 0.1UF/10V

12

C541 0.1UF/10V

12

C557 0.1UF/10V

12

C533 0.1UF/10V

12

C561 0.1UF/10V

12

C534 0.1UF/10V

12

C559 0.1UF/10V

12

C549 0.1UF/10V

12

C548 0.1UF/10V

12

C564 0.1UF/10V

12

C546 0.1UF/10V

12

C544 0.1UF/10V

12

C552 0.1UF/10V

12

C537 0.1UF/10V

12

C554 0.1UF/10V

12

C539 0.1UF/10V

12

C556 0.1UF/10V

12

C542 0.1UF/10V

12

C558 0.1UF/10V

12

C535 0.1UF/10V

12

C562 0.1UF/10V

12

C540 0.1UF/10V

12

C560 0.1UF/10V

12

C565 0.1UF/10V

12

Tolerence:
X7R +/-10%

PCIE_MTX_GRX_N[0..15] 22
PCIE_MTX_GRX_P[0..15] 22

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14

5

D D

4

3

2

1

DDR_A_D[0..63]19

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38 DDR_A_MA6
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U11D

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AM8
AN10

AT9
AN9

AM9
AN11

CRESTLINE_965PM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_BS0

BB19

SA_BS_0
SA_BS_1

SA_BS_2
SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

DDR SYSTEM MEMORY A

SA_RCVEN#

SA_WE#

BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1

DDR_A_BS2
DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

1

DDR_A_WE#

DDR_A_RAS# 19,20

T134

DDR_A_WE# 19,20

DDR_A_BS0 19,20
DDR_A_BS1 19,20
DDR_A_BS2 19,20

DDR_A_CAS# 19,20
DDR_A_DM[0..7] 19

DDR_A_DQS[0..7] 19

DDR_A_DQS#[0..7] 19

DDR_A_MA[0..13] 19,20

DDR_B_D[0..63]19

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15 DDR_B_DQS0
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20 DDR_B_DQS5
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U11E

AP49
AR51

AW50
AW51

AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4

BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

CRESTLINE_965PM

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

DDR SYSTEM MEMORY B

SB_WE#

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1

DDR_B_BS2
DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4

DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

1

DDR_B_WE#

DDR_B_RAS# 19,20

T136

DDR_B_WE# 19,20

DDR_B_BS0 19,20
DDR_B_BS1 19,20
DDR_B_BS2 19,20

DDR_B_CAS# 19,20
DDR_B_DM[0..7] 19

DDR_B_DQS[0..7] 19

DDR_B_DQS#[0..7] 19

DDR_B_MA[0..13] 19,20

A A

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

11 69

4

DESCRIPTION:

Crestline(DDR2)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

4

3

2

1

+3.3V_RUN

12

C290
1UF/10V

MLCC/+/-10%
pt_c0603

R473 10Ohm 5%

12

C614
22UF/4V

MLCC/+/-20%
pt_c0805_h53

+1.05V_VCCP

Non-iAMT

+VCC_GMCH

D D

+1.8V_SUS

C C

B B

A A

U11G

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20

AN14

CRESTLINE_965PM

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

12

C622

0.1UF/10V

MLCC/+/-10%

12

C631

0.1UF/10V

MLCC/+/-10%

12

C638

0.22UF/10V

MLCC/+/-10%
pt_c0603

+1.05V_VCCP

Layout Note:
370 mils form edge.

12

C600

0.22UF/10V

MLCC/+/-10%
pt_c0603

12

C292

0.47UF/10V

MLCC/+/-10%
pt_c0603

12

C291
1UF/10V

MLCC/+/-10%
pt_c0603

12

+

CE11
220UF/4V

pt_c7343d_h79
+/-20%

+VCC_GMCH_L

12

12

C576

0.22UF/10V

MLCC/+/-10%

pt_c0603

Layout Note:
Inside GMCH cavity

+VCC_AXM

12

C583

0.1UF/10V

MLCC/+/-10%

12

C572

22UF/4V

MLCC/+/-20%
pt_c0805_h53

Layout Note:
Place close to GMCH edge.

D18

21

RB751V_40

+VCC_GMCH

12

12

C575

C581

0.22UF/10V

MLCC/+/-10%

Layout Note:
Inside GMCH cavity

12

C584

0.1UF/10V

MLCC/+/-10%

12

C620

0.22UF/10V

MLCC/+/-10%

pt_c0603

0.1UF/10V

MLCC/+/-10%

pt_c0603

12

C582

0.1UF/10V

MLCC/+/-10%

12

C574

0.22UF/10V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

Layout Note:
Place C577 where LVDS
andDDR2 taps

12

C577

0.1UF/10V

MLCC/+/-10%

U11F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37 A3

VCC_NCTF_37 VSS_SCB1

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_965PM

12

+

CE1
330UF/6.3V

pt_c7343d_h110
+/-20%

POWER

12

C302
22UF/4V

MLCC/+/-20%
pt_c0805_h53

Layout Note:
Place on the edge

VCC NCTF

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

12

C296
22UF/4V

MLCC/+/-20%
pt_c0805_h53

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCC_AXM

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

12 69

4

DESCRIPTION:

Crestline(VCC,NCTF)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

4

3

2

1

+1.05V_VCCP

Place caps close to
VCC_AXF

+1.05V_VCCP

21

D17

RB751V_40

/*

+VCC_HV_L

21
12

R472
10Ohm 5%

/*

+3.3V_RUN

+1.25V_RUN

+VCC_AXF

12

12

C598
1UF/10V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

1uH+-20%_300mA

C592
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

45mA MAX.

Non-iAMT

D D

+1.25V_RUN

C C

B B

+1.25V_RUN

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

A A

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

L45

120Ohm/100Mhz

21

BLM18AG121SN1D

L22

120Ohm/100Mhz

21

BLM18AG121SN1D

R200

12

0.5Ohm 1%

pt_r0603

+VCC_MPLL_L

12

C641
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

220Ohm/100Mhz

BLM21PG221SN1D

pt_l0805_h41

12

L39

+VCCA_HPLL

C640
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

+VCCA_MPLL

+VCCA_PEG_PLL

21

12

12

12

C637

0.1UF/10V

MLCC/+/-10%

12

C364

0.1UF/10V

MLCC/+/-10%

R478
1Ohm

1%
pt_r0603

C608
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+1.25V_RUN

12

C569

0.1UF/10V

MLCC/+/-10%

+1.25V_RUN

Non-iAMT

12

12

CE10

+

100UF/6.3V

+/-20%
pt_c3528_h79

JP2

12

0Ohm

12

C363

JUMP

22UF/4V

MLCC/+/-20%
pt_c0805_h53

JUMP

JP3
0Ohm

+1.5V_RUN

12

C607

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C589
1UF/10V

MLCC/+/-10%
pt_c0603

12

10UF/6.3V

MLCC/+/-20%

pt_c0805_h53

C593

12

C602
22UF/4V

MLCC/+/-20%
pt_c0805_h53

12

C590
1UF/10V

MLCC/+/-10%
pt_c0603

12

0.1UF/10V

MLCC/+/-10%

+1.25V_RUN

Non-iAMT

+3.3V_RUN

C588

12

C566

0.1UF/10V

MLCC/+/-10%

12

C603
22UF/4V

MLCC/+/-20%
pt_c0805_h53

12

C578

0.1UF/10V

MLCC/+/-10%

12

+VCCA_SM

C587

0.022UF/16V

MLCC/+/-10%

12

C365

0.1UF/10V

MLCC/+/-10%

+VCCA_HPLL
+VCCA_MPLL

+VCCA_PEG_PLL

12

C606
1UF/10V

MLCC/+/-10%
pt_c0603

+VCCA_SM_CK

+VCCA_PEG_PLL

12

C571

0.1UF/10V

MLCC/+/-10%

U11H

J32

A33
B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32

L29
N28
AN2
U48

J41
H42

CRESTLINE_965PM

+VTTLF1
+VTTLF2
+VTTLF3

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

12

POWER

D TV/CRTLVDS

C366

0.47UF/10V

MLCC/+/-10%
pt_c0603

CRTPLLA PEGA SMTV

A CK A LVDS

12

C634

0.47UF/10V

MLCC/+/-10%
pt_c0603

VTT

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VTTLF1
VTTLF2
VTTLF3

12

C624

0.47UF/10V

MLCC/+/-10%
pt_c0603

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

+VTTLF1
+VTTLF2
+VTTLF3

+VCC_AXF

+VCC_SM_CK

+VCC_RXR_DMI

12

C636

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Place on the edge

12

C618

0.47UF/6.3V

MLCC/+/-10%

Place on the edge

+VCC_AXD_L

12

12

C597
1UF/10V

MLCC/+/-10%
pt_c0603

Place caps
close to
VCC_AXD

+3.3V_RUN

C573

12

0.1UF/10V

MLCC/+/-10%

12

C635

4.7UF/10V

MLCC/+/-10%
pt_c0805_h37

12

C639

4.7UF/10V

MLCC/+/-10%
pt_c0805_h37

12

0Ohm
C594
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

12

+VCC_PEG

12

+

CE9
220UF/4V

pt_c7343d_h79
+/-20%

12

+

CE7
220UF/4V

pt_c7343d_h79
+/-20%

12

+1.05V_VCCP

12

+

220UF/4V

pt_c7343d_h79
+/-20%

L42

+VCC_AXD_R

5%

pt_r0603

+1.25V_RUN

C570

0.1UF/10V

MLCC/+/-10%

12

C567
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

12

C294
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+VCC_SM_CK

C329
22UF/10V

MLCC/+80%-20%
pt_c1206_h71

CE13

JUMP

JP4

12

0Ohm

Reserved L1202 pad
for inductor

L41

21

91nH+-20%_1.5A

91NH/1.5A

L40

21

91NH/1.5A

91nH+-20%_1.5A

12

C301

0.1UF/10V

MLCC/+/-10%

Non­iAMT

+1.25V_RUN

L21

1UH/300mA

12

pt_l0805_h53

R187
1Ohm 1%

pt_r0603

+VCC_SM_CK_L

12

C346
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

+1.05V_VCCP

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

13 69

4

DESCRIPTION:

Crestline(POWER)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

U11I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

D D

C C

B B

A A

<Variant Name>

PROJECT:

AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

5

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AL1

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_965PM

VSS

Lanai

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

REVISION

1.2

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

4

Monday, March 19, 2007

DATE:
SHEET OF

4

14 69

U11J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_965PM

VSS

DESCRIPTION:

3

W11

VSS_287

W39

VSS_288

W43

VSS_289

W47

VSS_290

W5

VSS_291

W7

VSS_292

Y13

VSS_293

Y2

VSS_294

Y41

VSS_295

Y45

VSS_296

Y49

VSS_297

Y5

VSS_298

Y50

VSS_299

Y11

VSS_300

P29

VSS_301

T29

VSS_302

T31

VSS_303

T33

VSS_304

R28

VSS_305

AA32

VSS_306

AB32

VSS_307

AD32

VSS_308

AF28

VSS_309

AF29

VSS_310

AT27

VSS_311

AV25

VSS_312

H50

VSS_313

Crestline(VSS)

3

2

RELEASE DATE :

2

<OrgName>

1

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Ivan_Chou

1

5

12

R217 10MOhm 5%

X3

32.768KHZ

ICH_RTCX2 ICH_RTCX1

D D

C C

ICH_AZ_MDC_BITCLK36

ICH_AZ_CODEC_BITCLK44

NO.52

ICH_AZ_MDC_SYNC36

ICH_AZ_CODEC_SYNC44

ICH_AZ_MDC_RST#36

ICH_AZ_CODEC_RST#44

ICH_AZ_MDC_SDOUT36

ICH_AZ_CODEC_SDOUT44

Place all series terms close to ICH8 except for SDIN input lines, which
should be close to source. Placement of R235, R264, R265, R258 should
equal distance to the T split trace point as R236, R268, R270, R275
respective. Basically, keep the same distance from T for all series
termination resistors.

B B

SATA_TX0-31

SATA_TX0+31

Distance between the ICH-8 M and cap on the "P" signal
should be identical distance between the ICH-8 M and cap on
the "N" signal for same pair.

The circuit is only
needed if the
platform has the
SNIFFER.

A A

SATA_ACT#_R42

LED_MASK#38,41

C648 3900PF/50VMLCC/+/-10%
C650 3900PF/50VMLCC/+/-10%

Q43 2N7002

Id=180mA/Pd=300mW

R246 0Ohm 5% /*

12

NO.24

+RTC_CELL

R235 33Ohm 5%
R236 33Ohm 5%

12

C388
27PF/50V

MLCC/+/-5%

R264 33Ohm 5%
R268 33Ohm 5%

R265 33Ohm 5%
R270 33Ohm 5%

R258 33Ohm 5%
R275 33Ohm 5%

+3.3V_RUN

1

G

3

2

D

S

12

C377

15PF/50V

MLCC/+/-5%
/*

R295
1MOhm

5%

12

12

C389
27PF/50V

MLCC/+/-5%
/*

12
12

R247
10KOhm

5%

12

+/-10ppm/6PF

14

2

3

NO.24

R232

20KOhm

5%

ICH_RTCRST#

12

ICH_INTRUDER#

12

C391
1UF/10V/X7R

MLCC/+/-10%
pt_c0603

12
12

12
12

12
12

12
12

SATA_ACT#

ACZ_BIT_CLK

HD damping resistors will be
moved to daughter board

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

SATA_TX0-_C
SATA_TX0+_C

4

12

R213 0Ohm 5%

ICH _RSVD

0

0

1

1

NO.24

12

C375

15PF/50V

MLCC/+/-5%
/*

Place within 500 mils
of ICH8 ball

XOR Chain Entrance strap

ACZ_SDOUT

Description

0

RSVD

Enter XOR chain

1

0

Normal operation (Default)

Set PCIE port config bit 1

1

3

+RTC_CELL

R233
332KOhm

1%

ICH_INTVRMEN ICH_LAN100_SLP

12

R259
0Ohm 5%

/*

12

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5 and VccCL1.5)

ICH_INTVRMEN

+1.5V_PCIE_ICH

ICH_AZ_CODEC_SDIN044

ICH_AZ_MDC_SDIN136

CLK_PCIE_SATA#21
CLK_PCIE_SATA21

SPEAKER_DET#46
RTC_BAT_DET#40

SATA_RX0-31
SATA_RX0+31

Low = Internal VR Disabled
High = Internal VR Enable(Default)

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
ICH_INTRUDER#
ICH_INTVRMEN

ICH_LAN100_SLP
GLAN_CLK

T92

1

LAN_RXD0

T91

1

LAN_RXD1

T93

1

LAN_RXD2

T84

1

LAN_TXD0

T85

1

LAN_TXD1

T80

1

LAN_TXD2

T90

1

T145

1

GLAN_COMP

12

R344 24.9Ohm 1%

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#

T143

1

T54

1

ACZ_SDOUT
SPEAKER_DET#

RTC_BAT_DET#
SATA_ACT#

SATA_TX0-_C
SATA_TX0+_C

12

R301
1KOhm

5%
/*

ACZ_SDOUT

12

R517
1KOhm

5%
/*

SATABIAS

ICH_RSVD 17

12

R261 24.9Ohm 1%

+3.3V_RUN

U28A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8-M

Pull up for each detect line

ICH8M LAN100SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLANIHDASATA

CPUPWRGD/GPIO49

IDE LPCCPU

R257

100KOhm

5%

12

+RTC_CELL

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0

DA1

DA2

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

+3.3V_RUN+3.3V_RUN

R277

12

RTC_BAT_DET#SPEAKER_DET#

2

R300
332KOhm

1%

12

R298
0Ohm 5%

/*

12

High = Internal VR Enable(Default)

E5
F5
G8
F6

C4

LPC_LDRQ0#

G9

LPC_LDRQ1#

E6

SIO_A20GATE

AF13
AG26

H_DPRSTP#

AF26

H_DPSLP#

AE26

H_FERR#

AD24
AG29
AF27
AE24

AC20

SIO_RCIN#

AH14
AD23

AG28
AA24

THERMTRIP#_ICH

AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

100KOhm

5%

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

1

IDE_DD[0..15]

T53

LPC_LAD0 37
LPC_LAD1 37
LPC_LAD2 37
LPC_LAD3 37

LPC_LFRAME# 37

T71

1

T82

1

SIO_A20GATE 37
H_A20M# 7

H_DPRSTP# 7,10,53
H_DPSLP# 7

H_FERR# 7
H_PWRGOOD 7
H_IGNNE# 7
H_INIT# 7

H_INTR 7
SIO_RCIN# 37

H_NMI 7
H_SMI# 7

H_STPCLK# 7

IDE_DD[0..15] 31

IDE_DA0 31
IDE_DA1 31
IDE_DA2 31

IDE_DCS1# 31
IDE_DCS3# 31

IDE_DIOR# 31
IDE_DIOW# 31
IDE_DDACK# 31
IDE_IRQ 31
IDE_DIORDY 31
IDE_DDREQ 31

1

H_DPRSTP#
H_DPSLP#
H_FERR#

SIO_A20GATE
SIO_RCIN#

THERMTRIP#_ICH

12

R263
56Ohm

5%
/*

+1.05V_VCCP

12

+3.3V_RUN

12

R254
10KOhm

5%

+1.05V_VCCP

12

R271
56Ohm

5%
/*

R269
56Ohm

5%

12

12

R509
10KOhm

5%

R278
56Ohm

5%

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

15 69

4

DESCRIPTION:

ICH8: IDE/AC97/LPC/RTC

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

Place TX DC blocking caps close ICH8.

5

C434 0.1UF/10V MLCC/+/-10%

PCIE_TX1-50
PCIE_TX1+50

PCIE_TX2-50
PCIE_TX2+50

D D

C C

PCIE_TX4-35
PCIE_TX4+35

PCIE_TX6-/GLAN_TX-47
PCIE_TX6+/GLAN_TX+47

SPI_CS0#40

12

R595 15Ohm5% /*

12

R594 0Ohm 5%

12

C436 0.1UF/10V MLCC/+/-10%

12

C443 0.1UF/10V MLCC/+/-10%

12

C439 0.1UF/10V MLCC/+/-10%

12

C458 0.1UF/10V MLCC/+/-10%

12

C461 0.1UF/10V MLCC/+/-10%

12

C714 0.1UF/10V MLCC/+/-10%

12

C713 0.1UF/10V MLCC/+/-10%

12

Layout Note:
Place 15 ohm within
500 mils from ICH.

+3.3V_ALW

U33

5

VCC

ICH_SPI_CS#_R

2

4

A

Y

1

B

GND

3

74AHC1G08GW

/*

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

ICH_EC_SPI_CLK37

ICH_EC_SPI_DO37
ICH_EC_SPI_DIN37

R596 15Ohm 5%

12

R353 15Ohm 5%

R343 15Ohm 5%

ICH_SPI_CS#

SIO_SPI_CS# 37

Non-iAMT

OC4#

OC7#

OC6#

OC9#

B B

A A

<Variant Name>

PCI_AD[0..31]32

PCI_PIRQB#
PCI_PIRQC#32
PCI_PIRQD#32

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

T95

PCI_PIRQA#

1

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PROJECT:

5

U28B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10 B3

PIRQD# PIRQH#/GPIO5

ICH8-M

Lanai

PCI

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

REVISION

1.2

PAR

PME#

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18

PCI_GNT1#

C18

SB_WWAN_PCIE_RST#

B19

PCI_GNT2#

F18

SB_LOM_PCIE_RST#

A11

PCI_GNT3#

C10
C17

E15
F16
E17

PCI_IRDY#

C8
D9

PCI_RST#_G

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10
G7

ICH_GPIO2_PIRQE#

F8

SB_WLAN_PCIE_RST#

G11

SB_NB_PCIE_RST#

F12

DATE:
SHEET OF

4

PCIE_RX1-50

PCIE_RX1+50

MiniWWAN

PCIE_RX2-50

PCIE_RX2+50

MiniWLAN

PCIE_RX4-35

PCIE_RX4+35

ExpressCard

PCIE_RX6-/GLAN_RX-47
PCIE_RX6+/GLAN_RX+47

12

T78

1

12

USB_OC0_1#39
USB_OC2_3#50

RP1E

65

10KOhm 5%

RP1F

75

10KOhm 5%

RP1G

85

10KOhm 5%

RP1H

95

10KOhm 5%

PCI_REQ0#
PCI_GNT0#
PCI_REQ1# 32
PCI_GNT1# 32
SB_WWAN_PCIE_RST# 50

SB_LOM_PCIE_RST# 47

CLK_PCI_ICH 21

SB_WLAN_PCIE_RST# 50
SB_NB_PCIE_RST# 10
PCIE_MCARD2_DET# 50

Monday, March 19, 2007

16 69

4

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_C
GLAN_TXP_C

ICH_EC_SPI_CLK_R
ICH_SPI_CS#
ICH_SPI_CS1#_R

ICH_EC_SPI_DO_R

USB_OC0_1#
USB_OC2_3#
OC4#

OC5#
OC6#
OC7#
OC8#
OC9#

10

RP1D

10

10

RP1C

10

10

RP1B

10

10

RP1A

10

PCI_C_BE0# 32
PCI_C_BE1# 32
PCI_C_BE2# 32
PCI_C_BE3# 32

PCI_IRDY# 32
PCI_PAR 32

PCI_DEVSEL# 32
PCI_PERR# 32

PCI_SERR# 32
PCI_STOP# 32
PCI_TRDY# 32
PCI_FRAME# 32

ICH_PME# 38

45

10KOhm 5%

35

10KOhm 5%

25

10KOhm 5%

15

10KOhm 5%

1
1

NO.13

DESCRIPTION:

U28D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

ICH8-M

+3.3V_SUS

USB_OC2_3#

OC8#

OC5#

USB_OC0_1#

T77
T89

R5C833

ICH8: PCI/INT/DMI/USB

3

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

PCI-Express

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P
USBP6N

USB

USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

ICH_SPI_CS1#_R
PCI_GNT0#

REQ1 GNT1 PIRQC

3

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

12

ICH_USBP4­ICH_USBP4+

ICH_USBP8­ICH_USBP8+

R347
1KOhm

5%

DMI_COMP

USBRBIAS

DMI_MTX_IRX_N0 10
DMI_MTX_IRX_P0 10
DMI_MRX_ITX_N0 10
DMI_MRX_ITX_P0 10

DMI_MTX_IRX_N1 10
DMI_MTX_IRX_P1 10
DMI_MRX_ITX_N1 10
DMI_MRX_ITX_P1 10

DMI_MTX_IRX_N2 10
DMI_MTX_IRX_P2 10
DMI_MRX_ITX_N2 10
DMI_MRX_ITX_P2 10

DMI_MTX_IRX_N3 10
DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N3 10
DMI_MRX_ITX_P3 10

CLK_PCIE_ICH# 21
CLK_PCIE_ICH 21

12

R286 24.9Ohm 1%

ICH_USBP0- 39
ICH_USBP0+ 39
ICH_USBP1- 39
ICH_USBP1+ 39
ICH_USBP2- 50
ICH_USBP2+ 50
ICH_USBP3- 50
ICH_USBP3+ 50

ICH_USBP5- 28
ICH_USBP5+ 28
ICH_USBP6- 35
ICH_USBP6+ 35
ICH_USBP7- 41
ICH_USBP7+ 41

ICH_USBP9- 50
ICH_USBP9+ 50

USER1 Left side pair top/left

USER2 Left side pair bottom/right

USER3 Right side pair top/left

USER3 Right side pair bottom/right

1
1

CCD

Express Card

BlueTooth

1
1

WWAN

12

R561

22.6Ohm

1%
pt_r0603

Boot BIOS Strap

LPC 11 No stuff No stuff

R337
1KOhm

PCI 10 No stuff Stuff

5%
/*

12

SPI 01 Stuff No stuff

PCI_GNT3#

T63
T68

NO.5

T59
T62

GNT0# SPI_CS1#

R346
1KOhm/*5%

12

A16 away override strap.

PCI_GNT3# Low = A16 swap override enabled.

PIRQD

High = Default.

CLK_PCI_ICH

Reserved for EMI.
Place resister and cap
close to ICH.

R355
10Ohm

5%
/*

12

12

C475

8.2PF/50V

MLCC/+/-0.25PF
/*

RELEASE DATE :

2

+1.5V_PCIE_ICH

<OrgName>

2

BIOS should not enable the internal GPIO pull up
resistor

SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#

SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#
SB_WWAN_PCIE_RST#

R338 10KOhm 5%
R147 10KOhm 5%

R491 100KOhm 5%
R334 100KOhm 5%
R354 20KOhm 5%
R356 20KOhm 5%

1

12
12

12
12
12
12

+3.3V_RUN

Place within 500 mils of ICH8

PCI Pullups

PCI_STOP#
PCIE_MCARD2_DET#

PCI_DEVSEL#

PCI_FRAME#

ICH_GPIO2_PIRQE#

PCI_SERR#

PCI_REQ0#

PCI_PLOCK#

Non-iAMT

PCI_RST#_G

PCI_PLTRST#

PCI_PLTRST#

DESIGN ENGINEER :SCHEMATIC FILE NAME :

R350 8.2KOhm 5%

12

R613 100KOhm 5%

12

RP4E

65

8.2KOhm 5%
RP4F

75

8.2KOhm 5%
RP4G

85

8.2KOhm 5%
RP4H

95

8.2KOhm 5%

RP3E

65

8.2KOhm 5%
RP3F

75

8.2KOhm 5%
RP3G

85

8.2KOhm 5%
RP3H

95

8.2KOhm 5%

C689 0.047UF/10V

12

MLCC/+/-10%

U30

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

C382 0.047UF/10V

12

MLCC/+/-10%

U14

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

C747 0.047UF/10V

12

MLCC/+/-10%

U37

1

A

VCC

2

B

34

GND Y

SN74AHC1G32DBVR

Terry_Lin

10

10

10

10

10

10

10

10

5

5

5

RP4D

10

10

10

10

10

10

10

10

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

PCI_REQ1#

45

8.2KOhm 5%

RP4C

PCI_PIRQD#

35

8.2KOhm 5%

RP4B

25

8.2KOhm 5%

RP4A

PCI_TRDY#

15

8.2KOhm 5%

RP3D

45

8.2KOhm 5%

RP3C

35

8.2KOhm 5%

RP3B

25

8.2KOhm 5%

RP3A

15

8.2KOhm 5%

Add Buffers as needed for
Loading and fanout
concerns.

PCI_RST# 32

PLTRST# 10,35,37

PLTRST_LAN_MINICARD# 47,50

12

C758
47PF/50V

MLCC/+/-5%

1

+3.3V_RUN
+3.3V_RUN
+3.3V_RUN

+3.3V_RUN

PCI_PIRQC#

PCI_PIRQB#

PCI_PIRQA#PCI_PERR#

PCI_IRDY#

NO.51

NO.13

NO.36

5

+3.3V_SUS

R253 10KOhm 5% /*

+3.3V_SUS

RN36A

12

2.2KOhm

RN36B

34

2.2KOhm

D D

+3.3V_RUN

R512

8.2KOhm

5%

12

R507
10Ohm

5%
/*

12

Option to "Disable "
clkrun. Pulling it down

C C

will keep the clks
running.

USB_IDE#

R506 8.2KOhm 5%

SIO_EXT_SCI#

12

R297 10KOhm 5%

12

CLKRUN#

Non-iAMT

5%
5%

ICH_SMBDATA
ICH_SMBCLK

T45

LOM_SMB_ALERT#37

NO.14

+3.3V_RUN
+3.3V_SUS

12

R307 10KOhm 5%

12

R283 10KOhm 5%

12

R282 10KOhm 5%

12

R281 10KOhm 5%

12

R315 1KOhm 5%

12

ICH_SMBCLK35,50

ICH_SMBDATA35,50

1

XDP_DBRESET#7,38,52

R520 0Ohm 5% /*

ICH_PCIE_WAKE#38

IRQ_SERIRQ32,37

SIO_EXT_W AKE#38

PCIE_MCARD1_DET#50
USB_MCARD1_DET#50

USB_MCARD2_DET#50

IDE_RST_MOD31

SATA_CLKREQ#21

PLTRST_DELAY#22

CCD_VDD_ON28

NO.8

MCH_ICH_SYNC#10

ICH_RSVD15

T74

PM_BMBUSY#10

12

H_STP_PCI#21

H_STP_CPU#21

CLKRUN#32,37

T56

IMVP_PWRGD37,51,53

T139

T144

SIO_EXT_SMI#37

SIO_EXT_SCI#37

NO.13

SPKR44

12

R508 0Ohm 5%

1

1

1

1

R608 4.7KOhm 5%
T157

1

T142

1

T148

1

4

Non-iAMT

RSV_ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
LOM_ICH_SMBALERT#
ICH_PCIE_WAKE#

ICH_SMBCLK
ICH_SMBDATA
RSV_ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT

ICH_RI#

LOM_ICH_SMBALERT#

CLKRUN#
ICH_PCIE_WAKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD

USB_IDE#
RSVD_GPIO6
SIO_EXT_W AKE#
SIO_EXT_SMI#
SIO_EXT_SCI#
PCIE_MCARD1_DET#

12

RSVD_GPIO20
USB_MCARD2_DET#
USB_MCARD3_DET#

PLTRST_DELAY#

RSVD_GPIO39

CCD_VDD_ON

SPKR

MCH_ICH_SYNC#_R

U28C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8-M

SYS

SMB

GPIO

GPIO

MISC

SATA

GPIO

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

CLGPIO0/GPIO24
CLGPIO1/GPIO10
CLGPIO2/GPIO14

WOL_EN/GPIO9

AJ12
AJ10
AF11
AG11

CLK_ICH_14M

AG9

CLK_ICH_48M

G5

ICH_SUSCLK

D3
AG23

SIO_SLP_S4#

AF21
AD18

SIO_S4_STATE#

AH27

ICH_PWRGD

AE23

DPRSLPVR

AJ14

ICH_BATLOW#

AE21
C2

ICH_LAN_RST#

AH20

12

R252 0Ohm 5%

12

AG27

R251 0Ohm 5% /*

E1

ICH_CL_PWROK

E3

RSV_SIO_SLP_M#

AJ25
F23

RSV_ICH_CL_CLK1

AE18
F22

RSV_ICH_CL_DATA1

AF19

CL_VREF0

D24

CL_VREF1

AH23
AJ23

PCIE_MCARD3_DET#

AJ27

ME_EC_ALERT

AJ24

EC_ME_ALERT

AF22

WOL_EN

AG19

+3.3V_RUN

R513

8.2KOhm

5%

12

1

12

R299 8.2KOhm5%

T146

1

T48

1

T47

1

T140

1

T50

1

T141

1

T46

1

CLK_ICH_14M 21
CLK_ICH_48M 21

T156

SIO_SLP_S3# 37
SIO_SLP_S5# 37

T147

1

ICH_PWRGD 10,51
DPRSLPVR 10,53

SIO_PWRBTN# 37

ICH_RSMRST# 37
SUSPWROK 43, 51

CLK_PWRGD 21
ICH_CL_PWROK 10,37

CL_CLK0 10

CL_DATA0 10

ICH_CL_RST0# 10

1

+3.3V_SUS

2

1

Place these close to ICH8

CLK_ICH_48M

CLK_ICH_14M

T49

ICH_PWRGD
DPRSLPVR
WOL_EN
SUSPWROK
ICH_LAN_RST#
ICH_CL_PWROK

R266 10KOhm 5%

12

R515 100KOhm 5%

12

R256 100KOhm 5%

12

R249 10KOhm 5% /*

12

R516 1MOhm 5%

12

R340 1MOhm 5%

12

NO.31

12

R339
10Ohm

5%

12

C456

4.7PF/50V

MLCC/+/-0.25PF

12

R272
10Ohm

/*
5%

12

C395

4.7PF/50V

/*
MLCC/+/-0.25PF

Non-iAMT

+3.3V_SUS

EC_ME_ALERT

R231 8.2KOhm 5%

12

+3.3V_RUN

B B

+3.3V_RUN

R620 100KOhm 5%
R303 10KOhm 5%

R514 10KOhm 5% /*
R276 10KOhm 5%
R511 10KOhm 5%
R510 10KOhm 5%

R262 10KOhm 5%

R609 100KOhm 5%

12
12

12
12
12
12

12

12

NO.13

RSVD_GPIO20
RSV_THRM#

MCH_ICH_SYNC#_R
IRQ_SERIRQ
RSVD_GPIO6
RSVD_GPIO39

PLTRST_DELAY#

CCD_VDD_ON

R280
1KOhm 5%

/*

12

SPKR

No Reboot strap.

SPKR Low=Default
High=No Reboot

NO.8

+3.3V_SUS

A A

SIO_EXT_SMI#

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

17 69

4

<Variant Name>

R309 10KOhm 5%

12

PROJECT:

5

Non-iAMT

+3.3V_RUN

SMBus address D2

These are for
backdrive issue

1

ICH_SMBDATA35,50

ICH_SMBCLK35,50

DESCRIPTION:

ICH8: SMB/PWR/CLK/GPIO

3

D

Q40 2N7002

Id=180mA/Pd=300mW

+3.3V_RUN

1

3

D

Q41 2N7002

Id=180mA/Pd=300mW

3

G

2

S

G

2

S

RN35A

2.2KOhm

5%

RN35B

2.2KOhm

5%

12

34

MEM_SDATA 19

MEM_SCLK 19

RELEASE DATE :

Pull up for each detect line

RP2E

10

65

100KOhm 5%

RP2F

75

100KOhm 5%

100KOhm 5%

100KOhm 5%

RP2G

85

RP2H

95

USB_MCARD3_DET# PCIE_MCARD3_DET#

USB_MCARD2_DET#

Non-iAMT

CL_VREF0

12

C466

0.1UF/10V

MLCC/+80-20%

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

RP2D

10

10

RP2C

10

10

RP2B

10

10

RP2A

10

+3.3V_RUN +3.3V_SUS

12

R352

3.24KOhm

1%

CL_VREF1

12

12

R351
453Ohm

1%

Terry_Lin

+3.3V_RUN

45

100KOhm 5%

35

100KOhm 5%

25

100KOhm 5%

15

100KOhm 5%

C378

0.1UF/10V

MLCC/+80-20%
/*

USB_MCARD1_DET#

PCIE_MCARD1_DET#

12

R218

3.24KOhm

1%
/*

12

R219
453Ohm

1%
/*

1

NO.13

5

+RTC_CELL

R366 100Ohm 5%

12

+5V_RUN

D D

+3.3V_RUN

Non-iAMT

+3.3V_SUS

+1.5V_RUN

C C

+1.5V_RUN

12

R210
0Ohm 5%

+VCCSATPLL_L

L23

21

+VCCSATPLL

+VCCGLANPLL

12

C418
1UF/10V

MLCC/+/-10%
pt_c0603

12

C649
1UF/10V

MLCC/+/-10%
pt_c0603

B B

Non-iAMT

Place CAP
close to A24

+1.5V_RUN

A A

RB751V_40

12

+5V_SUS

R314 10Ohm5%

FB_330ohm+-25%_100mHz_

1.5A_0.09_ohm DC

L53
330Ohm/100Mhz

MURATA/BLM21PG331SN1D
pt_l0805_h41

21
12

+

CE14
220UF/4V

pt_c7343d_h79
+/-20%

10uH

Irat=100mA
pt_l0805

12

C646
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

D14

D12

RB751V_40

21

21

12

C470
22UF/10V

MLCC/+/-20%
pt_c1206_h75

+ICH_V5REF_RUN

12

C477

0.1UF/10V

MLCC/+/-10%

+ICH_V5REF_SUS

12

C445

0.1UF/10V

MLCC/+/-10%

+1.5V_RUN

+1.5V_PCIE_ICH

12

12

C412
22UF/10V

MLCC/+/-20%
pt_c1206_h75

12

C462

0.1UF/10V

MLCC/+/-10%

+3.3V_RUN

Non-iAMT

C403
1UF/10V

MLCC/+/-10%
pt_c0603

+1.5V_PCIE_ICH

12

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

12

C473

4.7UF/6.3V

MLCC/+/-10%
pt_c0603

12

C401

0.1UF/10V

MLCC/+/-10%

C428

2.2UF/10V

MLCC/+/-10%
pt_c0805_h53

T61
T67

12

C451

0.1UF/10V

MLCC/+/-10%

12

C402

0.1UF/10V

MLCC/+/-10%

+VCCSATPLL

12

C435

0.1UF/10V

MLCC/+/-10%

12

C411

0.1UF/10V

MLCC/+/-10%

12

C398

0.1UF/10V

MLCC/+/-10%

TP_VCCSUSLAN1

1

TP_VCCSUSLAN2

1

+3.3V_RUN

4

+VCCGLANPLL

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27
F24
F25
G24
H23
H24

J23

J24
K24
K25

L23
L24

L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25

Y25
AJ6
AE7

AF7
AG7
AH7
AJ7

AC1
AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17
G18

F19
G20

A24
A26

A27
B26
B27
B28

B25

U28F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8-M

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

3

12

C455

0.1UF/10V

MLCC/+/-10%

+VCC_DMI

+V_CPU_IO

12

C419

0.1UF/10V

MLCC/+/-10%

12

C450

0.1UF/10V

MLCC/+/-10%

12

C467

0.1UF/10V

MLCC/+/-10%

+TP_VCCSUS1.05_1
+TP_VCCSUS1.05_2

+TP_VCCSUS1.5_1
+TP_VCCSUS1.5_2
+VCCSUS3_3[0~6]

+VCCSUS3_3[7~19]

TP_VCCCL1.05
VCCCL1_5

+3.3V_RUN

Non-iAMT

+1.5V_DMIPLL

12

C432

0.01UF/25V

MLCC/+/-10%

12

C390

0.1UF/10V

MLCC/+/-10%

12

C460

0.1UF/10V

MLCC/+/-10%

T75

1

T51

1

T52

1

T72

1

T70

1

+1.05V_VCCP

12

C465

0.1UF/10V

MLCC/+/-10%

L49 0.1Ohm/100Mhz

pt_inductor_2p_126x98_tdk

21

12

C695
10UF/6.3V

MLCC/+/-20%
pt_c0805_h53

12

C397

0.1UF/10V

MLCC/+/-10%

Intel 20%

12

C410

12

C424

0.1UF/10V

MLCC/+/-10%

12

C396

0.1UF/10V

MLCC/+/-10%

0.1UF/10V

MLCC/+/-10%

12

C476

0.1UF/10V

MLCC/+/-10%
/*

+3.3V_RUN

Non-iAMT

+3.3V_SUS

+1.5V_DMIPLL_R

12

C392
22UF/10V

MLCC/+/-20%
pt_c1206_h75

12

C409

0.1UF/10V

MLCC/+/-10%

+3.3V_RUN

R285

0Ohm

5%

12

12

C407

0.1UF/10V

MLCC/+/-10%

12

C474
1UF/10V

MLCC/+/-10%
pt_c0603
/*

D13

1
2

BAT54C

+1.5V_RUN

12

R572 1Ohm 5%

pt_r0603

+1.25V_RUN

12

C440

4.7UF/10V

MLCC/+/-10%
pt_c1206_h71

Non-iAMT

12

2

3

+1.05V_VCCP

VCCHDA

C433

0.022UF/16V

MLCC/+/-10%

+1.5V_RUN+1.05V_VCCP

12

R332 10Ohm

pt_r0805_h24

+3.3V_SUS

12

C464

0.022UF/16V

MLCC/+/-10%

12

C427

0.1UF/10V

MLCC/+/-10%

1

U28E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

5%

AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AE12
AE22
AE25

AF14
AF16
AF18

AH10
AH13
AH16
AH19

AF28
AH22
AH24
AH26

VSS[004]

A25

VSS[005]

AB1

VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]
VSS[021]

AE2

VSS[022]
VSS[023]

AD1

VSS[024]
VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]
VSS[029]
VSS[030]
VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]

AH2

VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

ICH8-M

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

J25
J26
J27

J4

J5
K23
K28
K29

K3
K6

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

18 69

4

DESCRIPTION:

ICH8-M(POWER,GND)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Terry_Lin

1

5

A is required to route to Top
S0DIMM for AMT to function
Ch.A SODIMM needs to be
populated for Intel AMT support.

D D

C C

DDR_CKE0_DIMMA10,20

DDR_A_BS211,20

DDR_A_BS011,20
DDR_A_WE#11,20

DDR_A_CAS#11,20
DDR_CS1_DIMMA#10,20

M_ODT110,20

B B

MEM_SDATA17
MEM_SCLK17

+3.3V_RUN

A A

Non-iAMT

<Variant Name>

SMbus address A0

PROJECT:

+1.8V_SUS +1.8V_SUS

DDR_A_D5
DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D1
DDR_A_D3

DDR_A_D15
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11
DDR_A_D10

DDR_A_D16
DDR_A_D21

DDR_A_DQS#2

DDR_A_D19
DDR_A_D22

DDR_A_D25
DDR_A_D27

DDR_A_DM3

DDR_A_D31
DDR_A_D24

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_WE#
DDR_A_CAS#

M_ODT1

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D40

DDR_A_D47
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D54

DDR_A_D56
DDR_A_D60

DDR_A_DM7
DDR_A_D61

DDR_A_D59

MEM_SDATA
MEM_SCLK

5

V_DDR_MCH_REF

Lanai

TOP

CON14

1

VREF

VSS46

3

VSS47

DQ4

5

DQ0

DQ5

7

DQ1

VSS15

9

VSS37

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201 202

DM0

DQS#0

VSS5

DQS0

DQ6

VSS48

DQ7

DQ2

VSS16

DQ3

DQ12

VSS38

DQ13

DQ8

VSS17

DQ9

DM1

VSS49

VSS53

DQS#1

CK0

DQS1

CK0#

VSS39

VSS41

DQ10

DQ14

DQ11

DQ15

VSS50

VSS54

VSS18

VSS20

DQ16

DQ20

DQ17

DQ21

VSS1

VSS6

DQS#2

NC3

DQS2

DM2

VSS19

VSS21

DQ18

DQ22

DQ19

DQ23

VSS22

VSS24

DQ24

DQ28

DQ25

DQ29

VSS23

VSS25

DM3

DQS#3

NC4

DQS3

VSS9

VSS10

DQ26

DQ30

DQ27

DQ31

VSS4

VSS8

CKE0

CKE1

VDD7

VDD8

NC1

A15

A16_BA2

A14

VDD9

VDD11

A12

A11

A9

A7

A8

A6

VDD5

VDD4

A5

A4

A3

A2

A1

A0

VDD10

VDD12

A10/AP

BA1

BA0

RAS#

WE#

S0#

VDD2

VDD1

CAS#

ODT0

S1#

A13

VDD3

VDD6

ODT1

NC2

VSS11

VSS12

DQ32

DQ36

DQ33

DQ37

VSS26

VSS28

DQS#4

DM4

DQS4

VSS42

VSS2

DQ38

DQ34

DQ39

DQ35

VSS55

VSS27

DQ44

DQ40

DQ45

DQ41

VSS43

VSS29

DQS#5

DM5

DQS5

VSS51

VSS56

DQ42

DQ46

DQ43

DQ47

VSS40

VSS44

DQ48

DQ52

DQ49

DQ53

VSS52

VSS57

NCTEST

CK1

VSS30

CK1#

DQS#6

VSS45

DQS6

DM6

VSS31

VSS32

DQ50

DQ54

DQ51

DQ55

VSS33

VSS35

DQ56

DQ60

DQ57

DQ61

VSS3

VSS7

DM7

DQS#7

VSS34

DQS7

DQ58

VSS36

DQ59

DQ62

VSS14

DQ63

SDA

VSS13

SCL

SA0

VDDSPD

SA1

GND0 GND1

NP_NC2NP_NC1

STD

FOXCONN/AS0A426-N2SN-7F

CLOCK 0 , 1
CKE 0 , 1

REVISION

1.2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

204203

DATE:
SHEET OF

4

+1.8V_SUS

DDR_A_D4
DDR_A_D6

DDR_A_DM0
DDR_A_D2

DDR_A_D7
DDR_A_D8

DDR_A_D12
DDR_A_DM1

M_CLK_DDR0 10
M_CLK_DDR#0 10

DDR_A_D14
DDR_A_D13

DDR_A_D17
DDR_A_D20

PM_EXTTS#0
DDR_A_DM2DDR_A_DQS2

DDR_A_D18
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D26

DDR_A_MA14 DDR_B_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1

DDR_A_RAS#DDR_A_BS0

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D38

DDR_A_DM4
DDR_A_D37

DDR_A_D35DDR_A_D39
DDR_A_D45

DDR_A_D44

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D41
DDR_A_D46

DDR_A_D53
DDR_A_D52

DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D58

DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D63
DDR_A_D62

R505
10KOhm

5%

12

PM_EXTTS#0 10

DDR_CKE1_DIMMA 10,20

DDR_A_BS1 11,20
DDR_A_RAS# 11,20

DDR_CS0_DIMMA# 10,20

M_ODT0 10,20

M_CLK_DDR1 10
M_CLK_DDR#1 10

R501
10KOhm

5%

12

Monday, March 19, 2007

19 69

4

DDR_A_DM[0..7] 11
DDR_A_D[0..63] 11
DDR_A_DQS[0..7] 11
DDR_A_DQS#[0..7] 11
DDR_A_MA[0..14] 10,11,20

V_DDR_MCH_REF

MLCC/+80-20%

12

C280

0.1UF/10V

+3.3V_RUN

MLCC/+/-10%

12

C373

2.2UF/6.3V

pt_c0805_h53

MLCC/+/-10%

12

C278

2.2UF/6.3V

pt_c0805_h53

Non-iAMT

MLCC/+80-20%

12

C374

0.1UF/10V

Non-iAMT

DESCRIPTION:

DDR_CKE2_DIMMB10,20

DDR_B_BS211,20

DDR_B_BS011,20
DDR_B_WE#11,20

DDR_B_CAS#11,20 M_ODT2 10,20
DDR_CS3_DIMMB#10,20

M_ODT310,20

DDR2 SO-DIMM (0)

3

V_DDR_MCH_REF

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D2

DDR_B_D9
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D14

DDR_B_D20
DDR_B_D16

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D25
DDR_B_D28

DDR_B_DM3

DDR_B_D27
DDR_B_D30

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#

M_ODT3

DDR_B_D38
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D33

DDR_B_D45
DDR_B_D46

DDR_B_DM5
DDR_B_D44

DDR_B_D42 DDR_B_D43
DDR_B_D53

DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D54

DDR_B_D56
DDR_B_D62

DDR_B_DM7
DDR_B_D63

DDR_B_D60
MEM_SDATA

MEM_SCLK

+3.3V_RUN

SMbus address A4

3

BOT

CON15

1

VREF

VSS46

3

VSS47

DQ4

5

DQ0

DQ5

7

DQ1

VSS15

9

VSS37

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201 202

DM0

DQS#0

VSS5

DQS0

DQ6

VSS48

DQ7

DQ2

VSS16

DQ3

DQ12

VSS38

DQ13

DQ8

VSS17

DQ9

DM1

VSS49

VSS53

DQS#1

CK0

DQS1

CK0#

VSS39

VSS41

DQ10

DQ14

DQ11

DQ15

VSS50

VSS54

VSS18

VSS20

DQ16

DQ20

DQ17

DQ21

VSS1

VSS6

DQS#2

NC3

DQS2

DM2

VSS19

VSS21

DQ18

DQ22

DQ19

DQ23

VSS22

VSS24

DQ24

DQ28

DQ25

DQ29

VSS23

VSS25

DM3

DQS#3

NC4

DQS3

VSS9

VSS10

DQ26

DQ30

DQ27

DQ31

VSS4

VSS8

CKE0

CKE1

VDD7

VDD8

NC1

A15

A16_BA2

A14

VDD9

VDD11

A12

A11

A9

A7

A8

A6

VDD5

VDD4

A5

A4

A3

A2

A1

A0

VDD10

VDD12

A10/AP

BA1

BA0

RAS#

WE#

S0#

VDD2

VDD1

CAS#

ODT0

S1#

A13

VDD3

VDD6

ODT1

NC2

VSS11

VSS12

DQ32

DQ36

DQ33

DQ37

VSS26

VSS28

DQS#4

DM4

DQS4

VSS42

VSS2

DQ38

DQ34

DQ39

DQ35

VSS55

VSS27

DQ44

DQ40

DQ45

DQ41

VSS43

VSS29

DQS#5

DM5

DQS5

VSS51

VSS56

DQ42

DQ46

DQ43

DQ47

VSS40

VSS44

DQ48

DQ52

DQ49

DQ53

VSS52

VSS57

NCTEST

CK1

VSS30

CK1#

DQS#6

VSS45

DQS6

DM6

VSS31

VSS32

DQ50

DQ54

DQ51

DQ55

VSS33

VSS35

DQ56

DQ60

DQ57

DQ61

VSS3

VSS7

DM7

DQS#7

VSS34

DQS7

DQ58

VSS36

DQ59

DQ62

VSS14

DQ63

SDA

VSS13

SCL

SA0

VDDSPD

SA1

GND0 GND1

NP_NC2NP_NC1

STD

FOXCONN/AS0A426-NASN-7F

CLOCK 2 , 3
CKE 2 , 3

RELEASE DATE :

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

204203

2

+1.8V_SUS

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D12
DDR_B_DM1

DDR_B_D11
DDR_B_D15

DDR_B_D21
DDR_B_D23

PM_EXTTS#1
DDR_B_DM2

DDR_B_D22
DDR_B_D17

DDR_B_D29
DDR_B_D31

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D24
DDR_B_D26

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#

M_ODT2
DDR_B_MA13

DDR_B_D35
DDR_B_D32

DDR_B_DM4
DDR_B_D39

DDR_B_D37
DDR_B_D40

DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47

DDR_B_D52
DDR_B_D49

DDR_B_DM6
DDR_B_D55

DDR_B_D50
DDR_B_D57

DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D58
DDR_B_D59

<OrgName>

2

M_CLK_DDR2 10
M_CLK_DDR#2 10

PM_EXTTS#1 10

DDR_CKE3_DIMMB 10,20

DDR_B_BS1 11,20
DDR_B_RAS# 11,20

DDR_CS2_DIMMB# 10,20

M_CLK_DDR3 10
M_CLK_DDR#3 10

R212
10KOhm

5%

12

DDR_B_DM[0..7] 11
DDR_B_D[0..63] 11
DDR_B_DQS[0..7] 11
DDR_B_DQS#[0..7] 11
DDR_B_MA[0..14] 10,11,20

V_DDR_MCH_REF

Non-iAMT

+3.3V_RUN

R211

12

10KOhm

5%

DESIGN ENGINEER :SCHEMATIC FILE NAME :

MLCC/+80-20%

12

C281

0.1UF/10V

+1.8V_SUS

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

+1.8V_SUS

0.1UF/10V

MLCC/+80-20%

+1.8V_SUS

0.1UF/10V

MLCC/+80-20%

+3.3V_RUN

MLCC/+/-10%

2.2UF/6.3V

pt_c0805_h53

12

C651

12

C327

12

C321

12

C315

12

C340

MLCC/+/-10%

STANLY_HSU

1

12

C275

2.2UF/6.3V

pt_c0805_h53

Please these Caps near So-Dimm1.

12

C300

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C333

12

C341

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Please these Caps near So-Dimm2.

12

C591

12

C331

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C619

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

Please these Caps near So-Dimm1.

12

C325

0.1UF/10V

MLCC/+80-20%

0.1UF/10V

MLCC/+80-20%

C319

C323

0.1UF/10V

MLCC/+80-20%

12

12

Please these Caps near So-Dimm2.

12

C609

12

C616

0.1UF/10V

MLCC/+80-20%

12

C601

0.1UF/10V

MLCC/+80-20%

0.1UF/10V

MLCC/+80-20%

Non-iAMT

MLCC/+80-20%

12

C647

0.1UF/10V

1

12

C342

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

12

C317

2.2UF/6.3V

MLCC/+/-10%
pt_c0603

5

4

3

2

1

D D

+0.9V_DDR_VTT

12

C326

0.1UF/10V

MLCC/+80-20%

+0.9V_DDR_VTT

12

C332

0.1UF/10V

MLCC/+80-20%

C C

DDR_A_BS111,19

DDR_A_RAS#11,19

B B

Please these resistor
closely DIMMA, all
trace length<750 mil.

A A

DDR_A_BS211,19

DDR_A_BS011,19

DDR_A_WE#11,19
DDR_A_CAS#11,19

M_ODT010,19 M_ODT2 10,19
M_ODT110,19

DDR_CS0_DIMMA#10,19
DDR_CS1_DIMMA#10,19
DDR_CKE0_DIMMA10,19
DDR_CKE1_DIMMA10,19

Layout note : Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

12

12

12

12

DDR_A_MA[0..14]10,11,19 DDR_B_MA[0..14] 10,11,19

C305

C361

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

12

C355

C309

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

DDR_A_MA6
DDR_A_MA7

DDR_A_MA0
DDR_A_BS1

DDR_A_RAS#
DDR_A_MA13

DDR_A_MA4
DDR_A_MA2

DDR_A_MA3
DDR_A_MA5

DDR_A_MA9
DDR_A_MA12

DDR_A_BS2
DDR_A_MA8

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_B_MA4
DDR_B_MA5

M_ODT0 M_ODT2
DDR_A_MA1

C344

0.1UF/10V

MLCC/+80-20%

12

C338

0.1UF/10V

MLCC/+80-20%

RN21A
RN21B

RN25A
RN25B

RN27A
RN27B

RN23A
RN23B

RN18A
RN18B

RN16A
RN16B

RN17A
RN17B

RN32A
RN32B

RN31A
RN31B

RN26A
RN26B

R186 56Ohm5%
R194 56Ohm5%
R190 56Ohm5%
R188 56Ohm5%
R195 56Ohm5%
R181 56Ohm5%
R175 56Ohm5%

12

C359

0.1UF/10V

MLCC/+80-20%

12

C299

0.1UF/10V

MLCC/+80-20%

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

56Ohm

5%

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12

56Ohm

34

5%

56Ohm

12
12
12
12
12
12
12

12

C314

0.1UF/10V

MLCC/+80-20%

12

C303

0.1UF/10V

MLCC/+80-20%

+0.9V_DDR_VTT

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

TOP

12

12

C358

C356

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

BOT

12

12

C306

C347

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

RN20A

12

56Ohm

RN20B

34

5%

56Ohm

RN15A

12

56Ohm

RN15B

34

5%

56Ohm

RN34A

12

56Ohm

RN34B

34

5%

56Ohm

RN29A

12

56Ohm

RN29B

34

56Ohm

5%

RN19A

12

56Ohm

RN19B

34

5%

56Ohm

RN28A

12

56Ohm

RN28B

34

5%

56Ohm

RN33A

12

56Ohm

RN33B

34

5%

56Ohm

RN22A

12

56Ohm

RN22B

34

5%

56Ohm

RN30A

12

56Ohm

RN30B

34

5%

56Ohm

RN24A

12

56Ohm

RN24B

34

56Ohm

5%

R191 56Ohm5%

12

R189 56Ohm5%

12

R182 56Ohm5%

12

R192 56Ohm5%

12

R193 56Ohm

12

R174 56Ohm

12

R178 56Ohm5%

12

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%
5%

12

C316

0.1UF/10V

MLCC/+80-20%

12

C360

0.1UF/10V

MLCC/+80-20%

DDR_B_MA6
DDR_B_MA7

DDR_B_MA14
DDR_B_MA11

DDR_B_BS1
DDR_B_MA0

DDR_B_MA13
DDR_B_RAS#

DDR_A_MA11
DDR_A_MA14

DDR_B_MA3
DDR_B_MA1

DDR_B_WE#
DDR_B_BS0

DDR_B_MA9
DDR_B_MA12

DDR_B_MA10
DDR_B_CAS#

DDR_B_MA2
DDR_B_MA8

12

C324

0.1UF/10V

MLCC/+80-20%

12

C320

0.1UF/10V

MLCC/+80-20%

DDR_B_BS1 11,19

DDR_B_RAS# 11,19

DDR_B_WE# 11,19
DDR_B_BS0 11,19

DDR_B_CAS# 11,19

M_ODT3 10,19
DDR_B_BS2 11,19
DDR_CS2_DIMMB# 10,19
DDR_CS3_DIMMB# 10,19
DDR_CKE2_DIMMB 10,19
DDR_CKE3_DIMMB 10,19

12

C328

0.1UF/10V

MLCC/+80-20%

12

C343

0.1UF/10V

MLCC/+80-20%

12

12

C348

C304

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

12

12

C354

C337

0.1UF/10V

0.1UF/10V

MLCC/+80-20%

MLCC/+80-20%

Please these resistor
closely DIMMB, all
trace length<750 mil.

<Variant Name>

PROJECT:

5

Lanai

REVISION

1.2

Monday, March 19, 2007

DATE:
SHEET OF

20 69

4

DESCRIPTION:

DDR2 SO-DIMM (1)

3

RELEASE DATE :

<OrgName>

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

STANLY_HSU

1