Datasheet VT83205S1, VT83205S1X, VT83205QX, VT83205Q, VT83205-D Datasheet (Vaishali Semiconductor)
Page 1
C
VT83205
3.3V Low Phase Noise VCXO
(Voltage-Controlled Crystal Oscillator)
and PLL Clock Synthesizer
Applications
•= Telecom switching
•= Set-top boxes
General Description
The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer.
The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz,
30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V
control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs SO:S2
are used for frequency and output selection.
Features
•= 3.3V supply operation
•= Packaged in 16-pin SOIC & QSOP packages.
•= Replaces separate VCXO and multiplier
•= Uses inexpensive pullable crystal
•= HDTV
•= MPEG Video clock source
•= On-chip VCXO with 200 ppm pull range (±100
ppm)
•= 5V-tolerant control inputs
•= Zero ppm synthesis error in both clocks
Figure 1. Functional Block Diagram
10-14 MHz
Pullable
Crystal
VIN
X2
X1
Load Cap Control
Load
Caps
VDD1 VDD2
osc
Low
Phase
Noise
PLL
Output
Buffer
Output
Buffer
LK1
CLK2
2001-03-08 Page 1 MDST-0001-01
Vaishali Semiconductor 1300 White Oaks Road, Ste. 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
S2:S0
www.vaishali.com
OE
Page 2
VT83205
Figure 2. Pin Configuration
VT83205 Pinout
X1
V
DD
V
DD
VIN
GND
GND
OE
S2
1
2
1
3
1
4
5
6
7
8
16
15
14
13
12
11
10
X2
NC
S1
GND
CLK2
VDD2
S0
9
CLK1
Table 1. Pin Description
Name Pin # Type Description
X1 1 XI Crystal connection. Connect to a pullable crystal of 10–14.318 MHz
VDD1 2,3 P Core VDD. Connect to 3.3V
VIN 4 I Voltage input to VCXO. Zero to 3V signal controls the frequency of the VCXO.
GND 5,6,13 P Connect to ground.
S2 7 I Select input #2. Selects outputs per Table 2
OE 8 I Active HIGH Output enable . Outputs in Hi-Z state when LOW
CLK1 9 O Clock output #1 per Table 2.
SO 10 I Select input #0. Selects output per Table 2
VDD2 11 P Output VDD. Connect to 3.3V
CLK2 12 O Clock output #2 per Table 2
S1 14 I Select input #1. Selects outputs per Table 2
NC 15 - There is no internal connection to this pin.
X2 16 XO Crystal connection. Connect to a pullable crystal of 10 MHz – 14.318 MHz.
Legend: I = Input
O = Output
P = Power supply connection
XI, XO = Crystal connections.
Table 2. Pullable Crystal Specifications
Parameter Value
Correlation (load) capacitance 30 pF
C0/C1 240 max
ESR
Operating Temperature
Initial Accuracy ±20 ppm
Temperature + Aging Stability ±50 ppm
2001-03-08 Page 2 MDST-0001-01
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Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
35 Ω max
0°C to +70°C
Page 3
VT83205
Table 3 Clock Selection Table (OE = High)
S2 S1 S0 CLK1 CLK2
0 0 0 REF/4 REF/2
0 0 M
(1)
OFF X 0.666
0 0 1 OFF X 2.6666
0 1 0 OFF X 4
0 1 M
(1)
OFF X 1.5
0 1 1 OFF X 1.3333
1 0 0 Test Test
1 0 M
(1)
OFF X 4
1 0 1 OFF X 2
1 1 0 OFF X 3
1 1 M
(1)
OFF X 5
1 1 1 OFF X 6
Note:
1. SO has three valid states: 0 = VIN ≤ 0.5V
≥ V
1 = V
IN
M = 0.5V
– 0.5
DD
< VIN < VDD – 0.5V
Table 4 Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Supply voltage, VDD Referenced to GND 5 V
Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V
Soldering Temperature Max of 10 seconds 260 °C
Storage temperature -65 150 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only and correct functional operation of the device at these or any
other conditions above those listed in the operational sections of the specifications is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect product reliability.
Table 5 Operating Conditions
Parameter Conditions Min Typ Max Units
Operating Voltage, VDD 3.15 3.3 3.45 V
Input High Voltage, VIH, X1 pin only 2.5 V
Input Low Voltage, VIL, X1 pin only 0.4 V
Input High Voltage, VIH, binary inputs S2, S1, OE 2 V
Input Low Voltage, VIL, binary inputs S2, S1, OE 0.8 V
Input High Voltage, VIH, trinary input S0 VDD-0.5 V
Input Low Voltage, VIL, trinary input S0 0.5 V
Operating Temperature 0 70 °C
VCXO control voltage, VIN 0 3 V
2001-03-08 Page 3 MDST-0001-01
www.vaishali.com
Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Page 4
VT83205
Table 6. DC Electrical Characteristics
T
= 0°C to +70°C, V
A
Parameter Condition Min Typ
Output High Voltage, VOH I
Output Low Voltage, VOL I
= 3.15 V to 3.45 V
DD
(1)
Max Units
=-25mA 2.4 V
OH
=25mA 0.4 V
OL
Operating Supply Current, IDD No Load 38 mA
Short Circuit Current Each output ±85 mA
Input Capacitance S2:0, OE 7 pF
Note:
1. Typical values are at V
= 3.3V and 25°C
DD
Table 7. AC Electrical Characteristics
T
= 0°C to +70°C, V
A
= 3.15 V to 3.45 V
DD
Symbol Parameter Condition Min Typ Max Units
Fosc Input Crystal Frequency 10 14.318 MHz
Tr Output Clock Rise Time 0.8 to 2.0V 1.5 ns
tf Output Clock Fall Time 2.0 to 0.8V 1.5 ns
tod Output Clock Duty Cycle At VDD/2 40 60 %
tpZL, tpZH Enable Time. OE to CLK CL = 50pf 5 6.5 ns
tpLZ, tpHZ Disable Time. OE to CLK CL = 50pf 4 5.5 ns
t
(pk-pk) Maximum Absolute Jitter
jit
±100 ps
(Peak to Peak)
Phase Noise, relative to carrier 10 KHz offset -115 dBc/Hz
Output pullability 0V <VIN <3V ±100 ppm
Note:
1. Typical values are at V
= 3.3V and 25°C
DD
Figure 3. External Crystal Connection Block Diagram
10-14MHz
Pullable Crystal
20pF
33pF
)
(C
X2
C
External Crystal
External
Load Capacitors
20pF
33pF
C
C
X2
X2
XTAL OSC
XTAL OSC
X1
X1
X1
PLL
PLL
CLOCK
CLOCK
GEN
Clk 1
Clk 2
OE
Ordering Information
Part Number Marking Shipping/Packaging No. of Pins Package Temperature
VT83205Q VT83205Q Tubes 16 QSOP
VT83205QX VT83205Q Tape & Reel 16 QSOP
VT83205S1 VT83205S1 Tubes 16 SOIC
VT83205S1X VT83205S1 Tape & Reel 16 SOIC
VT83205/D Die
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
2001-03-08 Page 4 MDST-0001-01
www.vaishali.com
Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
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