TABLE OF CONTENTS..................................................................................................................................................................II
LIST OF FIGURES..........................................................................................................................................................................IV
LIST OF TABLES...........................................................................................................................................................................IV
Super-I/O Configuration Index / Data Registers...............................................................................................................45
Floppy Disk Controller Registers.......................................................................................................................................................... 48
Parallel Port Registers........................................................................................................ ................................................................... 49
Serial Port 1 Registers........................................................................................................................................................................... 50
Serial Port 2 Registers........................................................................................................................................................................... 51
SoundBlaster Pro Port Registers.........................................................................................................................................52
FM Registers......................................................................................................................................................................................... 52
Game Port Registers............................................................................................................................................................. 53
PCI Configuration Space I/O...............................................................................................................................................54
Function 0 Registers - PCI to ISA Bridge...........................................................................................................................55
PCI Configuration Space Header.......................................................................................................................................................... 55
ISA Bus Control.................................................................................................................................................................................... 55
Plug and Play Control........................................................................................................................................................................... 59
Distributed DMA / Serial IRQ Control.................................................................................................................................................61
Miscellaneous / General Purpose I/O....................................................................................................................................................62
Function 1 Registers - Enhanced IDE Controller..............................................................................................................68
PCI Configuration Space Header.......................................................................................................................................................... 68
IDE I/O Registers.................................................................................................................................................................................. 75
Function 2 Registers - USB Controller Ports 0-1...............................................................................................................76
PCI Configuration Space Header.......................................................................................................................................................... 76
USB I/O Registers................................................................................................................................................................................. 78
Function 3 Registers - USB Controller Ports 2-3...............................................................................................................79
PCI Configuration Space Header.......................................................................................................................................................... 79
USB I/O Registers................................................................................................................................................................................. 81
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VT82C686A
Function 4 Regs - Power Management, SMBus and HWM..............................................................................................82
PCI Configuration Space Header.......................................................................................................................................................... 82
Power Management-Specific PCI Configuration Registers .................................................................................................................. 83
System Management Bus-Specific Configuration Registers................................................................................................................. 90
Power Management I/O-Space Registers ..............................................................................................................................................91
System Management Bus I/O-Space Registers.................................................................................................................................... 100
Hardware Monitor I/O Space Registers .............................................................................................................................................. 103
PCI Configuration Space Header – Function 5 Audio........................................................................................................................ 107
PCI Configuration Space Header – Function 6 Modem...................................................................................................................... 108
Function 5 & 6 Codec-Specific Configuration Registers.................................................................................................................... 109
I/O Base 0 Registers –Audio/Modem Scatter/Gather DMA................................................................................................................ 111
I/O Base 1 Registers – Audio FM NMI Status Registers.................................................................................................................... 115
I/O Base 2 Registers – MIDI / Game Port........................................................................................................................................... 115
Power Management Subsystem Overview.......................................................................................................................................... 118
Processor Bus States........................................................................................................................................................................... 118
System Suspend States and Power Plane Control............................................................................................................................... 119
General Purpose I/O Ports...................................................................................................................................................................119
Power Management Events................................................................................................................................................................. 120
System and Processor Resume Events................................................................................................................................................ 120
Legacy Power Management Timers.................................................................................................................................................... 121
System Primary and Secondary Events............................................................................................................................................... 121
TABLE 2. SYSTEM I/O MAP.......................................................................................................................................................27
•Inter-operable with VIA and other Host-to-PCI Bridges
−
Combine with VT82C598 for a complete Super-7 (66/75/83/100MHz) PCI / AGP / ISA system (Apollo MVP3)
−
Combine with VT8501 for a complete Super-7 system with integrated 2D / 3D graphics (Apollo MVP4)
−
Combine with VT82C693 for a complete 66 / 100 / 133 MHz Socket-370 or Slot-1 system (Apollo Pro133)
−
Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket-370 or Slot-1 system with integrated 2D / 3D
graphics (Apollo ProMedia)
−
Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI / AGP / ISA system
•PCI to ISA Bridge
−
Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller
−
Integrated Keyboard Controller with PS2 mouse support
−
Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
−
Integrated USB Controller with root hub and four function ports
−
Integrated UltraDMA-33/66 master mode EIDE controller with enhanced PCI bus commands
−
PCI-2.2 compliant with delay transaction and remote power management
−
Eight double-word line buffer between PCI and ISA bus
−
One level of PCI to ISA post-write buffer
−
Supports type F DMA transfers
−
Distributed DMA support for ISA legacy DMA across the PCI bus
−
Serial interrupt for docking and non-docking applica tions
−
Fast reset and Gate A20 operation
−
Edge trigger or level sensitive interrupt
−
Flash EPROM, 4Mb EPROM and combined BIOS support
−
Supports positive and subtractive decoding
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•UltraDMA-33 / 66 Master Mode PCI EIDE Controller
−
Dual channel master mode PCI supporting four Enhanced IDE devices
−
Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface
−
Increased reliability using UltraDMA-66 transfer protocols
−
Thirty-two levels (doublewords) of prefetch and write buffers
−
Dual DMA engine for concurrent dual channel operatio n
−
Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
−
Full scatter gather capability
−
Support ATAPI compliant devices including DVD devices
−
Support PCI native and ATA compatibility modes
−
Complete software driver support
•Integrated Super IO Controller
−
Supports 2 serial ports, IR port, parallel port, and floppy disk controller functions
−
Two UARTs for Complete Serial Ports
Programmable character lengths (5,6,7,8)
Even, odd, stick or no parity bit generation and detection
Programmable baud rate generator
High speed baud rate (230Kbps, 460Kbps) support
Independent transmit/receiver FIFOs
Modem Control
Plug and play with 96 base IO address and 12 IRQ options
−
Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR port multiplexed on COM2
−
Multi-mode parallel port
Standard mode, ECP and EPP support
Plug and play with 192 base IO address, 12 IRQ and 4 DMA options
−
Floppy Disk Controller
16 bytes of FIFO
Data rates up to 1Mbps
Perpendicular recording driver support
Two FDDs with drive swap support
Plug and play with 48 base IO address, 12 IRQ and 4 DMA options
VT82C686A
•SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller
−
Dual full-duplex Direct Sound channels between system memory and AC97 link
−
PCI master interface with scatter / gather and bursting capability
−
32 byte FIFO of each direct sound channel
−
Host based sample rate co nverter and mixer
−
Standard v1.0 or v2.0 AC97 Codec interface for single or cascaded AC97 Codec’s from multiple vendors
−
Loopback capability for re-directing mixed audio streams into USB and 1394 speakers
−
Hardware SoundBlaster Pro for Windows DOS box and real-mode DOS legacy compatibility
−
Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware
−
Hardware assisted FM synthesis for legacy compatibility
−
Direct two game ports and one MIDI port interface
−
Complete software driver support for Windows-95/98/2000 and Windows-NT
•Voltage, Temperature, Fan Speed Monitor and Controller
−
Five positive voltage (one internal), three temperature (one internal) and two fan-speed monitoring
−
Programmable control, status, monitor and alarm for flexible desktop management
−
External thermister or internal bandgap temperature sensing
−
Automatic clock throttling with integrated temperature sensing
−
Internal core VCC voltage sensing
−
Flexible external voltage sensing arrangement (any positive supply and battery)
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•Universal Serial Bus Controller
−
USB v.1.1 and Intel Universal HCI v.1.1 compatible
−
Eighteen level (doublewords) data FIFO with full scatter and gather capability
−
Root hub and four function ports
−
Integrated physical layer transceivers with optional over-current detection status on USB inputs
−
Legacy keyboard and PS/2 mouse support
•System Management Bus Interface
−
Host interface for processor communications
−
Slave interface for external SMBus masters
•Sophisticated PC99-Compatible Mobile Power Management
−
Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
−
ACPI v1.0 Compliant
−
APM v1.2 Compli ant
−
CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
−
PCI bus cloc k run, Power Management Enable (PME) control, and PCI/CPU clock generator sto p control
−
Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
−
Multiple suspend power plane controls and suspend status indicators
−
One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
−
Normal, doze, sleep, suspend and conserve modes
−
Global and local device power control
−
System event monitoring with two event classes
−
Primary and secondary interrupt differentiation for individual channels
−
Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for
system wake-up
−
Up to 12 general purpose input ports and 23 output ports
−
Multiple internal and external SMI sources for flexible power management models
−
One programmable chip select and one microcontroller chip select
−
Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
−
Thermal alarm on either external or any combination of three internal temperature sensing circuits
The VT82C686A PSIPC (PCI Super-I/O Integrated Peripheral Controller) is a high integration, high performance, power-efficient,
and high compatibility device that supports Intel and non-Intel based processor to PCI bus bridge functionality to make a complete
Microsoft PC99-compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C686A includes
standard intelligent peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT82C686A also supports the UltraDMA-33 standard to
allow reliable data transfer rates up to 33MB /sec throughput. The VT 82C686A also supports the UltraDMA-66 standard.
The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.
b) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT82C686A includes the root hub
with four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and
isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy
keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system
environment.
c) Keyboard controller with PS2 mouse support.
d) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also
includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
e) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states
(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional
functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI b us clock sto p co ntrol,
modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip
select and external SMI.
f) Hardware monitoring subs yste m for managing system / motherboard voltage levels, temperatures, and fan speeds
g) Full System Management Bus (SMBus) interface.
h) Two 16550-compatible serial I/O ports with infrared communications port option on the second port.
i) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro and
hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is
also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.
j) Two game ports and one MIDI port
k) ECP/EPP-capable parallel port
l) Standard floppy disk drive interface
m) Distributed DMA capability for support of ISA legacy DMA over the PCI bus. Serial IRQ is also supported for docking and
non-docking ap plications.
n) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to any
interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-
board peripherals for Windows family compliance.
o) Internal I/O APIC (Advanced Programmable Interrupt Controller)
VT82C686A
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VT82C686A
The VT82C686A also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both
edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to
standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT82C686A supports delayed transactions and remote
power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow
concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels
(doublewords) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.
CPU / Cache
Sideband Signals:
Init / CPUreset
IRQ / NMI
SMI / StopClk
FERR / IGNNE
SLP# (Slot-1)
Boot ROM
Expansion
Cards
RTC
Crystal
ISA
CA
CD
North Bridge
VT82C686A
352 BGA
MA/Command
MD
PCI
SMB
USB Ports 0-3
Keyboard / Mouse
MIDI / Game Ports
Parallel Port
Serial Port s 1 and 2
Infrared Comm Port
IDE Primary and Secondary
Floppy Disk Interface
AC97 Lin k
Hardware Monitor Inputs
GPIO, Power Control, Reset
System Memory
DIMM Module ID
Expansion
Figure 1. PC System Configuration Using the VT82C686A
Cards
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P
INOUTS
VT82C686A
Pin Diagram
Figure 2. VT82C686A Ball Diagram (Top View)
Key1234567891011121314151617181920
R
P3-
W
DS
CTS
DATA#
DS0#DTR2#RXD2RTS1#RXD
MTR1#RI2#DSR2#CTS1#DSR
DIR#
TRK
STEP#
00#
GNDUVCC
GPO0SMB
GPIODSMB
FERR#
CPU
RST#
INTR
CLK#
A20M#IGN
NE#
DCD
DRV
DEN0
MTR0#RTS2#RI1#IR
VCC GND VCC VCC VCC GND
U
VCCSVCC
DATA
CLK
SUSA#SUS
ST1#
SUSB#SMB
ALRT#
SUSC#EXT
SMI#
TXD
DCD
TXD2DTR1#IR
S
SUS
THRM
CLK
PME#
LID
LOW#
RING#
IRQ8#
BTN#
RX
TX
VCCHGND
VCC
FAN
BAT
FAN2V
PCI
STP#VSENS2
PCK
RUN#TSENS1VSENS3
PWR
CPU
STP#TSENS2VSENS4
1#
PD
PD
ERR#
ACK#
1
BUSY
SLCT
VREF
1
SENS1
PD3PD0PCI
PD4P
PD5PD1STR
PE
PD6SLCT
VCC GND
H
GPIOASDD10
SDD7
JBX
GPIOCSDD9
AUTO
INIT#
OBE#
IN#PCLKAD20AD19AD18AD17
JAB2
SDD5
SDD12
ACRS
SDD3
JAX
SYNC
SDD6
SDD11
JBY
SDD8
SDD4
JAY
AD
AD
AD
PIRQ
PIRQD#AD29AD27AD
RST#
PIRQC#AD30C/BE3#ID
FD#
PIRQB#AD23AD22AD
AD16C/BE
DEV
SEL#
AD15AD14AD13AD12AD
AD10AD9AD8C/BE0#AD
AD6AD5AD4AD3AD
AD1AD
PD
CS3#PDA0PDA2PDA1
PD
RDYPDIOR#PDIOW#PDDRQ
PDD0PDD14PDD1PDD13PDD
PDD12PDD3PDD11PDD4PDD
PDD5PDD9PDD6PDD8PDD
JBB2SDCS1#SDCS3#SDA0SDA2
JAB1
SDO
FRM#
2#
STOP# SERR# PAR CBE1#
PREQ#PGNT#
0
SDD1
SDISDA1
SDD13
JBB1
SDD2
SDI2
DACK#
SDD0
BTCKSDIOR#SDIOW#
SDD14
SDD15
MSO
AD
24
SEL
21
I
RDY#TRDY#
11
7
2
PD
CS1#
PD
DACK#
PDD
15
2
10
7
SD
SD
RDY
MSISDDRQ
IOCH
USB
SMEM
A
SMEM
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AEN
W#
ROM
CS#IOW#
IOR#DACK3#DRQ3USB
DACK1#DRQ
MCS
16#SBHE#
IRQ6
SLPB
TCBALE
RST
DRVLA23LA22LA21LA20
SA19SA18IRQ10IRQ11IRQ
IRQ14DACK0#DRQ0DACK5#SD
DRQ5SD9DACK6#SD10DRQ
SD11DACK7#SD12DRQ7SD
SD14SD15SA17SA16SA15
SA14
SDD14
SA9
SDD9
SA5
SDD5
SA2
SDD2
SA0
SDD0
SD0SD1SD3SD6RTC
RFSH# OSC
1
IRQ5IRQ4IRQ3DACK
SA13
SDD13
SA8
SDD8
SA4
SDD4
SA1
SDD1
SD2SD4SD7RTCX2PWRGDSTP
USB
USB
USB
P0-
USB
USB
CLK
IOCS
16#IOCHK#
DRQ2
SIRQ
SA12
SA11
SDD12
SDD11
SA7
SA6
SDD7
SDD6
SA3
MEM
SDD3
SD5MEM
P1+MSDT
IRQ9B
KB
USB
P2-
P3+
P1-MSCK
KBCKUSB
IRQ
7
2#
CLK
15
8
6
13
SDD15
SA10
SDD10
XDIR INIT SLP#
SOE# SMI# NMI
R#
SPKR
W#
X1
WRT
DATA#WGATE#
DSK
CHG#HDSEL#
DRV
DEN1INDEX#
GND VCC
GNDG78910111213G14GND
VCCHHVCC
VCCJGND GND GND GNDJVCC
VCCKGND GND GND GNDKVCC
GNDLGND GND GND GNDLGND
VCCMGND GND GND GNDMVCC
VCCNNVCC
GNDP78910111213P14GND
GND VCC VCC
RSM
RST#
VBAT
Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but
the pin lists and pin descriptions contain all names.
Revision 1.54 February 25, 2000-6-Pinouts
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N
VCC
)
Q
J06PVCC
J09PGN
J10PGN
J
J
J
9
)
5PVCCR10PVCCS
VCC
06PGN
Q
GN
06PGN
9
9
VCCL09PGN
)
Q
GN
5PVCC
)
06PVCC
Q
)
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VT82C686A
Pin Lists
Figure 3. VT82C686A Pin List (Numerical Order)
PinPin Name PinPin NamePinPin NamePinPin NamePinPin Name
The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following cycles.
Comma n d / B y te En a b l e .
The command is driven with FRAME# assertion. Byte enables
corresponding to supplied or requested data are driven on following clocks.
Frame.
Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
Initiator Ready.
Target Ready.
Asserted by the target to request the master to stop the current transaction.
Stop.
Device Select.
Asserted when the initiator is ready for data transfer.
Asserted when the target is ready for data transfer.
The VT82C686A asserts this signal to claim PCI transactions through
positive or subtractive decoding. As an input, DEVSEL# indicates the response to a
VT82C686A-initiated transaction and is also sampled when decoding whether to
subtractively decode the cycle.
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
Parity.
System Error.
SERR# can be pulsed active by any PCI device that detects a system error
condition. Upon sampling SERR# active, the VT82C686A can be programmed to
generate an NMI to the CPU.
Initialization Device Select.
IDSEL is used as a chip select during configuration read and
write cycles. Connect this pin to AD18 using a 100 Ω resistor.
I
PCI Interrupt Request
. These pins are typically connected to the PCI bus INTA#-
This signal goes to the North Bridge to request the PCI bus.
This signal is driven by the North Bridge to grant PCI access to the
VT82C686A.
PCI Clock.
PCI Bus Clock Run.
PCLK provides timing for all transactions on the PCI Bus.
This signal indicates whether the PCI clock is or will be stopped
(high) or running ( low). The VT82 C686A drives this signal low when the PCI clock is
running (default on r eset) and releases it when it st ops the PCI clo ck. External d evices
may assert this signal low to request that the PCI clock be restarted or prevent it from
stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used.
Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for
more details.
PCI Reset.
Active low reset signal for the PCI bus. The VT82C686A will assert this pin
during power-up or from the control register.
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CPU Interface
Signal NamePin #I/OSignal Description
VT82C686A
CPURST
V8OD
CPU Reset.
The VT82C686A asserts CPURST to reset the CPU
during power-up.
INTR
W8OD
CPU Interrupt.
CPU that an interrupt request is pending and needs service.
NMI
U7OD
Non-Maskable Interrupt.
interrupt to the CPU. The VT82C686A generates an NMI when either
SERR# or IOCHK# is a sse rted.
INIT
T6OD
Initialization.
The VT82C686A asserts INIT if it detects a shut-down
special cycle on the PCI bus or if a soft reset is initiated by the register
STPCLK#
W7OD
Stop Clock.
STPCLK# is asserted by the VT82C686A to the CPU to
throttle the processor clock.
SMI#
U6OD
System Management Interrupt.
VT82C686A to the CPU in response to different Power-Management
events.
FERR#
V7I
Numerical Coprocessor Error.
error signal on the CPU. Internally generates interrupt 13 if active.
IGNNE#
Y8OD
Ignore Numeric Error.
pin on the CPU.
SLP#
/ GPO7
T7OD
(Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1
Sleep
CPUs only. Not currently used with socket-7 CPUs.
A20M#
Y7OD
A20 Mask.
Connect to A20 mask input of the CPU to control address
bit-20 generation. Logical combination of the A20GATE input (from
internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).
Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.
INTR is driven by the VT82C686A to signal the
NMI is used to force a non-maskable
SMI# is asserted by the
This signal is tied to the coprocessor
This pin is connected to the “ignore error”
Advanced Programmable Interrupt Controller (APIC)
Signal NamePin #I/OSignal Description
WSC# (CG)
APICD0 (CG)
APICD1 (CG)
/ GPI3 / LID
/ GPO1 / SUSA#
/ SUSCLK
For programming information, refer to Function 0 Rx74,77, Function 4 Rx54[3-2], and Memory Mapped / Indexed APIC registers.
U10I / I / I
V9IO / O / O
T10IO / O
Write Snoop Complete.
Asserted by the north bridge to indicate that
all snoop activity on the CPU bus initiated by the last PCI-to-DRAM
write is complete and that it is safe to perform an APIC interrupt.
Pin U10 is WSC# if Rx74[7]=1.
A3IO
B3IO
C4IO
D4IO
A4IO
B4IO
B5IO
E6IO
C3I
G5I / I / O
O / I
H3I / I / O
I / I / I
(W2)I
(Y2)I
(Y1)I
(Y3)I
M3O
N2O
USB Port 0 Data +
USB Port 0 Data USB Port 1 Data +
USB Port 1 Data USB Port 2 Data +
USB Port 2 Data USB Port 3 Data +
USB Port 3 Data USB Clock.
USB Port 0 Over Current Detect.
USB Port 1 Over Current Detect.
48MHz clock input for the USB interface
Port 0 is disabled if low.
Port 1 is disabled if this
input is low. Direct inputs are provided for overcurrent
protection for ports 0 and 1 which may be used if the alternate
functions of these two pins are not required. If overcurrent
protection is desired on all four ports ( or it is desired to use the
alternate functions of these two pins), an external buffer may be
used to drive the state of USBOC[3-0]# onto SD[3-0] during ISA
bus refresh cycles (i.e., while ISA bus RFSH# is low, so that
RFSH# may be used as the buffer enable).
USB Port 0 Over Current Detect
USB Port 1 Over Current Detect
USB Port 2 Over Current Detect
USB Port 3 Over Current Detect
USB Interrupt Request A.
USB Interrupt Request B.
Output of internal block.
Output of internal block.
System Management Bus (SMB) Interface (I2C Bus)
Signal NamePin #I/OSignal Description
SMBCLK
SMBDATA
SMBALRT#
/ GPI6
Revision 1.54 February 25, 2000-11-Pinouts
U9IO
T9IO
W10I
SMB / I2C Clock.
SMB / I2C Data.
SMB Alert.
(System Management Bus I/O space Rx08[3] = 1)
When the chip is enabled to allow it, assertion generates an IRQ
or SMI interrupt or a power management resume event. The
same pin is used as General Purpose Input 6 whose value is
reflected in Rx48[6] of function 4 I/O space
device may stop DSTROBE to pause input data transfers
EIDE Mode:
UltraDMA Mode:
Secondary I/O Channel Ready.
Secondary Device DMA Ready
device may assert DDMARDY to pause output transfers
Secondary Device Strobe
device may stop DSTROBE to pause input data transfers
EIDE Mode:
UltraDMA Mode:
Primary Device I/O Read.
Primary Host DMA Ready
The host may assert HDMARDY to pause input transfers
Primary Host Strobe
host may stop HSTROBE to pause output data transfers
EIDE Mode:
UltraDMA Mode:
Secondary Device I/O Read.
Secondary Host DMA Ready
may assert HDMARDY to pause input transfers
Host Strobe B
. Output strobe (both ed ges). The host may stop
HSTROBE to pause output data transfers
EIDE Mode:
UltraDMA Mode:
Primary Device I/O Write.
Primary Stop
. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
EIDE Mode:
UltraDMA Mode:
Secondary Device I/O Write.
Secondary Stop
. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
either the ATA command block or control block is being accessed.
Secondary Disk Address.
SDA[2:0] are used to indicate which byte in
either the ATA command block or control block is being accessed.
Primary Disk Data
Secondary Disk Data
ISA Bus Address only
muxed with ISA Bus Address (Audio Enabled)
(Audio Disabled / Dedicated Secondary IDE
Data) Note: Audio is enabled by strapping the SPKR pin high with
4.7K ohms and disabled by strapping the SPKR pin low with 4.7K ohms.
Secondary Disk Data
AC-Link/Game Ports
(SPKR strap = 0)
(SPKR strap = 1)
or
Secondary Disk Data 15 / Midi Serial In
Secondary Disk Data 14 / Midi Serial Out
Secondary Disk Data 13 / Game Port Joystick B Button 1
Secondary Disk Data 12 / Game Port Joystick B Button 2
Secondary Disk Data 11 / Game Port Joystick A Button 1
Secondary Disk Data 10 / Game Port Joystick A Button 2
Secondary Disk Data 9 / Game Port Joystick A X-axis
Secondary Disk Data 8 / Game Port Joystick A Y-axis
Secondary Disk Data 7 / Game Port Joystick B X-axis
Secondary Disk Data 6 / Game Port Joystick B Y-axis
Secondary Disk Data 5 / AC97 Reset
Secondary Disk Data 4 / AC97 Serial Data Out
Secondary Disk Data 3 / AC97 Sync
Secondary Disk Data 2 / AC97 Serial Data In 2
Secondary Disk Data 1 / AC97 Serial Data In
Secondary Disk Data 0 / AC97 Bit Clock
IDE Interrupt Request A.
IDE Interrupt Request B.
Output of internal block.
Output of internal block.
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MIDI Interface
Signal NamePin #I/OSignal Description
VT82C686A
MSI
MSO
/ SDD[15]
/ SDD[14]
Y19I / IO
Y18O / IO
MIDI Serial In
MIDI Serial Out
AC97 Audio / Modem Interface
Signal NamePin #I/OSignal Description
ACRST
SDOUT
SYNC
SDIN2
SDIN
BITCLK
AC97IRQ
MC97IRQB
/ SDD[5]
/ SDD[4]
/ SDD[3]
/ SDD[2]
/ SDD[1]
/ SDD[0]
/ DACK3#
/ DACK5#
U15O / IO
Y16O / IO
V16O / IO
Y17I / IO
V17I / IO
W18I / IO
D2O
L4O
AC97 Reset
AC97 Serial Data Out
AC97 Sync
AC97 Serial Data In 2
AC97 Serial Data In
AC97 Bit Clock
AC97 Interrupt Request.
MC97 Interrupt Request.
Game Port Interface
Signal NamePin #I/OSignal Description
/ SDD[11] / PDRQA
JAB1
/ SDD[10] / PGNTA
JAB2
/ SDD[13] / PDRQB
JBB1
/ SDD[12] / PGNTB
JBB2
/ SDD[9] / GPO23
JAX
/ SDD[8] / GPO22
JAY
/ SDD[7] / GPI23
JBX
/ SDD[6] / GPI22
JBY
See Function 0 Rx77[6]
W16I / I O / I
T15I / IO / O
W17I / I O / I
U16I / IO / O
V15I / IO / O
Y15I / IO / O
U14I / IO / I
W15I / I O / I
Joystick A Button 1
Joystick A Button 2
Joystick B Button 1
Joystick B Button 2
Joystick A X-axis
Joystick A Y-axis
Joystick B X-axis
Joystick B Y-axis
/ Secondary Disk Data 15 (SPKR strap = 1)
/ Secondary Disk Data 14 (SPKR strap = 1)
/ Secondary Disk Data 5 (SPKR strap = 1)
/ Secondary Disk Data 4 (SPKR strap = 1)
/ Secondary Disk Data 3 (SPKR strap = 1)
/ Secondary Disk Data 2 (SPKR strap = 1)
/ Secondary Disk Data 1 (SPKR strap = 1)
/ Secondary Disk Data 0 (SPKR strap = 1)
Output of internal block.
Output of internal block.
/ Secondary Disk Data 11 (SPKR strap = 1)
/ Secondary Disk Data 10 (SPKR strap = 1)
/ Secondary Disk Data 13 (SPKR strap = 1)
/ Secondary Disk Data 12 (SPKR strap = 1)
/ Secondary Disk Data 9 (SPKR strap = 1)
/ Secondary Disk Data 8 (SPKR strap = 1)
/ Secondary Disk Data 7 (SPKR strap = 1)
/ Secondary Disk Data 6 (SPKR strap = 1)
Drive Density Select 0.
Drive Density Select 1.
Motor Control 0.
Motor Control 1.
Drive Select 0.
Drive Select 1.
Direction.
Step.
Index.
Direction of head movement (0 = inward motion, 1 = outward motion)
Low pulse for each track-to-track movement of the head.
Sense to detect that the head is positioned over the beginning of a track
Head Select.
Track 0.
Sense to detect that the head is positioned over track 0.
Read Data.
Write Data.
Write Gate.
Disk Change.
Select motor on drive 0.
Select motor on drive 1
Select drive 0.
Select drive 1
Selects the side for R/W operations (0 = side 1, 1 = side 0)
Raw serial bit stream from the drive for read operatrions.
Encoded data to the drive for write operations.
Signal to the drive to enable current flow in the write head.
Sense that the drive door is open or the diskette has been changed
since the last drive selection.
Write Protect.
Sense for detection that the diskette is write protected (causes write
commands to be ignor ed)
FDC Interrupt Request.
FDC DMA Request.
Rx75[3] = 1.
Rx75[3] = 1.
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Parallel Port Interface
Signal NamePin #I/OSignal Description
VT82C686A
PINIT#
/ DIR#
STROBE#
AUTOFD#
/ nc
/ DRVEN0
C15IO / O
D16IO / -
C16IO / O
Initialize.
Strobe.
Output used to strobe data into the printer. I/O in ECP/EPP mode.
Auto Feed.
Initialize printer. Output in standard mode, I/O in ECP/EPP mode.
Output used to cause the printer to automatically feed one line after
each line is printed. I/O pin in ECP/EPP mode.
SLCTIN#
/ WGATE#
SLCT
/ DS1#
ACK#
/ STEP#
E15IO / O
E13I / O
B13I / O
Select In.
Select.
Acknowledge.
Output used to select the printer. I/O pin in ECP/EPP mode.
Status output from the printer. High indicates that it is powered on.
Status output from the printer. Low indicates that it has received
the data and is ready to accept new data
ERROR#
/ HDSEL#
A15I / O
Status output from the printer. Low indicates an error condition in the
Error.
printer.
/ MTR1#
BUSY
/ WDAT A#
PE
/ nc,
PD7
/ nc,
PD6
/ nc,
PD5
/ DSKCHG#,
PD4
/ RDATA#,
PD3
/ WRTPRT#,
PD2
/ TRK00#,
PD1
/ INDEX#
PD0
C13I / O
D13I / O
A13,
E14,
D14,
C14,
B14,
A14,
D15,
B15
IO / IO / IO / IO / I
IO / I
IO / I
IO / I
IO / I
Status output from the printer. High indicates not ready to accept data.
Busy.
Paper End.
Status output from the printer. High indicates that it is out of paper.
Parallel Port Data.
As shown by the alternate functions above, in mobile applications the parallel port pins in chip version CF and CG can optionally
be selected to function as a floppy disk interface for attachment of an external floppy drive using the parallel port connector (see
Super I/O Configuration Index F6[5]).
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Serial Ports and Infrared Interface
Signal NamePin #I/OSignal Description
TXD1
TXD2
/ GPO14
IRTX
RXD1
RXD2
/ GPO15
IRRX
RTS1#
RTS2##
CTS1#
CTS2#
DTR1#
DTR2#
DSR1#
DSR2#
DCD1#
DCD2#
RI1#
RI2#
A11O
D10O
E12O
B12I
B10I
D12IO
B11O
E10O
C11I
A9I
D11O
B9O
C12I
C10I
A12I
A10I
E11I
C9I
Transmit Data 1.
Transmit Data 2.
Infrared Transmit.
General Purpose Output 14 if Rx76[5] = 1
Receive Data 1.
Receive Data 2.
Serial port 1 receive data in.
Serial port 2 receive data in.
Infrared Receive.
Purpose Output 15 if Rx76[5] = 1
Request To Send 1.
Typically used as hardware handshake with CTS1# for low level flow control.
Designed for direct input to external RS-232C driver.
Request To Send 2.
Typically used as hardware handshake with CTS2# for low level flow control.
Designed for direct input to external RS-232C driver.
Clear To Send 1.
ready to receive data. Typically used as hardware handshake with RTS1# for low
level flow control. Designed for input from external RS-232C receiver.
Clear To Send 2.
ready to receive data. Typically used as hardware handshake with RTS2# for low
level flow control. Designed for input from external RS-232C receiver.
Data Terminal Ready 1.
and ready. Typically used as hardware handshake with DSR1# for overall
readiness to communicate. Designed for direct input to external RS-232C driver.
Data Terminal Ready 2.
and ready. Typically used as hardware handshake with DSR2# for overall
readiness to communicate. Designed for direct input to external RS-232C driver.
Data Set Ready 1.
device is powered, initialized, and ready. Typically used as hardware handshake
with DTR1# for overall readiness to communicate. Designed for direct input from
external RS-232C receiver.
Data Set Ready 2.
device is powered, initialized, and ready. Typically used as hardware handshake
with DTR2# for overall readiness to communicate. Designed for direct input from
external RS-232C receiver.
Data Carrier Detect 1.
a carrier signal (i.e., a communications channel is currently open). In direct
connect environments, this input will typically be driven by DTR1# as part of the
DTR/DSR handshake. Designed for direct input from external RS-232C receiver.
Data Carrier Detect 2.
a carrier signal (i.e., a communications channel is currently open). In direct
connect environments, this input will typically be driven by DTR2# as part of the
DTR/DSR handshake. Designed for direct input from external RS-232C receiver.
Ring Indicator 1.
ring condition. Used by software to initiate operations to answer and open the
communications channel. Designed for direct input from external RS-232C
receiver (whose input is typically not connected in direct connect environments).
Ring Indicator 2.
condition. Used by software to initiate operations to answer and open the
communications channel. Designed for direct input from external RS-232C
receiver (whose input is typically not connected in direct connect environments).
VT82C686A
Serial port 1 transmit data out.
Serial port 2 transmit data out.
IR transmit data out (Rx76[5] = 0) from serial port 2.
IR receive data in (Rx76[5] = 0) to serial port 2. General
Indicator that serial output port 1 is ready to transmit data.
Indicator that serial output port 2 is ready to transmit data.
Indicator to serial port 1 that external communications device is
Indicator to serial port 2 that external communications device is
Serial port 1 indicator that port is powered, initialized,
Serial port 2 indicator that port is powered, initialized,
Indicator to serial port 1 that external serial communications
Indicator to serial port 2 that external serial communications
Indicator to serial port 1 that external modem is detecting
Indicator to serial port 2 that external modem is detecting
Indicator to serial port 1 that external modem is detecting a
Indicator to serial port 2 that external modem is detecting a ring
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ISA Bus Interface
Signal NamePin #I/OSignal Description
VT82C686A
SA[19:16],
SA[15-0]
/
SDD[15-0]
LA[23:20]
SD[15:0]
SBHE#
IOR#
IOW#
MEMR#
MEMW#
SMEMR#
SMEMW#
BALE
IOCS16#
MCS16#
IOCHCK#
GPI0
IOCHRDY
AEN
K1, K2, P3, P4,
P5, R1, R2, R3,
R4, R5, T1, T2,
T3, T4, U1, U2,
U3, V1, V2,
W1
IO
System Address Bus
IO
SA[19-17] are also connected to LA[19-17] of the ISA bus. If the audio interface is
. SA[19-16] are connected to ISA bus SA[19-16] directly.
disabled (SPKR pin strapped low), SA[15-0] are connected directly to ISA address
bus pins SA[15-0] (the audio interface pins are used for the IDE secondary data bus).
If the audio interface is enabled (SPKR pin strapped high), SA[15-0] are multiplexed
with the IDE Secondary Data Bus. In this case, SA[15-0] may be connected to both
SDD[15-0] and ISA bus SA[15-0]. However, if ISA address bus loading is a
concern, 74F245 transceivers may be used to externally drive ISA address bus pins
SA[15-0]. In this case, these pins would connect directly to the IDE secondary data
bus and to the transceiver “A” pins and the ISA address bus would connect to the
transceiver “B” pins. SOE# would be used to control the transceiver output enables
and the ISA bus MASTER# signal would drive the transceiver direction controls.
J2, J3, J4, J5IO
System “Latched” Address Bus
: The LA[23:20] address lines are bi-directional.
These address lines allow accesses to physical memory on the ISA bus up to
16Mbytes. LA[19-17] on the ISA bus are connected to SA[19-17] (see notes above).
P2, P1, N5, N3,
N1, M4, M2,
L5, W4, Y4,
V3, W3, Y3,
W2, Y2, Y1
F2IO
IO
System Data.
SD[15:0] provide the data path for devices residing on the ISA bus.
X-Bus data signals XD[7:0] may be derived if needed from SD[7:0] using an
external 74F245-type transceiver (see the XDIR pin description for transceiver
connection details).
SD7:4 are strap options for keyboard inputs 6:3 (see Function 0 Rx5A)
System Byte High Enable.
SBHE# indicates, when asserted, that a byte is being
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
D1IO
I/O Read.
IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus.
C2IO
I/O Write.
IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus.
U4IO
Memory Read.
MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus.
V4IO
Memory Write.
MEMW# is the command to a memory slave that it may latch data
from the ISA data bus.
A1O
Standard Memory Read.
SMEMR# is the command to a memory slave, under
1MB, which indicates that it may drive data onto the ISA data bus
B1O
Standard Memory Write.
SMEMW# is the command to a memory slave, under
1MB, which indicates that it may latch data from the ISA data bus.
H2O
Bus Address Latch Enable.
BALE is an active high signal asserted by the
VT82C686A to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
F3I
16-Bit I/O Chip Select.
This signal is driven by I/O devices on the ISA Bus to
indicate that they support 16-bit I/O bus cycles.
F1I
Memory Chip Select 16.
ISA slaves that are 16-bit memory devices drive this line
low to indicate they support 16-bit memory bus cycles.
/
F4I
I/O Channel Check
(Rx74[0] = 1). When this signal is asserted, it indicates that a
parity or an uncorrectable error has occurred for an I/O or memory device on the
ISA Bus. The same pin may optionally be used as General Purpose Input 0.
A2I
I/O Channel Ready
(Rx74[0] = 1). This signal is normally high. Device s on the
ISA Bus assert IOCHRDY low to indicate that additional time (wait states) is
required to complete the cycle.
B2O
Address Enable.
AEN is asserted during DMA cycles to prevent I/O slaves from
Used to request DMA services from the internal DMA
controller.
DRQ2: Rx68[3] = 0 & Rx75[3] = 0 & Rx75[1] = 0
See also Function 0 Rx77[7]
Acknowledge.
Used by the internal DMA controller to indicate that a
request for DMA service has been granted.
DACK5#: Rx68[3] = 0
DACK2#: Rx68[3] = 0 & Rx75[3] = 0 & Rx75[2] = 0
See also Function 0 Rx77[7]
Terminal Count.
Speaker Drive.
a
strap input
Terminal count indicator asserted to DMA slaves.
Output of internal timer/counter 2. Also functions as
sampled at reset to determine the function of the Audio /
Game interface pins: 0=Disable Audio / Game interface (pins used for
IDE Secondary Data Bus SDD[15-0]; ISA SA[15-0] pins used for ISA
bus only), 1=Enable Audio / Game interface (pins used for
Audio/Game functions; SDD[15-0] multiplexed with ISA SA[15-0]
with SOE# / MASTER# as 245 OE# / DIR control.).
ISA Address (SA) Output Enable.
Asserted low when ISA address
(SA) is valid (deasserted when SDD is valid) when SA and SDD are
multiplexed on SA pins 15-0 (i.e., when SPKR is strapped low to
enable the audio interface pins). SOE# is tied directly to the output
enable of 74F245 transceivers that buffer IDE Secondary Bus data and
ISA-address (see SA pins for more information).
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XD Interface
Signal NamePin #I/O Signal Description
VT82C686A
/ PCS0# / GPO12
XDIR
T5O
X-Bus Data Direction.
memory read cycles to the programmed BIOS address space. XDIR is tied
directly to the direction control of a 74F245 transceiver that buffers the X-Bus
data and ISA-Bus data. The transceiver output enable may be grounded. SD0-7
connect to the “A” side of the transceiver and XD0-7 connect to the “B” side.
XDIR high indicates that SD0-7 drives XD0-7.
Serial IRQ
Signal NamePin #I/O Signal Description
SERIRQ
/ DRQ2
/ GPI12 / GPO24
/ FDCDRQ / USBOC1#
SERIRQ
/ DACK5#
/ GPO19 / MC97IRQ
H3I
L4I
Serial IRQ
Serial IRQ
(Rx68[3] = 1 and Rx74[6] = 0)
(Rx68[3] = 1 and Rx74[6] = 1)
(Rx76[1]=0) Asserted low for all I/O read cycles and for
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Internal Keyboard Controller
Signal NamePin #I/OSignal Description
VT82C686A
MSCK
MSDT
KBCK
KBDT
KBCS#
/ IRQ1
/ IRQ12
/ A20GATE
/ KBRC
/ ROMCS# /
KBIN[6-3]
/ SD[7-4]
strap
D5IO / I
C5I O / I
E5IO / I
A5IO / I
C1O / O / I
W4,
I / IO
Y4,
V3,
W3
MultiFunction Pin
Rx5A[1]=1
Rx5A[1]=0
MultiFunction Pin
Rx5A[1]=1
Rx5A[1]=0
MultiFunction Pin
Rx5A[0]=1
Rx5A[0]=0
MultiFunction Pin
Rx5A[0]=1
Rx5A[0]=0
(Internal mouse controller enabled by Rx5A[1])
Mouse Clock.
Interrupt Request 1
From internal mouse controller.
. Interrupt input 1.
(Internal mouse controller enabled by Rx5A[1])
Mouse Data.
Interrupt Request 12
From internal mouse controller.
. Interrupt input 12.
(Internal keyboard controller enabled by Rx5A[0])
Keyboard Clock.
Gate A20.
Input from external keyboard controller.
From internal keyboard controller
(Internal keyboard controller enabled by Rx5A[0])
Keyboard Data.
Keyboard Reset.
From internal keyboard controller.
From external keyboard controller (KBC)
for CPURST# generation
Keyboard Chip Select
Power-Up Configuration Stra p (Sampled At Reset)
(Rx5A[0]=0). To external keyboard controller chip.
:
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
Keyboard Inputs 6-3.
Sampled at reset on SD[7-4] and latched into
Rx5A[7-4].
Chip Selects
Signal NamePin #I/OSignal Description
ROMCS#
/ KBCS# /
strap
C1O / O / I
ROM Chip Select
Power-Up Configuration Stra p (Sampled At Reset)
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
/ GPO12 / XDIR
PCS0#
T5O / O / O
Programmable Chip Select 0
Rx8B[0] = 1 (CF/CG)). Asserted during I/O cycles to programmable read
or write ISA I/O port ranges. Addressed devices drive data to the SD pins
(XDIR is disabled and the X-Bus is not implemented). See also Rx59[3]
and Rx77[2].
MCCS#
(CD/CE)
/ GPIOD / GPIO11
U8O / IO / IO
Microcontroller Chip Select
Rx76[4] = 1). Asserted during read or write accesses to I/O ports 62h or
66h.
MCCS#
(CF/CG)
/ GPO13 / SOE#
U5O / IO / IO
Microcontroller Chip Select
Asserted during read or write accesses to I/O ports 62h or 66h.
(Rx5A[0]=1). Chip Select to the BIOS ROM.
:
(Rx76[1] = 1 and Rx76[4] =1 (CD/CE) or
(Rx74[5] = 1, Rx74[7] = 0, Rx76[3] = 1,
(Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).
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General Purpose Inputs
Signal NamePin #I/O Signal Description
VT82C686A
/ IOCHCK#
GPI0
/ IRQ8#
GPI1
/ BATLOW#
GPI2
/ LID / WSC#
GPI3
/ IRQ6 / SLPBTN#
GPI4
/ THRM / PME#
GPI5
/ SMBALRT#
GPI6
/ RING#
GPI7
/ GPO8 / GPIOA / GPOWE#
GPI8
/ GPO9 / GPIOB / FAN2 / DTEST
GPI9
/ GPO10 / GPIOC / CHAS / ATEST
GPI10
/ GPO11 / GPIOD
GPI11
/ GPO24 / DRQ2 / FDCDRQ
GPI12
/ USBOC1# / SERIRQ
/ GPO25 / DACK2# / FDCIRQ
GPI13
/ USBOC0#
/ DRQ0
GPI16
/ DRQ1
GPI17
/ DRQ3
GPI18
/ DRQ5
GPI19
/ DRQ6
GPI20
/ DRQ7
GPI21
/ SDD6
GPI22
/ SDD7
GPI23
GPI[23-22]
GPI[23-16]
(CF/CG)
(CF/CG)
(CF/CG)
(CF/CG)
(CF/CG)
(CF/CG)
(CF/CG)
(CF/CG)
(SD[7-6] & RFSH#
(SD[7-0] & RFSH#)
See also Function 0 Rx77[7-6]
(CF)
(CG)
F4I
W11I
U11I
U10I
G1I
T11I
W10I
V11I
T14I
U12I
V14I
U8I
H3I
G5I
L3I
E2I
D3I
M1I
M5I
N4I
W15I
U14I
n/aI
General Purpose Input 0
General Purpose Input 1
(Rx74[0] = 0)
(Rx5A[2] = 1)
General Purpose Input 2
General Purpose Input 3
General Purpose Input 4
General Purpose Input 5
(Read pin state at PMU IO Rx48[5])
General Purpose Input 6
General Purpose Input 7
General Purpose Input 8
General Purpose Input 9
General Purpose Input 10
General Purpose Input 11
General Purpose Input 12
General Purpose Input 13
General Purpose Input 16
General Purpose Input 17
General Purpose Input 18
General Purpose Input 19
General Purpose Input 20
General Purpose Input 21
General Purpose Input 22
General Purpose Input 23
General Purpose Inputs 16-23
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Output 4
General Purpose Output 5
General Purpose Output 7
General Purpose Output 8
General Purpose Output 9
General Purpose Output 10
(Rx74[7] = 0 and Function 4 Rx54[2] = 1)
(Rx74[7] = 0 and Function 4 Rx54[3] = 1)
(Function 4 Rx54[4] = 1)
(Rx75[4] = 1)
(Rx75[5] = 1)
(Rx75[7] = 1)
(Rx74[2] = 1 and Rx76[0] = 0)
(Rx74[3] = 1)
(Rx74[4] = 1 and Rx76[2] = 0)
General Purpose Output 11(CG
(CF:
General Purpose Output 12
General Purpose Output 13
General Purpose Output 14
General Purpose Output 15
General Purpose Output 16
General Purpose Output 17
General Purpose Output 18
General Purpose Output 19
General Purpose Output 20
General Purpose Output 21
General Purpose Output 22
General Purpose Output 23
General Purpose Output 24
(Rx76[1] = 1 and Rx76[4] = 0)
(Rx77[0] = 1) see also Rx76[4-3]
(Rx76[5] = 1)
(Rx76[5] = 1)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[7] = 1 and Rx77[3] = 0)
(Rx77[6] = 1, audio enabled, game disabled)
(Rx77[6] = 1, audio enabled, game disabled)
(Rx75[3] = 1 & Rx75[1]=1 & Rx68[3]=0)
Default pin functions are underlined in table above (with default level following in parentheses)
See also Function 0 Rx77[7-6]
(Rx74[2] = 1 and Rx76[0] = 1).
General Purpose I/Os
Signal NamePin #I/O Signal Description
GPIOA
GPIOB
/ GPI8 / GPO8 / GPOWE#
/ GPI9 / GPO9 / FAN2
/ DTEST
GPIOC
/ GPI10 / GPO10 / CHAS
/ ATEST
GPIOD
/ MCCS#
/ GPI11 / GPO11
(CD/CE)
Revision 1.54 February 25, 2000-23-Pinouts
T14IO
U12IO
V14IO
U8IO
General Purpose I/O A / 8
also Rx74[2]
General Purpose I/O B / 9.
General Purpose I/O C / 10.
General Purpose I/O D / 11.
(Rx76[0] = 0). GPOWE# if Rx76[0] = 1. See
See also Rx74[3]
(Rx76[2] = 0). See also Rx74[4]
(Rx76[3] = 0). See also Rx74[5]
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Hardware Monitoring
Signal NamePin # I/O Signal Description
VT82C686A
VSENS1
VSENS2
VSENS3
VSENS4
VREF
TSENS1
TSENS2
FAN1
/ GPIOB/9 / DTEST
FAN2
/ GPIOC/10 / ATEST
CHAS
DTEST
ATEST
/ FAN2 / GPIOB/9
/ CHAS / GPIOC/10
U13I
V13I
W14I
Y14I
T13P
W13I
Y13I
T12I
U12I
V14I
U12O
V14O
Voltage Sense 2.0V.
Voltage Sense 2.5V.
Monitor for CPU core voltage.
Monitor fo r North Bridge c ore voltage.
Voltage Sense 5V.
Voltage Sense 12V.
Connect +12V through a resistive voltage divider to insure 5V
max to the input pin (see MVP4 Design Guide for details).
Voltage Reference for Thermal Sensing
(5V ±5%)
Temperature Sense 1.
Temperature Sense 2.
Fan Speed Monitor 1.
(3.3V only)
Fan Speed Monitor 2.
Chassis Intrusion Detect
(Func 0 Rx76[2] = 1). Used for system security purposes.
Hardware Monitor Digital Test Out
Hardware Monitor Analog Test Out
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Power Management
Signal NamePin #I/OSignal Description
VT82C686A
THRM
/ GPI5 / PME#
PWRBTN#
SLPBTN#
/ IRQ6 / GPI4
RSMRST#
EXTSMI#
/ GPI5 / THRM
PME#
SMBALRT#
/ GPI3 / WSC# (CG)
LID
RING#
BATLOW#
CPUSTP#
PCISTP#
SUSA#
SUSB#
/ GPI6
/ GPI7
/ GPI2
/ GPO4
/ GPO5
/ GPO1 / APICD0 (CG)
/ GPO2
SUSC#
SUSST1#
SUSCLK
/ GPO3
/ APICD1 (CG)
T11I
Y11I
G1I / I /
I
V6I
Y10IOD
T11I
W10I
U10I
V11I
U11I
Y12O
V12O
V9O
W9O
Y9O
V10O
T10O
Thermal Alarm Monitor
Power Button.
Used by the Power Management subsystem to monitor an
(Rx74[1] = 1)
external system on/off button or switch. The VT82C686A performs a 200us
debounce of this input if Function 4 Rx40[5] is set to 1. (3.3V only)
Sleep Button.
Used by the Power Management subsystem to monitor an
external system sleep button or switch. (Function 4 Rx40[6]=1) (10K PU to
VCC if not used)
Resume Reset.
Resets the internal logic connected to the VCCS power plane
and also resets portions of the internal RTC logic.
External System Management Interrupt.
When enabled to allow it, a
falling edge on this input causes an SMI# to be generated to the CPU to enter
SMI mode. (10K PU to VCCS if not used) (3.3V only)
Power Management Event.
SMB Alert
(System Management Bus I/O space Rx08[3] = 1). When the
(Rx74[1]=0) (1K PU to VCCS if not used)
chip is enabled to allow it, assertion generates an IRQ or SMI or power
management event. (10K PU to VCCS if not used)
Notebook Computer Display Lid Open / Closed Monitor.
Used by the
Power Management subsystem to monitor the opening and closing of the
display lid of notebook computers. Can be used to detect either low-to-high
and/or high-to-low transitions to generate an SMI#. The VT82C686A
performs a 200 usec debounce of this input if Function 4 Rx40[5] is set to 1.
(10K PU to VCCS if not used)
Ring Indicator.
May be connected to external modem circuitry to allow the
system to be re-activated by a received phone call. (10K PU to VCCS if not
used)
Battery Low Indicator.
CPU Clock Stop
(10K PU to VCCS if not used) (3.3V only)
(Rx75[4] = 0). Signals the system clock generator to
disable the CPU clock outputs. Not connected if not used. See also PMU I/O
Rx2C[3].
PCI Clock Stop
(Rx75[5] = 0). Signals the system clock generator to disable
the PCI clock outputs. Not connected if not used.
Suspend Plane A Control
(Rx74[7]=0 and Function 4 Rx54[2]=0). Asserted
during power management POS, STR, and STD suspend states. Used to
control the primary power plane. (10K PU to VCCS if not used)
Suspend Plane B Control
(Rx74[7]=0 and Function 4 Rx54[3]=0). Asserted
during power management STR and STD suspend states. Used to control the
secondary power plane. (10K PU to VCCS if not used)
Suspend Plane C Control.
Asserted during power management STD
suspend state. Used to control the tertiary power plane. Also connected to
ATX power-on circuitry.
Suspend Status 1
(Func4 Rx54[4] = 1 for GPO3). Typically connected to
the North Bridge to provide information on host clock status. Asserted when
the system may stop the host clock, such as Stop Clock or during POS, STR,
or STD suspend states. Connect 10K PU to VCCS.
Suspend Clock.
32.768 KHz output clock for use by the North Bridge (e.g.,
Apollo MVP3 or MVP4) for DRAM refresh purposes. Stopped during
Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VCCS.
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Resets and Clocks
Signal NamePin #I/OSignal Description
VT82C686A
PWRGD
PCIRST#
W6I
B16O
Power Good.
PCI Reset.
Connected to the PWRGOOD signal on the Power Supply.
Active low reset signal for the PCI bus. The VT82C686A will
assert this pin during power-up or from the control register.
RSTDRV
J1O
Reset Drive.
Reset signal to the I S A bus. Connect through an inverter to the
chipset north bridge RESET# input and to PCI bus RESET#.
BCLK
OSC
RTCX1
H5O
E4I
Y5I
Bus Clock.
Oscillator.
RTC Crystal Input
ISA bus clock.
14.31818 MHz clock signal used by the internal Timer.
used for the internal RTC and for power-well power management logic.
RTCX2
SLOWCLK
/ GPO0
W5O
T8O
RTC Crystal Output
Slow Clock.
.Frequency selectable if PMU function 4 Rx54[1-0] is nonzero
(set to 01, 10, or 11).
Power and Ground
Signal NamePin #I/OSignal Description
VCC
GND
VCCS
VBAT
VREF
VCCH
GNDH
VCCU
GNDU
F7, F10, F12-F14,
H6, H15, J6, J15,
K6, K15, M6,
M15, N6, N15,
R7-R8, R11, R14
F6, F11, F15, G6,
G15, J9-J12, K9-
K12, L6, L9-L12,
L15, M9-M12,
P6, P15, R6, R15
R9-R10P
Y6P
T13P
R12P
R13P
F9P
F8P
P
Core Power.
3.3V nominal (3.15V to 3.45V). This supply is turned on only
when the mechanical switch on the power supply is turned on and the
PWRON signal is conditioned high. This pin should be connected to the
same voltage as the CPU I/O circuitry. Internally connected to hardware
monitoring system voltage detection circuitry for 3.3V monitoring.
P
Ground.
Suspend Power.
Connect to primary motherboard ground plane.
Always available unless the mechanical switch of the power
supply is turned off. If the “soft-off” state is not implemented, then this pin
can be connected to VCC. Signals powered by or referenced to this plane are:
PWRGD, RSMRST#, PWRBTN#, SMBCLK, SMBDATA, SUSCLK,
SUSA# / GPO1, SUSB# / GPO2, SUSC#, SUSST1# / GPO6, GPI1 / I RQ8#,
GPI2 / BATLOW#, GPI3 / LID, GPI5 / PME#, GPI6 / SMBALRT#, GPI7 /
RING#, GPO0
RTC Battery.
Battery input for internal RTC (RTCX1, RTCX2)
Voltage Reference
Hardware Monitor Power.
(voltage monitoring, temperature monitoring, and fan speed monitoring).
Connect to VCC thr ough a ferrite bead.
Hardware Monitor Gro und.
USB Differential Output Power.
(USBP0+, P0-, P1+, P1-, P2+, P 2-, P3+, P3-). Connec t to VCC through a
ferrite bead.
USB Differential Output Ground.
: 32.768 KHz crystal or oscillator input. This input is
: 32.768 KHz crystal output
(5V ±5%). For thermal sensing and 5V input tolerance.
Power for hardware monitoring subsystem
Connect to GND through a ferrite bead.
Power for USB differential outputs
Connect to GND through a ferrite bead.
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R
EGISTERS
VT82C686A
Register Overview
The following tables summarize the configuration and I/O
registers of the VT82C686A. These tables also document the
power-on default value (“Default”) and access type (“Acc”)
for each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see
individual register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless ot herwise indicated
100-CF7-available for system use*
CF8-CFB PCI Configuration Address 0000 1100 1111 10xx
CFC-CFF PCI Configuration Data0000 1100 1111 11xx
D00-FFFF -available for system use-
* On-Chip Super-I/O Functi ons – PC-Standard Port Addresses
200-20FGame Port
2E8-2EFCOM4
2F8-2FFCOM2
378-37FParallel Port (Standard & EPP)
3E8-3EFCOM3
3F0-3F1Configuration Index / Data
3F0-3F7Floppy Controller
3F8-3FFCOM1
778-77AParallel Port (ECP Extensions) (Port 378+400)
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VT82C686A
Table 3. Registers
Legacy I/O Registers
PortMaster DMA Controller RegistersDefa ult Acc
00Channel 0 Base & Current AddressRW
01Channel 0 Base & Current CountRW
02Channel 1 Base & Current AddressRW
03Channel 1 Base & Current CountRW
04Channel 2 Base & Current AddressRW
05Channel 2 Base & Current CountRW
06Channel 3 Base & Current AddressRW
07Channel 3 Base & Current CountRW
08Status / CommandRW
09Write Request
0AWrite Single Mask
0BWrite Mode
0CClear Byte Pointer FF
0DMaster Clear
0EClear Mask
71CMOS Memory Data (128 bytes)RW
72CMOS Memory AddressRW
73CMOS Memory Data (256 bytes)RW
74CMOS Memory AddressRW
75CMOS Memory Data (256 bytes)RW
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC
is disabled.
C0Channel 0 Base & Current AddressRW
C2Channel 0 Base & Current CountRW
C4Channel 1 Base & Current AddressRW
C6Channel 1 Base & Current CountRW
C8Channel 2 Base & Current AddressRW
CAChannel 2 Base & Current CountRW
CCChannel 3 Base & Current AddressRW
CEChannel 3 Base & Current CountRW
D0Status / CommandRW
D2Write Request
D4Write Single Mask
D6Write Mode
Configuration Space PCI-to-ISA Bridge-Specific Registers
VT82C686A
Offset Plug and Play ControlDefaultAcc
50PnP DMA Request Control
2D
51PnP Routing for LPT / FDC IRQ00RW
52PnP Routing for COM2 / COM1 IRQ00RW
53-reserved-00—
54PCI IRQ Edge / Level Select00RW
55PnP Routing for PCI INTA00RW
56PnP Routing for PCI INTB-C00RW
57PnP Routing for PCI INTD00RW
58APIC IRQ Output Control00RW
59-reserved-
5AKB C / RTC Control
04
x4†
5BInternal RTC Test Mode00RW
5CDMA Control00RW
5D-5E -reserved-00—
5F-reserved- (do not program)
04
† Bit 7-4 power-up default depends on external strapping
Offset
Distributed DMADefaultAcc
61-60 Channel 0 Base Address / Enable0000RW
63-62 Channel 1 Base Address / Enable0000RW
65-64 Channel 2 Base Address / Enable0000RW
67-66 Channel 3 Base Address / Enable0000RW
69-68 Serial IRQ Control0000RW
6B-6A Channel 5 Base Address / Enable0000RW
6D-6C Channel 6 Base Address / Enable0000RW
6F-6E Channel 7 Base Address / Enable0000RW
RW
—
RW
RW
Offset ISA Bus ControlDefaultAcc
40ISA Bus Control00RW
41ISA Test Mode00RW
42ISA Clock Control00RW
43ROM Decode Control00RW
44Keyboard Controller Control00RW
45T ype F DMA Control00RW
46Miscellaneous Control 100RW
47Miscellaneous Control 200RW
48Miscellaneous Control 3
01
RW
49-reserved-00—
4AIDE Interrupt Routing
04
RW
4B-reserved-00—
4CDMA / Master Mem Access Control 100RW
4DDMA / Master Mem Access Control 200RW
4F-4E DMA / Master Mem Access Control 3
0300
RW
Offset MiscellaneousDefaultAcc
70Subsystem ID Write00WO
71-73 -reserved-00—
74GPIO Control 100RW
75GPIO Control 200RW
76GPIO Control 300RW
77GPIO Control 4
4B-48 GPI Port Input Value
4F-4C GPO Port Output Value
inputRO
03FF FFFF
50-FF -reserved-00
—
RO
—
RW
—
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I/O Space Hardware Monitor Registers
VT82C686A
Offset Hardware MonitorDefaultAcc
00-3F Value RAM
00-12 -reserved-00
—
13 Analog Data 15-800RW
14 Analog Data 7-000RW
15 Digital Data 7-000RW
16 Channel Counter00RW
17 Data Valid & Channel Indicators00RW
18-1C -reserved-00
—
1D TSENS3 Hot Hi Limit00RW
1E TSENS3 Hot Hysteresis Lo Lim00RW
1F TSENS3 (Int) Temp Reading00RW
20 TSENS1 (W13) Temp Reading00RW
21 TSENS2 (Y13) Temp Reading00RW
22 VSENS1 (U13) Voltage Reading00RW
23 VSENS2 (V13) Voltage Reading00RW
24 Internal Core VCC Voltage Reading0 0RW
25 VSENS3 (W14) Voltage Reading00RW
26 VSENS4 (Y14) Voltage Reading00RW
27 -reserved- (-12V Voltage Reading)00
28 -reserved- (-5V Voltage Reading)00
—
—
29 FAN1 (T12) Count Reading00RW
2A FAN2 (U12) Count Reading00RW
2B VSENS1 (CPU) Voltage High Limit0 0RW
2C VSENS1 (CPU) Voltage Low Limit00RW
2D VSENS2 (NB) Voltage High Limit00RW
2E VSENS2 (NB) Voltage Low Limit00RW
2F Internal Core VCC High Limit00RW
30 Internal Core VCC Low Limit00RW
31 VSENS3 (5V) Voltage High Limit00RW
32 VSENS3 (5V) Voltage Low Limit00RW
33 VSENS4 (12V) Voltage High Limit00RW
34 VSENS4 (12V) Voltage Low Limit00RW
35 -reserved- (-12V Sense High Limit)00
36 -reserved- (-12V Sense Low Limit)00
37 -reserved- (-5V Sense High Limit)00
38 -reserved- (-5V Sense Low Limit)00
—
—
—
—
39 TSENS1 Hot High Limit00RW
3A TSENS1 Hot Hysteresis Lo Lim00RW
3B FAN1 Fan Count Li mit00RW
3C FAN2 Fan Count Li mit00RW
3D TSENS2 Hot High Limit00RW
3E TSENS2 Hot Hysteresis Lo Lim00RW
3F Stepping ID Number00RW
Offset Hardware Monitor (continued)DefaultAcc
40Hardware Monitor Configuration
08
41Hardware Monitor Interrupt Status 100
42Hardware Monitor Interrupt Status 200
Function 5 I/O Base 2 Registers – MIDI / Game Port
Offset FM NMI Status RegistersDefaultAcc
1-0MIDI Port Base0330RW
3-2Game Port Base0200RW
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VT82C686A
I/O Registers – SoundBlaster Pr o
Offset SB Pro Registers (220 or 240h typ)Default Acc
0FM Le ft Channel Index / StatusRW
1FM Left Channel Data
WO
2FM Right Channel Index / StatusRW
3FM Right Channel Data
4Mixer Index
WO
WO
5Mixer DataRW
6Sound Processor Reset
WO
7-reserved-00-8FM I ndex / Status (Both Channels)RW
9FM D ata (Both Channels)
ASound P rocessor Data
WO
RO
B-reserved-00-CSound Processor Command / Data
Sound Proce ssor Buffer Status
WR
RD
D-reserved-00--
ESnd Processor Data Available Status
RO
F-reserved-00--
PortSB Pro Regs (same as offsets 8 & 9)Default Acc
388h FM Index / StatusRW
389h FM Data
WO
The above group of registers emulates the “FM”, “Mixer”, and
“Sound Processor” functions of the SoundBlas t er Pro.
I/O Registers – Game Por t
Offset Game Port (200-20F typical)Default Acc
0-reserved-00-1Game Port Status
1Start One-Shot
RO
WO
2-F-reserved-00--
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VT82C686A
Register Descriptions
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All of
these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control ................. RW
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register. Bit-3 should be cleared to
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
5Timer/Counter 2 Output
......................................RO
This bit reflects the output of Timer/Counter 2
without any synchronization.
0Normal
1Briefly pulse system reset to switch from
protected mode to real mode
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VT82C686A
Keyboard Controller Registers
The keyboard controller handles the keyboard and mouse
interfaces. Two ports are used: port 60 and port 64. Reads
from port 64 return a status byte. Writes to port 64h are
command codes (see command code list following the register
descriptions). Input and output data is transferred via port 60.
A “Control” register is also available. It is accessable by
writing commands 20h / 60h to the command port (port 64h);
The control byte is written by first sending 60h to the
command port, then sending the control byte value. The
control register may be read by sending a command of 20h to
port 64h, waiting for “Output Buffer Full” status = 1, then
reading the control byte value from port 60h.
Traditional (non-integrated) keyboard controllers have an
“Input Port” and an “Output Port” with specific pins dedicated
to certain functions and other pins available for general
purpose I/O. Specific commands are provided to set these pins
high and low. All outputs are “open-collector” so to allow
input on one of these pins, the output value for that pin would
be set high (non-driving) and the desired input value read on
the input port. These ports are defined as follows:
1T1 - Mouse Clock In––
Note: Command code C0h transfers input port data to the
output buffer. Command code D0h copies output port values
to the output buffer. Command code E0h transfers test input
port data to the output buffer.
Port 60 - Keyboard Controller Input Buffer ................. WO
Only write to port 60h if port 64h bit-1 = 0 (1=full).
Port 64 - Keyboard / Mouse Status .................................. RO
Port 60 - Keyboard Controller Output Buffer ................ RO
Only read from port 60h if port 64h bit-0 = 1 (0=empty).
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Port 64 - Keyboard / Mouse Command .......................... WO
This port is used to send commands to the keyboard / mouse
controller. The command codes recognized by the
VT82C686A are listed n the table below.
Note: The VT82C686A Keyboard Controller is compatible
with the VIA VT82C42 Industry-Standard Keyboard
Controller except that due to its integrated nature, many of the
input and output port pins are not available externally for use
as general purp ose I/O pins (even though P13-P16 are set on
power-up as strapping options). In other words, many of the
commands below are provided and “work”, but otherwise
perform no useful funct ion (e.g., commands that se t P12-P17
high or low). Also note that setting P10-11, P22-23, P26-27,
and T0-1 high o r low directly serves no use ful purpose, since
these bits are used to implement the keyboard and mouse ports
and are directly controlled by keyboard controller logic.
Table 4. Keyboard Controller Command Codes
VT82C686A
CodeKeyboard Command Code Description
20hRead Control Byte (next byte is Control Byte)
21-3FhRead SRAM Data (next byte is Data Byte)
60hWrite Control Byte (next byte is Control Byte)
61-7FhWrite SRAM Data (next byte is Data Byte)
9xhWrite low nibble (bits 0-3) to P10-P13
A1hOutput Keyboard Controller Version #
A4hTest if Password is installed
(always returns F1h to indicate not installed)
A7hDisable Mouse Interface
A8hEnable Mouse Interface
A9hMouse Interface Test (puts test results in port 60h)
(value: 0=OK, 1=clk stuck low, 2=clk stuc k hi gh,
3=data stuck lo, 4=data stuck hi, FF=general error)
AAhKBC self test (returns 55h if OK, FCh if not)
ABhKeyboard Interface Test (see A9h Mouse Test)
ADhDisable Keyboard Interface
AEhEnable Keyboard Interface
AFhReturn Version #
B0hSet P10 low
B1hSet P11 low
B2hSet P12 low
B3hSet P13 low
B4hSet P22 low
B5hSet P23 low
B6hSet P14 low
B7hSet P15 low
B8hSet P10 high
B9hSet P11 high
BAhSet P12 high
BBhSet P13 high
BChSet P22 hi gh
BDhSet P23 high
BEhS et P14 high
BFhSet P15 high
CodeKeyboard Command Code Description
C0hRead input port (read P10-17 input data to
the output buffer)
C1hPoll input port low (read input data on P11-13
repeatably & put in bits 5-7 of status
C2hPoll input port high (same except P15-17)
C8hUnblock P22-23 (use before D1 to change
active mode)
C9hReblock P22-23 (protection mechanism for D1)
CAhRead mode (output KBC mode info to port 60
output buffer (bit-0=0 if ISA, 1 if PS/2)
D0hRead Output Port (copy P10-17 output port values
to port 60)
D1hWrite Output Port (data byte following is written to
keyboard output port as if it came from keyboard)
D2hWrite Keyboard Output Buffer & clear status bit-5
(write following byte to keyboard)
D3hWrite Mouse Output Buffer & set status bit-5 (write
following byte to mouse; put value in mouse input
buffer so it appears to have come from the mouse)
D4hWrite Mouse (write following byte to mouse)
E0hRead test inputs (T0-1 read to bits 0-1 of resp byte)
ExhSet P23-P21 per command bits 3-1
FxhPulse P23-P20 low for 6usec per command bits 3-0
All other codes not listed are undefined.
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DMA Controller I/O Registers
VT82C686A
Ports 00-0F - Master DMA Controller
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0Register Name
0000 0000 000x 0000Ch 0 Base / Current AddressRW
0000 0000 000x 0001Ch 0 Base / Current CountRW
0000 0000 000x 0010Ch 1 Base / Current AddressRW
0000 0000 000x 0011Ch 1 Base / Current CountRW
0000 0000 000x 0100Ch 2 Base / Current AddressRW
0000 0000 000x 0101Ch 2 Base / Current CountRW
0000 0000 000x 0110Ch 3 Base / Current AddressRW
0000 0000 000x 0111Ch 3 Base / Current CountRW
0000 0000 000x 1000Status / CommandRW
0000 0000 000x 1001Write RequestWO
0000 0000 000x 1010Write Single MaskWO
0000 0000 000x 1011Write ModeWO
0000 0000 000x 1100Clear Byte Pointer F/FWO
0000 0000 000x 1101Master ClearWO
0000 0000 000x 1110Clear MaskWO
0000 0000 000x 1111R/W All Mask BitsRW
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0Register Name
0000 0000 1100 000xCh 4 Base / Current AddressRW
0000 0000 1100 001xCh 4 Base / Current CountRW
0000 0000 1100 010xCh 5 Base / Current AddressRW
0000 0000 1100 011xCh 5 Base / Current CountRW
0000 0000 1100 100xCh 6 Base / Current AddressRW
0000 0000 1100 101xCh 6 Base / Current CountRW
0000 0000 1100 110xCh 7 Base / Current AddressRW
0000 0000 1100 111xCh 7 Base / Current CountRW
0000 0000 1101 000xStatus / CommandRW
0000 0000 1101 001xWrite RequestWO
0000 0000 1101 010xWrite Single MaskWO
0000 0000 1101 011xWrite ModeWO
0000 0000 1101 100xClear Byte Pointer F/FWO
0000 0000 1101 101xMaster ClearWO
0000 0000 1101 110xClear MaskWO
0000 0000 1101 111xRead/Write All Mask BitsWO
Note that not all bits of the address are decoded.
The Master and Slave DMA Controllers are compatible with
the Intel 8237 DMA Controller chip. Detailed description of
8237 DMA controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
The DMA Controller shadow registers are enabled by setting
function 0 Rx77 bit 0. If the shadow registers are enabled,
they are read back at the indicated I/O port instead of the
standard DMA controller registers (writes are unchanged).
Port 0 –Channel 0 Base Address ...................................... RO
Port 1 –Channel 0 Byte Count .......................................... RO
Port 2 –Channel 1 Base Address ...................................... RO
Port 3 –Channel 1 Byte Count .......................................... RO
Port 4 –Channel 2 Base Address ...................................... RO
Port 5 –Channel 2 Byte Count .......................................... RO
Port 6 –Channel 3 Base Address ...................................... RO
Port 7 –Channel 3 Byte Count .......................................... RO
Port 8 –1st Read Channel 0-3 Command Register .......... RO
Port 8 –2nd Read Channel 0-3 Request Register.............. RO
Port 8 –3rd Read Channel 0 Mode Register ..................... RO
Port 8 –4th Read Channel 1 Mode Register ..................... RO
Port 8 –5th Read Channel 2 Mode Register ..................... RO
Port 8 –6th Read Channel 3 Mode Register ..................... RO
Port F –Channel 0-3 Read All Mask ................................ RO
Port C4 –Channel 5 Base Address.................................... RO
Port C6 –Channel 5 Byte Count ....................................... RO
Port C8 –Channel 6 Base Address.................................... RO
Port CA –Channel 6 Byte Count ...................................... RO
Port CC –Channel 7 Base Address ................................... RO
Port CE –Channel 7 Byte Count ...................................... RO
Port D0 –1st Read Channel 4-7 Command Register ........ RO
Port D0 –2nd Read Channel 4-7 Request Register ........... RO
Port D0 –3rd Read Channel 4 Mode Register .................. RO
Port D0 –4th Read Channel 5 Mode Register .................. RO
Port D0 –5th Read Channel 6 Mode Register .................. RO
Port D0 –6th Read Channel 7 Mode Register .................. RO
Port DE –Channel 4-7 Read All Mask ............................. RO
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VT82C686A
Interrupt Controller Registers
Ports 20-21 - Master Interrupt Controller
The Master Interrupt Controller controls system interrupt
channels 0-7. Two registers control the Master Interrupt
Controller. They are:
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Cont roller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting function
0 Rx47[4]. If the shadow registers are enabled, they are read
back at the indicated I/O port instead of the standard interrupt
controller registers (writes are unchanged).
Port 20 - Master Interrupt Control Shadow ................... RO
Port A0 - Slave Interrupt Control Shadow ..................... RO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Timer / Counter Shadow Registers
The following shadow registers are enabled for readback by
setting function 0 Rx47[4]. If the shadow registers are
enabled, they are read back at the indicated I/O port instead of
the standard timer / counter registers (writes are unchanged).
Port 40 – Counter 0 Base Count Value (LSB 1
st
MSB 2nd) RO
Port 41 – Counter 1 Base Count Value (LSB 1st MSB 2nd) RO
Port 42 – Counter 2 Base Count Value (LSB 1st MSB 2nd) RO
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CMOS / RTC Registers
Port 70 - CMOS Address .................................................. RW
Port 72 - CMOS Address .................................................. RW
7-0CMOS Address
(256 bytes).................................RW
Port 73 - CMOS Data........................................................ RW
7-0CMOS Data
(256 bytes)
Note:P orts 72-73 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 72-73 will be directed to an
external RTC.
Port 74 - CMOS Address .................................................. RW
7-0CMOS Address
(256 bytes).................................RW
Port 75 - CMOS Data........................................................ RW
7-0CMOS Data
(256 bytes)
Note:P orts 74-75 may be accessed only if Function 0 Rx5B
bit-1 is set to one to enable the internal RTC SRAM
and if Rx48 bit-3 (Port 74/75 Access Enable) is set to
one to enable port 74/75 access.
Note:Ports 70-71 are compatible with PC industry-
standards and may be used to access the lower 128
bytes of the 256-byte on-chip CMOS RAM. Ports
72-73 may be used to access the full extended 256byte space. Ports 74-75 may be used to access the
full on-chip extended 256-byte space in cases where
the on-chip RTC is disabled.
Note:The system Real Time Clock (RTC) is part of the
“CMOS” block. The RTC control registers are
located at specific offsets in the CMOS data area (00Dh and 7D-7Fh). Detailed descriptions of CMOS /
RTC operation and programming can be obtained
from the VIA VT82887 Data Book or numerous
other industry publications. For reference, the
definition of the RTC register locations and bits are
summarized in the following table:
0ARegister A
7UIP
6-4DV2-0
3-0RS3-0
Update In Progress
Divide (010=ena osc & keep time)
Rate Select for Periodic Interrupt
0BRegister B
7SET
6PIE
5AIE
4UIE
3SQWE
2DM
124/12
0DSE
Inhibit Update Transfers
Periodic Interrupt Enable
Alarm Interrupt Enable
Update Ended Interrupt Enable
No function (read/write bit)
Data Mode (0=BCD, 1=binary)
Hours Byte Format (0=12, 1=24)
Daylight Savings Enable
0CRegister C
7IRQF
6PF
5AF
4UF
3-00
Interrupt Request Flag
Periodic Interrupt Flag
Alarm Interrupt Flag
Update Ended Flag
Unused (always read 0)
0DRegister D
7VRT
6-00
Reads 1 if VBAT voltage is OK
Unused (always read 0)
0E-7C Software-Defined Storage Registers
Offset Extended Functions
7DDate Alarm
01-1Fh01-31h
7EMonth Alarm
7FCentury Field
Binary Range BCD Range
01-0Ch01-12h
13-14h19-20h
80-FF Software-Defined Storage Registers
Table 5. CMOS Register Summary
(111 Bytes)
(128 Bytes)
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VT82C686A
Super-I/O Configuration Index / Data Registers
Super-I/O configuration registers are accessed by performing
I/O operations to / from an index / data pair of registers in
system I/O space at port addresses 3F0h and 3F1h. The
configuration registers accessed using this mechanism are used
to configure the Super-I/O registers (parallel port, serial ports,
IR port, and floppy controller).
Super I/O configuration is accomplished in three steps:
1) Enter configuration mode (set Function 0 Rx85[1] = 1)
2) Configure the chip
a) Write index to port 3F0
b) Read / write data from / to port 3F1
c) Repeat a and b for all desired registers
3) Exit configuration mode (set Function 0 Rx85[1] = 0)
Port 3F0h – Super-I/O Configuration Index ................... RW
7-0Index value
Function 0 PCI configuration space register Rx85[1] must be
set to 1 to enable access to the Super-I/O configuration
registers.
Port 3F1h – Super-I/O Configuration Data .................... RW
7-0Data value
This register shares a port with the Floppy Status Port (which
is read only). This port is accessible only when Rx85[1] is set
to 1 (the floppy status port is accessed if Rx85[1] = 0).
Super-I/O Configuration Registers
These registers are accessed via the port 3F0 / 3F1 index / data
register pair using the indicated index values below
Index E0 – Super-I/O Device ID (3Ch) ............................ RO
If EPP is not enabled, the parallel port can be set to 192
locations on 4-byte boundaries from 100h to 3FCh. If EPP is
enabled, the parallel port can be set to 96 locations on 8-byte
boundaries from 100h to 3F8h.
Index E7 – Serial Port 1 I/O Base Address (00h) ........... RW
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Super-I/O I/O Ports
Floppy Disk Controller Registers
These registers are located at I/O ports which are offsets from
“FDCBase” (index E3h of the Super-I/O configuration
registers). FDCBase is typically set to allow these ports to be
accessed at the standard floppy disk controller address range
of 3F0-3F7h.
VT82C686A
Port FDCBase+2 – FDC Command ................................. RW
7Motor 3 (unused in VT82C686A: no MTR3# pin)
6Motor 2 (unused in VT82C686A: no MTR2# pin)
5Motor 1
0Motor Off
1Motor On
4Motor 0
0Motor Off
1Motor On
3DMA and IRQ Channels
0Disable
1Enable
2FDC Reset
0E xe cute FDC Reset
1FDC Enable
1-0Drive Select
00 Select Drive 0
01 Select Drive 1
1x -reserved-
Port FDCBase+4 – FDC Main Status ............................... RO
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Parallel Port Registers
These registers are located at I/O ports which are offsets from
“LPTBase” (index E6h of the Super-I/O configuration
registers). LPTBase is typically set to allow these ports to be
accessed at the standard parallel port address range of 37837Fh.
VT82C686A
Port LPTBase+0 – Parallel Port Data ............................. RW
7-0Parallel Port Data
Port LPTBase+1 – Parallel Port Status ............................ RO
7BUSY#
0Printer busy, offline, or error
1Printer not busy
6ACK#
0Data transfer to printer complete
1Data transfer to pr inter in pr ogress
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VT82C686A
Serial Port 1 Registers
These registers are located at I/O ports which are offsets from
“COM1Base” (index E7h of the Super-I/O configuration
registers). COM1Base is typically set to allow these ports to
be accessed at the standard serial port 1 address range of 3F83FFh.
Port COM1Base+0 – Transmit / Receive Buffer ............ RW
7-0Serial Data
Port COM1Base+1 – Interrupt Enable ........................... RW
3Interrupt on Handshake Input State Change
2Intr on Parity, Overrun, Framing Error or Break
1Interrupt on Transmit Buffer Empty
0Interrupt on Receive Data Ready
Port COM1Base+1-0 – Baud Rate Generator Divisor ... RW
15-0 Divisor Value for Baud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
Port COM1Base+2 – Interrupt Status ............................. RO
01 byte in transmit hold or transmit shift register
10 bytes transmit hold and transmit shift regs
5Transmit Buffer Empty
01 b yte in transmit hold register
1Transmit hold register e mpty
4Break Detected
0No break detected
1Break detected
3Framing Error Detected
0No error
1Error
2Parity Error Detected
0No error
1Error
1Overrun Error Detected
0No error
1Error
0Received Data Ready
0No received d ata available
1Received data in receiver buffer register
Port COM1Base+6 – Handshake Status ......................... RW
7DCD Status (1=Active, 0=Inactive)
6RI Status (1=Active, 0=Inactive)
5DSR Status (1=Active, 0=Inactive)
4CTS Status (1=Active, 0=Inactive)
3DCD Changed (1=Changed Since Last Read)
2RI Changed (1=Changed Since Last Read)
1DSR Changed (1=Changed Since Last Read)
0CTS Changed (1=Changed Since Last Read)
Port COM1Base+7 – Scratchpad .................................... RW
7Scratchpad Data
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VT82C686A
Serial Port 2 Registers
These registers are located at I/O ports which are offsets from
“COM2Base” (index E8h of the Super-I/O configuration
registers). COM2Base is typically set to allow these ports to
be accessed at the standard serial port 2 address range of 2F82FFh.
Port COM2Base+0 – Transmit / Receive Buffer ............ RW
7-0Serial Data
Port COM2Base+1 – Interrupt Enable ........................... RW
3Interrupt on Handshake Input State Change
2Intr on Parity, Overrun, Framing Error or Break
1Interrupt on Transmit Buffer Empty
0Interrupt on Receive Data Ready
Port COM2Base+1-0 – Baud Rate Generator Divisor ... RW
15-0 Divisor Value for Baud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
Port COM2Base+2 – Interrupt Status ............................. RO
01 byte in transmit hold or transmit shift register
10 bytes transmit hold and transmit shift regs
5Transmit Buffer Empty
01 b yte in transmit hold register
1Transmit hold register e mpty
4Break Detected
0No break detected
1Break detected
3Framing Error Detected
0No error
1Error
2Parity Error Detected
0No error
1Error
1Overrun Error Detected
0No error
1Error
0Received Data Ready
0No received data available
1Received data in receiver buffer register
Port COM2Base+6 – Handshake Status ......................... RW
7DCD Status (1=Active, 0=Inactive)
6RI Status (1=Active, 0=Inactive)
5DSR Status (1=Active, 0=Inactive)
4CTS Status (1=Active, 0=Inactive)
3DCD Changed (1=Changed Since Last Read)
2RI Changed (1=Changed Since Last Read)
1DSR Changed (1=Changed Since Last Read)
0CTS Changed (1=Changed Since Last Read)
Port COM2Base+7 – Scratchpad .................................... RW
7Scratchpad Data
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VT82C686A
SoundBlaster Pro Port Registers
These registers are located at offsets from “SBPBase” (defined
in Rx43 of Audio Function 5 PCI configuration space).
SBPBase is typically set to allow these ports to be accessed at
the standard SoundBlaster Pro port address of 220h or 240h.
FM Registers
Port SBPBase+0 – FM Left Channel Index / Status ....... RW
7-0FM Right Channel Index / Status
Port SBPBase+1 – FM Left Channel Data ..................... WO
7-0Right Channel FM Data
Port SBPBase+2 – FM Right Channel Index / Status .... RW
7-0FM Right Channel Index / St atus
Port SBPBase+3 – FM Right Channel Data .................. WO
7-0Right Channel FM Data
Port 388h or SBPBase+8 – FM Index / Status ................ RW
7-0FM Index / Status (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 0 and 2 as well)
Port 389h or SBPBase+9 – FM Data .............................. WO
7-0FM Data (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 1 and 3 as well)
Mixer Registers
Port SBPBase+4 – Mixer Index....................................... WO
7-0Mixer Index
Port SBPBase+5 – Mixer Data ......................................... RW
7-0Mixer Data
Sound Processor Registers
Register Summary - FM
Index Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Port SBPBase+6 – Sound Processor Reset ..................... WO
01 = Sound Processor Reset
Port SBPBase+A – Sound Processor Read Data ............. RO
7-0Sound Processor Read Data
Port SBPBase+C – Sound Processor Command / Data WO
7-0Sound Processor Command / Write Data
Port SBPBase+C – Sound Processor Buffer Status ......... RO
71 = Sound Processor Command / Data Port Busy
Port SBPBase+E – Sound Processor Data Avail Status .. RO
71 = Sound Processor Data Availa ble
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VT82C686A
Command Summary – Sound Processor
#TypeCommand
10 Play8 bits directly
14 Play8 bits via DMA
91 PlayHigh-speed 8 bits via DMA
16 Play2-bit compressed via DMA
17 Play2-bit compressed via DMA with reference
74 Play4-bit compressed via DMA
75 Play4-bit compressed via DMA with reference
76 Play2.6-bit compressed via DMA
77 Play2.6-bit compressed via DMA with reference
20 Record Direct
24 Record Via DMA
99 Record High-speed 8 bits via DMA
D1 Speaker Turn on speaker connection
D3 Speaker Turn off speaker connection
D8 Speaker Get speaker setting
These registers are fixed at the standard game port address of
201h.
I/O Port 201h – Game Port Status ................................... RO
7Joystick B Button 2 Status
6Joystick B Button 1 Status
5Joystick A Button 2 Status
4Joystick A Button 1 Status
3Joystick B One-Shot Status for Y-Potentiometer
2Joystick B One-Shot Status for X-Potentiometer
1Joystick A One-Shot Status for Y-Potentiometer
0Joystick A One-Shot Status for X-Potentiometer
I/O Port 201h – Start One-Shot ....................................... WO
(Value Written is Ignored)
7-0
30 MIDIDirect MIDI input
31 MIDIMIDI input via interrupt
32 MIDIDirect MIDI input with time stamp
33 MIDIMIDI input via interrupt with time stamp
34 MIDIDirect MIDI UART mode
35 MIDIMIDI UART mode via interrupt
36 MIDIDirect MIDI UART mode with time stamp
37 MIDIMIDI UART mode via interrupt with time stamp
38 MIDISend MIDI code
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PCI Configuration Space I/O
PCI configuration space accesses for functions 0-6 use PCI
configuration mechanism 1 (see PCI specification revision 2.2
for more details). The ports respond only to double-word
accesses. Byte or word accesses will be passed on unchanged.
Port CFB-CF8 - Configuration Address ......................... RW
The following sections describe the registers and register bits
of these functions.
Port CFF-CFC - Configuration Data .............................. RW
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VT82C686A
Function 0 Registers - PCI to ISA Bridge
All registers are located in the function 0 PCI configuration
space of the VT82C686A. These registers are accessed
through PCI configuration mechanism #1 via I/O address
CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h ......................................... RO
Offset 3-2 - Device ID = 0686h .......................................... RO
† If the test bit at offset 46 bit-4 is set, access to the above
indicated bits is reversed: bit-3 above becomes read only
(reading back 1) and bits 0-1 above become read / write (with
a default of 1).
Offset 7-6 - Status ........................................................... RWC
1Enable (DMA Clock = ISA Clock)
This function can be enabled for external ISA devices
(e.g., advanced Super-IO or FIR controllers) which
support 8MHz DMA channels. However, if this bit is
set to 1, then all DMA channels will be 8 MHz. If
this bit is set to 1 and Rx45[n] is set to 1, then I SA
DMA channel ‘n’ will be 16 MHz. Therefore,
typically this bit is set to 0 and the appropriate bits of
Rx45 should be set to 1 to enable 8 MHz DMA clock
only for specific channels that support the higher rate.
2SHOLD Lock During INTA
1Refresh Request Test Mode
6DMA type F Timing on Channel 7
5DMA type F Timing on Channel 6
4DMA type F Timing on Channel 5
3DMA type F Timing on Channel 3
2DMA type F Timing on Channel 2
1DMA type F Timing on Channel 1
0DMA type F Timing on Channel 0
............default=0
............default=0
............default=0
............default=0
............default=0
............default=0
............default=0
Note:For bits 0-6 above, see also Rx41[3]
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VT82C686A
Offset 46 - Miscellaneous Control 1 ................................. RW
7PCI Master Write Wait States
00 Wait States ..........................................default
1Enable
The Posted Memory Write function is automatically
enabled when Delay Transaction (see Rx47 bit-6) is
enabled, independent of the state of this bit.
Offset 47 - Miscellaneous Control 2 ................................ RW
7CPU Reset Source
0Use CPURST as CPU Reset.................. default
Note:All ISA DMA / Masters that access addresses higher
than the top of PCI memory will not be directed to the
PCI bus.
11Forward E0000-EFFFF Accesses to PCI
10Forward A0000-BFFFF Accesses to PCI
9Forward 80000-9FFFF Accesses to PCI
8Forward 00000-7FFFF Accesses to PCI
7Forward DC000-DFFFF Accesses to PCI
6Forward D8000-DBFFF Accesses to PCI
5Forward D4000-D7FFF Accesses to PCI
4Forward D0000-D3FFF Accesses to PCI
3Forward CC000-CFFFF Accesses to PCI
2Forward C8000-CBFFF Accesses to PCI
1Forward C4000-C7FFF Accesses to PCI
0Forward C0000-C3FFF Accesses to PCI
........def=0
.......def=0
........ def=1
........ def=1
......def=0
...... def=0
....... def=0
....... def=0
.....def=0
...... def=0
....... def=0
....... def=0
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Plug and Play Control
VT82C686A
Offset 50 – PNP DMA Request Control .......................... RW
7-4Reserved
3-2PnP Routing for Parallel Port DRQ
1-0PnP Routing for Floppy DRQ
Offset 5A – KBC / RTC Control ...................................... RW
Bits 7-4 of this register are latched from pins SD7-4 at powerup but are read/write accessible so may be changed after
power-up to change the default strap setting:
This bit is set if the internal RTC is disabled but it is
desired to still be able to access the internal RTC
SRAM via ports 74-75. If the internal RTC is
enabled, setting this bit does nothing (the internal
RTC SRAM should be accessed at either ports 70/71
or 72/73.
0RTC Test Mode Enable
(do not program).default=0
Offset 5C - DMA Control ................................................. RW
Offset 8D-8C – PCS2# I/O Port Address (CF/CG) ........ RW
15-0 PCS2# I/O Port Address
Offset 8F-8E – PCS3# I/O Port Address (CF/CG) ......... RW
15-0 PCS3# I/O Port Address
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VT82C686A
Function 1 Registers - Enhanced IDE Controller
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O re giste rs. T he P CI co nfigur at io n re giste rs
are located in the function 1 PCI configuration space of the
VT82C686A. The Bus Master IDE I/O registers are defined
in the SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO
Offset 3-2 - Device ID (0571h=IDE Controller) ............... RO
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VT82C686A
Function 2 Registers - USB Controller Ports 0-1
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 2 PCI configuration space of the
VT82C686A. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 0-1 (see function 3 for ports 2-3).
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
0-7Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ......................................................... RO
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
I/O Offset 1-0 - USB Command
I/O Offset 3-2 - USB Status
I/O Offset 5-4 - USB Interrupt Enable
I/O Offset 7-6 - Frame Number
I/O Offset B-8 - Frame List Base Address
I/O Offset 0C - Start Of Frame Modify
I/O Offset 11-10 - Port 0 Status / Control
I/O Offset 13-12 - Port 1 Status / Control
Offset 84 – PM Capability Status (CF/CG)..................... RW
7-0PM Capability Status
........................... default = 00h
Supports 00h (Off) and 11h (On) only
Offset C1-C0 - Legacy Support ......................................... RO
15-0 UHCI v1.1 Compliant
................ always reads 2000h
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VT82C686A
Function 3 Registers - USB Controller Ports 2-3
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 3 PCI configuration space of the
VT82C686A. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 2-3 (see function 2 for ports 0-1).
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
0-7Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ......................................................... RO
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
I/O Offset 1-0 - USB Command
I/O Offset 3-2 - USB Status
I/O Offset 5-4 - USB Interrupt Enable
I/O Offset 7-6 - Frame Number
I/O Offset B-8 - Frame List Base Address
I/O Offset 0C - Start Of Frame Modify
I/O Offset 11-10 - Port 0 Status / Control
I/O Offset 13-12 - Port 1 Status / Control
Offset 84 – PM Capability Status (CF/CG)..................... RW
7-0PM Capability Status
.......supports 00h and 11h only
Offset C1-C0 - Legacy Support ......................................... RO
15-0 UHCI v1.1 Compliant
................ always reads 2000h
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Function 4 Regs - Power M anagement, SMBus and HWM
This section describes the ACPI (Advanced Configuration and
Power Interface) Power Management system of the
VT82C686A which includes a System Management Bus
(SMBus) interface controller and Hardware Monitoring
(HWM) subsystem. The power management system of the
VT82C686A supports both ACPI and legacy power
management functions and is compatible with the APM v1.2
and ACPI v1.0 specifications.
PCI Configuration Space Header
VT82C686A
Offset 1-0 - Vendor ID ....................................................... RO
0-7Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ......................................................... RO
Offset 41 - General Configuration 1 ................................ RW
7I/O Enable for ACPI I/O Base
0Disable access to ACPI I/O block..........default
1Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block). The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
Port Address for the base of the 128-byte Power
Management I/O Register block, corresponding to
AD[15:7]. The "I/O Space" bit at offset 41 bit-7
enables access to this register block. The definitions
of the registers in the Power Management I/O
Register Block are included in the following section
this document.
6-00000001b
Offset 4C – Host Bus Power Management Control ........ RW
7-4Thermal Duty Cycle (THM_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the THRM# pin is asserted
low. The field is decoded as follows:
On setting this bit to 1, the GP0 timer loads the value
defined by bits 15-8 of this register and starts
counting down. The GP0 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP Timer Reload Enable Register (Power
Management I/O Space Offset 38h). If no such event
occurs and the GP0 timer counts down to zero, then
the GP0 Timer Timeout Status bit is set to one (bit-2
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP0 Timer Timeout Enable bit is set (bit-2 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
2GP0 Timer Automatic Reload
0GP0 Timer stops at 0 ............................default
Write to load count value; Read to get current count
15-8 GP0 Timer Count Value
Write to load count value; Read to get current count
7GP1 Timer Start
On setting this bit to 1, the GP1 timer loads the value
defined by bits 23-16 of this register and starts
counting down. The GP1 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP Timer Reload Enable Register (Power
Management I/O Space Offset 38h). If no such event
occurs and the GP1 timer counts down to zero, then
the GP1 Timer Timeout Status bit is set to one (bit-3
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP1 Timer Timeout Enable bit is set (bit-3 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
6GP1 Timer Automatic Reload
0GP1 Timer stops at 0 .............................default
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VT82C686A
Offset 58 – GP2 / GP3 Timer Control ............................. RW
7GP3 Timer Start
On setting this bit to 1, the GP3 timer loads the value
defined by Rx5A and starts counting down. The GP3
timer is reloaded at the occurrence of certain events
enabled in the GP Timer Reload Enable Register
(Power Management I/O Space Offset 38h). If no
such event occurs and the GP3 timer counts down to
zero, then the GP3 Timer Timeout Status bit is set to
one (bit-13 of the Global Status register at Power
Management Register I/O Space Offset 28h).
Additionally, if the GP3 Timer Timeout Enable bit is
set (bit-13 of the Global Enable register at Power
Management Register I/O Space Offset 2Ah), then an
SMI is generated.
6GP3 Timer Automatic Reload
0GP3 Timer stops at 0 .............................default
On setting this bit to 1, the GP2 timer loads the value
defined by Rx59 and starts counting down. The GP2
timer is reloaded at the occurrence of certain events
enabled in the GP Timer Reload Enable Register
(Power Management I/O Space Offset 38h). If no
such event occurs and the GP2 timer counts down to
zero, then the GP2 Timer Timeout Status bit is set to
one (bit-12 of the Global Status register at Power
Management Register I/O Space Offset 28h).
Additionally, if the GP2 Timer Timeout Enable bit is
set (bit-12 of the Global Enable register at Power
Management Register I/O Space Offset 2Ah), then an
SMI is generated.
2GP2 Timer Automatic Reload
0GP2 Timer stops at 0 .............................default
Offset D4 – SMBus Slave Address for Port 1 ................. RW
7-0SMBus Slave Address for P ort 1
...............default=0
Bit-0 must be set to 0 for proper operation
Offset D5 – SMBus Slave Address for Port 2 ................. RW
7-0SMBus Slave Address for P ort 2
...............default=0
Bit-0 must be set to 0 for proper operation
Offset D6 – SMBus Revision ID ....................................... RO
7-0SMBus Revision Code
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Power Management I/O-Space Registers
Basic Power Management Control and Status
VT82C686A
I/O Offset 1-0 - Power Management Status ................. RWC
The bits in this register are set only by hardware and can be
reset by software by writing a one to the desired bit position.
15Wakeup Status
(WAK_STS) ................... default = 0
This bit is set when the system is in the suspend state
and an enabled resume event occurs. Upon setting
this bit, the system automatically transitions from the
suspend state to the normal working state (from C3 to
C0 for the processor).
This bit is set when the RTC generates an alarm (on
assertion of the RTC IRQ signal).
9Sleep Button Status
(SB_STS)................. default = 0
This bit is set when the sleep button (SLPBTN# /
IRQ6 / GPI4) is pressed.
8Power Button Status
(PB_STS)............... default = 0
This bit is set when the PWRBTN# signal is asser ted
LOW. If the PWRBTN# signal is held LOW for
more than four seconds, this bit is cleared and the
system will transition into the soft off state.
This bit is set by hardware when BIOS_RLS is set
(typically by an SMI routine to release control of the
SCI/SMI lock). When this bit is cleared by software
(by writing a one to this bit position) the BIOS_RLS
bit is also cleared at the same time by hardware.
4Bus Master Status
(BM_STS) ................. default = 0
This bit is set when a system bus master requests the
system bus. All PCI master, ISA master and ISA
DMA devices are included.
This is a write-only bit; reads from this bit always
return zero. Writing a one to this bit causes the
system to sequence into the sleep (suspend) state
defined by the SLP_TYP field.
12-10 Sleep Type
(SLP_TYP)
000 Normal On
001 Suspend to RAM (STR)
010 Suspend to Disk (STD) (also called Soft Off).
The VCC power plane is turned off while the
VCCS and VBAT planes remain on.
011 Reserved
100 Power On Suspend without Reset
101 Power On Suspend with CPU Reset
110 Power On Suspend with CPU/PCI Reset
111 Reserved
In any sleep state, there is minimal interface between
powered and non-powered planes so that the effort
for hardware design may be well managed.
This bit is set by ACPI software to indicate the
release of the SCI / SMI lock. Upon setting of this
bit, the hardware automatically sets the BIOS_STS
bit. The bit is cleared by hardware when the
BIOS_STS bit is cleared by software. Note that the
setting of this bit will cause an SMI to be generated if
the BIOS_EN bit is set (bit-5 of the Global Enable
register at offset 2Ah).
1Generate SMI
Note that certain power management events can be
programmed individually to generate an SCI or SMI
independent of the setting of this bit (refer to the
General Purpose SCI Enable and General Purpose
SMI Enable registers at offsets 22 and 24). Also,
TMR_STS & GBL_STS always generate SCI and
BIOS_STS always generates SMI.
I/O Offset 0B-08 - Power Management Timer ............... RW
31-24 Extended Timer Value (ETM_VAL)
This field reads back 0 if the 24-bit timer option is
selected (Rx41 bit-3).
23-0 Timer Value (TMR_VAL)
This read -only field returns the running co unt of the
power management timer. This is a 24/32-bit counter
that runs off a 3.579545 MHz clock, and counts while
in the S0 (working) system state. The timer is reset to
an initial value of zero during a reset, and then
continues counting until the 14.31818 MHz input to
the chip is stopped. If the clock is restarted without a
reset, then the counter will continue counting from
where it stopped.
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Processor Power Management Registers
VT82C686A
I/O Offset 13-10 - Processor & PCI Bus Control............ RW
Setting this bit starts clock throttling (modulating the
STPCLK# signal) regar dless of the CPU state. The
throttling duty cycle is determined by bits 3-0 of this
register.
3-0Throttling Duty Cycle (THT_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the system is in throttling
mode (the "Throttling Enable" bit is set to one). The
duty cycle indicates the percentage of time the
STPCLK# signal is asserted while the Throttling
Enable bit is set. The field is decoded as follows:
Reads from this register put the processor into the
Stop Grant state (the VT82C686A asserts STPCLK#
to suspend the processor). Wake up from Stop Grant
state is by interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.
Reads from this register put the processor in the C3
clock state with the STPCLK# signal asserted. If
Rx10[9] = 1 then the CPU clock is also stopped by
asserting CPUSTP #. Wakeup from the C3 stat e is by
interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.
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General Purpose Power Management Registers
VT82C686A
I/O Offset 21-20 - General Purpose Status (GP_STS) . RWC
This bit is set when the BATLOW# input is asserted
low.
11Notebook Lid Status (LID_STS)
This bit is set when the LID input detects the edge
selected by Rx2C bit-7 (0=rising, 1=falling).
10Thermal Detect Status ( TH RM_STS)
This bit is set when the THRM input detects the edge
selected by Rx2C bit-6 (0=rising, 1=falling).
9USB Resume Status (USB_STS)
This bit is set when a USB peripheral generates a
resume event.
8Ring Status (RING_STS)
This bit is set when the RING# input is asserted low.
7GPI18 Toggle Status (GPI18_STS)
This bit is set when the GPI18 pin is toggled.
6GPI6 / EXTSMI6 Toggle Status (GPI6_STS)
This bit is set when the GPI6 pin is toggled.
5GPI5 Toggle Status (GPI5_STS)
This bit is set when the GPI5 pin is toggled.
4GPI4 / EXTSMI4 Toggle Status (GPI4_STS)
This bit is set when the GPI4 pin is toggled.
3GPI17 Toggle Status (GPI17_STS)
This bit is set when the GPI17 pin is toggled.
2GPI16 Toggle Status (GPI16_STS)
This bit is set when the GPI16 pin is toggled.
1GPI1 Toggle Status (GPI1_STS)
This bit is set when the GPI1 pin is toggled.
0EXTSMI# Status (EXT_STS)
This bit is set when the EXTSMI# pin is asserted low.
Note that the above bits correspond one for one with the bits
of the General Purpose SCI Enable and General Purpose SMI
Enable registers at offsets 22 and 24: an SCI or SMI is
generated if the corresponding bit of the General Purpose SCI
or SMI Enable registers, respectively, is set to one.
The above bits are set by hardware only and can only be
cleared by writing a one to the desired bit.
I/O Offset 23-22 - General Purpose SCI Enable ............ RW
15Reserved
14Enable SCI on setting of the UWAK_STS bit
13Enable SCI on setting of the AWAK_STS bit
12Enable SCI on setting of the BL_STS bit
11Ena ble SCI on setting of the LID_STS bit
10Enable SCI on setting of the THRM_STS bit
9Enable SCI on setting of the USB_STS bit
8Enable SCI on setting of the RING_STS bit
7Enable SCI on setting of the GPI18_STS bit
6Enable SCI on setting of the GPI6_STS bit
5Enable SCI on setting of the GPI5_STS bit
4Enable SCI on setting of the GPI4_STS bit
3Enable SCI on setting of the GPI17_STS bit
2Enable SCI on setting of the GPI16_STS bit
1Enable SCI on setting of the GPI1_STS bit
0Enable SCI on setting of the EXT_STS bit
These bits allow generation of an SCI using a separate set of
conditions from those used for generating an SMI.
I/O Offset 25-24 - General Purpose SMI Enable ........... RW
15-14 Reserved
13Enable SMI on setting of the AWAK_STS bit
12Enable SMI on setting of the BL_STS bit
11Ena ble SMI on setting of the LID_STS bit
10Enable SMI on setting of the THRM_STS bit
9Enable SMI on setting of the USB_STS bit
8Enable SMI on setting of the RING_STS bit
7Enable SMI on setting of the GPI18_STS bit
6Enable SMI on setting of the GPI6_STS bit
5Enable SMI on setting of the GPI5_STS bit
4Enable SMI on setting of the GPI4_STS bit
3Enable SMI on setting of the GPI17_STS bit
2Enable SMI on setting of the GPI16_STS bit
1Enable SMI on setting of the GPI1_STS bit
0Enable SMI on setting of the EXT_ STS bit