TABLE OF CONTENTS..................................................................................................................................................................II
LIST OF FIGURES..........................................................................................................................................................................III
LIST OF TABLES ...........................................................................................................................................................................IV
PCI to ISA Bridge Registers (Function 0) ..........................................................................................................................22
PCI Configuration Space Header.......................................................................................................................................................... 22
ISA Bus Control.................................................................................................................................................................................... 22
Plug and Play Control........................................................................................................................................................................... 25
Power Management............................................................................................................................................................................... 26
Enhanced IDE Controller Registers (Function 1)..............................................................................................................29
PCI Configuration Space Header.......................................................................................................................................................... 29
IDE I/O Registers..................................................................................................................................................................................33
Universal Serial Bus Controller Registers (Function 2)....................................................................................................34
PCI Configuration Space Header.......................................................................................................................................................... 34
USB I/O Registers................................................................................................................................................................................. 35
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VT82C586A
VT82C586A PIPC
PCI I
M
ASTER MODE
K
EYBOARD CONTROLLER AND REAL TIME CLOCK
NTEGRATED PERIPHERAL CONTROLLER
PC97 C
WITH
OMPLIANT
P
LUG AND PLAY
IDE C
•PC97 Compliant PCI to ISA Bridge
−
Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller
−
Integrated keyboard controller with PS2 mouse support
−
Integrated DS12885 style real time clock with extended 128 byte CMOS RAM
−
Integrated USB controller with root hub and two function ports
−
Integrated master mode enhanced IDE controller with enhanced PCI bus commands
−
PCI-2.1 compliant with delay transaction
−
Four double-word line buffer between PCI and ISA bus
−
Supports type F DMA transfers
−
Fast reset and Gate A20 operation
−
Edge trigger or level sensitive interrupt
−
Flash EPROM, 2MB EPROM and combined BIOS support
−
Programmable ISA bus clock
PCI-TO-ISA B
, USB C
ONTROLLER
RIDGE
ONTROLLER WITH ULTRA
,
DMA-33,
•Inter-operable with Intel and other Host-to-PCI Bridges
−
Combine with VT82C595 for a complete Pentium / PCI / ISA system (Apollo VP2)
−
Combine with VT82C685/687 for a complete Pentium-Pro /PCI / ISA system (Apollo P6)
−
Inter-operable with other Intel or non-Intel Host-to-PCI bridges for a complete PC97 compliant PCI/ISA system
•Enhanced Master Mode PCI IDE Controller with Extension to UltraDMA-33
−
Dual channel master mode PCI supporting four Enhanced IDE devices
−
Transfer rate up to 22MB/sec to cover PIO mode 4 and multi-word DMA mode 2 drives and beyond
−
Extension to UltraDMA-33 / ATA-33 interface for up to 33MB/sec transfer rate
−
Sixteen levels (doublewords) of prefetch and write buffers
−
Interlaced commands between two channels
−
Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
−
Full scatter and gather capability
−
Support ATAPI compliant devices
−
Support PCI native and ATA compatibility modes
−
Complete software driver support
•Universal Serial Bus Controller
−
USB v.1.0 and Intel Universal HCI v.1.1 compatible
−
Eighteen level (doublewords) data FIFO with full scatter and gather capability
−
Root hub and two function ports with integrated physical layer transceivers
−
Legacy keyboard and PS/2 mouse support
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Sophisticated Power Management
•
−
Normal, doze, sleep, suspend and conserve modes
−
System event monitoring with two event classes
−
One idle timer, one peripheral timer and one general purpose timer
−
More than ten general purpose input and output ports
−
Seven external event input ports with programmable SMI condition
−
Complete leakage control when external component is in power off state
−
Primary and secondary interrupt differentiation for individual channels
−
Clock stretching, clock throttling and clock stop control
−
Multiple internal and external SMI sources for flexible power management models
−
APM 1.2 compliant
−
Pin-compatible upgrade to VT82C586B for OnNow / ACPI (Advanced Configuration and Power Interface) powermanagement support, 256-byte extended CMOS, Distributed DMA, and I
Plug and Play Controller
•
−
PCI interrupts steerable to any interrupt channel
−
Dual interrupt and DMA channel controllers for on-board plug and play devices
−
Microsoft Windows 95
Built-in Nand-tree pin scan test capability
•
0.5um mixed voltage, high speed and low power CMOS process
•
TM
and plug and play BIOS compliant
2
C capabilities
VT82C586A
Single chip 208 pin PQFP
•
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O
VERVIEW
The VT82C586A PIPC (PCI Integrated Peripheral Controller) is a high integration, high performance and high compatibility
device that supports Intel and non-Intel based processor to PCI bus bridge to make a complete Microsoft PC97 compliant PCI/ISA
system. In addition to complete ISA extension bus functionality, the VT82C586A includes standard intelligent peripheral
controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT82C586A also supports the emerging UltraDMA-33
standard to allow reliable data transfer rates up to 33MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-95 compliant.
b) Universal Serial Bus controller that is USB v1.0 and Universal HCI v1.1 compliant. The VT82C586A includes the root hub
with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and
isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy
keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system
environment.
c) Keyboard controller with PS2 mouse support.
d) Real Time Clock with 128 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also
includes the date alarm and other enhancements for compatibility with the emerging ACPI standard.
VT82C586A
e) Notebook-class power management functionality including event monitoring, CPU clock throttling (Intel processor protocol),
power and leakage control, hardware- and software-based event handling, general purpose IO, chip select and external SMI.
The power management function supports legacy APM v1.2.
f) Plug and Play controller that allows complete steerability of all PCI interrupts to any interrupt channel. Two additional
interrupt and DMA channels are provided to allow plug and play and reconfigurability of on-board peripherals for Windows
95 compliance.
The VT82C586A also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both
edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to
standard ISA DMA modes. Compliant with the PCI-2.1 specification, the VT82C586A supports delayed transactions so that
slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without
causing dead lock even in a PCI-to-PCI bridge environment The chip also includes four levels (doublewords) of line buffers from
the PCI bus to the ISA bus to further enhance overall system performance.
Preliminary Revision 0.1 October 13, 1996-3-Overview
This signal is driven by the VT82C595 to grant PCI access to the
ISA Bus Control
B
System Address Bus/IDE Data Bus
System Address Bus
Multifunction Pins
ISA Bus Cycles:
Unlatched Address: The LA[23:17] address lines are bi-directional. These address
lines allow accesses to physical memory on the ISA bus up to 16MBytes.
PCI IDE Cycles:
Chip Select: DCS1A# is for the ATA command register block and corresponds to
CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register
block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the
ATA command register block and corresponds to CS17X# on the primary IDE
connector. DCS3B# is for the ATA command register block and corresponds to
CS37X# on the primary IDE connector.
Disk Address: DA[2:0] are used to indicate which byte in either the ATA command
block or control block is being accessed.
B
System Data.
the ISA bus.
System Byte High Enable.
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
I/O Read.
data on to the ISA data bus.
I/O Write.
latch data from the ISA data bus.
Memory Read.
onto the ISA data bus.
Memory Write.
from the ISA data bus.
Standard Memory Read.
1MB, which indicates that it may drive data onto the ISA data bus
Standard Memory Write.
1MB, which indicates that it may latch data from the ISA data bus.
Bus Address Latch Enable.
VT82C586A to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
16-Bit I/O Chip Select.
indicate that they support 16-bit I/O bus cycles.
Memory Chip Select 16.
low to indicate they support 16-bit memory bus cycles.
Multi-function Pin
1. Rx46h[2]=1 and Rx44h[0]=0:
2. Otherwise:
I/O Channel Check.
uncorrectable error has occurred for a device or memory on the ISA Bus.
I/O Channel Ready.
additional time (wait states) is required to complete the cycle.
Refresh.
an input REFRESH# is driven by 16-bit ISA Bus masters to indicate refresh cycle.
Address Enable.
misinterpreting DMA cycles as valid I/O cycles.
SD[15:8] provide the high order byte data path for devices residing on
SBHE# indicates, when asserted, that a byte is being
IOR# is the command to an ISA I/O slave device that the slave may drive
IOW# is the command to an ISA I/O slave device that the slave may
MEMR# is the command to a memory slave that it may drive data
MEMW# is the command to a memory slave that it may latch data
SMEMR# is the command to a memory slave, under
SMEMW# is the command to a memory slave, under
BALE is an active high signal asserted by the
This signal is driven by I/O devices on the ISA Bus to
ISA slaves that are 16-bit memory devices drive this line
IRQ12
MASTER#.
When this signal is asserted, it indicates that a parity or an
Devices on the ISA Bus negate IOCHRDY to indicate that
As an output REFRESH# indicates when a refresh cycle is in progress. As
AEN is asserted during DMA cycles to prevent I/O slaves from
ISA master cycle indicator
Preliminary Revision 0.1 October 13, 1996-6-Pinouts
ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU.
I
DMA Request.
VT82C586A’s DMA controller.
O
Multifunction Pins
Pin 135 (ROMCS#/KBCS#) strapped 1 at power up:
Normal Operation:
DMA service has been granted.
Power-up:
Pin 135 (ROMCS#/KBCS#) strapped 0 at power up:
Pin 60:
Other pins:
Multifunction Pin
Normal Operation:
Power-up Strapping:
The VT82C586A asserts TC to DMA slaves as a terminal count
The IRQ signals provide both system board components and
The DREQ lines are used to request DMA services from the
Acknowledge.
Strap Inputs.
DACEN.
To enable external 137 for decoding DACKs from XD0-2.
External SMI or General Purpose Inputs.
Speaker Drive.
0/1 = Fixed/flexible IDE I/O base
Strapped inputs stored in configuration register 96h.
The DACK output lines indicate a request for
The SPKR signal is the output of counter 2.
Enhanced IDE Interface
Disk I/O Read A.
Disk I/O Write A.
Disk I/O Read B.
Disk I/O Write B.
I/O Channel Ready A.
I/O Channel Ready B.
for UltraDMA/33 IDE interface).
System Address Transceiver Output Enable.
enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The
transceiver direction controls are driven by MASTER# with DD[15-0] connected to
the “A” side of the transceivers and SA[15-0] connected to the “B” side.
Disk DMA Request A.
Disk DMA Request B.
Disk DMA Acknowledge A.
Disk DMA Acknowledge B.
is used as a power-up strap option: 0/1 = Fixed/relocatable IDE I/O address
Primary IDE channel drive read strobe.
Primary IDE channel drive write strobe.
Secondary IDE channel drive read strobe.
Secondary IDE channel drive write strobe.
IDE drive ready indicator.
IDE drive ready indicator from the second channel (required
This signal controls the output
Primary IDE channel DMA request.
Secondary IDE channel DMA request.
Primary IDE channel DMA acknowledge.
Secondary IDE channel DMA acknowledge. This pin
Universal Serial Bus Interface
USB Port 0 Data +
USB Port 0 Data USB Port 1 Data +
USB Port 1 Data USB Clock.
Clock input for Universal serial bus interface
Keyboard Interface
Multifunction Pin.
Internal KBC enabled:
Internal KBC disabled:
Multifunction Pin.
Internal KBC enabled:
Internal KBC disabled:
Multifunction Pin.
PS/2 mouse enabled:
PS/2 mouse disable and internal KBC disabled:
IRQ 1 input from external KBC.
Function depends on enable/disable of internal KBC.
Keyboard Clock.
Gate A20:
Function depends on enable/disable of internal KBC.
Keyboard Data.
Keyboard Reset:
Function depends on enable/disable of internal KBC.
Mouse Clock.
Clock to keyboard interface.
Gate A20 output from external KBC
Data to keyboard interface.
Reset input from external KBC.
Clock to PS/2 mouse interface.
Interrupt Request 1.
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VT82C586A
MSDT / IRQ12111B
A20M147O
KEYLOCK106I
TURBO107I
RTCX1 /
IRQ8#
RTCX2/
RTCCS#
VBAT102I
VEXT103I
MDRQ091I
MDACK092O
MIRQ[1:0]88, 87I
XD[7:0]122-121, 119-
XDIR112O
RTCAS/
PCWE0
ROMCS# /
KBCS#
PCWE193O
EXTSMI#136I
APICCS#90I
104I
105O
116, 114-113
94O
135O
Multifunction Pin.
PS/2 mouse enabled:
PS/2 mouse disabled:
A20 Mask.
Keyboard Lock.
Turbo.
Direct connect A20 mask on CPU.
Turbo mode indicator input.
Function depends on enable/disable of internal KBC.
Mouse Data.
Interrupt Request 12.
Keyboard lock signal for internal keyboard controller.
transceiver that buffers the X-Bus data and ISA-Bus data (the output enable of the
transceiver should be grounded). SD0-7 connect to the “A” side of the transceiver
and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7.
Multifunction Pin
Internal RTC disabled:
directly to the address strobe input of the external RTC.
Internal RTC enabled:
an external 373 for general purpose outputs (SD15-8).
Multifunction Pin. ROM Chip Select / Keyboard Controller Chip Select.
Normal Operation:
ISA memory cycle:
ISA I/O cycle:
Power-up:
0: DACKn by external 137, DACK0 as
1: DACKn as
General Purpose Write Enable 1.
general purpose outputs (SD15-8).
. These pins are used as strap options during power-up:
XDIR is tied directly to the direction control of a 74F245
Real Time Clock Address Strobe
General Purpose Write Enable 0
ROMCS#.
KBCS#.
DACKn
Chip Select to the BIOS ROM.
Chip Select to the external keyboard controller.
DACEN
LATCH enable signal to an external 373 for
: RTCAS is connected
: LATCH enable signal to
, DACK1-3,5-7 as
Miscellaneous Control
External SMI.
External IOAPIC Chip Select.
External input to trigger SMI output to the CPU.
EXTSMI2-7
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VDD517, 34, 53, 79,
115
VDD3144I
VDD_PCI157, 171, 184,
198
AVDD100I
AGND101I
GND13, 26, 39, 52,
68, 84, 120,
140, 156, 166,
177, 188, 197,
208
Power and Ground
I
Power Supply.
Power Supply.
I
PCI Voltage.
USB Differential Output Power Source
USB Differential Output Ground
I
Ground
4.5 to 5.5V.
For the CPU Voltage.
3.3 or 5V
VT82C586A
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VT82C586A
R
EGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT82C586A. These tables also document the
power-on default value (“Default”) and access type (“Acc”) for
each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see individual
register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
C0-DFSlave DMA Controller0000 0000 110n nnnx
E0-FF-available for system use-0000 0000 111x xxxx
100-CF7-available for system useCF8-CFBPCI Configuration Address 0000 1100 1111 10xx
CFC-CFFPCI Configuration Data0000 1100 1111 11xx
D00-FFFF -available for system use-
Table 3. Registers
Legacy I/O Registers
PortMaster DMA Controller RegistersDefault Acc
00Channel 0 Base & Current AddressRW
01Channel 0 Base & Current CountRW
02Channel 1 Base & Current AddressRW
03Channel 1 Base & Current CountRW
04Channel 2 Base & Current AddressRW
05Channel 2 Base & Current CountRW
06Channel 3 Base & Current AddressRW
07Channel 3 Base & Current CountRW
08Status / CommandRW
09Write Request
0AWrite Single Mask
0BWrite Mode
0CClear Byte Pointer FF
0DMaster Clear
0EClear Mask
0FRead / Write MaskRW
PortMaster Interrupt Controller RegsDefault Acc
20Master Interrupt Control—*
21Master Interrupt Mask—*
20Master Interrupt Control Shadow—
9Programming Interface00RO
ASub Class Code01RO
BBase Class Code06RO
C-reserved- (cache line size
D-reserved- (latency timer
EHeader Type80RO
FBuilt In Self Test (BIST
† Power-up default value depends on external strapping
VT82C586A
WC
WC
00RW
RO
RO
RO
—
Configuration Space PCI-to-ISA Bridge-Specific Registers
Offset ISA Bus ControlDefaultAcc
40ISA Bus Control00RW
41Refresh and Port 9200RW
42ISA Clock Control00RW
43ROM Decode Control00RW
44Keyboard Controller Control00RW
45Type F DMA Control00RW
46Miscellaneous Control 100RW
47Miscellaneous Control 200RW
48Miscellaneous Control 301RW
49-reserved-00—
4AIDE Interrupt Routin
4B-reserved-00—
4CDMA / Master Mem Access Control 100RW
4DDMA / Master Mem Access Control 200RW
4F-4E DMA / Master Mem Access Control 30300RW
Offset Plug and Play ControlDefaultAcc
50PNP DRQ Routin
51-53 -reserved-00—
54PCI IRQ Edge / Level Selection00RW
55PNP IRQ Routing 100RW
56PNP IRQ Routing 200RW
57PNP IRQ Routing 300RW
04RW
24RW
Preliminary Revision 0.1 October 13, 1996-12-Register Overview
9Programming Interface85
ASub Class Code01RO
BBase Class Code01RO
C-reserved- (cache line size
DLatency Timer00RW
EHeader Type00RO
FBuilt In Self Test (BIST
13-10 Base Address - Pri Data / Command000001F0 RO
17-14 Base Address - Pri Control / Status000003F4 RO
1B-18 Base Address - Sec Data / Command00000170 RO
1F-1C Base Address - Sec Control / Status00000374 RO
23-20 Base Address - Bus Master Control0000CC01
24-2F -reserved- (unassigned
Offset Configuration Space IDE RegistersDefaultAcc
40Chip Enable08RW
41IDE Configuration02RW
42-reserved- (do not program
43FIFO Configuration3ARW
44Miscellaneous Control 168RW
45Miscellaneous Control 200RW
46Miscellaneous Control 3C0RW
Port CFF-CFC - Configuration Data .............................. RW
Refer to PCI Bus Specification Version 2.1 for further details
on operation of the above configuration registers.
Preliminary Revision 0.1 October 13, 1996-15-Configuration Space I/O
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VT82C586A
Register Descriptions
VIA-Specific I/O Ports
A8/A9 is a VIA-legacy I/O index/data pair. Chipset registers
in earlier VIA chipsets were accessed using this mechanism.
These registers are the only remaining functions accessed in
this way (norte: in future ACPI-capable versions of the
82C586A chip, access to these functions will be defined by
ACPI so the A8/A9 mechanism will no longer be used).
These functions are accessed by writing the indicated offset
(C8h or C9h) to I/O port A8h then writing the desired data to
I/O port A9h.
Port A8/A9 Offset C8h - General Purpose Output Port 0
These bits are controlled by PCW0 for latching data in an
external 373 latch. A 1-0-1 pulse is generated on PCW0 when
this port is written and the contents of this register appear on
the indicated bits of the ISA SD bus.
7-0SD15-8
Port A8/A9 Offset C9h - General Purpose Output Port 1
These bits are controlled by PCW1 for latching data in an
external 373 latch. A 1-0-1 pulse is generated on PCW1 when
this port is written and the contents of this register appear on
the indicated bits of the ISA SD bus.
7-0SD15-8
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All of
these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control ................. RW
7Reserved
6IOCHCK# Active
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register. Bit-3 should be cleared to
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
5Timer/Counter 2 Output
This bit reflects the output of Timer/Counter 2
without any synchronization.
4Refresh Detected
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
The keyboard controller handles the keyboard and mouse
interfaces. Two ports are used: port 60 and port 64. Reads
from port 64 return a status byte. Writes to port 64h are
command codes (see command code list following the register
descriptions). Input and output data is transferred via port 60.
A “Control” register is also available. It is accessable by
writing commands 20h / 60h to the command port (port 64h);
The control byte is written by first sending 60h to the
command port, then sending the control byte value. The
control register may be read by sending a command of 20h to
port 64h, waiting for “Output Buffer Full” status = 1, then
reading the control byte value from port 60h.
Traditional (non-integrated) keyboard controllers have an
“Input Port” and an “Output Port” with specific pins dedicated
to certain functions and other pins available for general
purpose I/O. Specific commands are provided to set these pins
high and low. All outputs are “open-collector” so to allow
input on one of these pins, the output value for that pin would
be set high (non-driving) and the desired input value read on
the input port. These ports are defined as follows:
1T1 - Mouse Clock In––
Note: Command code C0h transfers input port data to the
output buffer. Command code D0h copies output port values
to the output buffer. Command code E0h transfers test input
port data to the output buffer.
Port 60 - Keyboard Controller Input Buffer ................. WO
Only write to port 60h if port 64h bit-1 = 0 (1=full).
Port 60 - Keyboard Controller Output Buffer ................ RO
Only read from port 60h if port 64h bit-0 = 1 (0=empty).
Lo Code Hi Code
Lo Code Hi Code
Hi Code
Port 64 - Keyboard / Mouse Status .................................. RO
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Port 64 - Keyboard / Mouse Command .......................... WO
This port is used to send co mmands to the keyboard / mouse
controller. The command codes recognized by the
VT82C586A are listed n the table below.
Note: The VT82C586A Keyboard Controller is compatible
with the VIA VT82C42 Industry-Standard Keyboard
Controller except that due to its integrated nature, many of the
input and output port pins are not available externally for use
as general purpo se I/O pins (even though P 13-P16 are set on
power-up as strapping options). In other words, many of the
commands below are provided and “work”, but otherwise
perform no useful function (e. g., commands that set P12-P 17
high or low). Also note that setting P10-11, P22-23, P26-27,
and T0-1 high or lo w directly serves no useful purpose, sinc e
these bits are used to implement the keyboard and mouse ports
and are directly controlled by keyboard controller logic.
Table 4. Keyboard Controller Command Codes
VT82C586A
CodeKeyboard Command Code Description
20hRead Control Byte (next byte is Control Byte)
60hWrite Control Byte (next byte is Control Byte)
9xhWrite low nibble (bits 0-3) to P10-P13
A1hOutput Keyboard Controller Version #
A4hTest if Password is installed
(always returns F1h to indicate not installed)
A7hDisable Mouse Interface
A8hEnable Mouse Interface
A9hMouse Interface Test (puts test results in port 60h)
(value: 0=OK, 1=clk stuck low, 2=clk stuck high,
3=data stuck lo, 4=data stuck hi, FF=general error)
AAhKBC self test (returns 55h if OK, FCh if not)
ABhKeyboard Interface Test (see A9h Mouse Test)
ADhDisable Keyboard Interface
AEhEnable Keyboard Interface
AFhReturn Version #
B0hSet P10 low
B1hSet P11 low
B2hSet P12 low
B3hSet P13 low
B4hSet P22 low
B5hSet P23 low
B6hSet P14 low
B7hSet P15 low
B8hSet P10 high
B9hSet P11 high
BAhSet P12 high
BBhSet P13 high
BChSet P22 high
BDhSet P23 high
BEhSet P14 high
BFhSet P15 high
CodeKeyboard Command Code Description
C0hRead input port (read P10-17 input data to
the output buffer)
C1hPoll input port low (read input data on P11-13
repeatably & put in bits 5-7 of status
C2hPoll input port high (same except P15-17)
C8hUnblock P22-23 (use before D1 to change
active mode)
C9hReblock P22-23 (protection mechanism for D1)
CAhRead mode (output KBC mode info to port 60
output buffer (bit-0=0 if ISA, 1 if PS/2)
D0hRead Output Port (copy P10-17 output port values
to port 60)
D1hWrite Output Port (data byte following is written to
keyboard output port as if it came from keyboard)
D2hWrite Keyboard Output Buffer & clear status bit-5
(write following byte to keyboard)
D3hWrite Mouse Output Buffer & set status bit-5 (write
following byte to mouse; put value in mouse input
buffer so it appears to have come from the mouse)
D4hWrite Mouse (write following byte to mouse)
E0hRead test inputs (T0-1 read to bits 0-1 of resp byte)
ExhSet P23-P21 per command bits 3-1
FxhPulse P23-P20 low for 6usec per command bits 3-0
All other codes not listed are undefined.
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VT82C586A
DMA Controller I/O Registers
Ports 00-0F - Master DMA Controller
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0Register Name
0000 0000 000x 0000Ch 0 Base / Current AddressRW
0000 0000 000x 0001Ch 0 Base / Current CountRW
0000 0000 000x 0010Ch 1 Base / Current AddressRW
0000 0000 000x 0011Ch 1 Base / Current CountRW
0000 0000 000x 0100Ch 2 Base / Current AddressRW
0000 0000 000x 0101Ch 2 Base / Current CountRW
0000 0000 000x 0110Ch 3 Base / Current AddressRW
0000 0000 000x 0111Ch 3 Base / Current CountRW
0000 0000 000x 1000Status / CommandRW
0000 0000 000x 1001Write RequestWO
0000 0000 000x 1010Write Single MaskWO
0000 0000 000x 1011Write ModeWO
0000 0000 000x 1100Clear Byte Pointer F/FW O
0000 0000 000x 1101Master ClearWO
0000 0000 000x 1110Clear MaskWO
0000 0000 000x 1111R/W All Mask BitsRW
Note that not all bits of the address are decoded.
The Master DMA Controller is compatible with the Intel 8237
DMA Controller chip. Detailed descriptions of 8237 DMA
Controller operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0Register Name
0000 0000 1100 000xCh 0 Base / Current AddressRW
0000 0000 1100 001xCh 0 Base / Current CountRW
0000 0000 1100 010xCh 1 Base / Current AddressRW
0000 0000 1100 011xCh 1 Base / Current CountRW
0000 0000 1100 100xCh 2 Base / Current AddressRW
0000 0000 1100 101xCh 2 Base / Current CountRW
0000 0000 1100 110xCh 3 Base / Current AddressRW
0000 0000 1100 111xCh 3 Base / Current CountRW
0000 0000 1101 000xStatus / CommandRW
0000 0000 1101 001xWrite RequestWO
0000 0000 1101 010xWrite Single MaskWO
0000 0000 1101 011xWrite ModeWO
0000 0000 1101 100xClear Byte Pointer F/FWO
0000 0000 1101 101xMaster ClearWO
0000 0000 1101 110xClear MaskWO
0000 0000 1101 111xRead/Write All Mask BitsWO
Note that not all bits of the address are decoded.
The Slave DMA Controller is compatible with the Intel 8237
DMA Controller chip. Detailed description of 8237 DMA
controller operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting bit 4 of
Rx47 to 1 (offset 47h in the PCI-ISA Bridge function 0
register group). If the shadow registers are enabled, they are
read back at the indicated I/O port instead of the standard
interrupt controller registers (writes to the interrupt controller
register ports are directed to the standard interrupt controller
registers).
Port 20 - Master Interrupt Control Shadow ................... RO
7-5Reserved
4OCW3 bit 5
3OCW2 bit 7
2ICW4 bit 4
1ICW4 bit 1
0ICW1 bit 3
Port 21 - Master Interrupt Mask Shadow ....................... RO
7-5Reserved
4-0T7-T3 of Interrupt Vector Address
Port A0 - Slave Interrupt Control Shadow ..................... RO
7-5Reserved
4OCW3 bit 5
3OCW2 bit 7
2ICW4 bit 4
1ICW4 bit 1
0ICW1 bit 3
Port A1 - Slave Interrupt Mask Shadow ........................ RO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
CMOS / RTC Registers
Port 70 - CMOS Address ................................................. WO
Port 71 - CMOS Data ....................................................... RW
7-0CMOS Data
Note:The system Real Time Clock (RTC) is part of the
“CMOS” block. The RTC control registers are
located at specific offsets in the CMOS data area.
Detailed descriptions of CMOS / RTC operation and
programming can be obtained from the VIA
VT82887 Data Book or numerous other industry
publications.
........................................................ WO
encountering IOCHCK# on the ISA bus or
SERR# on the PCI bus.
(128 bytes)................................ WO
(128 bytes)
Preliminary Revision 0.1 October 13, 1996-21-Register Descriptions
Page 28
9,$7HFKQRORJLHV,QF
VT82C586A
PCI to ISA Bridge Registers (Function 0)
All registers are located in the function 0 PCI configuration
space of the VT82C586A. These registers are accessed
through PCI configuration mechanism #1 via I/O address
CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h ......................................... RO
Offset 3-2 - Device ID = 0586h .......................................... RO
Offset 45 - Type F DMA Control ..................................... RW
7ISA Master / DMA to PCI Line Buffer
6DMA type F Timing on Channel 7
5DMA type F Timing on Channel 6
4DMA type F Timing on Channel 5
3DMA type F Timing on Channel 3
2DMA type F Timing on Channel 2
1DMA type F Timing on Channel 1
0DMA type F Timing on Channel 0
Note:All ISA DMA / Masters that access addresses higher
than the top of PCI memory will not be directed to the
PCI bus.
11Forward E0000-EFFFF Accesses to PCI
10Forward A0000-BFFFF Accesses to PCI
9Forward 80000-9FFFF Accesses to PCI
8Forward 00000-7FFFF Accesses to PCI
7Forward DC000-DFFFF Accesses to PCI
6Forward D8000-DBFFF Accesses to PCI
5Forward D4000-D7FFF Accesses to PCI
4Forward D0000-D3FFF Accesses to PCI
3Forward CC000-CFFFF Accesses to PCI
2Forward C8000-CBFFF Accesses to PCI
1Forward C4000-C7FFF Accesses to PCI
0Forward C0000-C3FFF Accesses to PCI
for ISA DMA/Master accesses
(HA[23:16])
........def=0
.......def=0
........ def=1
........ def=1
......def=0
...... def=0
....... def=0
....... def=0
.....def=0
...... def=0
....... def=0
....... def=0
Preliminary Revision 0.1 October 13, 1996-24-Register Descriptions
(same as PIRQD# routing)...def=0
(same as PIRQD# routing)...def=0
(same as PIRQD# routing)...def=0
(same as PIRQD# routing) ....def=0
Preliminary Revision 0.1 October 13, 1996-25-Register Descriptions
Page 32
9,$7HFKQRORJLHV,QF
VT82C586A
Power Management
Refer to VIA application note AP-053 (“APM-Compliant
Power Management Model of the VT82C586A”) for
additional information on power mangement programming.
Offset 82 - Primary Activity Detect Status ................... RWC
These bits correspond to the activity detect enable bits above.
7Keyboard Controller Access Status
6Serial Port Access Status
5Parallel Port Access Status
4Video IO/Memory Access Status
3DRV (HDD/Floppy) Access Status
2Turbo Pin Toggle Status
1Primary INTR Activity Status
0DMA/Master Activity Status
Preliminary Revision 0.1 October 13, 1996-26-Register Descriptions
.......................... default=0
....................... default=0
........................... default=0
.......... default=0
............. default=0
.......... default=0
................. default=0
................... default=0
Page 33
9,$7HFKQRORJLHV,QF
VT82C586A
Offset 88 - Timer Control 1 .............................................. RW
7GP1 Timer Enable
6GP1 Timer Auto Reload After Count to 0
01 Time base = 10 msec
10 Time base = 1 second
11 Time base = 1 minute
Offset 89 - Timer Control 2 .............................................. RW
7-0GP0 Timer Load Value
Offset 8A - Timer Control 3 ............................................. RW
7-0GP1 Timer Load Value
Offset 8B - GP Timer Reload Enable .............................. RW
7-5Reserved
The following bits all default to 0 on power up:
4GP0 Timer Enable Reload on Primary Activity
3GP1 Timer Enable Reload on HDD/Floppy Access
2GP1 Timer Enable Reload on Video Access
1GP1 Timer Enable Reload on Serial Port Access
0GP1 Timer Enable Reload on KBC Access
Preliminary Revision 0.1 October 13, 1996-27-Register Descriptions
Page 34
9,$7HFKQRORJLHV,QF
VT82C586A
The following 4 registers all default to 00 at power-up (all
events disabled):
Offset 90 - ISA IRQ 7-0 as Primary Event ...................... RW
7-0IRQ7-0
Offset 91 - ISA IRQ 15-8 as Primary Event .................... RW
7-0IRQ15-8
Offset 92 - ISA IRQ 7-0 as Secondary Event .................. RW
7-0IRQ7-0
Offset 93 - ISA IRQ15-8 as Secondary Event ................. RW
7-0IRQ15-8
Offset 94 - External SMI Pin Status ................................. RO
7EXTSMI7 Pin Status
6EXTSMI6 Pin Status
5EXTSMI5 Pin Status
4EXTSMI4 Pin Status
3EXTSMI3 Pin Status
2EXTSMI2 Pin Status
1EXTSMI Pin Status
0TURBO Pin Status
1Disable external SMI on EXTSMI2-7
EXTSMI2-7 are on the same pins as DAC1-3,5-7
(pins 18, 33, 31, 58, 131, and 133) (see pin
definitions for more information)
0IDE Addressing
0Fixed
1Flexible
See also IDE offset 9 bits 0-3 for more information
Note:External strap option values may be set by connecting
the indicated external pin to a 4.7K ohm pullup (for
1) or drive it low during reset with a 7407 TTL open
collector buffer (for 0) as shown in the suggested
circuit below:
............................ latched from XD7
........................... latched from XD6
........................... latched from XD5
........................... latched from XD4
................................. latched from XD3
.................... latched from XD2
......... latched from XD1
................... latched from XD0
............latched from DACK7 (pin 133)
............latched from DACK6 (pin 131)
..............latched from DACK5 (pin 58)
..............latched from DACK3 (pin 31)
..............latched from DACK2 (pin 33)
..............latched from DACK1 (pin 18)
...latched from ROMCS# (pin 135)
........... latched from SPKR (pin 134)
9&&
5(6(7
9&&
.
;'
Figure 2. Strap Option Circuit
Preliminary Revision 0.1 October 13, 1996-28-Register Descriptions
Page 35
9,$7HFKQRORJLHV,QF
VT82C586A
Enhanced IDE Controller Registers (Function 1)
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT82C586A. The Bus Master IDE I/O registers are defined
in the SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO
Offset 3-2 - Device ID (0571h=IDE Controller) ............... RO
Offset 8 - Secondary Channel Command
Offset A - Secondary Channel Status
Offset C-F - Secondary Channel PRD Table Address
VT82C586A
Preliminary Revision 0.1 October 13, 1996-33-Register Descriptions
Page 40
9,$7HFKQRORJLHV,QF
VT82C586A
Universal Serial Bus Controller Registers (Function 2)
This USB host controller interface is fully compatible with
UHCI specification v1.1. There are two sets of software
accessible registers: PCI configuration registers and USB I/O
registers. The PCI configuration registers are located in the
function 2 PCI configuration space of the VT82C586A. The
USB I/O registers are defined in the UHCI v1.1 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
0-7Vendor ID
Offset 3-2 - Device ID ......................................................... RO
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
Offset 1-0 - USB Command
Offset 3-2 - USB Status
Offset 5-4 - USB Interrupt Enable
Offset 7-6 - Frame Number
Offset B-8 - Frame List Base Address
Offset 0C - Start Of Frame Modify
Offset 11-10 - Port 1 Status / Control
Offset 13-12 - Port 2 Status / Control
Offset 41 - Miscellaneous Control 2 ................................. RW
7-3Reserved
2Trap Option
0Set trap 60/64 status bits without checking
1Set trap 60/64 status bits only when trap 60/64
1A20gate Pass Through Option
0Pass through A20GATE command sequence
1Don’t pass through Write I/O port 64 (ff)
0Reserved
Offset 60 - Serial Bus Release Number ............................. RO
7-0Release Number
Offset C1-C0 - Legacy Support ......................................... RO
Note: Stress above the conditions listed may cause permanent damage to the
device. Functional operation of this device should be restricted to the
conditions described under operating conditions.
DC Characteristics
TA-0-70oC, VDD=5V+/-5%, GND=0V
SymbolParameterMinMaxUnitCondition
V
IL
V
IH
V
OL
V
OH
I
IL
I
OZ
I
CC
Input low voltage-0.500.8V
Input high voltage2.0VDD+0.5V
Output low voltage-0.45VIOL=4.0mA
Output high voltage2.4-VIOH=-1.0mA
Input leakage current-+/-10uA0<VIN<V
Tristate leakage current-+/-20uA0.45<V
Power supply current-80mA
+ 0.5Volts
DD
DD
OUT<VDD
Preliminary Revision 0.1 October 13, 1996-36-Electrical Specifications