Datasheet VT8231 Datasheet (VIA)

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EVISION HISTORY

Document Release Date Revision Initials

Revision 0.4 9/17/99 Initial release based on 82C686A “Super South” Data Sheet revision 1.42

Updated feature bullets, document title, and block diagram Replaced pinout diagram with blank BGA352 template Added LAN, LPC, and EEPROM pin descriptions, removed signals as req’d

Updated Functions 5 and 6 per engineering input Revision 0.5 9/27/99 Added Preliminary Ballout & Mechanical Spec DH Revision 0.6 10/1/99 Updated pin descriptions and pin lists DH Revision 0.7 10/15/99 Updated pinouts to conform to engineering pinout revision 0.4 dated 10/6/99 DH Revision 0.8 10/29/99 Updated feature bullets and performed partial edit of Overview text

Updated pinouts per engineering pinout rev 0.6 / pinlist rev 0.2 dated 10/20/99

Updated Electrical Specs and added “output drive” and “input voltage” tables

VT8231

Preliminary Revision 0.8 October 29, 1999 -i- Revision History

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ABLE OF CONTENTS

VT8231

REVISION HISTORY........................................................................................................................................................................I

TABLE OF CONTENTS..................................................................................................................................................................II

LIST OF FIGURES..........................................................................................................................................................................IV

LIST OF TABLES...........................................................................................................................................................................IV

OVERVIEW.......................................................................................................................................................................................5

PINOUTS............................................................................................................................................................................................7

IN DIAGRAM

.................................................................................................................................................................................7

IN LISTS

IN DESCRIPTIONS

........................................................................................................................................................................................8

.......................................................................................................................................................................10

REGISTERS.....................................................................................................................................................................................29

EGISTER OVERVIEW

EGISTER DESCRIPTIONS

.................................................................................................................................................................29

............................................................................................................................................................41

Legacy I/O Ports...................................................................................................................................................................41

Keyboard Controller Registers.............................................................................................................................................................. 42

DMA Controller I/O Registers.............................................................................................................................................................. 44

Interrupt Controller Registers ............................................................................................................................................................... 45

Timer / Counter Registers..................................................................................................................................................................... 45

CMOS / RTC Registers......................................................................................................................................................................... 46

Super-I/O Configuration Index / Data Registers...............................................................................................................47

Super-I/O Configuration Registers.....................................................................................................................................47

Super-I/O I/O Ports..............................................................................................................................................................50

Floppy Disk Controller Registers.......................................................................................................................................................... 50

Parallel Port Registers........................................................................................................ ................................................................... 51

Serial Port 1 Registers........................................................................................................................................................................... 52

Serial Port 2 Registers........................................................................................................................................................................... 53

SoundBlaster Pro Port Registers.........................................................................................................................................54

FM Registers......................................................................................................................................................................................... 54

Mixer Registers .....................................................................................................................................................................................54

Sound Processor Registers ....................................................................................................................................................................54

Game Port Registers............................................................................................................................................................. 55

PCI Configuration Space I/O...............................................................................................................................................56

Function 0 Registers - PCI to ISA Bridge...........................................................................................................................57

PCI Configuration Space Header.......................................................................................................................................................... 57

ISA Bus Control.................................................................................................................................................................................... 57

Plug and Play Control........................................................................................................................................................................... 61

Distributed DMA / Serial IRQ Control.................................................................................................................................................63

Miscellaneous / General Purpose I/O.................................................................................................................................................... 64

Function 1 Registers - Enhanced IDE Controller..............................................................................................................69

PCI Configuration Space Header.......................................................................................................................................................... 69

IDE-Controller-Specific Confiiguration Registers................................................................................................................................ 71

IDE I/O Registers.................................................................................................................................................................................. 76

Function 2 Registers - USB Controller Ports 0-1...............................................................................................................77

PCI Configuration Space Header.......................................................................................................................................................... 77

USB-Specific Configuration Registers..................................................................................................................................................78

USB I/O Registers................................................................................................................................................................................. 79

Function 3 Registers - USB Controller Ports 2-3...............................................................................................................80

PCI Configuration Space Header.......................................................................................................................................................... 80

USB-Specific Configuration Registers..................................................................................................................................................81

USB I/O Registers................................................................................................................................................................................. 82

Preliminary Revision 0.8 October 29, 1999 -ii- Table of Contents

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VT8231

Function 4 Regs - Power Management, SMBus and HWM..............................................................................................83

PCI Configuration Space Header.......................................................................................................................................................... 83

Power Management-Specific PCI Configuration Registers .................................................................................................................. 84

Hardware-Monitor-Specific Configuration Registers ........................................................................................................................... 91

System Management Bus-Specific Configuration Registers................................................................................................................. 91

Power Management I/O-Space Registers ..............................................................................................................................................92

System Management Bus I/O-Space Registers.................................................................................................................................... 101

Hardware Monitor I/O Space Registers .............................................................................................................................................. 104

Function 5 & 6 Registers - AC97 Audio & Modem Codecs............................................................................................108

PCI Configuration Space Header – Function 5 Audio........................................................................................................................ 108

PCI Configuration Space Header – Function 6 Modem...................................................................................................................... 109

Function 5 & 6 Codec-Specific Configuration Registers....................................................................................................................110

Function 5 I/O Base 0 Regs – DXSn Scatter/Gather DMA................................................................................................................. 112

Function 5 I/O Base 1 Registers –Audio FM NMI Status................................................................................................................... 117

Function 5 I/O Base 2 Registers –MIDI / Game Port.......................................................................................................................... 117

Function 6 I/O Base 0 Regs –Modem Scatter/Gather DMA............................................................................................................... 118

FUNCTIONAL DESCRIPTIONS................................................................................................................................................120

OWER MANAGEMENT

Power Management Subsystem Overview.......................................................................................................................................... 120

Processor Bus States........................................................................................................................................................................... 120

System Suspend States and Power Plane Control............................................................................................................................... 121

General Purpose I/O Ports...................................................................................................................................................................121

Power Management Events................................................................................................................................................................. 122

System and Processor Resume Events................................................................................................................................................ 122

Legacy Power Management Timers.................................................................................................................................................... 123

System Primary and Secondary Events............................................................................................................................................... 123

Peripheral Events................................................................................................................................................................................ 123

..............................................................................................................................................................120

ELECTRICAL SPECIFICATIONS.............................................................................................................................................124

BSOLUTE MAXIMUM RATINGS

HARACTERISTICS

DC C

UTPUT DRIVE

NPUT VOLTAGE

..........................................................................................................................................................................125

..............................................................................................................................................................124

........................................................................................................................................................................125

...............................................................................................................................................124

PACKAGE MECHANICAL SPECIFICATIONS......................................................................................................................126

Preliminary Revision 0.8 October 29, 1999 -iii- Table of Contents

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IST OF FIGURES

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT8231......................................................................................... 6

FIGURE 2. VT8231 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 7

FIGURE 3. VT8231 PIN LIST (NUMERICAL ORDER)............................................................................................................. 8

FIGURE 4. VT8231 PIN LIST (ALPHABETICAL ORDER)......................................................................................................9

FIGURE 5. STRAP OPTION CIRCUIT.......................................................................................................................................62

FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM.........................................................................120

FIGURE 8. MECHANICAL SPECIFICATIONS – 376 PIN BALL GRID ARRAY PACKAGE.........................................126

IST OF TABLES

TABLE 1. PIN DESCRIPTIONS...................................................................................................................................................10

TABLE 2. SYSTEM I/O MAP.......................................................................................................................................................29

TABLE 3. REGISTERS..................................................................................................................................................................30

TABLE 4. KEYBOARD CONTROLLER COMMAND CODES ..............................................................................................43

TABLE 5. CMOS REGISTER SUMMARY.................................................................................................................................46

VT8231

Preliminary Revision 0.8 October 29, 1999 -iv- Table of Contents

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VT8231

SOUTH BRIDGE

PC99 COMPLIANT

INTEGRATED SUPER-I/O (FDC, LPT, COM, AND FIR),

NTEGRATED FAST ETHERNET, LPC, ISA / LPC BIOS ROM,

NTEGRATED SOUNDBLASTER PRO / MULTICHANNEL

DIRECT SOUND AC97 AUDIO AND MC97 MODEM INTERFACE,

LTRADMA-33/66/100 MASTER MODE EIDE CONTROLLER,

ORT USB CONTROLLER, KEYBOARD CONTROLLER, RTC,

4 P

ERIAL IRQ, SMBUS, SERIAL EEPROM,

LUG AND PLAY, ACPI, ENHANCED POWER MANAGEMENT,

EMPERATURE, VOLTAGE, AND FAN-SPEED MONITORING

VT8231

• Inter-operable with VIA and other Host-to-PCI Bridges

−

Combine with VT82C598 for a complete Super-7 (66 / 75 / 83 / 100MHz) AGP 2x system (Apollo MVP3)

−

Combine with VT8501 for a complete Super-7 system with integrated 2D / 3D graphics (Apollo MVP4)

−

Combine with VT82C694X for a complete 66 / 100 / 133 MHz Socket370 / Slot1 AGP 4x system (Apollo Pro133A)

−

Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket370 / Slot1 system with integrated 2D / 3D graphics (Apollo ProMedia)

−

Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI / AGP / LPC system

• Integrated Peripheral Controllers

−

Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability

−

Integrated USB Controller with two root hub and four function ports

−

Dual channel UltraDMA-33 / 66 /100 master mode EIDE controller

−

AC-link interface for AC-97 audio codec and modem codec

−

HSP modem support

−

Interface for optional external modem DSP

−

Integrated SoundBlasterPro / DirectSound compatible digital audio controller

−

LPC interface for Low Pin Count interface to Super-I/O or ROM

• Integrated Legacy Functions

−

Integrated Keyboard Controller with PS2 mouse support

−

Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI

−

Integrated Bus Controller including DMA, timer, and interrupt controller

−

Serial IRQ for docking and non-do cking applications

−

Flash EPROM, 32Mbit (4Mbyte) EPROM and combined BIOS support

−

Fast reset and Gate A20 operation

Preliminary Revision 0.8 October 29, 1999 -1- Features

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• Fast Ethernet Controller

−

High performance PCI master interface with scatter / gather and bursting capability

−

Standard MII interface to PHYceiver

−

1 / 10 / 100 MHz full and half duplex operation

−

Transmit data buffer byte alignment for low CPU utilization

−

Separate 2K byte FIFOs for receive and transmit of full Ethernet packets

−

Flexible dynamically loadable EEPROM algorithm

−

Physical, Broadcast, and Multicast address filtering using hashing function

−

Flexible wakeup events: link status change, magic packet, unicast physical address match, predefined pattern match

−

Software controllable power down

• UltraDMA-33 / 66 / 100 Master Mode PCI EIDE Controller

−

Dual channel master mode PCI supporting four Enhanced IDE devices

−

Transfer rate up to 100MB/sec to cover up to PIO mode 4, multi-word DMA mode 2, and UltraDMA mode 5

−

Thirty-two levels (doublewords) of prefetch and write buffers per channel

−

Dual DMA engine for concurrent dual channel operatio n

−

Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 / 98 / 2000 compliant

−

Full scatter gather capability

−

Support ATAPI compliant devices including DVD devices

−

Support PCI native and ATA compatibility modes

−

Complete software driver support

VT8231

• Integrated Super IO Controller

−

Supports 2 serial ports, IR port, parallel port, and floppy disk controller functions

−

Two UARTs for Complete Serial Ports Programmable character lengths (5,6,7,8) Even, odd, stick or no parity bit generation and detection Programmable baud rate generator High speed baud rate (230Kbps, 460Kbps) support Independent transmit/receiver FIFOs Modem Control Plug and play with 96 base IO address and 12 IRQ options

−

Fast IR (FIR) port IrDA 1.0 SIR and IrDA 1.1 FIR compliant IR function through the second serial port Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR

−

Multi-mode parallel port Standard mode, ECP and EPP support Dynamic and static switch between parallel port pinout and FDC pinout Plug and play with 192 base IO address, 12 IRQ and 4 DMA options

−

Floppy Disk Controller 16 bytes of FIFO Data rates up to 1Mbps Perpendicular recording driver support Two FDDs with drive swap support Plug and play with 48 base IO address, 12 IRQ and 4 DMA options

Preliminary Revision 0.8 October 29, 1999 -2- Features

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• SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller

−

Up to six concurrent AC97 output channels for six-speaker surround sound experience

−

Multiple Direct Sound channels between system memory and AC97 link 10 Direct Sound output channels 4 Direct Sound input channels 8-channel hardware sample-rate-converter / mixer 1 Surround Sound channel of up to six data st reams

−

PCI bus master interface with scatter / gather and bursting capability

−

32 byte FIFO for each direct sound channel

−

Host based wave table synthesis

−

Standard v1.03 or v2.1 AC97 Codec interface with up to four AC97 codec’s from multiple vendors

−

Loopback capability for re-directing mixed audio streams into USB and 1394 speakers

−

Hardware SoundBlaster Pro for legacy compatibility

−

Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware

−

Hardware assisted FM synthesis for legacy compatibility

−

Direct two game ports and one MIDI port interface

−

Complete software driver support for Windows-95 / 98 / 2000 and Windows-NT

• MC97 HSP Modem Controller

−

PCI bus master interface with scatter / gather and burst capability

−

Standard AC97 codec interface for MC or AMC codec

−

Wake on ring in APM or ACPI mode through AC97 link

−

Supported by most HSP modem vendors

VT8231

• Universal Serial Bus Controller

−

USB v.1.1 and Intel Universal HCI v.1.1 compatible

−

Eighteen level (doublewords) data FIFO with full scatter and gather capability

−

Root hub and four function ports

−

Integrated physical layer transceivers with optional over-current detection status on USB inputs

−

Legacy keyboard and PS/2 mouse support

• System Management Bus Interface

−

One master / slave SMBus and one slave-only SMBus

−

Host interface for processor communications

−

Slave interface for external SMBus masters

Preliminary Revision 0.8 October 29, 1999 -3- Features

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• Voltage, Temperature, Fan Speed Monitor and Controller

−

Five universal input channels for voltage or temperature sensing

−

Two fan-speed moni toring channels

−

Input channel for thermal diode in Intel™ high speed Pentium II™ / Pentium III™ CPUs

−

Programmable control, status, monitor and alarm for flexible desktop management

−

External thermister or internal bandgap temperature sensing

−

Automatic clock throttling with integrated temperature sensing

−

Internal core VCC voltage sensing

−

Flexible external voltage sensing arrangement (any positive supply and battery)

• Sophisticated PC99-Compatible Mobile Power Management

−

Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management

−

ACPI v1.0 Compliant

−

APM v1.2 Compli ant

−

CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support

−

PCI bus cloc k run, Power Management Enable (PME) control, and PCI/CPU c lock generator stop control

−

Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options, suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up

−

Multiple suspend power plane controls and suspend status indicators

−

One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer

−

Normal, doze, sleep, suspend and conserve modes

−

Global and local device power control

−

System event monitoring with two event classes

−

Primary and secondary interrupt differentiation for individual channels

−

Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for system wake-up

−

Multiple internal and external SMI sources for flexible power management models

−

One programmable chip select and one microcontroller chip select

−

Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field

−

Thermal alarm on either external or any combination of three internal temperature sensing circuits

−

Hot docking support

−

I/O pad leakage control

VT8231

• Plug and Play Controller

−

PCI interrupts steerable to any interrupt channel

−

Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI

−

Steerable DMA channels for integrated floppy, parallel, and soundblaster pro controllers

−

One additional steerable interrupt channel for on-board plug and play devices

−

Microsoft Windows 2000TM, Windows 98SETM, Windows 98TM, Windows NTTM, Windows 95 BIOS compliant

and plug and play

• Built-in NAND-tree pin scan test capability

• 0.30um, 3.3V, low power CMOS process

• Single chip 27x27 mm, 376 pin BGA

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VERVIEW

The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI / LPC system. The VT8231 includes standard intelligent peripheral controllers:

a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated

FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100 standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external PHY. The LAN

controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex operation and has separate 2Kbyte FIFOs for receive and transmit of full ethernet packets. The internal high-performance PCI interface has scatter / gather and bursting capability and can align bytes in the transmit data buffer to reduce CPU utilization. The LAN interface can perform address filtering on physical, broadcast, and multicast packets. The interface can also be configured for system wake up on link status change, receipt of magic packet, unicast physical address match on incoming packets, and predefined pattern

match in the incoming data. c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with

four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous

peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and

mouse support so that legacy software can run transparently in a non-USB-aware operating system environment. e) Keyboard controller with PS2 mouse support f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also includes

the date alarm, century field, and other enhancements for compatibility with the ACPI standard. g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states

(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional

functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI b us clock sto p co ntrol,

modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip

select and external SMI. h) Hardware monitoring subsystem for managing system / motherb oard voltage level s , temperatures, and fa n speeds i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port j) 16550-compatible serial I/O port with “Fast-IR” infrared communications port option. k) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro and

hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is

also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio. l) Game port and MIDI port m) Standard floppy disk drive interface n) ECP/EPP-capable parallel port with floppy disk controller pinout option o) Serial IRQ for docking and non-docking applications p) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts to any interrupt channel.

One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-board peripherals for

Windows family compliance.

VT8231

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VT8231

CPU / Cache

Sideband Signals:

Init / CPUre s et

IRQ / NMI

SMI / StopClk

FERR / IGNNE

SLP# (Slot-1)

Boot ROM

Onboard LPC I/O

LPC

RTC Crystal

CA CD

North Bridge

VT8231

376 BGA

MA/Command

PCI

SMB USB Ports 0-3

Keyboard / Mouse MIDI / Game Ports Parallel Port Serial Ports 1 and 2 Infrared Comm Port IDE Primary and Secondary Floppy Disk Interface AC97 Lin k Hardware Monitor Inputs GPIO, Power Cont rol, Reset Fast Ethernet Interface

Figure 1. PC System Configuration Using the VT8231

System Memory

DIMM Module ID

Expansion

Cards

Preliminary Revision 0.8 October 29, 1999 -6- Overview

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INOUTS

VT8231

Pin Diagram

Figure 2. VT8231 Ball Diagram (Top View)

Key1234567891011121314151617181920

AD30AD31AD26AD24AD21AD16DEV

PINTB#PINTA#AD28AD25AD23AD18T

PREQH#PINTD#PINTC#AD27CBE3#AD19I

PGNTL#PREQL#PGNTH#AD29AD20CBE2#STOP#AD14AD7AD2PD0SLCT

RTCX2RTCX1PWRGDPCI

JBB1V

K VREF

BAT

SYNCACRSTJAB1

SDIN0ACSDIN1ACSDOJBB2JAY

PCS1#

GPIOCAC

SDIN2

FAN1FAN2

UIC5DTD+DTD-UIC

UIC1UIC3UIC2KB

KBDTMSCKSUSC#MSDTSUS

SUSA

SUSB#AOL

#/strap

SMB

CK2

DT2

SMB

ALRT#

DT1

PWR

PME#

BTN#

PCK

GPIOAGPI1WSC#

RUN#

PCI

CPU

STP#

GPIO

LID

RST#AD22AD17

INTR

GPI0RSM

UDR#

MSI

I2SJAX

MSO

BCLK

SPDIFJBY

SLPB#JAB2JBX

SUS

GPI

CLK

SMB

GPO0CPU

CK1

BAT

EXT

LOW#

SMI#

RING#CPU

RST

ARQ#

GPIOEAPICD0A20M#MCCS

APIC

CLK

FRM#

RST#

VCC GND VCC VCC VCC GND VCC

VCC H7 8 9 10 11 12 13 H14 GND

VCC J GND GND GND GND GND GND J VCC

GND K GND GND GND GND GND GND K VCC

GND

VCC L GND GND GND GND GND GND L GND

HWM

VCC

VCC M GND GND GND GND GND GND M VCC

HWM

VCC N7 8 9 10 11 12 13 N14 GND

ST#

VCC

SUS

INTR

MISS

IGN

NMI

NE#IOW#IRRX2

FERR

SLP#

STP

INIT

CLK#LAD3LAD0

#/strapLAD2LFRM# PCS0#

SMI#

/strapLAD1LDRQ#

CBE1#AD9AD

SEL#

RDY#AD15AD10AD4

AD12AD6AD0PD1PD4PD7USB

PAR

RDY#

SERR#AD13AD8AD3AUTO

VCC

GND VCC VCC GND VCC VCC VCC GND VCC

VCC

IOR#IR

VCC

VCC VCC

ROM

CS#

SPKR

SER IRQ

MEMR#SD14

MEMW#SD13

CBE

SD11

HG2#

SD12

LR1#

SD15

LG2#

LR2#

LG1#

STR#

ERR#

SD10

HR2#

HG1#

HR1#

PD2PD

AD1P

INIT#PD5

IN#

FD#PD3

VCC VCC

SD6SD

OSC

SD5SD4SA18IRQ15SA7

SD1SA19SA5

SD9

SD2LA20SA9

SD8

SD3LA21SA16

BUSY RTS# DTR#

ACK# TXD CTS#

CLK

PE DSR#

SLCT RXD

GND

RAM

VCC VCC VCC

SA17 /strap

GND

USB

VCC

USB

DCD#

VCC VCC

GND

RAM

IRQ14SA8

SDD8PDD0PDD15PDD13PDD3PDD12

SDD7

SA11

SDD11

SDD5

SA4

SDD9

SDD4

SA10

/strap

SDD10

USB

OC0#

USB

P3-

USB

RI#

P3+EECS#EEDIEEDO

USB

OC1#MDCKMDIO

EECKMRX

CLK

MTX

VCC

CLK

MII

CRSMCOL

TRK

WRT

00#

PRT#

MTR1#DS

VCC

GND

SDD6SDDRQ

SDD2

SA12

SDD12

SDD3

DRV

DEN1

MII

DRV

DEN0

PLL

PCI

CLKPDA1PDA0PDA2

PLL

D10PDD5PDIOR#PDRDY

PDD4PD

D11PDD8PDDRQPDIOW#

PDD1PD

D14PDD7PDD9PDD6

SA6

SA2

SA14

SDD14SDA1SDA0SDA2

SA1

SDD1

SDD15SDIOR#

SA3

SA13

SDD13

USB

P2-

USB

P2+

P1+

MRXD3MRX

MRXD1MRXD0MRX

MRX

MTX

ERR

ENA

MTXD1MTXD2MTX

DSK

CHG#HDSEL#

STEP#

DATA#WGATE#

MTR0#DS

PDCS1#PDCS3#IN

SDCS1#SDCS3#PD

SA15

SA0

SDD0SDIOW#SDRDY

P1-

USB

P0-

USB

P0+

MTX

DATA#

DIR#

DEX#

DACK#

Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the pin lists and pin descriptions contain all names.

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VT8231

Pin Lists

Figure 3. VT8231 Pin List (Numerical Order)

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

A01 IO AD30 D12 IO SLCTIN#/STEP# H03 O ACSDOUT P02 O SUSB# / GPIO2 U13 IO SA18 A02 IO AD31 D1 3 I PE / WDATA# H04 I JBB2 / GAMED7 P03 I AOLGPI/THRM/I17 U14 I IRQ15 A03 IO AD26 D14 I DSR# H05 I JAY / GAMED1 P04 O SUSCLK / GP O4 U15 IO SA07 / SDD07 A04 IO AD24 A05 IO AD21 D16 I USBOC1# A06 IO AD16 D17 O MDCK H16 I TRK00# A07 IODEVSEL# D18 IOMDIO H17 I WRTPRT# A08 IO CBE1# D19 I MRXD3 H18 I DSKCHG#

D15 P GNDUSB H06 P VCC P05 P VCCSUS

H15 P GND P06 P VCCSUS

P07 P GND P08 P VCC P09 P VCC

U16 IO SA06 / SDD06 U17 I SDDR U18 O SDCS1# U19 O SDCS3# U20 IO PDD02

A12 IO PD2 / WRTPRT# E03 I P WRGD J02 IO GPIOC/IO25/ATST A13 IO PD6 E04 O PCIRST# J03 I ACBITCLK A14 I BUSY / MTR1# E05 IO AD22 J04 O MSO / SPDIF A15 O RTS# E06 IO AD17 J05 I JBY / GAMED3 P16 IO PDD0 4 V07 IO LAD3 A16 O DTR# E07 I SERR# A17 I USBOC0# E08 IO AD13 A18 IO USBP2- E09 IO AD08 J16 OD MTR1# P19 I PDDR A19 IO USBP1- E10 IO AD03 J17 OD DS0# P20 O PDIOW# V11 I HRQ2#/SD10/I11

B02 I PINTA# E13 I SLCT/WGATE# J20 OD WGATE# R03 IO SMBCK1 V14 IO SA05 / SDD05 B04 IO AD25

B05 IO AD23 E16 O EECK K03 I FAN2/SLPB#/IO18 R06 OD INTR V17 IO SA14 / SDD14 B06 IO AD18 E17 I MRXCLK / AIRQK04 I JAB2 / GAMED5 B07 IO TRDY# E18 I MRXD1 K05 I JBX / GAMED2 R08 O IRTX / GPO14 V19 O SDA0 B08 IO AD15 E19 I MRXD0 / AIR

B11 IO AD01 B12 IO PINIT# / DIR# F03 I INTRUDER#/GPI8 K18 OD MTR0# B13 IO PD5 F04 I GPI0 K19 OD DS1# B14 I ACK# / DS1# F05 I RSMRST# K20 OD DIR#

B16 I CTS# B17 IO USBP3- F08 IO AD11 L03 AI DTD- R18 IO PDD07 W09 IO MEMR# B18 IO USBP2+ B19 IO USBP1+ F10 IO CBE0#

C02 I PINTD# C03 I PINTC# F14 I DCD# L17 OD DRVDEN0 T04 IOD EXTSMI# / GPI2 W15 IO SA04 / SDD04 C04 IO AD27 C05 IO CBE3# F16 I MTXCLK / AIRQL19 O PDCS3# T06 OD IGNNE# W17 IO SA01 / SDD01 C06 IO AD19

C08 IO PAR F19 O MTXENA / AIRQM02 AI UIC3 T09 O ROMCS#/KBCS# W20 O SDDACK#

E15 P VCCUSB

F02 P VBAT

F07 P VCC F09 P VCC

F13 P VCC L16 P VCCPLL F15 P VCC F16 P VCCMII

06 P VCC 15 P VCC

K02 I FAN1 R05 I CPUMISS / GPI16 V16 IO SA02 / SDD02

K06 P GND R09 P VCC

K17 OD DRVDEN1 R12 IO SD00 W03 IO GPIOE / GPIO31

L02 AI DTD+ R17 IO PDD14 W08 O LFRAME# L04 AI UIC4 R19 IO PDD09 W10 I LRQ2#/SD14/I13

L05 P GNDHWM

L18 O PDCS1# T05 OD NMI W16 IO SA12 / SDD12 L20 I INDEX# T07 IO IOW# / GPO23 W18 IO SA15 / SDD15

P13 P VCC P14 P GND P15 P VCC

P17 IO PDD11 V08 IO LAD0 P18 IO PDD08 V09 I SERIR

R07 P VCC

R13 P VCC R14 P VCC R15 P VCC

R20 IO PDD06 W11 O HGT1#/SD09/O8

T03 I BATLOW# / GPI5 W14 IO SA09 / SDD09

V04 I WSC#/ARQ#/I24 V05 OD INIT V06 OD STPCLK#

V10 O LGT2#/SD15/O11

V18 O SDA1 V20 O SDA2

W04 O APD0/ACS#/IO28 W05 OD A20M# W06 O MCCS#/O17/stra

C11 IO AD00 G02 O ACRST C12 IO PD1 / TRK00# G03 I JAB1 / GAMED4 C13 IO PD4 / DSKCHG# G04 I MSI / I2S C14 IO PD7 G05 I JAX / GAMED0 C15 I USBCLK C16 I RI# C17 IO USBP3+ C18 O EECS#

D02 O PREQL# D03 I PGNTH# D04 IO AD29 D05 IO AD20 G16 I MCRS / AIR D06 IO CB E 2# G17 I MCOL / AIR D07 IO STOP# G18 O MTXD1 / AIR D08 IO AD14 G19 O MTXD2 / AIR

Center

pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13

GND

G06 P VCC G07 P GND G08 P VCC G09 P VCC

G13 P GNDRAM G14 P GND G15 P VCCRAM N06 P VCC

M05 P VCCHWM M06 P VCC M15 P VCC M16 P GNDPLL

M17 I PCICLK T16 IO PDD00 Y07 IO LAD1 M18 O PDA1 T17 IO PDD15 Y08 I LDRQ#/SIN3/I15 M19 O PDA0 T18 IO PDD13 Y09 IO MEMW# M20 O PDA2 T19 IO PDD03 Y10 O LG1#/ SD13/O10

N04 IO MSDT / IRQ12 U03 I RING# / GPI3 Y14 IO SA16 / stra N05 O SUSST1# / GPO3 U04 OD CPURST Y15 IO SA10 / SDD10

N15 P GND

N16 IO PDD10 U07 IO IOR# / GPO22 Y18 IO SA00 / SDD00 N17 IO PDD05 U08 I IRRX / GPO15 Y1 9 O SDIOW# N18 O PDIOR# U09 O SPKR Y20 I SDRDY

T12 I OSC Y03 I APICCLK / GPI9 T13 IO SA17 / stra T14 I IRQ14 Y05 OD SMI# T15 IO SA08 / SDD08 Y06 O PCS0#/O16/stra

U05 I FERR# Y16 IO SA03 / SDD03 U06 OD SLP# / GPO7 Y17 IO SA13 / SDD13

Y04 O APD1/AK#/IO29

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06IO

00E20

C16

06PGN

N15PGN

J04OMSO / S

ORTCX2C15IUSBC

0PGN

05PGNDHW

6PGN

G13PGN

5PGNDUS

VCC

09PVCC

VCC

5PVCC

G08PVCC

G10PVCC

06PVCC

J06PVCC

5PVCC

06PVCC

5PVCC

N06PVCC

G03IJ

V19OSDA0

CBE0

05IJ

U18OSDCS

VCC

J05IJ

W19OSDIO

3PVCC

VCC

W13IO

0/OC2#/O20

N16IO

V09IS

05PVCCHW

6PVCC

G15PVCC

05PVCCSUS

06PVCCSUS

5PVCCUS

:H&RQQHFW

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VT8231

Figure 4. VT8231 Pin List (Alphabetical Order)

PinPin Name PinPin Name PinPin Name PinPin Name PinPin Name

W05 OD A20M# F11 I ERROR#/HDSEL# D18 IO MDIO C03 I PINTC# P01 O SUSA# / GPO1

J03 I ACBITCLK T04 IOD EXTSMI# / GPI2 W09 IO MEMR# C02 I PINTD# P02 O SUSB# / GPO2

B14 I ACK# / DS1# K02 I FAN1 Y09 IO MEMW# U01 I PME# / GPI6 N03 O SUSC# G02 O ACRST K03 I FAN2/SLPB#/IO18 E17 I MRXCLK / AIRQC01 O PREQH# P04 O SUSCLK H01 I ACSDIN0 U05 I FERR # E19 I MRXD0 / AIRQD02 O PREQL# N05 O SUSST1# / GPO3 H02IACSDIN1F H03 O ACSDOUT G01 O ACSYNC

11 IOAD

B11 IO AD01 D10 IO AD02

E10 IO AD03

B10 IO AD04 A10IOAD

C10 IO AD06 D09 IO AD07

E09 IO AD08 A09 IO AD09

B09 IO AD10

F08 IO AD11

C09 IO AD12 F04 I GPI0 G20 O MTXD3/AIR

E08 IO AD13 V03 I GPI1 / IRQ8# F19 O MTXENA/AIRQV14 IO SA05 / SDD05 B18 IO USBP2+ D08 IO AD14 V02 IO GPIOA/24 T05 OD NMI U16 IO SA06 / SDD06 B17 IO USBP3-

B08 IO AD15 J02 IO GPIOC/25/ATST T12 I OSC U15 IO SA07 / SDD07 C17 IO USBP3+ A06 IO AD16 Y01 IO GPIOD/30/SCIOU# C08 IO PAR T15 IO SA08 / SDD0 8

E06 IO AD17 W03 IO GPIOE V01 IO PCKRUN# W14 IO SA09 / SDD09

B06 IO AD18 H19 OD HDSEL# M17 I PCICLK Y15 IO SA10 / SDD10

C06 IO AD19 W11 O HGNT1#/SD09/O8 E04 O PCIRST# V15 IO SA11 / SDD11 D05 IO AD20 T10 O HGNT2#/SD11/O9 W01 O PCISTP# / GPO6 W16 IO SA12 / SDD12 A05 IO AD21 Y11 I HREQ1#/SD08/I10 Y06 O PCS0#/O16/strapY17 IO SA13 / SDD13

E05 IO AD22 V11 I HREQ2#/SD10/I11 J01 O PCS1#/SIN2/IO19 V17 IO SA14 / SDD14

B05 IO AD23 T06 OD IGNNE# D11 IO PD0/INDEX# W18 IO SA15 / SDD15 A04 IO AD24 L20 I INDEX# C12 IO PD1/TRK00# Y14 IO SA16 / stra

B04 IO AD25 V05 OD INIT A12 IO PD2/WRTPRT# T13 IO SA17 / stra A03 IO AD26 R06 OD INTR E12 IO PD3/RDATA# U13 IO SA18

C04 IO AD27 F03 I INTRUDER#/GPI8 C13 IO PD4/DSKCHG# V13 IO SA19

B03 IO AD28 U0 7 IO IOR# / GPO22 B13 IO PD5 R12 IO SD00 D04 IO AD29 T07 IO IOW# / G PO23 A13 IO PD6 V12 IO SD01 A01 IO AD30 C07 IO IRDY# C14 IO PD7 W12 IO SD02 A02 IO AD31 T14 I IRQ14 M19 O PDA0 Y12 IO SD03

P03 I AOLGPI/THRM/I17 U14 I IRQ15 M18 O PDA1 U12 IO SD04 Y03 O APICLK / GPI9 U08 I IRRX / GPO15 M20 O PDA2 U11 IO SD05 Y04 I APICD1/AK#/IO29 T08 I IRRX2 / GPI L18 O PDCS1# R11 IO SD06 W04 O APICD0/ACS#/IO28 R08 O IRTX / GPO14 L19 O PDCS3# T11 IO SD07

E11 IOAUTOFD# / DR

T03 I BATLOW# / GPI5 K04 I JAB2 / GAMED5 R16 IO PDD01 V18 O SDA1 A14 I BUSY / MTR1# G05 I JAX / GAMED0 U20 IO PDD0 2 V20 O SDA2

F10I A08 IO CBE1# F01 I JBB1 / GAMED6 P16 IO PDD04 U19 O SDCS3# D06 IO CBE 2# H0 4 I JBB2 / GAMED7 N17 IO PDD05 W20 O SDDACK#

C05 IO CBE3# K05 I JBX / GAMED2 R20 IO PDD06 U17 I SDDR

R05ICPUMISS / GPI1 U04 OD CPURST M04 IO KBCK / A20G P18 IO PDD08 Y19 O SDIOW# W02 O CPUSTP# / GPO5 N01 IO KBDT / KBRC R19 IO PDD09 Y20 I SDRDY

B16ICTS#

F14 I DCD# Y13 IO LA21/OC3#/O21 P17 IO PDD11 E07 I SERR# A07 IO DEVSEL# V08 IO LAD0 T20 IO PDD12 E13 I SLCT/WGATE# K20 OD DIR# Y07 IO LAD1 T18 IO PDD13 D12 IO SLCTIN#/STEP#

L17 OD DRVDEN0 W07 IO LAD2 R17 IO PDD14 R04 O SLOWCLK / O0 K17 OD DRVDEN1 V07 IO LAD3 T17 IO PDD15 U06 OD SLP# / GPO7

J17 OD DS0# Y08 I LDRQ#/SDIN3/I15 N20 O PDDACK# T02 I SMBALRT# / I7 K19 OD DS1# W08 O LF RAME# P19 I PDDR H18 I DSKCHG# Y10 O LGNT1#/SD13/O10 N18 O PDIOR# R01 IO SMBCK2 / IO27 D14 I DSR# V10 O LGNT2#/SD15/O11 P20 O PDIOW # T01 IO SMBDT1

L02 AI DTD+ Y02 I LID / GPI4 N19 I P DRDY R02 IO SMBDT2 / IO 26 J19 OD WDATA# L03 AI DTD- U10 I LREQ1#/SD12/I12 D13 I PE / WDATA# Y05 OD SMI# J20 OD WGATE#

A16 O DTR# W10 I LREQ2#/SD14/I13 D03 I PGNTH# U09 O SPKR H17 I WRTPRT#

E16 O EECK W06 O MCCS#/O17/strapD01 I PGNTL# J18 OD STEP# V04 I WSC#/ARQ#/I14 C18 O EECS# G17 I MCOL / AIR C19 I EEDI G16 I MCRS / AIR C20 O EEDO D17 O MDCK B01 I PINTB# A11 IO STROBE#

Center

pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13

GND

11 P

H15 P GND K L15 P GND

P1 P14 P GND L

FRAME# E18I MRXD1

7PGND

D D D

M DPLL DRAM

AB1 / GAMED4 T16IOPDD

AY / GAMED1 T19IOPDD

BY / GAMED

LA2

D20 I MRXD2 E03 I PWRGD H16 I TRK00# D19 I MRXD3 H20 I RDATA# B15 O T XD

F18 I MRXERR/AIRQU03 I RING# / GPI3 M03 I UIC2 N02 IO MSCK / IR N04 IO MSDT / IRQ12 F05 I RSMRST# L04 I UIC4 G04 I M SI / I2S E02 I RTCX1 L01 I UIC5

K18 OD MTR0# A15 O RTS# A17 I USBOC0#

J16 OD MTR1# E14 I RXD D16 I USBOC1#

F16 I MTXCLK/AIR

F20 O MTXD0/AIR G18 O MTXD1/AIR G19 O MTXD2/AIR

R18IOPDD

B12 IO PINIT# / DIR# D07 IO STOP# B02 I PINTA# V06 OD STPCLK#

IMRXDV / AIR

PDIF E01

PDD1

2IPWRBTN#B07IOTRDY#

IRI# M01IUIC1

1 T09 O ROMCS#/KBCS# M02 I UIC3

Y18 IO SA00 / SDD00 A20 IO USBP0-

W17 IO SA01 / SDD01 B20 IO USBP0+

V16 IO SA02 / SDD02 A19 IO USBP1Y16 IO SA03 / SDD03 B19 IO USBP1+

W15 IO SA04 / SDD04 A18 IO USBP2-

2PVBAT

7P F F12 P F13 P VCC F1

G06 P VCC G09 P VCC G12 P VCC

15 P VCC K1 L

M M1

P08 P VCC P11 P VCC

ERIRQ#

R03 IO SMBCK1

P12 P VCC P15 P VCC

R R09 P VCC

R1 R14 P

F1 K16 P VCCMII L1

P E1 K

1PVREF

MII PLL

RAM

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Pin Descriptions

Table 1. Pin Descriptions

PCI Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY# TRDY# STOP# DEVSEL#

PAR SERR#

PINTA-D#

PREQH# PGNTH#

PREQL# PGNTL#

PCICLK PCKRUN#

PCIRST# PCISTP# CPUSTP#

/ GPO6

/ GPO5

(see pin

list) C5, D6, A8, F10

F6 IO

C7 IO

B7 IO D7 IO A7 IO

C8 IO

E7 I

B2, B1,

C3, C2

C1 O D3 I

D2 O D1 I

M17 I

V1 IO

E4 O

W1 O W2 O

Address/Data Bus.

FRAME# assertion and data is driven or received in following cycles.

Command/Byte Enable.

enables corresponding to supplied or requested data are driven on following clocks.

Frame.

one more data transfer is desired by the cycle initiator.

Initiator Ready. Target Ready. Stop. Device Select.

or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8231initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

Parity. System Error.

error condition. Upon sampling SERR# active, the VT8231 can be programmed to generate an NMI to the CPU.

PCI Interrupt Request

INTD# pins as follows:

PCI Request. PCI Grant.

VT8231.

PCI Request. PCI Grant.

VT8231.

PCI Clock. PCI Bus Clock Run.

(high) or running (low). The VT8231 drives this signal low when the PCI clock is running (default on reset ) and releases it when it st ops the PCI cloc k. External device s may assert this signal low to request that the PCI clock be restarted or prevent it fro m stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used. Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for more details.

PCI Reset. PCI Stop. CPU Stop.

Assertion indicates the address phase of a PCI transfer. Negation indicates that

Asserted by the target to request the master to stop the current transaction.

A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

PCI Slot 1 INTA# INTB# INT C# INTD# PCI Slot 2 INTB# INTC# INTD# INTA# PCI Slot 3 INTC# INTD# INTA# INTB# PCI Slot 4 INTD# INTA# INTB# INTC# PCI Slot 5 INTA# INTB# INT C# INTD#

PCLK provides timing for all transactions on the PCI Bus.

The standard PCI address and data lines. The address is driven with

The command is driven with FRAME# assertion. Byte

Asserted when the initiator is ready for data transfer.

Asserted when the target is ready for data transfer.

The VT8231 asserts this signal to claim PCI transactions through positive

SERR# can be pulsed active by any PCI device that detects a system

. These pins are typically connected to the PCI bus INTA#-

PINTA# PINTB#

This signal goes to the North Bridge to request the PCI bus.

This signal is driven by the North Bridge to grant PCI access to the

This signal goes to the North Bridge to request the PCI bus.

This signal is driven by the North Bridge to grant PCI access to the

This signal indicates whether the PCI clock is or will be stopped

PINTC# PINTD#

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CPU Interface

Signal Name Pin # I/O Signal Description

VT8231

CPURST

INTR

NMI

INIT

STPCLK#

SMI#

FERR#

IGNNE#

/ GPO7

SLP#

A20M#

DTD+

DTD-

Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.

U4 OD

R6 OD

T5 OD

V5 OD

V6 OD

Y5 OD

U5 I

T6 OD

U6 OD

W5 OD

L2 Analog I

L3 Analog I

CPU Reset.

power-up.

CPU Interrupt.

an interrupt request is pending and needs service.

Non-Maskable Interrupt.

interrupt to the CPU. The VT8231 generates an NMI when either SERR# or IOCHK# is a sse rted.

Initialization.

special cycle on the PCI bus or if a soft reset is initiated by the register

Stop Clock.

throttle the processor clock.

System Management Interrupt.

the CPU in resp onse to different Power-Management events.

Numerical Coprocessor Error.

error signal on the CPU. Internally generates interrupt 13 if active.

Ignore Numeric Error.

on the CPU.

Sleep

CPUs only. Not currently used with socket-7 CPUs.

A20 Mask.

bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

CPU DTD (Thermal Diode) Channel Plus.

external temperature sensing diode.

CPU DTD (Thermal Diode) Channel Minus.

first external temperature sensing diode.

The VT8231 asserts CPURST to reset the CPU during

INTR is driven by the VT8231 to signal the CPU that

The VT8231 asserts INIT if it detects a shut-down

STPCLK# is asserted by the VT8231 to the CPU to

(Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1

Connect to A20 mask input of the CPU to control address

NMI is used to force a non-maskable

SMI# is asserted by the VT8231 to

This signal is tied to the coprocessor

This pin is connected to the “ignore error” pin

Connect to cathode of first

Connect to anode of

Strap Options

Signal Name Pin # I/O Signal Description

/ SUSA#

Strap

/ MCCS#

Strap

/ PCS0#

Strap

/ SA16

Strap

/ SA17

Strap

/ KBCS# / ROMCS#

Strap

Preliminary Revision 0.8 October 29, 1999 -11- Pinouts

P1 I / O

W6 I / O

Y6 I / O

Y14 I / IO

T13 I / IO

T9 I / O / O

CPURST / INIT Polarity

H: L:

CPU Frequency Strapping

H: Disable L: Enable

SD Bus Width

H: 16-Bit L: 8-Bit

BIO ROM Interface

H: LPC L: Conventional

Auto Reboot

H: Disable L: Enable

CPU Type

4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1

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Advanced Programmable Interrupt Controller (APIC) Interface

Signal Name Pin # I/O Signal Description

VT8231

/ APICREQ# / GPI14

WSC#

APICD0

APICD1

APICCLK SCIOUT#

/ GPIO30 / DTEST

AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ

/ APICCS# / GPIO28

/ APICACK# / GPIO29

/ GPI9

/ GPIOD

/ MCOL / MCRS / MRXCLK / MRXD0 / MRXDV / MRXERR / MTXCLK / MTXD0 / MTXD1 / MTXD2 / MTXD3 / MTXENA

V4 I / I / I

W4 O / O / IO

Y4 O / O / IO

Y3 I / I Y1 O / IO

IO / O

G17 O G16 O E17 O E19 O E20 O

F18 O F16 O

F20 O G18 O G19 O G20 O

F19 O

Internal APIC Write Snoop Complete.

bridge to indicate that all snoop activity on the CPU bus initiated by the last PCI-to-DRAM write is complete and that it is safe to perform an APIC interrupt.

External APIC Request.

to PCICLK prior to sending an interrupt over the APIC serial bus. This signals the VT8231 to flush its internal buffers.

Internal APIC Data 0. External APIC Chip Select.

to select an external APIC (if used). This occurs if the external APIC is enabled and a PCI cycle is detected within the programmed APIC address range.

Internal APIC Data 1. External APIC Acknowledge.

that it internal buffers have been flushed (in response to APICREQ#). This indicates to the external APIC that the VT8231’s internal buffers have been flushed and that it is OK for the APIC to send its interrupt.

APIC Clock. SCI Out.

interrupts to external APIC (if used). Defined as SCIOUT# if external APIC enabled (function 0 Rx74[7] = 1).

APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ.

Used to route internally generated SCI and SMBus

Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC.

Asserted by external APIC synchronous

The VT8231 drives this signal active

Asserted by the VT8231 to indicate

Asserted by the north

Serial EEPROM Interface

Signal Name Pin # I/O Signal Description EECS#

EECK EEDO EEDI

Preliminary Revision 0.8 October 29, 1999 -12- Pinouts

C18 O E16 O C20 O C19 I

Serial EEPROM Chip Select. Serial EEPROM Clock. Serial EEPROM Data Output. Serial EEPROM Data Input.

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Low Pin Count (LPC) Interface

Signal Name Pin # I/O Signal Description

VT8231

LFRAME# LDRQ# LAD[3-0] HREQ1# HGNT1# HREQ2# HGNT2# LREQ1# LGNT1# LREQ2# LGNT2#

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

/ ACSDIN3 / GPI15

/ SD8 / GPI10 / SD9 / GPO8 / SD10 / GPI11

/ SD11 / GPO9 / SD12 / GPI12 / SD13 / GPO10 / SD14 / GPI13 / SD15 / GPO11

W8 O

Y8 I / I / I

V7, W7, Y7, V8 IO / IO

Y11 I / IO

W11 O / IO

V11 I / IO

T10 O / IO U10 I / IO Y10 O / IO

W10 I / IO

V10 O / IO

LPC Frame. LPC Data Request. LPC Address / Data. High Priority Request 1. High Priority Grant 1. High Priority Request 2. High Priority Grant 2. Low Priority Request 1. Low Priority Grant 1. Low Priority Request 2. Low Priority Grant 2.

LAN Controller - Media Independent Interface (MII)

Signal Name Pin # I/O Signal Description MCOL

MCRS

MDCK

MDIO

MRXCLK MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXDV MRXERR

MTXCLK

MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXENA

/ APICIRQ

/ APICIRQ , , , / APICIRQ

/ APICIRQ

/ APICIRQ, / APICIRQ, / APICIRQ, / APICIRQ

/ APICIRQ

G17 I / I G16 I / I

D17 O

D18 IO

E17 I / I D19 D20

E18

E19

E20 I / I

F18 I / I

F16 I / I

G20 G19 G18

F20

F19 O / I

I I I

I / I

O / I O / I O / I O / I

MII Collision Detect. MII Carrier Sense.

media is active.

MII Management Data Clock.

timing reference for MDIO

MII Manag e ment Data I/O.

the MDO bit.

MII Receive Clock. MII Receive Data.

external PHY synchronous with MRXCLK.

MII Receive Data Valid. MII Receive Error.

decoding error.

MII Transmit Clock.

supplied by the PHY.

MII Transmit Data.

MTXCLK.

MII Transmit Enable.

port to the PHY.

From the external PHY.

Asserted by the external PHY when the

Sent to the external PHY as a

Read from the MDI bit or written to

2.5 or 25 MHz clock recovered by the PHY. Parallel receive data lines driven by the

Asserted by the PHY when it detects a data

Always active 2.5 or 25 MHz clock

Parallel transmit data lines synchronized to

Indicates transmit active from the MII

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Universal Serial Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBCLK USBOC0# USBOC1# USBOC2# USBOC3#

/ LA20 / GPO20 / LA21 / GPO21

B20 IO A20 IO B19 IO A19 IO B18 IO A18 IO C17 IO B17 IO C15 I A17 I D16 I

W13 I / IO / O

Y13 I / IO / O

USB Port 0 Data + USB Port 0 Data USB Port 1 Data + USB Port 1 Data USB Port 2 Data + USB Port 2 Data USB Port 3 Data + USB Port 3 Data USB Clock.

48MHz clock input for the USB interface

USB Port 0 Over Current Detect. USB Port 1 Over Current Detect. USB Port 2 Over Current Detect. USB Port 3 Over Current Detect.

System Management Bus (SMB) Interface (I2C Bus)

Signal Name Pin # I/O Signal Description SMBCK1

SMBCK2

/ GPIO27

SMBDT1 SMBDT2

/ GPIO26

SMBALRT#

/ GPI7

R3 IO R1 IO / IO T1 IO R2 IO / IO T2 I / I

SMB / I2C Channel 1 Clock. SMB / I SMB / I2C Channel 1 Data. SMB / I SMB Alert.

C Channel 2 Clock.

C Channel 2 Data.

(System Management Bus I/O space Rx08[3] = 1) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. The same pin is used as General Purpose Input 6 whose value is reflected in Rx48[6] of function 4 I/O space

Port 0 is disabled if this input is low. Port 1 is disabled if this input is low Port 2 is disabled if this input is low. Port 3 is disabled if this input is low.

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UltraDMA-33 / 66 Enhanced IDE Interface

Signal Name Pin # I/O Signal Description

VT8231

PDRDY

PDDMARDY / PDSTROBE

SDRDY

SDDMARDY / SDSTROBE

PDIOR#

PHDMARDY / PHSTROBE

SDIOR#

SHDMARDY / SHSTROBE

PDIOW#

PSTOP

SDIOW#

SSTOP

PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15

N19 I

Y20 I

N18 O

W19 O

P20 O

Y19 O

P19 I U17 I N20 O

W20 O

T14 I U14 I

EIDE Mode: UltraDMA Mode:

Primary Device DMA Request. Secondary Device DMA Request. Primary Device DMA Acknowledge. Secondary Device DMA Acknowledge. Primary Channel Interrupt Request. Secondary Channel Interrupt Request.

Primary I/O Channel Ready. Primary Device DMA Ready

may assert DDMARDY to pause output transfers

Primary Device Strobe

device may stop DSTROBE to pause input data transfers

Secondary I/O Channel Ready. Secondary Device DMA Ready

device may assert DDMARDY to pause output transfers

Secondary Device Strobe

device may stop DSTROBE to pause input data transfers

Primary Device I/O Read. Primary Host DMA Ready

The host may assert HDMARDY to pause input transfers

Primary Host Strobe

may stop HSTROBE to pause output data transfers

Secondary Device I/O Read. Secondary Host DMA Ready

assert HDMARDY to pause input transfers

Host Strobe B

HSTROBE to pause output data transfers

Primary Device I/O Write. Primary Stop

initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

Secondary Device I/O Write. Secondary Stop

. Output strobe (both edges). T he host may stop

. Stop transfer: Asserted by the host prior to

Primary channel DMA request

Secondary channel DMA request

Primary channel DMA acknowledge

Device ready indicator

. Output flow cont rol. The device

. Input data strobe (both edges). The

Device ready indicator

. Output flow control. The

. Input data strobe (both edges). The

Device read strobe

. Primary channel input flow control

. Output data strobe (both edges). The host

Device read strobe

. Input flow control. The host may

Device write strobe

Secondary channel DMA acknowledge

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UltraDMA-33 / 66 Enhanced IDE Interface (continued)

Signal Name Pin # I/O Signal Description

VT8231

PDCS1#

PDCS3#

SDCS1#

SDCS3#

PDA[2-0]

SDA[2-0]

PDD[15-0]

SDD[15-0]

/ SA[15-0]

L18 O

L19 O

U18 O

U19 O

M20, M18, M19 O

V20, V18, V19 O

T17, R17, T18, T20, P17, N16, R19, P18, R18, R20, N17, P16,

T19, U20, R16, T16

W18, V17, Y17, W16,

V15, Y15, W14, T15,

U15, U16, V14, W15,

Y16, V16, W17, Y18

Primary Master Chip Select.

on the primary IDE connector.

Primary Slave Chip Select.

the primary IDE connector.

Secondary Master Chip Select.

CS17X# on the secondary IDE connector.

Secondary Slave Chip Select.

on the secondary IDE connector.

Primary Disk Address.

in either the ATA command block or control block is being accessed.

Secondary Disk Address.

in either the ATA command block or control block is being accessed.

Primary Disk Data

Secondary Disk Data ISA Address

(SPKR strap 4.7K ohms high)

(SPKR strap 4.7K ohms low)

This signal corresponds to CS1FX#

This signal corresponds to CS3FX# on

This signal corresponds to

This signal corresponds to CS37X#

PDA[2:0] are used to indicate which byte

SDA[2:0] are used to indicate which byte

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MIDI Interface

Signal Name Pin # I/O Signal Description

VT8231

MSI MSO

/ I2S

/ SPDIF

G4 I / I

J4 O / O

MIDI Serial In

MIDI Serial Out

Serial Digital Audio Interface

Signal Name Pin # I/O Signal Description

/ MSI

I2S SPDIF

/ MSO

G4 I / I

J4 O / O

Serial Digital Audio In. Serial Digital Audio Out.

AC97 Audio / Modem Interface

Signal Name Pin # I/O Signal Description ACRST

ACSYNC ACSDOUT ACSDIN0 ACSDIN1 ACSDIN2 ACSDIN3 ACBITCLK

/ PCS1# / GPIO19 / LDRQ# / GPI5

G2 O G1 O H3 O H1 I H2 I

J1 I / O / IO

Y8 I / I / I

J3 I

AC97 Reset AC97 Sync AC97 Serial Data Out AC97 Serial Data In 0 AC97 Serial Data In 1 AC97 Serial Data In 2 AC97 Serial Data In 3 AC97 Bit Clock

Game Port Interface

Signal Name Pin # I/O Signal Description

/ GAMED0

JAX

/ GAMED1

JAY

/ GAMED2

JBX

/ GAMED3

JBY

/ GAMED4

JAB1

/ GAMED5

JAB2

/ GAMED6

JBB1

/ GAMED7

JBB2

See Function 0 Rx77[6]

G5 I H5 I K5 I

J5 I G3 I K4 I

F1 I

H4 I

Joystick A X-axis Joystick A Y-axis Joystick B X-axis Joystick B Y-axis Joystick A Button 1 Joystick A Button 2

Joystick B Button 1

Joystick B Button 2

Preliminary Revision 0.8 October 29, 1999 -17- Pinouts

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Floppy Disk Interface

Signal Name Pin # I/O Signal Description

VT8231

DRVDEN0 DRVDEN1 MTR0# MTR1# DS0# DS1# DIR# STEP# INDEX# HDSEL# TRK00# RDATA# WDATA# WGATE# DSKCHG#

WRTPRT#

See also Parallel Port pin descriptions for optional Floppy Disk interface functionality

L17 OD K17 OD K18 OD

J16 OD

J17 OD K19 OD K20 OD

J18 OD

L20 I H19 OD H16 I H20 I

J19 OD

J20 OD H18 I

H17 I

Drive Density Select 0. Drive Density Select 1. Motor Control 0. Motor Control 1. Drive Select 0. Drive Select 1. Direction. Step. Index. Head Select. Track 0. Read Data. Write Data. Write Gate. Disk Change.

since the last drive selection.

Write Protect.

commands to be ignor ed)

Direction of head movement (0 = inward motion, 1 = outward motion)

Low pulse for each track-to-track movement of the head.

Sense to detect that the head is positioned over the beginning of a track

Sense to detect that the head is positioned over track 0.

Select motor on drive 0.

Select motor on drive 1 Select drive 0. Select drive 1

Selects the side for R/W operations (0 = side 1, 1 = side 0)

Raw serial bit stream from the drive for read operatrions.

Encoded data to the drive for write operations.

Signal to the drive to enable current flow in the write head.

Sense that the drive door is open or the diskette has been changed

Sense for detection that the diskette is write protected (causes write

Preliminary Revision 0.8 October 29, 1999 -18- Pinouts

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Parallel Port Interface

Signal Name Pin # I/O Signal Description

VT8231

PINIT# STROBE# AUTOFD#

SLCTIN# SLCT ACK#

ERROR#

BUSY PE PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

As shown by the alternate functions above, in mobile applications the parallel port pins can op tionally be selected to function as a floppy disk interface for attachment of an external floppy drive using the parallel port connector (see Super I/O Configuration Index F6[5]).

/ DIR#

/ nc

/ DRVEN0

/ STEP#

/ WGATE#

/ DS1#

/ HDSEL#

/ MTR1#

/ WDAT A#

/ nc, / nc, / nc, / DSKCHG#, / RDATA#, / WRTPRT#, / TRK00#, / INDEX#

B12 IO / O A11 IO / E11 IO / O

D12 IO / O E13 I / O B14 I / O

F11 I / O

A14 I / O D13 I / O C14 A13 B13 C13 E12 A12 C12 D11

IO / IO / IO / IO / I IO / I IO / I IO / I IO / I

Initialize. Strobe. Auto Feed.

each line is printed. I/O pin in ECP/EPP mode.

Select In. Select. Acknowledge.

the data and is ready to accept new data

Error.

printer.

Busy. Paper End. Parallel Port Data.

Initialize printer. Output in standard mode, I/O in ECP/EPP mode.

Output used to strobe data into the printer. I/O in ECP/EPP mode.

Output used to cause the printer to automatically feed one line after

Output used to select the printer. I/O pin in ECP/EPP mode.

Status output from the printer. High indicates that it is powered on.

Status output from the printer. Low indicates that it has received

Status output from the printer. Low indicates an error condition in the

Status output from the printer. High indicates not ready to accept data.

Status output from the printer. High indicates that it is out of paper.

Preliminary Revision 0.8 October 29, 1999 -19- Pinouts

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Serial Port and Infrared Interface

Signal Name Pin # I/O Signal Description TXD

RXD IRTX

IRRX

IRRX2 RTS#

CTS#

DTR#

DSR#

DCD#

RI#

/ GPO14

/ GPO15

/ GPI

B15 O E14 I

R8 O / O

U8 I / O

T8 I / I

A15 O

B16 I

A16 O

D14 I

F14 I

C16 I

Transmit Data. Receive Data. Infrared Transmit.

1, 2, or 3. General Purpose Output 14 if Rx76[5] = 1

Infrared Receive.

or 3. General Purpose Output 15 if Rx76[5] = 1

Infrared Receive. Request To Send.

Typically used as hardware handshake with CTS# for low level flow control. Designed for direct input to external RS-232C driver.

Clear To Send.

device is ready to receive data. Typically used as hardware handshake with RTS# for low level flow control. Designed for input from external RS-232C receiver.

Data Terminal Ready.

ready. Typically used as hardware handshake with DSR# for overall readiness to communicate. Designed for direct input to external RS-232C driver.

Data Set Ready.

device is powered, initialized, and ready. Typically used as hardware handshake with DTR# for overall readiness to communicate. Designed for direct input from external RS-232C receiver.

Data Carrier Detect.

a carrier signal (i.e., a communications channel is currently open). In direct connect environments, this input will typically be driven by DTR# as part of the DTR/DSR handshake. Designed for direct input from external RS-232C receiver.

Ring Indicator.

condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments).

Serial port transmit data out.

Serial port receive data in.

Indicator to the serial port that an external communications

Indicator to serial port that an external modem is detecting a ring

VT8231

IR transmit data out (Rx76[5] = 0) selectable from serial port

IR receive data in (Rx76[5] = 0) selectable to serial port 1, 2,

IR receive data in (Rx76[5] = 0)

Indicator that the serial output port is ready to transmit data.

Indicator that serial port is powered, initialized, and

Indicator to serial port that an external serial communications

Indicator to serial port that an external modem is detecting

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Conventional BIOS ROM / ISA Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

/ USBOC3# / GPO21

LA21

/ USBOC2# / GPO20

LA20 SA[19:18],

/ strap,

SA17

/ strap,

SA16 SA[15:0]

SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

IOR#

IOW#

MEMR#

MEMW#

IRQ1 IRQ8# IRQ12 IRQ14 IRQ15 SPKR

/ SDD[15:0]

/ LGNT2# / GPO11, / LREQ2# / GPI13, / LGNT1# / GPO10, / LREQ1# / GPI12, / HGNT2# / GPO9,

/ HREQ2# / GPI11, / HGNT1# / GPO8, / HREQ1# / GPI10, , , , , , , ,

/ GPO22

/ GPO23

/ MSCK

/ GPI1 / MSDT

Y13

W13

V13, U13,

T13, Y14,

W18, V17, Y17, W16,

V15, Y15, W14, T15, U15, U16, V14, W15,

Y16, V16, W17, Y18

V10

W10

Y10 U10 T10 V11

W11

Y11 T11 R11 U11 U12 Y12

W12

V12 R12

U7 IO

T7 IO

W9 IO

Y9 IO

N2 I / IO V3 I / I

N4 I / IO T14 I U14 I

U9 O

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO IO IO IO IO IO IO IO

System Address Bus

devices (e.g., BIOS ROMs) up to 4 Mbytes.

System Address Bus

interface to BIOS ROMs but may also be used to implement a subset of the ISA bus if required. SA[19-16] are connected to ISA bus SA[19-16] directly. SA[19-17] are also connected to LA[19-17] of the ISA bus.

System Data.

ROMs and for devices residing on the ISA bus. SD0-7 also output general purpose output information when GPOWE# is active.

I/O Read.

device that the slave may drive data on to the ISA data bus.

I/O Write.

device that the slave may latch data from the ISA data bus.

Memory Read.

slave that it may drive data onto the ISA data bus.

Memory Write.

slave that it may latch data from the ISA data bus.

Interrupt 1 (optional external Keyboard Controller). Interrupt 8 (optional external RTC). Interru Interrupt 14 (IDE Primary Channel). Interrupt 15 (IDE Secondary Channel). Speaker Drive.

IOR# is the command to an ISA I/O slave

IOW# is the command to an ISA I/O slave

t 12 (optional external PS2 Mouse Controller).

. Allows access to physical memory

. These address lines are used to

SD[15:0] provide the data path for BIOS

MEMR# is the command to a memory

MEMW # is t he comma nd to a memory

Output of internal timer/counter 2.

Serial IRQ

Signal Name Pin # I/O Signal Description SERIRQ

Preliminary Revision 0.8 October 29, 1999 -21- Pinouts

V9 I

Serial IRQ

(Rx68[3] = 1 and Rx74[6] = 0)

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Internal Keyboard Controller

Signal Name Pin # I/O Signal Description

VT8231

MSCK

MSDT

KBCK

KBDT

KBCS#

/ IRQ1

/ IRQ12

/ A20GATE

/ KBRC

/ ROMCS# / strap

N2 IO / I

N4 IO / I

M4 IO / I

N1 IO / I

T9 O / O / I

MultiFunction Pin

Rx5A[1]=1 Rx5A[1]=0

MultiFunction Pin

Rx5A[1]=1 Rx5A[1]=0

MultiFunction Pin

Rx5A[0]=1 Rx5A[0]=0

MultiFunction Pin

Rx5A[0]=1 Rx5A[0]=0

for CPURST# generation

Keyboard Chip Select

Mouse Clock. Interrupt Request 1

Mouse Data. Interrupt Request 12

Keyboard Clock. Gate A20.

Keyboard Data.

Keyboard Reset.

Chip Selects

Signal Name Pin # I/O Signal Description ROMCS#

MCCS#

PCS0#

PCS1#

/ KBCS# / strap

/ GPO17 / strap

/ GPO16 / strap

/ ACSDIN2 / GPIO19

T9 O / O / I

W6 O / IO

Y6 O / IO / IO

J1 O / I / IO

ROM Chip Select Microcontroller Chip Select

Asserted during read or write accesses to I/O ports 62h or 66h.

Programmable Chip Select 0.

during I/O cycles to programmable read or write ISA I/O port ranges. See also Rx59[3] and Rx77[2].

Programmable Chip Select 1.

(Internal mouse controller enabled by Rx5A[1])

From internal mouse controller.

. Interrupt 1 (external KBC).

(Internal mouse controller enabled by Rx5A[1])

From internal mouse controller.

. Interrupt 12 (ext PS2 mouse ctlr).

(Internal keyboard controller enabled by Rx5A[0])

From internal keyboard controller

Input from external keyboard controller.

(Internal keyboard controller enabled by Rx5A[0])

From internal keyboard controller.

From external keyboard controller (KBC)

(Rx5A[0]=0). To external keyboard controller chip.

(Rx5A[0]=1). Chip Select to the BIOS ROM.

(Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).

(Rx76[1] = 1 and Rx8B[0] = 1). Asserted

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General Purpose Inputs

Signal Name Pin # I/O Signal Description

VT8231

GPI0

/ IRQ8#

GPI1

/ EXTSMI#

GPI2

/ RING#

GPI3

/ LID

GPI4

/ BATLOW#

GPI5

/ PME#

GPI6

/ SMBALRT#

GPI7

/ INTRUDER#

GPI8

/ APICCLK

GPI9

/ SD8 / HREQ1#

GPI10

/ SD10 / HREQ2#

GPI11

/ SD12 / LREQ1#

GPI12

/ SD14 / LREQ2#

GPI13

/ WSC# / APICREQ#

GPI14

/ LDRQ# / ACSDIN3

GPI15

/ CPUMISS

GPI16

/ AOLGPI / THRM

GPI17

/ GPO18 / FAN2 / SLPBTN#

GPI18

/ GPO19 / ACSDIN2 / PCS1#

GPI19 GPI20 General Purpose Input 20 GPI21 General Purpose Input 21 GPI22 General Purpose Input 22 GPI23 General Purpose Input 23

/ GPO24 / GPIOA

GPI24

/ GPO25 / GPIOC / ATEST

GPI25

/ GPO26 / SMBDT2

GPI26

/ GPO27 / SMBCK2

GPI27

/ GPO28 / APICD0 / APICCS#

GPI28

/ GPO29 / APICD1 / APICACK#

GPI29

/ GPO30 / GPIOD / DTEST / SCIOUT#

GPI30

/ GPO31 / GPIOE

GPI31

F4 I V3 I / I T4 I / IO U3 I / I Y2 I / I T3 I / I U1 I / I T2 I / I F3 I / I

Y3 I / I Y11 I / IO / I W11 I / I O / I U10 I / IO / I W10 I / I O / I

V4 I / I / I

Y8 I / I / I

R5 I / I

P3 I / I / I

K3 I / O / I / I

J1 I / O / I / O

V2 I / O / IO

J2 I / O / IO / O R2 I / O / IO R1 I / O / IO

W4 I / O / O / O

Y4 I / O / O / O Y1 I / O / IO / O / O

W3 I / O / IO

General Purpose Input 0 General Purpose Input 1 General Purpose Input 2 General Purpose Input 3 General Purpose Input 4 General Purpose Input 5 General Purpose Input 6 General Purpose Input 7 General Purpose Input 8 General Purpose Input 9 General Purpose Input 10 General Purpose Input 11 General Purpose Input 12 General Purpose Input 13 General Purpose Input 14 General Purpose Input 15 General Purpose Input 16 General Purpose Input 17 General Purpose Input 18 General Purpose Input 19

General Purpose Input 24 General Purpose Input 25 General Purpose Input 26 General Purpose Input 27 General Purpose Input 28 General Purpose Input 29 General Purpose Input 30 General Purpose Input 31

(Rx5A[2] = 1)

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General Purpose Outputs

Signal Name Pin # I/O Signal Description

VT8231

/ SLOWCLK

GPO0

/ SUSA#

GPO1

/ SUSB#

GPO2

/ SUSST1#

GPO3

/ SUSCLK

GPO4

/ CPUSTP#

GPO5

/ PCISTP#

GPO6

/ SLP#

GPO7

/ SD9 / HGNT1#

GPO8

/ SD11 / HGNT2#

GPO9 GPO10 GPO11 GPO12 General Purpose Output 12. GPO13 General Purpose Output 13. GPO14 GPO15 GPO16 GPO17 GPO18 GPO19 GPO20 GPO21 GPO22 GPO23 GPO24 GPO25 GPO26 GPO27 GPO28 GPO29 GPO30 GPO31

/ SD13 / LGNT1# / SD15 / LGNT2#

/ IRTX / IRRX / PCS0# / MCCS# / / / LA20 / USBOC2# / LA21 / USBOC3# / IOR# / IOW# / / / / / / / /

/ FAN2 / SLPBTN#

GPI18

/ PCS1# / ACSDIN2

GPI19

/ GPIOA

GPI24

/ GPIOC / ATEST

GPI25

/ SMBDT2

GPI26

/ SMBCK2

GPI27

/ APICD0 / APICCS#

GPI28

/ APICD1 / APICACK#

GPI29

/ GPIOD / DTEST / SCIOUT#

GPI30

/ GPIOE

GPI31

R4 O / O

P1 O / O P2 O / O N5 O / O P4 O / O

W2 O / O W1 O / O

U6 O / O

W11 O / IO / O

T10 O / IO / O Y10 O / IO / O V10 O / IO / O

R8 O / O U8 O / I Y6 O / O

W6 O / O

K3 O / I / I / I

J1 O / I / O / I W13 O / IO / I Y13 O / IO / I

U7 O / O T7 O / O V2 O / I / IO

J2 O / I / IO / O

R2 O / I / IO R1 O / I / IO

W4 O / I / O / O

Y4 O / I / O / O Y1 O / I / IO / O / O

W3 O / I / IO

General Purpose Output 0.

00). Output value determined by PMU I/O Rx4C[0]

General Purpose Output 1. General Purpose Output 2. General Purpose Output 3. General Purpose Output 4. General Purpose Output 5. General Purpose Output 6. General Purpose Output 7. General Purpose Output 8. General Purpose Output 9. General Purpose Output 10. General Purpose Output 11.

General Purpose Output 14 General Purpose Output 15 General Purpose Output 16. General Purpose Output 17. General Purpose Output 18. General Purpose Output 19. General Purpose Output 20. General Purpose Output 21. General Purpose Output 22. General Purpose Output 23. General Purpose Output 24. General Purpose Output 25. General Purpose Output 26. General Purpose Output 27. General Purpose Output 28. General Purpose Output 29. General Purpose Output 30. General Purpose Output 31.

(Func 4 Rx54[1-0] =

(Rx76[5] = 1) (Rx76[5] = 1)

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General Purpose I/Os

Signal Name Pin # I/O Signal Description

VT8231

GPIOA

GPIOB General Purpose I/O B GPIOC GPIOD

/ SCIOUT#

GPIOE

/ GPI24 / GPO24

/ GPI25 / GPO25 / ATEST / GPI30 / GPO30 / DTEST

/ GPI31 / GPO31

V2 IO / I / O

J2 IO / I / O / O

Y1 IO / I / O / O

W3 IO

General Purpose I/O A / 24

= 1. See also Rx74[2]

General Purpose I/O C / 25. General Purpose I/O D / 30.

General Purpose I/O E / 31.

Hardware Monitoring

Signal Name Pin # I/O Signal Description UIC1

UIC2 UIC3 UIC4 UIC5 DTD+ DTDVREF

FAN1

/ SLPBTN# / GPI18 / GP O18

FAN2 DTEST ATEST

/ GPIOD (30) / SCIOUT# / GPIOC (25)

M1 Analog I M3 Analog I M2 Analog I

L4 Analog I L1 Analog I L2 Analog I L3 Analog I K1 P

K2 I K3 I / I / I / O Y1 O

J2 O

Universal Input Channel. Universal Input Channel. Universal Input Channel. Universal Input Channel. Universal Input Channel. CPU DTD (Thermal Diode) Channel Plus. CPU DTD (Thermal Diode)Channel Minus.

Voltage Reference for Thermal Sensing Fan Speed Monitor 1. Fan Speed Monitor 2.

Hardware Monitor Digital Test Out Hardware Monitor Analog Test Out

(Rx76[0] = 0). GPOWE# if Rx76[0]

(Rx76[2] = 0). See also Rx74[4] (Rx76[3] = 0). See also Rx74[5]

For temperature / voltage monitoring. For temperature / voltage monitoring. For temperature / voltage monitoring. For temperature / voltage monitoring. For temperature / voltage monitoring.

(5V ±5%) (3.3V only) (3.3V only)

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Power Management and External State Monitoring

Signal Name Pin # I/O Signal Description

VT8231

/ GPI6

PME# EXTSMI#

SMBALRT#

THRM

LID

RING#

BATLOW# CPUMISS

AOLGPI INTRUDER# RSMRST#

SUSA#

SUSB#

SUSC#

SUSST1#

SUSCLK

/ GPI2

/ AOLGPI / GPI17

/ GPI4

/ GPI3

/ GPI5

/ GPI16

/ GPI17 / THRM

/ GPO1 / strap

/ GPO2

/ GPO

/ GPO3

/ GPO4

/ GPI7

/ GPI8

U1 I / I

T4 IOD / I

T2 I / I

P3 I / I / I

Y2 I / I

U3 I / I

T3 I / I

R5 I / I

P3 I / I / I F3 I / I F5 I

P1 O / O / I

P2 O / O

N3 O / O

N5 O / O

P4 O / O

Power Management Event. External System Management Interrupt.

falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. (10K PU to VCCS if not used) (3.3V only)

SMB Alert

chip is enabled to allow it, assertion generates an IRQ or SMI or power management event. (10K PU to VCCS if not used)

Monitor Input - Thermal Alarm.

used)

Monitor Input - Notebook Computer Display Lid Open / Closed.

Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high and/or high-to-low transitions to generate an SMI#. The VT8231 performs a 200 usec debounce of this input if Function 4 Rx40[5] is set to 1. (10K PU to VCCS if not used)

Monitor Input – M odem Ring.

circuitry to allow the system to be re-activated by a received phone call. (10K PU to VCCS if not used)

Monitor Input - Bat t ery Low. Monitor Input - CPU M issing.

correctly.

Monitor Input - Awa ke On LAN External Event. Monitor Input – Chassis Intr usion. Resume Reset.

plane and also resets portions of the internal RTC logic.

Suspend Plane A Control

Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane. (10K PU to VCCS if not used)

Suspend Plane B Control

Asserted during power management STR and STD suspend states. Used to control the secondary power plane. (10K PU to VCCS if not used)

Suspend Plane C Control.

suspend state. Used to control the tertiary power plane. Also connected to ATX power-on circuitry.

Suspend Status 1

the North Bridge to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. Connect 10K PU to VCCS.

Suspend Clock.

(e.g., Apollo MVP3 or MVP4) for DRAM refresh purposes. Stopped during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VCCS.

(System Management Bus I/O space Rx08[3] = 1). When the

Resets the internal logic connected to the VCCS power

(Func4 Rx54[4] = 1 for GPO3). Typically connected to

32.768 KHz output clock for use by the North Bridge

(Rx74[1]=0) (1K PU to VCCS if not used)

When enabled to allow it, a

(Rx74[1]=1) (1K PU to VCCS if not

May be connected to external modem

(10K PU to VCCS if not used)

Indicates whether t he CPU is plugged in

(Rx74[7]=0 and Function 4 Rx54[2]=0).

(Rx74[7]=0 and Function 4 Rx54[3]=0).

Asserted during power management STD

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Resets, Clocks, and Clock Control

Signal Name Pin # I/O Signal Description

VT8231

PWRGD PWRBTN#

SLPBTN#

FAN2 / GPIO18

PCIRST#

RTCX1

RTCX2 OSC SLOWCLK

GPO0

CPUSTP#

GPO5

PCISTP#

GPO6

E3 I

U2 I

K3 I / I

E4 O

E2 I

E1 O

T12 I

R4 O

W2 O /

W1 O /

Power Good. Power Button.

external system on/off button or switch. The VT8231 performs a 200us debounce of this input if Function 4 Rx40[5] is set to 1. (3.3V only)

Sleep Button.

/ IO

external system sleep button or switch (Function 4 Rx40[6] = 1). Connect to VCC if not used.

PCI Reset.

this pin during power-up or from the control register.

RTC Crystal Input

used for the internal RTC and for power-well power management logic.

RTC Crystal Output Oscillator. Slow Clock.

(set to 01, 10, or 11).

CPU Clock Stop

disable the CPU clock outputs. Not connected if not used. See also PMU I/O Rx2C[3].

PCI Clock Stop

the PCI clock outputs. Not connected if not used.

Connected to the PWRGOOD signal on the Power Supply.

Used by the Power Management subsystem to monitor an

Used by the power management subsystem to monitor an

Active low reset signal for the PCI bus. The VT8231 will assert

: 32.768 KHz crystal or oscillator input. This input is

: 32.768 KHz crystal output

14.31818 MHz clock signal used by the internal Timer. Frequency selectable if PM U function 4 Rx54[1-0] is nonzero

(Rx75[4] = 0). Signals the system clock generator to

(Rx75[5] = 0). Signals the system clock generator to disable

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Power and Ground

Signal Name Pin # I/O Signal Description

VT8231

(27 Pins)

VCC

(27 Pins)

GND

VCCSUS

VBAT

VREF VCCHWM

GNDHWM VCCMII

VCCRAM

GNDRAM VCCPLL

GNDPLL VCCUSB

GNDUSB

F7, F9, F12-F13, F15,

G6, G8-G10, G12,

H6, J6, J15, K15,

L6, M6, M15, N6,

P8-P9, P11-P13, P15,

R7, R9-R10, R1 3-R15

G7, G11, G14, H15,

J8-J13, K6, K8-K13,

L8-L13, L15, M8-M13,

N15, P7, P10, P14

P5, P6 P

F2 P

K1 P M5 P

L5 P

F16, K16 P

G15 P

G13 P L16 P

M16 P

E15 P

D15 P

Core Power.

when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high. These pins should be connected to the same voltage as the CPU I/O circuitry. Internally connected to hardware monitoring system voltage detection circuitry for 3.3V monitoring.

Ground.

Suspend Power.

supply is turned off. If the “soft-off” state is not implemented, then this pin can be connected to VCC. Signals powered by or referenced to this plane are: SMBCK1/DT1, KBCK/DT, MSCK/DT, PWRBTN#, SUSC#, GPO0 / SLOWCLK, GPO1 / SUSA#, GPO2 / SUSB#, GPO3 / SUSST1#, GPO4 / SUSCLK, GPI1 / IRQ8#, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5 / BATLOW#, GPI6 / PME#, GPI7 / SMBALRT#, GPI16 / CPUMISS, GPI17 / AOLGPI / THRM, GPIO26 / SMBDT2, GPIO27 / SMBCK2

RTC Battery.

referenced to this plane are: RTCX1, RTCX2, PWRGD, RSMRST#, GPI0, and INTRUDER#.

Voltage Reference Hardware Monitor Power.

(voltage monitoring, temperature monitoring, and fan speed monitoring). Connect to VCC thr ough a ferri te bead. Signals powere d by or re ferenced to this plane are: UIC[5:1], DTD+/-, FAN1, FAN2 / SLPBTN# / GPIO18

Hardware Monitor Gro und. LAN MII Power.

external PHY) . Connect to VCC through a fe rrite be ad. Signals po wered by or referenced to this plane are: MCRS, MCOL, MDCK, MDIO, MTXD[3:0], MTXENA, MTXCLK, MRXERR, MRXCLK, MRXDV, and MRXD[3:0]

LAN RAM Power.

a ferrite bead.

LAN RAM Ground. PLL Power.

bead.

PLL Ground. USB Differential Output Power.

(USBP0+, P0-, P1+, P 1-, P2+, P2-, P3+, P 3-). Connect to VCC through a ferrite bead.

USB Differential Output Ground.

3.3V nominal (3.15V to 3.45V). This supply is turned on only

Connect to primary motherboard ground plane.

Always available unless the mechanical switch of the power

Battery input for internal RTC. Signals powered by or

(5V ±5%). For thermal sensing and 5V input tolerance.

Power for hardware monitoring subsystem

Connect to GND through a ferrite bead.

Power for LAN Media Independent Interface (interface to

Power for LAN internal RAM. Connect to VCC through

Connect to GND through a ferrite bead.

Power for internal PLL. Connect to VCC through a ferrite

Connect to GND through a ferrite bead.

Power for USB differential outputs

Connect to GND through a ferrite bead.

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EGISTERS

VT8231

The following tables summarize the configuration and I/O registers of the VT8231. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions for details).

Detailed register descriptions are provided in the following section of this document. All offset and default values are shown in hexadecimal unless ot herwise indicated

Table 2. System I/O Map

Port Function Actual Port Decoding

00-1F Master DMA Controller 0000 0000 000x nnnn 20-3F Master Interrupt Controller 0000 0000 001x xxxn 40-5F Timer / Counter 0000 0000 010x xxnn 60-6F Keyboard Controller 0000 0000 0110 xnxn (60h) KBC Data 0000 0000 0110 x0x0 (61h) Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1 (64h) KBC Command / Status 0000 0000 0110 x1x0 70-77 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn 78-7F -available for system use- 0000 0000 0111 1xxx 80 -reserved- (debug port) 0000 0000 1000 0000 81-8F DMA Page Registers 0000 0000 1000 nnnn 90-91 -available for system use- 0000 0000 1001 000x 92 System Control 0000 0000 1001 0010 93-9F -available for system use- 0000 0000 1001 nnnn A0-BF Slave Interrupt Controller 0000 0000 101x xxxn C0-DF Slave DMA Controller 0000 0000 110n nnnx E0-FF -available for system use- 0000 0000 111x xxxx

100-CF7 -available for system use* CF8-CFB PCI Configuration Address 0000 1100 1111 10xx

CFC-CFF PCI Configuration Data 0000 1100 1111 11xx D00-FFFF -available for system use-

* On-Chip Super-I/O Functi ons – PC-Standard Port Addresses 200-20F Game Port 2E8-2EF COM4 2F8-2FF COM2 378-37F Parallel Port (Standard & EPP) 3E8-3EF COM3 3F0-3F1 Configuration Index / Data 3F0-3F7 Floppy Controller 3F8-3FF COM1 400-402 Parallel Port (ECP Extensions)

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Table 3. Registers

VT8231

Legacy I/O Registers

Port Master DMA Controller Registers Default Acc

00 Channel 0 Base & Current Address RW 01 Channel 0 Base & Current Count RW 02 Channel 1 Base & Current Address RW 03 Channel 1 Base & Current Count RW 04 Channel 2 Base & Current Address RW 05 Channel 2 Base & Current Count RW 06 Channel 3 Base & Current Address RW 07 Channel 3 Base & Current Count RW 08 Status / Command RW

09 Write Request 0A Write Single Mask 0B Write Mode 0C Clear Byte Pointer FF 0D Master Clear

0E Clear Mask

0F Read / Write Mask RW

Port Master Interrupt Controller Regs Default Acc

20 Master Interrupt Control — *

21 Master Interrupt Mask — *

20 Master Interrupt Control Shadow —

21 Master Interrupt Mask Shadow —

* RW if shadow registers are disabled

Port

Port Keyboard Controller Registers Default Acc

Port CMOS / RTC / NMI Registers Default Acc

NMI Disable is port 70h (CMOS Memory Address) bit-7. RTC control occurs via specific CMOS data locations (0-Dh). Ports 72-73 may be used to access all 256 locations of CMOS. Ports 74-75 may be used to access CMOS if the internal RTC is disabled.

Timer/Counter Registers Default Acc

40 Timer / Counter 0 Count RW

41 Timer / Counter 1 Count RW

42 Timer / Counter 2 Count RW

43 Timer / Counter Control

60 Keyboard Controller Data RW

61 Misc Functions & Speake r Control RW

64 Keyboard Ctrlr Command / Status RW

70 CMOS Memory Address & NMI Disa

71 CMOS Memory Data (128 bytes) RW

72 CMOS Memory Address RW

73 CMOS Memory Data (256 bytes) RW

74 CMOS Memory Address RW

75 CMOS Memory Data (256 bytes) RW

WO WO WO WO WO WO

RW RW

Legacy I/O Registers (continued)

Port DMA Page Registers Default Acc

87 DMA Page – DMA Channel 0 RW 83 DMA Page – DMA Channel 1 RW 81 DMA Page – DMA Channel 2 RW 82 DMA Page – DMA Channel 3 RW 8F DMA Page – DMA Channel 4 RW 8B DMA Page – DMA Channel 5 RW 89 DMA Page – DMA Channel 6 RW

8A DMA Page – DMA Channel 7 RW

Port System Control Registers Default Acc

92 System Control RW

Port Slave Interrupt Controller Regs Default Acc

A0 Slave Interrupt Control — * A1 Slave Interrupt Mask — * A0 Slave Interrupt Control Shadow — A1 Slave Interrupt Mask Shadow —

* RW accessible if shadow registers are disabled

Port

Slave DMA Controller Registers Default Acc

C0 Channel 0 Base & Current Address RW C2 Channel 0 Base & Current Count RW C4 Channel 1 Base & Current Address RW C6 Channel 1 Base & Current Count RW

C8 Channel 2 Base & Current Address RW CA Channel 2 Base & Current Count RW CC Channel 3 Base & Current Address RW CE Channel 3 Base & Curr ent Count RW

D0 Status / Command RW

D2 Write Request

D4 Write Single Mask

D6 Write Mode

D8 Clear Byte Pointer FF DA Master Clear DC Clear Mask DE Read / Write Mask RW

RW RW

WO WO WO WO WO WO

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VT8231

Super-I/O Configuration Registers (I/O Spa ce)

Port Super-I/O Configuration Registers Default Acc

3F0 Super-I/O Config Index (Rx85[1]=1) 00 RW 3F1 Super-I/O Config Data (Rx85[1]=1) 00 RW

Super-I/O Config Registers (Indexed via Port 3F0/1)

Offset Super-I/O Control Default Acc

00-DF -reserved- 00 RO

E0 Super-I/O Device ID E1 Super-I/O Device Revision 00 E2 Function Se l ect 00 E3 Floppy Ctrlr Base Addr (def = 3F0-7)

E4-E5 -reserved- 00 RO

E6 Parallel Port Base Addr (def = 378-F) E7 Serial Port 1 Base Addr (def = 3F8-F) E8 Serial Port 2 Base Addr (def = 2F8-F)

E9-ED -reserved- 00 RO

EE Se rial Port Configuration 00

EF Power Down Control 00 F0 Parallel Port Control 00 F1 Serial Port Control 00 F2 Test Mode (Do Not Program) 00 F3 -reserved- 00 RO F4 Test Mode (Do Not Program) 2 00 F5 -reserved- 00 RO F6 Floppy Controller Configuration 00 F7 -reserved- 00 RO F8 Floppy Controller Drive Select 00

F9-FB -reserved- 00 RO

FC General Purpose I/O 00

FD-FF -reserved- 00 RO

3C RW

RW RW

FC RW

DE RW

FE RW BE RW

RW RW RW RW RW

Super-I/O I/O Ports

Offset Floppy Disk Controller (3F0-3F7) Default Acc

00-01 -reserved- 00 --

02 FDC Command -- RW 03 -reserved- 00 -04 FDC Main Status -04 FDC Data Rate Select 00 05 FDC Data -- RW 06 -reserved- 00 -07 Diskchange Status -07 FDC Configuration Control 00

Offset Parallel Port (378-37F typical) Default Acc

00 Parallel Port Data -- RW 01 P a r a llel Port Status -02 Parallel Port Control 03 EPP Address RW 04 EPP Data Port 0 RW 05 EPP Data Port 1 RW 06 EPP Data Port 2 RW

07 EPP Data Port 3 RW 400h ECP Data / Configuration A RW 401h ECP Configuration B RW 402h ECP Extended Control RW

Offset Serial Port 1 (COM1=3F8, 3=3E8) Default Acc

0 Transmit (Wr) / Receive (Rd) Buffer RW 1 Interrupt Enable RW 2 FIFO Control 2 Inte rrupt Status

3UART Control RW

4 Handshake Control RW

5UART Status RW

6 Hand s hake Status RW

7 Scratchpad RW

9-8 Baud Rate Generator Divisor RW

A-F -undefined- --

Offset Serial Port 2 (COM2=2F8, 4=2E8) Default Acc

0 Transmit (Wr) / Receive (Rd) Buffer RW 1 Interrupt Enable RW 2 FIFO Control 2 Inte rrupt Status

3UART Control RW

4 Handshake Control RW

5UART Status RW

6 Hand s hake Status RW

7 Scratchpad RW

9-8 Baud Rate Generator Divisor RW

A-F -undefined- --

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PCI Function 0 Registers – PCI-to-ISA Bridge

Configuration Space PCI-to-ISA B ridge Header Registers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status

8 Revision ID

9 Programming Interface 00 RO A Sub Class Code B Base Class Code C -reserved- (cache line size) 00 — D -reserved- (latency timer) 00 —

E Header Type

F Built In Self Test (BIST ) 00 RO

10-27 -reserved- (base address registers) 00 — 28-2B -reserved- (unassigned) 00 — 2F-2C Subsystem ID Read 00 RO

30-33 -reserved- (expan. ROM base addr) 00 — 34-3B -reserved- (unassigned) 00 —

3C -reserved- (interrupt line) 00 — 3D -reserved- (interrupt pin) 00 — 3E -reserved - (min gnt) 00 —

3F -reserved- (max lat) 00 —

Configuration Space PCI-to-ISA Bridge-Specific Registers

1106 8231 0087 RW 0200 WC

01 06

RO RO

VT8231

Offset Plug and Play Control Default Acc

50 PnP DMA Request Control 51 PnP Routing for LPT / FDC IRQ 00 RW 52 P nP Routing for COM2 / COM1 IRQ 00 RW 53 -reserved- 00 — 54 PCI IRQ Edge / Level Select 00 RW 55 PnP Routing for PCI INTA 00 RW 56 PnP Routing for PCI INTB-C 00 RW 57 PnP Routing for PCI INTD 00 RW 58 -reserved- 00 — 59 -reserved-

5A KBC / RTC Co ntrol

5B Internal RTC Test Mode 00 RW 5C DMA Control 00 RW

5D-5E -reserved- 00 —

5F -reserved- (do not program)

† Bit 7-4 power-up default depends on external strapping

Offset

6B-6A Channel 5 Base Address / Enable 0000 RW 6D-6C Channel 6 Base Address / Enable 0000 RW

6F-6E Channel 7 Base Address / Enable 0000 RW

Distributed DMA Default Acc

61-60 Channel 0 Base Address / Enable 0000 RW 63-62 Channel 1 Base Address / Enable 0000 RW 65-64 Channel 2 Base Address / Enable 0000 RW 67-66 Channel 3 Base Address / Enable 0000 RW 69-68 Serial IRQ Control 0000 RW

x4†

—

Offset ISA Bus Control Default Acc

40 ISA Bus Control 00 RW 41 ISA Test Mode 00 RW 42 ISA Clock Control 00 RW 43 ROM Decode Control 00 RW 44 Keyboard Controller Control 00 RW 45 Type F DMA Control 00 RW 46 Miscellaneous Control 1 00 RW 47 Miscellaneous Control 2 00 RW 48 Miscellaneous Control 3

49 -reserved- 00 — 4A IDE Interrupt Routing 4B -reserved- 00 — 4C DMA / Master Mem Access Control 1 00 RW 4D DMA / Master Mem Access Control 2 00 RW

4F-4E DMA / Master Mem Access Control 3

0300

Offset Miscellaneous Default Acc

70 Subsystem ID Write 00 WO

71-73 -reserved- 00 —

74 GPIO Control 1 00 RW 75 GPIO Control 2 00 RW 76 GPIO Control 3 00 RW 77 GPIO Control 4 00 RW

79-78 PCS0# I/O Port Address 0000 0000 RW 7B-7A PCS1# I/O Port Address 0000 0000 RW 7D-7C PCI DMA Channel Enable 0000 RW

7F-7E 32-Bit DMA Control 0000 RW

80 Programmable Chip Select Mask 00 RW 81 ISA Positive Decoding Control 1 00 RW 82 ISA Positive Decoding Control 2 00 RW 83 ISA Positive Decoding Control 3 00 RW 84 ISA Positive Decoding Control 4 00 RW 85 Extended Function Enable 00 RW

86-87 PnP IRQ/DRQ Test (do not program) 00 RW

88 PLL Test 00 RW 89 PLL Control 00 RW

8A PCS2/3 I/O Port Address Mask 00 RW

8B PCS Control 00 RW

8D-8C PCS2# I/O Port Address 0000 RW

8F-8E P CS3# I/O Port Address 0000 RW 90-FF -reserved- 00 —

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PCI Function 1 Registers – IDE Controller

VT8231

Configuration Space IDE Header Registers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status

8 Revision ID

9 Programming Interface A Sub Class Code B Base Class Code C -reserved- (cache line size) 00 — D Latency Timer 00

E Header Type 00 RO

F Built In Self Test (BIST ) 00 RO

13-10 Base Address – Pri Data / Command

17-14 Base Address – Pri Control / Status 1B-18 Base Address – Sec Data / Command 1F-1C Base Address – Sec Control / Status

23-20 Base Address – Bus Master Control

24-2F -reserved- (unassigned) 00 —

30-33 -reserved- (expan ROM base addr) 00 —

34 Capability Pointer

35-3B -reserved- (unassigned) 00 —

3C Interrupt Line 3D Interrupt Pin 00 RO 3E Minimum Grant 00 R O

3F Maximum Latency 00 R O

Configuration Space IDE-Specific Registers

Offset Configuration Space IDE Registers Default Acc

40 IDE Chip Enable 41 IDE Configuration 42 -reserved- (do not program) 43 IDE FIFO Configuration 44 IDE Miscellaneous Control 1 45 IDE Miscellaneous Control 2 46 IDE Miscellaneous Control 3

4B-48 IDE Drive Timing Control

4C IDE Address Setup Time 4D -reserved- (do not program) 00 4E Sec Non-1F0 IDE Port Access Timing

4F Pri Non-1F0 IDE Port Access Timing

1106 0571 0080 0280 RW

85 RW 01 01

000001F0 000003F4 00000170 00000374

0000CC01 RW

0E RW

08 02 09 RW

68 03

A8A8A8A8

FF FF

RO RO RO

RO RO

RO RO RO RO

RW RW

RW RW RW RW RW RW

RW RW

Configuration Space IDE-Specific Registers ( c ontinued)

Offset Configuration Space IDE Registers Default Acc

53-50 UltraDM A E xtended Timing Control

54 UltraDMA FIFO Control 55-5F -reserved- 00 — 61-60 IDE Primary Sector Size 62-67 -reserved- 00 — 69-68 IDE Secondary Sector Size 69-6F -reserved- 00 —

70 IDE Primary Status 00 RW

71 IDE Primary Interrupt Control 00 RW 72-77 -reserved- 00 —

78 IDE Secondary Status 00 RW

79 IDE Secondary Interrupt Control 00 RW

7A-7F -reserved- 00 —

83-80 IDE Primary S/G Descriptor Address 0000 0000 RW 84-87 -reserved- 00 —

8B-88 IDE Secondary S/G Descriptor Addr 0000 0000 RW 8C-BF -reserved- 00 — C3-C0 PCI PM Block 1 C7-C4 P CI PM Block 2 0000 RW C8-FF -reserved- 00 —

I/O Registers – IDE Controller (SFF 8038 v1.0 Compliant

Offset IDE I/O Registers Default Acc

0 Primary Channel Command 00 RW 1 -reserved- 00 — 2 Primary Channel Status 00 3 -reserved- 00 —

4-7 Primary Channel PRD Table Addr 00 RW

8 Se condary Channel Command 0 0 RW

9 -reserved- 00 — A Secondary Channel Status 00 B -reserved- 00 —

C-F Secondary Channel PRD Table Addr 00 RW

03030303

0200

0201 RO

RW RW

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PCI Function 2 Registers – USB Controller Ports 0-1

Configuration Space USB Header Regist ers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 0000 7-6 Status

8 Revision ID

9 Programming Interface 00 RO A Sub Class Code B Base Class Code C Cache Line Size 00 RO D Latency Timer

E Header Type 00 RO

FBIST 00 RO

10-1F -reserved- 00 — 23-20 USB I/O Register Base Address

24-3B -reserved- 00 —

3C Interrupt Line 00 3D Interrupt Pin

3E-3F -reserved- 00 —

1106 3038

0200 WC

16 RW

00000301 RW

04 RO

RO RO

PCI Function 3 Registers – USB Controller Ports 2-3

Configuration Space USB Header Regist ers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 0000 7-6 Status

8 Revision ID

9 Programming Interface 00 RO A Sub Class Code B Base Class Code C Cache Line Size 00 RO D Latency Timer E Header Type 00 RO

FBIST 00 RO

10-1F -reserved- 00 — 23-20 USB I/O Register Base Address

24-3B -reserved- 00 —

3C Interrupt Line 00

3D Interrupt Pin

3E-3F -reserved- 00 —

1106 3038

0200 WC

16 RW

00000301 RW

04 RO

RO RO

Configuration Space USB-Specific Registers

Offset USB Control Default Acc

40 USB Miscellaneous Contro l 1 00 41 USB Miscellaneous Contro l 2 42 USB FIFO Control 00

43 -reserved- 00 RO 44-45 -reserved- (test, do not program) 46-47 -reserved- (test) RO 48-5F -reserved- 00 —

60 USB Serial Bus Release Number 61-7F -reserved- 00 — 83-80 PM Capability

84 PM Capability Status 00

85-BF -reserved- 00 — C1-C0 USB Legacy Support C2-FF -reserved- 00 —

I/O Registers – USB Controller

Offset USB I/O Registers Default Acc

1-0 USB Command 0000 RW 3-2 USB Status 0000 5-4 USB Interrupt Enable 0000 RW 7-6 Frame Number 0000 RW

B-8 Frame List Base Address 00000000 RW

C Start Of Frame Modify 11-10 Port 0 Status / Control 13-12 Port 1 Status / Control 14-1F -reserved- 00 —

10 RW

0002 0001

2000 RW

40 0080 WC 0080 WC

Configuration Space USB-Specific Registers

Offset USB Control Default Acc

40 USB Miscellaneous Contro l 1 00 41 USB Miscellaneous Contro l 2 42 USB FIFO Control 00

43 -reserved- 00 RO 44-45 -reserved- (test only, do not program) 46-47 -reserved- (test) RO 48-5F -reserved- 00 —

60 USB Serial Bus Release Number 61-7F -reserved- 00 — 83-80 PM Capability

84 PM Capability Status 00

85-BF -reserved- 00 — C1-C0 USB Legacy Support C2-FF -reserved- 00 —

I/O Registers - USB Controller

Offset USB I/O Registers Default Acc

1-0 USB Command 0000 RW 3-2 USB Status 0000 5-4 USB Interrupt Enable 0000 RW 7-6 Frame Number 0000 RW

B-8 Frame List Base Address 00000000 RW

C Start Of Frame Modify 11-10 Port 2 Status / Control 13-12 Port 3 Status / Control 14-1F -reserved- 00 —

10 RW

0002 0001

2000 RW

40 0080 WC 0080 WC

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PCI Function 4 Registers - Power Management

VT8231

Configuration Space Power Management Header Registers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 0000 RO 7-6 Status

8 Revision ID

9Programming Interface A Sub Class Code B Base Class Code C Cache Line Size 00 RO D Latency Timer 00 RO

E Header Type00RO

FBIST 00 RO

10-3F -reserved- 00 — † The default values for these registers may be changed by writing to offsets 61-63h (see below).

Configuration Space Power Management Registers

Offset Power Management Default Acc

40 General Configuration 0 00 RW 41 General Configuration 1 00 RW 42 ACPI Interrupt Select 00 RW

43 Internal Timer Read Test 45-44 Primary Interrupt Channel 0000 RW 47-46 Secondary Interrupt Channel 0000 RW

4B-48 Power Mgmt I/O Base (256 Bytes)

4C Host Bus Power Management Control 00 RW

4D Throttle / Clock Stop Control 00 RW 4E-4F -reserved- 00 53-50 GP Timer Control 0000 0000 RW

54 Power Well Control 00 RW 55 USB Wakeup Control 00 RW

56-57 -reserved- 00

58 GP2 / GP3 Timer Control 00 RW 59 GP2 Timer 00 RW

5A GP3 Timer 00 RW

5B-60 -reserved- 00

61 Write value for Offset 9 (Prog Intfc) 00 62 Write value for Offset A (Sub Class) 00 63 Write value for Offset B (Base Class) 00

64-7F -reserved- 00

1106 3068

0280 WC

— RO

0000 0001

RO RO

RO RO RO RO

—

WO WO WO

—

Configuration Space Hardware Monitor Registers

Offset System Management Bus Default Acc

71-70 Hardware Mon IO Base (128 Bytes) 72-73 -reserved- 00

74 Hardware Monitor Control 00 RW

75-8F -reserved- 00

Configuration Space SMBus Registers

Offset System Management Bus Default Acc

93-90 SMBus I/O Base (16 Bytes)

94-D1 -reserved- 00

D2 SMBus Host Configuration 00 RW D3 SMBus Host Slave Command 00 RW D4 SMBus Slave Address Shadow Port 1 00 RW D5 SMBus Slave Address Shadow Port 2 00 RW D6 SMBus Revision ID

D7-FF -reserved- 00

0001

0000 0001

nn RO

—

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I/O Space Power Management- Registers

Offset Basic Control / Status Registers Default Acc

1-0 Power Management Status 0000

3-2 Power Management Enable 0000 RW

5-4 Power Management Control 0000 RW

6-7 -reserved- 00

B-8 Power Management Timer 0000 0000 RW C-F -reserved- 00

Offset Processor Registers Default Acc

13-10 Processor and PCI Bus Control 0000 0000 RW

14 Processor LVL2 00 15 Processor LVL3 00

16-1F -reserved- 00

Offset General Purpose Registers Default Acc

21-20 General Purpose Status 0000 23-22 General Purpose SCI Enable 0000 RW 25-24 General Purpose SMI Enable 0000 RW 26-27 -reserved- 00

Offset Generic Registers Default Acc

29-28 Global Status 0000

2B-2A Global Enable 0000 RW 2D-2C Global Control

2E -reserved- 00

2F SMI Command 00 RW 33-30 Primary Activity Detect Status 0000 0000 37-34 Primary Activity Detect Enable 0000 0000 RW

3B-38 GP Timer Reload Enable 0000 0000 RW 3C-3F -reserved- 00

0010

—

RO RO

—

I/O Space System Management Bus Registers

Offset System Management Bus Default Acc

0 SMBus Host Status 00 1 SMBus Slave Status 00 RW 2 SM Bus Host Control 00 RW 3 SMBus Host Command 00 RW 4 SMBus Host Address 00 RW 5 SMBus Host Data 0 00 RW 6 SMBus Host Data 1 00 RW 7 SM Bus Block Data 00 RW 8 SMBus Slave Control 00 RW

9 SMBus Shadow Command 00 A-B SMBus Slave Event 0000 RW C-D SMBus Slave Data 0000

E-F -reserved- 00

—

Offset General Purpose I/O Registers Default Acc

40 Extended I/O Trap Status 00 41 -reserved- 00 42 Extended I/O Trap Enable 00 RW 43 -reserved- 00 44 External SMI / GPI Input Value 45 SMI / IRQ / Resume Status 00

46-47 -reserved- 00 4B-48 GPI Port Input Value 4F-4C GPO Port Output Value

50-FF -reserved- 00

Preliminary Revision 0.8 October 29, 1999 -36- Register Overview

input RO

03FF FFFF

—

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I/O Space Hardware Monitor Registers

VT8231

Offset Hardwa re Monitor Default Acc

00-3F Value RAM 00-12 -reserved- 00

13 Analog Data 15-8 00 RW 14 Analog Data 7-0 00 RW 15 Digital Data 7-0 00 RW 16 Channel Counter 00 RW 17 Data Valid & Channel Indicators 00 RW

18-1C -reserved- 00

1D TSENS3 Ho t Hi Limit 00 RW

1E TSENS3 Hot Hysteresis Lo Lim 00 RW 1F TSENS3 (Int) Temp Reading 0 0 RW

20 TSENS1 (W13) Temp Reading 00 RW 21 TSENS2 (Y13) Temp Reading 00 RW 22 VSENS1 (U13) Voltage Reading 00 RW 23 VSENS2 (V13) Voltage Reading 00 RW 24 Internal Core VCC Voltage Reading 00 RW 25 VSENS3 (W14) Voltage Reading 00 RW 26 VSENS4 (Y14) Voltage Reading 00 RW 27 -reserved- (-12V Voltage Reading) 00 28 -reserved- (-5V Voltage Reading) 00 29 FAN1 (T12) Count Reading 00 RW

2A FAN2 (U12) Count Reading 00 RW

2B VSENS1 (CPU) Voltage High Limit 00 RW 2C VSENS1 (CPU) Voltage Low Limit 00 RW

2D VSENS2 (NB) Vo ltage High Limit 00 RW

2E VSENS2 (NB) Voltage Low Limit 00 RW 2F Internal Core VCC High Limit 00 RW

30 Internal Core VCC Low Limit 00 RW 31 VSENS3 (5V) Voltage High Limit 00 RW 32 VSENS3 (5V) Voltage Low Limit 00 RW 33 VSENS4 (12V) Voltage High Limit 00 RW 34 VSENS4 (12V) Voltage Low Limit 0 0 RW 35 -reserved- (-12V Sense High Limit) 00 36 -reserved- (-12V Sense Low Limit) 00 37 -reserved- (-5V Sense High Limit) 00 38 -reserved- (-5V Sense Low Limit) 00 39 TSENS1 Hot High Limit 00 RW

3A TSENS1 Hot Hysteresis Lo Lim 00 RW

3B FAN1 Fan Count Limit 00 RW 3C FAN2 Fan Count Limit 00 RW

3D TSENS2 Hot High Limit 00 RW

3E TSENS2 Hot Hysteresis Lo Lim 00 RW 3F Stepping ID Number 00 RW

—

— —

— — — —

Offset Hardware Monitor (continued) Default Acc

40 Hardware Monitor Configuration 41 Hardware Monitor Interrupt Status 1 00 42 Hardware Monitor Interrupt Status 2 00 43 Hardware Monitor Interrupt Mask 1 00 RW 44 Hardware Monitor Interrupt Mask 2 00 RW

45-46 -reserved- 00

47 Hardware Monitor Fan Configuration 48 -reserved- 00

49 HW Mon Temp Value Lo-Order Bits 00 RW 4A -reserved- 00 4B Temperat ure Interrupt Configur ation

4C-FF -reserved- 00

RO RO

—

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PCI Function 5 & 6 Registers – AC97 / MC97 Codecs

VT8231

Function 5 Configuration Space AC97 Header Registers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 0000 7-6 Status

8 Revision ID

9 Programming Interface 00 RO A Sub Class Code B Base Class Code C Cache Line Size 00 RO D Latency Timer 00

E Header Type 00 RO

FBIST 00 RO

13-10 Base Address 0 - SGD Control/Status

17-14 Base Address 1 - FM NMI Status 1B-18 Base Address 2 - MIDI Port 1F-1C Base Address 3 (reserved) 0000 0000 —

23-20 Base Address 4 (reserved) 0000 0000 —

27-24 Base Address 5 (reserved) 0000 0000 —

28-29 -reserved- 00 — 2F-2C Subsystem ID / SubVendor ID 0000 0000

33-30 Expansion ROM (reserved) 0000 0000 —

34 Capture Pointer 00

35-3B -reserved- 00 —

3C Interrupt Line 00 3D Interrupt Pin 3E Minimum Grant 00 R O

3F Maximum Latency 00 R O

1106 3058

0210 WC

01 04

0000 0001 RW 0000 0001 RW 0000 0331 RW

RO RO

Function 6 Configuration Space MC97 Header Registers

Offset PCI Configuration Space Header Default Acc

1-0 Vendor ID 3-2 Device ID 5-4 Command 0000 7-6 Status

8 Revision ID

9 Programming Interface 00 RO A Sub Class Code B Base Class Code C Cache Line Size 00 RO D Latency Timer 00 E Header Type 00 RO

FBIST 00 RO

13-10 Base Address 0 - SGD Control/Status

17-14 Base Address 1 - (reserved) 0000 0000 1B-18 Base Address 2 - (reserved) 0000 0000 1F-1C Base Address 3 – Codec Reg Shadow

23-20 Base Address 4 (reserved) 0000 0000 —

27-24 Base Address 5 (reserved) 0000 0000 —

28-29 -reserved- 00 — 2F-2C Subsystem ID / SubVendor ID 0000 0000

33-30 Expansion ROM (reserved) 0000 0000 —

34 Capture Pointer 00

35-3B -reserved- 00 —

3C Interrupt Line 00

3D Interrupt Pin

3E Minimum Grant 00 R O 3F Maximum Latency 00 R O

1106 3068

0200 WC

80 07

0000 0001 RW

0000 0001

RO RO

RW RW

—

Configuration Space Audio Codec-Specific Regist ers

Offset Audio Codec Link Control Default Acc

40 AC-Link Interface Status 00 41 AC-Link Interface Control 00 RW 42 Functi on Enable 00 RW 43 Plug and Play Control 44 MC97 Interface Control 00

45-47 -reserved- 00 —

48 FM NMI Control 00 RW 49 -reserved- 00 —

4B-4A Game Port Base Address 0000 RW

4C-FF -reserved- 00 —

Preliminary Revision 0.8 October 29, 1999 -38- Register Overview

Configuration Space Modem Codec-Specific Registers

Offset Modem Codec Link Control Default Acc

40 AC-Link Interface Status 00 41 AC-Link Interface Control 00 RW 42 Function Enable 00 43 Plug and Play Control 44 MC97 Interface Control 00 RW

45-47 -reserved- 00 —

48 FM NMI Control 00

49 -reserved- 00 — 4B-4A Game Port Base Address 0000 4C-FF -reserved- 00 —

1C RO

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Func 5 I/O Base 0 Regs – Audio Scatter-Gather DMA

Offset SGD I/O Registers (DSXn: n=1-3

n0 SGD DXSn Read Channel Status 0 0 n1 SGD DXSn Read Channel Control 00 RW n2 SGD DXSn Read Chan Left Volume 0 0 RW n3 SGD DXSn Read Chan Right Volume 00 RW

n7-n4 SGD DXSn Read Ch Table Ptr Base

SGD DXSn Read Ch Current Address

nB-n8 SGD DXSn Read Channel Format 0000 0000

nF-nC SGD DXSn Read Chan Index / Count 0000 0000

40 SGD 3D Channel Status 00 41 SGD 3D Channel Control 00 RW 42 SGD 3D Channel Format 00 RW 43 SGD 3D Channel Scratch 00 RW

47-44 SGD 3D Channel Table Ptr Base

SGD 3D Channel Curr ent Address 4B-48 SGD 3D Channel Slot Select 0000 0000 RW 4F-4C SGD 3D Channel Index / Count 0000 0000

50 SGD FM Channel Status 00 51 SGD FM Channel Control 00 RW 52 SGD FM Channel Type 00 RW 53 -reserved- 00 —

57-54 SGD FM Channel Table Pointer Base

SGD FM Channel Current Ad dress 58-5B -reserved- 00 — 5F-5C SGD FM Channel Current Count 0000 0000

60 SGD Write Channel 0 Status 00 61 SGD Write Channel 0 Contro l 00 RW 62 SGD Write Channel 0 Format 00 RW 63 -reserved- 00 —

67-64 SGD Write Channel 0 Table Ptr Base

SGD Write Channel 0 Current Addr 68-6B -reserved- 00 — 6F-6C SGD Write Channel 0 Current Count 0000 0000

70 SGD Write Channel 1 Status 00 71 SGD Write Channel 1 Contro l 00 RW 72 SGD Write Channel 1 Format 00 RW 73 -reserved- 00 —

77-74 SGD Write Channel 1 Table Ptr Base

SGD Write Channel 1 Current Addr 78-7B -reserved- 00 — 7F-7C SGD Write Channel 1 Current Count 0000 0000

Offset AC97 Controller I/O Registers Default Acc

80-DF -reserved- 00 — E3-E0 AC97 Controller Command / Status 0000 0000 RW E4-EF -reserved- 00 —

F3-F0 SGD Status Shadow 0000 0000 F4-FF -reserved- 00 —

The above registers are accessable through

Default Acc

0000 0000 WR

function 5

RO RO

only.

Function 5 I/O Base 1 Registers – FM NMI Status

Offset FM NMI St atus Registers Default Acc

0FM NMI Status 00 1 FM NMI Data 00 2 FM NMI Index 00 3 Reserved 00 —

The above registers are accessable through

Function 5 I/O Base 2 Registers – MIDI / Game Port

Offset FM NMI St atus Registers Default Acc

1-0 MIDI Port Base 0330 RW 3-2 Game Port Base 0200 RW

The above registers are accessable through

Func 6 I/O Base 0 Regs – Modem Scatter Gather DMA

Offset MC97 SGD I/O Registers Default Acc

0 SGD Modem Read Channel Status 00 1 SGD Modem Read Channel Control 00 RW 2 SGD Modem Read Channel Type 00 RW 3 -reserved- 00 —

7-4 SGD Modem Read Ch Table Ptr Base

SGD Modem Read Ch Current Addr 8-B -reserved- 00 — F-C SGD Modem Read Ch Current Count 0000 0000

10 SGD Modem Write Channel Status 00 11 SGD Modem Write Channel Control 00 RW 12 SGD Modem Write Channel Type 00 RW 13 -reserved- 00 —

17-14 SGD Modem Wr Ch Table Ptr Base

SGD Modem Wr Ch Current Address

18-1B -reserved- 00 — 1F-1C SGD Modem Write Ch Current Count 0000 0000

Offset Modem Codec I/O Registers Default Acc

23-20 Modem Codec Command / Status 0000 0000 RW 24-2F -reserved- 00 — 33-30 Codec GPI Interrupt Status / GPIO 0000 0000 37-34 Codec GPI Interrupt Enable 0000 0000 RW

38-FF Reserved 00 —

The above registers are accessable through

function 5

0000 0000 WR

function 6

RO RO RO

only.

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I/O Registers – SoundBlaster Pr o

Offset SB Pro Registers (220 or 240h typ) Default Acc

0 FM Le ft Channel Index / Status RW 1 FM Left Channel Data 2 FM Right Channel Index / Status RW 3 FM Right Channel Data 4Mixer Index 5 Mixer Data RW 6 Sound Processor Reset 7 -reserved- 00 -8 FM I ndex / Status (Both Channels) RW

9 FM D ata (Both Channels) A So und Processor Data B -reserved- 00 -C Sound Processor Co mmand / Data

Sound Proce ssor Buffer Status D -reserved- 00 -E Snd Processor Data Available Status F -reserved- 00 --

Port SB Pro Regs (same as offsets 8 & 9) Default Acc

388h FM Index / Status RW

389h FM Data The above group of registers emulates the “FM”, “Mixer”, and “Sound Processor” functions of the SoundBlas t er Pro.

WO WO

I/O Registers – Game Por t

Offset Game Port (200-20F typical) Default Acc

0 -reserved- 00 -1 Game Port Status 1Start One-Shot

2-F -reserved- 00 --

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Legacy I/O Ports

This group of registers includes the DMA Controllers, Interrupt Controllers, and Timer/Counters as well as a number of miscellaneous ports originally implemented using discrete logic on original PC/AT motherboards. All of the registers listed are integrated on-chip. These registers are implemented in a precise manner for backwards compatibility with previous generations of PC hardware. These registers are listed for information purposes only. Detailed descriptions of the actions and programming of these registers are included in numerous industry publications (duplication of that information here is beyond the scope of this document). All of these registers reside in I/O space.

Port 61 - Misc Functions & Speaker Control ................. RW

7 Reserved 6 IOCHCK# Active

This bit is set when the ISA bus IOCHCK# signal is asserted. Once set, this bit may be cleared by setting bit-3 of this register. Bit-3 should be cleared to enable recording of the next IOCHCK#. IOCHCK# generates NMI to the CPU if NMI is enabled.

5 Timer/Counter 2 Output

This bit reflects the output of Timer/Counter 2 without any synchronization.

4 Refresh Detected

This bit toggles on every rising edge of the ISA bus REFRESH# signal.

3 IOCHCK# Disable

0 Enable IOCHCK# assertions................. default

1 Force IOCHCK# inactive and clear any

2 Reserved 1 Speaker Enable

0 Disable...................................................default

1 Enable Timer/Ctr 2 output to drive SPKR pin

0 Timer/Counter 2 Enable

0 Disable...................................................default

1 Enable Timer/Counter 2

........................................always reads 0

.................................................RO

......................................RO

...................................................RO

...............................................RW

“IOCHCK# Active” condition in bit-6

........................................RW, default=0

....................................................RW

.....................................RW

Port 92h - System Control ................................................ RW

7-6 Hard Disk Activity LED Status

0 Off .................................................... default

1-3 On

5-4 Reserved

3 Power- On Password Bytes Inaccessable 2 Reserved 1 A20 Address Line Enable

0 A20 disabled / forced 0 (real mode)...... default

1 A20 address line enabled

0 High Speed Reset

0Normal 1 Briefly pulse system reset to switch from

........................................always reads 0

..default=0

........................................always reads 0

protected mode to real mode

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Keyboard Controller Registers

The keyboard controller handles the keyboard and mouse interfaces. Two ports are used: port 60 and port 64. Reads from port 64 return a status byte. Writes to port 64h are command codes (see command code list following the register descriptions). Input and output data is transferred via port 60.

A “Control” register is also available. It is accessable by writing commands 20h / 60h to the command port (port 64h); The control byte is written by first sending 60h to the command port, then sending the control byte value. The control register may be read by sending a command of 20h to port 64h, waiting for “Output Buffer Full” status = 1, then reading the control byte value from port 60h.

Traditional (non-integrated) keyboard controllers have an “Input Port” and an “Output Port” with specific pins dedicated to certain functions and other pins available for general purpose I/O. Specific commands are provided to set these pins high and low. All outputs are “open-collector” so to allow input on one of these pins, the output value for that pin would be set high (non-driving) and the desired input value read on the input port. These ports are defined as follows:

Bit Input Port

0 P10 - Keyboard Data In B0 B8 1 P11 - Mouse Data In B1 B9 2 P12 - Turbo Pin (PS/2 mode only) B2 BA 3 P13 - user-defined B3 BB 4 P14 - user-defined B6 BE 5 P15 - user-defined B7 BF 6 P16 - user-defined –– 7 P17 - undefined ––

Bit Output Port

0 P20 - SYSRST (1=execute r e set) –– 1 P21 - GATEA20 (1=A20 enabled) –– 2 P22 - Mouse Data Out B4 BC 3 P23 - Mouse Clock Out B5 BD 4 P24 - Keyboard OBF Interrupt (IRQ1) –– 5 P25 - Mouse OBF Interrupt (IRQ 12) –– 6 P26 - Keyboard Clock Out –– 7 P27 - Keyboard Data Out ––

Bit Test Port Lo Code

0 T0 - Keyboard Clock In ––

1 T1 - Mouse Clock In –– Note: Command code C0h transfers input port data to the output buffer. Command code D0h copies output port values to the output buffer. Command code E0h transfers test input port data to the output buffer.

Port 60 - Keyboard Controller Input Buffer ................. WO

Only write to port 60h if port 64h bit-1 = 0 (1=full).

Port 60 - Keyboard Controller Output Buffer ................ RO

Only read from port 60h if port 64h bit-0 = 1 (0=empty).

Lo Code Hi Code

Hi Code

Port 64 - Keyboard / Mouse Status .................................. RO

7 Parity Error

0 No parity error (odd parity received)..... default

1 Even parity occurred on last byte received

from keyboard / mouse

6 General Receive / Transmit Timeout

0 No error ................................................. default

1 Error

5 Mouse Output Buffer F ull

0 Mouse output buffer empty....................default

1 Mouse output buffer holds mouse data

4 Keylock Status

0Locked 1Free

3 Command / Data

0 Last write was data write ....................... default

1 Last write was command write

2 System Flag

0 Power-On Default.................................. default

1 Self Test Successful

1 Input Buffer Full

0 Input Buffer Empty................................ default

1 Input Buffer Full

0 Keyboard Output Buffer Full

0 Keyboard Output Buffer Empty.............default

1 Keyboard Output Buffer Full

KBC Control Register .......... (R/W via Commands 20h/60h)

7 Reserved 6 PC Compatibility

0 Disable scan conversion 1 Convert scan codes to PC format; convert 2-

5 Mouse Disable

0 Enable Mouse Interface......................... default

1 Disable Mouse Interface

4 Keyboard Disable

0 Enable Keyboard Interface.................... default

1 Disable Keyboard Interface

3 Keyboard Lock Disable

0 Enable Keyboard Inhibit Function.........default

1 Disable Keyboard Inhibit Function

2 System Flag

This bit may be read back as status register bit-2

1 Mouse Inter rupt Enable

0 Disable mouse interrupts ....................... default

1 Generate interrupt on IRQ12 when mouse data

0 Keyboard Interrupt Enable

0 Disable Keyboard Interrupts.................. default

1 Generate interrupt on IRQ1 when output buffer

........................................always reads 0

byte break sequences to 1-byte PC-compatible

break codes............................................ default

................................................default=0

comes in output bufer

has been written.

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Port 64 - Keyboard / Mouse Command .......................... WO

This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT8231 are listed n the table below.

Note: The VT8231 Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Keyboard Controller except that due to its integrated nature, many of the input and output port pins are not available externally for use as general purpose I/ O p ins ( eve n tho ugh P 1 3 -P1 6 a re set o n p o wer-up a s strapping options). In other words, many of the commands below are provided and “work”, but otherwise perform no useful function (e.g., co mmands that set P1 2-P 17 hi gh or l ow). Also note that setting P10-11, P22-23, P26-27, and T0-1 high or low directly serves no useful purpose, since these bits are used to implement the keyboard and mouse ports and are directly controlled by keyboard controller logic.

Table 4. Keyboard Controller Command Codes

VT8231

Code Keyboard Command Code Description

20h Read Control B yte (next byte is Control Byte) 21-3Fh Read SRAM Data (next byte is Data Byte) 60h Write Contro l Byte (next byte is Control Byte) 61-7Fh Write SRAM Data (next byte is Data Byte)

9xh Write low nibble (bits 0-3) to P10-P13 A1h Output Keyboard Co ntroller Version # A4h Test if Password is installed

(always returns F1h to indicate not installed) A7h Disable Mouse Interface A8h Enable Mouse Interface A9h Mouse Interface Test (puts test results in port 60h)

(value: 0=OK, 1=clk stuck low, 2=clk stuc k hi gh,

3=data stuck lo, 4=data stuck hi, FF=general error) AAh KBC self test (returns 55h if OK, FCh if not) ABh Keyboard Interface Test (see A9h Mouse Test) ADh Disable Keyboard Interface AEh Enable Keyboard Interface AFh Return Version #

B0h Set P10 low B1h Set P11 low B2h Set P12 low B3h Set P13 low B4h Set P22 low B5h Set P23 low B6h Set P14 low B7h Set P15 low B8h Set P10 high B9h Set P11 high BAh Set P12 high BBh Set P13 high BCh Set P22 hi gh BDh Set P23 high BEh S et P14 high BFh Set P1 5 high

Code Keyboard Command Code Description

C0h Read input port (read P10-17 input data to

the output buffer)

C1h Poll input port low (read input data on P11-13

repeatably & put in bits 5-7 of status

C2h Poll input port high (same except P15-17) C8h Unblock P22-23 (use before D1 to change

active mode)

C9h Reblock P22-23 (protection mechanism for D1) CAh Read mode (output KBC mode info to port 60

output buffer (bit-0=0 if ISA, 1 if PS/2)

D0h Read Output Port (copy P10-17 output port values

to port 60)

D1h Write Output Port (data byte following is written to

keyboard output port as if it came from keyboard)

D2h Write Keyboard Output Buffer & clear status bit-5

(write following byte to keyboa r d)

D3h Write Mouse Output Buffer & set status bit-5 (write

following byte to mouse; put value in mouse input buffer so it appears to have come from the mouse)

D4h Write Mouse (write following byte to mouse) E0h Read test inputs (T0-1 read to bits 0-1 of resp byte)

Exh Set P23-P21 per command bits 3-1 Fxh Pulse P23-P20 low for 6usec per command bits 3-0

All other codes not listed are undefined.

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DMA Controller I/O Registers

VT8231

Ports 00-0F - Master DMA Controller

Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3. There are 16 Master DMA Controller registers:

I/O Address Bits 15-0 Register Name

0000 0000 000x 0000 Ch 0 Base / Current Address RW 0000 0000 000x 0001 Ch 0 Base / Current Count RW 0000 0000 000x 0010 Ch 1 Base / Current Address RW 0000 0000 000x 0011 Ch 1 Base / Current Count RW 0000 0000 000x 0100 Ch 2 Base / Current Address RW 0000 0000 000x 0101 Ch 2 Base / Current Count RW 0000 0000 000x 0110 Ch 3 Base / Current Address RW 0000 0000 000x 0111 Ch 3 Base / Current Count RW 0000 0000 000x 1000 Status / Command RW 0000 0000 000x 1001 Write Request WO 0000 0000 000x 1010 Write Single Mask WO 0000 0000 000x 1011 Write Mode WO 0000 0000 000x 1100 Clear Byte Pointer F/F WO 0000 0000 000x 1101 Master Clear WO 0000 0000 000x 1110 Clear Mask WO 0000 0000 000x 1111 R/W All Mask Bits RW

Ports C0-DF - Slave DMA Controller

Channels 0-3 of the Slave DMA Controller control System DMA Channels 4-7. There are 16 Slave DMA Controller registers:

I/O Address Bits 15-0 Register Name

0000 0000 1100 000x Ch 4 Base / Current Address RW 0000 0000 1100 001x Ch 4 Base / Current Count RW 0000 0000 1100 010x Ch 5 Base / Current Address RW 0000 0000 1100 011x Ch 5 Base / Current Count RW 0000 0000 1100 100x Ch 6 Base / Current Address RW 0000 0000 1100 101x Ch 6 Base / Current Count RW 0000 0000 1100 110x Ch 7 Base / Current Address RW 0000 0000 1100 111x Ch 7 Base / Current Count RW 0000 0000 1101 000x Status / Com m and RW 0000 0000 1101 001x Write Request WO 0000 0000 1101 010x Write Single Mask WO 0000 0000 1101 011x Write Mode WO 0000 0000 1101 100x Clear Byte Pointer F/F WO 0000 0000 1101 101x Master Clear WO 0000 0000 1101 110x Clear Mask WO 0000 0000 1101 111x Read/Write All Mask Bi ts WO

Note that not all bits of the address are decoded. The Master and Slave DMA Controllers are compatible with

the Intel 8237 DMA Controller chip . Detailed description of 8237 DMA controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.

Ports 80-8F - DMA Page Registers

There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses:

I/O Address Bits 15-0 Register Name

0000 0000 1000 0111 Channel 0 DMA Page (M-0).........RW

0000 0000 1000 0011 Channel 1 DMA Page (M-1).........RW

0000 0000 1000 0001 Channel 2 DMA Page (M-2).........RW

0000 0000 1000 0010 Channel 3 DMA Page (M-3).........RW

0000 0000 1000 1111 Channel 4 DMA Page (S-0)..........RW

0000 0000 1000 1011 Channel 5 DMA Page (S-1)..........RW

0000 0000 1000 1001 Channel 6 DMA Page (S-2)..........RW

0000 0000 1000 1010 Channel 7 DMA Page (S-3) .........RW

DMA Controller Shadow Registers

The DMA Controller shadow registers are enabled by setting function 0 Rx77 bit 0. If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard DMA controller registers (writes are unchanged).

Port 0 –Channel 0 Base Address ...................................... RO

Port 1 –Channel 0 Byte Count .......................................... RO

Port 2 –Channel 1 Base Address ...................................... RO

Port 3 –Channel 1 Byte Count .......................................... RO

Port 4 –Channel 2 Base Address ...................................... RO

Port 5 –Channel 2 Byte Count .......................................... RO

Port 6 –Channel 3 Base Address ...................................... RO

Port 7 –Channel 3 Byte Count .......................................... RO

Port 8 –1st Read Channel 0-3 Command Register .......... RO

Port 8 –2nd Read Channel 0-3 Request Register.............. RO

Port 8 –3rd Read Channel 0 Mode Register ..................... RO

Port 8 –4th Read Channel 1 Mode Register ..................... RO

Port 8 –5th Read Channel 2 Mode Register ..................... RO

Port 8 –6th Read Channel 3 Mode Register ..................... RO

Port F –Channel 0-3 Read All Mask ................................ RO

Port C4 –Channel 5 Base Address.................................... RO

Port C6 –Channel 5 Byte Count ....................................... RO

Port C8 –Channel 6 Base Address.................................... RO

Port CA –Channel 6 Byte Count ...................................... RO

Port CC –Channel 7 Base Address ................................... RO

Port CE –Channel 7 Byte Count ...................................... RO

Port D0 –1st Read Channel 4-7 Command Register ........ RO

Port D0 –2nd Read Channel 4-7 Request Register ........... RO

Port D0 –3rd Read Channel 4 Mode Register .................. RO

Port D0 –4th Read Channel 5 Mode Register .................. RO

Port D0 –5th Read Channel 6 Mode Register .................. RO

Port D0 –6th Read Channel 7 Mode Register .................. RO

Port DE –Channel 4-7 Read All Mask ............................. RO

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VT8231

Interrupt Controller Registers

Ports 20-21 - Master Interrupt Controller

The Master Interrupt Controller controls system interrupt channels 0-7. Two registers control the Master Interrupt Controller. They are:

I/O Address Bits 15-0 Register Name

0000 0000 001x xxx0 Master Interrupt Control RW 0000 0000 001x xxx1 Master Interrupt Mask RW

Note that not all bits of the address are decoded. The Master Interrupt Controller is compatible with the Intel

8259 Interrupt Co ntroller chip. Detailed descriptions of 8259 Interrupt Controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.

Ports A0-A1 - Slave Interrupt Cont roller

The Slave Interrupt Controller controls system interrupt channels 8-15. The slave system interrupt controller also occupies two register locations:

I/O Address Bits 15-0 Register Name

0000 0000 101x xxx0 Slave Interrupt Control RW 0000 0000 101x xxx1 Slave Interrupt Mask RW

Note that not all address bits are decoded. The Slave Interrupt Controller is compatible with the Intel

8259 Interrupt Co ntroller chip. Detailed descriptions of 8259 Interrupt Controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.

Interrupt Controller Shadow Registers

The following shadow registers are enabled by setting function 0 Rx47[4]. If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard interrupt controller registers (writes are unchanged).

Port 20 - Master Interrupt Control Shadow ................... RO

Port A0 - Slave Interrupt Control Shadow ..................... RO

7 Reserved

........................................always reads 0

6 OCW3 bit 2 (POLL) 5 OCW3 bit 0 (RIS) 4 OCW3 bit 5 (SMM) 3 OCW2 bit 7 (R) 2 ICW4 bit 4 (SFNM) 1 ICW4 bit 1 (AEOI) 0 ICW1 bit 3 (LTIM)

Port 21 - Master Interrupt Mask Shadow ....................... RO

Port A1 - Slave Interrupt Mask Shadow ........................ RO

7-5 Reserved

........................................always reads 0

4-0 T7-T3 of Interrupt Vector Address

Timer / Counter Registers

Ports 40-43 - Timer / Counter Registers

There are 4 Timer / Counter registers: I/O Address Bits 15-0 Register Name

0000 0000 010x xx00 Timer / Counter 0 Cou nt RW 0000 0000 010x xx01 Timer / Counter 1 Cou nt RW 0000 0000 010x xx10 Timer / Counter 2 Cou nt RW 0000 0000 010x xx11 Timer / Counter Cmd Mode WO

Note that not all bits of the address are decoded. The Timer / Counters are compatible with the Intel 8254

Timer / Counter chip. Detailed descriptions of 8254 Timer / Counter operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.

Timer / Counter Shadow Registers

The following shadow registers are enabled for readback by setting function 0 Rx47[4]. If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard timer / counter registers (writes are unchanged).

Port 40 – Counter 0 Base Count Value (LSB 1

MSB 2nd) RO Port 41 – Counter 1 Base Count Value (LSB 1st MSB 2nd) RO Port 42 – Counter 2 Base Count Value (LSB 1st MSB 2nd) RO

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CMOS / RTC Registers

Port 70 - CMOS Address .................................................. RW

7NMI Disable

0 Enable NMI Generation. NMI is asserted on

1 Disable NMI Generation........................ default

6-0 CMOS Address

Port 71 - CMOS Data........................................................ RW

7-0 CMOS Data

Note: P orts 70-71 may be accessed if Rx5A bit-2 is set to

one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 70-71 will be directed to an external RTC.

.........................................................RW

encountering IOCHCK# on the ISA bus or SERR# on the PCI bus.

(lower 128 bytes).......................RW

(128 bytes)

Offset Description

00 Seconds 01 Seconds Alarm 02 Minutes 03 Minutes Alarm 04 Hours

05 Hours Alarm

06 Day of the Week 07 Day of the Month 08 Month 09 Year

VT8231

Binary Range BCD Range

00-3Bh 00-59h 00-3Bh 00-59h 00-3Bh 00-59h

00-3Bh 00-59h am 12hr: 01-1Ch 01-12h pm 12hr: 81-8Ch 81-92h

24hr: 00-17h 00-23h am 12hr: 01-1Ch 01-12h pm 12hr: 81-8Ch 81-92h

24hr: 00-17h 00-23h

Sun=1: 01-07h 01-07h

01-1Fh 01-31h 01-0Ch 01-12h

00-63h 00-99h

Port 72 - CMOS Address .................................................. RW

7-0 CMOS Address

Port 73 - CMOS Data........................................................ RW

7-0 CMOS Data

Note: P orts 72-73 may be accessed if Rx5A bit-2 is set to

one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 72-73 will be directed to an external RTC.

Port 74 - CMOS Address .................................................. RW

7-0 CMOS Address

Port 75 - CMOS Data........................................................ RW

7-0 CMOS Data

Note: P orts 74-75 may be accessed only if Function 0 Rx5B

bit-1 is set to one to enable the internal RTC SRAM and if Rx48 bit-3 (Port 74/75 Access Enable) is set to one to enable port 74/75 access.

Note: Ports 70-71 are compatible with PC industry-

standards and may be used to access the lower 128 bytes of the 256-byte on-chip CMOS RAM. Ports 72-73 may be used to access the full extended 256byte space. Ports 74-75 may be used to access the full on-chip extended 256-byte space in cases where the on-chip RTC is disabled.

Note: The system Real Time Clock (RTC) is part of the

“CMOS” block. The RTC control registers are located at specific offsets in the CMOS data area (00Dh and 7D-7Fh). Detailed descriptions of CMOS / RTC operation and programming can be obtained from the VIA VT82887 Data Book or numerous other industry publications. For reference, the definition of the RTC register locations and bits are summarized in the following table:

(256 bytes).................................RW

(256 bytes)

(256 bytes).................................RW

(256 bytes)

0A Register A

7UIP 6-4 DV2-0 3-0 RS3-0

0B Register B

7SET

6PIE

5AIE

4UIE

3SQWE

2DM

1 24/12

0DSE

0C Register C

7IRQF

6PF

5AF

4UF 3-0 0

0D Register D

7 VRT 6-0 0

0E-7C Software-Defined Storage Registers

Offset Extended Functions

7D Date Alarm 7E Month Alarm 7F Century Field

80-FF Software-Defined Storage Registers

Update In Progress Divide (010=ena osc & keep time) Rate Select for Periodic Interrupt

Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable No function (read/write bit) Data Mode (0=BCD, 1=binary) Hours Byte Format (0=12, 1=24) Daylight Savings Enable

Interrupt Request Flag Periodic Interrupt Flag Alarm Interrupt Flag Update Ended Flag Unused (always read 0)

Reads 1 if VBAT voltage is OK Unused (always read 0)

Binary Range BCD Range

01-1Fh 01-31h

01-0Ch 01-12h

13-14h 19-20h

Table 5. CMOS Register Summary

(111 Bytes)

(128 Bytes)

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VT8231

Super-I/O Configuration Index / Data Registers

Super-I/O configuration registers are accessed by performing I/O operations to / from an index / data pair of registers in system I/O space at port addresses 3F0h and 3F1h. The configuration registers accessed using this mechanism are used to configure the Super-I/O registers (parallel port, serial ports, IR port, and floppy controller).

Super I/O configuration is accomp lished in three steps:

1) Enter configuration mode (set Function 0 Rx85[1] = 1)

2) Configure the chip a) Write index to port 3F0

b) Read / write data from / to port 3F1 c) Repeat a and b for all desired registers

3) Exit configuration mode (set Function 0 Rx85[1] = 0)

Port 3F0h – Super-I/O Configuration Index ................... RW

7-0 Index value

Function 0 PCI configuration space register Rx85[1] must be set to 1 to enable access to the Super-I/O configuration registers.

Port 3F1h – Super-I/O Configuration Data .................... RW

7-0 Data value

This register shares a port with the Floppy Status Port (which is read only). T his port is accessible only when Rx85[1] is set to 1 (the floppy status port is accessed if Rx85[1] = 0).

Super-I/O Configuration Registers

These registers are accessed via the port 3F0 / 3F1 index / data register pair using the indicated index values below

Index E0 – Super-I/O Device ID ....................................... RO

7-0 Super-I/O ID

Index E1 – Super-I/O Device Revision ............................. RO

7-0 Super-I/O Revision Code

Index E2 – Super-I/O Function Select ............................ RW

7-5 Reserved

4 Floppy Controller Enable

0 Disable...................................................default

1Enable

3 Serial Port 2 Enable

0 Disable...................................................default

1Enable

2 Serial Port 1 Enable

0 Disable...................................................default

1Enable

1-0 Parallel Port Mode / Enable

00 Unidirectional mode.............................. default

01 ECP 10 EPP 11 Parallel Port Disabled

Index E3 – Floppy Controller I/O Base Address ........... RW

7-2 I/O Address 9-4 1-0 Must be 0

........................................ default = 3Ch

.........................default = 0

........................................always reads 0

.........................................default = 0

..............................................default = 0

Index E6 – Parallel Port I/O Base Address .................... RW

7-0 I/O Address 9-2

If EPP is not enabled, the parallel port can be set to 192 locations on 4-byte boundaries from 100h to 3FCh. If EPP is enabled, the parallel port can be set to 96 locations on 8-byte boundaries from 100h to 3F8h.

Index E7 – Serial Port 1 I/O Base Address ..................... RW

7-1 I/O Address 9-3

0 Must be 0

Index E8 – Serial Port 2 I/O Base Address ..................... RW

7-1 I/O Address 9-3

0 Must be 0

.........................................default = 0

..............................................default = 0

.........................................default = 0

..............................................default = 0

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VT8231

Index EE – Serial Port Configuration ............................. RW

7 Serial Port 2 High Speed Enable

0 Disable ...................................................default

1Enable

6 Serial Port 1 High Speed Enable

0 Disable ...................................................default

1Enable

5-3 Serial Port 2 Mode

000 Standard 001 IrDA (HIPSIR) 010 Amplitude shift keyed IR @ 500KHz 011 -reserved1xx -reserved-

2 Serial Port 2 Half Duplex

0 Disable ...................................................default

1Enable

1 Serial Port 2 TX Output Inversion

0 Disable ...................................................default

1Enable

0 Serial Port 2 RX Input Inversion

0 Disable ...................................................default

1Enable

Index EF – Power Down Control ..................................... RW

7-6 Reserved

5 Clock Power Down

0 Normal operation ...................................default

1Power Down

4 Parallel Port Power Down

0 Normal operation ...................................default

1Power Down

3 Serial Port 2 Power Down

0 Normal operation ...................................default

1Power Down

2 Serial Port 1 Power Down

0 Normal operation ...................................default

1Power Down

1 FDC Power Down

0 Normal operation ...................................default

1Power Down

0 All Power Down

0 Normal operation ...................................default

1Power Down All

........................................ always reads 0

Index F0 – Parallel Port Control ..................................... RW

7 PS2 Type BiDirectionl Parallel Port

0 Disable...................................................default

1Enable

6 EPP Direction by Register not by IOW

0 Disable...................................................default

1Enable

5 EPP+ECP

0 Disable...................................................default

1Enable

4 EPP Version

0 Version 1.9 ............................................ default

1 Version 1.7

3-0 Reserved

Index F1 – Serial Port Control ........................................ RW

7-6 Reserved

5 IR Loop Back

0 Disable...................................................default

1Enable

4 Serial Port 2 Power-Down State

0 Normal...................................................default

1 Tristate output in power down mode

3 Serial Port 1 Power-Down State

0 Normal...................................................default

1 Tristate output in power down mode

2 IR Dedicated Pin (IRTX/IRRX) Select

0 IRTX / IRRX Output from Serial Port 2......def

1 Function 0 Rx76[5] = 0:

1-0 Reserved

Index F2 – Test Mode (Do Not Program) ....................... RW

Index F4 – Test Mode (Do Not Program) ....................... RW

........................................always reads 0

IRRX output from dedicated pin D12 IRTX output from dedicated pin E12

........................................always reads 0

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VT8231

Index F6 – Floppy Controller Configuration .................. RW

7-6 Reserved

5 Floppy Drive On Parallel Port

0 Parallel Port (SPP) Mode .......................default

1 FDC Mode This bit is used in notebook applications to allow attachment of an external floppy drive using the parallel port I/O connector:

SPP Mode Pin Type STROBE# I/O - n/a

PD0 I/O INDEX# I PD1 I/O TRK00# I PD2 I/O WRTPRT# I PD3 I/O RDATA# I PD4 I/O DSKCHG# I PD5 I/O - n/a PD6 I/O - n/a PD7 I/O - n/a

ACK# I DS1# O BUSY I MTR1# O PE I WDATA# O SLCT I WGATE# O AUTOFD# I/O DRVEN0 O ERROR# I HDSEL# O PINIT# I/O DIR# O SLCTIN# I/O STEP# O

........................................ always reads 0

FDC Mode Pin Type

Index F8 – Floppy Drive Control .................................... RW

7-6 Floppy Drive 3 5-4 Floppy Drive 2 3-2 Floppy Drive 1 1-0 Floppy Drive 0

00 DRATE0 DENSEL 01 DRATE0 DRATE1 10 DRATE0 DENSEL# 11 DRATE1 DRATE0

(see table below)

(see table below) (see table below) (see table below)

DRVEN1 DRVEN0

43-Mode FDD

0 Disable ...................................................default

1Enable

3 Reserved 2 Four Floppy Drive Option

0 Internal 2-Drive Decoder .......................default

1 External 4-Drive Decoder

1 FDC DMA Non-Burst

0 Burst .....................................................default

1Non-Burst

0 FDC Swap

0 Disable ...................................................default

1Enable

........................................ always reads 0

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Super-I/O I/O Ports

Floppy Disk Controller Registers

These registers are located at I/O ports which are offsets from “FDCBase” (index C3h of the Super-I/O configuration registers). FDCBase is typically set to allow these ports to be accessed at the standard floppy disk controller address range of 3F0-3F7h.

VT8231

Port FDCBase+2 – FDC Command ................................. RW

7 Motor 3 (unused in VT8231: no MTR3# pin) 6 Motor 2 (unused in VT8231: no MTR2# pin) 5 Motor 1

0 Motor Off 1 Motor On

4 Motor 0

0 Motor Off 1 Motor On

3 DMA and IRQ Channels

0 Disabled 1Enabled

2 FDC Reset

0 Execute FDC Reset 1FDC Enabled

1-0 Drive Select

00 Select Drive 0 01 Select Drive 1 1x -reserved-

Port FDCBase+4 – FDC Main Status ............................... RO

7 Main Request

0 Data register not ready 1 Data register ready

6 Data Input / Output

0 CPU => FDC 1 FDC => CPU

5 Non-DMA Mode

0 FDC in DMA mode 1 FDC not in DMA mode

4 FDC Busy

0 FDC inactive 1 FDC active

3-2 Reserved

1 Drive 1 Active

0 Drive inactive 1 Drive performing a positioning change

0 Drive 0 Active

0 Drive inactive 1 Drive performing a positioning change

........................................ always reads 0

Port FDCBase+4 – FDC Data Rate Select ...................... WO

Port FDCBase+5 – FDC Data .......................................... RW

Port FDCBase+7 – FDC Disk Change Status .................. RO

7 Disk Change

0 Floppy not changed 1 Floppy changed since last instruction

6-3 Undefined 2-1 Data Rate

00 500 Kbit/sec (1.2MB 5” or 1.44 MB 3” drive) 01 300 Kbit/sec (360KB 5” drive) 10 250 Kbit/sec (720KB 3” drive) 11 1 Mbit/sec

0 High Density Rate

0 500 Kbit/sec or 1 Mbit/sec selected 1 250 Kbit/set or 300 Kbit/sec selected

Port FDCBase+7 – FDC Configuration Control ............ WO

7-2 Undefined 1-0 Data Rate

00 500 Kbit/sec (1.2MB 5” or 1.44 MB 3” drive) 01 300 Kbit/sec (360KB 5” drive) 10 250 Kbit/sec (720KB 3” drive) 11 1 Mbit/sec

......................................... always read 1

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Parallel Port Registers

These registers are located at I/O ports which are offsets from “LPTBase” (index C6h of the Super-I/O configuration registers). LPTBase is typically set to allow these ports to be accessed at the standard parallel port address range of 37837Fh.

VT8231

Port LPTBase+0 – Parallel Port Data ............................. RW

7-0 Parallel Port Data

Port LPTBase+1 – Parallel Port Status ............................ RO

7 BUSY#

0 Printer busy, offline, or error 1 Printer not busy

6 ACK#

0 Data transfer to printer complete 1 Data transfer to printer in progress

5PE

0 Paper available 1 No paper available

4SLCT

0 Printer offline 1 Printer online

3 ERROR#

0 Printer error 1Printer OK

2-0 Reserved

Port LPTBase+2 – Parallel Port Control ........................ RW

7-5 Undefined

4 Hardware Interrupt

0 Disable ...................................................default

1Enable

3 Printer Select

0 Deselect printer ......................................default

1 Select printer

2 Printer Initialize

0 Initialize Printer......................................default

1 Allow printer to operate normally

1 Automatic Line Feed

0 Host handles line feeds...........................default

1 Printer does automatic line feeds

0Strobe

0 No data transfer......................................default

1 Transfer data to printer

...................................always read 1 bits

................................. always read back 1

Port LPTBase+3 – Parallel Port EPP Address............... RW

Port LPTBase+4 – Parallel Port EPP Data Port 0 ......... RW

Port LPTBase+5 – Parallel Port EPP Data Port 1 ......... RW

Port LPTBase+6 – Parallel Port EPP Data Port 2 ......... RW

Port LPTBase+7 – Parallel Port EPP Data Port 3 ......... RW

Port LPTBase+400h – Parallel Port ECP Data / Cfg A RW

Port LPTBase+401h – Parallel Port ECP Config B ....... RW

Port LPTBase+401h – Parallel Port ECP Extd Ctrl ...... RW

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Serial Port 1 Registers

These registers are located at I/O ports which are offsets from “COM1Base” (index C7h of the Super-I/O configuration registers). COM1Base is typically set to allow these ports to be accessed at the standard serial port 1 address range of 3F83FFh.

Port COM1Base+0 – Transmit / Receive Buffer ............ RW

7-0 Serial Data

Port COM1Base+1 – Interrupt Enable ........................... RW

7-4 Undefined

3 Interrupt on Hnadshake Input State Change 2 Intr on Parity, Overrun, Framing Error or Break 1 Interrupt on Transmit Buffer Empty 0 Interrupt on Receive Data Ready

Port COM1Base+2 – Interrupt Status ............................. RO

7-3 Undefined 2-1 Interrupt ID

00 Priority 3 (Handshake Input Changed State) 01 Priority 2 (Transmit Buffer Empty) 10 Priority 1 (Data Received) 11 Priority 0 (Serialization Error or Break)

0 Interrupt Pending

0 Inter rupt Pending 1 No Interrupt Pending

Port COM1Base+2 – FIFO Control ............................... WO

Port COM1Base+3 – UART Control ............................... RW

7 Divisor Latch Access

0 Select transmit / receive registers 1 Select divisor latch

6 Break

0 Break condition off 1 Break condition on

5-3 Parity

000 None 001 Odd 011 Even 101 Mark 111 Space

2 Stop Bits

01 12

1-0 Data Bits

00 5 01 6 10 7 11 8

..........................................always read 0

(0=highest priority)

Port COM1Base+4 – Handshake Control ...................... RW

7-5 Undefined

4 Loopback Check

0 Normal operation 1 Loopback enabled

3 General Purpose Output 2 (unused in VT8231) 2 General Purpose Output 1 (unused in VT8231) 1 Request To Send

0 Disabled 1Enabled

0 Data Terminal Ready

0 Disabled 1Enabled

Port COM1Base+5 – UART Status ................................. RW

7 Undefined 6 Transmitter Empty

0 1 byte in transmit hold or transmit shift register 1 0 bytes transmit hold and transmit shift regs

5 Transmit Buffer Empty

0 1 byte in transmit hold register 1 Tra nsmit hold register empty

4 Break Detected

0 No break detected 1 Break detected

3 Framing Error Detected

0 No error 1 Error

2 Parity Error Detected

0 No error 1 Error

1 Overrun Error Detected

0 No error 1 Error

0 Received Data Ready

0 No received data available 1 Received data in receiver buffer register

Port COM1Base+6 – Handshake Status ......................... RW

7 DCD Status (1=Active, 0=Inactive) 6 RI Status (1=Active, 0=Inactive) 5 DSR Status (1=Active, 0=Inactive) 4 CTS Status (1=Active, 0=Inactive) 3 DCD Changed (1=Changed Since Last Read) 2 RI Changed (1=Changed Since Last Read) 1 DSR Changed (1=Changed Since Last Read) 0 CTS Changed (1=Changed Since La st Read)

Port COM1Base+7 – Scratchpad .................................... RW

7 Scratchpad Data

Port COM1Base+9-8 – Baud Rate Generator Divisor .. RW

15-0 Divisor Value for Basud Rate Generator

Baud Rate = 115,200 / Divisor (e.g., setting this register to 1 selects 115.2 Kbaud)

......................................... always read 0

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Serial Port 2 Registers

These registers are located at I/O ports which are offsets from “COM2Base” (index C8h of the Super-I/O configuration registers). COM2Base is typically set to allow these ports to be accessed at the standard serial port 2 address range of 2F82FFh.

Port COM1Base+0 – Transmit / Receive Buffer ............ RW

7-0 Serial Data

Port COM1Base+1 – Interrupt Enable ........................... RW

7-4 Undefined

3 Interrupt on Hnadshake Input State Change 2 Intr on Parity, Overrun, Framing Error or Break 1 Interrupt on Transmit Buffer Empty 0 Interrupt on Receive Data Ready

Port COM1Base+2 – Interrupt Status ............................. RO

7-3 Undefined 2-1 Interrupt ID

00 Priority 3 (Handshake Input Changed State) 01 Priority 2 (Transmit Buffer Empty) 10 Priority 1 (Data Received) 11 Priority 0 (Serialization Error or Break)

0 Interrupt Pending

0 Inter rupt Pending 1 No Interrupt Pending

Port COM1Base+2 – FIFO Control ............................... WO

Port COM1Base+3 – UART Control ............................... RW

7 Divisor Latch Access

0 Select transmit / receive registers 1 Select divisor latch

6 Break

0 Break condition off 1 Break condition on

5-3 Parity

000 None 001 Odd 011 Even 101 Mark 111 Space

2 Stop Bits

01 12

1-0 Data Bits

00 5 01 6 10 7 11 8

..........................................always read 0

(0=highest priority)

Port COM1Base+4 – Handshake Control ...................... RW

7-5 Undefined

4 Loopback Check

0 Normal operation 1 Loopback enabled

3 General Purpose Output 2 (unused in VT8231) 2 General Purpose Output 1 (unused in VT8231) 1 Request To Send

0 Disabled 1Enabled

0 Data Terminal Ready

0 Disabled 1Enabled

Port COM1Base+5 – UART Status ................................. RW

7 Undefined 6 Transmitter Empty

0 1 byte in transmit hold or transmit shift register 1 0 bytes transmit hold and transmit shift regs

5 Transmit Buffer Empty

0 1 byte in transmit hold register 1 Tra nsmit hold register empty

4 Break Detected

0 No break detected 1 Break detected

3 Framing Error Detected

0 No error 1 Error

2 Parity Error Detected

0 No error 1 Error

1 Overrun Error Detected

0 No error 1 Error

0 Received Data Ready

0 No received data available 1 Received data in receiver buffer register

Port COM1Base+6 – Handshake Status ......................... RW

Port COM1Base+7 – Scratchpad .................................... RW

7 Scratchpad Data

Port COM1Base+9-8 – Baud Rate Generator Divisor .. RW

15-0 Divisor Value for Basud Rate Generator

Baud Rate = 115,200 / Divisor (e.g., setting this register to 1 selects 115.2 Kbaud)

......................................... always read 0

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SoundBlaster Pro Port Registers

These registers are located at offsets fr om “SBPBase” (defined in Rx43 of Audio Function 5 PCI configuration space). SBPBase is typically set to allow these ports to be accessed at the standard SoundBlaster Pro port address of 220h or 240h.

FM Registers

Port SBPBase+0 – FM Left Channel Index / Status ....... RW

7-0 FM Right Channel Index / Status

Port SBPBase+1 – FM Left Channel Data ..................... WO

7-0 Right Channel FM Data

Port SBPBase+2 – FM Right Channel Index / Status .... RW

7-0 FM Right Channel Index / Status

Port SBPBase+3 – FM Right Channel Data .................. WO

7-0 Right Channel FM Data

Port 388h or SBPBase+8 – FM Index / Status ................ RW

7-0 FM Index / Status (Bot h Channels)

Writing to this port programs both the left and right channels (the write programms port offsets 0 and 2 as well)

Port 389h or SBPBase+9 – FM Data .............................. WO

7-0 FM Data (Both Channels)

Writing to this port programs both the left and right channels (the write programms port offsets 1 and 3 as well)

Mixer Registers

Port SBPBase+4 – Mixer Index....................................... WO

7-0 Mixer Index

Port SBPBase+5 – Mixer Data ......................................... RW

7-0 Mixer Data

Sound Processor Registers

Index Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

01 Test 02 Fast Counter (80 usec) 03 Slow Counter (320 usec) 04 IRQ MFC MSC SSSC SSFC

08 CSM SEL 20-35 AM VIB EGT KSR Multi 40-55 KSL Total Level (TL) 60-75 Attack Rate (AR) Decay Rate (DR) 80-95 Sustain Level (SL) Release Rate (RR)

A0-A8 F-Number B0-B8 Key Block F-Number

BD Int AM VIB Ryth Bass Snare Tom Cym HiHat

C0-C8 Feedback FM

E0-F5 WS MFC=Mask Fast Counter SSFC=Start / Stop Fast Counter MSC=Mask Slow Counter SSSC=Start / Stop Slow Counter

Index Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

00 Data Reset

02 SP Volume L SP Volume R 0A Mic Vol 0C Finp TFIL Select 0E Fout ST

22 General Volume General Volume

26 FM Volume L FM Volume R

28 CD Volume L CD Volume R 2E Line Volume L Line Volume R

Finp = Input Filter Fout = Output Filter TFIL = Input Filter Type ST = Stereo / Mono Mode Select = Input Choices (0=Microphone, 1=CD, 3=Line)

Command Summary – Sound Processor (see next page)

Port SBPBase+6 – Sound Processor Reset ..................... WO

0 1 = Sound Processor Reset

Port SBPBase+A – Sound Processor Read Data ............. RO

7-0 Sound Processor Read Data

Port SBPBase+C – Sound Processor Command / Data WO

7-0 Sound Processor Command / Write Data

Port SBPBase+C – Sound Processor Buffer Status ......... RO

7 1 = Sound Processor Command / Data Port Busy

Port SBPBase+E – Sound Processor Data Avail Status .. RO

7 1 = Sound Processor Data Available

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Command Summary – Sound Processor #TypeCommand

10 Play 8 bits directly 14 Play 8 bits via DMA 91 Play High-speed 8 bits via DMA 16 Play 2-bit compressed via DMA 17 Play 2-bit compressed via DMA with reference 74 Play 4-bit compressed via DMA 75 Play 4-bit compressed via DMA with reference 76 Play 2.6-bit compressed via DMA 77 Play 2.6-bit compressed via DMA with reference

20 Record Direct 24 Record Via DMA 99 Record High-speed 8 bits via DMA

D1 Speaker Turn on speaker connection D3 Speaker Turn off speaker connection D8 Speaker Get speaker setting

40 Misc Set sample rate 48 Misc Set block length 80 Misc Set silence block D0 Misc Stop DMA D4 Misc Continue DMA E1 Misc Get version

Game Port Registers

These registers are fixed at the standard game port address of 201h.

I/O Port 201h – Game Port Status ................................... RO

7 Joystick B Button 2 Status 6 Joystick B Button 1 Status 5 Joystick A Button 2 Status 4 Joystick A Button 1 Status 3 Joystick B One-Shot Status for Y-Potentiometer 2 Joystick B One-Shot Status for X-Potentiometer 1 Joystick A One-Shot Status for Y-Potentiometer 0 Joystick A One-Shot Status for X-Potentiometer

I/O Port 201h – Start One-Shot ....................................... WO

(Value Written is Ignored)

7-0

30 MIDI Direct MIDI input 31 MIDI MIDI input via interrupt 32 MIDI Direct MIDI input with time stamp 33 MIDI MIDI input via interrupt with time stamp 34 MIDI Direct MIDI UART mode 35 MIDI MIDI UART mode via interrupt 36 MIDI Direct MIDI UART mode with time stamp 37 MIDI MIDI UART mode via interrupt with time stamp 38 MIDI Send MIDI code

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PCI Configuration Space I/O

PCI configuration space accesses for functions 0-6 use PCI configuration mechanism 1 (see PCI specification revision 2.2 for more details). The ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged.

Port CFB-CF8 - Configuration Address ......................... RW

31 Co nfiguration Space Enable

0 Disabled .................................................default

1 Convert configuration data port writes to

configuration cycles on the PCI bus

30-24 Reserved 23-16 PCI Bus Number

Used to choose a specific PCI bus in the system

15-11 Device Number

Used to choose a specific device in the system

10-8 Function Number

Used to choose a specific function if the selected device supports multiple functions

7-2 Register Number

Used to select a specific DWORD in the device’s configuration space

1-0 Fixed

........................................ always reads 0

VT8231

There are 7 “functions” implemented in the VT 8231:

Function # Function

0 PCI to ISA Bridge 1 IDE Controller 2 USB Controller Ports 0-1 3 USB Controller Ports 2-3 4 Power Management, SMBus & Hardware

Monitor 5 AC97 Audio Codec Controller 6 MC97 Modem Codec Controller

The following sections describe the registers and register bits of these functions.

Port CFF-CFC - Configuration Data .............................. RW

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Function 0 Registers - PCI to ISA Bridge

All registers are located in the function 0 PCI configuration space of the VT8231. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC.

PCI Configuration Space Header

Offset 1-0 - Vendor ID = 1106h ......................................... RO

Offset 3-2 - Device ID = 8231h .......................................... RO

Offset 5-4 - Command ....................................................... RW

15-8 Reserved

7 Address / Data Stepping

0 Disable

1 Enable ....................................................default

6-4 Reserved

3 Special Cycle Enable 2Bus Master 1 Memory Space 0 I/O Space

† If the test bit at offset 46 bit-4 is set, access to the above indicated bits is reversed: bit-3 above becomes read only (reading back 1) and bits 0-1 above become read / write (with a default of 1).

Offset 7-6 - Status ........................................................... RWC

15 Detected Parity Error 14 Sig nalled System Error 13 Signalled Master Abort 12 Received Target Abort 11 Signalled Target Abort

10-9 DEV SEL# Timing

8 Data Parity Detected 7 Fast Back-to-Back

6-0 Reserved

Offset 8 - Revision ID = nn ................................................ RO

7-0 Revision ID

Offset 9 - Program Interface = 00h ................................... RO

Offset A - Sub Class Code = 01h ....................................... RO

Offset B - Class Code = 06h ............................................... RO

........................................ always reads 0

..... Normally RW†, default = 0

........................................ always reads 1

.................. Normally RO†, reads as 1

...................... Normally RO†, reads as 1

....................write one to clear

...................... always reads 0

.................write one to clear

..................write one to clear

....................fixed at 01 (medium)

.......................... always reads 0

.............................. always reads 0

........................................ always reads 0

ISA Bus Control

Offset 40 - ISA Bus Control ............................................. RW

7 ISA Command Delay

0 Normal...................................................default

1Extra

6 Extended ISA Bus Ready

0 Disable...................................................default

1Enable

5 ISA Slave Wait States

0 4 Wait States..........................................default

1 5 Wait States

4 Chipset I/O Wait States

0 2 Wait States..........................................default

1 4 Wait States

3 I/O Recovery Time

0 Disable...................................................default

1Enable

2 Extend-ALE

0 Disable...................................................default

1Enable

1ROM Wait States

0 1 Wait State ........................................... default

1 0 Wait States

0ROM Write

0 Disable...................................................default

1Enable

Offset 41 - ISA Test Mode ................................................ RW

7 Bus Refresh Arbitration 6 XRDY Test Mode 5 Port 92 Fast Reset

0 Disable...................................................default

1Enable

4 A20G Emulation 3 Double DMA Clock

0 Disable (DMA Clock = ½ ISA Clock)...default 1 Enable (DMA Clock = ISA Clock)

2 SHOLD Lock During INTA 1 Refresh Request Test Mode 0 ISA Refresh

0 Disable...................................................default

1Enable

This bit should be set to 1 for ISA compatibility.

(do not program)............. default=0

(do not program) default=0

(do not program)...........default=0

(do not program) def=0

(do not program).def=0

Offset E - Header Type = 80h ............................................ RO

7-0 Header Type Code .........

Offset F - BIST = 00h ......................................................... RO

Offset 2F-2C - Subsystem ID ............................................. RO

Use offset 70-73 to change the value returned.

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80h (Multifunction Device)

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Offset 42 - ISA Clock Control. ......................................... RW

7 Latch IO16#

0 Enable (recommended setting)...............default

1 Disable

6 MCS16# Output

0 Disable ...................................................default

1Enable

5 Master Request Test Mode

0 Disable ...................................................default

1Enable

4 Reserved (Do Not Program) 3 ISA Clock (BCLK) Select Enable

0 BCLK = PCICLK/4................................default

1 BCLK selected per bits 2-0

2-0 ISA Bus Clock Select

000 BCLK = PCICLK/3................................default

001 BCLK = PCIC LK/2 010 BCLK = PCIC LK/4 011 BCLK = PCIC LK/6 100 BCLK = PCIC LK/5 101 BCLK = PCIC LK/10 110 BCLK = PCIC LK/12 111 BCLK = OSC

Note: Procedure for ISA Clock switching:

1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1

(do not program)

................... default = 0

(if bit-3 = 1)

Offset 43 - ROM Decode Control .................................... RW

Setting these bits enables the indicated address range to be included in the ROMCS# decode:

7 FFFE0000h-FFFEFFFFh 6 FFF80000h-FFFDFFFFh 5 FFF00000h-FFF7FFFFh 4 000E0000h-000EFFFFh 3 000D8000h-000DFFFFh 2 000D0000h-000D7FFFh 1 000C8000h-000CFFFFh 0 000C0000h-000C7FFFh

Offset 44 - Keyboard Controller Control ....................... RW

7 KBC Timeout Test

6-4 Reserved

3 Mouse Lo c k Enable

2-1 Reserved

0 Reserved

Offset 45 - Type F DMA Control .................................... RW

7 ISA Master / DMA to PCI Line Buffer

6 DMA type F Timing on Channel 7 5 DMA type F Timing on Channel 6 4 DMA type F Timing on Channel 5 3 DMA type F Timing on Channel 3 2 DMA type F Timing on Channel 2 1 DMA type F Timing on Channel 1 0 DMA type F Timing on Channel 0

(do not program)........................ default = 0

0 Disable...................................................default

1Enable

(do not program)........................ default = 0

(no function)..............................default = 0

0 Disable...................................................default

1Enable

(do not program)........default = 0

..........................default=0

.......................... default=0

............................default=0

.............................default=0

............................default=0

............................ default=0

............................default=0

.............................default=0

............default=0

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Offset 46 - Miscellaneous Control 1 ................................. RW

7 PCI Master Write Wait States

0 0 Wait States ..........................................default

1 1 Wait State

6Gate INTR

0 Disable ...................................................default

1Enable

5 Flush Line Buffer for Int or DMA IOR Cycle

0 Disable ...................................................default

1Enable

4 Config Command Reg Rx04 Access (Test Only)

0 Normal: Bits 0-1=RO, Bit 3=RW..........default

1 Test Mode: B its 0-1=RW, Bit-3=RO

3 Reserved 2 Reserved 1 PCI Burst Read Interruptability

0 Posted Memory Write Enable

The Posted Memory Write function is automatically enabled when Delay T ransaction (see Rx47 bit-6) is enabled, independent of the state of this bit.

(do not program)........................default = 0

(no function).............................. default = 0

0 Allow burst reads to be interrupted by ISA

master or DMA.......................................default

1Don’t allow PCI burst reads to be interrupted

0 Disable ...................................................default

1Enable

Offset 47 - Miscellaneous Control 2 ................................ RW

7 CPU Reset Source

0 Use CPURST as CPU Reset.................. default

1 Use INIT as CPU Reset

6 PCI Delay Transaction Enable

0 Disable...................................................default

1Enable The "Posted Memory Write" function is automatically enabled when this bit is enabled, independent of the state of Rx46 bit-0.

5 EISA 4D0/4D1 Port Enable

0 Disable (ignore ports 4D0-1).................default

1 Enable (ports 4D0-1 per EISA specification)

4 Interrupt Controller Shadow Register Enable

0 Disable...................................................default

1 Enable (for test purposes, enable readback of

interrupt controller internal functions on I/O reads from ports 20-21, A0-A1, A8-A9, and C8-C9) (Contact VIA Test Engineering department)

3 Reserved (always program to 0)

Note: Always mask this bit. This bit may read back

as either 0 or 1 but must always be programmed with 0.

2 Write Delay Tr ansaction Time-Out Timer

0 Disable...................................................default

1Enable

1 Read Delay Transaction Time-Out Timer

0 Disable...................................................default

1Enable

0 Softwar e PCI Reset

......write 1 to generate PCI reset

..............default = 0

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Offset 48 - Miscellaneous Control 3 ................................. RW

7-4 Reserved

3 Extra RTC Port 74/75 Enable

0 Disable ...................................................default

1Enable

2 Integrated USB Controller Disable

0 Enable.....................................................default

1 Disable

1 Integrated IDE Controller Disable

0 Enable.....................................................default

1 Disable

0 512K PCI Memory Decode

0 Use Rx4E[15-12] to select top of PCI memory 1 Use contents of Rx4E[15-12] plus 512K as top

Offset 4A - IDE Interrupt Routing .................................. RW

7 Wait for PGNT Before Grant to ISA Master /

DMA

0 Disable ...................................................default

1Enable

6 Bus Select for Access to I/O Devices Below 100h

0 Access ports 00-FFh via XD bus............default

1 Access ports 00-FFh via SD bus (applies to

5-4 Reserved (do not program) 3-2 IDE Second Channel IRQ Routing

00 IRQ14

01 IRQ15.....................................................default

10 IRQ10 11 IRQ11

1-0 IDE Primary Channel IRQ Routing

00 IRQ14.....................................................default

01 IRQ15 10 IRQ10 11 IRQ11

........................................ always reads 0

of PCI memory....................................... default

external devices only; internal devices such as the mouse controller are not effected)

..................... default = 0

4C - ISA DMA/Master Memory Access Control 1 ........ RW

7-0 PCI Memory Hole Bottom Address

These bits correspond to HA[23:16]............default=0

4D - ISA DMA/Master Memory Access Control 2 ........ RW

7-0 PCI Memory Hole Top Address

These bits correspond to HA[23:16]............default=0

Note: Access to the memory defined in the PCI memory

hole will not be forwarded to PCI. This function is disabled if the top address is less than or equal to the bottom address.

4F-4E - ISA DMA/Master M emory Access Control 3 ... RW

15-12 Top of PCI Memory

0000 1M ....................................................default

0001 2M

... ...

1111 16M

Note: All ISA DMA / Masters that access addresses higher

than the top of PCI memory will not be directed to the PCI bus.

11 Forward E0000-EFFFF Accesses to PCI 10 Forward A0000-BFFFF Accesses to PCI

9 Forward 80000-9FFFF Accesses to PCI 8 Forward 00000-7FFFF Accesses to PCI 7 Forward DC000-DFFFF Accesses to PCI 6 Forward D8000-DBFFF Accesses to PCI 5 Forward D4000-D7FFF Accesses to PCI 4 Forward D0000-D3FFF Accesses to PCI 3 Forward CC000-CFFFF Accesses to PCI 2 Forward C8000-CBFFF Accesses to PCI 1 Forward C4000-C7FFF Accesses to PCI 0 Forward C0000-C3FFF Accesses to PCI

for ISA DMA/Master accesses

(HA[23:16])

........def=0

.......def=0

........ def=1

......def=0

...... def=0

....... def=0

.....def=0

...... def=0

....... def=0

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Plug and Play Control

VT8231

Offset 50 – PNP DMA Request Control .......................... RW

7-4 Reserved 3-2 PnP Routing for Parallel Port DRQ 1-0 PnP Routing for Floppy DRQ

DRQ Mapping: 00=DRQ0, 01=DRQ1, 10=DRQ2, 11=DRQ3

Offset 51 - PNP IRQ Routing 1 ........................................ RW

7-4 PnP Routing for Parallel Port IRQ

routing table)

3-0 PnP Routing for Floppy IRQ

table)

Offset 52 - PNP IRQ Routing 2 ........................................ RW

7-4 PnP Routing for Serial Port 2 IRQ

routing table)

3-0 PnP Routing for Serial Port 1 IRQ

routing table)

Offset 54 - PCI IRQ Edge / Level Select .......................... RW

7-4 Reserved

The following bits all default to “level” triggered (0)

3 PIRQA# Invert (edge) / Non-invert (level) 2 PIRQB# Invert (edge) / Non-invert (level) 1 PIRQC# Invert (edge) / Non-invert (level) 0 PIRQD# Invert (edge) / Non-invert (level)

Note: PIRQA-D# normally connect to PCI interrupt pins

INTA-D# (see pin definitions for more information).

.............................................. default = 0

.....def = DRQ3

...............def = DRQ2

(see PnP IRQ

(see PnP IRQ routing

(see PnP IRQ

........................................ always reads 0

.......(1/0)

PnP IRQ Routing Table

0000 Disabled................................................. default

0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 1111 IRQ15

Offset 55 - PNP IRQ Routing 4 ........................................ RW

7-4 PIRQA# Routing 3-0 Reserved

Offset 56 - PNP IRQ Routing 5 ........................................ RW

7-4 PIRQC# Routing 3-0 PIRQB# Routing

Offset 57 - PNP IRQ Routing 6 ........................................ RW

7-4 PIRQD# Routing 3-0 Reserved

(see PnP IRQ routing table)

........................................ always reads 0

(see PnP IRQ routing table) (see PnP IRQ routing table)

(see PnP IRQ routing table)

........................................ always reads 0

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Offset 59 – PCS0# Control ............................................... RW

7-4 Reserved

........................................ always reads 0

3 PCS0# Pin Function (Pin T5)

0 Pin is defined as PCS0# ........................default

1 Pin is defined as Internal Trap I/O

2-0 Reserved

........................................ always reads 0

Offset 5A – KBC / RTC Control ...................................... RW

Bits 7-4 of this register are latched from pins SD7-4 at powerup but are read/write accessible so may be changed after power-up to change the default strap setting:

7 Keyboard RP16 6 Keyboard RP15 5 Keyboard RP14 4 Keyboard RP13

............................. latched from SD7

............................ latched from SD6

............................ latched from SD5

............................ latched from SD4

3 Audio Function Enable

....... RO, strapped from SPKR pin V5

0 Disable (SDD pins function as SDD) 1 Enabl e (SDD pins function as Audi o / Game)

2 Internal RTC Enable

0 Disable

1 Enable ....................................................default

1 Internal PS2 Mouse Enable

0 Disable ..................................................default

1Enable

0 Internal KBC Enable

0 Disable ..................................................default

1Enable

Note: External strap option values may be set by connecting

the indicated external pin to a 4.7K ohm pullup (for

1) or driving it low during reset with a 7407 TTL open collector buffer (for 0) as shown in the suggested circuit below:

9&&



5(6(7

9&&

.

6'Q

Offset 5B - Internal RTC Test Mode .............................. RW

7-4 Reserved

........................................always reads 0

3 Map RTC Rx32 to Rx3F

0 Disable...................................................default

1Enable

2 RTC Reset Enable

(do not program)

0 Disable...................................................default

1Enable

1 RTC SRAM Access Enable

0 Disable...................................................default

1Enable

This bit is set if the internal RTC is disabled but it is desired to still be able to access the internal RTC SRAM via ports 74-75. If the internal RTC is enabled, setting this bit does nothing (the internal RTC SRAM should be accessed at either ports 70/71 or 72/73.

0 RTC Test Mode Enable

(do not program).default=0

Offset 5C - DMA Control ................................................. RW

7 PCS0# & PCS1# 16-Bit I/O

0 Disable...................................................default

1Enable

6 Passive Release

0 Disable...................................................default

1Enable

5 Internal Passive Release

0 Disable...................................................default

1Enable

4 Dummy PREQ

0 Disable...................................................default

1Enable

3 Reserved

........................................always reads 0

2 APIC Connection

0 APIC on SD Bus.................................... default

1 APIC on XD Bus

1 Reserved (Do Not Program)

....................default = 0

0 DMA Line Buffer Disable

0 DMA cycles can be to/from line buffer .......def

1 Disable DMA Line Buffer

Figure 5. Strap Option Circuit

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Distributed DMA / Serial IRQ Control

VT8231

Offset 61-60 - Distributed DMA Ch 0 Base / Enable ...... RW

15-4 Channel 0 Base Address Bits 15-4

3 Channel 0 Enable

0 Disable ...................................................default

1Enable

2-0 Reserved

Offset 63-62 - Distributed DMA Ch 1 Base / Enable ...... RW

15-4 Channel 1 Base Address Bits 15-4

3 Channel 1 Enable

0 Disable ...................................................default

1Enable

2-0 Reserved

Offset 65-64 - Distributed DMA Ch 2 Base / Enable ...... RW

15-4 Channel 2 Base Address Bits 15-4

3 Channel 2 Enable

0 Disable ...................................................default

1Enable

2-0 Reserved

Offset 67-66 - Distributed DMA Ch 3 Base / Enable ...... RW

15-4 Channel 3 Base Address Bits 15-4

3 Channel 3 Enable

0 Disable ...................................................default

1Enable

2-0 Reserved

........................................ always reads 0

.......... default = 0

Offset 6B-6A - Distributed DMA Ch 5 Base / Enable .... RW

15-4 Channel 5 Base Address Bits 15-4

3 Channel 5 Enable

0 Disable...................................................default

1Enable

2-0 Reserved

Offset 6D-6C - Distributed DMA Ch 6 Base / Enable ... RW

15-4 Channel 6 Base Address Bits 15-4

3 Channel 6 Enable

0 Disable...................................................default

1Enable

2-0 Reserved

Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW

15-4 Channel 7 Base Address Bits 15-4

3 Channel 7 Enable

0 Disable...................................................default

1Enable

2-0 Reserved

........................................always reads 0

...........default = 0

Offset 69-68 – Serial IRQ Control ................................... RW

15-4 Reserved

3 ISA IRQ Asserted Via Serial IRQ (Pin H3 or L4)

0 Disable ...................................................default

1Enable

2 Serial IRQ Mode

0 Continuous Mode...................................default

1 Quiet Mode

1-0 Serial IRQ Start-Frame Width

00 4 PCI Clocks..........................................default

01 6 PCI Clocks 10 8 PCI Clocks 11 10 PCI Clocks

The frame size is fixed at 21 PCI clocks.

........................................ always reads 0

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Miscellaneous / General Purpose I/O

Offset 73-70 - Subsystem ID ............................................ WO

31-0 Subsystem ID / Vendor ID

Contents may be read at offset 2C.

................. always reads 0

VT8231

Offset 74 – GPIO Control 1 .............................................. RW

7APIC Enable

0 Disable (Pin U8 is GPIOD / MCCS#)....default

1 Enable (Pin U8 is SCIOUT#)

6SERIRQ Pin

0 SERIRQ input from DRQ2 (Pin H3)......default

1 SERIRQ input from DACK5# (Pin L4)

5 GPIOD Direction (Pin U8)

0 Input .....................................................default

1 Output (GPO11)

4 GPIOC Direction (Pin V14)

0 Input .....................................................default

1Output

3 GPIOB Direction (Pin U12)

0 Input .....................................................default

1Output

2 GPIOA Direction (Pin T14)

0 Input .....................................................default

1Output

1 THRM Enable (Pin T11)

0 PME# / GPI5 (see Func 4 Rx48[5]).......default

1THRM

0 GPI0 / IOCHCK# Select

0 GPI0 .....................................................default

1 IOCHCK#

Offset 75 – GPIO Control 2 ............................................. RW

7 GPO7 Enable (Pin T7)

0 Pin defined as SLP#............................... default

1 Pin defined as GPO7

6 Reserved 5 GPO5 Enable (Pin V12)

0 Pin defined as PCISTP# ........................default

1 Pin defined as GPO5

4 GPO4 Enable (Pin Y12)

0 Pin defined as CPUSTP#.......................default

1 Pin defined as GPO4

3 FDC External IRQ / DRQ Via DACK2# / DRQ2

0 Pin G5 is FDCIRQ, pin H3 is FDCDRQ..... def

1 Pin G5 is DACK2# or other alternate function

2 GPO25 Enable (Pin G5)

0 Rx75[3]=0: Pin G5 defined as DACK2#.... def

1 Pin G5 defined as GPO25

1 GPO24 Enable (Pin H3)

0 Rx75[3]=0: ............................................ default

1 Pin H3 defined as GPO24

0 Positive Decode

0 Subtractive Decode................................default

1 Positive Decode

........................................always reads 0

Pin H3 is DRQ2 or other alternate function

Rx68[3]=0: Pin H3 defined as DRQ2 Rx68[3]=1: Pin H3 defined as SERIRQ

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VT8231

Offset 76 – GPIO Control 3 .............................................. RW

7 Over-Current (OC) Input

0 Disable ...................................................default

1Enable

6 OC[3:0] From SD[3:0] By Scan

0 Disable ...................................................default

1Enable

5 GPO14 / GPO15 Enable (Pins E12 / D12)

0 Pins used for IRTX and IRRX ...............default

1 Pins used for GPO14 and GPO15

4 MCCS# Pin Select

0 MCCS# is on Pin U5..............................default

1 MCCS# is on Pin U8

3 MCCS# Function

0 Disable MCCS# function on U5/U8.......default

1 Enable MCCS# function on U5/U8

(see bit-4 for select of U5 or U8 for MCCS#)

2 CHAS Enable (Pin V14)

0 Pin is defined as GPIOC.........................default

1 Pin is defined as CHAS

1 GPO12 Enable (Pin T5)

0 Pin is defined as XDIR...........................default

1 Pin is defined as GPO12

0 GPOWE# (GPO[23-16]) Enable (Pin T14)

0 Pin is defined as GPIOA ........................default

1 Pin is defined as GPOWE# (Rx74[2] also must

be set to 1)

Offset 77 – GPIO Control 4 Control ................................ RW

7 DRQ / DACK# Pins are GPI / GPO

0 Disable ...................................................default

1Enable

6 Game Port XY Pins are GPI / GPO

0 Disable ...................................................default

1Enable

5-4 Reserved

3 SERIRQ SMI Slot

0 Disable ...................................................default

1Enable

2 RTC Rx32 Write Protect

0 Disable ...................................................default

1Enable

1 RTC Rx0D Write Protect

0 Disable ...................................................default

1Enable

0 GPO13 Enable (Pin U5)

0 Pin defined as SOE#...............................default

1 Pin defined as GPO13

........................................ always reads 0

Offset 79-78 – PCS0# I/O Port Address .......................... RW

15-0 PCS0# I/O Port Address [15-0]

Offset 7B-7A – PCS1# I/O Port Address ........................ RW

15-0 PCS1# I/O Port Address [15-0]

Offset 7D-7C – PCI DMA Channel Enable .................... RW

15-9 Reserved

8 PCI DMA Pair A

0 Disable...................................................default

1Enable

7 PCI DMA Channel 7

0 Disable...................................................default

1Enable

6 PCI DMA Channel 6

0 Disable...................................................default

1Enable

5 PCI DMA Channel 5

0 Disable...................................................default

1Enable

4 Reserved 3 PCI DMA Channel 3

0 Disable...................................................default

1Enable

2 PCI DMA Channel 2

0 Disable...................................................default

1Enable

1 PCI DMA Channel 1

0 Disable...................................................default

1Enable

0 PCI DMA Channel 0

0 Disable...................................................default

1Enable

Offset 7F-7E – 32-Bit DMA Control ............................... RW

15-3 32-Bit DMA High Page (A31-24) Registers IOBase

2-1 Reserved

0 32-Bit DMA

0 Disable...................................................default

1Enable

Offset 80 – Programmable Chip Select Mask ................ RW

7-4 PCS1# I/O Port Address Mask [3-0] 3-0 PCS0# I/O Port Address Mask [3-0]

........................................always reads 0

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Offset 81 – ISA Positive Decoding Control 1 .................. RW

7 On-Board I/O Po rt P ositive Decoding

0 Disable ...................................................default

1Enable

6 Microsoft-Sound System I/O Port Positive

Decoding

0 Disable ...................................................default

1Enable

5-4 Microsoft-Sound System I/O Decode Range

00 0530h-0537h..........................................default

01 0604h-060Bh 10 0E80-0E87h 11 0F40h-0F47h

3 APIC Positive Decoding

0 Disable ...................................................default

1Enable

2 BIOS ROM Po sitive Decoding

0 Disable ...................................................default

1Enable

1 Reserved 0 PCS0 Positive Decoding

0 Disable ...................................................default

1Enable

........................................ always reads 0

Offset 83 – ISA Positive Decoding Control 3 .................. RW

7 COM Port B Positive Decoding

0 Disable...................................................default

1Enable

6-4 COM-Port B Decode Range

000 3F8h-3FFh (COM1)............................default

001 2F8h-2FFh (COM2) 010 220h-227h 011 228h-22Fh 100 238h-23Fh 101 2E8h-2EFh (COM4) 110 338h-33Fh 111 3E8h-3EFh (COM3)

3 COM Port A Positive Decoding

0 Disable...................................................default

1Enable

2-0 COM-Port A Decode Range

000 3F8h-3FFh (COM1)............................default

001 2F8h-2FFh (COM2) 010 220h-227h 011 228h-22Fh 100 238h-23Fh 101 2E8h-2EFh (COM4) 110 338h-33Fh 111 3E8h-3EFh (COM3)

Offset 82 – ISA Positive Decoding Control 2 .................. RW

7 FDC Positive Decoding

0 Disable ...................................................default

1Enable

6 LPT Positive Decoding

0 Disable ...................................................default

1Enable

5-4 LPT Decode Range

00 3BCh-3BFh, 7BCh-7BEh.......................default

01 378h-37Fh, 778h-77Ah 10 278h-27Fh, 678h-67Ah 11 -reserved-

3 Game Port Positive Decoding

0 Disable ...................................................default

1Enable

2 MIDI Positiv e Decoding

0 Disable ...................................................default

1Enable

1-0 MIDI Decode Range

00 300h-303h..............................................default

01 310h-313h 10 320h-323h 11 330h-333h

Offset 84 – ISA Positive Decoding Control 4 .................. RW

7-4 Reserved

3 FDC Decoding Range

0 Primary..................................................default

1 Secondary

2 Sound Blaster Positive Decoding

0 Disable...................................................default

1Enable

1-0 Sound Blaster Decode Range

00 220h-22Fh, 230h-233h ..........................default

01 240h-24Fh, 250h-253h 10 260h-26Fh, 270h-273h 11 280h-28Fh, 290h-293h

........................................always reads 0

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VT8231

Offset 85 – Extended Function Enable ............................ RW

7-5 Reserved

4 Function 3 USB Ports 2-3

0 Enable.....................................................default

1 Disable

3 Function 6 Modem / Audio

0 Enable.....................................................default

1 Disable

2 Function 5 Audio

0 Enable.....................................................default

1 Disable

1 Super-I/O Configuration

0 Disable ...................................................default

1Enable

0 Super-I/O

0 Disable ...................................................default

1Enable

........................................ always reads 0

Offset 86 – PNP IRQ/DRQ Test 1 (Do Not Program) ... RW Offset 87 – PNP IRQ/DRQ Test 2 (Do Not Program) ... RW

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VT8231

Offset 88 – PLL Test ......................................................... RW

7 PCS0# Access Status 6 RTC Rx32 / Rx7F Write Protect

0 Disable ...................................................default

1Enable

5 MC IRQ Test (Do Not Program)

0 Disable ...................................................default

1Enable

4 PLL PU (Do Not Program)

0 Disable ...................................................default

1Enable

3 PLL Test Mode (Do Not Program)

0 Disable ...................................................default

1Enable

2-0 PLL Test Mode Selec t

Offset 89 – PLL Control ................................................... RW

7-4 Reserved 3-2 PLL PCLK Input Delay Select 1-0 PLL CLK66 Feedback Delay Select

........................................ always reads 0

Offset 8A – PCS2/3 I/O Port Address Mask ................... RW

7-4 PCS3# I/O Port Address Mask 3-0 3-0 PCS2# I/O Port Address Mask 3-0

Offset 8B – PCS Control .................................................. RW

7 PCS3# For Internal I/O

0 Disable...................................................default

1Enable

6 PCS2# For Internal I/O

0 Disable...................................................default

1Enable

5 PCS1# For Internal I/O

0 Disable...................................................default

1Enable

4 PCS0# For Internal I/O

0 Disable...................................................default

1Enable

3PCS3#

0 Disable...................................................default

1Enable

2PCS2#

0 Disable...................................................default

1Enable

1PCS1#

0 Disable...................................................default

1Enable

0PCS0#

0 Disable...................................................default

1Enable

Offset 8D-8C – PCS2# I/O Port Address ........................ RW

15-0 PCS2# I/O Port Address

Offset 8F-8E – PCS3# I/O Port Address ......................... RW

15-0 PCS3# I/O Port Address

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VT8231

Function 1 Registers - Enhanced IDE Controller

This Enhanced IDE controller interface is fully compatible with the SFF 8038i v.1.0 specification. There are two sets of software accessible registers -- PCI configuration registers and Bus Master IDE I/O re giste rs. T he P CI co nfigur at io n re giste rs are located in the function 1 PCI configuration space of the VT8231. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification.

PCI Configuration Space Header

Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO

Offset 3-2 - Device ID (0571h=IDE Controller) ............... RO

Offset 5-4 - Command ....................................................... RW

15-10 Reserved

9 Fast Back to Back Cycles 8 SERR# Enable 7 Address Stepping

A value of 1 provides additional address decode time to IDE devices.

6 Parity Error Response 5 VGA Palette Snoop 4 Memory Write & Invalidate 3 Special Cycles 2Bus Master

S/G operation can be issued only when the “Bus Master” bit is enabled.

1 Memory Space 0 I/O Space

When the “I/O Space” bit is disabled, the device will not respond to any I/O addresses for both compatible and native mode.

........................................ always reads 0

....... default = 0 (disabled)

......................... default = 0 (disabled)

......................

............ default = 0 (disabled)

....................fixed at 0 (disabled)

.............................fixed at 0 (disabled)

............................. default = 0 (disabled)

............................fixed at 0 (disabled)

............................. default = 0 (disabled)

fixed at 1 (enabled)

.....fixed at 0 (disabled)

Offset 9 - Programming Interface ................................... RW

7 Master IDE Capabilit y

6-4 Reserved

3 Programmable Indicator - Secondary

Supports both modes (may be set to either mode by writing bit-2)

2 Reserved 1 Programmable Indicator - Primary

Supports both modes (may be set to either mode by writing bit-0)

0 Reserved

Compatibility Mode (fixed IRQs and I/O addresses):

Command Block Control Block

Channel Registers

Pri 1F0-1F7 3F6 14

Sec 170-177 376 15

Native PCI Mode (registers are programmable in I/O space)

Command Block Control Block

Channel Registers

Pri BA @offset 10h BA @offset 14h

Sec BA @offset 18h BA @offset 1Ch

Command register blocks are 8 bytes of I/O space Control registers are 4 bytes of I/O space (only byte 2 is used)

Offset A - Sub Class Code (01h=IDE Controller) ........... RO

Offset B - Base Class Code (01h=Mass Storage Ctrlr) ... RO

Offset C – Cache Line Size (00h) ...................................... RO

Offset D - Latency Timer (Default=0) ............................. RW

Offset E - Header Type (00h) ............................................ RO

........................................always reads 0

...........fixed at 1 (Supported)

......fixed at 1

..........fixed at 1

Registers IRQ

Registers

Offset 7-6 - Status ............................................................... RO

15 Detected Parity Error 14 Sig nalled System Error 13 Received Master Abort 12 Received Target Abort 11 Signalled Target Abort

10-9 DEV SEL# Timing

8 Data Parity Detected 7 Fast Back to Back

6-0 Reserved

Offset 8 - Revision ID (06) ................................................. RO

0-7 Revision Code for IDE Controller Logic Block

Preliminary Revision 0.8 October 29, 1999 -69- Function 1 Registers - Enhanced IDE Control ler

........................................ always reads 0

.................................fixed at 0

...............................fixed at 0

..................default = 01 (medium)

...................................fixed at 0

.......................................fixed at 1

Offset F - BIST (00h) ......................................................... RO

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VT8231

Offset 13-10 - Pri Data / Command Base Address.......... RW

pecifies an 8 byte I/O address space.

31-16 Reserved

15-3 Port Address

2-0 Fixed at 001b

Offset 17-14 - Pri Control / Status Base Address............ RW

Specifies a 4 byte I/O address space of which only the third byte is active (i.e., 3F6h for the default base address of 3F4h).

31-16 Reserved

15-2 Port Address

1-0 Fixed at 01b

Offset 1B-18 - Sec Data / Command Base Address ........ RW

pecifies an 8 byte I/O address space.

31-16 Reserved

15-3 Port Address

2-0 Fixed at 001b

Offset 1F-1C - Sec Control / Status Base Address .......... RW

Specifies a 4 byte I/O address space of which only the third byte is active (i.e., 376h for the default base address of 374h).

31-16 Reserved

15-2 Port Address

1-0 Fixed at 01b

..........................................always read 0

.......................................default=01F0h

..................................................... fixed

..........................................always read 0

.......................................default=03F4h

....................................................... fixed

..........................................always read 0

...................................... default=0170h

..................................................... fixed

..........................................always read 0

...................................... default=0374h

....................................................... fixed

Offset 34 - Capability Pointer (C0h) ................................ RO

Offset 3C - Interrupt Line (0Eh) ...................................... RO

Offset 3D - Interrupt Pin (00h) ......................................... RO

7-0 Interrupt Routing Mode

00h Legacy mode interrupt routing...............default

01h Native mode interrupt routing

Offset 3E - Min Gnt (00h) ................................................. RO

Offset 3F - Max Latency (00h).......................................... RO

Offset 23-20 - Bus Master Control Regs Base Address .. RW

Specifies a 16 byte I/O address space compliant with the

8038i rev 1.0

31-16 Reserved

15-4 Port Address

3-0 Fixed at 0001b

specification.

..........................................always read 0

....................................... default=CC0h

.................................................. fixed

SFF-

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IDE-Controller-Specific Confiiguration Registers

VT8231

Offset 40 - Chip Enable ..................................................... RW

7-4 Reserved 3-2 Reserved (Do Not Program)

1 Primary Channel Enable 0 Secondary Channel Enable

Offset 41 - IDE Configuration .......................................... RW

7 Primary IDE Read Prefetch Buffer

0 Disable ...................................................default

1Enable

6 Primary IDE Post Write Buffer

0 Disable ...................................................default

1Enable

5 Secondary IDE Read Prefetch Buffer

0 Disable ...................................................default

1Enable

4 Secondary IDE Post Write Buffer

0 Disable ...................................................default

1Enable

3 Reserved

2 Reserved (Do Not Change) 1 Reserved (Do Not Change)

........................................ always reads 0

...........R/W, default = 0

........ default = 0 (disabled)

.... default = 0 (disabled)

........................................ always reads 0

........................ default=1

Offset 43 - FIFO Configuration ....................................... RW

7-4 Reserved 3-2 Threshold for Primary Channel

00 0 01 1/4

10 1/2 .................................................... default

11 3/4

1-0 Threshold for Secondary Channel

00 0 01 1/4

10 1/2 .................................................... default

11 3/4

........................................always reads 0

0 Reserved

Offset 42 - Reserved (Do Not Program) .......................... RW

........................................ always reads 0

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Offset 44 - Miscellaneous Control 1 ................................. RW

7 Reserved 6 Master Read Cycle IRDY# Wait States

0 0 wait states

1 1 wait state..............................................default

5 Master Write Cycle IRDY# Wait States

0 0 wait states

1 1 wait state..............................................default

4 Reserved 3 Bus Master IDE Sta tus Register Read Retry

Retry bus master IDE status register read when master write operation for DMA read is not complete

0 Disabled

1 Enabled...................................................default

2-1 Reserved

0 UltraDMA Host Must Wait for First Strobe

Before Termination

0 Enabled...................................................default

1 Disabled

Offset 45 - Miscellaneous Control 2 ................................. RW

7 Reserved 6 Interrupt Steering Swap

0Don’t swap channel interrupts................default

1 Swap interrupts between the two channels

5-4 Reserved

3 Memory Read Multiple Command

0 Disable ...................................................default

1Enable

2 Memory Read and Invalidate Command

0 Disable ...................................................default

1Enable

1 Secondary Channel Threshold Enable

0 Disable (data transfer starts immediately if

1 Enable (data transfer will not start until the

0 Primary Channel Threshold Enable

0 Disable (data transfer starts immediately if

1 Enable (data transfer will not start until the

........................................ always reads 0

FIFO is not empty)

FIFO is filled to the threshold set in bits 1-0 of

Rx43) .....................................................default

FIFO is not empty)

FIFO is filled to the threshold set in bits 3-2 of

Rx43) .....................................................default

Offset 46 - Miscellaneous Control 3 ................................ RW

7 Primary Channel Read DMA FIFO Flush

1 = Enable FIFO flush for read DMA when interrupt

asserts primary channel. ...............default=1 (enabled)

6 Secondary Channel Read DMA FIFO Flush

1 = Enable FIFO flush for Read DMA when interrupt

asserts secondary channel............ Default=1 (enabled)

5 Primary Channel End-of-Sector FIFO Flush

1 = Enable FIFO flush at the end of each sector for

the primary channel.................... Default=0 (disabled)

4 Secondary Channel End-of-Secto r F IFO Flush

1 = Enable FIFO flush at the end of each sector for

the secondary channel.................Default=0 (disabled)

3-2 Reserved 1-0 Max DRDY Pulse Width

Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang.

00 No limitation.......................................... default

01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks

........................................always reads 0

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VT8231

Offset 4B-48 - Drive Timing Control ............................... RW

The following fields define the Active Pulse Width and Recovery Time for the IDE DIOR# and DIOW# signals:

31-28 Primary Drive 0 Active Pulse Width 27-24 Primary Drive 0 Recovery Time 23-20 Primary Drive 1 Active Pulse Width 19-16 Primary Drive 1 Recovery Time 15-12 Secondary Drive 0 Active Pulse Width

11-8 Secondary Drive 0 Recovery Time

7-4 Secondary Drive 1 Active Pulse Width 3-0 Secondary Drive 1 Recovery Time

The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks.

Offset 4C - Address Setup Time ....................................... RW

7-6 Primary Drive 0 Address Setup Time 5-4 Primary Drive 1 Address Setup Time 3-2 Secondary Drive 0 Address Setup Time 1-0 Secondary Drive 1 Address Setup Time

For each field above:

00 1T 01 2T 10 3T

11 4T .....................................................default

Offset 4E - Secondary Non-1F0 Port Access Timing ...... RW

7-4 DIOR#/DIOW# Active Pulse Width 3-0 DIOR#/DIOW# Recovery Time

The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks.

Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW

7-4 DIOR#/DIOW# Active Pulse Width 3-0 DIOR#/DIOW# Recovery Time

The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks.

......def=1010b

.............def=1000b

......def=1010b

.............def=1000b

..def=1010b

.........def=1000b

..def=1010b

.........def=1000b

.......def=1111b

..............def=1111b

.......def=1111b

..............def=1111b

Offset 53-50 - UltraDMA Extended Timing Control ..... RW

31 Pri Drive 0 UltraDMA-Mode Enable Method

0 Enable by using “Set Feature” command.....def

1 Enable by setting bit-30 of this register

30 Pri Drive 0 UltraDMA-Mode Enable

0 Disable...................................................default

1 Enable UltraDMA-Mode Operation

29 Pri Drive 0 Transfer Mode

0 DMA or PIO Mode ............................... default

1 UltraDMA Mode

28-27 Reserved 26-24 Pri Drive 0 Cycle Time (T = 30nsec @33MHz)

000 2T 001 3T 010 4T 011 5T 100 6T 101 7T 110 8T

111 9T .................................................... default

23 Pri Drive 1 UltraDMA-Mode Enable Method 22 Pri Drive 1 UltraDMA-Mode Enable 21 Pri Drive 1 Transfer Mode 20 Reserved 19 Pri Clock Source

0 33 MHz..................................................default

1 66 MHz

18-16 Pri Drive 1 Cycle Time

15 Sec Drive 0 UltraDMA-Mode Enable Method 14 Sec Drive 0 UltraDMA-Mode Enable 13 Sec Drive 0 Transfer Mode

12-11 Reserved

10-8 Sec Drive 0 Cycle Time

7 Sec Drive 1 UltraDMA-Mode Enable Method 6 Sec Drive 1 UltraDMA-Mode Enable 5 Sec Drive 1 Transfer Mode 4 Reserved 3 Sec Clock Source

0 33 MHz..................................................default

1 66 MHz

2-0 Sec Drive 1 Cycle Time

Each byte defines UltraDMA operation for the indicated drive. The bit definitions are the same within each byte.

........................................always reads 0

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Offset 54 – UltraDMA FIFO Control .............................. RW

7-5 Reserved

4 One Frame For Each PCI Request For IDE PCI

Master Cycles

0 Disabled ................................................default

1Enabled

3 Grant ISA While Sharing Bus with SA & IDE in

IDLE State

0 Enable.....................................................default

1 Disable

2 Change Drive to Clear All FIFO & Internal States

0 Disabled

1 Enabled...................................................default

1 Add Dummy FIFO Push After End of Transfer

0Enabled

1 Disabled .................................................default

This bit is normally set to 0 for effective handling of transfer lengths that are not doubleword multiples

0 Complete DMA Cycle with Transfer Size Less

Than FIFO Size

0 Enabled...................................................default

1 Disabled

........................................ always reads 0

Offset 61-60 - Primary Sector Size .................................. RW

15-12 Reserved

11-0 Number of Bytes Per Sector

Offset 69-68 - Secondary Sector Size .............................. RW

15-12 Reserved

11-0 Number of Bytes Per Sector

........................................always reads 0

...def=200h (512 bytes)

........................................always reads 0

...def=200h (512 bytes)

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Offset 70 – Primary IDE Status ....................................... RW

7 Interrupt Status 6 Prefetch Buffer Status 5 Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete

1-0 Reserved

Offset 71 – Primary Interrupt Control ............................ RW

7-1 Reserved

0 Flush FIFO Before Generating IDE Interrupt

0 Disable ...................................................default

1Enable

........................................ always reads 0

Offset 78 – Secondary IDE Status ................................... RW

7 Interrupt Status 6 Prefetch Buffer Status 5 Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete

1-0 Reserved

Offset 79 - Secondary Interrupt Control ........................ RW

7-1 Reserved

0 Flush FIFO Before Generating IDE Interrupt

0 Disable...................................................default

1Enable

........................................always reads 0

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Offset 83-80 – Primary S/G Descriptor Address ............ RW

Offset 8B-88 – Secondary S/G Descriptor Address ........ RW

Offset C3-C0 – PCI PM Block 1 ....................................... RO

31-0 PCI PM Block 1

Offset C7-C4 – PCI PM Block 2 ....................................... RO

31-2 Reserved

1-0 Pow er State

00 On .....................................................default

01 Off 1x -reserved-

.......................... always reads 0201h

........................................ always reads 0

IDE I/O Registers

These registers are compliant with the SFF 8038I v1.0 standard. Refer to the SFF 8038I v1.0 specification for further details.

I/O Offset 0 - Primary Channel Command I/O Offset 2 - Primary Channel Status I/O Offset 4-7 - Primary Channel PRD Table Address

I/O Offset 8 - Secondary Channel Command I/O Offset A - Secondary Channel Status I/O Offset C-F - Secondary Channel PRD Table Address

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Function 2 Registers - USB Controller Ports 0-1

This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT8231. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 0-1 (see function 3 for ports 2-3).

PCI Configuration Space Header

Offset 1-0 - Vendor ID ....................................................... RO

0-7 Vendor ID

Offset 3-2 - Device ID ......................................................... RO

0-7 Device ID

Offset 5-4 - Command ....................................................... RW

15-8 Reserved

7 Address Stepping 6 Reserved 5 Reserved 4 Memory Write and Invalidate 3 Reserved 2Bus Master 1 Memory Space 0 I/O Space

Offset 7-6 - Status ........................................................... RWC

15 Reserved 14 Sig nalled System Error 13 Received Master Abort 12 Received Target Abort 11 Signalled Target Abort

10-9 DEV SEL# Timing

00 Fast

01 Medium......................................default (fixed)

10 Slow 11 Reserved

8-0 Reserved

................. (1106h = VIA Technologies)

(3038h = VT8231 USB Controller)

........................................ always reads 0

...................... default=0 (disabled)

(parity error response)..................fixed at 0

(VGA palette snoop)....................fixed at 0

. d efault=0 (disabled)

(special cycle monitoring) ............fixed at 0

............................... default=0 (disabled)

........................... default=0 (disabled)

............................... default=0 (disabled)

(detected parity error).......... always reads 0

.............................. default=0

........................................ always reads 0

Offset 8 - Revision ID (nnh) .............................................. RO

7-0 Silicon Revision Code (0 indicates first silicon)

06h Corresponds to Chip Revision D

Offset 9 - Programming Interface (00h) .......................... RO

Offset A - Sub Class Code (03h=USB Controller) .......... RO

Offset B - Base Class Code (0Ch=Serial Bus Controller) RO

Offset C – Cache Line Size (00h) ...................................... RO

Offset D - Latency Timer ................................................. RW

7-0 Timer Value

Offset E - Header Type (00h) ............................................ RO

Offset F - BIST (00h) ......................................................... RO

Offset 23-20 - USB I/O Register Base Address ............... RW

31-16 Reserved

15-5 USB I/O Register Base Address.

the base of the 32-byte USB I/O Register block, corresponding to AD[15:5]

4-0 00001b

Offset 3C - Interrupt Line (00h) ...................................... RW

7-4 Reserved 3-0 USB Interrupt Routing

0000 Disabled................................................. default

0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled

..........................................default = 16h

........................................always reads 0

Port Address for

........................................always reads 0

........................default = 16h

Offset 3D - Interrupt Pin (04h) ......................................... RO

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USB-Specific Configuration Registers

VT8231

Offset 40 - Miscellaneous Control 1 ................................. RW

7 PCI M emory Command Option

0 Support Memory-Read-Line, Memory-Read-

Multiple, & Memory-Write-&-Invalidate.... def

1 Only support Mem Read, Mem Write Cmds

6 Babble Option

0 Automatically disable babbled port when EOF

babble occurs..........................................default

1Don’t disable babbled port

5 PCI Parity Check Option

0 Disable PERR# generation.....................default

1 Enable parity check and PERR# generation

4 Frame Interval Select

0 1 ms frame..............................................default

1 0.1 ms frame

3 USB Data Length Option

0 Support TD length up to 1280................default

1 Support TD length up to 1023

2 USB Power M anagement

0 Disable USB power management...........default

1 Enabl e USB power management

1DMA Option

0 8 DW burst access with better FIFO latencydef 1 16 DW burst access (original performance)

0PCI Wait States

0 Zero wait ................................................default

1One wait

Offset 41 - Miscellaneous Control 2 ................................ RW

7 USB 1.1 Improvement for EOP

0 USB Specification 1.1 Compliant.......... default

If a bit stuffing error occurs before EOP, the receiver will accept the packet

1 USB Specification 1.0 Compliant

If a bit stuffing error occurs before EOP, the receiver will ignore the packet

6-5 Reserved (Do Not Program)

4 Hold PCI Request for Successive Accesses

0 Disable

1 Enable....................................................default

Setting this bit to “enable” causes the system to treat the USB request as higher priority

3 Frame Counter Test Mode

0 Disable...................................................default

1Enable

2Trap Option

0 Set trap 60/64 status bits only when trap 60/64

enable bits are set. .................................default

1 Set trap 60/64 status bits without checking

enable bits

1 A20gate Pass Through Option

0 Pass through A20GATE command sequence

defined in UHCI....................................default

1Don’t pass through Wri te I/O port 64 (ff)

0 USB IRQ Test Mode

0 Normal Operation..................................default

1 Generate USB IRQ

....................default = 0

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Offset 42 - FIFO Control .................................................. RW

7-4 Reserved 3-2 Reserved (Do Not Program) 1-0 Release Continuous REQ After “N” PCICLKs

00 Do Not Release ........................................... def

01 N = 32 PCICLKs 10 N = 64 PCICLKs 11 N = 96 PCICLKs

Offset 60 - Serial Bus Release Number ............................. RO

7-0 Release Number

Offset 83-80 – PM Capability ............................................ RO

31-0 PM Capability

Offset 84 – PM Capability Status .................................... RW

7-0 PM Capability Status

Supports 00h (Off) and 11h (On) only

Offset C1-C0 - Legacy Support ......................................... RO

15-0 UHCI v1.1 Compliant

........................................ always reads 0

.................... default = 0

.............................. always reads 10h

.................... always reads 00020001h

........................... default = 00h

................ always reads 2000h

USB I/O Registers

These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details.

I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control

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Function 3 Registers - USB Controller Ports 2-3

This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 3 PCI configuration space of the VT8231. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 2-3 (see function 2 for ports 0-1).

PCI Configuration Space Header

Offset 1-0 - Vendor ID ....................................................... RO

0-7 Vendor ID

Offset 3-2 - Device ID ......................................................... RO

0-7 Device ID

Offset 5-4 - Command ....................................................... RW

15-8 Reserved

7 Address Stepping 6 Reserved 5 Reserved 4 Memory Write and Invalidate 3 Reserved 2Bus Master 1 Memory Space 0 I/O Space

Offset 7-6 - Status ........................................................... RWC

15 Reserved 14 Sig nalled System Error 13 Received Master Abort 12 Received Target Abort 11 Signalled Target Abort

10-9 DEV SEL# Timing

00 Fast

01 Medium......................................default (fixed)

10 Slow 11 Reserved

8-0 Reserved

................. (1106h = VIA Technologies)

(3038h = VT8231 USB Controller)

........................................ always reads 0

...................... default=0 (disabled)

(parity error response)..................fixed at 0

(VGA palette snoop)....................fixed at 0

. d efault=0 (disabled)

(special cycle monitoring) ............fixed at 0

............................... default=0 (disabled)

........................... default=0 (disabled)

............................... default=0 (disabled)

(detected parity error).......... always reads 0

.............................. default=0

........................................ always reads 0

Offset 8 - Revision ID (nnh) .............................................. RO

7-0 Silicon Revision Code (0 indicates first silicon)

Offset 9 - Programming Interface (00h) .......................... RO

Offset A - Sub Class Code (03h=USB Controller) .......... RO

Offset B - Base Class Code (0Ch=Serial Bus Controller) RO

Offset C – Cache Line Size (00h) ...................................... RO

Offset D - Latency Timer ................................................. RW

7-0 Timer Value

Offset E - Header Type (00h) ............................................ RO

Offset F - BIST (00h) ......................................................... RO

Offset 23-20 - USB I/O Register Base Address ............... RW

31-16 Reserved

15-5 USB I/O Register Base Address.

the base of the 32-byte USB I/O Register block, corresponding to AD[15:5]

4-0 00001b

Offset 3C - Interrupt Line (00h) ...................................... RW

7-4 Reserved 3-0 USB Interrupt Routing

0000 Disabled................................................. default

0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled

..........................................default = 16h

........................................always reads 0

Port Address for

........................................always reads 0

........................default = 16h

Offset 3D - Interrupt Pin (04h) ......................................... RO

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USB-Specific Configuration Registers

VT8231

Offset 40 - Miscellaneous Control 1 ................................. RW

7 PCI M emory Command Option

0 Support Memory-Read-Line, Memory-Read-

Multiple, & Memory-Write-&-Invalidate.... def

1 Only support Mem Read, Mem Write Cmds

6 Babble Option

0 Automatically disable babbled port when EOF

babble occurs..........................................default

1Don’t disable babbled port

5 PCI Parity Check Option

0 Disable PERR# generation.....................default

1 Enable parity check and PERR# generation

4 Frame Interval Select

0 1 ms frame..............................................default

1 0.1 ms frame

3 USB Data Length Option

0 Support TD length up to 1280................default

1 Support TD length up to 1023

2 USB Power M anagement

0 Disable USB power management...........default

1 Enabl e USB power management

1DMA Option

0 8 DW burst access with better FIFO latencydef 1 16 DW burst access (original performance)

0PCI Wait States

0 Zero wait ................................................default

1One wait

Offset 41 - Miscellaneous Control 2 ................................ RW

7 USB 1.1 Improvement for EOP

0 USB Specification 1.1 Compliant.......... default

If a bit stuffing error occurs before EOP, the receiver will accept the packet

1 USB Specification 1.0 Compliant

If a bit stuffing error occurs before EOP, the receiver will ignore the packet

6-5 Reserved (Do Not Program)

4 Hold PCI Request for Successive Accesses

0 Disable

1 Enable....................................................default

Setting this bit to “enable” causes the system to treat the USB request as higher priority

3 Frame Counter Test Mode

0 Disable...................................................default

1Enable

2Trap Option

0 Set trap 60/64 status bits only when trap 60/64

enable bits are set. .................................default

1 Set trap 60/64 status bits without checking

enable bits

1 A20gate Pass Through Option

0 Pass through A20GATE command sequence

defined in UHCI....................................default

1Don’t pass through Wri te I/O port 64 (ff)

0 USB IRQ Test Mode

0 Normal Operation..................................default

1 Generate USB IRQ

....................default = 0

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Offset 42 - FIFO Control .................................................. RW

7-4 Reserved 3-2 Reserved (Do Not Program) 1-0 Release Continuous REQ After “N” PCICLKs

00 Do Not Release ........................................... def

01 N = 32 PCICLKs 10 N = 64 PCICLKs 11 N = 96 PCICLKs

Offset 60 - Serial Bus Release Number ............................. RO

7-0 Release Number

Offset 83-80 – PM Capability ............................................ RO

31-0 PM Capability

Offset 84 – PM Capability Status .................................... RW

7-0 PM Capability Status

Offset C1-C0 - Legacy Support ......................................... RO

15-0 UHCI v1.1 Compliant

........................................ always reads 0

.................... default = 0

.............................. always reads 10h

.................... always reads 00020001h

.......supports 00h and 11h only

................ always reads 2000h

USB I/O Registers

These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details.

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Function 4 Regs - Power M anagement, SMBus and HWM

This section describes the ACPI (Advanced Configuration and Power Interface) Power Management system of the VT8231 which includes a System Management Bus ( SMBus) interfac e controller and Hardware Monitoring (HWM) subsystem. The power management system of the VT8231 supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v1.0 specifications.

PCI Configuration Space Header

Offset 1-0 - Vendor ID ....................................................... RO

0-7 Vendor ID

Offset 3-2 - Device ID ......................................................... RO

0-7 Device ID

Offset 5-4 - Command ....................................................... RW

15-8 Reserved

7 Address Stepping 6 Reserved 5 Reserved 4 Memory Write and Invalidate 3 Reserved 2Bus Master 1 Memory Space 0 I/O Space

Offset 7-6 - Status ........................................................... RWC

15 Detected Parity Error 14 Sig nalled System Error 13 Received Master Abort 12 Received Target Abort 11 Signalled Target Abort

10-9 DEV SEL# Timing

00 Fast

01 Medium .....................................default (fixed)

10 Slow 11 Reserved

8 Data Parity Detected 7 Fast Back to Back Capable

6-0 Reserved

................. (1106h = VIA Technologies)

................(3057h = ACPI Power Mgmt)

........................................ always reads 0

........................................fixed at 0

(parity error response)..................fixed at 0

(VGA palette snoop)....................fixed at 0

...................fixed at 0

(special cycle monitoring) ............fixed at 0

.................................................fixed at 0

.............................................fixed at 0

.................................................fixed at 0

........................ always reads 0

...................... always reads 0

.......................... always reads 0

............... always reads 1

........................................ always reads 0

VT8231

Offset 8 - Revision ID (nnh) .............................................. RO

7-0 Silicon Revision Code

Offset 9 - Programming Interface (00h) .......................... RO

The value returned by this register may be changed by writing the desired value to PCI Configurati on Function 4 offset 61h.

Offset A - Sub Class Code (00h) ....................................... RO

The value returned by this register may be changed by writing the desired value to PCI Configurati on Function 4 offset 62h.

Offset B - Base Class Code (00h) ...................................... RO

The value returned by this register may be changed by writing the desired value to PCI Configurati on Function 4 offset 63h.

Offset 0D - Latency Timer ............................................... RW

7-0 Timer Value

Offset 0E - Header Type (00h) .......................................... RO

..............................................default = 0

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Power Management-Specific PCI Configuration Registers

VT8231

Offset 40 – General Configuration 0 ............................... RW

7 Thermal Alarm Source Select

0 From pin T11 (Function 0 Rx74[1] must be set

to define the pin as THRM#)..................default

1 From any of the three internal temperature

sensing circuits (see Rx43 and Rx44 of Hardware Monitoring configuration space)

6 Sleep Button

0 Disable ...................................................default

1 Sleep Button is on IRQ6 pin (pin G1)

5 Debounce LID and PWRBTN# Inputs for 200us

0 Disable ...................................................default

1Enable

4 Reserved 3 Microsoft Sound Monitor in Audio Access

0 Disable ...................................................default

1Enable

2 Game Port Monitor in Audio Access

0 Disable ...................................................default

1Enable

1 SoundBlaster Monitor in Audio Access

0 Disable ...................................................default

1Enable

0 MIDI Monitor in Audio Access

0 Disable ...................................................default

1Enable

........................................ always reads 0

Offset 41 - General Configuration 1 ................................ RW

7 I/O Enable for ACPI I/O Base

0 Disable access to ACPI I/O block..........default

1 Allow access to Power Management I/O

Register Block (see offset 4B-48 to set the base address for this register block). The definitions of the registers in the Power Management I/O Register Block are included later in this document, following the Power Management Subsystem overview.

6 ACPI Timer Reset

0 Normal Timer Operation ....................... default

1 Reset Timer

5-4 PMU Timer Test Mode

3 ACPI Timer Count Select

0 24-bit Timer...........................................default

1 32-bit Timer

2 RTC Enable Signal Gated with PSON (SUSC#) in

Soft-Off Mode

0 Disable...................................................default

1Enable

1 Clock Throttling Clock Selection

0 32 usec (512 usec cycle time)................default

1 1 msec (16 msec cycle time)

0 DEVSEL# Test Mode

(Do Not Program)....def = 0

(Do Not Program).......def = 0

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Offset 42 - ACPI Interrupt Select .................................... RW

7 ATX / AT Power Indicator

0ATX 1AT

6 SUSC# State 5 Reserved 4 SUSC# AC-Power-On Default Value

This bit is written at RTC Index 0A bit-7.

3-0 SCI Interrupt Assignment

0000 Disabled .................................................default

0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 IRQ15

Offset 43 – Internal Timer Read Test ............................... RO

7-0 Internal Timer Read Test

..........................................................RO

........................................ always reads 0

..................................RO

.................RO

Offset 45-44 - Primary Interrupt Channel (0000h) ....... RW

15 1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel 14 1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel 13 1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel 12 1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel 11 1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel 10 1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel

9 1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel 8 1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel 7 1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel 6 1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel 5 1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel 4 1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel 3 1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel 2 Reserved 1 1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel 0 1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel

Offset 47-46 - Secondary Interrupt Channel (0000h) .... RW

15 1/0 = Ena/Disa IRQ15 as Secondary Intr Channel 14 1/0 = Ena/Disa IRQ14 as Secondary Intr Channel 13 1/0 = Ena/Disa IRQ13 as Secondary Intr Channel 12 1/0 = Ena/Disa IRQ12 as Secondary Intr Channel 11 1/0 = Ena/Disa IRQ11 as Secondary Intr Channel 10 1/0 = Ena/Disa IRQ10 as Secondary Intr Channel

9 1/0 = Ena/Disa IRQ9 as Secondary Intr Channel 8 1/0 = Ena/Disa IRQ8 as Secondary Intr Channel 7 1/0 = Ena/Disa IRQ7 as Secondary Intr Channel 6 1/0 = Ena/Disa IRQ6 as Secondary Intr Channel 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel 2 Reserved 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel

........................................always reads 0

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Offset 4B-48 – Power Management I/O Base ................. RW

31-16 Reserved

15-7 Power Management I/O Register Base Address.

Port Address for the base of the 128-byte Power Management I/O Register block, corresponding to AD[15:7]. The "I/O Space" bit at offset 41 bit-7 enables access to this register block. The definitions of the registers in the Power Management I/O Register Block are included later in this document, following the Power-Management-Specific PCI Configuration register descriptions and the Power Management Subsystem overview.

6-0 0000001b

Offset 4C – Host Bus Power Management Control ........ RW

7-4 Thermal Duty Cycle (THM_DTY)

This 4-bit field determines the duty cycle of the STPCLK# signal when the THRM# pin is asserted low. The field is decoded as follows:

0000 Reserved.................................................default

0001 0-6.25% 0010 6.25-12.50% 0011 18.75-25.00% 0100 31.25-37.50% 0101 37.50-43.75% 0110 43.75-50.00% 0111 50.00-56.25% 1000 56.25-62.50% 1001 62.50-68.75% 1010 68.75-75.00% 1011 75.00-87.50% 1100 75.00-81.25% 1101 81.25-87.50% 1110 87.50-93.75% 1111 93.75-100%

3THRM Enable

0 Disable ...................................................default

1Enable

2 Frame Input as Resume Event in C3

0 Disable ...................................................default

1Enable

1 Reserved 0 CPU Stop Grant Cycle Select

0 From Halt and Stop Grant Cycle............default

1 From Stop Grant Cycle This bit is combined with I/O space Rx2C[3] for controlling the start of CPUSTP# assertion during system suspend mode:

Rx2C[3] Rx4C[0]

Function 4 Function 4

I/O Space Cfg Space

0 x Immediate 1 0 Wait for CP U Halt

1 1 Wait for CPU

........................................ always reads 0

CPUSTP# Assertion

/ Stop Grant cycle

Stop Grant cycle

Offset 4D – Throttle / Clock Stop Control ...................... RW

7 Throttle Timer Reset

6-5 Throttle Timer

0x 4-Bit ....................................................default

10 3-Bit 11 2-Bit

4 Fast Clock (7.5us) as Throttle Timer Tick

0 Disable...................................................default

1Enable

3 Reserved 2 Internal Clock Stop for PCI Idle

0 Disable...................................................default

1Enable

1 Internal Clock Stop During C3

0 Disable...................................................default

1Enable

0 Internal Clock Stop During Suspend

0 Disable...................................................default

1Enable

........................................always reads 0

......................................def = 0

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Offset 53-50 - GP Timer Control (0000 0000h) .............. RW

31-30 Conserve Mode Timer Count Value

00 1/16 second ............................................default

01 1/8 second 10 1 second 11 1 minute

29 Conserve Mode Status

This bit reads 1 when in Conserve Mode

28 Conserve Mo de Enable

0 Disable ...................................................default

1Enable

27-26 Secondary Event Timer Count Value

00 2 milliseconds.........................................default

01 64 milliseconds 10 ½ second 11 by EOI + 0.25 milliseconds

25 Secondary Event Occurred Status

This bit reads 1 to indicate that a secondary event has occurred (to resume the system from susp end) and the secondary event timer is counting down.

24 Secondary Event Timer Enable

0 Disable ...................................................default

1Enable

3 GP0 Timer Start

On setting this bit to 1, the GP0 timer loads the value defined by bits 15-8 of this register and starts counting down. The GP0 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP0 timer counts down to zero, then the GP0 Timer Timeout Status bit is set to one (bit-2 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP0 Timer Timeout Enable bit is set (bit-2 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated.

2 GP0 Timer Automatic Reload

0 GP0 Timer stops at 0 ............................ default

1 Reload GP0 timer automatically after counting

down to 0

1-0 GP0 Timer Base

00 Disable................................................... default

01 1/16 second 10 1 second 11 1 minute

23-16 GP1 Timer Count Value

Write to load count value; Read to get current count

15-8 GP0 Timer Count Value

Write to load count value; Read to get current count

7 GP1 Timer Start

On setting this bit to 1, the GP1 timer loads the value defined by bits 23-16 of this register and starts counting down. The GP1 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP1 timer counts down to zero, then the GP1 Timer Timeout Status bit is set to one (bit-3 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP1 Timer Timeout Enable bit is set (bit-3 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated.

6 GP1 Timer Automatic Reload

0 GP1 Timer stops at 0 .............................default

1 Reload GP1 timer automatically after counting

down to 0

5-4 GP1 Timer Base

00 Disable ...................................................default

01 1/4 msec 10 1 second 11 1 minute

(base defined by bits 5-4)

(base defined by bits 1-0)

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Offset 54 – Power Well Control ...................................... WO

7 SMBus Clock Select

0 SMBus Clock from 14.31818 MHz Divider def

1 SMBus Clock from RTC 32.768 KHz

6 STR Power Well Output Gating

0 Disable ...................................................default

1Enable

5 SUSC# = 0 for STR

0 Disable ...................................................default

1Enable

4 SUSST1# / GPO3 Select (Pin V10)

0 SUSST1#................................................default

1GPO3

3 GPO2 / SUSB# Select (Pin W9)

0 SUSB#....................................................default

1GPO2 Before chip rev C, these definitions were reversed

2 GPO1 / SUSA# Select (Pin V9)

0 SUSA# ...................................................default

1GPO1 Before chip rev C, these definitions were reversed

1-0 GPO0 (SLOWCLK) Output Selection (Pin T8)

00 From GPO0 (PMU I/O Rx4C[0])...........default

01 1 Hz 10 4 Hz 11 16 Hz

Offset 55 – USB Wakeup .................................................. RW

7-1 Reserved

0 USB Wakeup for STR/STD/Soff

0 Disable...................................................default

1Enable

........................................always reads 0

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Offset 58 – GP2 / GP3 Timer Control ............................. RW

7 GP3 Timer Start

On setting this bit to 1, the GP3 timer loads the value defined by Rx5A and starts counting down. The GP3 timer is reloaded at the occurrence of certain events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP 3 timer counts down to zero, then the GP3 Timer Timeout Status bit is set to one (bit-13 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP3 Timer Timeout Enable bit is set (bit-13 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated.

6 GP3 Timer Automatic Reload

0 GP3 Timer stops at 0 .............................default

1 Reload GP3 timer automatically after counting

down to 0

5-4 GP3 Timer Tick Select

00 Disable ...................................................default

01 1/4 millisecond 10 1 second 11 1 minute

Offset 59 – GP2 Timer ...................................................... RW

7 Write: GP2 Timer Load Value

Read: GP2 Timer Current Count

Offset 5A – GP3 Timer ..................................................... RW

7 Write: GP3 Timer Load Value

Read: GP3 Timer Current Count

...............default = 0

3 GP2 Timer Start

On setting this bit to 1, the GP2 timer loads the value defined by Rx59 and starts counting down. The GP2 timer is reloaded at the occurrence of certain events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP 2 timer counts down to zero, then the GP2 Timer Timeout Status bit is set to one (bit-12 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP2 Timer Timeout Enable bit is set (bit-12 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated.

2 GP2 Timer Automatic Reload

0 GP2 Timer stops at 0 .............................default

1 Reload GP2 timer automatically after counting

down to 0

1-0 GP2 Timer Tick Select

00 Disable ...................................................default

01 1/16 second 10 1 second 11 1 minute

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Offset 61 – Program Interface Read Value .................... WO

7-0 Rx09 Read Value

The value returned by the register at offset 9h (Programming Interface) may be changed by writing the desired value to this location.

Offset 62 - Sub Class Read Value.................................... WO

7-0 Rx0A Read Value

The value returned by the register at offset 0Ah (Sub Class Code) may be changed by writing the desired value to this location.

Offset 63 - Base Class Read Value .................................. WO

7-0 Rx0B Read Value

The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location.

VT8231

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Hardware-Monitor-Specific Configuration Registers

Offset 71-70 – Hardware Monitor I/O Base ................... RW

15-7 I/O Base (128-byte I/O space)

6-0 Fixed

Offset 74 –Hardware Monitor Control ........................... RW

7-4 Reserved

3 Hardware Monitoring Interrupt

0 SMI .....................................................default

1SCI

2-1 Reserved

0 Hardware Monitoring I/O Enable

0 Disable hardware monitor functions.......default

1 Enabl e hardware monitor functions

.......................... always reads 0000001b

........................................ always reads 0

................. default = 0

System Management Bus-Specific Configuration Reg ist ers

Offset 93-90 – SMBus I/O Base ....................................... RW

31-16 Reserved

15-4 I/O Base (16-byte I/O space)

3-0 Fixed

Offset D2 – SMBus Host Configuration ......................... RW

7-4 Reserved

3 SMBus Interrupt Select

0 SMI .................................................... default

1SCI

2 Reserved 1SMBus IRQ

0 Disable...................................................default

1Enable

0 SMBus Host Controller Enable

0 Disable SMB controller functions .........default

1 Enable SMB controller functions

Offset D3 – SMBus Host Slave Command ...................... RW

7-0 SMBus Host Slave Command Code

Offset D4 – SMBus Slave Address for Port 1 ................. RW

7-0 SMBus Slave Address for Port 1

Bit-0 must be set to 0 for proper operation

........................................always reads 0

................default = 00h

................................always reads 0001b

........................................always reads 0

..........default=0

...............default=0

Offset D5 – SMBus Slave Address for Port 2 ................. RW

7-0 SMBus Slave Address for Port 2

Bit-0 must be set to 0 for proper operation

Offset D6 – SMBus Revision ID ....................................... RO

7-0 SMB us Revision Code

...............default=0

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Power Management I/O-Space Registers

Basic Power Management Control and Status

VT8231

I/O Offset 1-0 - Power Management Status ................. RWC

The bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position.

15 Wakeup Status

(WAK_STS) ................... default = 0

This bit is set when the system is in the suspend state and an enabled resume event occurs. Upon setting this bit, the system automatically tr ansitions from the suspend state to the no rmal working state (from C3 to C0 for the processor).

14-12 Reserved

11 Abnormal Power-Off 10 RTC Status

........................................ always reads 0

(APO_STS)........... default = 0

(RTC_STS)........................... default = 0

This bit is set when the RTC generates an alarm (on assertion of the RTC IRQ signal).

9 Sleep Button Status

(SB_STS)................. default = 0

This bit is set when the sleep button (SLPBTN# / IRQ6 / GPI4) is pressed.

8 Power Button Status

(PB_STS)............... default = 0

This bit is set when the PWRBTN# signal is asser ted LOW. If the PWRBTN# signal is held LOW for more than four seconds, this bit is cleared, the PBOR_STS bit is set, and the system will transition into the soft off state.

7-6 Reserved

5 Global Status

........................................ always reads 0

(GBL_STS)........................default = 0

This bit is set by hardware when BIOS_RLS is set (typically by an SMI routine to release control o f the SCI/SMI lock). When this bit is cleared by software (by writing a one to this bit position) the BIOS_RLS bit is also cleared at the same time by hardware.

4 Bus Master Status

(BM_STS) ................. default = 0

This bit is set when a system b us master requests the system bus. All PCI master, ISA master and ISA DMA devices are included.

3-1 Reserved

0 ACPI Timer Carry Status

The bit is set when the 23

........................................ always reads 0

(TMR_STS).. default = 0

(31st) bit of the 24 (32)

bit ACPI power management timer changes.

I/O Offset 3-2 - Power Management Enable .................. RW

The bits in this register correspond to the bits in the Power Management Status Register at offset 1-0.

15 Reserved

14-12 Reserved

11 Reserved 10 RTC Enable

........................................always reads 0

(RTC_EN)............................ default = 0

This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the RTC_STS bit is set.

9 Sleep Button Enable

(SB_EN) .................default = 0

This bit may be set to trigger either an SCI or SMI when the SB_STS bit is set.

8 Power Button Enable

(PB_EN) ...............default = 0

This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the PB_STS bit is set.

7-6 Reserved

5 Global Enable

........................................always reads 0

(GBL_EN).........................default = 0

This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the GBL_STS bit is set.

4 Reserved

3-1 Reserved

0 ACPI Timer Enable

........................................always reads 0

(TMR_EN)..............default = 0

This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the TMR_STS bit is set.

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I/O Offset 5-4 - Power Management Control ................. RW

15 Soft Resume 14 Reserved 13 Sleep Enable

This is a write-only bit; reads from this bit always return zero. Writing a one to this bit causes the system to sequence into the sleep (suspend) state defined by the SLP_TYP field.

12-10 Sleep Type

000 Normal On 001 Suspend to RAM (STR) 010 Suspend to Disk (STD) (also called Soft Off).

011 Reserved 100 Power On Suspend without Reset 101 Power On Suspend with CPU Reset 110 Power On Suspend with CPU/PCI Reset

111 Reserved In any sleep state, there is minimal interface between powered and non-powered planes so that the effort for hardware design may be well managed.

9-3 Reserved

2 Global Release

This bit is set by ACPI software to indicate the release of the SCI / SMI lock. Upon setting of this bit, the hardware automatically sets the BIOS_STS bit. The bit is cleared by hardware when the BIOS_STS bit is cleared by software. Note that the setting of this bit will cause an SMI to b e generated if the BIOS_EN bit is set (bit-5 of the Global Enable register at offset 2Ah).

1 Bus Master Reload

0 Bus master requests are ignored by power

1 Bus master requests transition the processor

0SCI Enable

Selects the power management event to generate either an SCI or SMI:

0 Generate SCI..........................................default

1 Generate SMI Note that certain power management events can be programmed individually to generate an SCI or SMI independent of the setting of this bit (refer to the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24). Also, TMR_STS & GBL_STS always generate SCI and BIOS_STS always generates SMI.

........................................ always reads 0

(SLP_EN)...................... always reads 0

(SLP_TYP)

The VCC power plane is turned off while the VCCS and VBAT planes remain on.

........................................ always reads 0

(GBL_RLS)............WO, default = 0

(BMS_RLD)

management logic...................................default

from the C3 state to the C0 state

(SCI_EN)

I/O Offset 0B-08 - Power Management Timer ............... RW

31-24 Extended Timer Value (ETM_VAL)

This field reads back 0 if the 24-bit timer option is selected (Rx41 bit-3).

23-0 Timer Value (TMR_VAL)

This read -only field returns the running co unt of the power management timer. This is a 24/32-bit counter that runs off a 3.579545 MHz clock, and counts while in the S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped.

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Processor Power Management Registers

VT8231

I/O Offset 13-10 - Processor & PCI Bus Control............ RW

31-12 Reserved

11 PCI Stop (PCISTP# asserted) w hen PCKRUN# is

Deasserted (PCI_STP)

0 Enable.....................................................default

1 Disable

10 PCI B us Clo ck Run Without Stop (PCI_RUN)

0 PCKRUN# will be de-activated after the PCI

1 PCKRUN# is always asserted

9 Host Clock Stop Enable (HOST_STP)

0 STPCLK# will be asserted in the C3 state, but

1 CPU clock is stopped in the C3 state

8 Assert SLP# for Processor Level 3 Read

0 Disable ...................................................default

1Enable Used in Slot-1 systems only.

7-5 Reserved

4 Throttling Enable (THT_EN)

Setting this bit starts clock throttling (modulating the STPCLK# signal) regar dless of the CPU state. The throttling duty cycle is determined by bits 3-0 of this register.

3-0 Throttling Duty Cycle (THT_DTY)

This 4-bit field determines the duty cycle of the STPCLK# signal when the system is in throttling mode (the "Throttling Enable" bit is set to one). The duty cycle indicates the percentage of time the STPCLK# signal is asserted while the Throttling Enable bit is set. The field is decoded as follows:

0000 Reserved 0001 0-6.25% 0010 6.25-12.50% 0011 18.75-25.00% 0100 31.25-37.50% 0101 37.50-43.75% 0110 43.75-50.00% 0111 50.00-56.25% 1000 56.25-62.50% 1001 62.50-68.75% 1010 68.75-75.00% 1011 75.00-87.50% 1100 75.00-81.25% 1101 81.25-87.50% 1110 87.50-93.75% 1111 93.75-100%

........................................ always reads 0

bus is idle for 26 clocks..........................default

the CPU clock is not stopped.................default

........................................ always reads 0

I/O Offset 14 - Processor Level 2 ...................................... RO

7-0 Level 2

Reads from this register put the processor into the Stop Grant state (the VT8231 asserts STPCLK# to suspend the processor). Wake up from Stop Grant state is by interrupt (INTR, SMI, and SCI).

Reads from this register return all zeros; writes to this register have no effect.

I/O Offset 15 - Processor Level 3 ...................................... RO

7-0 Level 3

Reads from this register put the processor in the C3 clock state with the STPCLK# signal asserted. If Rx10[9] = 1 then the CPU clock is also stopped by asserting CPUSTP #. Wakeup from the C3 stat e is by interrupt (INTR, SMI, and SCI).

Reads from this register return all zeros; writes to this register have no effect.

........................................always reads 0

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Datasheet VT8231 Datasheet (VIA)

Specifications and Main Features

Frequently Asked Questions

User Manual