Datasheet VT73LVP10S1X, VT73LVP10S1, VT73LVP10MX, VT73LVP10-DW, VT73LVP10M Datasheet (Vaishali Semiconductor)
...Page 1
Preliminary
VT73LVP10
TTL to Differential LVPECL Translator
with Enable
Applications
•= PECL clock source
General Description
The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW
enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts
an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail.
When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state.
Features
•= 700ps typical propagation delay
•= Differential LVPECL outputs
•= Flow-through pinout
•= -40
o
C to +85o C operating temperature range
•= 5V - tolerant inputs
•= ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
•= Available as die, 8-pin SOIC or 8 pin
MSOP package
Figure 1. Functional Block Diagram & Pin Assignment
NC
Q
QN
/EN
8 pin SOIC/ MSOP
1
2
LVPECL
3
4
100kΩ
TTL/
CMOS
8
VDD
7
D
6
NC
5 GND
2002-01-15 Page 1 MDST-0014-07
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
www.vaishali.com
Page 2
VT73LVP10 Preliminary
Table 1. Pin Description
Name Description Type Pin #
/EN CMOS/TTL Active LOW enable input, with pull-down resistor I 4*
Q PECL data output O 2
QN PECL complementary data output O 3
VDD Connect to 3.3V P 8
D CMOS/TTL data input I 7
GND Connect to ground P 5
Legend: I = Input
O = Output
P = Power supply connection
* = Internal 100kΩ pull-down resistor
Table 2. Absolute Maximum Ratings
Symbol Parameter Conditions Min Typ Max Units
VDD Supply voltage Referenced to GND 6 V
VIN Input voltage Referenced to GND -0.5 6 V
I
Output current in LOW state 50 mA
OUT
T
Storage temperature -65 150 oC
STG
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Table 3. Operating Conditions
Symbol Parameter Conditions Min Typ Max Units
VDD Power Supply Voltage 3.0 3.6 V
TA Ambient Temperature -40 85 oC
VIH Input HIGH Voltage D, /EN inputs 2.0 V
VIL Input LOW Voltage D, /EN inputs 0.8 V
t
Input slew rate
Rin
t
Input slew rate
Fin
10% to 90% (L → H)
90% to 10% (H → L)
1 V/ns
1 V/ns
2002-01-15 Page 2 MDST-0014-06
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Page 3
VT73LVP10 Preliminary
Table 4. DC Characteristics
TA = -40oC to +85oC, VDD = 3.0V to 3.6V unless otherwise stated below.
Symbol Parameter Conditions Min Typ Max Units
IIH
Input HIGH Current VIN = 2.7V
D input 1
/EN input
50
µA
IIL
Input LOW Current VIN = 0.5V
D input 1
/EN input
20
µA
VIK Input Clamp Diode Voltage IIN = -18mA -1.2 V
VOH Output HIGH Voltage
VOL Output LOW Voltage
IDD Power Supply Current
(1, 2)
(1, 2)
(2)
33 mA
-40oC 2275 2375 2475 mV
25oC 2200 2300 2400
o
85
C
-40oC 1350 1450 1550 mV
25oC 1400 1500 1600
85oC
= 3.3V
V
DD
VDD = 3.3V
2125 2225 2325
1450 1550 1650
mV
mV
mV
mV
Notes:1.The VT73LVP10 is designed to meet these specifications after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board.
2. Q and QN outputs are loaded with 50 ohms to V
-2 volts.
DD
Table 5. AC Characteristics
TA = -40oC to +85oC, VDD = 3.0V to 3.6V
Symbol Parameter Conditions Min Typ Max Units
t
Propagation Delay
PLH
t
Propagation Delay
PHL
t
Propagation Delay /EN to Q, QN 1.5 2.5 ns
PLH
t
Propagation Delay /EN to Q, QN 1.5 2.5 ns
PHL
tr/tf Output Rise/Fall time 20%-80% 0.25 0.35 0.7 ns
(1)
0.7 1.2 ns
(1)
0.7 1.2 ns
f
Maximum Input Frequency LVTTL or LVCMOS input 170 MHz
MAX
f
Maximum Input Frequency
MAX
(2)
750mV peak-to-peak sine
400 MHz
wave (AC coupled)
Notes: 1. Q and QN outputs are loaded with 50 ohms to V
-2 volts.
DD
2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source.
Ordering Information
Part Number Marking Shipping/Packaging No. of Pins Package Temperature
VT73LVP10S1 VT73LVP10S1 Tubes 8 SOIC
VT73LVP10S1X VT73LVP10S1 Tape & Reel 8 SOIC
VT73LVP10M VT73LVP10M Tubes 8 MSOP
VT73LVP10MX VT73LVP10M Tape & Reel 8 MSOP
VT73LVP10/D Dice in waffle-pak
VT73LVP10/DW Dice in wafer form
2002-01-15 Page 3 MDST-0014-06
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
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