The VNS1NV04D is a device formed by two
monolithic OMNIFET II chips housed in a
standard SO-8 package. The OMNIFET II are
designed in STMicroelectronics VIPower M0-3
BLOCK DIAGRAM
SO-8
Technology: they are int ended for repl acement of
standard Power MOSFETS from DC up to 50KHz
applications. Built in thermal shutdown, linear
current limitation and overvoltage clamp protects
the chip in harsh environments.
Fault feedback ca n be dete c ted by mo nitori ng the
voltage at the input pin.
INPUT1
GATE
CONTROL
OVER
TEMPERATURE
OVERVOLTAGE
CLAMP
LINEAR
CURRENT
LIMITER
DRAIN1
SOURCE1
DRAIN2
SOURCE2
OVERVOLTAGE
CLAMP
LINEAR
CURRENT
LIMITER
GATE
CONTROL
OVER
TEMPERATURE
INPUT2
Februa ry 20031/14
1
Page 2
VNS1NV04D
ABSOLUTE MAXIMUM RATI NG
SymbolParameterValueUnit
V
V
I
R
IN MINn
I
I
V
ESD1
V
ESD2
P
T
DSn
INn
INn
Dn
Rn
T
T
stg
Drain-source Voltage (V
Input Vol tageInternally Clamp edV
Input Current +/-20mA
Minimum I nput Series Impedance330Ω
Drain Current Internally LimitedA
Reverse DC Output Current -3A
Electros tatic Discharge (R=1.5KΩ, C=100pF)4000V
Electros tatic Discharge on output pins only (R=330Ω, C=150pF)16500V
Total Dissipation at Tc=25°C4W
(*) Pulsed: Pu ls e duration = 300µs, duty c y c le 1.5%
Drain Current LimitVIN=5V; VDS=13V 1.73.5A
=5V; VDS=13V
Step Response Current
Limit
Overtemperature
jsh
Shutdown
Overtemperature Reset135°C
jrs
Fault Sink CurrentVIN=5V; VDS=13V; Tj=T
gf
Sing l e Pu lse
as
Avala nche Energy
V
IN
starti ng T
V
IN
=25°C; VDD=24V
j
=5V R
gen=RIN MINn
(see figures 3 & 4)
jsh
=330Ω; L=50mH
2.0µ s
150175200°C
101520mA
55mJ
4/14
2
Page 5
VNS1NV04D
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC to
50KHz. The only difference from the user’s
standpoint is that a small DC current I
100µA) flows into the INPUT pin in order to supply
ISS
(typ.
the internal circuitry.
The de vice integrates :
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics o f the Power MOSFET
stage giv e this device unrivall ed ruggedne ss and
energy handl ing capability. This feat ure is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current ID to I
voltage. When the current limiter is active, the
whatever the INPUT pin
lim
device operates in the linear region, so power
dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing the
chip temperature and are not dependent on the
input voltage. The location of the sensi ng eleme nt
on the chip in the power st age ar ea ensures f ast,
accurate detection of the junction temperature.
Overtemperature cutout occurs in the range 150 to
190 °C, a typical value being 170 °C. The device is
automatically restarted when the chip temperature
falls of about 15°C below shut-down temperature.
- STATUS FEEDBACK: in the case of an
overtemperature fault condition (Tj > T
device tries to sink a diagnostic current Igf thro ug h
jsh
), the
the INPUT pin in order to indicate fault condition. If
driven from a l ow impedance sou rce, this curre nt
may be used in orde r to warn the contr ol circ uit of
a device shut down. If the drive impeda nc e is h i gh
enough so that the INPUT pin dri ver is not abl e to
supply the current Igf, the INPUT pin will fall to 0V.
This will not however affect the device
operation: no requirement is put on the current
capability of t he IN PUT pin dr ive r e xcep t t o b e
able to supply the normal operation drive
current I
ISS
.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
5/14
1
Page 6
VNS1NV04D
Figure 1: Switching Time Test Circuit for Resistive Load
I
D
90%
V
D
R
gen
V
gen
t
r
t
V
gen
d(on)t
10%
Figure 2: Test Circu it for Diode Recovery Times
A
D
I
OMNIFET
S
330Ω
B
R
FAST
DIODE
gen
d(off)
I
t
f
A
B
OMNIFET
L=100uH
D
t
t
V
DD
6/14
1
V
gen
S
8.5 Ω
Page 7
VNS1NV04D
Figure 3: Unclamped Inductive Load Test Circuits
R
V
IN
P
GEN
W
Figure 5: Input Charge Test Circuit
IN
V
GEN
Figure 4: Unclamped Inductive Waveforms
ND8003
7/14
1
1
Page 8
VNS1NV04D
Source-Drain Diode Forward Characteristics
Vsd (mV)
1000
950
Vin=0V
900
850
800
750
700
0 2 4 6 8 101214
Id (A)
Derating Curve
Voltage
Static Drain Source On Resistance
Rds(on) (ohms)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Vin=2.5V
00.050.10.150.20.250.3
Tj=-40ºC
Tj=25ºC
Tj=150ºC
Id(A)
Static Drain-Source On resistance Vs. Input
Voltage
Rds(on) (mohms)
500
450
400
350
300
250
200
150
100
50
0
33.544.555.566.57
Id=0.5A
Tj=150ºC
Tj=25ºC
Tj=-40ºC
Vin(V)
TransconductanceStatic Drain-Source On resistance Vs. Input
Rds(on) (mohms)
500
Tj=150ºC
450
400
350
300
Tj=25ºC
250
200
Tj=-40ºC
150
100
50
0
33.544.555.566.5
Vin(V)
8/14
1111
Id=1.5A
Id=1A
Id=1.5A
Id=1A
Id=1.5A
Id=1A
Gfs (S)
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Vds=13V
00.250.50.7511.251.51.752
Tj=-40ºC
Tj=25º C
Tj=150ºC
Id(A)
Page 9
VNS1NV04D
Static Drain-Source On Resistance Vs. Id
Rds(on) (mohms)
500
450
400
350
300
250
200
150
100
50
0
00.250.50.7511.251.51.752
Tj=150ºC
Tj=25ºC
Tj=-40ºC
Vin=3.5V
Vin=5V
Vin=3.5V
Vin=5V
Vin=3.5V
Vin=5V
Id(A)
Turn On Current Slope
di/dt(A/us)
6
5
4
Vin=5V
Vdd=15V
Id=1.5A
Transfer Characteristics
Idon(A)
2.25
2
Vds=13.5V
1.75
1.5
1.25
1
Tj=150ºC
0.75
0.5
0.25
0
1.5
1.7522.25
2.5
2.7533.25
Turn On Current Slope
di/dt(A/us)
1.4
1.2
1
Tj=-40ºC
Vin(V)
3.5
3.7544.25
Vin=3.5V
Vdd=15V
Id=1.5A
Tj=25ºC
4.5
4.75
5
3
2
1
0
05001000150020002500
Rg(ohm)
Input Voltage Vs. Input Charge
Vin (V)
6
5
4
3
2
1
0
Vds=12V
Id=0.5A
0123456
Qg (nC)
0.8
0.6
0.4
0.2
05001000150020002500
Rg(ohm)
Turn off drain source voltage slope
dv/dt(V/us)
350
300
250
200
150
100
50
0
05001000150020002500
Rg(ohm)
Vin=5V
Vdd=15V
Id=0.5A
9/14
1
11
Page 10
VNS1NV04D
Turn Off Drain-Source Voltage Slope
dv/dt(V/us)
350
300
250
Vin=3.5V
Vdd=15V
Id=0.5A
200
150
100
50
0
05001000150020002500
Rg(ohm)
Switching Time Resistive Load
t(us)
2
1.75
1.5
1.25
0.75
0.5
0.25
Vdd=15V
Id=0.5A
Vin=5V
1
0
0 250 500 750 1000 1250 1500 1750 2000 2250 2500
td(off)
Rg(ohm)
Output Characteristics
tr
tf
td(on)
Capacitance Variations
C(pF)
225
200
175
150
125
100
75
50
05101520253035
f=1MHz
Vin=0V
Vds(V)
Switching Time Resistive Load
t(ns)
550
500
450
400
350
300
250
200
150
100
50
0
3.253.53.7544.254.54.7555.25
tr
td(on)
Vdd=15V
Id=0.5A
Rg=330ohm
td(off)
tf
Vin(V)
Normalized On Resistance Vs. Temperature
10/14
1111
ID(A)
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0123456789101112
Vin=5.5V
Vin=4.5V
Vin=3.5V
Vin=3V
VDS(V)
Rds(on) (mOhm)
2.25
2
1.75
1.5
1.25
0.75
0.5
Vin=5V
Id=0.5A
1
-50 -250255075 100 125 150 175
Tc (ºC)
Page 11
VNS1NV04D
Normalized Input Threshold Voltage Vs.
Temperature
Information furnish ed is believed to be accurate and r eliable. However, STMicroel ec tronics assum es no responsibility for t he consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelect r onics. Specif ic ations mentioned in this publication are
subject to c hange withou t notice. This publication supersed es and replace s all informa tion previous ly s upplied. ST M icroelect r on ics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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The ST logo is a trademark of STMicroele c tronics
2003 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
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