Datasheet VND92013TR, VND920 Datasheet (SGS Thomson Microelectronics)

®

VND920

DOUBLE CHANNEL HIGH SIDE SOLID STATE RELAY

TYPE R

VND920 16mΩ 35 A (*) 36 V

(*) Per channel with all the output pins connected to the PCB.

■ CMOS COMPATIBLE INPUT

■ PROPORTIONAL LOAD CURRENT SENSE

■ SHORTED LOAD PROTECTION

■ UNDERVOLTAGE AND OVERVOLTAGE

DS(on)

I

OUT

V

CC

SHUTDOWN

■ OVERVOLTAGE CLAMP

■ THERMAL SHUTDOWN

■ CURRENT LIMITATION

■ PROTECTION AGAI NST LOSS OF GROUND

AND LOSS OF V

■ VERY LOW ST AND -BY P OWER DI SSIPA TION

■ REVERSE BA TTERY PROTECTION ( *)

CC

DESCRIPTION

The VND920 is a double chip device made by
using STMicroelectronics VIPower M0-3
Technology, intended fo r driving any kind of loa d
with one side connected to ground. Active VCC pin

CONNECTION DIAGRAM (TO P VI EW)

SO-28 (DOUBLE ISLAND)

ORDER CODES

PACKAGE TUBE T&R

SO-28 VND920 VND92013TR

voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown a nd automatic
restart prote ct the device against over load. Built­in analog cur rent sense output deli vers a current
proportional to the load current. Device
automatically turns off in case of ground pin
disconnection.

V

1

CC

GND 1
INPUT 1
CURRENT SENSE 1
NC
NC

V

1

CC

V

2

CC

GND 2
INPUT 2

CURRENT SENSE 2
NC
NC

2

V

CC

(*) See application schematic at page 10

October 20 02 1/18

1

14 15

28

V
OUTPUT 1
OUTPUT 1

OUTPUT 1

OUTPUT 1

OUTPUT 1

OUTPUT 1

OUTPUT 2
OUTPUT 2
OUTPUT 2

OUTPUT 2

OUTPUT 2

OUTPUT 2

V

CC

CC

1

2

1

VND920

BLOCK DIAGRAM

V

1

CC

GND 1

INPUT 1

GND 2

V

CC

CLAMP

OVERTEMPERATURE

DETECTION

V

CC

CLAMP

LOGIC

OVERVO LTAGE

DETECTION

UNDERVOLTAGE

DETECTION

DRIVER

CURRENT LIMITER

I

OVERVOLTAGE

DETECTION

UNDERVOLTAGE

DETECTION

Power CLAMP

OUTPUT 1

VDS LIMITER

OUT CURRENT

Power CLAMP

K

SENSE 1

V

CC

2

2/18

INPUT 2

LOGIC

OVERTEMPERATURE

DETECTION

DRIVER

CURRENT LIMITER

VDS LIMITER

I

OUT CURRENT

K

OUTPUT 2

SENSE 2

VND920

ABSOLUTE MAXIMUM RATI NG (Per each channel)

Symbol Parameter Value Unit

tot

DC Supply Voltage 41 V
Reverse DC Supply Voltage - 0.3 V

CC

DC Reverse Ground Pin Current - 200 mA
DC Output Current Internally Limited A
Reverse DC Output Current - 21 A
DC Input Curr ent +/- 10 mA
Current Sense Maximum Voltage -3

+15

Electros tatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)

- INPUT

- CURRENT SENSE

- OUTPU T

- V

CC

Maximum Switching Energy
(L=0.25m H; R

=0Ω; V

L

=13.5V ; T

bat

=150ºC ; IL=45A)

jstart

4000
2000
5000
5000

355 mJ

Powe r Dissipation Tl≤25°C 6.25 (**) W
Junction Operating Temperature Internally limited °C

j

Case Operating Temperature - 40 to 150 °C

c

Storage Temperature - 55 to 150 °C

V

CC

- V

- I

GND

I

OUT

- I

OUT

I

IN

V

CSENSE

V

ESD

E

MAX

P

T

T

T

STG

(**) Per island

V
V

V
V
V
V

CURRENT AND VOLTAGE CONVENTIONS

I

S1

V

CC1

I

IN1

V

IN1

I

IN2

V

IN2

INPUT1

INPUT2

GROUND1

I

GND1

V

CC2

OUTPUT1

OUTPUT2

GROUND2

V

CC1

CURRENT SENSE 1

CURRENT SENSE 2

I

GND2

I

OUT1

I

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

V

OUT2

I

S2

SENSE1

V

OUT1

V

CC2

3/18

VND920

THERMAL DATA (Per island)

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

R

thj-amb

(*) When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at leas t 35µ m thick) connected to all VCC pins.

Horizontal mounting and no artificial air flow.

ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)
(Per island)
POWER

Symbol Parameter Test Conditions Min Typ Max Unit

V

V

USD

V

R

V

clamp

I

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

Thermal R esistance Junction-lead 20 °C/W
Thermal Resistance Ju nction-ambient (one chi p ON) 55 (*) °C/W
Thermal Resistance Ju nction-ambient (two chi ps ON) 42 (*) °C/W

CC

Opera ting S u pply Vol tag e 5.5 13 36 V
Undervoltage Shut -down 3 4 5.5 V

OV

ON

Overv oltage Shut -down 36 V

=10A; Tj =25°C

I

On State Resistance

OUT

I

=10A

OUT

I

=3A; VCC=6V

OUT

Clamp Voltage ICC=20mA (See note 1) 41 48 55 V

Off Stat e; V

Supply Current

S

Off Stat e; V
T

=25°C

j

On State; V
R

SENSE

Off Stat e O utput Current VIN=V

OUT

Off Stat e O utput Current VIN=0V; V
Off Stat e O utput Current VIN=V
Off Stat e O utput Current VIN=V

OUT
OUT

=13V; VIN=V

CC

=13V; VIN=V

CC

=13V; VIN=5V; I

CC

=3.9KΩ

=0V 0 50 µA

=3.5V -75 0 µA

OUT

=0V; VCC=13V; Tj =125°C 5 µA
=0V; VCC=13V; Tj =25°C 3 µA

OUT
OUT

=0V
=0V;

OUT

=0A;

10

10

16
32
55

25

20

5

mΩ
mΩ
mΩ

µA

µA

mA

SWITCHING (VCC=13V)

Symbol Parameter Test Conditions Min Typ Max Unit

t

d(on)

t

d(off)

Turn-on Delay Time RL=1.3Ω (see figur e 2) 50 µs
Turn-off Delay Time RL=1.3Ω (see figur e 2) 50 µs

See

dV

/dt

OUT

Turn-on Voltage Slope RL=1.3Ω (see figure 2)

(on)

relative

diagram

See

/dt

dV

OUT

Turn-off Voltage Slope RL=1.3Ω (see figure 2)

(off)

relative

diagram

LOGIC INPUT

Symbol Parameter Test Conditions Min Typ Max Unit

V

I

V

I

V

I(hyst)

V

Note 1: V

4/18

IL

IH

ICL

Input Low Level 1.25 V

IL

Low Level Input Current VIN=1.25V 1 µA
Input High Level 3.25 V

IH

High Level Input Current VIN=3.25V 10 µA
Input Hysteresis Voltage 0.5 V

Input Cl am p Voltage

and VOV are correlat ed. Typical dif ference is 5V.

clamp

=1mA

I

IN

I

=-1mA

IN

66.8

-0.7

8V

V/µs

V/µs

V

1

VND920

ELECTRICAL CHARACTERISTICS (continued)

CURRENT SENSE ( 9V ≤

Symbol Parameter Test Conditions Min Typ Max Unit

K

dK1/K1Current Se nse Ratio Drift

K

dK2/K2Current Se nse Ratio Drift

K

dK3/K3Current Se nse Ratio Drift

I

SENSEO

V

SENSE

V

SENSEH

R

VSENSEH

t

DSENSE

I

1

OUT/ISENSE

I

2

OUT/ISENSE

I

3

OUT/ISENSE

Analog Sense Leakage
Current

Max Analog Sense Output
Voltage

Sense Voltage in
Overtemperature
conditions

Analog Sense Output
Impedance in
Overtemperature
Condition

Current sense delay
response

V

≤ 16V) (See Fig.1)

CC

I

OUT

T

= -40°C...150°C

j

I

OUT

T

= -40°C...+150°C

j

I

OUT

T

=25°C... 150°C

j

I

OUT

T

=-40°C.. .+150°C

j

I

OUT

T

=25°C... 150°C

j

I

OUT

T

=-40°C.. .+150°C

j

V

CC

T

=-40°C.. .+150°C

j

V

CC

V

CC

VCC=13V; R

VCC=13V; Tj>T

to 90% I

=1A; V

SENSE

=1A; V

SENSE

=10A; V

=10A; V

=30A; V

=30A; V

=6...16V; I

=5.5V; I

OUT

>8V; I

OUT

SENSE

=0.5V;

=0.5V;

=4V; Tj=-40°C

SENSE

=4V;

SENSE

=4V; Tj=-40°C

SENSE

=4V;

SENSE

=0A;V

OUT

=5A; R

=10A; R

SENSE

SENSE

=3.9KΩ 5.5 V

; All channels open 400 Ω

TSD

SENSE

SENSE

=0V;

=10KΩ

=10KΩ

3300 4400 6000

-10 +10 %

4200
4400

4900
4900

6000
5750

-8 +8 %

4200
4400

4900
4900

5500
5250

-6 +6 %

010µA

2
4

(see note 2) 500 µs

V
V

PROTECTIONS

Symbol Parameter Test Conditio ns Min Typ Max Unit

T

TSD

T

T

hyst

I

lim

V

demag

V

ON

Note 2: current sense signal delay after positive input sl ope

Note: Sense pin doesn’t have to be left floating.

Shut-down Temperature 150 175 200 °C
Reset Temp erature 135 °C

R

Ther ma l Hy steresi s 7 15 °C
DC Short Circuit Current
Turn-off Output Clamp

Voltage
Output Voltage Drop

Limitation

=13V

V

CC

5V<V
I

I

<36V

CC

=2A; VIN=0V; L=6mH VCC-41 VCC-48 VCC-55 V

OUT

=1A; Tj=-40°C....+150°C 50 mV

OUT

30 45 75

75

2

A
A

5/18

VND920

Figure 1: I

I

OUT/ISENSE

OUT/ISENSE

6500

6000

5500

versus I

OUT

max.Tj=25 ... 15 0 °C

5000

min.Tj=25...150°C

4500

4000

3500

3000

02468101214161820222426283032

I

(A)

OUT

Figure 2: Switching Characteristics (Resistive load RL=1.3Ω)

max.Tj=- 40°C

typical value

min.Tj=- 4 0° C

V

OUT

dV

OUT

I

SENSE

INPUT

/dt

(on)

t

d(on)

80%

90%

t

DSENSE

90%

dV

/dt

OUT

(off)

t

r

10%

t

f

t

t

t

d(off)

t

6/18

Switching time Waveforms

V

OUT

/dt

dV

OUT

(on)

80%

90%

dV

OUT

/dt

VND920

(off)

d(off)

t

f

t

r

V

IN

t

d(on)

10%

t

TRUTH TABLE (Per each channel)

CONDITIONS INPUT OUTPUT CURRENT SENS E

Normal operation

Overtem perature

Undervol tage

Overvoltage

L
H
L
H
L
H
L
H
L

Short circuit to GND

H
H

Short circuit to V

CC

L
H

Negative output volt age clamp L L 0

L

H

Nominal

L
L

V
L
L
L
L
L
L
L

(T
(T

j<TTSD
j>TTSD

H
H

< Nominal

0

0

SENSEH

0
0
0
0

0
) 0
) V

SENSEH

0

t

t

7/18

VND920

ELECTRICAL TRANS IENT REQUIREMENTS

ISO T/R 7637/1

Test Pulse

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -2 5 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

ISO T/R 7637/1

Test Pulse

1CCCC

2CCCC

3aCCCC
3bCCCC

4CCCC

5CEEE

CLASS CONTENTS

C All fu nctions of the device are performed as designed after exposure to disturbance.
E One or more functions of the device is not performed as designed after expos ure to disturbance

and cann ot be returne d to proper operation without replacing the device.

I II III IV Delays and

I II III IV

TEST LEVELS

TEST LEVELS RESULTS

Impedance

Ω

Ω

8/18

Figure 3: W aveforms

INPUTn
LOAD CURRENTn
SENSEn

V

CCn

INPUTn

LOAD CURREN Tn
SENSEn

V

CCn

INPUTn
LOAD CURRENTn
SENSEn

V

USD

V

VCC > V

VND920

NORMAL OPERATION

UNDERVOLTAGE

V

USDhyst

OVERVOLT AGE

OV

V

USD

OVhyst

INPUTn

LOAD CURRENTn
LOAD VOLTAGEn
SENSEn

INPUTn

LOAD VOLTAGEn
LOAD CURRENTn

SENSEn

T

j

INPUTn
LOAD CURRENTn
SENSEn

SHORT TO GROUND

SHORT TO V

<Nominal

T

TSD

T

R

OVERTEMPERATURE

CC

<Nominal

I

SENSE

=

V

SENSEH

R

SENSE

9/18

VND920

APPLICATION SCHEMATIC

+5V

R

prot

R

prot

R

prot

µ

C

R

prot

INPUT1

C. SENSE 1

INPUT2

C. SENSE 2

V

CC1

V

CC2

OUTPUT1

OUTPUT2

D

ld

R

SENSE1,2

GND PROTECTION NETWORK AGAINST
REVERSE BATTERY

Soluti on 1: Resistor in the ground line (R
can be us ed with any type of load.

The fo llowin g is an indica tion on how to dim ension the

resistor.

R

GND

where -I
be found in the absolute maximum rating section of the

1) R

2) R

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC re vers e grou nd pi n cu rren t an d can

GND

S(on)ma x

)

GND

).

device’s datasheet.
Power Dissipation in R

battery situations) is:

= (-VCC)2/R

P

D

GND

(when VCC<0: during reverse

GND

This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calcul ated with form ula (1) wher e I
sum of the maximum on-state currents of the different

S(on)max

devices.
Please note that if the microprocessor ground is not

common with the device ground then the R
produce a shift (I
and the status output values. This shift will vary

S(on)max

* R

) in the input thresholds

GND

depend ing on how many devi ces are ON in the c ase of
several high side d rivers shar ing the same R

If the calculated power dissipation leads to a large resistor
or several devices hav e to share the sa me resisto r then
the ST suggests to utiliz e Solu tio n 2 (se e below ).

Solution 2:
A resistor (R

D

GND

A diode (D

=1kΩ) sh ould b e insert ed in paral lel to

GND

if the device will be driving an inductive load.

) in the gr ound line.

GND

only). This

GND

becomes t he

GND

.

GND

will

GND

GND2

D

GND

GND1

V

GND

R

This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of

j

the ground network wi ll produce a shift (

600mV) in t he
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resisto r network.

LOAD DUMP PROTECTION

Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subject to transients on
the VCC line that are grea ter tha n the ones sh own in the
ISO T/R 7637/1 table.

C I/Os PROTECTION:

µ

If a ground protection network is used and negative
transients are present on the VCC line, th e con trol p ins will
be pulled negative. ST suggests to insert a resistor (R
in lin e to prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the
leakage c urrent of µC an d the current required by the
HSD I/Os ( Input le vels comp atibilit y) wi th the lat ch-up li mit
of µC I/Os.

≤ R

-V

CCpeak/Ilatchup

prot

≤ (V

OHµC-VIH-VGND

Calculation exampl e:

CCpeak

prot

= - 100V an d I

≤ 65kΩ.

For V
5kΩ ≤ R

Recommended R

value is 10kΩ.

prot

latchup

≥ 20mA; V

OHµC

) / I

prot

IHmax

≥ 4.5V

)

10/18

1

VND920

Off State Output Current

IL(off1) (u A)

9

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 17 5

Tc (°C)

Input Clamp Voltage

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2
6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

High Level Input Current

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Input High Level

Vih (V)

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75 100 125 150 175

Input Hysteresis VoltageInput Low Level

Tc (°C)

Tc (°C)

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

11/18

VND920

Overvoltage Shutdown

I

LIM

Vs T

case

Vov (V)

50

48

46

44

42

40

38

36

34

32
30

-50 -25 0 25 50 75 100 125 150 175

Ilim (A)

100

90

80

70

60

50

40

30

20

10

Vcc=13 V

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Turn-on Voltage Slope Turn-off Voltage Slope

dVout/dt(on) (V/ms)

700

650

600

550

500

450

400

350

300

250

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Rl=1.3Ohm

Tc (ºC)

dVout/dt(off) (V/ms)

550
500
450
400
350
300
250
200
150
100

50

Vcc=13V

Rl=1.3Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Tc (°C)

On State Resistance Vs T

case

Ron (mOhm)

50

45

40

35

30

25

20

15

10

5
0

-50 -25 0 25 50 75 100 125 150 175

Iout=10A

Vcc=8V; 36V

Tc (ºC)

12/18

On State Resistance Vs V

CC

Ron (mOhm)

50

45

40

35

30

25

20

15

10

5
0

5 10152025303540

Tc= 150ºC

Tc= 25ºC

Tc= - 40ºC

Vcc (V)

Maximum turn off current versus load inductance

LMAX (A)

I

100

10

VND920

A

B

C

1

0.01 0.1 1 10 100

A = Single Pulse at T

B= Repetitive pulse at T
C= Repetitive Pulse at T

Conditions:
VCC=13.5V

Values are generated with RL=0Ω
In case of repetitive pulses, T

the temperature specified above for curves B and C.

VIN, I

L

=150ºC

Jstart

=100ºC

Jstart

=125ºC

Jstart

jstart

Demagnetization

(at beginning of each demagnetization) of every pulse must not exceed

L(mH)

Demagnetization

Demagnetization

t

13/18

SO-28 DOUBLE ISLAND THERMAL DAT A

SO-28 Double island PC Board

VND920

Layout condition of Rth and Zth measur ements (PCB FR4 area= 58mm x 58mm, PCB thi ckness=2 m m ,
Cu thickness=35µm, Copper areas: 0.5cm

2

, 3cm2, 6cm2).

Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 T

ON OFF R

OFF ON R

ON ON R
ON ON (R

R

= Thermal resistance Junction to Ambient with one chip ON

thA

= Thermal resistance Junction to Ambient with both chips ON and P

R

thB

R

= Mutual thermal resistance

thC

R

Vs PCB copper area in open box free air condition

thj-amb

thA
thC
thB

thA

x P

x P

x (P

x P

dchip1

dchip2

dchip1
dchip1

+ T
+ T

+ P
) + R

jchip1

amb
amb

dchip2

thC

) + T

x P

amb

dchip2

+ T

amb(RthA

R

thC

R

thA

R

thB

RTHj_am b

(°C/W)

70
60
50
40
30
20

x P

dchip1

x P

dchip2

x (P

dchip1

x P

dchip2

dchip1=Pdchip2

T

+ T
+ T

+ P

) + R

jchip2

amb
amb

dchip2

thC

x P

) + T

dchip1

amb

+ T

R

R

R

P

ambPdchip1≠Pdchip2

thA

thB

thC

Note

dchi p1=Pdchi p2

10

01234567

PCB Cu heatsink area (cm^2)/island

14/18

VND920

SO-28 Thermal Impedance Junction Ambient Single Pulse

Zth(°C/W)

100

10

1

0.1

0,5 cm^2/island

3 cm^2/island

6 cm^2/island

One channel ON
Two channels ON

One channel ON

on same ch i p

Two channels ON

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000

time(s)

Thermal fitting model of a two channels HSD in
SO-28

Pulse calculation formula

Z

THδ

where

RTHδ Z

δ tpT⁄=

Thermal Parameter

Area/island (cm2)0.56

Tj_1

Pd1

Tj_2

C1

C1 C2

R1

Pd2

R2

C3 C4

R3R1 R6R5R2

T_amb

C5 C6C2

R4

R1= (°C/W) 0.02
R2= (°C /W ) 0.1
R3= (°C /W ) 2.2
R4= (°C /W ) 11
R5= (°C /W ) 15
R6= (°C /W ) 30 1 3
C1= (W.s/° C ) 0.0015
C2= (W.s/°C) 7.00E-03
C3= (W.s/°C) 1.50E-02
C4= (W.s/°C) 0.2
C5= (W.s/°C) 1.5
C6= (W.s/°C) 5 8

THtp

1 δ–()+⋅=

15/18

SO-28 MECHANICAL DATA

VND920

DIM.

A 2.65 0.104

a1 0.10 0.30 0.004 0.012

b 0.35 0.49 0.013 0.019

b1 0.23 0.32 0.009 0.012

C 0.50 0.020

c1 45 (typ .)

D 17.7 18.1 0.697 0.71 3
E 10.00 10.65 0.393 0.419
e 1.27 0.050

e3 16.51 0.650

F 7.40 7.60 0.291 0.299
L 0.40 1.27 0.016 0.050
S8 (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inc h

16/18

VND920

SO-28 TUBE SHIPMENT (no suffix)

Base Q.ty 28
Bulk Q.ty 700

C

B

Tube length (± 0.5) 532

A 3.5
B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

A

TAPE AND REEL SHIPMENT (suffix “13TR”)

REEL DIMENSIONS

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13

F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

TAPE DIMENSIONS

According to Electronic Indust ries Association
(EIA) S tandard 481 re v. A, Feb 1 986

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D ( ± 0.1/ -0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

17/18

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

VND920

Information furnished is believed to be accurate and reliable. Ho wev er, STMicroelectr onics assumes no r es ponsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent r ights of STMicr oelectronics . Specifications mentioned in this publication are
subject to c hange withou t notice. This publicatio n s upersedes an d r eplaces all information previously supplied. STM icroelectr on ics product s
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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18/18