Datasheet VND830P-E Datasheet (ST)

Features

Type R

VND830P-E 60 mΩ

1. Per each channel.

DS(on)

(1)

I

OUT

6A

(1)

V

CC

36 V

VND830P-E

Double channel high-side driver

■ ECOPACK

■ Automotive Grade: compliance with AEC

®

: lead free and RoHS compliant

guidelines

■ Very low standby current

■ CMOS compatible input

■ On-state open-load detection

■ Off-state open-load detection

■ Thermal shutdown protection and diagnosis

■ Undervoltage shutdown

■ Overvoltage clamp

■ Output stuck to V

■ Load current limitation

■ Reverse battery protection

■ Electrostatic discharge protection

detection

CC

Table 1. Device summary

Description

The VND830P-E is a monolithic device made by
using STMicroelectronics™ VIPower™ M0-3
technology, intended for driving any kind of load
with one side connected to ground.

Active V
against low energy spikes (see ISO7637 transient
compatibility table).

Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects
open-load condition both is on-state and off-state.
Output shorted to V
Device automatically turns-off in case of ground
pin disconnection.

pin voltage clamp protects the devices

CC

is detected in the off-state.

CC

Order codes

Package

Tube Tape and reel

SO-16L VND830P-E VND830PTR-E

September 2010 Doc ID 17546 Rev 2 1/27

www.st.com

1

VND830P-E Contents

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16

3.1.2 Solution 2: a diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

) in the ground line . . . . . . . . . . . . . . . . . . . . 17

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 SO-16L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 SO-16L packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 17546 Rev 2 2/27

VND830P-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. V

Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 9. Switching (V

Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 13. Electrical transient requirements on V
Table 14. Electrical transient requirements on V
Table 15. Electrical transient requirements on V

Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17. SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CC

= 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

Doc ID 17546 Rev 2 3/27

VND830P-E List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. I

Figure 14. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16. On-state resistance vs
Figure 17. On-state resistance vs V

Figure 18. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 19. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 20. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 21. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 23. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 24. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 25. SO-16L maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 26. SO-16L PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 27. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20

Figure 28. SO-16 L thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 29. Thermal fitting model of a quad channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 30. SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31. SO-16L tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 32. Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

LIM

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Tcase

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Doc ID 17546 Rev 2 4/27

VND830P-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

cc

V

GND

INPUT1

STATUS1

INPUT2

STATUS2

cc

CLAMP

OVERT EMP. 1

OVERT EMP. 2

LOGIC

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPEN-LOAD ON 1

OPEN-LOAD OFF 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPEN-LOAD ON 2

OPEN-LOAD OFF 2

OUTPUT1

OUTPUT2

Figure 2. Configuration diagram (top view)

V

CC

1

16

N.C.

GND

INPUT 1

STATUS 1

STATUS 2

INPUT 2

V

CC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

Floating X X X X

To ground - X -

8

9

V

CC

OUTPUT 1

OUTPUT 1

OUTPUT 1

OUTPUT 2

OUTPUT 2

OUTPUT 2

V

CC

Through 10 KΩ

resistor

Doc ID 17546 Rev 2 5/27

VND830P-E Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Tabl e 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

- V

- I

I

- I

I

STAT

V

E

P

T

CC

CC

GND

OUT

OUT

I

IN

ESD

MAX

tot

T

j

T

c

stg

DC supply voltage 41 V

Reverse DC supply voltage - 0.3 V

DC reverse ground pin current - 200 mA

DC output current Internally limited A

Reverse DC output current - 6 A

DC input current +/- 10 mA

DC status current +/- 10 mA

Electrostatic discharge (Human Body Model: R=1.5 KΩ;
C = 100 pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

4000
4000
5000
5000

V
V
V
V

Maximum switching energy
(L = 1.8 mH; R

= 9 A)

I

L

= 0 Ω; V

L

Power dissipation T

= 13.5 V; T

bat

=25°C 8.3 W

lead

= 150 °C;

jstart

102 mJ

Junction operating temperature Internally limited °C

Case operating temperature - 40 to 150 °C

Storage temperature - 55 to 150 °C

Doc ID 17546 Rev 2 6/27

VND830P-E Electrical specifications

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected to all VCC pins.
Horizontal mounting and no artificial air flow.

2. When mounted on a standard single-sided FR-4 board with 6 cm
Horizontal mounting and no artificial air flow.

Thermal resistance junction-lead (max) 15 °C/W

Thermal resistance junction-ambient (max) 65

2

of Cu (at least 35 µm thick) connected to all VCC pins.

(1)

48

(2)

°C/W

2.3 Electrical characteristics

Values specified in this section are for 8 V < V
otherwise stated.

(Per each channel)

Figure 3. Current and voltage conventions

I

IN1

INPUT 1

I

V

IN1

STAT1

STATUS 1

V

STAT1

I

IN2

INPUT 2

I

V

STAT2

IN2

STATUS 2

V

STAT2

< 36 V; -40 °C < Tj < 150 °C, unless

CC

(1)

V

F1

V

CC

I

OUT1

OUTPUT 1

V

OUT1

I

OUT2

OUTPUT 2

V

OUT2

GND

I

GND

I

S

V

CC

1. VFn = V

Table 5. Power output

CCn

- V

during reverse battery condition.

OUTn

Symbol Parameter Test conditions Min. Typ. Max. Unit

(1)

Operating supply voltage 5.5 13 36 V

(1)

Undervoltage shutdown 3 4 5.5 V

(1)

Overvoltage shutdown 36 V

I

= 2 A; Tj = 25 °C

On-state resistance

ON

OUT

I

OUT

= 2 A; V

CC

> 8 V

60

120mΩmΩ

V

V

USD

V

R

CC

OV

Doc ID 17546 Rev 2 7/27

VND830P-E Electrical specifications

Table 5. Power output (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

(1)

I

S

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

1. Per device.

Table 6. Protections

Supply current

Off-state output current V

Off-state output current V

Off-state output current

Off-state output current

(1)

Off-state; V

= V

V

IN

Off-state; V

= V

V

IN

On-state; V

= 5 V; I

V

IN

= V

IN

= 0 V; V

IN

V

= V

IN

= 125 °C

T

j

V

= V

IN

=25 °C

T

j

= 13 V;

CC

= 0 V

OUT

= 13 V;

CC

= 0 V; Tj = 25°C

OUT

= 13 V;

CC

= 0 A

OUT

= 0 V 0 50 µA

OUT

= 3.5 V -75 0 µA

OUT

OUT

OUT

= 0 V; V

= 0 V; V

CC

CC

= 13 V;

= 13 V;

12 40 µA

12 25 µA

57mA

5µA

3µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

T

Shutdown temperature 150 175 200 °C

TSD

Reset temperature 135 °C

T

R

Thermal hysteresis 7 15 °C

hyst

Status delay in overload

SDL

conditions

T

> T

j

TSD

20 µs

V

= 13 V 6 9 15 A

I

V

demag

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

Tabl e 7. VCC - output diode

Current limitation

lim

Turn-off output clamp
voltage

CC

5.5 V < V

I

OUT

< 36 V 15 A

CC

= 2 A; L = 6 mH V

-41 V

CC

CC

-48 V

-55 V

CC

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Forward on voltage -I

F

Table 8. Status pin

=1.3 A; Tj=150°C - - 0.6 V

OUT

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

STAT

I

LSTAT

C

STAT

Status low output voltage I

= 1.6 mA 0.5 V

STAT

Status leakage current Normal operation; V

Status pin input capacitance Normal operation; V

= 5 V 10 µA

STAT

= 5 V 100 pF

STAT

Doc ID 17546 Rev 2 8/27

VND830P-E Electrical specifications

Table 8. Status pin (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

= 1 mA 6 6.8 8 V

V

Table 9. Switching (V

Status clamp voltage

SCL

CC

= 13 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

dV/dt

dV/dt

Table 10. Open-load detection

Turn-on delay time

Turn-off delay time

Turn-on voltage slope

(on)

Turn-off voltage slope

(off)

STAT

I

= - 1 mA -0.7 V

STAT

= 6.5 Ω from VIN rising

R

L

edge to V

R

= 6.5 Ω from VIN falling

L

edge to V

= 6.5 Ω from V

R

L

to V

OUT

= 6.5 Ω from V

R

L

to V

OUT

= 1.3 V

OUT

= 11.7 V

OUT

= 10.4 V

= 1.3 V

OUT

OUT

= 1.3 V

= 11.7 V

-30-µs

-30-µs

See

-

-

Figure 14

See

Figure 15

-V/µs

-V/µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

t

DOL(on)

V

t

DOL(off)

Table 11. Logic input

Open-load on-state detection

OL

threshold

Open-load on-state detection
delay

Open-load off-state voltage

OL

detection threshold

Open-load detection delay at
turn-off

= 5 V 50 100 200 mA

V

IN

= 0 A 200 µs

I

OUT

V

= 0 V 1.5 2.5 3.5 V

IN

1000 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

V

V

Input low level 1.25 V

IL

I

Low level input current V

IL

Input high level 3.25 V

IH

High level input current V

IH

Input hysteresis voltage 0.5 V

hyst

Input clamp voltage

ICL

= 1.25 V 1 µA

IN

= 3.25 V 10 µA

IN

I

= 1 mA 6 6.8 8 V

IN

= -1 mA -0.7 V

I

IN

Doc ID 17546 Rev 2 9/27

VND830P-E Electrical specifications

Figure 4. Switching time waveforms

Table 12. Truth table

Conditions Input Output Sense

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

OL

OL

L

H

L
H
H

L
H

L
H

L
H

L
H

L
H

L

H

L
X
X

L

L

L

L

L

L

H
H

L
H

(T
(T

< T

j

> T

j

TSD

TSD

H
H

H
) H
) L

H

L

X

X

H

H

L

H

H

L

Doc ID 17546 Rev 2 10/27

VND830P-E Electrical specifications

Table 13. Electrical transient requirements on V

ISO T/R

7637/1

test pulse

I II III IV Delays and impedance

1 -25 V -50 V -75 V -100 V

2 +25 V +50 V +75 V +100 V

3a -25 V -50 V -100 V -150 V

3b +25 V +50 V +75 V +100 V 0.1 µs, 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω

5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω

Table 14. Electrical transient requirements on VCC pin (part 2)

Test levels

pin (part 1)

CC

2ms, 10Ω

0.2 ms, 10 Ω

0.1 µs, 50 Ω

ISO T/R

Test levels results

7637/1

test pulse

I II III IV

1 CCCC

2 CCCC

3a CCCC

3b CCCC

4 CCCC

5CEEE

Table 15. Electrical transient requirements on VCC pin (part 3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to
disturbance.

One or more functions of the device is not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.

Doc ID 17546 Rev 2 11/27

VND830P-E Electrical specifications

Figure 5. Waveforms

NORMAL OPERATION

INPUT

n

OUTPUT VOLTAGE

STATUS

n

V

CC

INPUT

n

OUTPUT VOLTAGE

STATUS

V

CC

INPUT

n

OUTPUT VOLTAGE

STATUS

n

n

n

n

V

USD

VCC<V

UNDERVOLTAGE

OVERVOLTAGE

OV

V

USDhyst

undefined

V

> V

CC

OV

INPUT

n

OUTPUT VOLTAGE

STATUS

n

INPUT

n

OUTPUT VOLTAGE

STATUS

n

T

j

INPUT

n

OUTPUT CURRENT

STATUS

n

OPEN-LOAD with external pull-up

V

> V

n

V

OL

OUT

OL

OPEN-LOAD without external pull-up

n

T

TSD

T

R

n

OVERTEMPERATURE

Doc ID 17546 Rev 2 12/27

VND830P-E Electrical specifications

2.4 Electrical characteristics curves

Figure 6. Off-state output current Figure 7. High level input current

IL(off1) (uA)

2.5

2.25

2

1.75

1.5

1.25

0.75

0.5

0.25

0

Figure 8. Input clamp voltage Figure 9. Status leakage current

Off state
Vcc=36V

Vin=Vout=0V

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Ilstat (uA)

0.05

0.04

Vstat=5V

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 10. Status low output voltage Figure 11. Status clamp voltage

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vscl (V)

8

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Doc ID 17546 Rev 2 13/27

VND830P-E Electrical specifications

Figure 12. Overvoltage shutdown Figure 13. I

Vov (V)

50

48

46

44

42

40

38

36

34

32

30

-50 -25 0 25 50 75 100 125 150 175

Ilim (A)

20

18

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 14. Turn-on voltage slope Figure 15. Turn-off voltage slope

dVout/dt(on) (V/ms)

800

700

600

500

400

300

200

100

Vcc=13V

Rl=6.5Ohm

0

-50 -25 0 25 50 75 100 125 150 175

dVout/dt(off) (V/ms)

600

550

500

450

400

350

300

250

200

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

vs T

LIM

Vcc=13V

Vcc=13V

Rl=6.5Ohm

case

Tc (°C)

Tc (ºC)

Figure 16. On-state resistance vs T

Ron (mOhm)

160

140

120

100

80

60

40

20

0

-50 -25 0 25 50 75 100 125 150 175

Iout=2A

Vcc=8V; 13V & 36V

Tc (°C)

case

Figure 17. On-state resistance vs V

CC

Ron (mOhm)

120

110

100

90

80

70

60

50

40

30

20

10

0

5 10152025303540

Tc=150°C

Tc=25°C

Tc= - 40°C

Iout=5A

Vcc (V)

Doc ID 17546 Rev 2 14/27

VND830P-E Electrical specifications

Figure 18. Input high level Figure 19. Input low level

Vih (V)

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C)

Figure 20. Open-load on-state detection

threshold

Iol (mA)

150

140

130

120

110

100

90

80

70

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C)

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (° C)

Figure 21. Open-load off-state detection

threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 22. Input hysteresis voltage

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Doc ID 17546 Rev 2 15/27

VND830P-E Application information

3 Application information

Figure 23. Application schematic

+5V

+5V

+5V

μ

R

prot

C

R

prot

R

prot

R

prot

STATUS1

INPUT1

STATUS2

INPUT2

V

CC

D

ld

OUTPUT1

D

OUTPUT2

GND

GND

R

V

GND

GND

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: a resistor in the ground line (R

This can be used with any type of load.

The following shows how to dimension the R

1. R

2. R

where - I

≤ 600 mV / (I

GND

≥ (-VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

)

)

maximum rating section of the device’s datasheet.

GND

resistor:

GND

only)

Power dissipation in R

P

=(-VCC)2/R

D

(when VCC< 0 during reverse battery situations) is:

GND

GND

This resistor can be shared amongst several different HSD. Please note that the value of this
resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the

maximum on-state currents of the different devices.

Doc ID 17546 Rev 2 16/27

VND830P-E Application information

Please note that, if the microprocessor ground is not common with the device ground, then
the R

produces a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift varies depending on how many devices are ON in the case of several high­side drivers sharing the same R

GND

.

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using Section 3.1.2 described below.

3.1.2 Solution 2: a diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produce a shift (~600 mV) in the input
threshold and the status output values if the microprocessor ground is not common with the
device ground. This shift does not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the absolute maximum
rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subjected to transients on the

CC

V

line that are greater than those shown in Tab l e 1 3 .

CC

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/O pins from latching up.

if the device is driving an

GND

) in line to prevent

prot

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:

-V

CCpeak

/ I

latchup

≤ R

prot

≤ (V

OHμC

- V

IH

- V

GND

) / I

IHmax

Example

For the following conditions:

V

CCpeak

I

latchup

V

OHμC

5kΩ ≤ R

The recommended values are:

R

prot

= -100 V

≥ 20 mA

≥ 4.5 V

prot

= 10 kΩ

≤ 65 kΩ.

Doc ID 17546 Rev 2 17/27

VND830P-E Application information

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open-load indication when load is connected: in this case
it needs to avoid V
V

OUT

= (V

/ (RL + RPU))RL < V

PU

to be higher than V

OUT

Olmin.

2. No misdetection when load is disconnected: in this case the V
V

Because I
up resistor R

; this results in the following condition R

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby.

) like the +5 V line used to supply the

PU

; this results in the following condition

Olmin

has to be higher than

< (V

PU

is pulled high (up to several mA), the pull-

out

PU

- V

OUT

OLmax

) / I

L(off2)

.

The values of V

OLmin

, V

OLmax

and I

are available in Chapter 2: Electrical specifications.

L(off2)

Figure 24. Open-load detection in off-state

IN PUT

STATUS

DRIVER

+

LOGIC

+

-

GROUND

V batt. VPU

V

CC

I

L(o ff2)

OUT

R

V

OL

R

PU

R

L

Doc ID 17546 Rev 2 18/27

VND830P-E Application information

3.5 Maximum demagnetization energy

Figure 25. SO-16L maximum turn-off current versus load inductance

I

LM A X ( A)

100

10

A

B

C

1

0,1 1 10 100

A = single pulse at T

Jstart

B= repetitive pulse at T

C= repetitive pulse at T

Conditions:

= 13.5 V

V

CC

VIN, I

L

Note:
Values are generated with RL = 0 Ω.
In case of repetitive pulses, T
specified above for curves B and C.

Demagnetization

(at beginning of each demagnetization) of every pulse must not exceed the temperature

jstart

= 150 °C

Jstart

Jstart

= 100 °C

= 125 °C

L( m H )

Demagnetization

Demagnetization

t

Doc ID 17546 Rev 2 19/27

VND830P-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO-16L thermal data

Figure 26. SO-16L PC board

Note:
Layout condition of R
35 µm, Copper areas: 0.5 cm

Figure 27. R

RTH j-amb (°C/W)

70

and Zth measurements (PCB FR4 area = 41 mm x 48 mm, PCB thickness = 2 mm, Cu thickness =

th

2

, 6 cm2).

vs PCB copper area in open box free air condition

thj-amb

65

(1)

60

55

50

45

40

01234567

PCB Cu heatsink area (cm^2)

Doc ID 17546 Rev 2 20/27

VND830P-E Package and PCB thermal data

Figure 28. SO-16 L thermal impedance junction ambient single pulse

Equation 1

Z

THδ

where

: pulse calculation formula

RTHδ Z

THtp

1 δ–()+⋅=

δ tpT⁄=

Figure 29. Thermal fitting model of a quad channel HSD in SO-16L

Tj_1

Pd1

Tj_2

C1

C1 C2

R1

Pd2

C3 C4

R3R1 R6R5R2

R2

R4

T_amb

C5 C6C2

Doc ID 17546 Rev 2 21/27

VND830P-E Package and PCB thermal data

Table 16. Thermal parameters

Area/ island (cm2) Footprint 6

R1 (°C/W) 0.05

R2 (°C/W) 0.3

R3 (°C/W) 2.2

R4 (°C/W) 12

R5 (°C/W) 15

R6 (°C/W) 37 22

C1 (W.s/°C) 0.001

C2 (W.s/°C) 5.00E-03

C3 (W.s/°C) 0.02

C4 (W.s/°C) 0.3

C5 (W.s/°C) 1

C6 (W.s/°C) 3 5

Doc ID 17546 Rev 2 22/27

VND830P-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 SO-16L package information

Figure 30. SO-16L package dimensions

Doc ID 17546 Rev 2 23/27

VND830P-E Package and packing information

Table 17. SO-16L mechanical data

mm.

DIM.

Min. Typ. Max.

A 2.65

a1 0.1 0.2

a2 2.45

b 0.35 0.49

b1 0.23 0.32

C0.5

c1 45° (typ.)

D 10.1 10.5

E 10.0 10.65

e1.27

e3 8.89

F7.4 7.6

L 0.5 1.27

M 0.75

S 8° (max.)

Doc ID 17546 Rev 2 24/27

VND830P-E Package and packing information

5.3 SO-16L packing information

Figure 31. SO-16L tube shipment (no suffix)

Base Q.ty 50
Bulk Q.ty 1000

C

B

A

Figure 32. Tape and reel shipment (suffix “TR”)

Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6

Reel dimensions

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

Doc ID 17546 Rev 2 25/27

VND830P-E Revision history

6 Revision history

Table 18. Document revision history

Date Revision Changes

25-May-2010 1 Initial release.

22-Sep-2010 2 Changed document status from preliminary data to datasheet.

Doc ID 17546 Rev 2 26/27

VND830P-E

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Doc ID 17546 Rev 2 27/27