Datasheet VND810P-E Datasheet (ST)

Features

Type R

VND810P-E 160 mΩ

1. Per each channel.

DS(on)

(1)

I

OUT

3.5 A

(1)

V

CC

36 V

VND810P-E

Double channel high-side driver

■ ECOPACK®: lead free and RoHS compliant

■ Automotive Grade: compliance with AEC

Guidelines

■ Very low standby current

■ CMOS compatible input

■ On-state open-load detection

■ Off-state open-load detection

■ Thermal shutdown protection and diagnosis

■ Undervoltage shutdown

■ Overvoltage clamp

■ Output stuck to V

■ Load current limitation

■ Reverse battery protection

■ Electrostatic discharge protection

detection

CC

SO-16

Description

The VND810P-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
technology, intended for driving any kind of load
with one side connected to ground.

Active V
against low energy spikes (see ISO7637 transient
compatibility table).

Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload.

The device detects open-load condition both in
on-state and off-state. Output shorted to V
detected in the off-state. Device automatically
turns off in case of ground pin disconnection.

pin voltage clamp protects the device

CC

CC

is

Table 1. Device summary

Order codes

Package

Tube Tape and reel

SO-16 VND810P-E VND810PTR-E

July 2010 Doc ID 17606 Rev 1 1/28

www.st.com

1

Contents VND810P-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17

3.1.2 Solution 2: a diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

) in the ground line . . . . . . . . . . . . . . . . . . . . 18

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Maximum demagnetization energy (V

= 13.5 V) . . . . . . . . . . . . . . . . . 20

CC

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 SO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 SO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 SO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 17606 Rev 1

VND810P-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. V

Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. Switching (V

Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 13. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 14. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 15. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. SO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

= 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

Doc ID 17606 Rev 1 3/28

List of figures VND810P-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. On-state resistance vs T
Figure 14. On-state resistance vs V

Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 20. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 23. I

LIM

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

case

Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 26. Maximum turn-off current versus load inductance
Figure 27. SO-16 PC board

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21

Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 30. Thermal fitting model of a quad channel HSD in SO-16. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 31. SO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32. SO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 33. SO-16 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4/28 Doc ID 17606 Rev 1

VND810P-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

cc

V

GND

INPUT1

STATUS1

INPUT2

STATUS2

cc

CLAMP

OVERT EMP. 1

OVERT EMP. 2

LOGIC

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPEN LOAD ON 1

OPEN LOAD OFF 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPEN LOAD ON 2

OPEN LOAD OFF 2

OUTPUT1

OUTPUT2

Figure 2. Configuration diagram (top view)

V

CC

1

16

N.C.

GND

INPUT 1

STATUS 1

STATUS 2

INPUT 2

V

CC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

8

9

V

CC

V

CC

OUTPUT 1

OUTPUT 1

OUTPUT 2

OUTPUT 2

V

CC

V

CC

Floating X X X X

To ground X

Through 10KΩ

resistor

Doc ID 17606 Rev 1 5/28

Electrical specifications VND810P-E

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

- V

- I

I

- I

I

V

E

T

CC

CC

GND

OUT

OUT

I

IN

STAT

ESD

MAX

P

tot

T

j

T

c

stg

DC supply voltage 41 V

Reverse DC supply voltage - 0.3 V

DC reverse ground pin current - 200 mA

DC output current Internally limited A

Reverse DC output current - 6 A

DC input current +/- 10 mA

DC Status current +/- 10 mA

Electrostatic discharge (human body model: R=1.5KΩ;
C = 100pF)

–INPUT
–STATUS
–OUTPUT
–V

CC

Maximum switching energy
(L = 1.5mH; R

= 0Ω; V

L

= 13.5V; T

bat

Power dissipation (per island) at T

= 150ºC; IL = 5A)

jstart

= 25°C 8.3 W

lead

4000
4000
5000
5000

26 mJ

V
V
V
V

Junction operating temperature Internally limited °C

Case operating temperature - 40 to 150

Storage temperature - 55 to 150 °C

6/28 Doc ID 17606 Rev 1

VND810P-E Electrical specifications

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.

2. When mounted on a standard single-sided FR-4 board with 4 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.

Thermal resistance junction-lead 15 °C/W

Thermal resistance junction-ambient 77

2.3 Electrical characteristics

Values specified in this section are for 8 V < V
otherwise stated.

Figure 3. Current and voltage conventions

I

IN1

I

IN2

I

I

V

STAT2

STAT1

IN2

STAT2

V

IN1

V

STAT1

V

INPUT 1

STATUS 1

INPUT 2

STATUS 2

(1)

< 36 V; -40 °C < Tj < 150 °C, unless

CC

(1)

V

F1

V

CC

I

OUT1

OUTPUT 1

V

I

OUT2

OUTPUT 2

V

OUT2

GND

I

GND

(2)

57

OUT1

°C/W

I

S

V

CC

1. VFn = V

CCn

- V

during reverse battery condition.

OUTn

Doc ID 17606 Rev 1 7/28

Electrical specifications VND810P-E

Table 5. Power output

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply

(1)

V

V

V

CC

USD

OV

R

I

S

voltage

(1)

Undervoltage shutdown 3 4 5.5 V

(1)

Overvoltage shutdown 36 V

I

= 1 A; Tj = 25 °C

On-state resistance

ON

(1)

Supply current

OUT

= 1 A; V

I

OUT

Off-state; V

= V

V

IN

OUT

Off-state; V

= V

V

IN

OUT

CC

= 13 V;

CC

= 0 V

= 13 V;

CC

= 0 V;

> 8 V

Tj = 25 °C

5.5 13 36 V

160
320mΩmΩ

12 40 µA

12 25 µA

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

1. Per device.

Table 6. Protections

Off-state output current V

Off-state output current V

Off-state output current

Off-state output current

(1)

On-state; V

= 0 A

I

OUT

= V

IN

= 0 V; V

IN

V

= V

IN

Tj = 125 °C

V

= V

IN

Tj =25°C

= 13 V; V

CC

= 0 V 0 50 µA

OUT

= 3.5 V -75 0 µA

OUT

= 0 V; V

OUT

= 0 V; V

OUT

CC

CC

= 5 V;

IN

= 13 V;

= 13 V;

57mA

5µA

3µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

t

Shutdown temperature 150 175 200 °C

TSD

Reset temperature 135 °C

T

R

Thermal hysteresis 7 15 °C

hyst

Status delay in overload

SDL

conditions

> T

T

j

TSD

20 µs

VCC = 13 V 3.5 5 7.5 A

Current limitation

I

lim

V

demag

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Turn-off output clamp voltage I

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

5.5 V < V

OUT

< 36 V 7.5 A

CC

= 1 A; L = 6 mH VCC-41 VCC-48 VCC-55 V

8/28 Doc ID 17606 Rev 1

VND810P-E Electrical specifications

Table 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

F

Table 8. Status pin

Forward on voltage -I

= 0.5 A; Tj = 150 °C — — 0.6 V

OUT

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

LSTAT

C

V

Table 9. Switching (V

Status low output voltage I

STAT

STAT

Status leakage current Normal operation; V

Status pin Input capacitance Normal operation; V

STAT

I

Status clamp voltage

SCL

CC

= 13V)

STAT

I

STAT

= 1.6 mA 0.5 V

= 5 V 10 µA

STAT

= 5V 100 pF

STAT

= 1mA 6 6.8 8 V

= - 1mA -0.7 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

= 13 Ω from VIN rising edge

R

t

d(on)

t

d(off)

Turn-on delay time

Turn-off delay time

L

to V

R
edge to V

= 1.3 V (see Figure 5)

OUT

= 13 Ω from VIN falling

L

OUT

= 11.7 V

—30 —µs

—30 —µs

(see Figure 5)

R

dV

dV

OUT

OUT

/dt

/dt

Turn-on voltage slope

(on)

Turn-off voltage slope

(off)

= 13 Ω from V

L

to V

= 10.4 V (see

OUT

Figure 5)

= 13 Ω from V

R

L

to V

= 1.3 V (see Figure 5)

OUT

OUT

OUT

= 1.3 V

= 11.7 V

—

—

See

Figure 21

See

Figure 22

—V/µs

—V/µs

Table 10. Open-load detection

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

t

DOL(on)

V

t

DOL(off)

Open-load on-state detection threshold V

OL

Open-load on-state detection delay I

Open-load off-state voltage detection

OL

threshold

= 5 V 20 40 80 mA

IN

= 0 A 200 µs

OUT

= 0 V 1.5 2.5 3.5 V

V

IN

Open-load detection delay at turn-off 1000 µs

Doc ID 17606 Rev 1 9/28

Electrical specifications VND810P-E

Table 11. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

I

V

I

I(hyst)

Input low level 1.25 V

IL

Low level input current V

IL

Input high level 3.25 V

IH

High level input current V

IH

Input hysteresis voltage 0.5 V

Input clamp voltage

ICL

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up)

V

> V

OUT

OL

V

INn

V

STATn

t

DOL(off)

= 1.25 V 1 µA

IN

= 3.25 V 10 µA

IN

I

= 1 mA 6 6.8 8 V

IN

I

= -1 mA -0.7 V

IN

I

OUT

t

DOL(on)

< I

OL

OVER TEMP STATUS TIMING

V

INn

V

STATn

t

SDL

Tj > T

TSD

t

SDL

Figure 5. Switching time waveforms

10/28 Doc ID 17606 Rev 1

VND810P-E Electrical specifications

Table 12. Truth table

Conditions Input Output Status

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

OL

OL

L

H

L
H
H

L
H

L
H

L
H

L
H

L
H

L
H

L
X
X

L
L

L
L

L
L

H
H

L
H

(T

(T

< T

j

> T

j

H
H

H

TSD

H
L

X
X

H
H

L
H

H
L

TSD

) H

) L

Doc ID 17606 Rev 1 11/28

Electrical specifications VND810P-E

Table 13. Electrical transient requirements (part 1/3)

ISO T/R

Test level

7637/1

Test pulse

I II III IV Delays and impedance

1 - 25 V - 50 V - 75 V - 100 V 2 ms, 10 Ω

2 + 25 V + 50 V + 75 V + 100 V 0.2 ms, 10 Ω

3a - 25 V - 50 V - 100 V - 150 V 0.1 µs, 50 Ω

3b + 25 V + 50 V + 75 V + 100 V 0.1 µs, 50 Ω

4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω

5 + 26.5 V + 46.5 V + 66.5 V + 86.5 V 400 ms, 2 Ω

Table 14. Electrical transient requirements (part 2/3)

ISO 7637-1:

Test p u lse

I II III IV

Test level results

1CCCC

2CCCC

3a C C C C

3b C C C C

4CCCC

5CEEE

Table 15. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device performed as designed after exposure to disturbance.

E

One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

12/28 Doc ID 17606 Rev 1

VND810P-E Electrical specifications

Figure 6. Waveforms

NORMAL OPERATION

INPUT

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

n

n

UNDERVOLTAGE

V

USDhyst

V

USD

n

undefined

OVERVOLTAGE

n

VCC<V

OV

V

> V

CC

OV

INPUT

n

OUTPUT VOLTAGE

STATUS

INPUT

n

n

OUTPUT VOLTAGE

STATUS

T

INPUT

n

j

n

OUTPUT CURRENT

STATUS

n

OPEN LOAD with external pull-up

V

> V

n

V

OL

OUT

OL

OPEN LOAD without external pull-up

n

T

TSD

T

R

n

OVERTEMPERATURE

Doc ID 17606 Rev 1 13/28

Electrical specifications VND810P-E

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current

Figure 9. Input clamp voltage Figure 10. Status leakage current

IL(off1) (uA)

1.6

1.44

1.28

1.12

0.96

0.8

0.64

0.48

0.32

0.16

0

-50 -25 0 25 50 75 100 125 150 175

Off state

Vcc=36V

Vin=Vout=0V

Tc (ºC)

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Ilstat (uA)

0.05

0.04

Vstat=5V

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 11. Status low output voltage Figure 12. Status clamp voltage

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vscl (V)

8

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

7

6

-50 -25 0 25 5 0 7 5 100 125 150 175

Tc (°C)

14/28 Doc ID 17606 Rev 1

VND810P-E Electrical specifications

Figure 13. On-state resistance vs T

case

Ron (mOhm)

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Iout=0.5A

Vcc=8V; 13V & 36V

Tc (°C)

Figure 15. Open-load on-state detection

threshold

Iol (mA)

60

55

50

45

40

35

30

25

20

15

10

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 14. On-state resistance vs V

CC

Ron (mOhm)

300

275

250

225

200

175

150

125

100

75

50

5 10152025303540

Iout=0.5A

Tc= 150°C

Tc= 25°C

Tc= - 40°C

Vcc (V)

Figure 16. Open-load off-state voltage

detection threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

Vin=0V

-50 -25 0 25 5 0 7 5 100 125 150 175

Tc (°C)

Figure 17. Input high level Figure 18. Input low level

Vih (V)

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 5 0 7 5 100 125 150 175

Tc (°C)

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 5 0 7 5 100 125 150 175

Tc (°C)

Doc ID 17606 Rev 1 15/28

Electrical specifications VND810P-E

Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 5 0 7 5 100 125 150 175

Tc (°C)

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

dVout/dt(on) (V/ms)

1000

900

800

700

600

500

400

300

200

100

Figure 23. I

Vcc=13V

Rl=13Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

vs T

LIM

case

Vov (V)

50

48

46

44

42

40

38

36

34

32

30

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

dVout/dt(off) (V/ms)

500

450

400

350

300

250

200

150

100

50

0

Vcc=13V

Rl=13Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Ilim (A)

10

9

8

7

6

5

4

3

2

1

0

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

16/28 Doc ID 17606 Rev 1

VND810P-E Application information

3 Application information

Figure 24. Application schematic

+5V

+5V

+5V

μ

R

prot

C

R

prot

R

prot

R

prot

STATUS1

INPUT1

STATUS2

INPUT2

V

CC

D

ld

OUTPUT1

D

OUTPUT2

GND

GND

R

V

GND

GND

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: a resistor in the ground line (R

This can be used with any type of load.

The following show how to dimension the R

Equation 1:

R

≤ 600 mV / I

GND

S(on)max

GND

resistor:

GND

only)

Equation 2

R

≥ (-VCC) / (-I

GND

where -I

is the DC reverse ground pin current and can be found in the absolute

GND

GND

)

maximum rating section of the device datasheet.

Doc ID 17606 Rev 1 17/28

Application information VND810P-E

Power dissipation in R

P

= (-VCC)2/ R

D

GND

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with Equation 1 where I
maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the
R

produces a shift (I

GND

S(on)max

values. This shift varies depending on how many devices are ON in the case of several high­side drivers sharing the same R

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: a diode (D

A resistor (R
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift (≈600 mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift not varies if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.

= 1 kΩ) should be inserted in parallel to D

GND

(when V

GND

< 0 during reverse battery situations) is:

CC

* R

GND

) in the input thresholds and the status output

GND

.

) in the ground line

S(on)max

becomes the sum of the

if the device is driving an

GND

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subject to transients on the VCC

CC

line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:

-V

CCpeak

Example

For the following conditions:

V

CCpeak

I

latchup

V

OHµC

5kΩ ≤ R

/ I

latchup

= - 100 V

≥ 20 mA

≥ 4.5 V

≤ 65 kΩ.

prot

≤ R

prot

≤ (V

OHµC

- V

IH

- V

GND

) / I

IHmax

) in line to prevent

prot

18/28 Doc ID 17606 Rev 1

VND810P-E Application information

Recommended values are:

R

= 10 kΩ

prot

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open-load indication when load is connected: in this case we have to avoid
V

to be higher than V

OUT

V

= (V

OUT

PU

/ (RL + RPU))RL < V

; this results in the following condition

Olmin

Olmin.

2. No misdetection when load is disconnected: in this case the V
V

Because I
up resistor R

; this results in the following condition R

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby.

) like the +5 V line used to supply the

PU

has to be higher than

< (V

PU

is pulled high (up to several mA), the pull-

out

PU

- V

OUT

OLmax

) / I

L(off2)

.

The values of V

OLmin

, V

OLmax

and I

are available in Section 2.3: Electrical

L(off2)

characteristics.

Figure 25. Open-load detection in off-state

V

CC

INPUT

STATUS

DRIVER

+

LOGIC

+

-

V

GROUND

V batt. VPU

I

L(off2)

OUT

R

OL

R

PU

R

L

Doc ID 17606 Rev 1 19/28

Application information VND810P-E

3.5 Maximum demagnetization energy (V

Figure 26. Maximum turn-off current versus load inductance

I

LM A X (A)

10

1

0,1 1 10 100

L( mH )

= 13.5 V)

CC

C

(1)

A

B

A = single pulse at T

B= repetitive pulse at T

C= repetitive pulse at T

VIN, I

L

1. Values are generated with R

In case of repetitive pulses, T
the temperature specified above for curves B and C.

= 150 °C

Jstart

= 100 °C

Jstart

= 125 °C

Jstart

Demagnetization

= 0 Ω.

L

(at beginning of each demagnetization) of every pulse must not exceed

jstart

Demagnetization

Demagnetization

t

20/28 Doc ID 17606 Rev 1

VND810P-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO-16 thermal data

Figure 27. SO-16 PC board

1. Layout condition of R

thickness = 1.6 mm, Cu thickness = 35 µm, Copper areas: 0.26 cm

Figure 28. R

thj-amb

RTH j- am b

and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB

th

vs PCB copper area in open box free air condition

(°C/W)

(1)

85

80

75

2

, 4 cm2).

70

65

60

55

50

45

40

012345

PCB Cu heats ink area (cm ^2)

Doc ID 17606 Rev 1 21/28

Package and PCB thermal data VND810P-E

Figure 29. Thermal impedance junction ambient single pulse

ZTH (°C/W)

1000

100

10

1

0.1

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Equation 3: pulse calculation formula

Z

where

THδ

RTHδ Z

δ tpT⁄=

THtp

1 δ–()+⋅=

0.26 cm

4 cm

2

2

Figure 30. Thermal fitting model of a quad channel HSD in SO-16

Tj_1

Pd1

Tj_2

22/28 Doc ID 17606 Rev 1

C1

C1 C2

R1

Pd2

C3 C4

R3R1 R6R5R2

R2

C5 C6C2

R4

T_amb

VND810P-E Package and PCB thermal data

Table 16. Thermal parameters

Area / island (cm2)0.54

R1 (°C/W) 0.35

R2 (°C/W) 1.8

R3 (°C/W) 4.5

R4 (°C/W) 10

R5 (°C/W) 16

R6 (°C/W) 48 25

C1 (W.s/°C) 0.0001

C2 (W.s/°C) 7E-04

C3 (W.s/°C) 6E-03

C4 (W.s/°C) 0.2

C5 (W.s/°C) 0.7

C6 (W.s/°C) 2 4

Doc ID 17606 Rev 1 23/28

Package and packing information VND810P-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

is an ST trademark.

5.2 SO-16 package information

Figure 31. SO-16 package dimensions

.

24/28 Doc ID 17606 Rev 1

VND810P-E Package and packing information

Table 17. SO-16 mechanical data

mm.

DIM.

Min. Typ. Max.

A 1.75

a1 0.1 0.2

a2 1.65

b 0.35 0.46

b1 0.19 0.25

C0.5

c1 45° (typ.)

D9.8 10

E5.8 6.2

e1.27

e3 8.89

F3.8 4.0

G4.6 5.3

L 0.5 1.27

M 0.62

S 8°

Doc ID 17606 Rev 1 25/28

Package and packing information VND810P-E

5.3 SO-16 packing information

Figure 32. SO-16 tube shipment (no suffix)

B

C

A

Figure 33. SO-16 tape and reel shipment (suffix “TR”)

Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A 3.2
B 6
C (± 0.1) 0.6

All dimensions are in mm.

Reel dimensions

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

26/28 Doc ID 17606 Rev 1

VND810P-E Revision history

6 Revision history

Table 18. Document revision history

Date Revision Changes

20-Jul-2010 1 Initial release.

Doc ID 17606 Rev 1 27/28

VND810P-E

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28/28 Doc ID 17606 Rev 1