Datasheet VND810-E Datasheet (ST)

VND810-E

DOUBLE CHANNEL HIGH SIDE DRIVER

Table 1. General Features

Type R

VND810-E 160 m

(*) Per each channel

CMOS COMPATIBLE INPUTS

■

■ OPEN DRAIN STATUS OUTPUTS

■ ON STATE OPEN LO AD DETECTION

■ OFF STATE OPEN LOAD DETECTION

■ SHOR T E D L O A D PROT E C TION

■ UNDERVOLTAGE AND OVERVOLTAGE

DS(on)

Ω (*) 3.5A (*) 36 V

I

out

V

CC

SHUTDOWN

■ PROTECTION AGAINST LOSS OF GROUND

■ VERY LOW STAND-BY CURRENT

■ REVERSE BATTERY PROTECTION (**)

■ IN COMPLIANCE WITH THE 2002/95/EC

EUROPEAN DIRECT IVE

DESCRIPTION

The VND810-E is a monolithic device designed in
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.

Activ e V

pin voltage clamp pro tects the device

CC

against low energy spikes (see ISO7637 transient
compatibility table).

Figure 1. Package

SO-16

Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects open
load condition both in on and off state. Output
shor te d to V

is detected in the off state. Device

CC

automatically turns off in case of ground pin
disconnection.

Table 2. Order Codes

Package Tube Tape and Reel

SO-16

Note: (**) See application schematic at page 9

VND810-E VND810TR-E

Rev. 1

1/20October 2004

VND810-E

Figure 2. Block Diagram

V

cc

CLAMP

OVERVOLTAGE

UNDERVOLTAGE

V

cc

GND

INPUT1

STATUS1

INPUT2

STATUS2

OVERTEMP. 1

OVERTEMP. 2

LOGIC

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

CLAMP 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPENLOAD ON 2

OPENLOAD OFF 2

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

DC Supply Voltage 41 V
Reverse DC Supply Voltage - 0.3 V
DC Reverse Ground Pin Current - 200 mA
DC Output Current Internally Limited A
Reverse DC Output Current - 6 A
DC Input Current +/- 10 mA
DC Status Current +/- 10 mA
Electrostatic Discharge (Human Body Model:

R=1.5KΩ; C=100pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

4000
4000
5000
5000

Maximum Switching Energy
(L=1.5mH; R

I

=5A)

L

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC;

26 mJ

Power Dissipation TC=25°C 8.3 W
Junction Operating Temperature Internally Limited °C
Case Operating Temperature - 40 to 150 °C
Storage Temperature - 55 to 150 °C

- V

- I
I

- I

V

E

V

CC

GND

OUT

OUT

I

IN

I

stat

ESD

MAX

P

tot

T

T

T

stg

CC

j

c

OUTPUT1

OUTPUT2

V
V
V
V

2/20

VND810-E

Figure 3. Con fig urat i on Dia g ra m (Top View) & Sugg est ed C o nnections for Unused and N.C. Pins

V

CC

N.C.

GND

INPUT 1
STATUS 1
STATUS 2

INPUT 2

V

CC

Connection / Pin Status N.C. Output Input

Floating X X X X
To Ground X Through 10KΩ resistor

Figure 4. Current and Voltage Conventions

1

8

16

9

V

CC

V

CC

OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V

CC

V

CC

I

S

V

(*)

F1

I

OUT2

V

I

OUT1

V

OUT2

OUT1

V

CC

(*) VFn = V

CCn

V

- V

I

IN1

I

IN1

V

STAT1

STAT1

I

IN2

I

V

STAT2

IN2

STATUS 2

V

STAT2

during reverse battery condition

OUTn

INPUT 1

STATUS 1

INPUT 2

GND

V

CC

OUTPUT 1

OUTPUT 2

I

GND

Table 4. Thermal Data

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm

Note: 2. When mounted on a standard single-sided FR-4 board with 4cm

Thermal Resistance Junction-lead 15 °C/W

Thermal Resistance Junction-ambient 77

2

mounting and no art i f i cial air flow .

mounting and no art i f i cial air flow.

of Cu (at least 35µm thick) connected to all VCC pins. Horizontal

2

of Cu (at least 3 5µm thick) connected to all VCC pins. Hori zontal

(1)

57

(2)

°C/W

3/20

VND810-E

ELECTRICAL CHARACTERISTICS

(8V<V

(Per each channel)

Table 5. Po we r Ou t put

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

V

V

Note: (**) Per device.

<36V; -40°C < Tj <150°C, unless otherwise specified)

CC

(**) Operating Supply Voltage 5.5 13 36 V

CC

(**) Undervoltage Shut-down 3 4 5.5 V

USD

(**) Overvoltage Shut- down 36 V

OV

I

R

ON

(**) Supply Current

I

S

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

On State Resistance

Off State Output Current VIN=V
Off State Output Current VIN=0V; V
Off State Output Current VIN=V
Off State Output Current VIN=V

=1A; Tj=25°C

OUT

I

=1A; VCC>8V

OUT

Off State; V
Off State; V

Tj=25°C

On State; V

OUT

OUT
OUT

=13V; VIN=V

CC

=13V; VIN=V

CC

OUT
OUT

=0V
=0V;

12

12

=13V; VIN=5V; I

CC

OUT

=0A

5

=0V 0 50 µA

=3.5V -75 0 µA

OUT

=0V; VCC=13V; Tj =125°C 5 µA
=0V; VCC=13V; Tj =25°C 3 µA

160
320

40

25

7

mΩ
mΩ

µA

µA

mA

Table 6. Protection (see note 1)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

T

TSD

T

T

hyst

t

SDL

I

lim

V

demag

Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be

Shut-down Temperature 150 175 200 °C
Reset Temperature 135 °C

R

Thermal Hysteresis 7 15 °C
Status Delay in Overload

Conditions

Current limitation

Turn-off Output Clamp
Voltage

used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles

Tj>T

TSD

5.5V<VCC<36V

=1A; L=6mH

I

OUT

3.5 5 7.5

-

V

CC

V

41

CC

-48

V

20 µs

7.5

-

CC

55

A
A

V

Table 7. VCC - Output Diode

Symbol Parameter Test Conditions Min Typ Max Unit

V

Forward on Voltage -I

F

=0.5A; Tj=150°C 0.6 V

OUT

4/20

VND810-E

ELECTRICAL CHARACTERISTICS (continued)
Table 8. Status Pin

Symbol Parameter Test Conditions Min Typ Max Unit

V

STAT

I

LSTAT

C

STAT

V

SCL

Status Low Output Voltage I

= 1.6 mA 0.5 V

STAT

Status Leakage Current Normal Operation; V
Status Pin Input

Capacitance
Status Clamp Voltage

Normal Operation; V
I

= 1mA

STAT

= - 1mA

I

STAT

= 5V 10 µA

STAT

= 5V 100 pF

STAT

66.8

8V

-0.7

V

Table 9. Switching (V

CC

=13V)

Symbol Parameter Test Conditions Min Typ Max Unit

=13Ω from VIN rising edge to

R

L

V

=1.3V

OUT

=13Ω from VIN falling edge to

R

L

V

=11.7V

OUT

=13Ω from V

R

L

V

=10.4V

OUT

=13Ω from V

R

L

V

=1.3V

OUT

=1.3V to

OUT

=11.7V to

OUT

30 µs

30 µs

See

relative

diagram

See

relative

diagram

dV

dV

t

t

OUT

OUT

d(on)

d(off)

Turn-on Delay Time

Turn-off Delay Time

/dt

Turn-on Voltage Slope

(on)

/dt

Turn-off Voltage Slope

(off)

Table 10. Openload Detection

Symbol Parameter Test Conditions Min Typ Max Unit

I

OL

t

DOL(on)

V

OL

t

DOL(off)

Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Openload OFF State

Voltage Detection
Threshold

Openload Detection Delay
at Turn Off

=5V 20 40 80 mA

V

IN

I

=0A 200 µs

OUT

V

=0V 1.5 2.5 3.5 V

IN

1000 µs

V/µs

V/µs

Table 11. Logic Input

Symbol Parameter Test Conditions Min Typ Max Unit

V

I(hyst)

V

V

I

V

I

IH

ICL

Input Low Level 1.25 V

IL

Low Level Input Current VIN = 1.25V 1 µA

IL

Input High Level 3.25 V

IH

High Level Input Current VIN = 3.25V 10 µA
Input Hysteresis Voltage 0.5 V

Input Clamp Voltage

I

= 1mA

IN

= -1mA

I

IN

66.8

-0.7

8V

V

5/20

VND810-E

Figure 5.

OPEN L OAD STATUS TIMING (with ex terna l pu ll-u p)

V

> V

OUT

OL

V

INn

V

STAT n

t

DOL(off)

t

DOL(on)

Tabl e 12. Truth Table

CONDITIONS INPUT OUTPUT SENSE

Normal Operation

Current Limitation

Overtemperature

Undervoltage

Overvoltage

Output Voltage > V

OL

L

H

L
H
H

L
H

L
H

L
H

L
H

I

OUT

< I

OVERTEMP STA TUS TIMING

OL

V

INn

V

STAT n

L

H

L
X
X

L

L

L

L

L

L
H

H

t

SDL

Tj > T

TSD

(T

(T

< T

j

> T

j

t

TSD

TSD

SDL

H
H

H

) H

) L

H
L

X
X

H
H

L
H

Output Current < I

6/20

OL

L

H

L
H

H
L

Figure 6. Swi tc hing Time Wave form s

V

OUTn

80%

dV

/dt

OUT

(on)

V

INn

t

d(on)

10%

t

d(off)

90%

dV

OUT

/dt

VND810-E

(off)

t

t

Table 13. Electrical Transient Requirements On V

ISO T/R 7637/1

Test Pulse

I II III IV Delays and

CC

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

ISO T/R 7637/1

Test Pulse

I II III IV

TEST LEVELS RESULTS

1CCCC

2CCCC
3aCCCC
3bCCCC

4CCCC

5C E E E

CLASS CONTENTS

C All functions of the device are performed as designed after exposure to disturbance.

E One or more functions of the device is not performed as designed after exposure and cannot be

returned to proper operation without replacing the device.

Pin

TEST LEVELS

Impedance

Ω

Ω

7/20

VND810-E

Figure 7. Waveforms

INPUT

n

OUTPUT VOLTAGE
STATUS

V

CC

INPUT

n

OUTPUT VOLTAGE
STATUS

V

CC

INPUT

n

OUTPUT VOLTAGE

STATUS

NORMAL OPERATION

n

n

UNDERVOLTAGE

V

USDhyst

V

USD

n

n

undefined

OVERVOLTAGE

VCC>V

VCC<V

OV

n

n

OV

INPUT

n

OUTPUT VOLTAGE
STATUS

INPUT

n

n

OUTPUT VOLTAGE
STATUS

T

INPUT

n

j

n

OUTPUT CURRENT

STATUS

n

OPEN LOAD with external pull-up

V

n

V

OL

OUT>VOL

OPEN LOAD without external pull-up

n

OVERTEMPERATURE

T

TSD

T

R

n

8/20

Figure 8. Application Schematic

+5V

+5V

+5V

R

prot

R

µ

C

prot

R

prot

R

prot

STATUS1

INPUT1

STATUS2

INPUT2

VND810-E

V

CC

D

ld

OUTPUT1

GND PROTECTION NETWORK AGAINST
REVERSE BATTERY

Solution 1: Re sistor in th e ground line (R
can be used with any type of load.

The following is an indication on how to d imension the
R

resistor.

GND

1) R

2) R

where -I
be found in the absolute maxim um rating section of the

≤ 600mV / I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can

GND

S(on)max

GND

.

)

device’s datasheet.
Power Dissipation in R

battery situations) is:

= (-VCC)2/R

P

D

GND

(when VCC<0: during rever se

GND

This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) wh ere I
sum of the maximum on-state currents of the different

S(on)max

devices.
Please note that if the microprocessor ground is not

common with the device ground then the R
produce a shift (I
and the status output values. This shift will vary

S(on)max

* R

) in the input thresho lds

GND

depending on how many dev ices are ON in the case of
several high side drivers sharing the same R

only). This

GND

becomes t he

GND

.

GND

will

D

OUTPUT2

GND

GND

R

V

GND

GND

If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize So lution 2 (see
below).

Solution 2:
A resistor (R

D

GND

A diode (D

=1kΩ) should be inserted in parallel to

GND

if the device will be driving an inductive load.

) in the ground line.

GND

This small signal diode can be safely shared amongst
several different HS D. Also in this cas e, the presenc e of
the ground network will produce a shift (j600mV) in the

input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.

Series resistor in INPUT and STATUS lines are also
required to p reven t tha t, d uring bat tery voltag e tr ansie nt,
the current exceeds the Absolute Maximum Rating.

Safest configu ration for unu sed INPU T and S TAT US pin
is to leave them unconnected.

LOAD DUMP PROTECTIO N

Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds V
The same applies if the device will be subject to
transients on the V

line that are greater than the ones

CC

shown in the ISO T/R 7637/1 table.

max DC rating.

CC

9/20

VND810-E

µC I/Os PROTECTION:

If a ground protection network is used and negative
transient are present on the V
be pulled negative. ST suggests to insert a resistor (R
in line to prevent the µC I/Os pins to latch-up.

The value of thes e resistors is a compro mise between
the leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.

-V

CCpeak/Ilatchup

≤ R

prot

Calculation example:
For V
5kΩ ≤ R
Recommended R

CCpeak

prot

= - 100V and I

≤ 65kΩ.

value is 10kΩ.

prot

line, the control pins will

CC

≤ (V

OHµC-VIH-VGND

≥ 20mA; V

latchup

) / I

OHµC

prot

IHmax

≥ 4.5V

OPEN LOAD DETECTION IN OFF STATE

Off state open load detection requires an external pull-up
resistor (R

) connected between OUTPUT pin and a

PU

Figure 9. Open Load detection in off state

positive supply voltage (V

) like the +5V line used to

PU

supply the microprocessor.
The external res istor has to be s electe d ac cordin g to t he
following requirements:

)

1) no false o pen load indic ation when lo ad is con necte d:
in this case we have to avoid V

; this results in the following condition

V

Olmin

=(VPU/(RL+RPU))RL<V

V

OUT

to be high er than

OUT

Olmin.

2) no misdetection when load is disconnected: in this
case the V
results in the fol lowing condition R

.

I

L(off2)

Because I

has to be higher than V

OUT

may significantly increase if V

s(OFF)

PU

<(V

pulled high (up to several mA), the pull-u p resistor R
should be connected to a supply that is switched OFF
when the module is in standby.

The values of V

OLmin

, V

OLmax

and I

are available in

L(off2)

the Electrical Characteristics section.

V batt. VPU

; this

OLmax

PU–VOLmax

out

)/

is

PU

INPUT

STATUS

DRIVER

+

LOGIC

V

CC

+

­VOL

GROUND

R

OUT

IL(off2)

R

PU

RL

10/20

VND810-E

Figure 10. Off State Output Current

IL(off1) (uA)

1.6

1.44

1.28

1.12

0.96

0.8

0.64

0.48

0.32

0.16
0

-50 -25 0 25 50 75 100 125 150 175

Off state
Vcc=36V

Vin=Vout=0V

Tc (ºC)

Figure 11. Input Clamp Voltage

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 13. High Level Input Current

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 14. Status Leakage Current

Ilstat (uA)

0.05

0.04

Vstat= 5 V

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 12. S t at us Low Output Vol ta ge

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 15. Status Clamp Voltage

Vscl (V)

8

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

11/20

VND810-E

)

Figure 16. On State Resistance Vs T

case

Ron (mOhm)

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Iout=0.5A

Vcc=8V; 13V & 36V

Tc (°C)

Figure 17. Openload On State Detection

Threshol d

Iol (mA)

60

55

50

45

40

35

30

25

20

15
10

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C

Figure 19. On State Resistance Vs V

CC

Ron (mOhm)

300

275

250

225

200

175

150

125

100

75
50

510152025303540

Iout=0.5A

Tc= 150°C

Tc= 25°C

Tc= - 40°C

Vcc (V)

Figure 20. Openload Off State Detection

Threshold

Vol (V )

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5
0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 18. Input High Level

Vih (V )

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

12/20

Figure 21. Input Low Level

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

VND810-E

Figure 22. Input Hysteresis Voltage

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 23. Turn-on Voltage Slope

dVout/dt( on ) (V /ms )

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

Rl=13Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Figure 25. Overvoltage Shutdown

Vov (V)

50

48

46

44

42

40

38

36

34

32
30

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 26. Turn-off Voltage Slope

dVout/dt( off) (V/ms)

500

450

400

350

300

250

200

150

100

50

0

Vcc=13V

Rl=13Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Figure 24. I

LIM

Vs T

case

Ilim ( A)

10

9

8

7

6

5

4

3

2

1
0

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

13/20

VND810-E

Figure 27. Maximum turn off current versus load inductance

LMAX (A)

I

10

A

B

C

1

0.1 1 10 10 0

A = Single Pulse at T

B= Repetitive pulse at T
C= Repetitive Pulse at T

Conditions:
VCC=13.5V

VIN, I

L

Jstart

=150ºC

=100ºC

Jstart

=125ºC

Jstart

Demagnetization

L(mH)

Values are generated with R
In case of repetitive pulses, T

each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.

Demagnetization

=0Ω

L

(at beginning of

jstart

Demagnetization

14/20

t

PowerSO-10™ Thermal Data

Figure 28. SO-16 PC Board

VND810-E

Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=1.6mm,
Cu thickness=35µm, Copper areas: 0.26cm

Figure 29. R

Vs PCB copper area in open box free air condition

thj-amb

2

, 4cm2).

RTH j-am b

(°C/W)

85
80
75
70
65
60
55
50
45
40

012345

PCB Cu heatsink area (cm^2)

15/20

VND810-E

Figure 30. SO-16 Thermal Impedance Jun ction Ambient Single Pu lse

ZTH (°C/W)

1000

100

10

1

0.1

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Figure 31. Th e rm al fit t in g m od e l of a double
channel HSD in SO-16

Pulse calculation formula

Z

TH

R

δ Z

δ

TH

THtp

2

0.26 cm

2

4 cm

1 δ–()+⋅=

Tj_1

Tj_2

16/20

Pd1

C1

C1 C2

R1

Pd2

where

δ tpT⁄=

Table 14. Thermal Parameter

C3 C4

R4

R3R1 R6R5R2

R2

T_amb

C5 C6C2

Area/island (cm2) 0.5 4

R1 (°C/W) 0.35
R2 (°C/W) 1.8
R3 ( °C/W) 4.5
R4 (°C/W) 10
R5 (°C/W) 16
R6 (°C/W) 48 25
C1 (W.s/°C) 0.0001
C2 (W.s/°C) 7.00E-04
C3 (W.s/°C) 6.00E-03
C4 (W.s/°C) 0.2
C5 (W.s/°C) 0.7
C6 (W.s/°C) 2 4

PACKAGE MECHANICAL

Table 15. SO-16 Mechanical Data

Symbol

A 1.75
a1 0.1 0.2
a2 1.65

b 0.35 0.46
b1 0.19 0..25

C 0.5

c1 45° (typ.)

D 9.8 10

E 5.8 6.2

e 1.27
e3 8.89

F 3.8 4.0

G 4.6 5.3

L 0.5 1.27

M 0.62

S 8° (max.)

Min Typ Max

Figure 32. SO-16 Package Dimensions

VND810-E

millimeters

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VND810-E

Figure 33. SO-16 Sugge st ed P a d Layout And Tube Shipment ( no suffix)

B

C

A

Figure 34. Tape And Reel Shipment (suffix “TR”)

Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A 3.2
B 6
C (± 0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

.All dimensions are in mm.

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13

F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

18/20

Top

cover

tape

End

500mm min

Empty componen ts poc kets
saled with cov e r ta pe.

User direction of feed

Start

No componentsNo components Com ponents

500mm m in

REVISION HIST ORY

Date Revision Descrip tion of Changes

Oct. 2004 1 - First Issue

VND810-E

19/20

VND810-E

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