Datasheet VND81013TR, VND810 Datasheet (SGS Thomson Microelectronics)

Page 1
®
July 2002 1/19
VND810
DOUBLE CHANNEL HIGH SIDE DRIVER
CMOS COMPATIBLE INPUTS
OPEN DRAIN STATUS OUTPUTS
ON STATE OPEN LOAD DETECTION
SHORTED LOAD PROTECTION
UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
PROTECTION AGAINST LOSS OF GROUND
VERY LOW STAND-BY CURRENT
REVERSE BATTERY PROTECTIO N (**)
DESCRIPTION
The VND810 is a monolithic device designe d in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltag e clamp protects th e dev ice against low energy spikes (see ISO7637 transient compatibility table). Active current limitation
combined with thermal shutdown and automatic restart protects the device against overloa d. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Dev ice auto mati cally tur ns off in c ase of ground pin disconnection.
TYPE R
DS(on)
I
OUT
V
CC
VND810 160 m(*) 3.5 A (*) 36 V
SO-16
ORDER CODES
PACKAGE TUBE T&R
SO-16
VND810 VND81013TR
(*) Per each channel
BLO C K DIAG RA M
(**) See appl ic ation schema tic at page 8
OVERTEMP. 1
V
cc
GND
INPUT1
OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
V
cc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPENLOAD ON 1
CURRENT LIMITER 1
OPENLOAD OFF 1
OUTPUT2
DRIVER 2
CLAMP 2
OPENLOAD ON 2
OPENLOA D OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
Page 2
2/19
VND810
ABSOLUTE MAXIMUM RATI NG
CONNECTION DIAGRAM (TOP VIEW)
CURRENT AND VOLTAGE CONVENTIONS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage 41 V
- V
CC
Reverse DC Supply Voltage - 0.3 V
- I
GND
DC Reverse Ground Pin Current - 200 mA
I
OUT
DC Output Current Internally Limited A
- I
OUT
Reverse DC Output Current - 6 A
I
IN
DC Input Current +/- 10 mA
I
stat
DC Status Cur rent +/- 10 mA
V
ESD
Electros tatic Discharge (Hum an Body Model: R=1.5KΩ; C=100pF)
- INPUT
- STATUS
- OUTPU T
- V
CC
4000 4000 5000 5000
V V V V
E
MAX
Maximum Switching Energy (L=1.5mH; R
L
=0; V
bat
=13.5V; T
jstart
=150ºC; IL=5A)
26 mJ
P
tot
Powe r Dissipation TC=25°C 8.3 W
T
j
Junction Operating Temperature Internally Limited °C
T
c
Case Operating Temperature - 40 to 150 °C
T
stg
Storage Temperature - 55 to 150 °C
V
CC
V
CC
OUTPUT 2
OUTPUT 2
OUTPUT 1
V
CC
OUTPUT 1
V
CC
V
CC
INPUT 2
STA TUS 2
ST ATUS 1
INPUT 1
V
CC
GND
N.C.
1
8
9
16
I
S
I
GND
OUTPUT 2
V
CC
GND
STATUS 2
INPUT 2
I
OUT2
I
IN2
I
STAT2
V
STAT2
V
IN2
V
CC
V
OUT2
OUTPUT 1
I
OUT1
V
OUT1
INPUT 1
I
IN1
STATUS 1
I
STAT1
V
IN1
V
STAT 1
Page 3
3/19
VND810
THERMAL DATA
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mounting an d no ar tificial ai r flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C < Tj <150°C, unless otherwise specified)
(Per each channel) POWER OUTPUTS
(**) Per device
SWITCHING (VCC=13V)
LOGIC INPUT
Symbol Parameter Value Unit
R
thj-lead
Thermal R esistanc e Junctio n-lead 15 °C/W
R
thj-amb
Thermal Resistance Junctio n-ambient 75 (*) °C/W
Symbol Parameter Test Conditions Min Typ Max Unit
V
CC
(**) Operating Supply Voltage 5.5 13 36 V
V
USD
(**) Under Voltage Shut-down 3 4 5.5 V
V
OV
(**) Ove rvoltage Shut-down 36 V
R
ON
On State Resistance
I
OUT
=1A; Tj=25°C
I
OUT
=1A; VCC>8V
160 320
m m
I
S
(**) Supply Current
Off State; V
CC
=13V; VIN=V
OUT
=0V
Off State; V
CC
=13V; VIN=V
OUT
=0V;
Tj=25°C
On State; V
CC
=13V; VIN=5V; I
OUT
=0A
12
12
5
40
25
7
µA
µA
mA
I
L(off1)
Off State Output Curr ent VIN=V
OUT
=0V 0 50 µA
I
L(off2)
Off State Output Curr ent VIN=0V; V
OUT
=3.5V -75 0 µA
I
L(off3)
Off State Output Curr ent VIN=V
OUT
=0V; Vcc=13V; Tj =125°C 5 µA
I
L(off4)
Off State Output Curr ent VIN=V
OUT
=0V; Vcc=13V; Tj =25°C 3 µA
Symbol Parameter Test Conditions Min Typ Max Unit
t
d(on)
Turn-on Delay Time
RL=13from VIN rising ed ge to V
OUT
=1.3V
30 µs
t
d(off)
Turn-off Delay Time
RL=13from VIN falling edge to V
OUT
=11.7V
30 µs
dV
OUT
/dt
(on)
Turn-on Voltage Slope
RL=13from V
OUT
=1.3V to
V
OUT
=10.4V
See
relative
diagram
V/µs
dV
OUT
/dt
(off)
Turn-off Voltag e Slope
RL=13from V
OUT
=11.7V to
V
OUT
=1.3V
See
relative
diagram
V/µs
Symbol Param eter Test Conditions Min Typ Max Unit
V
IL
Input Low Level 1.25 V
I
IL
Low Level Input Current VIN = 1.25V 1 µA
V
IH
Input High Level 3.25 V
I
IH
High Level Input Curr ent VIN = 3.25V 10 µA
V
I(hyst)
Input Hyst eresis Voltage 0.5 V
V
ICL
Input Clamp Voltage
I
IN
= 1mA
I
IN
= -1mA
66.8
-0.7
8V
V
1
Page 4
4/19
VND810
ELECTRICAL CHARACTERISTICS (continued)
STATUS PIN
PROTECTIONS
OPENLOAD DETECTION
Symbol Parameter Test Conditions Min Typ Max Unit
V
STAT
Status Low Output Voltage I
STAT
= 1.6 mA 0.5 V
I
LSTAT
Status Leakage Current Normal Operation; V
STAT
= 5V 10 µA
C
STAT
Status Pin Input Capacitance
Normal Operation; V
STAT
= 5V 100 pF
V
SCL
Status Clamp Voltage
I
STAT
= 1mA
I
STAT
= - 1mA
66.8
-0.7
8V
V
Symbol Parame ter Test Condit ions Min Typ Max Unit
T
TSD
Shut-down Temperature 150 175 200 °C
T
R
Reset Temp erature 135 °C
T
hyst
Ther ma l Hy steresi s 7 15 °C
t
SDL
Status Delay in Overload Conditions
Tj>T
TSD
20 µs
I
lim
Current limitation
5.5V<V
CC
<36V
3.5 5 7.5
7.5
A A
V
demag
Turn-off Output Clamp Voltage
I
OUT
=1A; L= 6m H VCC-41 VCC-48 VCC-55 V
Symbol Param eter Test Conditions Min Typ Max Unit
I
OL
Openload ON State Detectio n Threshol d
V
IN
=5V 20 40 80 mA
t
DOL(on)
Openload ON State Detection Delay
I
OUT
=0A 200 µs
V
OL
Openload OFF State Voltage Detection Threshold
VIN=0V 1.5 2.5 3.5 V
t
DOL(off)
Openload Detection Delay at Turn Off
1000 µs
2
V
INn
V
STAT n
t
DOL(off)
OPEN LOAD STATUS TIMING (with external pull-up)
V
INn
V
STAT n
OVERTEMP ST ATUS TIMING
t
SDL
t
SDL
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
Tj > T
TSD
Page 5
5/19
VND810
t
t
V
OUTn
V
INn
80%
10%
dV
OUT
/dt
(on)
t
d(off)
90%
dV
OUT
/dt
(off)
t
d(on)
Switching time Waveforms
TRUTH TABLE
CONDITIONS INPUT OUTPUT STATUS
Normal Operation
L
H
L
H
H H
Current Limitation
L H H
L X X
H
(T
j
< T
TSD
) H
(T
j
> T
TSD
) L
Overtemperature
L
H
L
L
H L
Undervoltage
L
H
L
L
X X
Overvoltage
L
H
L
L
H H
Output Voltage > V
OL
L
H
H H
L H
Output Current < I
OL
L
H
L H
H L
Page 6
6/19
VND810
ELECTRICAL TRANS IENT REQUIREMENTS ON VCC PIN
ISO T/R 7637/1
Test Pulse
TEST LEVELS
I II III IV Delays and
Impedance
1 -25 V -50 V -75 V -100 V 2 ms 10
2 +25 V +50 V +75 V +100 V 0.2 ms 10 3a -2 5 V - 50 V - 100 V -150 V 0.1 µs 50 3b + 25 V +50 V +75 V +100 V 0.1 µs 50
4 -4 V -5 V -6 V -7 V 100 ms, 0.01
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2
ISO T/R 76 37 / 1
Test Pulse
TEST LEVELS RESULTS
I II III IV
1CCCC
2CCCC 3aCCCC 3bCCCC
4CCCC
5CEEE
CLASS CONTENTS
C All func tions of the device are performed as desi gned afte r exposure to disturbance. E One or more f unctions of the device is not per formed as designe d after exp osure and cannot be
returned to prop er operation withou t replacing the device.
Page 7
7/19
VND810
1
OPEN LOAD without external pull-up
STATUS
n
INPUT
n
NORMAL OPERATION
UNDERVOLTAGE
V
CC
V
USD
V
USDhyst
INPUT
n
OVERVOLTAGE
V
CC
STATUS
n
INPUT
n
STATUS
n
STATUS
n
INPUT
n
STATUS
n
INPUT
n
OPEN LOAD wi th external pull-up
undefined
OVERTEMPE RATURE
INPUT
n
STATUS
n
T
TSD
T
R
Figure 1: Waveforms
T
j
OUTPUT VOLTAGE
n
VCC<V
OV
OUTPUT VOLTAGE
n
OUTPUT VOLTAGE
n
OUTPUT VOLTAGE
n
OUTP U T VO LTAGE
n
OUTPUT CURRENT
n
V
OUT>VOL
V
OL
VCC>V
OV
Page 8
8/19
VND810
GND PROTECTION NETWORK AGAINST REVERSE BATTERY
Soluti on 1: Resistor in the ground line (R
GND
only). This
can be us ed with any t ype of load . The fo llowin g is an indica tion on how to dim ension the
R
GND
resistor.
1) R
GND
600mV / I
S(on)max
.
2) R
GND
≥ (−VCC) / (-I
GND
)
where -I
GND
is the DC re vers e grou nd pi n cu rren t an d can
be found in the absolute maximum rating section of the
device’s datasheet. Power Dissipation in R
GND
(when VCC<0: during reverse
battery situations) is: P
D
= (-VCC)2/R
GND
This resistor can be shared amongst several different HSD. Please note that the value of this resis t o r sh ould be calcul ated with form ula (1) wher e I
S(on)max
becomes t he sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not common with the device ground then the R
GND
will
produce a shift (I
S(on)max
* R
GND
) in the input thresholds
and the status output values. This shift will vary
depending on how man y devic es are ON in the ca se of several high side drivers s haring the same R
GND
.
If the calculated power dissipation leads to a large resistor or seve ral de vic es have to s hare t he s ame r esisto r then the ST suggests to uti li ze Solution 2 (see below).
Solution 2:
A diode (D
GND
) in the gro und line.
A resistor (R
GND
=1kΩ) should be inserted in parallel to
D
GND
if the devi ce will be driving an inductive load.
This small signal diode can be safely shared amongst several different HSD . Also in this case, the presence of the ground network wi ll produce a shift (
j
600mV) in t he input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor netw ork.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are grea ter tha n the ones sh own in the ISO T/R 7637/1 table.
APPLICATION SCHEMATIC
V
CC
OUTPUT2
D
ld
+5V
R
prot
OUTPUT1
STA T US1
INPUT1
+5V
STA TUS2
INPUT2
GND
+5V
µ
C
R
prot
R
prot
R
prot
D
GND
R
GND
V
GND
Page 9
9/19
VND810
µ
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R
prot
)
in line to prevent the µC I/Os pins to latch-up. The valu e of these res istors is a compromise between
the leakage cur rent of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os.
-V
CCpeak/Ilatchup
R
prot
(V
OHµC-VIH-VGND
) / I
IHmax
Calculation example: For V
CCpeak
= - 100V an d I
latchup
20mA; V
OHµC
4.5V
5k R
prot
65k.
Recommended R
prot
value is 10kΩ.
Page 10
10/19
VND810
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (R
PU
) connected between OUTPUT pin and a
positive supply voltage (V
PU
) like the +5 V line used to
supply the microprocessor. The external resistor has to be selected according to the following requirements:
1) no f al se op en load i nd icat ion wh en load i s co nne cted : in thi s case we have to avoi d V
OUT
to be hi gher than
V
Olmin
; this results in the following condition
V
OUT
=(VPU/(RL+RPU))RL<V
Olmin.
2) no misdetection when load is disconnected: in this case the V
OUT
has to be higher than V
OLmax
; this
results in the following condition R
PU
<(V
PU–VOLma x
)/
I
L(off2)
.
Beca us e I
s(OFF)
may si gn ifi c a ntly increase if V
out
is pulled
high (up t o several mA ), the pul l-up resi stor R
PU
should
be conne cted t o a su pp ly t ha t is swit ch ed OFF when t h e module is in standby. The values of V
OLmin
, V
OLmax
and I
L(off2)
are available in
the Electrical Characteristics section.
V
OL
V batt. VPU
R
PU
R
L
R
DRIVER
+
LOGIC
+
-
INPUT
STATUS
V
CC
OUT
GROUND
I
L(off2)
Open Load detection in off state
Page 11
11/19
VND810
High Level Input Current
Input Clamp Voltage Status Leakage Current
Off State Output Current
Status Clamp VoltageStatus Low Output Voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.01
0.02
0.03
0.04
0.05
Ilstat (uA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Istat=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
0.16
0.32
0.48
0.64
0.8
0.96
1.12
1.28
1.44
1.6
IL(off1) (uA)
Off state
Vcc=36V
Vin=Vout=0V
Page 12
12/19
VND810
Input Hysteresis VoltageInput Low Level
On State Resistance Vs T
case
On State Resistance Vs V
CC
Input High LevelOpenload On State Detection Threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
10
15
20
25
30
35
40
45
50
55
60
Iol (mA)
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
Ron (mOhm)
Iout=0.5A
Vcc=8V; 13V & 36V
5 10152025303540
Vcc (V)
50
75
100
125
150
175
200
225
250
275
300
Ron (mOhm)
Iout=0.5A
Tc= - 40°C
Tc= 25°C
Tc= 150°C
Page 13
13/19
VND810
Overvoltage Shutdown
Turn-on Voltage Slope Turn-off Voltage Slope
I
LIM
Vs T
case
Openload Off State Voltage Detection Threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt(on) (V/ms)
Vcc=13V
Rl=13Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
50
100
150
200
250
300
350
400
450
500
dVout/dt(off) (V/ms)
Vcc=13V
Rl=13Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Ilim (A)
Vcc=13V
Page 14
14/19
VND810
Maximum turn off current versus load inductance
A = Single Pulse at T
Jstart
=150ºC
B= Repetitive pulse at T
Jstart
=100ºC
C= Repetitive Pulse at T
Jstart
=125ºC
Conditions: VCC=13.5V
Values are generated with RL=0 In case of repetitive pulses, T
jstart
(at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, I
L
t
Demagnetization
Demagnetization
Demagnetization
1
10
0.1 1 10 100 L(mH)
I
LMAX (A)
A
B
C
Page 15
15/19
VND810
SO-16 PC Boar d
R
thj-amb
Vs PCB copper area in open box free air condition
SO-16 THERMAL DATA
Layout condition of Rth and Zth measur ements (PCB FR4 area= 58mm x 58mm , PCB thick ness=1.6mm, Cu thickness=35µm, Copper areas: 0.26cm
2
, 4cm2).
40
45
50
55
60
65
70
75
80
85
012345
PC B Cu heatsink area (cm^2 )
RTH j-amb
(°C/W)
Page 16
16/19
VND810
Thermal fitting model of a doubl e channel H SD in SO-16
Pulse calculation formula
Thermal Parameter
Area/island (cm2)0.54
R1 (°C/W) 0.35 R2 (°C/W) 1.8 R3 ( °C/W) 4.5 R4 (°C/W) 10 R5 (°C/W) 16 R6 (°C/W) 48 25 C1 (W.s/°C) 0.0001 C2 (W.s/°C) 7.00E-04 C3 (W.s/°C) 6.00E-03 C4 (W.s/°C) 0.2 C5 (W.s/°C) 0.7 C6 (W.s/°C) 2 4
Z
THδ
RTHδ Z
THtp
1 δ()+=
where
δ tpT=
SO-16 Thermal Impedance Junction Ambient Single Pulse
T_amb
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2
R2
C1 C2
R1
Tj_1
Tj_2
0.01
0.1
1
10
100
1000
0.0001 0.001 0.01 0.1 1 10 100 1000 Tim e (s)
ZTH (°C/W)
0.26 cm
2
4 cm
2
Page 17
17/19
VND810
DIM.
mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068 a1 0.1 0.2 0.004 0.007 a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019 c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5 .8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 1.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.05 0
M 0.62 0.024
S8° (max.)
SO-16 MECHANICAL DATA
Page 18
18/19
VND810
SO-16 TUBE SHIPMENT (no suffi x)
1
All dimensions are in mm.
Base Q.ty 50 Bulk Q.ty 1000 Tube length (± 0.5) 532
A 3.2 B 6 C (± 0.1) 0.6
TAPE AND REEL SHIPMENT (suf fix “13TR”)
All dimensions are in mm.
Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13
F 20.2 G (+ 2 / -0) 16.4 N (min) 60 T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Associat ion (EIA) S tandard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 16 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets saled with cover tape.
User direction of feed
REEL DIMENSIONS
C
B
A
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VND810
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