The VNN7NV04, VNS7NV04, VND7NV04
VND7NV04-1, are mon ol ithi c devic es desi g ned in
STMicroelectronics VIPower M0-3 Technology,
intended for replacement of standard Power
MOSFETS from DC up to 50KHz applications.
Built in thermal shutdown, l inear curren t limitation
and overvoltage cla mp protects the chip in harsh
environments.
Fault feedback can be de tected by mon itori ng the
voltage at the input pin.
DRAIN
2
Overvoltage
Clamp
INPUT
1
Februa ry 20031/29
Gate
Control
Over
T emperature
Linear
Current
Limiter
3
SOURCE
FC01000
1
Page 2
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ABSOLUTE MAXIMUM RATI NG
SymbolParameter
Drain-source Voltage (VIN=0V)Intern ally ClampedV
Input VoltageInternally ClampedV
IN
Input Current +/-20mA
Minimum I nput Series Impedance150Ω
Drain Current Internally LimitedA
Reverse DC Output Current -10.5A
Electros tatic Discharge (R=1.5KΩ, C=100pF)4000V
Electros tatic Discharge on output pin only
(R=330Ω, C=150pF)
Total Dissipation at Tc=25°C74.660W
(*) Pulsed: Pu ls e duration = 300µs, duty c y c le 1.5%
Drain Current LimitVIN=5V; VDS=13V 6912A
=5V; VDS=13V
Step Response Current
Limit
Overtemperature
jsh
Shutdown
Overtemperature Reset135°C
jrs
Fault Sink CurrentVIN= 5V; VDS=13V; Tj=T
gf
Sing l e Pu lse
as
Avala nche Energy
V
IN
starti ng T
V
IN
=25°C; VDD=24V
j
=5V; R
gen=RIN MIN
(see figures 3 & 4)
jsh
=150Ω; L=24mH
4.0µs
150175200°C
15mA
200mJ
4/29
2
Page 5
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC to
50KHz. The only difference from the user’s
standpoint is that a small DC current I
100µA) flows into the INPUT pin in order to supply
ISS
(typ.
the internal circuitry.
The de vice integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics o f the Power MOSFET
stage giv e this device unrivall ed ruggedne ss and
energy handl ing capability. This feat ure is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current ID to I
voltage. When the current limiter is active, the
whatever the INPUT pin
lim
device operates in the linear region, so power
dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUI T
PROTECTION: these are based on sensing the
chip temperature and are not dependent on the
input voltage. The location of the sensi ng eleme nt
on the chip in the power st age ar ea ensures f ast,
accurate detection of the junction temperature.
Overtemperatur e cut-out occurs i n the range 1 50
to 190 °C, a typical value being 170 °C. The device
is automatically restarted when the chip
temperature fa lls of about 15°C be low shut-d own
temperature.
- STATUS FEEDBACK: in the case of an
overtemperature fault condition (Tj > T
device tries to sink a diagnostic current Igf thro ug h
jsh
), the
the INPUT pin in order to indicate fault condition. If
driven from a l ow impedance sou rce, this curre nt
may be used in orde r to warn the contr ol circ uit of
a device shut down. If the drive impeda nc e is h i gh
enough so that the INPUT pin dri ver is not abl e to
supply the current Igf, the INPUT pin will fall to 0V.
This will not however affect the device
operation: no requirement is put on the current
capability of t he IN PUT pin dr ive r e xcep t t o b e
able to supply the normal operation drive
current I
ISS
.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
5/29
1
Page 6
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Figure 1: Switching Time Test Circuit for Resistive Load
V
gen
I
D
90%
V
D
R
gen
t
r
t
V
gen
d(on)t
10%
Figure 2: Test Circuit for Diode Recovery Times
A
D
I
OMNIFET
S
150Ω
B
R
gen
FAST
DIODE
d(off)
I
t
f
A
B
OMNIFET
L=100uH
D
t
t
V
DD
6/29
1
V
gen
S
8.5 Ω
Page 7
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Figure 3: Unclamped Inductive Load Test Circuits
R
V
IN
P
GEN
W
Figur e 5: Input Charge Test Circuit
V
IN
Figure 4: Unclamped Inductive Waveforms
7/29
1
Page 8
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Source-Drain Diode Forward Characteristics
Vsd (mV)
1000
950
900
850
800
750
700
650
600
550
500
Vin=0V
0 2 4 6 8 101214
Id(A)
Derating Curve
Static Drain-Source On resistance Vs. Input
Voltage
Rds(on) (mOhm)
140
120
Tj=150ºC
100
80
Tj=25ºC
60
Tj=-40ºC
40
20
0
33.544.555.566.5
Vin(V)
Id=6A
Id=1A
Id=6A
Id=1A
Id=6A
Id=1A
Static Drain Source On Resistance
Rds(on) (mOhm)
500
450
400
350
300
250
200
150
100
50
0
00.250.50.7511.25
Tj= - 40ºC
Vin=2.5V
Tj=25ºC
Tj=150ºC
Id(A)
Static Drain-Source On resistance Vs. Input
Voltage
Normalized Input Threshold Voltage Vs.
Temperature
Vin(th)
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
-50 -250255075 100 125 150 175
T(ºC)
Vds=Vin
Id=1mA
Step Response Current Limit
Tdlim(us)
7
6.5
6
Vin=5V
Rg=150ohm
Current Limit Vs. Junction Temperature
Ilim (A)
15
14
13
12
11
10
9
8
7
6
5
Vds=13V
Vin=5V
-50 -250255075 100 125 150 175
Tj (ºC)
5.5
5
4.5
4
3.5
5 101520253035
Vdd(V)
11/29
1
11
Page 12
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SO-8 Maximum turn off current versus load inductance
LMAX (A)
I
100
10
A
B
C
1
0.010.1110100
A = Single Pulse at T
B= Repetitive pulse at T
C= Repetitive Pulse at T
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, T
the temperature specified above for curves B and C.
VIN, I
L
=150ºC
Jstart
=100ºC
Jstart
=125ºC
Jstart
jstart
Demagnetization
(at beginning of each demagnetization) of every pulse must not exceed
L(mH)
Demagnetization
Demagnetization
12/29
t
Page 13
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
DPAK Maximum turn off current versus load inductance
LMAX (A)
I
100
10
A
B
C
1
0.010.1110100
A = Single Pulse at T
B= Repetitive pulse at T
C= Repetitive Pulse at T
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, T
the temperature specified above for curves B and C.
VIN, I
L
=150ºC
Jstart
=100ºC
Jstart
=125ºC
Jstart
jstart
Demagnetization
(at beginning of each demagnetization) of every pulse must not exceed
L(mH)
Demagnetization
Demagnetization
t
13/29
Page 14
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SOT-223 Maximum turn off current versus load inductance
LMAX (A)
I
100
10
A
B
C
1
0.010.1110
A = Single Pulse at T
B= Repetitive pulse at T
C= Repetitive Pulse at T
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, T
the temperature specified above for curves B and C.
VIN, I
L
=150ºC
Jstart
=100ºC
Jstart
=125ºC
Jstart
jstart
Demagnetization
(at beginning of each demagnetization) of every pulse must not exceed
L(mH)
Demagnetization
Demagnetization
14/29
t
Page 15
SO-8 PC Board
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SO-8 THERMAL DATA
R
thj-amb
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 5 8m m , PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.14cm
Vs PCB copper area in open box free air condition
2
, 0.6cm2, 1.6cm2).
SO-8 at 4 pins connected to TAB
RTHj_amb
(ºC/W)
110
105
100
95
90
85
80
75
70
00.511.522.5
PCB CU heatsink are a (cm^2)
15/29
Page 16
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SOT-223 THERMAL DATA
SOT-223 PC Board
R
thj-amb
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 5 8m m , PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.11cm
2
, 1cm2, 2cm2).
Vs PCB copper area in open box free air condition
RTH j-amb (°C/W)
140
130
120
110
100
90
80
16/29
70
60
00.511.522.5
Cu area (cm^2)
Page 17
DPAK PC Board
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
DPAK THERMAL DATA
Layout condition of Rth and Zth measur em ents (PCB FR 4 area= 60mm x 60mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from mi nimum pad lay-out to 8c m
R
Vs PCB copper area in open box free air condition
thj-amb
RTH j_amb (ºC/W)
90
80
70
60
50
40
2
).
30
0246810
PCB CU heatsink area (cm^2)
17/29
Page 18
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
DPAK Thermal Impedance Junction Ambient Single Pulse
Information furnish ed is believed to be accurate and r eliable. However, STMicroel ec tronics ass um es no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise unde r any patent or patent rights of STMicroelect r onics. Specifications mentioned in this publication are
subject to c hange without notice. T his publication supersedes and replac es all information pr ev iously supplied. STMicroelectr on ics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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The ST logo is a trademark of STMicroele c tronics
2003 STMicroelectronics - Printed in ITALY- All Rights Reserved.
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