Datasheet UDA1360TS-N1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC01

2000 Feb 08

INTEGRATED CIRCUITS

UDA1360TS

Low-voltage low-power stereo
audio ADC

2000 Feb 08 2

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

FEATURES
General

• Low power consumption

• 2.4 to 3.6 V power supply

• Supports 256 and 384fs system clock

• Supports sampling frequency range of 5 to 55 kHz

• Small package size (SSOP16)

• Integrated high-pass filter to cancel DC offset

• Power-down mode

• Supports 2 V (RMS) input signals

• Easy application

• Non-inverting ADC plus decimation filter.

Multiple format output interface

• I2S-bus and MSB-justified format compatible

• Up to 20 significant bits serial output.

Advanced audio configuration

• Stereo single-ended input configuration

• High linearity, dynamic range and low distortion.

GENERAL DESCRIPTION

The UDA1360TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-powerportable digital audio equipment
which incorporates recording functions.

TheUDA1360TSsupportstheI2S-busdataformatandthe
MSB-justified data format with word lengths of up to
20 bits.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

analog supply voltage 2.4 3.0 3.6 V

V

DDD

digital supply voltage 2.4 3.0 3.6 V

I

DDA

analog supply current − 9 − mA

I

DDD

digital supply current − 3.5 − mA

T

amb

operating ambient temperature −40 − +85 °C

ADC

V

i(rms)

input voltage (RMS value) see Table 1 − 1.0 − V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−37 −33 dB

S/N signal-to-noise ratio V

I

= 0 V; A-weighted − 97 − dB

α

cs

channel separation − 100 − dB

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1360TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2000 Feb 08 3

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGM967

ADC

(Σ∆)

DECIMATION

FILTER

CLOCK

CONTROL

1

DC-CANCELLATION

FILTER

DIGITAL

INTERFACE

ADC

(Σ∆)

3

13

16

15 5 4 2

11
12

6

8

14

9

10

7

UDA1360TS

VINL

V

ref

VINR

V

ref(n)

V

ref(p)

SFOR

PWON

SYSCLK

V

DDD

V

SSD

BCK

WS

DATAO

FSEL

V

SSA

V

DDA

2000 Feb 08 4

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

PINNING

SYMBOL PIN DESCRIPTION

VINL 1 left channel input
V

ref

2 reference voltage
VINR 3 right channel input
V

ref(n)

4 ADC negative reference voltage
V

ref(p)

5 ADC positive reference voltage
SFOR 6 data format selection input
PWON 7 power control input
SYSCLK 8 system clock input 256 or 384f

s

V

DDD

9 digital supply voltage
V

SSD

10 digital ground
BCK 11 bit clock input
WS 12 word selection input
DATAO 13 data output
FSEL 14 system clock frequency select
V

SSA

15 analog ground
V

DDA

16 analog supply voltage

Fig.2 Pin configuration.

handbook, halfpage

UDA1360TS

MGM968

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

VINL

V

ref

VINR

V

ref(n)

V

ref(p)

SFOR

PWON

SYSCLK

V

DDD

V

SSD

BCK

WS

DATAO

FSEL

V

SSA

V

DDA

FUNCTIONAL DESCRIPTION
System clock

The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.

The options are 256fs (FSEL = LOW) and 384f

s

(FSEL = HIGH). The sampling frequency range is
5 to 55 kHz.

The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: f

BCK

≤ 128 × fWS.

Notes:

1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface.

2. For MSB justified formats it is important to have a WS
signal with 50% duty factor.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

Input level

The overall system gain is proportional to V

DDA

. The 0 dB
inputlevel is defined as that which gives a −1 dB FS digital
output(relativetothefull-scaleswing).Inaddition,an input
gain switch is incorporated with the above definitions.

The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 kΩ.

For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.

If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.

2000 Feb 08 5

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

Table 1 Application modes using input gain stage

Multiple format output interface

The UDA1360TS supports the following data output
formats;

• I2S-bus with data word length of up to 20 bits

• MSB-justifiedserial format with data word length of up to

20 bits.

Theoutput format can be set bythestatic SFOR pin. When
SFOR is LOW, the I2S-bus is selected, when SFOR is set
HIGH the MSB-justified format is selected.

Thedataformatsare illustrated in Fig.4. Left and right data
channel words are time multiplexed.

Decimation filter

The decimation from 128fs is performed in two stages.
The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.

Table 2 DC cancellation filter characteristics

Mute

On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:

; where f

s

= 44.1 kHz.

Power-down mode

The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.

Application modes

The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.

Table 3 Mode selection summary

RESISTOR

(12 kΩ)

INPUT GAIN

SWITCH

MAXIMUM INPUT

VOLTAGE

Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)

Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)

ITEM CONDITION

VALUE

(dB)

Pass-band ripple none
Pass-band gain 0
Stop band >0.55f

s

−60

Droop at 0.00045f

s

0.031

Attenuation at DC at 0.00000036f

s

>40

Dynamic range 0 to 0.45f

s

>110

PIN V

SS

1

⁄2V

DD

V

DD

SFOR I2S-bus test mode MSB
PWON power-down 0 dB gain 6 dB gain
FSEL 256f

s

− 384f

s

t

12288

f

s

----------------

279 ms==

2000 Feb 08 6

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V

DDD=VDDA

= 3 V; T

amb

=25°C; unless otherwise specified.

Notes

1. All V

DD

and VSS connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

digital supply voltage note 1 − 5.0 V

V

DDA

analog supply voltage note 1 − 5.0 V

T

xtal(max)

maximum crystal temperature − 150 °C

T

stg

storage temperature −65 +125 °C

T

amb

operating ambient temperature −40 +85 °C

V

es

electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

SYMBOL PARAMETER VALUE VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 140 K/W

Fig.3 Serial interface timing.

handbook, full pagewidth

MGM969

WS

BCK

DATAO

t

f

t

r

t

h;WS

t

s;WS

t

BCK(H)

t

BCK(L)

T

cy

t

d;DAT

t

d;DAT(WS)

t

h;DAT

2000 Feb 08 7

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

DC CHARACTERISTICS

V

DDD=VDDA

=3V; T

amb

=25°C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified.

Note

1. All power supply pins (V

DD

and VSS) must be connected to the same external power supply unit.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

analog supply voltage note 1 2.4 3.0 3.6 V

V

DDD

digital supply voltage note 1 2.4 3.0 3.6 V

I

DDA

analog supply current operation mode − 9 − mA

power-down mode − 3.5 − mA

I

DDD

digital supply current operation mode − 3.5 − mA

power-down mode − 0.5 − mA

Digital inputs

P

INS BCK, FSEL, SYSCLK AND WS

V

IH

HIGH-level input voltage 0.8V

DDD

− V

DDD

+ 0.5 V

V

IL

LOW-level input voltage −0.5 − 0.2V

DDD

V

I

LI

 input leakage current −−10 µA

C

I

input capacitance −−10 pF
PINS PWON AND SFOR
V

IH

HIGH-level input voltage 0.8V

DDD

− V

DDD

+ 0.5 V

V

IM

MIDDLE-level input voltage 0.3V

DDD

− 0.7V

DDD

V

V

IL

LOW-level input voltage −0.5 − 0.2V

DDD

V

Digital output; Pin DATAO

V

OH

HIGH-level output voltage IOH= −2 mA 0.85V

DDD

−− V

V

OL

LOW-level output voltage IOL=2mA −−0.4 V

Analog

V

ref

reference voltage referenced to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

R

I

input resistance − 12 − kΩ
C

I

input capacitance − 20 − pF

2000 Feb 08 8

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA

=3V; fi= 1 kHz; T

amb

=25°C; all voltages referenced to ground (pins10 and 15);

unless otherwise specified.

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA

= 2.7 to 3.6 V; T

amb

= −20 to +85 °C; all voltages referenced to ground (pins 10 and 15);

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

V

i(rms)

input voltage (RMS value) see Table 1 1.0 − V
∆V

i

unbalance between channels 0.1 − dB
(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −85 −80 dB
at −60 dB; A-weighted −37 −33 dB

S/N signal-to-noise ratio V

I

= 0 V; A-weighted 97 − dB

α

cs

channel separation 100 − dB
PSRR power supply rejection ratio 30 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

T

sys

clock cycle f

sys

= 256f

s

71 89 782 ns

f

sys

= 384f

s

47 59 522 ns

t

CWL

f

sys

LOW-level pulse width 0.4T

sys

− 0.6T

sys

ns

t

CWH

f

sys

HIGH-level pulse width 0.4T

sys

− 0.6T

sys

ns
Serial data timing (see Fig.3)
T

cy

bit clock cycle

1

⁄64f

s

−−ns

t

BCK(H)

bit clock HIGH time 100 −−ns

t

BCK(L)

bit clock LOW time 100 −−ns

t

r

rise time −−20 ns

t

f

fall time −−20 ns

t

d;DAT

data output delay time (from BCK
falling edge)

−−80 ns

t

d;DAT(WS)

data output delay time (from WS
edge)

MSB-justified format −−80 ns

t

h;DAT

data output hold time 0 −−ns

t

s;WS

word selection set-up time 20 −−ns

2000 Feb 08 9

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

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handbook, full pagewidth

MGM970

I2S-BUS FORMAT

123 1≥823

LSB MSB LSB MSBB2MSB

DATA

BCK

WS

B2

RIGHT

LEFT

≥8

MSB-JUSTIFIED FORMAT

123 1≥823

LSB MSB LSB MSBB2 B2MSB

DATA

BCK

WS

B2

RIGHT

LEFT

≥8

Fig.4 Serial interface formats.

2000 Feb 08 10

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

APPLICATION INFORMATION

Fig.5 Application diagram.

handbook, full pagewidth

MGM971

47 Ω

C11

47 µF (16 V)

C6
47 µF
(16 V)

C1

100 µF

(16 V)

C2
100 µF
(16 V)

C10
100 nF
(63 V)

R3

R7
47 kΩ

R6
47 kΩ

116

VINL

V

DDA

V

DDA

V

DDD

V

DDA

V

DDD

V

D

V

SSA

V

SSA

V

SSD

V

SSD

V

SSD

V

SSD

V

SSA

V

SSA

V

SSD

V

SSD

V

SSD

V

SSA

V

SSD

V

DDD

C5

47 µF

(16 V)

C9
100 nF
(63 V)

R2

R11

UDA1360TS

215

V

ref

R

in

314

VINR FSEL

413

V

ref(n)

DATAO

512

V

ref(p)

WS

611

SFOR BCK

710

PWON

89

SYSCLK

C4

47 µF

(16 V)

C8
100 nF
(63 V)

R1

1Ω

1Ω

1Ω

X1-1
X1-2

X1-4
X1-6

X1-7
X1-8
X1-9
X1-10

X1-5

X1-3

X3-1
X3-2
X3-3

X2-1

X4

X2-2
X2-3

R4
47 kΩ

47 Ω

R10

R5
47 kΩ

V

DDD

V

DDD

V

DDA

V

SSD

X5

C12

47 µF (16 V)

C3

47 µF

(16 V)

C7
100 nF
(63 V)

R

in

X6

L1 BLM32A07

L2 BLM32A07

2000 Feb 08 11

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

PACKAGE OUTLINE

UNIT A1A2A

3

b

p

cD

(1)E(1)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.15

0.00

1.4

1.2

0.32

0.20

0.25

0.13

5.30

5.10

4.5

4.3

0.65

6.6

6.2

0.65

0.45

0.48

0.18

10

0

o

o

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

1.0

SOT369-1 MO-152

95-02-04
99-12-27

w M

θ

A

A

1

A

2

b

p

D

y

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

0.25

18

16

9

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

A

max.

1.5

2000 Feb 08 12

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a very brief insight to acomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices (SMDs) or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leads on four sides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Feb 08 13

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

2000 Feb 08 14

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

NOTES

2000 Feb 08 15

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

69

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Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

Printed in The Netherlands 753503/25/02/pp16 Date of release: 2000 Feb 08 Document order number: 9397750 05031