Datasheet UDA1352TS Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

UDA1352TS

48 kHz IEC 60958 audio DAC

Preliminary speciﬁcation Supersedes data of 2002 May 22

2002 Nov 22

Page 2

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

CONTENTS

1 FEATURES

1.1 General

1.2 Control

1.3 IEC 60958 input

1.4 Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Clock regeneration and lock detection

8.2 Mute

8.3 Auto mute

8.4 Data path

8.5 Control 9 L3-BUS DESCRIPTION

9.1 General

9.2 Device addressing

9.3 Register addressing

9.4 Data write mode

9.5 Data read mode

9.6 Initialization string 10 I2C-BUS DESCRIPTION

10.1 Characteristics of the I2C-bus

10.2 Bit transfer

10.3 Byte transfer

10.4 Data transfer

10.5 Start and stop conditions

10.6 Acknowledgment

10.7 Device address

10.8 Register address

10.9 Write and read data

10.10 Write cycle

10.11 Read cycle

11 SPDIF SIGNAL FORMAT

11.1 SPDIF channel encoding

11.2 SPDIF hierarchical layers for audio data

11.3 SPDIF hierarchical layers for digital data

11.4 Timing characteristics 12 REGISTER MAPPING

12.1 SPDIF mute setting (write)

12.2 Power-down settings (write)

12.3 Volume control left and right (write)

12.4 Sound feature mode, treble and bass boost settings (write)

12.5 Mute (write)

12.6 Polarity (write)

12.7 SPDIF input settings (write)

12.8 Interpolator status (read-out)

12.9 SPDIF status (read-out)

12.10 Channel status (read-out)

12.11 FPLL status (read-out)

13 LIMITING VALUES 14 THERMAL CHARACTERISTICS 15 CHARACTERISTICS 16 TIMING CHARACTERISTICS 17 APPLICATION INFORMATION 18 PACKAGE OUTLINE 19 SOLDERING

19.1 Introduction to soldering surface mount packages

19.2 Reflow soldering

19.3 Wave soldering

19.4 Manual soldering

19.5 Suitability of surface mount IC packages for wave and reflow soldering methods

20 DATA SHEET STATUS 21 DEFINITIONS 22 DISCLAIMERS 23 PURCHASE OF PHILIPS I2C COMPONENTS

2002 Nov 22 2

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog

Converter (DAC)

• 256fs system clock output

• 20-bit data path in interpolator

• High performance

• No analog post filtering required for DAC

• Supporting sampling frequencies from 28 up to 55 kHz.

1.2 Control

• Controlled either by means of static pins, I2C-bus or L3-bus microcontroller interface.

1.3 IEC 60958 input

• On-chip amplifier for converting IEC 60958 input to CMOS levels

• Lock indication signal available on pin LOCK

• Information ofthe Pulse Code Modulation (PCM) status

bit and the non-PCM data detection is available on pin PCMDET

• Forleftand right 40 key channel-status bits available via L3-bus or I2C-bus interface.

1.4 Digital sound processing and DAC

• Automatic de-emphasis when using IEC 60958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by means of a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interface

• Left and right independent dB linear volume control with

0.25 dB steps from 0 to −50 dB, 1 dB steps to −60,

−66 and −∞ dB

• Bass boost and treble control in L3-bus or I2C-bus mode

• Interpolating filter (fsto 64fs) by means of a cascade of

a recursive filter and a FIR filter

• Fifth-order noise shaper (operating at 64fs) generates the bitstream for the DAC

• Filter Stream DAC (FSDAC).

2 APPLICATIONS

• Digital audio systems.

3 GENERAL DESCRIPTION

The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques.

A lock indication signal is available on pin LOCK, indicating that the IEC 60958 decoder is locked. A separate pin PCMDET is available to indicate whether or not the PCM data is applied to the input.

By default, the DAC output is muted when the decoder is out-of-lock. However, this setting can be overruled in the L3-bus or I2C-bus mode.

The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package.

Besides the UDA1352TS, the UDA1352HL is also available. The UDA1352HL is the full featured version in LQFP48 package.

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1352TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

2002 Nov 22 3

NAME DESCRIPTION VERSION

PACKAGE

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

5 QUICK REFERENCE DATA

DDD=VDDA

to ground; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

DDA

DDA(DAC)

DDA(PLL)

DDD(C)

DDD

P power dissipation DAC in playback mode − 38 − mW

General

rst

amb

Digital-to-analog converter

o(rms)

∆V

(THD+N)/S total harmonic

S/N signal-to-noise ratio f

= 3.0 V; IEC 60958 input with fs= 48.0 kHz; T

=25°C; RL=5kΩ; all voltages measured with respect

amb

digital supply voltage 2.7 3.0 3.6 V analog supply voltage 2.7 3.0 3.6 V analog supply current of DAC power-on − 3.3 − mA

power-down; clock off − 35 −µA analog supply current of PLL − 0.3 − mA digital supply current of core − 9 − mA digital supply current − 0.3 − mA

DAC in Power-down mode − tbf − mW

reset active time − 250 −µs ambient temperature −40 − +85 °C

output voltage (RMS value) fi= 1.0 kHz tone at 0 dBFS; note 1 850 900 950 mV unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB

= 1.0 kHz tone

distortion-plus-noise to signal ratio

at 0 dBFS −−82 −77 dB at −40 dBFS; A-weighted −−60 −52 dB

= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB

channel separation fi= 1.0 kHz tone − 110 − dB

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

2002 Nov 22 4

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

6 BLOCK DIAGRAM

handbook, full pagewidth

DDA(PLL)

SSA(PLL)

DDD(C)

SSD(C)

DA0 DA1

L3MODE

L3CLOCK

L3DATA

SELSTATIC

SELIIC

SPDIF

DDD

SSD

DDA(DAC)

TEST12TEST2

24 23

28 25

9 8

26 4

3 7

n.c.

CLOCK

TIMING CIRCUIT

L3-BUS

C-BUS

OR I INTERFACE

SLICER

21, 22, 27

AND

IEC 60958

DECODER

PCMDET

UDA1352TS

NON-PCM DATA

SYNC

DETECTOR

LOCK

VOUTL

DAC

AUDIO FEATURE PROCESSOR

SSA(DAC)

NOISE SHAPER

INTERPOLATOR

ref

VOUTR

DAC

MUTE

RESET

MGU655

Fig.1 Block diagram.

2002 Nov 22 5

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

PCMDET 1 DO PCM detection indicator output TEST1 2 DO test pin 1; must be left open-circuit in application V

DDD

SELIIC 4 DID I

3 DS digital supply voltage

C-bus or L3-bus mode selection input RESET 5 DID reset input V

DDD(C)

SSD

L3DATA 8 IIC L3-bus or I L3CLOCK 9 DIS L3-bus or I

6 DS digital supply voltage for core 7 DGND digital ground

C-bus interface data input and output

C-bus interface clock input L3MODE 10 DIS L3 interface mode input MUTE 11 DID mute control input V

SSD(C)

12 DGND digital ground for core SPDIF 13 AIO IEC 60958 channel input V

DDA(DAC)

14 AS analog supply voltage for DAC VOUTL 15 AIO DAC left channel analog output LOCK 16 DO SPDIF and PLL lock indicator output VOUTR 17 AIO DAC right channel analog output TEST2 18 DID test pin 2; must be connected to digital ground (V V

ref

SSA(DAC)

19 AIO DAC reference voltage

20 AGND analog ground for DAC n.c. 21 − not connected n.c. 22 − not connected V

SSA(PLL)

DDA(PLL)

23 AGND analog ground for PLL

24 AS analog supply voltage for PLL DA1 25 DISU A1 device address selection input SELSTATIC 26 DIU static pin control selection input n.c. 27 − not connected (reserved) DA0 28 DID A0 device address selection input

) in application

SSD

Note

1. See Table 1.

2002 Nov 22 6

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

Table 1 Pin types

TYPE DESCRIPTION

DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DISU digital Schmitt-triggered input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output IIC input and open-drain output for I AIO analog input and output

C-bus

handbook, halfpage

DDA(DAC)

PCMDET

TEST1

DDD

SELIIC

RESET

DDD(C)

SSD

L3DATA

L3CLOCK

L3MODE

MUTE

SSD(C)

SPDIF

1 2 3 4 5 6 7

UDA1352TS

9 10 11 12 13 14

MGU654

DA0

n.c.

SELSTATIC

DA1

V n.c.

n.c.

21 20

V V

TEST2

VOUTR

LOCK

VOUTL

DDA(PLL) SSA(PLL)

SSA(DAC) ref

Fig.2 Pin configuration.

2002 Nov 22 7

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

8 FUNCTIONAL DESCRIPTION

8.1 Clock regeneration and lock detection

The UDA1352TS contains an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream.

Remark: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band.

When the on-board clock locks to the incoming frequency, the lock indicator bit is set and can be read via the L3-bus or I2C-bus interface. Internally, the PLL lock indication can be combined with the PCM status bit of the input data stream and the status whether any burst preamble is detected or not. By default, when both the IEC 60958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level. This combination of the lock status and the PCM detection can be overruled by the L3-bus or I2C-bus register setting.

handbook, halfpage

mute

factor

0.8

0.6

0.4

0.2

01051525

Fig.3 Mute as a function of raised cosine roll-off.

MGU119

t (ms)

The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal).

TheUDA1352TShasadedicatedpin PCMDET to indicate whether valid PCM data stream is detected or (supposed to be) non-PCM data is detected.

8.2 Mute

The UDA1352TS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC (by pin MUTE or via bit MT in the L3-bus or I2C-bus mode) will result in a soft mute as shown in Fig.3. The cosine roll-off soft mute takes 32 × 32 samples = 23 ms at

44.1 kHz sampling frequency. When operating in the L3-bus or I2C-bus mode, the device

will mute on start-up. In the L3-bus or I2C-bus mode, it is necessary to explicitly switch off the mute for audio output by means of bit MT in the device register.

In the L3-bus or I2C-bus mode, pin MUTE will at all time mute the output signal. This is in contrast to the UDA1350 and the UDA1351 in which pin MUTE in the L3-bus mode does not have any function.

8.3 Auto mute

By default, the DAC outputs will be muted until the UDA1352TS is locked, regardless of the level on pin MUTEorthe state of bit MT. In this way, only validdata will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute.

If needed, this muting can be bypassed by setting bit MUTEBP = 1 via the L3-bus or I2C-bus interface. As a result, the UDA1352TS will no longer mute during out-of-lock situations.

2002 Nov 22 8

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

8.4 Data path

The UDA1352TS data path consists of the IEC 60958 decoder, the audio feature processor, the digital interpolator and noise shaper and the DACs.

8.4.1 IEC 60958 INPUT The IEC 60958 decoder features an on-chip amplifier with

hysteresis, which amplifies the SPDIF input signal to CMOS level (see Fig.4).

All 24 bits of data for left and right are extracted from the inputbitstreamaswellas40 channel status bits for left and right. These bits can be read via the L3-bus or I2C-bus interface.

handbook, halfpage

75 Ω

10 nF

180 pF

13SPDIF

UDA1352TS

MGU656

8.4.2 AUDIO FEATURE PROCESSOR The audio feature processor automatically provides

de-emphasis for the IEC 60958 data stream in the static pincontrol mode and default muteat start-up in the L3-bus or I2C-bus mode.

When used in the L3-bus or I2C-bus mode, it provides the following additional features:

• Left and right independent volume control

• Bass boost control

• Treble control

• Mode selection of the sound processing bass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off.

8.4.3 INTERPOLATOR The UDA1352TS includes an on-board interpolating filter

which converts the incoming data stream from 1fsto 64f by cascading a recursive filter and a FIR filter.

Table 2 Interpolator characteristics

PARAMETER CONDITIONS VALUE (dB)

Pass-band ripple 0 to 0.45f Stop band >0.55f Dynamic range 0 to 0.45f

±0.03

−50

114

DC gain −−5.67

Fig.4 IEC 60958 input circuit and typical

application.

The UDA1352TS supports the following sample frequencies and data bit rates:

• fs= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

• fs= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

• fs= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.

The UDA1352TS supports timing levels I, II and III, as specified by the IEC 60958 standard. This means that the accuracy of the above mentioned sampling frequencies depends on the timing level I, II or III as mentioned in Section 11.4.1.

2002 Nov 22 9

8.4.4 NOISE SHAPER The fifth-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper outputisconvertedtoananalogsignalusingafilterstream DAC.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

8.4.5 FILTER STREAM DAC The Filter Stream DAC (FSDAC) is a semi-digital

reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage.

The filter coefficients are implemented as current sources andaresummedatvirtualground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due tothe inherent filter function of the DAC. On-board amplifiers convert the FSDAC

8.5 Control

TheUDA1352TS can be controlled by means of static pins (when pin SELSTATIC = HIGH), via the I2C-bus (when pin SELSTATIC = LOWandpin SELIIC = HIGH) or viathe L3-bus (when pins SELSTATIC and SELIIC are LOW). For optimum use of the features of the UDA1352TS, the L3-bus or I2C-bus mode is recommended since only basic functions are available in the static pin control mode.

It should be noted that the static pin control mode and the

L3-bus or I2C-bus mode are mutually exclusive. output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC is scaled proportionally with the power supply voltage.

8.5.1 STATIC PIN CONTROL MODE

The default values for all non-pin controlled settings are

identical to the default values at start-up in the L3-bus or

I2C-bus mode (see Table 3).

Table 3 Pin description of static pin control mode

PIN NAME VALUE FUNCTION

Mode selection pin

26 SELSTATIC 1 select static pin control mode; must be connected to V

DDD

Input pins

5 RESET 0 normal operation

1 reset

9 L3CLOCK 0 must be connected to V

10 L3MODE 0 must be connected to V

8 L3DATA 0 must be connected to V

SSD SSD SSD

11 MUTE 0 no mute

1 mute active

Status pins

1 PCMDET 0 non-PCM data or burst preamble detected

1 PCM data detected

16 LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected

1 clock regeneration and IEC 60958 decoder locked and PCM data detected

Test pins

2 TEST1 − must be left open-circuit

18 TEST2 0 must be connected to V

SSD

2002 Nov 22 10

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

8.5.2 L3-BUS OR I2C-BUS MODE The L3-bus or I2C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4). It should be noted that in the L3-bus or I2C-bus mode, several base-line functions are still controlled by pins on the device

and that, on start-up in the L3-bus or I2C-bus mode, the output is explicitly muted by bit MT via the L3-bus or I2C-bus interface.

Table 4 Pin description in the L3-bus or I

PIN NAME VALUE FUNCTION

Mode selection pins

26 SELSTATIC 0 select L3-bus mode or I

4 SELIIC 0 select L3-bus mode; must be connected to V

1 select I2C-bus mode; must be connected to V

Input pins

5 RESET 0 normal operation

1 reset

8 L3DATA − must be connected to the L3-bus

− must be connected to the SDA line of the I2C-bus

9 L3CLOCK − must be connected to the L3-bus

− must be connected to the SCL line of the I2C-bus 10 L3MODE − must be connected to the L3-bus 11 MUTE 0 no mute

1 mute active

Status pins

1 PCMDET 0 non-PCM data or burst preamble detected

1 PCM data detected

16 LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected

1 clock regeneration and IEC 60958 decoder locked and PCM data detected

Test pins

2 TEST1 − must be left open-circuit

18 TEST2 0 must be connected to V

C-bus mode

C-bus mode; must be connected to V

SSD

DDD

SSD

2002 Nov 22 11

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

9 L3-BUS DESCRIPTION

9.1 General

The UDA1352TS has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller.

The controllable settings are:

• Restoring L3-bus default values

• Power-on

• Selection of filter mode and settings of treble and bass

boost

• Volume settings left and right

• Selection of soft mute via cosine roll-off and bypass of

auto mute.

The readable settings are:

• Mute status of interpolator

• PLL locked

• SPDIF input signal locked

• Audio sample frequency

• Valid PCM data detected

• Pre-emphasis of the IEC 60958 input signal

• Accuracy of the clock.

Theexchange of data and control informationbetween the microcontroller and the UDA1352TS is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins:

• L3DATA: data line

• L3MODE: mode line

• L3CLOCK: clock line.

The L3-bus format has two modes of operation:

• Address mode

• Data transfer mode.

The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulseson L3CLOCK, accompanied by 8 bits (seeFig.5). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data.

Basically, two types of data transfers can be defined:

• Write action: data transfer to the device

• Read action: data transfer from the device.

Remark: when the device is powered-up, at least one L3CLOCK pulse must be given to the L3-bus interface to wake-uptheinterfacebeforestartingsendingtothedevice (see Fig.5). This is only needed once after the device is powered-up.

9.2 Device addressing

The device address consists of 1 byte with:

• Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 5)

• Address bits 2 to 7 representing a 6-bit device address. The bits 2 and 3 of the address can be selected via the external pins DA0 and DA1, which allows up to 4 UDA1352TSdevicestobeindependentlycontrolledin a single application.

The primary address of the UDA1352TS is ‘001000’ (LSB to MSB) and the default address is ‘011000’.

Table 5 Selection of data transfer

DOM

TRANSFER

BIT 0 BIT 1

0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data

9.3 Register addressing

After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address.

Basically, there are three methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a

write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.5)

2. Addressing for prepare read: bit 0 is logic 1, indicating

that data will be read from the register (see Fig.6)

3. Addressing for data read action. Here, the device

returns a register address prior to sending data from thatregister.Whenbit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid.

2002 Nov 22 12

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

MBL565

MGS753

data byte 1 data byte 2

write

Fig.5 Data write mode (for L3-bus version 2).

device address

10 0

DOM bits

0/1

valid/invalid

Fig.6 Data read mode.

read

prepare read send by the device

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2002 Nov 22 13

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

L3DATA

L3CLOCK

device address

L3MODE

111 0

DOM bits

L3DATA

Page 14

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

9.4 Data write mode

The data write mode is explained in the signal diagram of Fig.5. For writing data to a device, 4 bytes must be sent (see Table 6):

1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1352TS default)

2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination register address in binary format with A6 being the MSB and A0 being the LSB

3. One data byte (from the two data bytes) with D15 being the MSB

4. One data byte (from the two data bytes) with D0 being the LSB.

Itshouldbenotedthateachtimea new destination register address needs to be written, the device address must be sent again.

9.5 Data read mode

To read data from the device, a prepare read must first be doneand then data read. The data read modeis explained in the signal diagram of Fig.6.

For reading data from a device, the following 6 bytes are involved (see Table 7):

1. One byte with the device address, including ‘01’ for signalling the write action to the device

2. One byte is sent with the register address from which data needs to be read; this byte starts with a ‘1’, which indicates that there will be a read action from the register, followed by seven bits for the source register address in binary format, with A6 being the MSB and A0 being the LSB

3. One byte with the device address preceded by ‘11’ is sent to the device; the ‘11’ indicates that the device must write data to the microcontroller

4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whetherthe requested register was valid (bit islogic 0) or invalid (bit is logic 1)

5. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D15 being the MSB

6. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D0 being the LSB.

Table 6 L3-bus write data

BYTE

1 address device address 0 1 DA0 DA1 1000 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

Table 7 L3-bus read data

BYTE

1 address device address 0 1 DA0 DA1 1000 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 DA0 DA1 1000 4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0 5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

L3-BUS

MODE

L3-BUS

MODE

ACTION

FIRST IN TIME LAST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LAST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2002 Nov 22 14

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

9.6 Initialization string

For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8.

Table 8 L3-bus initialization string and set defaults after power-up

BYTE

L3-BUS

MODE

ACTION

FIRST IN TIME LAST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

1 address init string device address 0 1 DA0 DA1 1 0 0 0 2 data transfer register address 0 1 0 0 0 0 0 0 3 data transfer data byte 1 0 0 0 0 0 0 0 0 4 data transfer data byte 2 0 0 0 0 0 0 0 1 5 address set 6 data transfer register address 0 1 1 1 1 1 1 1

defaults

device address 0 1 DA0 DA1 1 0 0 0

7 data transfer data byte 1 0 0 0 0 0 0 0 0 8 data transfer data byte 2 0 0 0 0 0 0 0 0

10 I2C-BUS DESCRIPTION

10.1 Characteristics of the I

C-bus

10.2 Bit transfer

One data bit is transferred during each clock pulse (see Fig.7).Thedata on the SDA line must remain stable during

The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA)andaserialclockline (SCL).Bothlinesmustbe

the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz.

connected to the VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used,

To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this

high-speed I

C-bus according to specification

I2C-bus and how to use it”

, (order code 9398 393 40011).

“The

between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

Fig.7 Bit transfer on the I2C-bus.

2002 Nov 22 15

change

of data

allowed

MBC621

Page 16

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

10.3 Byte transfer

Each byte (8 bits) is transferred with the MSB first (see Table 9).

Table 9 Byte transfer

MSB BIT NUMBER LSB

76543210

10.4 Data transfer

A device generating a message is a transmitter, a device receiving a message is the receiver. The device that

handbook, full pagewidth

SDA

SCL

controls the message is the master and the devices which are controlled by the master are the slaves.

10.5 Start and stop conditions

Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Fig.8. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P).

SDA

SCL

START condition

Fig.8 START and STOP conditions on the I2C-bus.

10.6 Acknowledgment

The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.9). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

STOP condition

MBC622

The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

2002 Nov 22 16

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

START

condition

Fig.9 Acknowledge on the I2C-bus.

10.7 Device address

Before any data is transmitted on the I2C-bus, the device whichshouldrespondisaddressedfirst.Theaddressingis always done with byte 1 transmitted after the start procedure.

The device address can be one out of four, being set by pin DA0 and pin DA1.

The UDA1352TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1352TS device address is shown in Table 10.

9821

clock pulse for

acknowledgement

MBC602

10.8 Register address

The register addresses in the I

C-bus mode are the same

as in the L3-bus mode.

10.9 Write and read data

The I2C-bus configuration for a write and read cycle are shown respectively in Tables 11 and 12. The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. It is also possible to read these locations for the device status information.

Table 10 I

C-bus device address

DEVICE ADDRESS R/

A6 A5 A4 A3 A2 A1 A0 −

1 0 0 1 1 DA1 DA0 0/1

2002 Nov 22 17

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

(1)

DATA n

(1)

C-bus configuration for a writecycle is shown in Table 11. The write cycle is used to write thedata to the internal registers. The device and register

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10.10 Write cycle

The I

C-bus mode.

DAT A 1 DATA 2

acknowledge from UDA1352TS

C-bus and the microcontroller can generate a stop condition (P).

ADDRESS

R/W

DEVICE

ADDRESS

acknowledge is followed from the UDA1352TS.

UDA1352TS.

addresses are one byte each, the setting data is always a pair of two bytes.

The format of the write cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1352TS.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start.

5. The UDA1352TS acknowledges this register address (A).

6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an

7. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the

8. Finally, the UDA1352TS frees the I

Table 11 Master transmitter writes to the UDA1352TS registers in the I

S 1001 110 0 A ADDR A MS1 A LS1 A MS2 A LS2 A MSn A LSn A P

Note

1. Auto increment of register address.

2002 Nov 22 18

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

(1)

DATA n

(1)

C-bus configuration for a read cycle is shown in Table 12.

C-bus and the microcontroller can generate a stop condition (P).

C-bus mode.

R/W DATA 1 DATA 2

DEVICE

ADDRESS

R/W

acknowledge from UDA1352TS acknowledge from master

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10.11 Read cycle

The read cycle is used to read the data values from the internal registers. The I

2002 Nov 22 19

is followed from the UDA1352TS.

acknowledge is followed from the microcontroller.

The format of the read cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1352TS.

4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1352TS must start.

5. The UDA1352TS acknowledges this register address.

6. Then the microcontroller generates a repeated start (Sr).

8. The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an

7. Then the microcontroller generates the device address ‘1001 110’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge

9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the

microcontroller.

10. The microcontroller stops this cycle by generating a negative acknowledge (NA).

11. Finally, the UDA1352TS frees the I

Table 12 Master transmitter reads from the UDA1352TS registers in the I

DEVICE

ADDRESS

S 1001 110 0 A ADDR A Sr 1001 110 1 A MS1 A LS1 A MS2 A LS2 A MSn A LSn NA P

Note

1. Auto increment of register address.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

11 SPDIF SIGNAL FORMAT

11.1 SPDIF channel encoding

The digital signal is coded using Bi-phase Mark Code (BMC), which is a kind of phase-modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. An example of the encoding is given in Fig.10.

handbook, halfpage

clock

data

BMC

MGU606

Fig.10 Bi-phase mark encoding.

11.2 SPDIF hierarchical layers for audio data

From an abstract point of view an SPDIF signal can be represented as in Fig.11. A 2-channel PCM signal can be transmitted as various sequential blocks. Each block in turn consists of 192 frames. Each frame contains two sub-frames, one for each channel.

Each sub-frame is preceded by a preamble. There are three types of preambles being B, M and W. Preambles can be spotted easily in an SPDIF stream because these sequences can never occur in the channel parts of a valid SPDIF stream. Table 13 indicates the values of the preambles.

A sub-frame in turn contains a single audio sample which may be up to 24 bits wide, a validity bit which indicates whether the sample is valid, a single bit of user data, and a single bit of channel status. Finally, there is a parity bit for this particular sub-frame (see Fig.12).

Table 13 Preambles

PRECEDING

STATE

CHANNEL CODING 01

B 1110 1000 0001 0111 M 1110 0010 0001 1101 W 1110 0100 0001 1011

11.3 SPDIF hierarchical layers for digital data

The difference with the audio format is that the data contained in the SPDIF signal is not audio but is digital data.

When transmitting digital data via SPDIF using the IEC 60958 protocol, the allocation of the bits inside the data word is done as shown in Table 14.

Table 14 Bit allocation for digital data

FIELD

IEC 60958 TIME

SLOT BITS

DESCRIPTION

0 to 3 preamble according to IEC 60958 4 to 7 auxiliary bits not used; all logic 0 8 to 11 unused data bits not used; all logic 0 12 16 bits data sections of the digital

bitstream 13 user data according to IEC 60958 14 to 27 16 bits data sections of the digital

bitstream 28 validity bit according to IEC 60958 29 user data according to IEC 60958 30 channel status bit according to IEC 60958 31 parity bit according to IEC 60958

As shown in Table 14 and Fig.13, the non-PCM encoded data bitstreams are transferred within the basic 16 bits data area of the IEC 60958 sub-frames [time-slots 12 (LSB) to 27 (MSB)].

The data bits from 4 to 31 in each sub-frame will be modulated using a BMC scheme. The sync preamble actually contains a violation of the BMC scheme and consequently can be detected easily.

2002 Nov 22 20

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

handbook, full pagewidth

channel 1MMMWW WBchannel 2 channel 1

channel 2 channel 1 channel 2 channel 1 channel 2

handbook, full pagewidth

03478 27 28 31

sync preamble

L S B

auxiliary

sub-frame

L S B

sub-frame

frame 0 frame 191frame 191

Fig.11 SPDIF block format.

block

validity flag

user data

channel status

parity bit

MGU607

CUV

MGU608

Paudio sample word

Fig.12 Sub-frame format in audio mode.

unused data

11 12

L S B

handbook, full pagewidth

03478 27 28 31

sync preamble

L S B

auxiliary

L S B

Fig.13 Sub-frame format in non-PCM mode.

2002 Nov 22 21

validity flag

user data

channel status

parity bit

M S B

CUV

MGU609

P16-bit data stream

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

11.3.1 FORMAT OF THE BITSTREAM The non-PCM data is transmitted in data bursts, consisting of four 16-bit words (called Pa, Pb, Pc and Pd) followed by

the so called burst-payload. The definition of the burst preambles is given in Table 15.

Table 15 Burst preamble words

PREAMBLE WORD LENGTH OF THE FIELD CONTENTS VALUE

Pa 16 bits sync word 1 F872 (hex) Pb 16 bits sync word 2 4E1F (hex) Pc 16 bits burst information see Table 16 Pd 16 bits length code number of bits

11.3.2 BURST INFORMATION The burst information given in preamble Pc, meaning the information contained in the data stream, is defined according

to IEC 60958 as given in Table 16.

Table 16 Fields of burst information in preamble Pc

BITS OF Pc VALUE CONTENTS

0 to 4 0 NULL data − none

1 AC-3 data R_AC-3 1536 2 reserved −− 3 pause bit 0 of Pa refer to IEC 60958 4 MPEG-1 layer 1 data bit 0 of Pa 384 5 MPEG-1 layer 1, 2 or 3 data or MPEG-2

without extension 6 MPEG-2 with extension bit 0 of Pa 1152 7 reserved −− 8 MPEG-2, layer 1 low sampling rate bit 0 of Pa 768 9 MPEG-2, layer 2 or 3 low sampling rate bit 0 of Pa 2304 10 reserved −− 11 to 13 reserved (DTS) − refer to IEC 61937 14 to 31 reserved −−

5 to 6 0 reserved −−

7 0 error ﬂag indicating a valid burst-payload −−

1 error ﬂag indicating an invalid

burst-payload

8to12 − data type dependant information −−

13 to 15 0 bitstream number −−

REFERENCE

POINT R

bit 0 of Pa 1152

−−

REPETITION TIME OF

DATA BURST IN

IEC 60958 FRAMES

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

11.3.3 MINIMUM BURST SPACING In order to be able to detect the start of a data burst, it is

prescribed to have a data-burst which does not exceed 4096 frames. After 4096 frames there must be a synchronization sequence containing 2 frames of complete zero data (being 4 times 16 bits) followed by the preamble burst Pa and Pb. In this way a comparison with a sync code of 96 bits can detect the start of a new burst-payload including the Pc and Pd preambles containing additional stream information.

11.4 Timing characteristics

11.4.1 FREQUENCY REQUIREMENTS The SPDIF specification IEC 60958 supports three levels

of clock accuracy, being:

• Level I, high accuracy: tolerance of transmitting sampling frequency shall be within 50 × 10

−6

• Level II, normal accuracy: all receivers should receive a signal of 1000 × 10−6 of nominal sampling frequency

• Level III,variablepitchshiftedclockmode:a deviation of

12.5% of the nominal sampling frequency is possible.

11.4.2 RISE AND FALL TIMES

Rise and fall times (see Fig.14) are defined as:

Rise time =

-------------------tLtH+()

100%×

Rise and fall times should be in the range:

• 0% to 20% when the data bit is a logic 1

• 0% to 10% when the data bits are two succeeding logic

zeros.

11.4.3 DUTY CYCLE The duty cycle (see Fig.14) is defined as:

Duty cycle =

-------------------tLtH+()

100%×

The duty cycle should be in the range:

• 40% to 60% when the data bit is a logic 1

• 45% to 55%whenthedatabitsaretwo succeeding logic

zeros.

handbook, halfpage

90% 50% 10%

MGU612

Fall time =

-------------------tLtH+()

100%×

2002 Nov 22 23

Fig.14 Rise and fall times.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

12 REGISTER MAPPING Table 17 Register map of control settings (write)

ADDRESS

System settings

01H SPDIF mute setting 03H power-down settings

Interpolator

10H volume control left and right 12H sound feature mode, treble and bass boost 13H mute 14H polarity

SPDIF input settings

30H SPDIF input settings

Software reset

7FH restore L3-bus default values

Table 18 Register map of status bits (read-out)

ADDRESS

Interpolator

18H interpolator status

SPDIF input

59H SPDIF status 5AH channel status bits left [15:0] 5BH channel status bits left [31:16] 5CH channel status bits left[39:32] 5DH channel status bits right [15:0] 5EH channel status bits right [31:16] 5FH channel status bits right [39:32]

FPLL

68H FPLL status

FUNCTION

2002 Nov 22 24

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Philips Semiconductors Preliminary speciﬁcation

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12.1 SPDIF mute setting (write) Table 19 Register address 01H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−MUTEBP Default −−−−−−−0

BIT 76543210

Symbol −−−−−−−− Default −−−−−000

Table 20 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 9 − reserved

8 MUTEBP Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute

bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected, the output data will not be suppressed. If this bit is logic 0, then the output will be muted in out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock

situations. Default value0. 7to3 − reserved 2to0 − When writing new settings via the L3-bus or I

remain at logic 0 (default value) to guarantee correct operation.

C-bus interface, these bits should always

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Philips Semiconductors Preliminary speciﬁcation

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12.2 Power-down settings (write) Table 21 Register address 03H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−− Default −−−−−−−−

BIT 76543210

Symbol −−−PON_

SPDIFIN

Default −−−10011

Table 22 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 5 − reserved

4 PON_SPDIFIN Power control SPDIF input. A 1-bit value to enable or disable the power of

the IEC 60958 bit slicer. If this bit is logic 0, then the power is off. If this bit is logic 1, then the power is on. Default value 1.

3to2 − When writing new settings via the L3-bus or I2C-bus interface, these bits

should always remain at logic 0 (default value) to guarantee correct operation.

1 EN_INT Interpolator clock control. A 1-bit value to control the interpolator clock.

If this bit is logic 0, then the interpolator clock is disabled. If this bit is logic 1, then the interpolator clock is enabled. Default value 1.

0 PONDAC Power control DAC. A 1-bit value to switch the DAC into power-on or

Power-down mode. If this bit is logic 0, then the DAC is in Power-down mode. If this bit is logic 1, then the DAC is in power-on mode. Default value 1.

−−EN_INT PONDAC

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Philips Semiconductors Preliminary speciﬁcation

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12.3 Volume control left and right (write) Table 23 Register address 10H

BIT 15 14 13 12 11 10 9 8

Symbol VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0 Default 00000000

BIT 76543210

Symbol VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0 Default 00000000

Table 24 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 8 VCL_[7:0] Volume setting left channel. A 8-bit value to program the left channel volume

attenuation. The range is 0 to −50 dB in steps of 0.25 dB, to −60 dB in steps of 1 dB,

−66 dB and −∞ dB. Default value 0000 0000; see Table 25.

7 to 0 VCR_[7:0] Volume setting right channel. A 8-bit value to program the right channel volume

attenuation. The range is 0 to −50 dB in steps of 0.25 dB, to −60 dB in steps of 1 dB,

−66 dB and −∞ dB. Default value 0000 0000; see Table 25.

Table 25 Volume settings left and right channel

VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0 VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0

000000000 (default) 00000001−0.25 00000010−0.5

::::::::: 11000111−49.75 11001000−50 11001100−51 11010000−52

::::::::: 11110000−60 11110100−66 11111000−∞ 11111100−∞

::::::::: 11111111−∞

VOLUME (dB)

2002 Nov 22 27

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Philips Semiconductors Preliminary speciﬁcation

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12.4 Sound feature mode, treble and bass boost settings (write) Table 26 Register address 12H

BIT 15 14 13 12 11 10 9 8

Symbol M1 M0 TR1 TR0 BB3 BB2 BB1 BB0 Default 0 0 0 0 0 0 0 0

BIT76543210

Symbol −−−−−−−− Default −−−−−−−−

Table 27 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 14 M[1:0] Sound feature mode. A 2-bit value to program the sound processing filter sets (modes) of

bass boost and treble. Default value 00; see Table 28.

13 to 12 TR[1:0] Treble settings. A 2-bit value to program the treble setting. The set is selected by the

mode bits. Default value 00; see Table 29.

11 to 8 BB[3:0] Bass boost settings. A 4-bit value to program the bass boost settings. The set is selected

by the mode bits. Default value 0000; see Table 30.

7to0 − reserved

Table 28 Sound feature mode

M1 M0 MODE SELECTION

0 0 ﬂat set (default) 0 1 minimum set 10 1 1 maximum set

Table 29 Treble settings

TR1 TR0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB)

00000 01022 10044 11066

2002 Nov 22 28

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

Table 30 Bass boost settings

BB3 BB2 BB1 BB0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB)

0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 10 10 0110 0 12 12 0111 0 14 14 1000 0 16 16 1001 0 18 18 1010 0 18 20 1011 0 18 22 1100 0 18 24 1101 0 18 24 1110 0 18 24 1111 0 18 24

2002 Nov 22 29

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Philips Semiconductors Preliminary speciﬁcation

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12.5 Mute (write) Table 31 Register address 13H

BIT 15 14 13 12 11 10 9 8

Symbol QMUTE MT GS −−−−− Default 0 1 0 −−000

BIT76543210

Symbol −−−−−−−− Default −−−−−−−−

Table 32 Description of register bits

BIT SYMBOL DESCRIPTION

15 QMUTE Quick mute function. A 1-bit value to set the quick mute mode. If this bit is logic 0, then

the soft mute mode is selected. If this bit is logic 1, then the quick mute mode is selected. Default value 0.

14 MT Mute. A 1-bit value to set the mute function. If this bit is logic 0, then the audio output is not

muted (unless pin MUTE is logic 1). If this bit is logic 1, then the audio output is muted. Default value 1.

13 GS Gain select. A 1-bit value to set the gain of the interpolator path. If this bit is logic 0, then

the gain is 0 dB. If this bit is logic 1, then the gain is 6 dB. Default value 0.

12 to 11 − reserved

10 to 8 − When writing new settings via the L3-bus or I2C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

7to0 − reserved

2002 Nov 22 30

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Philips Semiconductors Preliminary speciﬁcation

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12.6 Polarity (write) Table 33 Register address 14H

BIT 15 14 13 12 11 10 9 8

Symbol DA_POL_

INV

Default 0 1 −−−−10

BIT76543210

Symbol −−−−−−−− Default 0 −−−−−−−

Table 34 Description of register bits

BIT SYMBOL DESCRIPTION

15 DA_POL_INV DAC polarity control. A 1-bit value to control the signal polarity of the DAC output

14 − When writing new settings via the L3-bus or I

13 to 10 − reserved

9 − When writing new settings via the L3-bus or I

8to7 − When writing new settings via the L3-bus or I

6to0 − reserved

−−−−−−−

signal. If this bit is logic 0, then the DAC output is not inverted. If this bit is logic 1, then the DAC output is inverted. Default value 0.

C-bus interface, this bit should always

remain at logic 1 (default value) to guarantee correct operation.

C-bus interface, this bit should always

remain at logic 1 (default value) to guarantee correct operation.

C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

2002 Nov 22 31

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Philips Semiconductors Preliminary speciﬁcation

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12.7 SPDIF input settings (write) Table 35 Register address 30H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−− Default −−−−−−−−

BIT76543210

Symbol −−−−COMBINE_

PCM

Default −−−−1100

Table 36 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 4 − reserved

3 COMBINE_PCM Combine PCM detection to lock indicator. A 1-bit value to combine the PCM detection

status to the lock indicator. If this bit is logic 0, then the lock indicator does not contain PCM detection status. If this bit is logic 1, then the PCM detection status is combined with the lock indicator. Default value 1.

2 BURST_

DET_EN

1to0 − When writing new settings via the L3-bus or I

Burst preamble settings. A 1-bit value to enable auto mute when burst preambles are detected. If this bit is logic 0, then there is no muting. If this bit is logic 1, then there is muting when preambles are detected. Default value 1.

remain at logic 0 (default value) to guarantee correct operation.

BURST_ DET_EN

C-bus interface, these bits should always

−−

2002 Nov 22 32

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Philips Semiconductors Preliminary speciﬁcation

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12.8 Interpolator status (read-out) Table 37 Register address 18H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−−

BIT76543210

Symbol −−−−−MUTE_

STATE

Table 38 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 3 − reserved

2 MUTE_STATE Mute status bit. A 1-bit value to indicate the status of the mute function. If this bit is

logic 0, then the audio output is not muted. If this bit is logic 1, then the mute sequence has been completed and the audio output is muted.

1to0 − reserved

−−

2002 Nov 22 33

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

12.9 SPDIF status (read-out) Table 39 Register address 59H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−−

BIT76543210

Symbol −−−−−BURST_

DET

Table 40 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 3 − reserved

2 BURST_DET Burst preamble detection. A 1-bit value to signal whether burst preamble words are

detected in the SPDIF stream or not. If this bit is logic 0, then no preamble words are detected. If this bit is logic 1, then burst-payload is detected.

1 B_ERR Bit error detection. A 1-bit value to signal whether there are bit errors detected in the

SPDIF stream or not. If this bit is logic 0, then no errors are detected. If this bit is logic 1, then bi-phase errors are detected.

0 SPDIFIN_LOCK SPDIF lock indicator. A 1-bit value to signal whether the SPDIF decoder block is in

lock or not. If this bit is logic 0, then the decoder block is out-of-lock. If this bit is logic 1, then the decoder block is in lock.

B_ERR SPDIFIN_

LOCK

2002 Nov 22 34

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

12.10 Channel status (read-out)

12.10.1 CHANNEL STATUS BITS LEFT [15:0]

Table 41 Register address 5AH

BIT 15 14 13 12 11 10 9 8

Symbol SPDI_

BIT15

BIT76543210

Symbol SPDI_

BIT7

SPDI_

BIT14

SPDI_

BIT6

SPDI_

BIT13

SPDI_

BIT5

SPDI_

BIT12

SPDI_

BIT4

SPDI_

BIT11

SPDI_

BIT3

SPDI_

BIT10

SPDI_

BIT2

SPDI_

BIT9

SPDI_

BIT1

SPDI_

BIT8

SPDI_

BIT0

12.10.2 C

HANNEL STATUS BITS LEFT [31:16]

Table 42 Register address 5BH

BIT 15 14 13 12 11 10 9 8

Symbol SPDI_

BIT31

SPDI_

BIT30

SPDI_

BIT29

SPDI_

BIT28

SPDI_

BIT27

SPDI_

BIT26

SPDI_

BIT25

SPDI_

BIT24

BIT76543210

Symbol SPDI_

BIT23

12.10.3 C

HANNEL STATUS BITS LEFT [39:32]

SPDI_

BIT22

SPDI_

BIT21

SPDI_

BIT20

SPDI_

BIT19

SPDI_

BIT18

SPDI_

BIT17

SPDI_

BIT16

Table 43 Register address 5CH

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−−

BIT76543210

Symbol SPDI_

BIT39

12.10.4 C

HANNEL STATUS BITS RIGHT [15:0]

SPDI_

BIT38

SPDI_

BIT37

SPDI_

BIT36

SPDI_

BIT35

SPDI_

BIT34

SPDI_

BIT33

SPDI_

BIT32

Table 44 Register address 5DH

BIT 15 14 13 12 11 10 9 8

Symbol SPDI_

BIT15

SPDI_

BIT14

SPDI_

BIT13

SPDI_

BIT12

SPDI_

BIT11

SPDI_

BIT10

SPDI_

BIT9

SPDI_

BIT8

BIT76543210

Symbol SPDI_

BIT7

SPDI_

BIT6

SPDI_

BIT5

SPDI_

BIT4

SPDI_

BIT3

SPDI_

BIT2

SPDI_

BIT1

SPDI_

BIT0

2002 Nov 22 35

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

12.10.5 CHANNEL STATUS BITS RIGHT [31:16]

Table 45 Register address 5EH

BIT 15 14 13 12 11 10 9 8

Symbol SPDI_

BIT31

BIT76543210

Symbol SPDI_

BIT23

SPDI_

BIT30

SPDI_

BIT22

SPDI_

BIT29

SPDI_

BIT21

SPDI_

BIT28

SPDI_

BIT20

SPDI_

BIT27

SPDI_

BIT19

SPDI_

BIT26

SPDI_

BIT18

SPDI_

BIT25

SPDI_

BIT17

SPDI_

BIT24

SPDI_

BIT16

12.10.6 C

Table 46 Register address 5FH

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−−

BIT76543210

Symbol SPDI_

Table 47 Description of register bits (two times 40 bits indicating the left and right channel status)

BIT SYMBOL DESCRIPTION

39 to 36 − reserved but undeﬁned at present 35 to 33 SPDI_BIT[35:33] Word length. A 3-bit value indicating the word length; see Table 48.

31 to 30 SPDI_BIT[31:30] reserved 29 to 28 SPDI_BIT[29:28] Clock accuracy. A 2-bit value indicating the clock accuracy; see Table 49. 27 to 24 SPDI_BIT[27:24] Sample frequency. A 4-bit value indicating the sampling frequency; see Table 50. 23 to 20 SPDI_BIT[23:20] Channel number. A 4-bit value indicating the channel number; see Table 51. 19 to 16 SPDI_BIT[19:16] Source number. A 4-bit value indicating the source number; see Table 52.

15 to 8 SPDI_BIT[15:8] General information. A 8-bit value indicating general information; see Table 53.

7 to 6 SPDI_BIT[7:6] Mode. A 2-bit value indicating mode 0; see Table 54. 5 to 3 SPDI_BIT[5:3] Audio sampling. A 3-bit value indicating the type of audio sampling; see Table 55.

HANNEL STATUS BITS RIGHT [39:32]

SPDI_

BIT39

32 SPDI_BIT[32] Audio sample word length. A 1-bit value to signal the maximum audio sample word

2 SPDI_BIT2 Software copyright. A 1-bit value indicating software for which copyright is asserted

1 SPDI_BIT1 Audio sample word. A 1-bit value indicating the type of audio sample word. If this bit is

0 SPDI_BIT0 Channel status. A 1-bit value indicating the consumer use of the status block. This bit

BIT38

length. If bit 32 is logic 0, then the maximum length is 20 bits. If bit 32 is logic 1, then the maximum length is 24 bits.

or not. If this bit is logic 0, then copyright is asserted. If this bit is logic 1, then no copyright is asserted.

logic 0, then the audio sample word represents linear PCM samples. If this bit is logic 1, then the audio sample word is used for other purposes.

is logic 0.

SPDI_

BIT37

SPDI_

BIT36

SPDI_

BIT35

SPDI_

BIT34

SPDI_

BIT33

SPDI_

BIT32

2002 Nov 22 36

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

Table 48 Word length

SPDI_BIT35 SPDI_BIT34 SPDI_BIT33

SPDI_BIT32 = 0 SPDI_BIT32 = 1

0 0 0 word length not indicated (default) word length not indicated (default) 0 0 1 16 bits 20 bits 0 1 0 18 bits 22 bits 0 1 1 reserved reserved 1 0 0 19 bits 23 bits 1 0 1 20 bits 24 bits 1 1 0 17 bits 21 bits 1 1 1 reserved reserved

Table 49 Clock accuracy

SPDI_BIT29 SPDI_BIT28 CLOCK ACCURACY

0 0 level II 01levelI 1 0 level III 1 1 reserved

Table 50 Sampling frequency

SPDI_BIT27 SPDI_BIT26 SPDI_BIT25 SPDI_BIT24 SAMPLING FREQUENCY

000044.1 kHz 000148kHz 001032kHz

::::other states reserved

1111

WORD LENGTH

Table 51 Channel number

SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 CHANNEL NUMBER

0000don’t care 0001A(left for stereo transmission) 0010B(right for stereo transmission) 0011C 0100D 0101E 0110F 0111G 1000H 1001I 1010J 1011K

2002 Nov 22 37

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 CHANNEL NUMBER

1100L 1101M 1110N 1111O

Table 52 Source number

SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 SOURCE NUMBER

0000don’t care 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115

2002 Nov 22 38

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

Table 53 General information

SPDI_BIT[15:8] FUNCTION

000 00000 general

100 xxxxL laser optical products 010 xxxxL digital-to-digital converters and signal processing products 110 xxxxL magnetic tape or disc based products 001 xxxxL broadcast reception of digitally encoded audio signals with video signals 011 1xxxL broadcast reception of digitally encoded audio signals without video signals

101 xxxxL musical instruments, microphones and other sources without copyright information 011 00xxL analog-to-digital converters for analog signals without copyright information 011 01xxL analog-to-digital converters for analog signals which include copyright information in the

form of ‘Cp- and L-bit status’

000 1xxxL solid state memory based products 000 0001L experimental products not for commercial sale

111 xxxxL reserved

000 0xxxL reserved, except 000 0000 and 000 0001L

Table 54 Mode

SPDI_BIT7 SPDI_BIT6 MODE

0 0 mode 0 0 1 reserved 10 11

Table 55 Audio sampling

SPDI_BIT5 SPDI_BIT4 SPDI_BIT3

SPDI_BIT1 = 0 SPDI_BIT1 = 1

0 0 0 2 audio samples without

pre-emphasis

0 0 1 2 audio samples with 50/15 µs

pre-emphasis

0 1 0 reserved (2 audio samples with

pre-emphasis)

0 1 1 reserved (2 audio samples with

pre-emphasis)

: : : other states reserved

111

AUDIO SAMPLE

default state for applications other than linear PCM

other states reserved

2002 Nov 22 39

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

12.11 FPLL status (read-out) Table 56 Register address 68H

BIT 15 14 13 12 11 10 9 8

Symbol −−−−−−−FPLL_

LOCK

BIT76543210

Symbol −−−VCO_

TIMEOUT

Table 57 Description of register bits

BIT SYMBOL DESCRIPTION

15 to 9 − reserved 8 FPLL_LOCK FPLL lock. A 1-bit value that indicates the FPLL status together with bit 4; see Table 58. 7to5 − reserved 4 VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8;

see Table 58.

3to0 − reserved

−−−−

Table 58 Lock status indicators of the FPLL

FPLL_LOCK VCO_TIMEOUT FUNCTION

0 0 FPLL out-of-lock 0 1 FPLL time-out 1 0 FPLL in lock 1 1 FPLL time-out

2002 Nov 22 40

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

13 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

stg

amb

esd

lu(prot)

sc(DAC)

Notes

1. All VDD and VSS connections must be made to the same power supply.

2. JEDEC class 2 compliant.

3. JEDEC class B compliant.

4. DAC operation after short-circuiting cannot be warranted.

supply voltage note 1 2.7 5.0 V storage temperature −65 +125 °C ambient temperature −40 +85 °C electrostatic discharge voltage Human Body Model (HBM); note 2 −2000 +2000 V

Machine Model (MM); note 3 −200 +200 V latch-up protection current T short-circuit current of DAC T

= 125 °C; VDD= 3.6 V − 200 mA

amb

=0°C; VDD= 3 V; note 4

amb

output short-circuited to V output short-circuited to V

SSA(DAC) DDA(DAC)

− 20 mA

− 100 mA

14 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 110 K/W

15 CHARACTERISTICS

DDD=VDDA

= 3.0 V; IEC 60958 input with fs= 48.0 kHz; T

=25°C; RL=5kΩ; all voltages measured with respect

amb

to ground; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies; note 1

DDA

DDA(DAC)

DDA(PLL)

DDD

DDD(C)

DDA(DAC)

analog supply voltage 2.7 3.0 3.6 V analog supply voltage for DAC 2.7 3.0 3.6 V analog supply voltage for PLL 2.7 3.0 3.6 V digital supply voltage 2.7 3.0 3.6 V digital supply voltage for core 2.7 3.0 3.6 V analog supply current of DAC power-on − 3.3 − mA

power-down; clock off − 35 −µA

DDA(PLL)

DDD(C)

DDD

analog supply current of PLL − 0.3 − mA digital supply current of core − 9 − mA digital supply current − 0.3 − mA

P power dissipation DAC in playback mode − 38 − mW

DAC in Power-down mode − tbf − mW

2002 Nov 22 41

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs

I

 input leakage current −−10 µA

pu(int)

pd(int)

HIGH-level input voltage 0.8V LOW-level input voltage −0.5 − +0.2V

input capacitance −−10 pF internal pull-up resistance 16 33 78 kΩ internal pull-down resistance 16 33 78 kΩ

Digital outputs

O(max)

HIGH-level output voltage IOH= −2 mA 0.85V LOW-level output voltage IOL=2mA −−0.4 V maximum output current − 3 − mA

Digital-to-analog converter; note 2 V

o(rms)

output voltage (RMS value) fi= 1.0 kHz tone at

850 900 950 mV

0 dBFS; note 3

∆V

ref

(THD+N)/S total harmonic

S/N signal-to-noise ratio f

unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB reference voltage measured with respect to

SSA

= 1.0 kHz tone

distortion-plus-noise to signal ratio

at 0 dBFS −−82 −77 dB at −40 dBFS; A-weighted −−60 −52 dB

= 1.0 kHz tone; code = 0;

0.45V

95 100 − dB

A-weighted

channel separation fi= 1.0 kHz tone − 110 − dB

SPDIF input

i(p-p)

AC input voltage

0.2 0.5 3.3 V

(peak-to-peak value)

hys

input resistance − 6 − kΩ hysteresis voltage − 40 − mV

Notes

1. All supply pins VDD and VSS must be connected to the same external power supply unit.

2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 Ω must be used to prevent oscillations in the output stage of the operational amplifier.

3. The output voltage of the DAC is proportional to the DAC power supply voltage.

− V

DDD

−− V

DDD

0.50V

DDA

DDD

0.55V

+ 0.5 V

DDD

DDA

2002 Nov 22 42

Page 43

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

16 TIMING CHARACTERISTICS

DDD=VDDA

otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Device reset

rst

PLL lock time

lock

L3-bus microcontroller interface; see Figs 15 and 16 T

cy(CLK)(L3)

CLK(L3)H

CLK(L3)L

su(L3)A

h(L3)A

su(L3)D

h(L3)D

(stp)(L3)

su(L3)DA

h(L3)DA

d(L3)R

dis(L3)R

C-bus microcontroller interface; see Fig 17

SCL

LOW

HIGH

HD;STA

SU;STA

SU;STO

BUF

= 2.4 to 3.6 V; T

= −40 to +85 °C; RL=5kΩ; all voltages measured with respect to ground; unless

amb

reset active time − 250 −µs

time-to-lock fs= 32.0 kHz − 85.0 − ms

= 44.1 kHz − 63.0 − ms

= 48.0 kHz − 60.0 − ms

L3CLOCK cycle time 500 −−ns L3CLOCK HIGH time 250 −−ns L3CLOCK LOW time 250 −−ns L3MODE set-up time in address mode 190 −−ns L3MODE hold time in address mode 190 −−ns L3MODE set-up time in data transfer mode 190 −−ns L3MODE hold time in data transfer mode 190 −−ns L3MODE stop time in data transfer mode 190 −−ns L3DATA set-up time in address and data

190 −−ns

transfer mode L3DATA hold time in address and data

30 −−ns

transfer mode L3DATA delay time in data transfer mode 0 − 50 ns L3DATA disable time for read data 0 − 50 ns

SCL clock frequency 0 − 400 kHz SCL LOW time 1.3 −−µs SCL HIGH time 0.6 −−µs rise time SDA and SCL note 1 20 + 0.1Cb− 300 ns fall time SDA and SCL note 1 20 + 0.1Cb− 300 ns hold time start condition 0.6 −−µs set-up time START condition 0.6 −−µs set-up time STOP condition 0.6 −−µs bus free time between a STOP and START

1.3 −−µs

condition

2002 Nov 22 43

Page 44

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SU;DAT

HD;DAT

Note

1. Cb is the total capacity of one bus line.

data set-up time 100 −−ns data hold time 0 −−µs pulse width of spikes to be suppressed by

0 − 50 ns

the input ﬁlter capacitive load for each bus line − 400 pF

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

h(L3)A

CLK(L3)L

su(L3)DA

CLK(L3)H

BIT 0

su(L3)A

Fig.15 Timing for address mode.

h(L3)DA

su(L3)A

h(L3)A

cy(CLK)(L3)

BIT 7

MGL723

2002 Nov 22 44

Page 45

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

write

L3DATA

read

su(L3)D

stp(L3)

CLK(L3)L

CLK(L3)H

h(L3)DA

BIT 0

d(L3)R

su(L3)DA

Fig.16 Timing for data transfer mode.

cy(CLK)L3

BIT 7

dis(L3)R

h(L3)D

MBL566

handbook, full pagewidth

SDA

HIGH

SU;STA

SCL

HD;DAT

SU;DAT

LOW

HD;STA

Fig.17 Timing of the I2C-bus transfer.

2002 Nov 22 45

HD;STA

SU;STO

BUF

MSC610

Page 46

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

17 APPLICATION INFORMATION

RST

123

DDD

NORM

n.c.

n.c. n.c.

RESET

TEST2

DDA(PLL)

SSA(PLL)

left_out

C14

10 µF

(16 V)

100 Ω

C15

100 nF

(50 V)

C17

47 µF

Vref

2722

182423

VOUTL

10 kΩ

(16 V)

C18

VOUTR

right_out

100 Ω

47 µF

10 kΩ

(16 V)

UDA1352TS

C-bus

L3-bus or

STATIC

231

DDD

no mute

mute

231

DDD

MUTE

SELSTATIC

C-bus

123

DDD

SELIIC

L3-bus

28 25

DDD

DA1

LOCK DA0

PCMDET

1 kΩ

MGU657

DDD

HLMP-1385 (2x)

handbook, full pagewidth

Fig.18 Application diagram.

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2002 Nov 22 46

BLM31A601S

DDA

(50 V)

100 nF

(16 V)

100 µF

DDA(DAC)

BLM31A601S

DDA

SSA(DAC)

C13

(50 V)

100 nF

C12

(16 V)

100 µF

L3MODE

L3CLOCK

L3DATA

SPDIF

10 nF

(50 V)

180 pF

R10

(50 V)

75 Ω

DDD(C)

BLM31A601S

DDD

SSD(C)

(50 V)

100 nF

(16 V)

100 µF

DDD

C11

C10

1 Ω

SSD

100 nF

100 µF

(50 V)

(16 V)

DDAVDDD

+3 V

C21

C20

100 µF

(16 V)

GND

Page 47

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

18 PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

28 15

pin 1 index

SOT341-1

(A )

v M

114

w M

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

max.

0.21

0.05

1.80

1.65

IEC JEDEC EIAJ

2.0

OUTLINE

VERSION

SOT341-1 MO-150

0.25

0.38

0.25

0.20

0.09

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

5.4

10.0

REFERENCES

0.65 1.25

5.2

2002 Nov 22 47

detail X

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

1.1

0.7

ISSUE DATE

95-02-04 99-12-27

Page 48

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

19 SOLDERING

19.1 Introduction to soldering surface mount

packages

Thistextgivesaverybriefinsighttoacomplextechnology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for certainsurfacemountICs,butitisnotsuitableforfinepitch SMDs. In these situations reflow soldering is recommended.

19.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied totheprinted-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages.

19.3 Wave soldering

Conventional single wave soldering is not recommended forsurfacemountdevices(SMDs)orprinted-circuitboards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

19.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

2002 Nov 22 48

Page 49

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

19.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

PACKAGE

(1)

SOLDERING METHOD

WAVE REFLOW

(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

not suitable

(3)

suitable

HVSON, SMS

(4)

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended

, SO, SOJ suitable suitable

(4)(5)

suitable

(6)

suitable

Notes

1. Formoredetailed information on the BGA packages refer to the

“(LF)BGAApplicationNote

”(AN01026);ordera copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2002 Nov 22 49

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

20 DATA SHEET STATUS

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

21 DEFINITIONS

22 DISCLAIMERS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device attheseoratanyotherconditionsabove those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationorwarrantythatsuchapplications will be suitable for the specified use without further testing or modification.

Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to resultin personal injury. Philips Semiconductorscustomersusingorsellingthese products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352TS

23 PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

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Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753503/02/pp52 Date of release: 2002 Nov 22 Document order number: 9397 750 10469

SCA74

Datasheet UDA1352TS Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual