Datasheet UDA1351TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1351TS

96 kHz IEC 958 audio DAC

Preliminary specification
File under Integrated Circuits, IC01

2000 Mar 28

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

CONTENTS

1 FEATURES

1.1 General

1.2 Control

1.3 IEC 958 input

1.4 Digital sound processing and DAC
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Clock regeneration and lock detection

8.2 Mute

8.3 Auto mute

8.4 Data path

8.4.1 IEC 958 input

8.4.2 Audio feature processor

8.4.3 Interpolator

8.4.4 Noise shaper

8.4.5 The Filter Stream DAC (FSDAC)

8.5 Control

8.5.1 Static pin control mode

8.5.2 L3 control mode

8.6 L3 interface

8.6.1 General

8.6.2 Device addressing

8.6.3 Register addressing

8.6.4 Data write mode

8.6.5 Data read mode

8.6.6 initialization string

8.6.7 Overview of L3 interface registers

8.6.8 Writable registers

8.6.9 Readable registers

9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 TIMING CHARACTERISTICS
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS

2000 Mar 28 2

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog Converter

(DAC)

• Master-mode dataoutput and input interface for off-chip
sound processing

• 256fssystem clock output

• 20-bit data path in interpolator

• High performance

• No analog post filtering required for DAC

• Support sampling frequencies from 28 kHz up

to 100 kHz

• The UDA1351TS is fully pin and function compatible
with the UDA1350ATS.

1.2 Control

Controlled either by means of static pins or via the
L3 microcontroller interface.

1.3 IEC 958 input

• On-chip amplifier for convertingIEC 958 inputto CMOS
levels

• Lock indication signal available on pin LOCK

• Lock indication signal combined on-chip with the Pulse

Code Modulation (PCM) status bit; when non-PCM is
detected, pin LOCK indicates out-of-lock

• Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, two channel
PCM indication and clock accuracy).

2 APPLICATIONS

Digital audio systems.

3 GENERAL DESCRIPTION

Available in two versions:

• UDA1351TS:
– only IEC 958 input to DAC in SSOP28 package.

• UDA1351H:
– full featured version in QFP44 package.

The UDA1351TS is a single chip IEC 958 audio decoder
with an integrated stereo DAC employing bitstream
conversion techniques.

A lock indication signal is available on pin LOCK,
indicating that the IEC 958 decoder is locked. This pin is
also used to indicate whether PCM data is applied to the
input or not. When non-PCM data is detected, the device
indicates out-of-lock.

By default, the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.

1.4 Digital sound processing and DAC

• Automatic de-emphasis when using IEC 958 input with

32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by meansof acosine roll-offcircuit selectable
via pin MUTE or the L3 interface

• dB linear volume control with 1 dB steps from 0 dB to

−60 dB and −∞ dB

• Bass boost and treble control in L3 control mode

• Interpolating filter (fsto 128fs) by means ofa cascade of

a recursive filter and a FIR filter

• Third order noise shaper operating at 128fsgenerates
the bitstream for the DAC

• Filter Stream DAC (FSDAC).

2000 Mar 28 3

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDD

V

DDA

I

DDA(DAC)

I

DDA(PLL)

I

DDD(C)

I

DDD

P power consumption at 48 kHz DAC in playback mode − 80 − mW

General

t

rst

T

amb

Digital-to-analog converter

V

o(rms)

(THD + N)/S total harmonic

S/N signal-to-noise ratio at 48 kHz f

α

cs

∆V

o

digital supply voltage 2.7 3.0 3.6 V
analog supply voltage 2.7 3.0 3.6 V
analog supply current of DAC power-on − 8.0 − mA

power-down − 750 −µA

analog supply current of PLL at 48 kHz − 0.7 − mA

at 96 kHz − 1.0 − mA

digital supply current of core at 48 kHz − 16.0 − mA

at 96 kHz − 24.5 − mA

digital supply current at 48 kHz − 2.0 − mA

at 96 kHz − 3.0 − mA

DAC in Power-down mode − 58 − mW

power consumption at 96 kHz DAC in playback mode − 109 − mW

DAC in Power-down mode − 87 − mW

reset active time − 250 −µs
ambient temperature −40 − +85 °C

output voltage (RMS value) note 1 − 900 − mV

f

= 1.0 kHz tone at 48 kHz

i

distortion-plus-noise to signal
ratio

at 0 dB −−90 −85 dB
at −40 dB; A-weighted −−60 −55 dB

f

= 1.0 kHz tone at 96 kHz

i

at 0 dB −−85 −80 dB
at −40 dB; A-weighted −−57 −52 dB

= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB

i

signal-to-noise ratio at 96 kHz f

= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB

i

channel separation fi= 1.0 kHz tone − 96 − dB
unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1351TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

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Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

6 BLOCK DIAGRAM

handbook, full pagewidth

V

DDA(PLL)

V

SSA(PLL)

V

DDD(C)

L3MODE

L3CLOCK

L3DATA

SELSTATIC

SPDIF

V

DDD

V

SSD

V

SSD(C)

24
23

TIMING CIRCUIT

6

10

9
8

26

13

3
7
12

n.c.

TEST1 TEST3

CLOCK

AND

L3

INTERFACE

SLICER

1, 2, 27

TEST2

18

4

IEC 958

DECODER

16

LOCK

TEST4

28

UDA1351TS

V

SSA

V

DDA

21

25

22

V

DDA(DAC)

V

VOUTL

DAC

AUDIO FEATURE PROCESSOR

SSA(DAC)

14

15

NOISE SHAPER

INTERPOLATOR

V

ref

VOUTR

19

20

DAC

17

11

MGU032

MUTE

5

RESET

Fig.1 Block diagram.

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Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

n.c. 1 − not connected
n.c. 2 − not connected
V

DDD

TEST1 4 DID test pin 1; must be connected to digital ground (V

3 DS digital supply voltage

SSD

)
RESET 5 DISD reset input
V

DDD(C)

V

SSD

6 DS digital supply voltage for core

7 DGND digital ground
L3DATA 8 DIOS L3 interface data input and output
L3CLOCK 9 DIS L3 interface clock input
L3MODE 10 DIS L3 interface mode input
MUTE 11 DID mute control input
V

SSD(C)

12 DGND digital ground
SPDIF 13 AI IEC 958 channel input
V

DDA(DAC)

14 AS analog supply voltage for DAC
VOUTL 15 AO analog DAC left channel output
LOCK 16 DO SPDIF and PLL lock indicator output
VOUTR 17 AO analog DAC right channel output
TEST2 18 DID test pin 2; must be connected to digital ground (V
V

ref

V

SSA(DAC)

V

SSA

V

DDA

V

SSA(PLL)

V

DDA(PLL)

19 A DAC reference voltage

20 AGND analog ground for DAC

21 AGND analog ground

22 AS analog supply voltage

23 AGND analog ground for PLL

24 AS analog supply voltage for PLL

SSD

)

TEST4 25 DIU test pin 4; must be connected to the digital supply voltage (V
SELSTATIC 26 DIU static pin control selection input
n.c. 27 − not connected
TEST3 28 DISD test pin 3; must be connected to digital ground (V

SSD

)

DDD

)

Note

1. See Table 1.

2000 Mar 28 6

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

Table 1 Pin type references

PIN TYPE DESCRIPTION

DS digital supply
DGND digital ground
AS analog supply
AGND analog ground
DI digital input
DIS digital Schmitt-triggered input
DID digital input with internal pull-down resistor
DISD digital Schmitt-triggered input with internal pull-down resistor
DIU digital input with internal pull-up resistor
DO digital output
DIO digital input and output
DIOS digital Schmitt-triggered input and output
A analog reference voltage
AI analog input
AO analog output

handbook, halfpage

V

DDA(DAC)

n.c.

1

n.c.

2
3

V

DDD

TEST1

4

RESET

V

DDD(C)

L3DATA

L3CLOCK

L3MODE

V

SSD(C)

V

SSD

MUTE

SPDIF

5
6
7

UDA1351TS

8

9
10
11
12
13
14

Fig.2 Pin configuration.

MGU033

TEST3

28

n.c.

27
26

SELSTATIC

25

TEST4

24

V
V

23

V

22

V

21

V

20

V

19

TEST2

18

VOUTR

17

LOCK

16

VOUTL

15

DDA(PLL)
SSA(PLL)
DDA
SSA
SSA(DAC)
ref

2000 Mar 28 7

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8 FUNCTIONAL DESCRIPTION

TheUDA1351TS isa low costaudio IEC 958decoder with
an on-board DAC. The minimum audio input sampling
frequency conforming to the IEC958 standard is 28.0 kHz
and the maximum audio sampling frequency is 100.0 kHz.

8.1 Clock regeneration and lock detection

The UDA1351TS contains an on-board PLL for
regenerating a system clock from the IEC 958 input
bitstream.

Note: If there is no input signal, the PLL generates a
minimum frequency and the output spectrum shifts
accordingly. Since the analog output does not have an
analog mute, this means noise that is out of band under
normal conditions can move into the audio band.

When the on-board clocklocks tothe incoming frequency,
the lock indicator bit is set and can be read via the
L3 interface. Internally, the PLL lock indication is
combined with thePCM statusbit ofthe input data stream.
When both the IEC 958 decoder and the on-board clock
have locked to the incoming signal and the input data
stream is PCM data, pin LOCK will beasserted. However,
when the IC is locked but the PCM status bit reports
non-PCM data, pin LOCK is returned to LOW level.

The lock indication output can be used, for example, for
muting purposes. The lock signal can be used to drive an
external analog muting circuitto prevent out of bandnoise
from becoming audible when the PLL runs at its minimum
frequency (e.g. when there is no SPDIF input signal).

8.2 Mute

The UDA1351TS is equippedwith a cosine roll-off mutein
the DSP data path of the DAC part. Muting the DAC, by
pin MUTE (in static mode) or via bit MT (in L3 mode), will
result in a soft mute, asshown in Fig.3. The cosine roll-off
soft mute takes 32 x 32 samples = 24 ms at 44.1 kHz
sampling frequency.

When operating in the L3 control mode, the device will
mute on start-up. In L3 mode, it is necessary to explicitly
switch off themute foraudio output bymeans ofthe MT bit
in the L3 register.

Inthe L3 mode,pin MUTE does nothave anyfunction (the
same holds for several other pins) and can either be left
open circuit (since it has an internal pull-down resistor) or
be connected to ground.

handbook, halfpage

1

mute

factor

0.8

0.6

0.4

0.2

0

01051525

MGU119

20

t (ms)

Fig.3 Mute as a function of raised cosine roll-off.

8.3 Auto mute

By default, the DAC outputs will be muted until the IC is
locked, regardless of the level on pin MUTE (in static
mode) or the state of bit MT of the sound feature register
(in L3 mode). In this way, only valid data will be passed to
the outputs. This mute is done in the SPDIF interface and
is a hard mute, not a cosine roll-off mute.

If needed, this muting can be bypassed by setting
bit AutoMT to logic 0 via the L3 interface. As a result, the
IC will no longer mute during out-of-lock situations.

8.4 Data path

The UDA1351TS data path consists of the IEC 958
decoder, the audio feature processor, digital interpolator
and noise shaper and the DACs.

8.4.1 IEC 958

INPUT

The UDA1351TS IEC 958 decoder features an on-chip
amplifierwithhysteresis, which amplifiesthe IEC 958input
signal to CMOS level (see Fig.4).

All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.

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Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

When used in the L3 control mode, it provides the
following additional features:

• Volume control, using 6 bits

• Bass boost control, using 4 bits

handbook, halfpage

75 Ω

10 nF

180 pF

13SPDIF

UDA1351TS

Fig.4 IEC 958 input circuit and typical application.

MGU034

• Treble control, using 2 bits

• Mode selection of thesound processingbass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off

• De-emphasis selection of the incoming data stream for

fs= 32.0, 44.1 and 48.0 kHz.

8.4.3 INTERPOLATOR
The UDA1351TS includes an on-board interpolating filter

which converts the incomingdata stream from 1fsto 128f
by cascading a recursive filter and a FIR filter.

Table 2 Interpolator characteristics

s

The extracted key parameters are:

• Pre-emphasis

• Audio sample frequency

• Two-channel PCM indicator

• Clock accuracy.

Both the lock indicator and the key channel status bits are
accessible via the L3 interface.

The UDA1351TS supports the following sample
frequencies and data bit rates:

fs= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
fs= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
fs= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s
fs= 64.0 kHz, resulting in a data rate of 4.096 Mbits/s
fs= 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s
fs= 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.

The UDA1351TS supports timing levels I, II and III, as
specified by the IEC 958 standard.

8.4.2 AUDIO FEATURE PROCESSOR
The audio feature processor automatically provides

de-emphasis for the IEC 958 data stream in the static pin
control mode and defaultmute at start-up in theL3 control
mode.

PARAMETER CONDITIONS VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.65f

s

Dynamic range 0 to 0.45f

s

s

±0.03

−50

115

DC gain −−3.5

8.4.4 NOISE SHAPER
The third-order noise shaper operates at 128fs. It shifts

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
outputis converted toananalog signal usinga filter stream
DAC.

8.4.5 THE FILTER STREAM DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way, very high signal-to-noise performance and low clock
jitter sensitivityis achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.

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Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.5 Control

TheUDA1351TS canbecontrolled bymeans of staticpins
or via the L3 interface. For optimum use of the features of
the UDA1351TS, the L3 control mode is recommended
since only basic functions are available in the static pin
control mode.

It should be noted that the static pin control mode and

control mode, pins L3MODE and L3DATA are used to
select the format for the data output and input interface.

8.5.1 STATIC PIN CONTROL MODE
The default values for all non-pin controlled settings are

identical to the default values at start-up in the L3 control
mode.

L3 control mode are mutually exclusive. In the static pin

Table 3 Pin description of static pin control mode

PIN NAME VALUE FUNCTION

Mode selection pin

26 SELSTATIC 1 select static pin control mode; must be connected to V

DDD

Input pins

5 RESET 0 normal operation

1 reset
8 L3DATA 0 must be connected to V
9 L3CLOCK 0 must be connected to V

10 L3MODE 0 must be connected to V

SSD
SSD
SSD

11 MUTE 0 normal operation

1 mute active

Status pin

16 LOCK 0 clock regeneration and IEC 958 decoder out-of-lock or non-PCM data

detected

1 clock regeneration and IEC 958 decoder locked and PCM data detected

Test pins

4 TEST1 0 must be connected to digital ground (V

18 TEST2 0 must be connected to digital ground (V
25 TEST4 1 must be connected to digital supply voltage (V
28 TEST3 0 must be connected to digital ground (V

SSD
SSD

SSD

)
)

)

DDD

)

2000 Mar 28 10

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.5.2 L3 CONTROL MODE
The L3 control mode allows maximum flexibility in controlling the UDA1351TS.
It should be noted that, in the L3 control mode, several base-line functions are still controlled by pins on the device and

that, on start-up in the L3 control mode, the output is explicitly muted by bit MT via the L3 interface.

Table 4 Pin description in the L3 control mode

PIN NAME VALUE FUNCTION

Mode selection pin

26 SELSTATIC 0 select L3 control mode; must be connected to V

Input pins

5 RESET 0 normal operation

1 reset
8 L3DATA − must be connected to the L3-bus
9 L3CLOCK − must be connected to the L3-bus

10 L3MODE − must be connected to the L3-bus

Status pin

16 LOCK 0 clock regeneration and IEC 958 decoder out-of-lock or non-PCM data

detected

1 clock regeneration and IEC 958 decoder locked and PCM data detected

Test pins

4 TEST1 0 must be connected to ground (V

18 TEST2 0 must be connected to ground (V

SSD
SSD

)

)
25 TEST4 1 must be connected to digital supply voltage (V
28 TEST3 0 must be connected to ground (V

SSD

)

SSD

DDD

)

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Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6 L3 interface

8.6.1 GENERAL
The UDA1351TS has an L3 microcontroller interface and

all the digital sound processing features and various
system settings can be controlled by a microcontroller.

The controllable settings are:

• Restoring L3 defaults

• Power-on

• Selection of filter mode and settings of treble and bass

boost

• Volume settings

• Selection of soft mute via cosine roll-off and bypass of

auto mute

• Selection of de-emphasis (only effective in L3 control
mode).

The readable settings are:

• Mute status of interpolator

• PLL locked

• SPDIF input signal locked

• Audio Sample Frequency (ASF)

• Valid PCM data detected

• Pre-emphasis of the IEC 958 input signal

• ACcuracy of the Clock (ACC).

Theexchange ofdata and controlinformation betweenthe
microcontroller and the UDA1351TS is LSB first and is
accomplished through a serial hardware L3 interface
comprising the following pins:

• L3DATA: data line

• L3MODE: mode line

• L3CLK: clock line.

The exchange of bytes via the L3 interface is LSB first.
The L3 format has two modes of operation:

• Address mode

• Data transfer mode.

The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by eight bits (see
Fig.5). The data transfer mode is characterized by
L3MODE being HIGH and is used to transfer one or more
bytes representing a register address, instruction or data.

Basically, two types of data transfers can be defined:

• Write action: data transfer to the device

• Read action: data transfer from the device.

Remark: when the device is powered up, at least one
L3CLOCK pulse must begiven tothe L3 interfaceto wake
up the interface before starting sending to the device,
see Fig.5. This is only needed once after the device is
powered up.

8.6.2 DEVICE ADDRESSING
The device address consists of one byte with:

• Data Operating Mode (DOM) bits 0 and 1 representing
the type of data transfer (see Table 5)

• Address bits 2 to 7 representing a 6-bit device address.

Table 5 Selection of data transfer

DOM

TRANSFER

BIT 0 BIT 1

0 0 not used
1 0 not used
0 1 write data or prepare read
1 1 read data

8.6.3 REGISTER ADDRESSING

After sending the device address (including DOM bits),
indicating whether the information is to be read or written,
one data byte is sent using bit 0 to indicate whether the
information will be read or written and bits 1 to 7 for the
destination register address.

Basically, there are three methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a

write action to the destination register, followed by
bits 1 to 7 indicating the register address (see Fig.5)

2. Addressing for prepare read:bit 0 is logic 1, indicating

that data will be read from the register (see Fig.6)

3. Addressing for data read action. Here, the device

returns a register address prior to sending data from
thatregister. When bit 0is logic 0, theregister address
is valid; when bit 0 is logic 1, the register address is
invalid.

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2000 Mar 28 13

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

register address

data byte 1 data byte 2

MGS753

L3DATA

device address

0

10

DOM bits

write

Fig.5 Data write mode (for L3 version 2).

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

L3CLOCK

L3MODE

L3DATA

device address

0

111

DOM bits

prepare read send by the device

register address device address register address

1

read

0/1

valid/non-valid

Fig.6 Data read mode.

data byte 1 data byte 2

MGS754

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6.4 DATA WRITE MODE
The data write mode is explained in the signal diagram of

Fig.5. For writing data to a device,four bytes must be sent
(see Table 6):

1. One byte starting with ‘01’ for signalling the write
action to the device, followed by the device address
(‘011000’ for the UDA1351TS)

2. One byte starting with a ‘0’ for signalling the write
action, followed by seven bits indicating the
destination addressin binary format with A6 being the
MSB and A0 being the LSB

3. Twodata byteswith D15 being the MSB and D0 being
the LSB.

Itshould be notedthat eachtime anewdestination register
address needs to be written, the device address must be
sent again.

8.6.5 DATA READ MODE

To readdata from the device, a prepare readmust first be
doneand thendata read. Thedata read modeis explained
in the signal diagram of Fig.6.

For readingdata from a device, the following six bytes are
involved (see Table 7):

1. One byte with the device address, including ‘01’ for
signalling the write action to the device

2. One byte is sent with the register address from which
dataneeds to beread. This bytestartswith a ‘1’,which
indicates that there will be a read action from the
register, followed again by seven bits for the
destination address inbinary format,with A6 beingthe
MSB and A0 being the LSB

3. Onebyte with thedeviceaddress, including ‘11’is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller

4. One byte, sent by the device to the bus, with the
(requested) register address and a flag bit indicating
whetherthe requestedregister was valid(bit is logic 0)
or invalid (bit is logic 1)

5. Two bytes, sent bythe deviceto the bus, with the data
information in binary format, with D15 being the MSB
and D0 being the LSB.

Table 6 L3 write data

BYTE L3 MODE ACTION

1 address device address 01011000
2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0
3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8
4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

Table 7 L3 read data

BYTE L3 MODE ACTION

1 address device address 01011000
2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0
3 address device address 11011000
4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0
5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8
6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2000 Mar 28 14

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6.6 INITIALIZATION STRING
For proper and reliable operation, the UDA1351TS must be initialized in the L3 control mode. This is required to have

the PLL start up after powering up of the device under all conditions. The initialization string is given in Table 8.

Table 8 L3 initialization string and set defaults after power-up.

BYTE L3 MODE ACTION

1 address init string device address 01011000
2 data transfer register address 01000000
3 data transfer data byte 1 00000000
4 data transfer data byte 2 00000011
5 address set defaults device address 01011000
6 data transfer register address 01111111
7 data transfer data byte 1 00000000
8 data transfer data byte 2 00000000

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2000 Mar 28 15

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2000 Mar 28 16

8.6.7 OVERVIEW OF L3 INTERFACE REGISTERS
Table 9 UDA1351TS register map

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

ADDR FUNCTION

Writable settings

00H system

parameters
default 1 0

10H sound

features
default 0 0 0 0 0 0 0 0 0 0 1

11H volume

control DAC
default 000000

40H multiplex

parameters
default 0

7FH restore

L3 defaults

Readable settings

18H interpolator

parameters

38H SPDIF input

and lock
parameters

BIT

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PON

(1)

(1)

0

(2)

1

(1)

0

(1)

0

M1 M0 BB3 BB2 BB1 BB0 TR1 TR0 DE1 DE0 MT

VC5 VC4 VC3 VC2 VC1 VC0

AutoMTRST

PLL

(1)

(1)

0

(1)

0

(1)

0

10

MT
stat

PLL
lock

SPD
lock

ASF1 ASF0 PCM

stat

PRE ACC1 ACC0

Notes

1. When writing new settings via the L3 interface, these bits should always remain at logic 0 (default value) to warrant correct operation.

2. When writing new settings via the L3 interface, these bits should always remain at logic 1 (default value) to warrant correct operation.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6.8 WRITABLE REGISTERS

8.6.8.1 Restoring L3 defaults

By writing to the 7FH register, all L3 control values are
restored to their default values. Only the L3 interface is
affected: the system will not be reset. Consequently,
readable registers that are not reset can be affected.

8.6.8.2 Power-on

A 1-bit value to switch the DAC on and off.

Table 10 Power-on setting

PON FUNCTION

0 power-down
1 power-on (default setting)

8.6.8.3 Filter mode selection

A 2-bit value to program the mode for the sound
processing filters of bass boost and treble.

Table 11 Filter mode settings

M1 M0 FUNCTION

0 0 flat (default setting)
0 1 minimum
10
1 1 maximum

8.6.8.4 Treble

A 2-bit value to program the treble setting, in combination
with the filter mode settings. At fs= 44.1 kHz, the −3dB
point for minimum setting is 3.0 kHz and the −3 dB point
for maximum setting is 1.5 kHz. The default value is ‘00’.

Table 12 Treble settings

LEVEL (dB)

TR1 TR0

FLAT MIN. MAX.

00000
01022
10044
11066

8.6.8.5 Bass boost

A 4-bit value to program the bass boost setting, in
combination with the filter mode settings. Atfs= 44.1 kHz,
the −3 dB point for minimum setting is 250 Hz and the

−3 dB point for maximum setting is 300 Hz. The default

value is ‘0000’.

Table 13 Bass boost settings

LEVEL (dB)

BB3 BB2 BB1 BB0

FLAT MIN. MAX.

0000000
0001022
0010044
0011066
0100088
010101010
011001212
011101414
100001616
100101818
101001820
101101822
110001824
110101824
111001824
111101824

8.6.8.6 De-emphasis

A 2-bit value to enable the digital de-emphasis filter.

Table 14 De-emphasis selection

DE1 DE0 FUNCTION

0 0 other (default setting)
01f
10f
11f

= 32.0 kHz

s

= 44.1 kHz

s

= 48.0 kHz

s

8.6.8.7 Soft mute

A 1-bit value to enable the digital mute.

Table 15 Soft mute selection

MT FUNCTION

0 no muting
1 muting (default setting)

2000 Mar 28 17

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6.8.8 Volume control

A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to −∞ dB in steps of 1 dB.

Table 16 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
110011
110100
110101
110110
110111
111000
111001

111011
111100
111101
111110
111111

−51

−52

−54

−57111010

−60

−∞

8.6.8.9 Auto mute

A 1-bitvalue to activate mute during out-of-lock. In normal
operation, the output isautomatically hardmuted whenan
out-of-lock situation is detected. Setting this bit to logic 0
will disable that function.

Table 17 Auto mute setting

Auto MT FUNCTION

0 do not mute output during out-of-lock
1 mute output during out-of-lock (default

setting)

8.6.8.10 PLL reset

A 1-bit value to reset the PLL. This is thebit which is set in
the initialization string. When this bit is asserted, the PLL
will be reset and the output clock of the PLL will be forced
to its lowest value, which is in the area of a few MHz.

Table 18 PLL reset

RST PLL FUNCTION

0 normal operation (default)
1 PLL is reset

8.6.9 READABLE REGISTERS

8.6.9.1 Mute status

A 1-bit value indicating whether the interpolator is muting
or not muting.

Table 19 Interpolator mute status

MT stat FUNCTION

0 no muting
1 muting

8.6.9.2 PLL lock detection

A 1-bit value indicating that the clock regeneration is
locked.

Table 20 PLL lock indication

PLL lock FUNCTION

0 out-of-lock
1 locked

8.6.9.3 SPDIF lock detection

A 1-bitvalue indicating the IEC 958 decoder is locked and
is decoding correct data.

Table 21 SPDIF lock detection

SPD lock FUNCTION

0 not locked or non-PCM data detected
1 locked and PCM data detected

2000 Mar 28 18

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

8.6.9.4 Audio sample frequency detection

A 2-bit value indicating the audio sample frequency of the
IEC 958 input signal.

Table 22 Audio sample frequency detection

ASF1 ASF0 FUNCTION

0 0 44.1 kHz
0 1 undefined
1 0 48.0 kHz
1 1 32.0 kHz

8.6.9.5 PCM detection

A 1-bit value which indicates whether the IEC 958 input
contains PCM audio data or other binary data.

Table 23 Two channel PCM input detection

PCM stat FUNCTION

0 input with two channel PCM data
1 input without two channel PCM data

8.6.9.6 Pre-emphasis detection

A 1-bit value that indicates whether the pre-emphasis bit
was set on the IEC 958 input signal or not set.

Table 24 Pre-emphasis detection

PRE FUNCTION

0 no pre-emphasis
1 pre-emphasis

8.6.9.7 Clock accuracy detection

A 2-bitvalue indicating whether the timing accuracy of the
IEC 958 input signal conforms to the IEC 958
specification.

Table 25 Input signal accuracy detection

ACC1 ACC0 FUNCTION

0 0 level II
01levelI
1 0 level III
1 1 undefined

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

xtal

T

stg

T

amb

V

es

supply voltage note 1 2.7 5.0 V
crystal temperature −25 +150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage Human Body Model (HBM); note 2 −2000 +2000 V

Machine Model (MM); note 3 −200 +200 V

I

lu(prot)

I

sc(DAC)

latch-up protection current T
short-circuit current of DAC T

= 125 °C; VDD= 3.6 V − 200 mA

amb

=0°C; VDD= 3 V; note 4

amb

output short circuited to V
output short circuited to V

SSA(DAC)
DDA(DAC)

− 482 mA

− 346 mA

Notes

1. All V

and VSS connections must be made to the same power supply.

DD

2. JEDEC class 2 compliant.

3. JEDEC class B compliant, except pin V

SSA(PLL)

, which can withstand ESD pulses of −130 to +130 V.

4. DAC operation after short circuiting cannot be warranted.

2000 Mar 28 19

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

10 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

11 CHARACTERISTICS

V

DDD=VDDA

ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies; note 1

V

DDA

V

DDA(DAC)

V

DDA(PLL)

V

DDD

V

DDD(C)

I

DDA(DAC)

I

DDA(PLL)

I

DDD(C)

I

DDD

P power consumption at 48 kHz DAC in playback mode − 80 − mW

Digital input pins

V

IH

V

IL

V

hys(RESET)

 input leakage current −−10 µA

I

LI

C

i

R

pu(int)

R

pd(int)

Digital output pins

V

OH

V

OL

I

L(max)

thermal resistance from junction to ambient in free air 85 K/W

= 3.0 V; IEC 958 input with fs= 48.0 kHz; T

=25°C; RL=5kΩ; all voltages measured with respect to

amb

analog supply voltage 2.7 3.0 3.6 V
analog supply voltage for DAC 2.7 3.0 3.6 V
analog supply voltage for PLL 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital supply voltage for core 2.7 3.0 3.6 V
analog supply current of DAC power-on − 8.0 − mA

power-down − 750 −µA

analog supply current of PLL at 48 kHz − 0.7 − mA

at 96 kHz − 1.0 − mA

digital supply current of core at 48 kHz − 16.0 − mA

at 96 kHz − 24.5 − mA

digital supply current at 48 kHz − 2.0 − mA

at 96 kHz − 3.0 − mA

DAC in Power-down mode − 58 − mW

power consumption at 96 kHz DAC in playback mode − 109 − mW

DAC in Power-down mode − 87 − mW

HIGH-level input voltage 0.8V
LOW-level input voltage −0.5 − +0.2V
hysteresis voltage on

− 0.8 − V

− VDD+ 0.5 V

DD

DD

pin RESET

input capacitance −−10 pF
internal pull-up resistance 16 33 78 kΩ
internal pull-down resistance 16 33 78 kΩ

HIGH-level output voltage IOH= −2 mA 0.85V

−−V

DD

LOW-level output voltage IOL=2mA −−0.4 V
maximum load current − 3 − mA

V

2000 Mar 28 20

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital-to-analog converter; note 2

V

ref

V

o(rms)

(THD + N)/S total harmonic

S/N signal-to-noise ratio at 48 kHz f

α

cs

∆V

o

IEC 958 input

V

i(p-p)

R

i

V

hys

Notes

1. All supply pins VDD and VSS must be connected to the same external power supply unit.

2. When the DAC must drive ahigher capacitiveload (above50 pF), a series resistor of 100 Ω mustbe usedto prevent
oscillations in the output stage of the operational amplifier.

reference voltage measured with respect to

V

SSA

0.45V

DDA

0.50V

DDA

0.55V

DDA

V

output voltage (RMS value) − 900 − mV

f

= 1.0 kHz tone at 48 kHz

i

distortion-plus-noise to signal
ratio

at 0 dB −−90 −85 dB
at −40 dB; A-weighted −−60 −55 dB

f

= 1.0 kHz tone at 96 kHz

i

at 0 dB −−85 −80 dB
at −40 dB; A-weighted −−57 −52 dB

= 1.0 kHz tone; code = 0;

i

95 100 − dB

A-weighted

signal-to-noise ratio at 96 kHz f

= 1.0 kHz tone; code = 0;

i

95 100 − dB

A-weighted
channel separation fi= 1.0 kHz tone − 96 − dB
unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB

AC inputvoltage (peak-to-peak

0.2 0.5 3.3 V

value)
input resistance − 6 − kΩ
hysteresis voltage − 40 − mV

2000 Mar 28 21

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

12 TIMING CHARACTERISTICS

V

DDD=VDDA

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. UNIT

Device reset

t

rst

PLL lock time

t

lock

Microcontroller L3 interface timing (see Figs 7 and 8)
T

cy(CLK)(L3)

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

h(L3)A

t

su(L3)D

t

h(L3)D

t

(stp)(L3)

t

su(L3)DA

t

h(L3)DA

t

su(L3)R

t

h(L3)R

= 2.7 to 3.6 V; T

= −40 to +85 °C; RL=5kΩ; all voltages measured with respect to ground; unless

amb

reset active time − 250 µs

time to lock fs= 32.0 kHz − 85.0 ms

f

= 44.1 kHz − 63.0 ms

s

= 48.0 kHz − 60.0 ms

f

s

f

= 48.0 kHz − 40.0 ms

s

L3CLOCK cycle time 500 − ns
L3CLOCK HIGH time 250 − ns
L3CLOCK LOW time 250 − ns
L3MODE set-up time for address mode 190 − ns
L3MODE hold time for address mode 190 − ns
L3MODE set-up time for data transfer mode 190 − ns
L3MODE hold time for data transfer mode 190 − ns
L3MODE stop time in data transfer mode 190 − ns
L3DATA set-up time in address and data

190 − ns

transfer mode
L3DATA hold time in address and data

30 − ns

transfer mode
L3DATA set-up time in data transfer mode read mode 50 −−
L3DATA hold time in data transfer mode read mode 360 −−

2000 Mar 28 22

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h(L3)A

t

CLK(L3)L

t

su(L3)DA

t

CLK(L3)H

t

BIT 0

su(L3)A

Fig.7 Timing for address mode.

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

BIT 7

MGL723

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

L3DATA

write

read

t

t

su(L3)D

t

en(L3)DA

stp(L3)

t

CLK(L3)L

t

CLK(L3)H

t

su(L3)R

t

su(L3)DA

t

h(L3)DA

BIT 0

t

h(L3)R

Fig.8 Timing for data transfer mode.

T

cy(CLK)L3

t

t

h(L3)DA

BIT 7

t

dis(L3)DA

h(L3)D

t

stp(L3)

MGL889

2000 Mar 28 23

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2000 Mar 28 24

ndbook, full pagewidth

13 APPLICATION INFORMATION

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

V

V

DDD(C)

L3-bus

IEC

channel

DDA

L27

BZN32A07

X16

X11

V

DDA

static

R41

75 Ω

C11

100 µF

(16 V)

J14

L3

L26

BZN32A07

100 nF

3

V

DDD(C)

2
1

C48

180 pF

(50 V)

C41

(50 V)

100 µF

C45

10 nF
(50 V)

C12

(16 V)

X1
X1
X1

X1
X1
X1

X1

X1

C42

100 nF

(50 V)

V

DDA

V

SSA

V

DDD(C)

L3CLOCK

L3MODE

L3DATA

SELSTATIC

SPDIF

22
21
6

9

10

8

26

13

X1

X1

DDA(PLL)

SSA(PLL)

V

V

24

X1

TEST1

4

UDA1351TS

X1

TEST2
18

X1

TEST3

28

V

DDD

X1

TEST4
2523

X1

X1

SSA(DAC)

DDA(DAC)

V

V

2014

L29

V

C13
10 µF
(16 V)

mute
no mute

X18

X13

DDA

output

left

C43
100 nF
(50 V)

X1

V

ref

19

C40

X1

RESET

5

MUTE

11

n.c.

1

n.c.

2

V

SSD(C)

12

n.c.

27

VOUTL

15

100 nF

(50 V)

V

X1

X1
X1

X1
X1

C15

X1

47 µF
(16 V)

C14

100 µF

(16 V)

100 nF

V

DDD(C)

R43
10 kΩ

C44

(50 V)

DDD(C)

100 Ω

BZN32A07

J26

3
2
1

R44

ground

+3 V

AGND DGND

C3
100 µF
(16 V)

AGND DGND

C5

100 µF

(16 V)

3

7

DDD

V

X1

V

X1

SSD

lock

16

LOCK

X1

R39

1 kΩ

V5

J1

V

DDA

J3

V

DDD(C)

J2

V

DDD

R38

V

DDD

1 Ω

C9

100 µF

(16 V)

C28

100 nF

(50 V)

17

MGU035

47 µF
(16 V)

R45
10 kΩ

100 Ω

C16

X1

VOUTR

R46

X19

X14

output

right

Fig.9 Test and application diagram.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

14 PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

D

c

y

Z

28 15

A

2

A

pin 1 index

114

w M

b

e

p

1

E

H

E

detail X

Q

L

p

L

(A )

A

X

v M

A

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

0.21

mm

2.0

OUTLINE
VERSION

SOT341-1 MO-150

0.05

1.80

0.25

1.65

IEC JEDEC EIAJ

p

0.38

0.25

0.20

0.09

(1)E(1) (1)

cD

10.4

5.4

10.0

REFERENCES

0.65 1.25

5.2

2000 Mar 28 25

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

1.1

0.7

ISSUE DATE

95-02-04
99-12-27

o

8

o

0

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

15 SOLDERING

15.1 Introduction to soldering surface mount
packages

Thistext gives averybrief insight toa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave solderingis notalways suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wavewith high upwardpressure followed bya
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leadsonfour sides, thefootprint must
be placedat a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.3 Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices(SMDs)or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

2000 Mar 28 26

15.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351TS

15.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is onlysuitable for SSOP and TSSOPpackages with a pitch (e) equal toor larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting valuesgiven are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2000 Mar 28 27

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 753503/25/01/pp28 Date of release: 2000 Mar 28 Document order number: 9397 750 06814