Datasheet UDA1351H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1351H

96 kHz IEC 958 audio DAC

Preliminary specification
File under Integrated Circuits, IC01

2000 Feb 18

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

CONTENTS

1 FEATURES

1.1 General

1.2 Control

1.3 IEC 958 input

1.4 Digital output and input interfaces

1.5 Digital sound processing and DAC
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Operating modes

8.2 Clock regeneration and lock detection

8.3 Mute

8.4 Auto mute

8.5 Data path

8.5.1 IEC 958 input

8.5.2 Digital data output and input interface

8.5.3 Audio feature processor

8.5.4 Interpolator

8.5.5 Noise shaper

8.5.6 The Filter Stream DAC (FSDAC)

8.6 Control

8.6.1 Static pin control mode

8.6.2 L3 control mode

8.7 L3 interface

8.7.1 General

8.7.2 Device addressing

8.7.3 Register addressing

8.7.4 Data write mode

8.7.5 Data read mode

8.7.6 Initialization string

8.7.7 Overview of L3 interface registers

8.7.8 Writable registers

8.7.9 Readable registers

9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 TIMING CHARACTERISTICS
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS

2000 Feb 18 2

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog

Converter (DAC)

• Master-mode data output interface for off-chip sound
processing

• 256fssystem clock output

• 20-bit data-path in interpolator

• High performance

• No analog post filtering required for DAC

• Supports sampling frequencies from 28 up to 100 kHz

• The UDA1351His fully pin and function compatible with

the UDA1350AH.

1.2 Control

• Controlled either by means of static pins or via the
L3 microcontroller interface.

1.3 IEC 958 input

1.5 Digital sound processing and DAC

• Pre-emphasis information of IEC 958 input bitstream
available in L3 interface register and on pins

• Automatic de-emphasis when using IEC 958 input with

32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface

• Interpolating filter (fsto 128fs) by means of a cascade of
a recursive filter and a FIR filter

• Third-order noise shaper operating at 128fs generates
bitstream for the DAC

• Filter stream digital-to-analog converter.

• On-chip amplifier for converting IEC 958 input to CMOS

levels

• Selectable IEC 958 input channel, one out of two

• Lock indication signal available on pin LOCK

• Lock indication signal combined on-chip with the Pulse

Code Modulation (PCM) status bit; in case non-PCM
has been detected pin LOCK indicates out-of-lock

• Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, 2 channel PCM
indication and clock accuracy).

1.4 Digital output and input interfaces

• When the UDA1351H is clock master of the data output
interfaces:

– BCKO and WSO signals are output
–I2S-bus or LSB-justified 16, 20 and 24 bits formats

are supported.

• When the UDA1351H is clock slave of the data input
interface:

– BCK and WS signals are input
–I2S-bus or LSB-justified 16, 20 and 24 bits formats

are supported.

2 APPLICATIONS

• Digital audio systems.

3 GENERAL DESCRIPTION

The UDA1351H is a single chip IEC 958 audio decoder
with an integrated stereo digital-to-analog converter
employing bitstream conversion techniques.

Besides the UDA1351H, which is the full featured version
in QFP44 package, there also exists the UDA1351TS.
The UDA1351TS has IEC 958 input to the DAC only and
is in SSOP28 package.

The UDA1351H can operate in various operating modes:

• IEC 958 input to the DAC including on-chip signal
processing

• IEC 958 input via the digital data output interface to the
external Digital Signal Processor (DSP)

• IEC 958 input to the DAC and a DSP

• IEC 958 input via a DSP to the DAC including on-chip

signal processing

• External source data input to the DAC including on-chip
signal processing.

2000 Feb 18 3

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

The IEC 958 input audio data including the accompanying
pre-emphasis information is available on the output data
interface.

By default the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.

Alock indication signal isavailable on pin LOCK indicating
that the IEC 958 decoder is locked.

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDD

V

DDA

I

DDA(DAC)

digital supply voltage 2.7 3.0 3.6 V
analog supply voltage 2.7 3.0 3.6 V
analog supply current of DAC power-on − 8.0 − mA

power-down − 750 −µA

I

DDA(PLL)

analog supply current of PLL at 48 kHz − 0.7 − mA

at 96 kHz − 1.0 − mA

I

DDD(C)

digital supply current of core at 48 kHz − 16.0 − mA

at 96 kHz − 24.5 − mA

I

DDD

digital supply current at 48 kHz − 2.0 − mA

at 96 kHz − 3.0 − mA

P power consumption at 48 kHz DAC in playback mode − 80 − mW

DAC in Power-down mode − 58 − mW

power consumption at 96 kHz DAC in playback mode − 109 − mW

DAC in Power-down mode − 87 − mW

General

t

rst

T

amb

reset active time − 250 −µs
ambient temperature −40 − +85 °C

Digital-to-analog converter

V

o(rms)

(THD + N)/S total harmonic distortion-plus-noise to

output voltage (RMS value) note 1 − 900 − mV

= 1.0 kHz tone at 48 kHz

f

i

signal ratio

at 0 dB −−90 −85 dB
at −40 dB; A-weighted −−60 −55 dB

f

= 1.0 kHz tone at 96 kHz

i

at 0 dB −−85 −80 dB
at −40 dB; A-weighted −−58 −53 dB

S/N signal-to-noise ratio at 48 kHz f

= 1.0 kHz tone;

i

95 100 − dB

code = 0; A-weighted

signal-to-noise ratio at 96 kHz f

= 1.0 kHz tone;

i

95 100 − dB

code = 0; A-weighted

α
∆V

cs

o

channel separation fi= 1.0 kHz tone − 96 − dB
unbalance of output voltages fi= 1.0 kHz tone 0.4 0.1 − dB

Note

1. The DAC output voltage is proportionally to the DAC power supply voltage.

2000 Feb 18 4

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1351H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);

body 10 × 10 × 1.75 mm

6 BLOCK DIAGRAM

handbook, full pagewidth

V

DDA(DAC)

V

DDA(PLL)

V

SSA(PLL)

TEST1

V

DDD(C)

V

SSD(C)

L3MODE

L3CLOCK

L3DATA

SELSTATIC

SPDIF0
SPDIF1

SELCHAN

V

DDD

V

SSD

32
31

34

2

4

10

6
5

35

15
16

13

43
3

CLKOUT

CLOCK

AND

TIMING CIRCUIT

L3

INTERFACE

SLICER

11, 14,
28, 38,
40, 41

n.c.

29

IEC 958

DECODER

21

PREEM1

LOCK

30

42

PREEM0

TC

23

TEST2

39

DATA

OUTPUT

INTERFACE

33

BCKO

RTCB

UDA1351H

WSO

44

37

36

DATAO

V

SSA

DATAI

V

26

7

BCKI

VOUTL

DDA

27

AUDIO FEATURE PROCESSOR

8

9

SELCLK

WSI

18

DAC

NOISE SHAPER

INTERPOLATOR

19

SELSPDIF

V

SSA(DAC)

17

20

V

ref

VOUTR

25

24

DAC

DATA

INPUT

INTERFACE

22

SOT307-2

12

1

MGL976

MUTE

RESET

Fig.1 Block diagram.

2000 Feb 18 5

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

RESET 1 DISD reset input
V

DDD(C)

V

SSD

V

SSD(C)

2 DS digital supply voltage for core
3 DGND digital ground

4 DGND digital ground for core
L3DATA 5 DIOS L3 interface data input and output
L3CLOCK 6 DIS L3 interface clock input
DATAI 7 DISD I
BCKI 8 DISD I
WSI 9 DISD I

2

S-bus data input

2

S-bus bit clock input

2

S-bus word select input
L3MODE 10 DIS L3 interface mode input
n.c. 11 − not connected
MUTE 12 DID mute control input
SELCHAN 13 DID IEC 958 channel selection input
n.c. 14 − not connected
SPDIF0 15 AI IEC 958 channel 0 input
SPDIF1 16 AI IEC 958 channel 1 input
V

DDA(DAC)

17 AS analog supply voltage for DAC
VOUTL 18 AO DAC left channel analog output
SELCLK 19 DID clock source for PLL selection input
SELSPDIF 20 DIU IEC 958 data selection input
LOCK 21 DO SPDIF and PLL lock indicator output
VOUTR 22 AO DAC right channel analog output
TC 23 DID test pin; must be connected to digital ground (V
V

ref

V

SSA(DAC)

V

SSA

V

DDA

24 A DAC reference voltage

25 AGND analog ground for DAC

26 AGND analog ground

27 AS analog supply voltage

SSD

)

n.c. 28 − not connected
CLKOUT 29 DO clock output (256f

)

s

PREEM1 30 DO IEC 958 input pre-emphasis output 1
V

SSA(PLL)

V

DDA(PLL)

BCKO 33 DO I

31 AGND analog ground for PLL

32 AS analog supply voltage for PLL

2

S-bus bit clock output
TEST1 34 DIU test pin 1: must be connected to digital supply voltage (V
SELSTATIC 35 DIU static pin control selection input
DATAO 36 DO I
WSO 37 DO I

2

S-bus data output

2

S-bus word select output
n.c. 38 − not connected
TEST2 39 DISD test pin 2; must be connected to digital ground (V

SSD

)

n.c. 40 − not connected

DDD

)

2000 Feb 18 6

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

SYMBOL PIN TYPE

(1)

DESCRIPTION

n.c. 41 − not connected
PREEM0 42 DO IEC 958 input pre-emphasis output 0
V

DDD

43 DS digital supply voltage

RTCB 44 DID test pin; must be connected to digital ground (V

Note

1. See Table 1.

Table 1 Pin type references

PIN TYPE DESCRIPTION

DS digital supply
DGND digital ground
AS analog supply
AGND analog ground
DI digital input
DIS digital Schmitt-triggered input
DID digital input with internal pull-down resistor
DISD digital Schmitt-triggered input with internal pull-down resistor
DIU digital input with internal pull-up resistor
DO digital output
DIO digital input and output
DIOS digital Schmitt-triggered input and output
A analog reference voltage
AI analog input
AO analog output

SSD

)

2000 Feb 18 7

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

handbook, full pagewidth

DDD

RTCB

44

V
43

PREEM0

n.c.

42

41

n.c.
40

n.c.

TEST2
39

38

WSO
37

DATAO

SELSTATIC

36

35

TEST1
34

RESET

V

DDD(C)

V

SSD

V

SSD(C)

L3DATA

L3CLOCK

DATAI

BCKI

WSI

L3MODE

n.c.

22

VOUTR

33

BCKO
V

32

V

31
30

PREEM1
CLKOUT

29
28

n.c.
V

27

V

26

V

25
24

V
TC

23

MGL977

DDA(PLL)
SSA(PLL)

DDA
SSA
SSA(DAC)

ref

1
2
3
4
5
6
7
8

9
10
11

12

13

MUTE

SELCHAN

14

n.c.

UDA1351H

15

16

SPDIF0

SPDIF1

17

18

VOUTL

DDA(DAC)

V

19

20

SELCLK

SELSPDIF

21

LOCK

Fig.2 Pin configuration.

2000 Feb 18 8

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8 FUNCTIONAL DESCRIPTION

8.1 Operating modes
MODE DESCRIPTION SCHEMATIC

1 IEC 958 input to the DAC

input

IEC 958

DAC

CLOCK

2 IEC 958 input via the data

output interface to the DSP

3 IEC 958 input to the DAC and

via the data output interface to
the DSP

4 IEC 958 input via the data

output interface to the external
DSP and via the data input
interface to the DAC

input

IEC 958

input

IEC 958

input

IEC 958

CLOCK

CLOCK

CLOCK

DSP

DSP

DSP

DSP

MGS758

MGS759

DAC

MGS760

DAC

MGS761

5 Data input interface signal to

the DAC

DSP

DAC

MGS762

The UDA1351H is a low cost multi-purpose IEC 958 decoder DAC with a variety of operating modes.
In modes 1, 2, 3 and 4 the UDA1351H is clock master; it generates the clock for both the outgoing and incoming digital

data streams. Consequently, any device providing data for the UDA1351H via the data input interface in mode 4 will be
slave to the clock generated by the UDA1351H.

In mode 5 the UDA1351H locks to signal WSI from the digital data input interface. Conforming to IEC 958, the audio
sample frequency of the data input interface must be between 28.0 and 100.0 kHz.

2000 Feb 18 9

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.2 Clock regeneration and lock detection

The UDA1351H contains an on-board PLL for
regenerating a system clock from the IEC 958 input
bitstream or the incoming digital data stream via the data
input interface. In addition to the system clock for the
on-board digital sound processing the PLL also generates
a 256fsclock output for use in the application. In the
absence of an input signal the clock will generate a
minimum frequency to warrant system functionality.

Note: in case of no input signal, the PLL generates a
minimum frequency and the output spectrum shifts
accordingly. Since the analog output does not have a
analog mute, this means noise which is out of band noise
under normal operation conditions, can move into the
audio band.

When the on-board clock has locked to the incoming
frequency the lock indicator bit will be set and can be read
via the L3 interface. Internally the PLL lock indication is
combinedwith the PCM status bitof the input datastream.
When both the IEC 958 decoder and the on-board clock
have locked to the incoming signal and the input data
stream is PCM data, then pin LOCK will be asserted.
However, when the IC is locked but the PCM status bit
reports non-PCM data then pin LOCK is returned to LOW
level.

8.3 Mute

The UDA1351H is equipped with a cosine roll-off mute in
the DSP data path of the DAC part. Muting the DAC, by
pin MUTE (in static mode) or via bit MT (in L3 mode) will
result in a soft mute as presented in Fig.3. The cosine
roll-off soft mute takes 32 × 32 samples = 24 ms at a
sampling frequency of 44.1 kHz.

handbook, halfpage

1

mute

factor

0.8

0.6

0.4

0.2

0

01 3

2

MGS755

t (ms)

The lock indication output can be used, for example, for
muting purposes. The lock signal can be used to drive an
external analog muting circuit to prevent out of band noise
to become audible in case the PLL runs at its minimum
frequency (e.g. when there is no SPDIF input signal).

Fig.3 Mute as a function of raised cosine roll-off.

When operating in the L3 control mode the device will
mute on start-up. In L3 mode it is necessary to explicitly
switch off the mute for audio output bymeans of the MT bit
in the L3 register.

In the L3 mode pin MUTE does not have any function (the
same holds for several other pins) and can either be left
open-circuit (since it has an internal pull-down resistor) or
be connected to ground.

2000 Feb 18 10

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.4 Auto mute

By default the outputs of the digital data output interface
and the DAC will be muted until the IC is locked,
regardless the level on pin MUTE (in static mode) or the
state of bit MT of the sound feature register (in L3 mode).
In this way only valid data will be passed to the outputs.
This mute is done in the SPDIF interface and is a hard
mute, not a cosine roll-off mute.

If needed this muting can be bypassed by setting
bit AutoMTtologic 0viathe L3 interface. As a result the IC
will no longer mute during out-of-lock situations.

8.5 Data path

The UDA1351H data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.

8.5.1 IEC 958 INPUT

The UDA1351H IEC 958 decoder can select 1 out of 2
IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.4).

The extracted key parameters are:

• Pre-emphasis

• Audio sample frequency

• Two-channel PCM indicator

• Clock accuracy.

Both the lock indicator and the key channel status bits are
accessible via the L3 interface.

The UDA1351H supports the following sample
frequencies and data bit rates:

• fs= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

• fs= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

• fs= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s

• fs= 64.0 kHz, resulting in a data rate of 4.096 Mbits/s

• fs= 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s

• fs= 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.

The UDA1351H supports timing level I, II and III as
specified by the IEC 958 standard.

handbook, halfpage

15,
16

UDA1351H

MGL975

75 Ω

10 nF

180 pF

SPDIF0,
SPDIF1

Fig.4 IEC 958 input circuit and typical application.

All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.

2000 Feb 18 11

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.5.2 DIGITAL DATA OUTPUT AND INPUT INTERFACE

The digital data interface enables the exchange of digital
data to and from an external signal processing device.

The digital output and input formats are identical by
design. The possible formats are (see Fig.5):

• I2S-bus with a word length of up to 24 bits

• LSB-justified with a word length of 16 bits

• LSB-justified with a word length of 20 bits

• LSB-justified with a word length of 24 bits.

Important: the edge of the WS signal must fall on the
negative edge of the BCK signal at all times for proper
operation of the input and output interface (see Fig.8).

In the static pin control mode the format is selected by
means of pins L3MODE and L3DATA. In the L3 control
mode the format defaults to the I2S-bus settings and is
programmable via the L3 interface.

The IEC 958 decoder provides the pre-emphasis
information from the IEC 958 input bitstream to pins
PREEM0 and PREEM1 and to the L3 interface register.

Controlling the de-emphasis is different for the 2 modes:

• Static pin control mode:

– For IEC 958 input de-emphasis is automatically

done, but for I2S-bus input de-emphasis is not
possible.

• L3 control mode:

– IEC 958 input: bit SPDSEL mustbe set to logic 1and

de-emphasis is done automatically

–I2S-bus input: bit SPDSEL must be set to logic 0 and

de-emphasis can be controlled via bits DE0
and DE1.

8.5.3 AUDIO FEATURE PROCESSOR

The audio feature processor automatically provides
de-emphasis for the IEC 958 data stream in the static pin
control mode and default mute at start-up in the L3 control
mode.

Whenused in the L3 controlmode it provides thefollowing
additional features:

• Volume control using 6 bits

• Bass boost control using 4 bits

• Treble control using 2 bits

• Mode selection of the sound processing bass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off

• De-emphasis selection of the incoming data stream for

fs= 32.0, 44.1 and 48.0 kHz.

8.5.4 INTERPOLATOR
The UDA1351H includes an on-board interpolating filter

which converts the incoming data stream from 1fsto 128f
by cascading a recursive filter and a FIR filter.

Table 2 Interpolator characteristics

PARAMETER CONDITIONS VALUE (dB)

Pass-band ripple 0f

to 0.45f

s

Stop band >0.65f
Dynamic range 0f

to 0.45f

s

s

s

s

±0.03

−50

115

DC gain −−3.5

8.5.5 NOISE SHAPER
The third-order noise shaper operates at 128fs. It shifts

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.

8.5.6 THE FILTER STREAM DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an
analog output voltage.

The filter coefficients are implemented as current sources
andaresummed at virtual ground of the outputoperational
amplifier. In this way very high signal-to-noise
performance and low clock jitter sensitivity is achieved.
A post filter is not needed dueto the inherent filter function
of the DAC. On-board amplifiers convert the FSDAC
output current to an output voltage signal capable of
driving a line output.

The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.

s

2000 Feb 18 12

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2000 Feb 18 13

handbook, full pagewidth

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

MSB B2

LEFT

RIGHT

3

21> = 812 3

MSB MSBB2

2

I

S-BUS FORMAT

LEFT

16

MSB

LEFT

16

MSB B2 B3 B4 B5 B6

LEFT

16

15 2 1

B2

1518 1720 19 2 1

1518 1720 1922 212324 2 1

B15

LSB-JUSTIFIED FORMAT 16 BITS

B19

LSB-JUSTIFIED FORMAT 20 BITS

> = 8

LSB

LSB

RIGHT

16

MSB B2

RIGHT

16

MSB B2 B3 B4 B5 B6

RIGHT

16

15 2 1

B15 LSB

1518 1720 19 2 1

B19 LSB

1518 1720 1922 212324 21

DATA

MSB

B23

B2

B3 B4

B5 B6 B7 B8 B9 B10

LSB-JUSTIFIED FORMAT 24 BITS

LSB

MSB

B2

B3 B4

B5 B6 B7 B8 B9 B10

B23 LSB

MGS752

Fig.5 Digital data interface formats.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.6 Control

The UDA1351H can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the
UDA1351H the L3 control mode is recommended since only basic functions are available in the static pin control mode.

It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control
mode pins L3MODE and L3DATA are used to select the format for the data output and input interface.

8.6.1 STATIC PIN CONTROL MODE

The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode.

Table 3 Pin description of static pin control mode

PIN NAME VALUE FUNCTION

Mode selection pin

35 SELSTATIC 1 select static pin control mode; must be connected to V

Input pins

1 RESET 0 normal operation

1 reset

6 L3CLOCK 0 must be connected to V

10 and 5 L3MODE and

L3DATA

00 select I2S-bus format for digital data interface
01 select LSB-justified format 16 bits for digital data interface

SSD

10 select LSB-justified format 20 bits for digital data interface
11 select LSB-justified format 24 bits for digital data interface

12 MUTE 0 normal operation

1 mute active

13 SELCHAN 0 select input SPDIF0 (channel 0)

1 select input SPDIF1 (channel 1)

19 SELCLK 0 slave to f

1 slave to f

from IEC 958; master on data output and input interfaces

s

from digital data input interface

s

20 SELSPDIF 0 select data from digital data interface to DAC output

1 select data from IEC 958 decoder to DAC output

Status pins

21 LOCK 0 clock regeneration or IEC 958 decoder out-of-lock or non-PCM data detected

1 clock regeneration and IEC 958 decoder locked plus PCM data detected

30 and 42 PREEM1 and

PREEM0

00 IEC 958 input: no pre-emphasis
01 IEC 958 input: f
10 IEC 958 input: f
11 IEC 958 input: f

= 32.0 kHz with pre-emphasis

s

= 44.1 kHz with pre-emphasis

s

= 48.0 kHz with pre-emphasis

s

Test pins

23 TC 0 must be connected to digital ground (V
34 TEST1 1 must be connected to digital supply voltage (V
39 TEST2 0 must be connected to digital ground (V
44 RTCB 0 must be connected to digital ground (V

SSD

SSD
SSD

)

DDD

)
)

DDD

)

2000 Feb 18 14

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.6.2 L3 CONTROL MODE

The L3 control mode allows maximum flexibility in controlling the UDA1351H.
It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and

that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface.
Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device

for reliable operation.

Table 4 Pin description in the L3 control mode

PIN NAME VALUE FUNCTION

Mode selection pin

35 SELSTATIC 0 select L3 control mode; must be connected to V

Input pins

1 RESET 0 normal operation

1 reset
5 L3DATA − must be connected to the L3-bus
6 L3CLOCK − must be connected to the L3-bus

10 L3MODE − must be connected to the L3-bus

Status pins

21 LOCK 0 clock regeneration or IEC 958 decoder out-of-lock

1 clock regeneration and IEC 958 decoder locked

30 and 42 PREEM1 and

PREEM0

00 IEC 958 input: no-pre-emphasis
01 IEC 958 input: f
10 IEC 958 input: f
11 IEC 958 input: f

= 32.0 kHz with pre-emphasis

s

= 44.1 kHz with pre-emphasis

s

= 48.0 kHz with pre-emphasis

s

Test pins

23 TC 0 must be connected to ground (V
34 TEST1 1 must be connected to supply voltage (V
39 TEST2 0 must be connected to ground (V
44 RTCB 0 must be connected to ground (V

SSD

SSD
SSD

)

DDD

)
)

SDD

)

2000 Feb 18 15

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7 L3 interface

8.7.1 GENERAL
TheUDA1351HhasanL3 microcontrollerinterface and all

the digital sound processing features and various system
settings can be controlled by a microcontroller.

The controllable settings are:

• Restoring L3 defaults

• Power-on

• Selection of input channel, clock source, DAC input and

external input format

• Selection of filter mode and settings of treble and bass
boost

• Volume settings

• Selectionof soft mute viacosine roll-off (only effectivein

L3 control mode) and bypass of auto mute

• Selection of de-emphasis.

The readable settings are:

• Mute status of interpolator

• PLL locked

• SPDIF input signal locked

• Audio Sample Frequency (ASF)

• Valid PCM data detected

• Pre-emphasis of the IEC 958 input signal

• ACcuracy of the Clock (ACC).

Theexchange of data andcontrol information between the
microcontroller and the UDA1351H is LSB first and is
accomplished through a serial hardware L3 interface
comprising the following pins:

• L3DATA: data line

• L3MODE: mode line

• L3CLK: clock line.

The exchange of bytes via the L3 interface is LSB first.
The L3 format has 2 modes of operation:

• Address mode

• Data transfer mode.

The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6).

Basically 2 types of data transfers can be defined:

• Write action: data transfer to the device

• Read action: data transfer from the device.

Remark: when the device is powered up, at least one
L3CLOCK pulse must be given to the L3 interface to
wake-uptheinterfacebefore starting sending to the device
(see Fig.6). This is only needed once after the device is
powered up.

8.7.2 DEVICE ADDRESSING
The device address consists of 1 byte with:

• Bits 0 and 1 (called DOM bits) representing the type of
data transfer (see Table 5)

• Bits 2 to 7 (address bits) representing a 6-bit device
address.

Table 5 Selection of data transfer

DOM

TRANSFER

BIT 0 BIT 1

0 0 not used
1 0 not used
0 1 write data or prepare read
1 1 read data

8.7.3 REGISTER ADDRESSING

After sending the device address, including Data
Operating Mode (DOM) bits indicating whether the
information is to be read or written, 1 data byte is sent
using bit 0 to indicate whether the information will be read
or written and bits 1 to 7 for the destination register
address.

Basically there are 3 methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a

write action to the destination register, followed by
bits 1 to 7 indicating the register address (see Fig.6)

2. Addressing for prepare read: bit 0 is logic 1 indicating

that data will be read from the register (see Fig.7)

3. Addressingfordataread action: in this case the device

returns a register address prior to sending data from
thatregister.When bit 0 is logic 0, the registeraddress
is valid; in case bit 0 is logic 1 the register address is
invalid.

The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.

2000 Feb 18 16

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2000 Feb 18 17

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

register address

data byte 1 data byte 2

MGS753

L3DATA

device address

0

10

DOM bits

write

Fig.6 Data write mode (for L3 version 2).

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

L3CLOCK

L3MODE

L3DATA

device address

0

111

DOM bits

prepare read send by the device

register address device address register address

1

read

0/1

valid/non-valid

Fig.7 Data read mode.

data byte 1 data byte 2

MGS754

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.4 DATA WRITE MODE
The data write mode is explained in the signal diagram

of Fig.6. For writing data to a device, 4 bytes must be sent
(see Table 6):

1. One byte starting with ‘01’ for signalling the write
action to the device, followed by the device address
(‘011000’ for the UDA1351H)

2. One byte starting with a ‘0’ for signalling the write
action, followed by 7 bits indicating the destination
address in binary format with A6 being the MSB and
A0 being the LSB

3. Two databytes with D15 being theMSB and D0 being
the LSB.

Note: each time a new destination register address needs
to be written, the device address must be sent again.

8.7.5 DATA READ MODE

For reading data fromthe device, firsta prepare readmust
be done and then data read. The data read mode is
explained in the signal diagram of Fig.7.

Table 6 L3 write data

For reading data from a device, the following 6 bytes are
involved (see Table 7):

1. One byte with the device address including ‘01’ for
signalling the write action to the device

2. One byte is sent with the register address from which
data needs to be read; this byte starts with a ‘1’, which
indicates that there will be a read action from the
register, followed again by 7 bits for the destination
address in binary format with A6 being the MSB and
A0 being the LSB

3. One byte with the device addressincluding ‘11’ is sent
to the device; the ‘11’ indicates that the device must
write data to the microcontroller

4. One byte, sent by the device to the bus, with the
(requested) register address and a flag bit indicating
whetherthe requested register was valid(bit is logic 0)
or invalid (bit is logic 1)

5. Two bytes, sent bythe device to the bus, with the data
information in binary format with D15 being the MSB
and D0 being the LSB.

BYTE L3 MODE ACTION

1 address device address 01011000
2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0
3 data transfer data byte1 D15 D14 D13 D12 D11 D10 D9 D8
4 data transfer data byte2 D7 D6 D5 D4 D3 D2 D1 D0

Table 7 L3 read data

BYTE L3 MODE ACTION

1 address device address 01011000
2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0
3 address device address 11011000
4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0
5 data transfer data byte1 D15 D14 D13 D12 D11 D10 D9 D8
6 data transfer data byte2 D7 D6 D5 D4 D3 D2 D1 D0

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2000 Feb 18 18

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.6 INITIALIZATION STRING
For proper and reliable operation it is needed that the UDA1351H is initialized in the L3 control mode. This is needed to

have the PLL start up after power-up of the device under all conditions. The initialization string is given in Table 8.

Table 8 L3 init string and set defaults after power-up.

BYTE L3 MODE ACTION

1 address init string device address 01011000
2 data transfer register address 01000000
3 data transfer data byte 1 00000000
4 data transfer data byte 2 00000011
5 address set defaults device address 01011000
6 data transfer register address 01111111
7 data transfer data byte 1 00000000
8 data transfer data byte 2 00000000

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2000 Feb 18 19

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2000 Feb 18 20

8.7.7 OVERVIEW OF L3 INTERFACE REGISTERS
Table 9 UDA1351H register map

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

ADDR FUNCTION

Writable settings

00H system

parameters
default 1 0 0 1 0 0

10H sound

features
default 0 0 0 0 0 0 0 0 0 0 1

11H volume

control DAC
default 00 0 000

40H multiplex

parameters
default 0

7FH restore

L3 defaults

Readable settings

18H interpolator

parameters

38H SPDIF input

and lock
parameters

BIT

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PON CHAN

sel

IIS sel SPD

sel

SFOR1 SFOR0

M1 M0 BB3 BB2 BB1 BB0 TR1 TR0 DE1 DE0 MT

VC5 VC4 VC3 VC2 VC1 VC0

AutoMTRST

PLL

(1)

(1)

0

(1)

0

(1)

0

10

MT
stat

PLL
lock

SPD
lock

ASF1 ASF0 PCM

stat

PRE ACC1 ACC0

Note

1. When writing new settings via the L3 interface, these bits should always remain logic 0 (default value) to warrant correct operation.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.8 WRITABLE REGISTERS

8.7.8.1 Restoring L3 defaults

By writing to the 7FH register, all L3 control values are
restored to their default values. Only the L3 interface is
affected, the system will not be reset. Consequently
readable registers, which are not reset, can be affected.

8.7.8.2 Power-on

A 1-bit value to switch the DAC on and off.

Table 10 Power-on setting

PON FUNCTION

0 power-down
1 power-on (default setting)

8.7.8.3 Slicer input selection

A 1-bit value to select an IEC 958 input channel.

Table 11 Slicer input selection

CHAN sel FUNCTION

0 IEC 958 input from pin SPDIF0

(default setting)

1 IEC 958 input from pin SPDIF1

8.7.8.4 Clock source selection

A 1-bit value to select the source for clock regeneration,
eitherfrom the IEC 958 inputor digital data inputinterface.
In the event that the IEC 958 input is used as a clock
source the UDA1351H is clock master on the digital data
output and input interfaces.

Table 12 Clock source selection

IIS sel FUNCTION

0 slave to audio sampling frequency of

IEC 958 input (default setting)

1 slave to audio sampling frequency of

digital data input interface

8.7.8.5 DAC input selection

A 1-bit value to select the data source, either the IEC 958
input or the digital data input interface.

Table 13 DAC input selection

SPD sel FUNCTION

0 input from data input interface
1 input from IEC 958 (default setting)

8.7.8.6 Serial format selection

A 2-bit value to set the serial format for the digital data
output and input interfaces.

Table 14 Serial format settings

SFOR1 SFOR0 FUNCTION

2

00I
0 1 LSB-justified, 16 bits
1 0 LSB-justified, 20 bits
1 1 LSB-justified, 24 bits

S-bus (default settings)

8.7.8.7 Filter mode selection

A 2-bit value to program the mode for the sound
processing filters of bass boost and treble.

Table 15 Filter mode settings

M1 M0 FUNCTION

0 0 flat (default setting)
0 1 minimum
10
1 1 maximum

8.7.8.8 Treble

A 2-bit value to program the treble setting in combination
with the filter mode settings. At fs= 44.1 kHz the −3dB
point for minimum setting is 3.0 kHz and the −3 dB point
for maximum setting is 1.5 kHz. The default value is ‘00’.

Table 16 Treble settings

TR1 TR0

FLAT (dB) MIN. (dB) MAX. (dB)

00000
01022
10044
11066

LEVEL

2000 Feb 18 21

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.8.9 Bass boost

A 4-bit value to program the bass boost setting in
combination with the filter mode settings. At fs= 44.1 kHz
the −3 dB point for minimum setting is 250 Hz and the

−3 dB point for maximum setting is 300 Hz. The default
value is ‘0000’.

Table 17 Bass boost settings

LEVEL

BB3 BB2 BB1 BB0

FLAT

(dB)

MIN.

(dB)

MAX.

(dB)

0000000
0001022
0010044
0011066
0100088
010101010
011001212
011101414
100001616
100101818
101001820
101101822
110001824
110101824
111001824
111101824

8.7.8.10 De-emphasis

A 2-bit value to enable the digital de-emphasis filter.

Table 18 De-emphasis selection

DE1 DE0 FUNCTION

0 0 other (default setting)
01f
10f
11f

= 32.0 kHz

s

= 44.1 kHz

s

= 48.0 kHz

s

8.7.8.11 Soft mute

A 1-bit value to enable the digital mute.

Table 19 Soft mute selection

MT FUNCTION

0 no muting
1 muting (default setting)

8.7.8.12 Volume control

A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to −60 dB and −∞ dB in
steps of 1 dB.

Table 20 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
110011
110100
110101
110110
110111
111000

−51

−52

−54

111001

−57111010
111011
111100
111101
111110
111111

−60

−∞

2000 Feb 18 22

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.8.13 Auto mute

A 1-bit value to activate mute during out-of-lock. In normal
operation the output is automatically hard muted when an
out-of-lock situation is detected. Setting this bit to logic 0
will disable that function.

Table 21 Auto mute setting

Auto MT FUNCTION

0 do not mute output during out-of-lock
1 mute output during out-of-lock (default

setting)

8.7.8.14 PLL reset

A 1-bit value to reset the PLL. This is the bit which is set in
the initialization string. When this bit is asserted, the PLL
will be reset and the output clock of the PLL will be forced
to its lowest value, which is in the area of a few MHz.

Table 22 PLL reset

RST PLL FUNCTION

0 normal operation (default)
1 PLL is reset

8.7.9.2 PLL lock detection

A 1-bit value indicating that the clock regeneration is
locked.

Table 24 PLL lock indication

PLL lock FUNCTION

0 out-of-lock
1 locked

8.7.9.3 SPDIF lock detection

A 1-bit value indicating the IEC 958 decoder is locked and
is decoding correct data.

Table 25 SPDIF lock detection

SPD lock FUNCTION

0 not locked or non-PCM data detected
1 locked and PCM data detected

8.7.9.4 Audio sample frequency detection

A 2-bit value indicating the audio sample frequency of the
IEC 958 input signal.

8.7.9 READABLE REGISTERS

8.7.9.1 Mute status

A 1-bit value indicating whether the interpolator is muting
or not muting.

Table 23 Interpolator mute status

MT stat FUNCTION

0 no muting
1 muting

Table 26 Audio sample frequency detection

ASF1 ASF0 FUNCTION

0 0 44.1 kHz
0 1 undefined
1 0 48.0 kHz
1 1 32.0 kHz

2000 Feb 18 23

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

8.7.9.5 PCM detection

A 1-bit value which indicates whether the IEC 958 input
contains PCM audio data or other binary data.

Table 27 Two-channel PCM input detection

PCM stat FUNCTION

0 input with 2 channel PCM data
1 input without 2 channel PCM data

8.7.9.7 Clock accuracy detection

A 2-bit value indicating the timing accuracy of the IEC 958
input signal is conforming to the IEC 958 specification.

Table 29 Input signal accuracy detection

ACC1 ACC0 FUNCTION

0 0 level II
01levelI
1 0 level III

8.7.9.6 Pre-emphasis detection

1 1 undefined

A 1-bitvalue which indicates whetherthe pre-emphasis bit
was set on the IEC 958 input signal or not set.

Table 28 Pre-emphasis detection

PRE FUNCTION

0 no pre-emphasis
1 pre-emphasis

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
T
T
T
V

DD
xtal
stg
amb

es

supply voltage note 1 2.7 5.0 V
crystal temperature −25 +150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage Human Body Model (HBM); note 2 −2000 +2000 V

Machine Model (MM) −200 +200 V

I

lu(prot)

I

sc(DAC)

latch-up protection current note 3 − 200 mA
short-circuit current of DAC note 4

output short-circuited to V
output short-circuited to V

SSA(DAC)
DDA(DAC)

− 482 mA

− 346 mA

Notes

1. All V

2. JEDEC class 2 compliant, except pin V

3. Latch-up test at T

4. Short-circuit test at T

and VSS connections must be made to the same power supply.

DD

which can withstand ESD pulses of −1600 to +1600 V.

= 125 °C and VDD= 3.6 V.

amb

=0°C and VDD= 3 V. DAC operation after short-circuiting cannot be warranted.

amb

SSA(PLL)

10 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 63 K/W

2000 Feb 18 24

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

11 CHARACTERISTICS

V

DDD=VDDA

ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies; note 1

V

DDA

V

DDA(DAC)

V

DDA(PLL)

V

DDD

V

DDD(C)

I

DDA(DAC)

I

DDA(PLL)

I

DDD(C)

I

DDD

P power consumption at 48 kHz DAC in playback mode − 80 − mW

Digital input pins

V

IH

V

IL

V

hys(RESET)

I

 input leakage current −−10 µA

LI

C

i

R

pu(int)

R

pd(int)

Digital output pins

V

OH

V

OL

I

L(max)

Digital-to-analog converter; note 2
V

ref

V

o(rms)

= 3.0 V; IEC 958 input with fs= 48.0 kHz; T

=25°C; RL=5kΩ; all voltages measured with respect to

amb

analog supply voltage 2.7 3.0 3.6 V
analog supply voltage for DAC 2.7 3.0 3.6 V
analog supply voltage for PLL 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital supply voltage for core 2.7 3.0 3.6 V
analog supply current of DAC power-on − 8.0 − mA

power-down − 750 −µA

analog supply current of PLL at 48 kHz − 0.7 − mA

at 96 kHz − 1.0 − mA

digital supply current of core at 48 kHz − 16.0 − mA

at 96 kHz − 24.5 − mA

digital supply current at 48 kHz − 2.0 − mA

at 96 kHz − 3.0 − mA

DAC in Power-down mode − 58 − mW

power consumption at 96 kHz DAC in playback mode − 109 − mW

DAC in Power-down mode − 87 − mW

HIGH-level input voltage 0.8V
LOW-level input voltage −0.5 − +0.2V
hysteresis voltage on

− 0.8 − V

− VDD+ 0.5 V

DD

DD

pin RESET

input capacitance −−10 pF
internal pull-up resistance 16 33 78 kΩ
internal pull-down resistance 16 33 78 kΩ

HIGH-level output voltage IOH= −2 mA 0.85V

−−V

DD

LOW-level output voltage IOL=2mA −−0.4 V
maximum load current − 3 − mA

reference voltage measured with respect to

V

SSA

0.45V

DDA

0.50V

DDA

0.55V

DDA

output voltage (RMS value) note 3 − 900 − mV

V

V

2000 Feb 18 25

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(THD + N)/S total harmonic

distortion-plus-noise to signal
ratio

S/N signal-to-noise ratio at 48 kHz f

signal-to-noise ratio at 96 kHz f

α
∆V

cs

o

channel separation fi= 1.0 kHz tone − 96 − dB
unbalance of output voltages fi= 1.0 kHz tone 0.4 0.1 − dB

IEC 958 inputs

V

i(p-p)

AC input voltage
(peak-to-peak value)

R

i

V

hys

input resistance − 6 − kΩ
hysteresis voltage − 40 − mV

Notes

1. All supply pins VDD and VSS must be connected to the same external power supply unit.

2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω must be used in
order to prevent oscillations in the output stage of the operational amplifier.

3. The output voltage of the DAC is proportional to the DAC power supply voltage.

fi= 1.0 kHz tone at 48 kHz

at 0 dB −−90 −85 dB
at −40 dB; A-weighted −−60 −55 dB

f

= 1.0 kHz tone at 96 kHz

i

at 0 dB −−85 −80 dB
at −40 dB; A-weighted −−58 −53 dB

= 1.0 kHz tone; code = 0;

i

95 100 − dB

A-weighted

= 1.0 kHz tone; code = 0;

i

95 100 − dB

A-weighted

0.2 0.5 3.3 V

12 TIMING CHARACTERISTICS

V

DDD=VDDA

= 2.7 to 3.6 V; T

= −40 to +85 °C; RL=5kΩ; all voltages measured with respect to ground; unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Device reset

t

rst

reset active time − 250 −µs

PLL lock time

t

lock

2

S-bus timing (see Fig.8)

I

T

cy(BCK)

time to lock fs= 32.0 kHz − 85.0 − ms

f

= 44.1 kHz − 63.0 − ms

s

f

= 48.0 kHz − 60.0 − ms

s

f

= 96.0 kHz − 40.0 − ms

s

bit clock cycle time Ts= cycle time of sample

−−

1

⁄

64Ts

frequency

t

BCKH

t

BCKL

t

r

bit clock HIGH time 140 − 280 ns
bit clock LOW time 140 − 280 ns
rise time −−20 ns

2000 Feb 18 26

s

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

f

t

su(WS)

t

h(WS)

t

su(DATAI)

t

h(DATAI)

t

h(DATAO)

t

d(DATAO-BCK)

t

d(DATAO-WS)

Microcontroller L3 interface timing (see Figs 9 and 10)
T

cy(CLK)(L3)

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

h(L3)A

t

su(L3)D

t

h(L3)D

t

(stp)(L3)

t

su(L3)DA

t

h(L3)DA

t

su(L3)R

t

h(L3)R

fall time −−20 ns
set-up time word select 20 −−ns
hold time word select 10 −−ns
set-up time data input 20 −−ns
hold time data input 0 −−ns
hold time data output 0 −−ns
data output to bit clock delay −−80 ns
data output to word select

−−80 ns

delay

L3CLOCK cycle time 500 −−ns
L3CLOCK HIGH time 250 −−ns
L3CLOCK LOW time 250 −−ns
L3MODE set-up time in

190 −−ns

address mode
L3MODE hold time in address

190 −−ns

mode
L3MODE set-up time in data

190 −−ns

transfer mode
L3MODE hold time in data

190 −−ns

transfer mode
L3MODE stop time in data

190 −−ns

transfer mode
L3DATA set-up time in

190 −−ns
address and data transfer
mode

L3DATA hold time in address

30 −−ns
and data transfer mode

L3DATA set-up time in data

read mode 50 −−ns

transfer mode
L3DATA hold time in data

read mode 360 −−ns

transfer mode

2000 Feb 18 27

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

handbook, full pagewidth

WS

t

BCK

DATAO

BCKH

t

r

T

cy(BCK)

t

f

t

BCKL

t

h(WS)

t

d(DATAO-WS)

t

su(WS)

t

h(DATAO)

t

su(DATAI)

t

d(DATAO-BCK)

t

h(DATAI)

DATAI

handbook, full pagewidth

L3MODE

L3CLOCK

Fig.8 I2S-bus timing of output and input interface.

t

h(L3)A

t

su(L3)A

t

su(L3)DA

t

CLK(L3)L

t

CLK(L3)H

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

MGS756

L3DATA

BIT 0

Fig.9 Timing for address mode.

2000 Feb 18 28

BIT 7

MGL723

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

L3DATA

write

read

t

t

su(L3)D

t

en(L3)DA

stp(L3)

t

CLK(L3)L

t

CLK(L3)H

t

su(L3)R

t

su(L3)DA

t

h(L3)DA

BIT 0

t

h(L3)R

Fig.10 Timing for data transfer mode.

T

cy(CLK)L3

t

t

h(L3)DA

BIT 7

t

dis(L3)DA

h(L3)D

t

stp(L3)

MGL889

2000 Feb 18 29

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2000 Feb 18 30

V

V

L3-bus

channel 0

channel 1

ground

+3 V

clock

output

DDD(C)

V

DDA

DDD(C)

IEC

IEC

AGND DGND

C3

100 µF

(16 V)

AGND DGND

L27

BZN32A07

X16

X11

X17

X12

SPDIF0

C5

100 µF

(16 V)

static

R41

75 Ω

R42

75 Ω

SPDIF1

C11

100 µF

(16 V)

J14

L3

J28

J1
J3

J2

V

3
2
1

3
2
1

DDA

V

C48

180 pF

(50 V)

C49

180 pF

(50 V)

V

V

DDA

V

DDD(C)

V

DDD

BZN32A07

C41

100 nF

(50 V)

DDD(C)

DDD(C)

L26

C45

10 nF
(50 V)

C46

10 nF
(50 V)

C12

100 µF

(16 V)

X1-34
X1-27
X1-26

X1-2
X1- 4

X1-6

X1-10

X1-5

X1-35

X1-15

X1-16

X1-13

V

DDD

V
V

L3CLOCK

L3MODE

SELSTATIC

SELCHAN

R38

1 Ω

C42

100 nF

(50 V)

TEST1

V

DDA

V

SSA
DDD(C)
SSD(C)

L3DATA

SPDIF0

SPDIF1

100 µF

(16 V)

X1-32

X1-31

X1-29

X1-28

DDA(PLL)

SSA(PLL)

V

V

C28

100 nF

(50 V)

43

DDD

V

X1-43

32

3

SSD

V

X1-3

lock

34
27
26
2
4

6

10

5

35

15

16

13

C9

CLKOUT

29

21

LOCK

X1-21

R39

1 kΩ

V5

n.c.
28

42

PREEM0

X1-42

pre­emphasis
indication

ndbook, full pagewidth

X1-39

TEST2
39

UDA1351H

30

36

DATAO

PREEM1

X1-30

X1-36

37

WSO

X1-37

I2S-bus

output

X1-38

n.c.
38

33

X1-33

X1-40

n.c.
40

BCKO

X1-41

n.c.
4131

7

DATAI

X1-7

I2S-bus

BCKI

X1-8

input

L29

R44

100 Ω

R46

100 Ω

3
2
1

3
2
1

3
2
1

J26

mute
no mute

J17

1 RTCB
0

J25

1 TC
0

MGL978

V

C13
10 µF
(16 V)

100 µF

(16 V)

C40

100 nF

(50 V)

C15

47 µF
(16 V)

C16

47 µF
(16 V)

C14

V

DDD(C)

V

DDD(C)

V

DDD(C)

2

S-bus

2

S-bus

BZN32A07

C44

100 nF

(50 V)

V

DDD(C)

R43
10 kΩ

R45
10 kΩ

C43

100 nF

(50 V)

X1-25

X1-17

SSA(DAC)

DDA(DAC)

V

V

2517

24

1

12

11
14

44

23

18

19

SELCLK

X1-19

22

20

SELSPDIF

X1-20

8

9

WSI

X1-9

V

ref

RESET

MUTE

n.c.
n.c.

RTCB

TC

VOUTL

VOUTR

V

DDD(C)

V

DDD(C)

X1-24

X1-1

X1-12

X1-11
X1-14

X1-44

X1-23

X1-18

X1-22

3
2
1

3
2
1

J32

data IEC
data I

J31

clock I
clock IEC

X18

X13

X19

X14

DDA

output

left

output

right

13 APPLICATION INFORMATION

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

Fig.11 Test and application diagram.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

14 PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

pin 1 index

44

1

22

Z

E

e

H

E

E

w M

b

p

12

11

A

2

A

A

1

detail X

SOT307-2

(A )

3

θ

L

p

L

w M

b

e

p

D

H

D

Z

D

B

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

0.25

UNIT A1A2A3b

cE

p

0.40

0.25

0.20

0.14

(1)

(1) (1)(1)

D

10.1

9.9

eH

10.1

9.9

12.9

0.8 1.3

12.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

IEC JEDEC EIAJ

REFERENCES

SOT307-2

2000 Feb 18 31

v M

H

v M

D

A

B

E

12.9

12.3

LL

p

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

1.2

0.8

o

10

o

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

15 SOLDERING

15.1 Introduction to soldering surface mount
packages

Thistextgivesa very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wavesoldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling)vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadson four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

2000 Feb 18 32

15.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

15.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2000 Feb 18 33

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

NOTES

2000 Feb 18 34

Philips Semiconductors Preliminary specification

96 kHz IEC 958 audio DAC UDA1351H

NOTES

2000 Feb 18 35

Philips Semiconductors – a w orldwide compan y

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Portugal: see Spain
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Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 753503/25/01/pp36 Date of release: 2000 Feb 18 Document order number: 9397750 06659