Datasheet UDA1344TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1344TS

Low-voltage low-power stereo
audio CODEC with DSP features

Preliminary specification
File under Integrated Circuits, IC01

1998 Jul 28

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

FEATURES
General

• Low power consumption

• 3.0 V power supply

• 256, 384 and 512f

• Support sampling frequencies from 16 to 48 kHz

• Non-inverting ADC plus integrated high pass filter to

cancel DC offset

• The ADC supports 2 V (RMS) input signals

• Overload detector for easy record level control

• Separate power control for ADC and DAC

• Integrated digital interpolation filter plus non-inverting

DAC

• Functions controllable either by L3 microcontroller
interface or via static pins

• The UDA1344TS is pin and function compatible with the
UDA1340M

• Small package size (SSOP28)

• Easy application.

Multiple format input interface

2

• I

S-bus, MSB-justified and LSB-justified

16, 18 and 20 bits format compatible

• Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input

• 1fs input and output format data rate.

DAC digital sound processing

The sound processing features of the UDA1344TS can
only be used in L3 microcontroller mode.

• Digital tone control, bass boost and treble

• Digital dB-linear volume control (low microcontroller

load) via L3 microcontroller

• Digital de-emphasis for 32, 44.1 and 48 kHz f

• Soft mute.

system clock

s

s

UDA1344TS

Advanced audio configuration

• Stereo single-ended input configuration

• Stereo line output (under microcontroller volume

control), no post filter required

• Power-down click prevention circuitry

• High linearity, dynamic range and low distortion.

GENERAL DESCRIPTION

The UDA1344TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.

The UDA1344TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1344TS also supports three combined data
formats with MSB-justified data output and LSB
16, 18 and 20 bits data input.

The UDA1344TS can be used either with static pin control
or under L3 microcontroller interface. Under L3 control the
UDA1344TS has special sound processing features in
playback mode such as de-emphasis, volume control,
bass boost, treble and soft mute.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UDA1344TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

1998 Jul 28 2

PACKAGE

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDO

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDO

I

DDD

I

pd(ADC)

I

pd(DAC)

T

amb

Analog-to-digital converter

V

i(rms)

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio V

α

cs

Digital-to-analog converter

V

o(rms)

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB

α

cs

Power performance

P

ADDA

P

DA

P

AD

P

PD

ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
operational amplifiers supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
ADC supply current operation mode − 9.0 11.0 mA

ADC power-down − 3.5 5.0 mA

DAC supply current operation mode − 4.0 6.0 mA

DAC power-down − 25 75 µA

operational amplifier supply current operation mode − 4.0 6.0 mA

DAC power-down − 250 350 µA
digital supply current operation mode − 6.0 9.0 mA
digital ADC power-down supply current − 2.5 4.0 mA
digital DAC power-down supply current − 3.5 5.0 mA
operating ambient temperature −20 − +85 °C

input voltage (RMS value) notes 1 and 2 − 1.0 − V

at 0 dB −−85 −80 dB
noise-to-signal ratio

at −60 dB; A-weighted −−35 −30 dB

= 0 V; A-weighted − 95 − dB

i

channel separation − 100 − dB

output voltage (RMS value) notes 3 and 4 − 900 − mV

at 0 dB −−90 −85 dB
noise-to-signal ratio

at −60 dB; A-weighted −−37 − dB

channel separation − 100 − dB

power consumption in record and

− 69 − mW

playback mode
power consumption in playback only

− 42 − mW

mode
power consumption in record only

− 37.5 − mW

mode
power consumption in power-down

− 17 − mW

mode

Notes

1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to about 1 mA by
using a series resistor.

2. The input voltage to the ADC scales inversely proportional with respect to the power supply.

3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.

4. The output of the DAC scales proportional with the power supply voltage.

1998 Jul 28 3

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

BLOCK DIAGRAM

handbook, full pagewidth

V

V

VINL

DDD

SSD

V

DDA(ADC)VSSA(ADC)

21

3 5

0 dB/6 dB

SWITCH

10

11

DC-CANCELLATION FILTER

V

ADCP

76 4

ADC

DECIMATION FILTER

ADC

V

ADCN

V

0 dB/6 dB

SWITCH

ref(A)

UDA1344TS

VINR

8

MC1

21

MC2

20

MP5

DATAO

BCK

WS

DATAI

MP1

VOUTL

18
16
17
19

9

UDA1344TS

26

DIGITAL INTERFACE

DSP FEATURES

INTERPOLATION FILTER

NOISE SHAPER

DAC

25 27 23 22

V

DDO

V

SSO

V

DAC

DDA(DAC)VSSA(DAC)

L3-BUS

INTERFACE

V

28

ref(D)

13

MP2

14

MP3

15

MP4

12

SYSCLK

24

VOUTR

MGL441

Fig.1 Block diagram.

1998 Jul 28 4

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

PINNING

SYMBOL PIN DESCRIPTION

V

SSA(ADC)

V

DDA(ADC)

VINL 3 ADC input left
V

ref(A)

VINR 5 ADC input right
V

ADCN

V

ADCP

MC1 8 mode control 1 (pull-down)
MP1 9 multi purpose pin 1
V

DDD

V

SSD

SYSCLK 12 system clock 256, 384 or 512f
MP2 13 multi purpose pin 2
MP3 14 multi purpose pin 3
MP4 15 multi purpose pin 4
BCK 16 bit clock input
WS 17 word select input
DATAO 18 data output
DATAI 19 data input
MP5 20 multi purpose pin 5 (pull down)
MC2 21 mode control 2 (pull-down)
V

SSA(DAC)

V

DDA(DAC)

VOUTR 24 DAC output right
V

DDO

VOUTL 26 DAC output left
V

SSO

V

ref(D)

1 ADC analog ground
2 ADC analog supply voltage

4 ADC reference voltage

6 ADC negative reference voltage
7 ADC positive reference voltage

10 digital supply voltage
11 digital ground

22 DAC analog ground
23 DAC analog supply voltage

25 operational amplifier supply voltage

27 operational amplifier ground
28 DAC reference voltage

UDA1344TS

handbook, halfpage

s

V

SSA(ADC)

V

DDA(ADC)

V

ref(A)

V

ADCN

V

ADCP

V

V

SYSCLK

VINL

VINR

MC1

MP1

DDD

SSD

MP2
MP3

1
2
3
4
5
6
7

UDA1344TS

8

9
10
11
12
13

MGL442

Fig.2 Pin configuration.

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

V

ref(D)

V

SSO

VOUTL
V

DDO

VOUTR
V

DDA(DAC)

V

SSA(DAC)

MC2
MP5
DATAI
DATAO
WS
BCK
MP4

1998 Jul 28 5

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

FUNCTIONAL DESCRIPTION

The UDA1344TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock.

The system clock must be locked in frequency to the audio
digital interface input signals.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1344TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input and can be set, via an external resistor,
to support 2 V (RMS) input.

Analog front-end

The analog front-end is equipped with a selectable 0 dB or
6 dB gain block (the pin to select this mode is given in
Section “L3 microcontroller mode”. This block can be used
in applications in which both 1 V (RMS) and 2 V (RMS)
input signals can be input to the UDA1344TS.

In applications in which 2 V (RMS) is used as input signal,
a 12 kΩ must be used in series with the input of the ADC.
This makes a voltage divider with the internal ADC resistor
and makes sure only 1 V (RMS) maximum is put into the
IC. Using this application for a 2 V (RMS) input signal, the
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application, the gain switch
must be set to 6 dB.

In Table 1 an overview is given of the maximum input
voltages allowed against the presence of an external
resistor and the setting of the gain switch.

Table 1 Application modes using input gain stage

RESISTOR

(12 kΩ)

Present 0 dB 2 V (RMS) input signal
Present 6 dB 1 V (RMS) input signal
Absent 0 dB 1 V (RMS) input signal
Absent 6 dB 0.5 V (RMS) input signal

Decimation filter (ADC)

The decimation from 128f
The first stage realizes 3rd-order characteristic.

INPUT GAIN

SWITCH

is performed in two stages.

s

MAXIMUM INPUT

VOLTAGE

sin x

----------- ­x

UDA1344TS

This filter decreases the sample rate by 16. The second
stage, an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.

Table 2 Decimation filter characteristics

ITEM CONDITIONS VALUE (dB)

Passband ripple 0 − 0.45f
Stopband >0.55f
Dynamic range 0 − 0.45f
Overall gain when

s

s

s

DC −1.16
0 dB signal is input to
ADC to digital output

Mute (ADC)

On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:

DC cancel off: time =
t = 23.2 ms when f

DC cancel on: time =
t = 279 ms when f

1024

------------ ­f

s

= 44.1 kHz

s

12288

----------------

f

s

= 44.1 kHz

s

Interpolation filter (DAC)

The digital filter interpolates from 1 to 128f
cascade of a recursive filter and an FIR filter.

Table 3 Interpolation filter characteristics

ITEM CONDITIONS VALUE (dB)

Passband ripple 0 − 0.45f
Stopband >0.55f
Dynamic range 0 − 0.45f

s

s

s

Gain DC −3.5

Noise shaper (DAC)

The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.

±0.05

−60

108

by means of a

s

±0.03

−50

108

1998 Jul 28 6

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally
with the power supply voltage.

L3MODE or static pin control

The UDA1344TS can be used under L3 microcontroller
interface mode or under static pin control. The mode can
be set via the Mode Control (MC) pins MC1 (pin 8) and
MC2 (pin 21). The function of these pins is given in
Table 4.

Table 4 Mode Control pins MC1 and MC2

MODE MC2 MC1

L3MODE LOW LOW
Test modes LOW HIGH

HIGH LOW

Static pin mode HIGH HIGH

Important: in L3MODE the UDA1344TS is completely pin
and function compatible with the UDA1340M.

UDA1344TS

Table 5 Pinning definition under L3 control

SYMBOL PIN DESCRIPTION

MP1 9 overload
MP2 13 L3-bus mode input
MP3 14 L3-bus clock input
MP4 15 L3-bus data input
MP5 20 ADC 1 or 2 V (RMS) input control

YSTEM CLOCK

S
Under L3 control the options are 256, 384 and 512fs.

M

ULTIPLE FORMAT INPUT/OUTPUT INTERFACE

The UDA1344TS supports the following data input/output
formats under L3 control:

• I2S-bus with data word length of up to 20 bits

• MSB-justified serial format with data word length of up to

20 bits

• LSB-justified serial format with data word lengths of
16, 18 or 20 bits

• Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits LSB data input.

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.

ADC

INPUT VOLTAGE CONTROL

The UDA1344TS supports 2 V (RMS) input using a series
resistor of 12 kΩ as described in Section “Analog
front-end”. In L3 microcontroller mode, the gain can be
selected via pin MP5.

L3 microcontroller mode

The UDA1344TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.

The definition of the control registers is given in
Section “L3 interface”.

P

INNING DEFINITION

The pinning definition under L3 microcontroller interface is
given in Table 5.

1998 Jul 28 7

When MP5 is set LOW 0 dB gain is selected. When MP5
is set HIGH 6 dB gain is selected.

O

VERLOAD DETECTION (ADC)

In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512fs cycles
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

DC CANCELLATION FILTER (ADC)
An optional IIR high-pass filter is provided to remove

unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.

Table 6 DC cancellation filter characteristics

ITEM CONDITIONS VALUE (dB)

Passband ripple none
Passband gain 0
Droop at 0.00045f
Attenuation at DC at 0.00000036f
Dynamic range 0 − 0.45f

s

s

s

Static pin mode

The UDA1344TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.

P

INNING DEFINITION

The pinning definition under static pin control is given in
Table 7.

0.031
>40

>110

UDA1344TS

MUTE AND DE-EMPHASIS
Under static pin control via MP2 we can select

de-emphasis and mute. The definition of the MP2 pin is
given in Table 9.

Table 9 Settings for pin MP2

MODE MP2

No de-emphasis and mute LOW
De-emphasis 44.1 kHz 0.5V
Muted HIGH

M

ULTIPLE FORMAT INPUT/OUTPUT INTERFACE

The data input/output formats supported under static pin
control.

• I2S-bus with data word length of up to 20 bits

• MSB justified serial format with data word length of up to

20 bits

• Two combined data formats with MSB data output and
LSB 16 and 20 bits LSB data input.

The data formats can be selected using pins MP1 (pin 9)
and MP5 (pin 20) as given in Table 10.

DDD

Table 7 Pinning definition for static pin control

SYMBOL PIN DESCRIPTION

MP1 9 data input/output setting
MP2 13 three level pin controlling

deemphasis and mute

MP3 14 256f

or 384fs system clock

s

MP4 15 three-level pin to control ADC

power mode and 1 V (RMS) or
2 V (RMS) input

MP5 20 data input/output setting

S

YSTEM CLOCK

Under static pin control the options are 256fs and 384fs.
With pin MP3 (pin 14) the mode can be set as is given in
Table 8.

Table 8 System clock settings under static pin mode

MODE MP3

256f

clock mode LOW

s

384f

clock mode HIGH

s

Table 10 Data format settings under static pin control

INPUT FORMAT MP1 MP5

MSB mode LOW LOW

2

I

S-bus LOW HIGH

MSB output

HIGH LOW

LSB 20 input
MSB output

HIGH HIGH

LSB 16 input

The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.

ADC

INPUT VOLTAGE CONTROL

The UDA1344TS supports 2 V (RMS) input using a series
resistor as is described in Section “Analog front-end”.

In static pin mode the three-level pin MP4 (pin 15) is used
to select 0 or 6 dB gain mode. When MP4 is set LOW the
ADC is powered down. When MP4 is set to half the power
supply voltage, then 6 dB gain is selected, and when MP4
is set HIGH then 0 dB gain is selected.

1998 Jul 28 8

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1998 Jul 28 9

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Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

CODEC with DSP features

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

LEFT

>=8 >=8

MSB B2 MSBLSB LSB MSBB2

LEFT

1321

>=8 >=8

MSB B2 MSBLSB LSB MSB B2B2

LEFT

1516 1

MSB LSBB2

LEFT

RIGHT

321321

INPUT FORMAT I

RIGHT

32

MSB-JUSTIFIED FORMAT

2

B15

LSB-JUSTIFIED FORMAT 16 BITS

215161718 1

2

S-BUS

RIGHT

21516 1

MSB LSBB2 B15

RIGHT

215161718 1

DATA

WS

BCK

DATA

MSB B2 B3 B4

LEFT

MSB B2 B3 B4 B5 B6

LSB

B17

LSB-JUSTIFIED FORMAT 18 BITS

2151617181920 1

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

Fig.3 Serial interface formats.

MSB B2 B3 B4

RIGHT

MSB B2 B3 B4 B5 B6

B17

B19

LSB

2151617181920 1

LSB

MGG841

UDA1344TS

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

L3 interface

The UDA1344TS has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:

• System clock frequency

• Data input format

• Power control

• DC-filtering

• De-emphasis

• Volume

• Flat/min./max. switch

• Bass boost

• Treble

• Mute.

The exchange of data and control information between the
microcontroller and the UDA1344TS is accomplished
through a serial hardware interface comprising the
following pins:

L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.

Information transfer via the microcontroller bus is
organized in accordance with the so called ‘L3’ format,
in which two different modes of operation can be
distinguished; address mode and data transfer mode
(see Figs 4 and 5).

The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1344TS can only be in one direction,
input to the UDA1344TS to program its sound processing
and other functional features.

UDA1344TS

Table 11 Selection of data transfer

BIT 1 BIT 0 TRANSFER

0 0 DATA (volume, bass boost, treble,

de-emphasis, mute, mode and power

control)
0 1 not used
1 0 STATUS (system clock frequency, data

input format and DC-filter)
1 1 not used

Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1344TS is 000101 (bit 7 to bit 2). In the event that the
UDA1344TS receives a different address, it will deselect
its microcontroller interface logic.

DATA TRANSFER MODE
The selection preformed in the address mode remains

active during subsequent data transfers, until the
UDA1344TS receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4.
The maximum input clock and data rate is 64fs.
All transfers are byte wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1344TS after the
eighth bit of a byte has been received. A multibyte transfer
is illustrated in Fig.6.

Programming the sound processing and other features

The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, bit 1 and bit 0
(see Table 11). The second selection is performed by the
2 MSBs of the data byte (bit 7 and bit 6). The other bits in
the data byte (bit 5 to bit 0) is the value that is placed in the
selected registers.

A

DDRESS MODE

The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.4. Data bits 0 to 1 indicate the type of
subsequent data transfer as given in Table 11.

1998 Jul 28 10

When the data transfer of type ‘data’ is selected, the
features Volume, Bass boost, Treble, De-emphasis, Mute,
Mode and Power control can be controlled. When the data
transfer of type ‘status’ is selected, the features system
clock frequency, data input format and DC-filter can be
controlled.

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h;MA

t

BIT 0

s;MA

t

s;DAT

t

HC

UDA1344TS

t

BIT 7

t

h;MA

s;MA

MGD016

t

LC

T

cy

t

h;DAT

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

write

t

s;MT

t

halt

BIT 0

Fig.4 Timing address mode.

t

LC

t

s;DAT

T

cy

t

HC

t

h;DAT

t

BIT 7

t

h;MT

h;DAT

t

halt

MGD017

Fig.5 Timing for data transfer mode.

1998 Jul 28 11

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

address

t

halt

UDA1344TS

addressdata byte #1 data byte #2

MGD018

Fig.6 Multibyte transfer.

Table 12 Data transfer of type ‘status’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (5 : 4)

data Input Format (3 : 1)
DC-filter

Table 13 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 VOLUME CONTROL (5 : 0)
0 1 BB3 BB2 BB1 BB0 TR1 TR0 BASS BOOST (5 : 2)

TREBLE (1 : 0)

1 0 0 DE1 DE0 MT M1 M0 DE-EMPHASIS (4 : 3)

MUTE
MODE (1 : 0)

110000PC1PC0POWER CONTROL (1 : 0)

1998 Jul 28 12

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

System clock frequency

A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 14).

Table 14 System clock frequency settings

SC1 SC0 FUNCTION

0 0 512f
0 1 384f
1 0 256f
1 1 not used

Data input format

A 3-bit value (IF2 to IF0) to select the used data format
(see Table 15).

Table 15 Data input format settings

IF2 IF1 IF0 FUNCTION

2

000I
0 0 1 LSB-justified; 16 bits
0 1 0 LSB-justified; 18 bits
0 1 1 LSB-justified; 20 bits
1 0 0 MSB-justified
1 0 1 MSB-justified output/LSB

1 1 0 MSB-justified output/LSB

1 1 1 MSB-justified output/LSB

S-bus

justified 16 bits input

justified 18 bits input

justified 20 bits input

s
s
s

UDA1344TS

DC filter

A 1-bit value to enable the digital DC-filter (see Table 16).

Table 16 DC-filtering

DC FUNCTION

0 no DC-filtering
1 DC-filtering

Volume control

A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in
steps of 1 dB (see Table 17).

Table 17 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
111011 −58
111100 −59
111101 −60
111110 −∞
111111 −∞

1998 Jul 28 13

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

Bass boost

A 4-bit value to program the bass boost setting. The used set depends on the mode bits.

Table 18 Bass boost settings

BB3 BB2 BB1 BB0

FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)

0000 0 0 0
0001 0 2 2
0010 0 4 4
0011 0 6 6
0100 0 8 8
0101 0 10 10
0110 0 12 12
0111 0 14 14
1000 0 16 16
1001 0 18 18
1010 0 18 20
1011 0 18 22
1100 0 18 24
1101 0 18 24
1110 0 18 24
1111 0 18 24

BASS BOOST

Treble

A 2-bit value to program the treble setting. The used set depends on the mode bits.

Table 19 Treble settings

TR1 TR0

FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)

00000
01022
10044
11066

TREBLE

1998 Jul 28 14

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

De-emphasis

A 2-bit value to enable the digital de-emphasis filter.

Table 20 De-emphasis settings

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis; 32 kHz
1 0 de-emphasis; 44.1 kHz
1 1 de-emphasis; 48 kHz

Mute

A 1-bit value to enable the digital mute.

Table 21 Mute

MT FUNCTION

0 no muting
1 muting

Mode

UDA1344TS

Table 22 The flat/min./max. switch

M1 M0 FUNCTION

0 0 flat
0 1 min.
1 0 min.
1 1 max.

Power control

A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.

Table 23 Power control settings

FUNCTION

PC1 PC0

ADC DAC

00offoff
0 1 off on
1 0 on off
1 1 on on

A 2-bit value to program the mode of the sound processing
filters of Bass Boost and Treble. There are three modes:
flat, min. and max.

1998 Jul 28 15

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). All voltages referenced to ground,
V

DDD=VDDA=VDDO

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

T

xtal(max)

T

stg

T

amb

V

es

Notes

1. All V

and VSS connections must be made to the same power supply.

DD

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

THERMAL CHARACTERISTICS

=3V; T

=25°C; unless otherwise specified.

amb

digital supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
operating ambient temperature −20 +85 °C
electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 90 K/W

DC CHARACTERISTICS

V

DDD=VDDA=VDDO

= 3.0 V; T

=25°C; RL=5kΩ; note 1; all voltages referenced to ground

amb

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDO

ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
operational amplifiers supply

2.7 3.0 3.6 V

voltage

V

DDD

I

DDA(ADC)

digital supply voltage 2.7 3.0 3.6 V
ADC supply current operation mode − 9.0 11.0 mA

ADC power-down − 3.5 5.0 mA

I

DDA(DAC)

DAC supply current operation mode − 4.0 6.0 mA

DAC power-down − 25 75 µA

I

DDO

operational amplifier supply current operation mode − 4.0 6.0 mA

DAC power-down − 250 300 µA

I

DDD

digital supply current operation mode − 6.0 9.0 mA

DAC power-down − 2.5 4.0 mA
ADC power-down − 3.5 5.0 mA

1998 Jul 28 16

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital input pins

V

IH

V

IL

I

 input leakage current −−10 µA

LI

C

i

HIGH-level input voltage 0.8V
LOW-level input voltage −0.5 − 0.2V

input capacitance −−10 pF

Three-level input pins (MP2; MP4)

V

IH

V

IM

V

IL

HIGH-level input voltage 0.9V
MIDDLE-level input voltage 0.4V
LOW-level input voltage −0.5 − 0.1V

Digital output pins

V

OH

V

OL

HIGH-level output voltage IOH= −2 mA 0.85V
LOW-level output voltage IOL=2mA −−0.4 V

Analog-to-digital converter

V
R
R
C

ref

o(ref)
i
i

reference voltage with respect to V
V

reference output resistance pin 4 − 24 − kΩ

ref(A)

SSA

0.45V

input resistance 1 kHz − 9.8 − kΩ
input capacitance − 20 − pF

Digital-to-analog converter

V

ref

R

o(ref)

R

o

I

o(max)

reference voltage with respect to V
V

reference output resistance pin 28 − 28 − kΩ

ref(D)

DAC output resistance − 0.13 3.0 Ω
maximum output current (THD + N)/S < 0.1%

0.45V

SSA

− 0.22 − mA

RL=5kΩ

R

L

C

L

load resistance 3 −− kΩ
load capacitance note 2 −−200 pF

Notes

1. All power supply pins (VDDand VSS) must be connected to the same external power supply unit.

2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output
in order to prevent oscillations in the output operational amplifier.

− V

DDD

− V

DDD

− 0.6V

DDD

−− V

DDD

0.5V

DDA

DDA

0.5V

DDA

DDA

DDD

DDD

0.55V

0.55V

+ 0.5 V

DDD

+ 0.5 V

DDD
DDD

DDA

DDA

V

V
V

V

V

1998 Jul 28 17

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA=VDDO

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital converter

V

i(rms)

∆V

i

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio V

α

cs

PSRR power supply rejection ratio f

Digital-to-analog converter

V

o(rms)

∆V

o

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio code = 0;

α

cs

PSRR power supply rejection ratio f

= 3.0 V; fi= 1 kHz; T

=25°C; RL=5kΩ all voltages referenced to ground

amb

input voltage (RMS value) − 1.0 − V
unbalance between channels − 0.1 − dB

at 0 dB −−85 −80 dB

noise-to-signal ratio

at −60 dB;

−−35 −30 dB

A-weighted

= 0 V; A-weighted − 95 − dB

i

channel separation − 100 − dB

ripple

V

ripple(p-p)

= 1 kHz;

=1%

− 30 − dB

output voltage (RMS value) − 900 − mV
unbalance between channels − 0.1 − dB

at 0 dB −−90 −85 dB

noise-to-signal ratio

at −60 dB;

−−37 − dB

A-weighted

− 100 − dB

A-weighted

channel separation − 80 − dB

ripple

V

ripple(p-p)

= 1 kHz;

=1%

− 50 − dB

1998 Jul 28 18

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA=VDDO

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing; see Fig.7

T

sys

t

CWL

t

CWH

Serial input/output data timing; see Fig.8
t

BCK

t

BCK(H)

t

BCK(L)

t

r

t

f

t

s;DATI

t

h;DATI

t

d(DATO)(BCK)

t

d(DATO)(WS)

t

h;DATO

t

s;WS

t

h;WS

Address and data transfer mode timing; see Figs 4 and 5
T

cy

t

HC

t

LC

t

s;MA

t

h;MA

t

s;MT

t

h;MT

= 2.7 to 3.6 V; T

clock cycle f

f

LOW level pulse width f

sys

f

HIGH level pulse width f

sys

bit clock period

= −20 to +85 °C; RL=5kΩ; all voltages referenced to ground

amb

= 256f
f
f

f

f

sys
sys
sys
sys
sys
sys
sys

s

= 384f

s

= 512f

s

< 19.2 MHz 0.30T

≥ 19.2 MHz 0.40T

< 19.2 MHz 0.30T

≥ 19.2 MHz 0.40T

78 88 262 ns
52 59 174 ns
39 44 132 ns

− 0.70T

sys

− 0.60T

sys

− 0.70T

sys

− 0.60T

sys

1

⁄64f

−−ns

s

sys
sys
sys
sys

bit clock HIGH time 100 −−ns
bit clock LOW time 100 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
data output delay time (from BCK falling

−−80 ns

edge)
data output delay time (from WS edge) MSB-justified

−−80 ns

format

data output hold time 0 −−ns
word selection set-up time 20 −−ns
word selection hold time 10 −−ns

L3CLOCK cycle time 500 −−ns
L3CLOCK HIGH period 250 −−ns
L3CLOCK LOW period 250 −−ns
L3MODE set-up time address mode 190 −−ns
L3MODE hold time address mode 190 −−ns
L3MODE set-up time data transfer

190 −−ns

mode

L3MODE hold time data transfer

190 −−ns

mode

ns
ns
ns
ns

1998 Jul 28 19

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

s;DAT

t

h;DAT

t

halt

handbook, full pagewidth

L3DATA set-up time data transfer

190 −−ns
mode and address
mode

L3DATA hold time data transfer

30 −−ns
mode and address
mode

L3MODE halt time 190 −−ns

t

CWH

t

T

sys

CWL

MGL443

handbook, full pagewidth

WS

BCK

DATAO

DATAI

t

r

t

BCK(H)

Fig.7 System clock timing.

t

h;DATO

d(DATO)(BCK)

t

s;DATI

t

h;DATI

MGG840

t

f

t

T

BCK(L)

cy

t

h;WS

t

d(DATO)(WS)

t

s;WS

t

Fig.8 Serial interface timing.

1998 Jul 28 20

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

APPLICATION INFORMATION

3 V

ground

system

clock

L1

8LM32A07

L2

8LM32A07

C12

100 µF

(16 V)

R30

47 Ω

C11

100 µF

(16 V)

V

DDA

V

DDD

SYSCLK

DATAO

BCK

DATAI

WS

12

18
16

17
19

100 µF

(16 V)

100 nF

(63 V)

V

SSA(ADC)

1

C2

C21

26711

handbook, full pagewidth

V

DDA

R21
1 Ω

R24

C25

100 nF

V

DDA(ADC)VADCNVADCPVSSD

(63 V)

C9

100 µF

(16 V)

C29

100 nF

(63 V)

V

DDD

R28
1 Ω

V

DDD

10

4

V

ref(A)

UDA1344TS

C22
100 nF
(63 V)

C3
47 µF
(16 V)

overload

flag

left

input

right

input

MP1

9

C1

X4

47 µF

(16 V)

C6

X5

47 µF

(16 V)

VINL

VINR

MP2
MP3
MP4

3

5

13
14
15

27

V

SSO

C26

100 nF
(63 V)

C7

100 µF

(16 V)

UDA1344TS

25

V

DDO

R25
1 Ω

V

DDO

22

V

SSA(DAC)

C27

100 nF

(63 V)

C10

100 µF

(16 V)

V

23

V

DDA(DAC)

R29
1 Ω

DDA

26

24

28

VOUTL

VOUTR

V

ref(D)

C5

47 µF

(16 V)

C8

47 µF

(16 V)

C23
100 nF
(63 V)

R22
10 kΩ

R27
10 kΩ

R23

100 Ω

R26

100 Ω

C4
47 µF
(16 V)

X2

X3

MGL444

left

output

right

output

Fig.9 Application diagram.

1998 Jul 28 21

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

D

c

y

Z

28 15

UDA1344TS

SOT341-1

E

H

E

A

X

v M

A

pin 1 index

114

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.0

0.21

0.05

1.80

1.65

2

A3b

0.25

0.38

0.25

p

cD

0.20

0.09

UNIT A1A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

p

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

10.0

eHELLpQZywv θ

5.4

0.65 1.25

5.2

7.9

7.6

Q

A

2

A

1

detail X

1.03

0.9

0.63

0.7

(A )

L

p

L

0.13 0.10.2

A

3

θ

1.1

0.7

o

8

o

0

OUTLINE

VERSION

SOT341-1 MO-150AH

IEC JEDEC EIAJ

REFERENCES

1998 Jul 28 22

EUROPEAN

PROJECTION

ISSUE DATE

93-09-08
95-02-04

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

UDA1344TS

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Jul 28 23

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio

UDA1344TS

CODEC with DSP features

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Jul 28 24

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1344TS

NOTES

1998 Jul 28 25

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1344TS

NOTES

1998 Jul 28 26

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1344TS

NOTES

1998 Jul 28 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
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220050 MINSK, Tel. [phone], Fax. [phone]

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Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

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72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
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Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545102/1200/01/pp28 Date of release: 1998 Jul 28 Document order number: 9397 750 03865