Datasheet UDA1343TT Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1343TT

Economy audio CODEC with
features

Product specification
Supersedes data of 2000 Jan 12
File under Integrated Circuits, IC01

2001 Jul 25

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

FEATURES
General

• Low power consumption

• 2.4 to 3.6 V power supply range, with 3 V typical

• 5 V tolerant TTL compatible digital inputs

• 256, 384 and 512fs system clock

• Supports sampling frequencies from 8 to 110 kHz

• Non-inverting ADC plus integrated high-pass filter to

cancel DC offset

• The ADC supports 2 V (RMS) input signals

• Stereo PGA with 0 to 24 dB gain in 3 dB steps

• Overload detector for easy record level control

• Separate power control for ADC + PGA and DAC

• Integrated digital interpolation filter plus non-inverting

DAC

• Functions controllable by L3 microcontroller interface

• Small package size (TSSOP28)

• ADC and DAC output polarity can be set.

Multiple format input interface

• I2S-bus, MSB-justified up to 24 bits and LSB-justified
16, 18, 20 and 24 bits format compatible

• Four combined data formats with MSB data output and
LSB 16, 18, 20 and 24 bits data input

• 1fs input and output format data rate.

• High linearity, dynamic range and low distortion

• Digital silence detector

• Digital mixer for mixing ADC signal and playback signal

• ADC volume controlin 0.25 dB steps and cosine roll-off

mute.

APPLICATIONS

• Portable equipment which includes audio functions

• Digital video camera.

GENERAL DESCRIPTION

The UDA1343TT is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with basic signal processing features employing bitstream
conversion techniques. The low power consumption, the
small package size and low voltage requirements make
the device eminently suitable for use in low-voltage
low-power portable digital audio equipment which
incorporates recording and playback functions.

DAC digital sound processing

• Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller in 0.25 dB steps

• Digital de-emphasis for 32, 44.1, 48 and 96 kHz

• Cosine roll-soft mute.

Advanced audio configuration

• Stereo single-ended input configuration

• Stereo line output (under microcontroller volume

control), no post filter required

ORDERING INFORMATION

TYPE

NUMBER

UDA1343TT TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1

2001 Jul 25 2

NAME DESCRIPTION VERSION

TheUDA1343TTis equipped with a digital mixer formixing
the ADC signal directly to the playback signal (forexample
for Karaoke applications). In the mixing mode the ADC
output signal can be output before or after the mixer.

The mixer can also be used as a selector to select
between the ADC or the digital data being played back at
the DAC.

PACKAGE

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDO(DAC)

I

DDD

T

amb

Analog-to-digital converter

V

i(rms)

(THD + N)/S totalharmonic distortion-plus-noise to

S/N signal-to-noise ratio V

α

cs

Digital-to-analog converter

V

o(rms)

(THD + N)/S totalharmonic distortion-plus-noise to

α

cs

S/N signal-to-noise ratio code = 0; A-weighted

ADC analog supply voltage 2.4 3.0 3.6 V
DAC analog supply voltage 2.4 3.0 3.6 V
digital supply voltage 2.4 3.0 3.6 V
ADC analog supply current operating mode − 10 − mA

ADC Power-down − 100 −µA

DAC analog supply current operating mode − 4 − mA

DAC Power-down − 50 −µA

DAC operational amplifier supply
current

operating mode − 2.5 − mA
DAC Power-down − 200 −µA

digital supply current operating mode − 5 − mA

ADC plus DAC

− 300 −µA

Power-down

ambient temperature −40 − +85 °C

input voltage (RMS value) notes 1, 2 and 3 − 1.0 − V

at 0 dB

signal ratio

f

= 44.1 kHz −−85 − dB

s

=96kHz −−81 − dB

f

s

at −60 dB; A-weighted

= 44.1 kHz −−37 − dB

f

s

=96kHz −−35 − dB

f

s

= 0 V; A-weighted

i

f

= 44.1 kHz − 97 − dB

s

=96kHz − 95 − dB

f

s

channel separation − 100 − dB

output voltage (RMS value) 860 900 940 mV

at 0 dB

signal ratio

= 44.1 kHz −−85 − dB

f

s

f

=96kHz −−80 − dB

s

at −60 dB; A-weighted

= 44.1 kHz −−37 − dB

f

s

f

=96kHz −−35 − dB

s

channel separation − 100 − dB

= 44.1 kHz − 100 − dB

f

s

f

=96kHz − 98 − dB

s

2001 Jul 25 3

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power performance

P

ADDA

P

DA

P

AD

P

PD

Notes

1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately

1 mA by using a series resistor.

2. The input voltage to the ADC scales proportionally with the power supply.

3. The performance figures and input voltage of the ADC are given with the PGA gain set to 0 dB.

power consumption in record and

− 64 − mW

playback mode
power consumption in playback mode − 36 − mW
power consumption in record mode − 46 − mW
power consumption in Power-down

− 2.0 − mW

mode

2001 Jul 25 4

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

BLOCK DIAGRAM

handbook, full pagewidth

VINL

V

DDD

V

SSD

DATAO

BCK

WS

DATAI

OVERFL

V

DDA(ADC)VSSA(ADC)

21

3 5

PGA PGA

10

11

18
16
17
19

9

DIGITAL INTERFACE

DE-EMPHASIS/VOLUME/MUTE

UDA1343TT

V

ADCP

ADC

DECIMATION FILTER

DC/VOLUME/MUTE

DIGITAL MIXER

INTERPOLATION FILTER

NOISE SHAPER

V

76 4

ADC

ADCN

V

L3-BUS

INTERFACE

DIGITAL

SILENCE

DETECTOR

ref(A)

21
20

13

14
15
12

8

VINR

TEST1
TEST2
RESET

L3MODE
L3CLOCK
L3DATA
SYSCLK

DAC

VOUTL

26

25 27 23 22

V

DDO

V

SSO

V

DDA(DAC)VSSA(DAC)

Fig.1 Block diagram.

2001 Jul 25 5

DAC

V

ref(D)

24

VOUTR

28

MGL886

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

PINNING

SYMBOL PIN TYPE DESCRIPTION

V

SSA(ADC)

V

DDA(ADC)

VINL 3 analog input pad ADC input left
V

ref(A)

VINR 5 analog input pad ADC input right
V

ADCN

V

ADCP

TEST1 8 5 V tolerant digital input pad with internal pull-down pad test pin 1
OVERFL 9 5 V tolerant slew-rate controlled digital output pad ADC overload output
V

DDD

V

SSD

SYSCLK 12 5 V tolerant digital Schmitt triggered input pad system clock input 256, 384 or 512f
L3MODE 13 digital input pad L3MODE input
L3CLOCK 14 5 V tolerant digital Schmitt triggered input pad L3CLOCK input
L3DATA 15 5 V tolerant digital Schmitt triggered input with pull-down,

BCK 16 5 V tolerant digital Schmitt triggered input pad bit clock input
WS 17 5 V tolerant digital Schmitt triggered input pad word select input
DATAO 18 5 V tolerant slew-rate controlled digital output pad data output
DATAI 19 5 V tolerant digital Schmitt triggered input pad data input
RESET 20 5 V tolerant digital Schmitt triggered input pad with

TEST2 21 5 V tolerant digital input pad with internal pull-down pad test pin 2
V

SSA(DAC)

V

DDA(DAC)

VOUTR 24 analog output pad DAC output right
V

DDO

VOUTL 26 analog output pad DAC output left
V

SSO

V

ref(D)

1 analog ground pad ADC analog ground
2 analog supply pad ADC analog supply voltage

4 analog pad ADC reference voltage

6 analog pad ADC negative reference voltage
7 analog pad ADC positive reference voltage

10 digital supply pad digital supply voltage
11 digital ground pad digital ground

L3DATA input

slew rate controlled output pad

reset input

internal pull-down

22 analog ground pad DAC analog ground
23 analog supply pad DAC analog supply voltage

25 analog supply pad operational amplifier supply voltage

27 analog ground pad operational amplifier ground
28 analog pad DAC reference voltage

s

2001 Jul 25 6

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Reset

handbook, halfpage

V

SSA(ADC)

V

DDA(ADC)

L3CLOCK

1
2

VINL

3

V

4

ref(A)

VINR

5
V
V

OVERFL

SYSCLK

L3MODE

ADCN
ADCP

TEST1

V

DDD

V

SSD

6

7

UDA1343TT

8

9

10
11
12
13

Fig.2 Pin configuration.

MGL887

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

V

ref(D)

V

SSO
VOUTL
V

DDO
VOUTR

V

DDA(DAC)
V

SSA(DAC)
TEST2

RESET
DATAI
DATAO
WS
BCK
L3DATA

Pin 20 is a reset pin (active HIGH), which resets the
internal digital core of the IC and also resets all feature
values of the L3 interface to their default settings as given
in Tables 8 and 9.

Since the RESET pin is a pull-down pad with
Schmitt-trigger, a Power-On Reset (POR) function can be
made by connecting this pinto the digital power supply via
a capacitor.

Note: care must be taken that during the HIGH period of
the reset signal it is best to have at least 8 SYSCLK clock
cycles to properly reset the device.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1343TT consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 64.

Analog front-end

The overall system gain is proportional to V

. The 0 dB

DDA

input level is defined as that which gives a −1dB
Full-Scale (FS) digital output (relative to the full-scale
swing).

FUNCTIONAL DESCRIPTION

The UDA1343TT accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock and the serial audio clock
signals.

Thesystemclock must be locked infrequencytothe digital
interface input signals.

The BCK clock can be up to 128fs, or in other words the
BCK frequency f
frequency fWS or less: f

is 128 times the Word Select (WS)

BCK

= < 128 × fWS.

BCK

Important: the WS edge MUST fall on the negative edge
of the BCK at all times for correct operation of the digital
I/O data interface.

Note: the sampling frequency range is from 8 to 110 kHz,
however for the 512f

clock mode the sampling range is

s

from 8 to 55 kHz.

The analog front-end is equipped with a Programmable
Gain Amplifier (PGA) which can be controlled via the L3
interface. The control range is from 0 dB to 24 dB gain in
3 dB steps independant for left and right.

In applications in which a 2 V (RMS) input signal is used,
a12kΩresistormust be connectedin series withthe input
of the ADC. This makes a voltage divider with the internal
ADC resistor andmakes sure only 1 V (RMS) maximumis
input to the IC. Using this application for a2 V (RMS) input
signal, the switch must be set to 0 dB. When a 1 V (RMS)
inputsignal is input totheADC in the sameapplication,the
gain switch of the PGA must be set to 6 dB via the L3
interface.

An overview of the maximum input voltages allowed
againstthe presence of an externalresistorand the setting
of the gain switch is given in Table 1.

2001 Jul 25 7

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Table 1 Application modes using input gain stage

RESISTOR

(12 kΩ)

PGA GAIN

MAXIMUM

INPUT

VOLTAGE

Present 0 dB 2V (RMS)
Present 6 dB 1V (RMS)
Absent 0 dB 1V (RMS)
Absent 6 dB 0.5 V (RMS)

Decimation filter (ADC)

Thedecimation from 64fsto1fsisperformed in twostages.
The first stage realizes a 4th-order characteristic.

sin x

----------- ­x

This filter decreases the sample rate by 16. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.

Table 2 Digital decimation filter characteristics

ITEM CONDITIONS VALUE (dB)

Pass-band ripple 0 − 0.45f
Stop band >0.55f
Dynamic range 0 − 0.45f
Overall gain with

DC −1.16

s

s

s

±0.05

−50

114

0 dB input to the
ADC

In the ADC path there is a volume control with a range of
0dBto−66 dB and −∞ dB in 0.25 dB steps, and a cosine
roll-off soft mute.

Table 3 Digital interpolation filter characteristics

ITEM CONDITIONS VALUE (dB)

Pass-band ripple 0 − 0.45f
Stop band >0.55f
Dynamic range 0 − 0.45f

s

s

s

±0.03

−65

116.5

Gain DC −3.5

Digital silence detector

The UDA1343 is equipped with a digital silence detector
on the digital data input. This detects whether a certain
amount of consecutive samples are 0. The status of the
digital silence detector can be read from the
microcontroller interface.

The number of samples can be set via the L3 interface to
3200, 4800, 9600 or 19600 samples.

The digital silence detection status can be read from the
microcontroller interface.

Mute

Muting the DAC will result in a cosine roll-off soft mute,
using32 × 4 = 128 samples (at 44.1 kHz thisis 3 ms). The
cosine roll-off curve is illustrated in Fig.3.

handbook, halfpage

1

mute

factor

0.8

MGS755

Note:thedigital output level is inversely proportional tothe
ADC analog power supply. This means that with a
constant analog input level and increasing analog power
supply, the digital output level will decrease proportionally.

Overload detection (ADC)

In practice the output is used to indicate whenever the
output data, ineither the left or rightchannel, is larger than

−1 dB (the actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output (pin 9) is forced HIGH for at least 512f

s

cycles (11.6 ms at fs= 44.1 kHz). This time-out is resetfor
each infringement.

Interpolation filter (DAC)

The digital filter interpolates from 1 to 128fsby means of a
cascade of a recursive filter and an FIR filter.

2001 Jul 25 8

0.6

0.4

0.2

0

01 3

2

t (ms)

Fig.3 Mute as a function of raised cosine roll-off.

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Double speed

SInce the device supports a sampling range of
8 to 110 kHz, the device can support double speed (e.g.
for 44.1 kHz and 48 kHz) by just doubling the system
speed. In double speed all features are available.

Digital mixer

The UDA1343TT has a digital mixer which can mix the
ADC signal to the playback signal. A functional block
diagram of the mixer mode is given in Fig.4.

When the device is in mixer mode, care is taken to avoid
clipping. This is done by reducing both signals by −6dB
before mixing. After mixing there is master volume and
mute, after which the signal is reamplified digitally by 6 dB.

handbook, full pagewidth

from ADC

and decimator

DIGITAL

DC FILTER

ADC volume + mute master volume + mute

VOLUME +

MUTE

−6 dB

The codec can be set to mixer mode via the L3 interface
by setting the MIX bit HIGH.

In the mixer mode there are 3 volume and mute controls
available; one for the ADC channel, one for the playback
channel and one for the master (equal sum) signal.
All three volume ranges can be controlled in 0.25 dB
steps.

In the mixer mode, the ADC volume control is used for
mixing purposes. The decimator output signal can be
output from the chip before the ADC volume control or
after the ADC volume control. This can be set via the L3
interface using the ADC output select bit.

+

VOLUME +

MUTE

+6 dB

to interpolator
and DAC

ADC_OUT

select (L3)

2

I

S-bus

output

−6 dB

VOLUME +

MUTE

I2S-bus

input

UDA1343TT

2

S-bus volume + mute

I

Fig.4 Mixing feature in the UDA1343TT.

MGL888

2001 Jul 25 9

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Digital output signal

The output to the digital output of the UDA1343TT can be
selected from 3 positions, using the two bits ADC_OUT
select in the L3 microcontroller interface. The 3 positions
are as follows:

• Directly from the ADC and decimator (default)

• After volume control and mute in the ADC data path

• After the digital mixer and before master volume control

and mute. It should be noted that this output is before
the +6 dB gain. This is done in order to prevent clipping
at the mixer output at all times.

Noise shaper (DAC)

The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier.

In this way very high signal-to-noise performance and low
clock jitter sensitivity is achieved. A post-filter is not
needed due to the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally
with the power supply voltage.

Multiple format input/output audio interface

The digital audio interface supports multiple standards:

• I2S-bus with data word length of up to 24 bits

• MSB-justifiedserial format with data wordlengthof up to

24 bits

• LSB-justified data formats with word lengths of 16, 18,
20 and 24 bits

• Four combined data formats with MSB data output
and 16, 18, 20 and 24 LSB data input.

The digital audio interface formats are illustrated in Fig.5.

2001 Jul 25 10

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2001 Jul 25 11

book, full pagewidth

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

LEFT

INPUT FORMAT I

LEFT

MSB-JUSTIFIED FORMAT

LEFT

LEFT

RIGHT

3

21> = 812 3

MSB MSBB2

2

S

RIGHT

>=8 >=8

MSB B2 B3 B4

321321

16

15 2 1

MSB

B2

16

1518 17 2 1

> = 8

B15

LSB

LSB JUSTIFIED FORMAT 16 BITS

B17

LSB

LSB JUSTIFIED FORMAT 18 BITS

RIGHT

RIGHT

16

MSB B2

16 1518 17 2 1

MSB B2 B3 B4

15 2 1

B15 LSB

B17 LSB

WS

BCK

DATA

WS

BCK

DATA

MSB

LEFT

16

1518 1720 19 2 1

B19

B23

LSB

LSB

MSB

B2

B3 B4

MSB B2 B3 B4 B5 B6

LSB JUSTIFIED FORMAT 20 BITS

LEFT

16

1518 1720 1922 2124 23 2 1

B2

B3 B4

B5 B6 B7 B8 B9 B10

LSB JUSTIFIED FORMAT 24 BITS

RIGHT

16

MSB B2 B3 B4 B5 B6

RIGHT

16

B5 B6 B7 B8 B9 B10

1518 1720 19 2 1

B19 LSB

1518 1720 1922 2124 23 2 1

B23 LSB

MBK983

Fig.5 The digital audio interface formats.

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

L3 INTERFACE
Introduction

The UDA1343TT has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlledby the microcontroller. Thecontrollable features
are:

• System clock frequency

• Data input format

• Power control

• DC filtering

• De-emphasis

• Volume:mastervolume,I2S-busmixervolumeandADC

volume

• Mute: master mute, I2S-bus mute and ADC mute

• Mixer settings

• PGA gain settings

• Digital silence control settings

• Polarity settings of the ADC and the DAC.

Theexchange of dataand control information betweenthe
microcontroller and the UDA1343TT is accomplished
through a serial hardware interface comprising the
following pins:

• L3DATA: microcontroller interface data line

• L3MODE: microcontroller interface mode line

• L3CLOCK: microcontroller interface clock line.

Information transfer via the microcontroller bus is
organized LSB first, and in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished; address mode and data transfer mode
(see Fig 6).

Important: when the device is powered-up, at least one
L3CLOCK pulse must be sent to the L3 interface to
wake-up the interface prior to sending to the device. This
is only needed once after the device is powered-up.

Device addressing

Table 4 Selection of data transfer

DOM

BIT 1

As can be seen in Table 4, the DATA and STATUS read
and write actions are combined.

The device address consists of one byte, which is split up
into two parts:

• Bits 7 to 2 represent a 6-bit device address

• Bits 1 and 0 represent the type of data transfer

according to Table 4.

As can be seen in Table 4, there are two types of data
transfers, being DATA and STATUS which can be read
and written.

Register addressing

After sending the device address, including the flags (the
DOM bits) whether the information is read or written, one
byte is sent with the destination register address using
7 bits, and 1 bit which signals whether information will be
read or written. The fundamental timing for the data mode
is illustrated in Fig.7.

Basically there are 3 cases for register addressing:

1. Register addressing for L3 write: the first bit is at

2. Prepare read addressing: the first bit of the byte is at

3. The read action itself: in this case the device returns a

DOM

BIT 0

0 0 not used
0 1 not used
1 0 DATA and STATUS write or pre-read
1 1 DATA and STATUS read

logic 0 indicating a write action to the destination
register, and is followed by 7 register address bits.

logic 1, signalling data will be read from the register
indicated.

register address prior to sending data from that
register. When the first bit of the byte is at logic 0, the
register address is valid, if the first bit is at logic 1 the
register address is invalid.

TRANSFER

The device addressing mode is used to select a device for
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits.
The fundamental timing is illustrated in Fig.6.

Basically, 2 types of transfer can be defined; data transfer
to the device and data transfer from the device;
see Table 4.

2001 Jul 25 12

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Data write mode

For writing data to a device four bytes must be sent.
The data write mode is illustrated in Fig.8.

1. One byte with the device address including ‘01’ for
signalling write to the device.

2. One byte starting with a logic 0 for signalling write
followed by 7 bits indicating the destination address.

3. Two data bytes.

Notes:

1. Each time a new destination address needs to be
written, the device address must sent again.

2. When addressing the device for the first time after
power-up of the device, at least one L3 clock cycle
must be sent to enable the L3 interface.

Data read mode

For reading from the device, a prepare-read must first be
done. After the prepare-read, the device address is sent
again. The device then returns with the register address,
indicating whether the address was valid or not, and the
data of the register. This procedure is explained below,
and an example transmission is illustrated in Fig.9.

1. One byte with the device address including ‘01’ for
signalling write to the address.

2. Onebyte is sent withtheregister address which needs
to be read. This byte starts with a logic 1, which
indicated that there will be a read action from the
register.

3. One byte with the device address including ‘11’ is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller.

4. The device now writes the requested register address
to the bus, indicating whether the requested register
was valid or not (logic 0 means valid, logic 1 means
invalid).

5. The device writes the data from the requested register
to the bus (two bytes).

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h(L3)A

t

BIT 0

su(L3)A

t

su(L3)DA

t

CLK(L3)L

t

CLK(L3)H

Fig.6 Timing address mode.

2001 Jul 25 13

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

BIT 7

MGL723

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

L3DATA

write

read

t

t

su(L3)D

t

en(L3)DA

stp(L3)

t

CLK(L3)L

T

t

h(L3)DA

BIT 0

t

CLK(L3)H

t

h(L3)R

t

su(L3)R

t

su(L3)DA

cy(CLK)L3

Fig.7 Data write and read mode timing.

t

h(L3)D

t

h(L3)DA

BIT 7

t

dis(L3)DA

t

stp(L3)

MGL889

2001 Jul 25 14

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2001 Jul 25 15

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

register address

data byte 1 data byte 2

MGS753

L3DATA

device address

0

10

DOM bits

write

Fig.8 Data write mode for L3 version 2.

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

L3CLOCK

L3MODE

L3DATA

device address

0

111

DOM bits

prepare read send by the device

register address register address

1

read

0/1

valid/non-valid

Fig.9 Data read mode for L3 version 2.

data byte 2 data byte 2

MGL890

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

L3 protocol

WARNING

Write followed by read
When issuing a read command following a write command, at least 8 µs delay must be inserted to allow the write to

take effect. No further restrictions apply to the order of L3 read and write commands.

Table 5 L3 data WRITE

MODE DATA

Addressing mode device address 0 1 1 1 1 0 0 0
Data transfer 1 register address 0 (write) A6 A5 A4 A3 A2 A1 A0
Data transfer 2 MS data byte D15 D14 D13 D12 D11 D10 D9 D8
Data transfer 3 LS data byte D7 D6 D5 D4 D3 D2 D1 D0

Table 6 L3 prepare READ DATA

MODE DATA

Addressing mode device address 0 1 1 1 1 0 0 0
Data transfer 1 register address 1 (read) A6 A5 A4 A3 A2 A1 A0

Table 7 L3 READ DATA

MODE DATA

Addressing mode device address 1 1 1 1 1 0 0 0
Data transfer 1 register address 0= valid

Data transfer 2 MS data byte D15 S14 D13 D12 D11 D10 D9 D8
Data transfer 3 LS data byte D7 D6 D5 D4 D3 D2 D1 D0

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

A6 A5 A4 A3 A2 A1 A0

1 = invalid

2001 Jul 25 16

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2001 Jul 25 17

L3 settings

L3 REGISTER MAPPING

Table 8 L3 register mapping including default register settings; bits D15 to D8

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

REG

NUM

Writeable and readable registers

00H system setting POLinv DAC POLinv ADC PON DAC SC1 SC0

11H MASTER volume

12H silence detector ADC_out

13H ADC volume VC-AD7 VC-AD6 VC-AD5 VC-AD4 VC-ADC3 VC-ADC2 VC-ADC1 VC-ADC0

14H mute MTM MT-ADC MT-IIS

20H ADC settings PON-R ADC PON-L ADC PON BIAS DCfilt1 DCfilt0

7FH software reset writing this sets all controllable settings to their default values

FUNCTION D15 D14 D13 D12 D11 D10 D9 D8

00001011

00000000

control

ADC_out

Select1

ADC output select 00000000

I2S-bus mixer
volume

de-emphasis 00000000

00000000

11100000

Select0

Readable registers

18H interpolator

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2001 Jul 25 18

Table 9 L3 register mapping including default register settings; bits D7 to D0

REG
NUM

Writable and readable registers

00H system setting SFOR3 SFOR2 SFOR1 SFOR0 MIX

FUNCTION D7 D6 D5 D4 D3 D2 D1 D0

010000 0

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

11H MASTER volume

control

12H silence detector SDET1 SDET0 SDET_on

ADC output select 00000001

13H ADC volume VC-IIS7 VC-IIS16 VC-IIS5 VC-IIS4 VC-IIS3 VC-IIS2 VC-IIS1 VC-IIS0

2

S-bus mixer volume 00000000

I

14H mute DE2 DE1 DE0

de-emphasis 00000000

20H ADC settings PGAL3 PGAL2 PGAL1 PGAL0 PGAR3 PGAR2 PGAR1 PGAR0

7FH software reset

Readable registers

18H interpolator SDET-IIS-R SDET-IIS-L MTM state MT-ADC

VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

00000000

00000000

MT-IIS state

state

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

POLARITY CONTROL OF THE DAC
A 1-bit value to program the DAC output polarity.

Table 10 Polarity control of the DAC

POLINV DAC FUNCTION

0 DAC output is not inverting
1 DAC output is inverting

POLARITY CONTROL OF THE ADC
A 1-bit value to program the ADC output polarity.

Table 11 Polarity control of the ADC

POLINV ADC FUNCTION

0 ADC output is not inverting
1 ADC output is inverting

POWER CONTROL OF THE DAC
A 1-bit value to program the power setting of the DAC.

Table 12 Power control of the DAC

PON DAC FUNCTION

0 DAC powered down
1 DAC powered up

SYSTEM CLOCK SETTINGS
A 2-bit value (SC1 and SC0) to select the required

external clock frequency (see Table 13).

Table 13 System clock frequency settings

SC1 SC0 FUNCTION

0 0 512f
0 1 384f
1 0 256f

s
s
s

11

DATA INPUT FORMAT
A 3-bit value (SFOR3 to SFOR0) to select the required

data format (see Table 14).

Table 14 : Data input format settings

SFOR3 SFOR2 SFOR1 SFOR0 FUNCTION

0000I

2

S-bus
0001LSB-justified; 16 bits
0010LSB-justified; 18 bits
0011LSB-justified; 20 bits
0100MSB-justified
0101MSB-justified output/LSB-justified 16 bits input
0110MSB-justified output/LSB-justified 18 bits input
0111MSB-justified output/LSB-justified 20 bits input
1000MSB justified output/ LSB-justified 24 bits input
1001LSB justified, 24 bits
1 : : : other codes are reserved for future use

IXER SETTING

M
A 1-bit value to enable or disable the digital mixer (for mixing the ADC signal to the playback signal).

Table 15 Mixer setting

MIX FUNCTION

0 mixer disabled
1 mixer enabled

2001 Jul 25 19

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

ADC OUTPUT SELECTOR
A 1-bit value to set the ADC I2S-bus output signal, being either before or after the mixer volume control and mute.

Table 16 ADC output select

ADC_OUT_SELECT1 ADC_OUT_SELECT0 FUNCTION

0 0 digital output before the ADC volume and mute
0 1 digital output after ADC volume control and mute
1 0 digital output after the mixer
1 1 not used

MASTER VOLUME CONTROL
An 8-bit valueto program the left andright channel master volume attenuation (VC5 to VC0). The range is 0 dB to −∞ dB

in steps of 0.25 dB (see Table 17).

Table 17 Master volume control: volume settings interpolator core

VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

00000000 0
00000100 0
00000101 −0.25
00000110 −0.5
00000111 −0.75
00001000 −1

:
11001100 −50
11010000 −52
11010100 −54
11011000 −57
11011100 −60
11100000 −66
11100100 -∞

11111111 -∞

SILENCE DETECTOR SAMPLES SETTING
A 2-bit value to set the number of samples for the digital

silence detector circuit.

SILENCE DETECTOR ENABLE SETTING
A 1-bit value to enable or disable the digital silence

detection signal.

Table 18 Silence detector settings

SDET1 SDET0 FUNCTION

0 0 3200 samples
0 1 4800 samples
1 0 9600 samples
1 1 19600 samples

2001 Jul 25 20

Table 19 Silence detector control setting

SDET_ON FUNCTION

0 silence detector disabled
1 silence detector enabled

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

ADC AND IIS MIXER VOLUME CONTROL
An 8-bit value to program the volume ADC attenuation. The range is 0 dB to −∞ dB in steps of 0.25 dB (see Table 20).

Table 20 Mixer volume settings.

VC-AD7

VC-IIS7

000000000
000001000
00000101−0.25
00000110−0.5
00000111−0.75
00000100−1

10110100−44
10111000−46
10111100−48
11000000−51
11000100−54
11001000−60
11001100−∞

11111111−∞

MASTER MUTE CONTROL

VC-AD6

VC-IIS6

VC-AD5

VC-IIS5

VC-AD4

VC-IIS4

VC-AD3

VC-IIS3

Table 22 Mixer mute

VC-AD2

VC-IIS2

VC-AD1

VC-IIS1

VC-AD0

VC-IIS0

VOLUME

(dB)

:

A 1-bit value to enable the digital master mute. This mute
control signal mutes the master playback signal after
mixing.

Table 21 Master mute

MTM FUNCTION

0 no muting
1 muting

MIXER MUTE CONTROL
Two 1-bit values to enable the digital mutes of the mixer.

These signals can be used to independently mute the
I2S-bus playback signal or the signal coming from the
ADC. These mute functions can only be used in the mixer
mode when the MIX bit is set HIGH.

The MT-ADC and MT-IIS bits can also be used to select
either the I2S-bus or the ADC signal for playback.

2001 Jul 25 21

MT-ADC/MT-IIS FUNCTION

0 no muting
1 muting

DIGITAL DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.

Table 23 De-emphasis settings

DE2 DE1 DE0 FUNCTION

0 0 0 no de-emphasis
0 0 1 de-emphasis; 32 kHz
0 1 0 de-emphasis; 44.1 kHz
0 1 1 de-emphasis; 48 kHz
1 0 0 de-emphasis; 96 kHz
1 0 1 not used
110
111

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

DC FILTER
A 1-bit value to enable the digital DC filter (see Table 24).

Table 24 DC filtering; note 1

DC1 DC0 FUNCTION

0 0 no DC filtering
0 1 DC filtering with −3 dB at 3 Hz
1 0 DC filtering with −3 dB at 100 Hz
1 1 DC filtering with −3 dB at 200 Hz

Note

1. The corner frequencies of the DC filter are given assuming 44.1 kHz sampling frequency.

ADC POWER CONTROL
Three 1-bit value to disable the ADC to reduce power consumption.

Table 25 Power control settings

PON BIAS PON-R ADC PON-L ADC FUNCTION

0 x x both ADC channels off and also bias block turned off
1 0 1 ADC left channel powered on, bias block turned on
1 1 0 ADC right channel powered on, bias block turned on
1 1 1 both left and right ADC channels enabled, bias block turned on

PGA GAIN SETTINGS
Two 4-bit values to program the PGA gain settings. The PGA settings can be set individually for the left and the right

channels.

Table 26 PGA gain control settings

PGAL3, PGAR3 PGAL2, PGAR2 PGAL1, PGAR1 PGAL0, PGAR0 FUNCTION

00000dB gain
00013dB gain
00106dB gain
00119dB gain
010012dB gain
010115dB gain
011018dB gain
011121dB gain
100024dB gain
1 : : : not used

2001 Jul 25 22

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

L3 readable registers

The L3 interface also contains some read-only registers in which system status can be read. The read-only registers are
given in Table 27. It should be noted that all bits mentioned in the table are active HIGH.

Table 27 Description of the bits from the READ ONLY registers

NAME FUNCTION

2

SDET-IIS-L signals whether the output data of the I
SDET-IIS-R signals whether the output data of the I
MTM_state signals whether there is master mute
MT-ADC_state signals whether there is mute in the ADC channel
MT-IIS_state signals whether there is mute in the I

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to ground;
V

DDD=VDDA=VDDO

=3V; T

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

T

xtal(max)

T

stg

T

amb

V

es

I

lu(prot)

I

sc(DAC)

digital supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage human body model; note 2 V

latch-up protection current T
DAC short-circuit current T

S-bus left channel is digitally zero

2

S-bus right channel is digitally zero

2

S-bus input channel

machine model; note 2 V

= 125 °C; VDD= 3.6 V − 200 mA

amb

=0°C; VDD=3V;

amb

note 3

output short-circuited to
V

SSA(DAC)

output short-circuited to
V

DDA(DAC)

− 450 mA

− 325 mA

Notes

1. All V

and VSS connections must be made to the same power supply.

DD

2. According to JEDEC II specification.

3. DAC operation after short-circuiting cannot be guaranteed.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 110 K/W

2001 Jul 25 23

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

DC CHARACTERISTICS

V

DDD=VDDA=VDDO

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDO(DAC)

I

DDD

Digital input pins (5 V tolerant TTL compatible)

V

IH

V

IL

V

IH(th)

V

IL(th)

V

hys

I

 input leakage current −−10 µA

LI

C

i

V

IL

Digital output pins

V

OH

V

OL

Analog-to-digital converter

V

ref(A)

R

o(refA)

R

i

C

i

Digital-to-analog converter

V

ref(D)

R

o(refD)

R

o

= 3.0 V; T

=25°C; RL=5kΩ; note 1; all voltages referenced to ground; unless otherwise

amb

ADC analog supply voltage 2.4 3.0 3.6 V
DAC analog supply voltage 2.4 3.0 3.6 V
digital supply voltage 2.4 3.0 3.6 V
ADC analog supply current operating mode − 10 − mA

ADC Power-down − 100 −µA

DAC analog supply current operating mode − 4 - mA

DAC Power-down − 50 −µA

DAC operational amplifier supply
current

operating mode − 2.5 − mA
DAC Power-down − 200 −

digital supply current operating mode − 5 − mA

ADC and DAC

− 300 −µA

Power-down

HIGH-level input voltage 2.0 − 5.0 V
LOW-level input voltage −0.5 − 0.8 V
HIGH-level threshold input voltage 1.3 − 1.9 V
LOW-level threshold input voltage 0.9 − 1.35 V
Schmitt trigger hysteresis 0.4 − 0.7 V

input capacitance −−10 pF
LOW-level input voltage −0.5 − 0.2V

HIGH-level output voltage IOH= −2 mA 0.85V

−−V

DDD

DDD

V

LOW-level output voltage IOL=2mA −−0.4 V

reference voltage referenced to

V

SSA(ADC)

V

reference output resistance − 24 − kΩ

ref(A)

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

input resistance fi= 1 kHz − 9.8 − kΩ
input capacitance − 20 − pF

reference voltage referenced to

V

SSA(DAC)

V

reference output resistance − 28 − kΩ

ref(D)

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

DAC output resistance − 0.13 3.0 Ω

2001 Jul 25 24

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

o(max)

R

L

C

L

Notes

1. All power supply pins (VDDand VSS) must be connected to the same external power supply unit.

2. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in
order to prevent oscillations in the output operational amplifier.

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA=VDDO

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

maximum output current (THD + N)/S < 0.1%;

− 3.5 − mA

RL= 800 Ω
load resistance 3 −−kΩ
load capacitance note 2 −−200 pF

= 3.0 V; fi= 1 kHz; fs= 44.1 kHz; T

=25°C; RL=5kΩ; all voltages referenced to ground;

amb

Analog-to-digital converter

V

i(rms)

∆V

i

(THD + N)/S total harmonic

input voltage (RMS value) note 1 − 1.0 − V
unbalance between channels − 0.1 − dB

at 0 dB

distortion-plus-noise to signal ratio

fs= 44.1 kHz −−85 − dB
fs= 96 kHz −−83 − dB

at −60 dB; A-weighted

fs= 44.1 kHz −−37 − dB
fs= 96 kHz −−35 − dB

S/N signal-to-noise ratio Vi= 0 V; A-weighted

fs= 44.1 kHz − 97 − dB
fs= 96 kHz − 95 − dB

α

cs

PSRR power supply rejection ratio f

channel separation − 100 − dB

= 1 kHz;

ripple

V

ripple(p-p)

=1%

Analog-to-digital converter using PGA

V

i(rms)

input voltage (RMS value)
resulting in −1 dB FS digital output

0 dB setting − 1000 − mV
3 dB setting − 708 − mV
6 dB setting − 500 − mV
9 dB setting − 354 − mV
12 dB setting − 250 − mV
15 dB setting − 178 − mV
18 dB setting − 126 − mV
21 dB setting − 89 − mV
24 dB setting − 63 − mV

− 30 − dB

2001 Jul 25 25

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

S/N signal-to-noise ratio Vi= 0 V; A-weighted;

Digital-to-analog converter

V

o(rms)

∆V

o

output voltage (RMS value) 860 900 940 mV
unbalance between channels − 0.1 − dB

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

α

cs

channel separation − 80 − dB

S/N signal-to-noise ratio code= 0; A-weighted

PSRR power supply rejection ratio f

Note

1. The performance figures and input voltage given are with the PGA gain set to 0 dB.

f

= 44.1 kHz; at 0 dB

s

0 dB setting −−85 − dB
3 dB setting −−85 − dB
6 dB setting −−85 − dB
9 dB setting −−85 − dB
12 dB setting −−83 − dB
15 dB setting −−83 − dB
18 dB setting −−82 − dB
21 dB setting −−81 − dB
24 dB setting −−81 − dB

fs= 44.1 kHz;
at −60 dB; A-weighted

0 dB setting −−37 − dB
3 dB setting −−37 − dB
6 dB setting −−37 − dB
9 dB setting −−35 − dB
12 dB setting −−34 − dB
15 dB setting −−33 − dB
18 dB setting −−31 − dB
21 dB setting −−29 − dB
24 dB setting −−27 − dB

− 97 − dB

at 44.1 kHz

at 0 dB

fs= 44.1 kHz −−87 − dB
fs= 96 kHz −−80 − dB

at −60 dB; A-weighted

fs= 44.1 kHz −−39 − dB
fs= 96 kHz −−37 − dB

fs= 44.1 kHz − 100 − dB
fs= 96 kHz − 98 − dB

ripple

V

ripple(p-p)

= 1 kHz;

=1%

− 60 − dB

2001 Jul 25 26

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA=VDDO

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing; see Fig.10

T

sys

t

CWL

t

CWH

t

r

t

f

Serial input/output data timing; see Fig.11
t

BCK

t

BCKH

t

BCKL

t

r

t

f

t

s(DATAI)

t

h(DATAI)

t

d(DATAO-BCK)

t

d(DATAO-WS)

t

h(DATAO)

t

s(WS)

t

h(WS)

Address and data transfer mode timing; see Fig 6
T

cy(CLK)(L3)

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

h(L3)A

t

su(L3)DA

t

h(L3)DA

t

su(L3)DAA

t

h(L3)DAA

t

halt

= 2.7 to 3.6 V; T

system clock cycle f

f

LOW level pulse width f

sys

f

HIGH level pulse width f

sys

= −40 to +85 °C; RL=5kΩ; all voltages referenced to ground; unless

amb

= 256fs, note 1 36 88 488 ns

sys

f

= 384fs, note 1 24 59 325 ns

sys

f

= 512fs, note 2 36 44 244 ns

sys

< 19.2 MHz 0.30T

sys

f

≥ 19.2 MHz 0.40T

sys

< 19.2 MHz 0.30T

sys

≥ 19.2 MHz 0.40T

f

sys

− 0.70T

sys

− 0.60T

sys

− 0.70T

sys

− 0.60T

sys

sys
sys
sys
sys

ns
ns
ns

ns
rise time −−20 ns
fall time −−20 ns

bit clock period

1

⁄

128fs

−−ns
bit clock HIGH time 30 −−ns
bit clock LOW time 30 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
data output delay time

−−80 ns

(from BCK falling edge)
data output delay time (from WS edge) MSB-justified format −−80 ns
data output hold time 0 −−ns
word select set-up time 20 −−ns
word select hold time 10 −−ns

L3CLOCK cycle time 500 −−ns
L3CLOCK HIGH period 250 −−ns
L3CLOCK LOW period 250 −−ns
L3MODE set-up time address mode 190 −−ns
L3MODE hold time address mode 190 −−ns
L3MODE set-up time data transfer mode 190 −−ns
L3MODE hold time data transfer mode 190 −−ns
L3DATA set-up time data transfer mode

190 −−ns

and address mode

L3DATA hold time data transfer mode

30 −−ns

and address mode

L3MODE halt time 190 −−ns

2001 Jul 25 27

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Notes to the AC characteristics (Digital)

1. Sampling range from 16 to 100 kHz is supported, with fs= 44.1 kHz typical.

2. Sampling range from 16 to 55 kHz is supported, with fs= 44.1 kHz typical.

handbook, full pagewidth

handbook, full pagewidth

WS

BCK

t

CWH

t

CWL

T

sys

MGR984

Fig.10 System clock timing.

t

BCKH

t

r

t

f

t

h(WS)

t

s(WS)

t

d(DATAO-BCK)

t

BCKL

t

d(DATAO-WS)

DATAO

DATAI

T

cy

Fig.11 Serial interface timing.

2001 Jul 25 28

t

h(DATAO)

t

s(DATAI)

t

h(DATAI)

MGL885

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

APPLICATION INFORMATION

The application information as given in Fig.12, is an optimum application environment. Simplification is possible at the
cost of some performance degradation. The following notes apply:

• The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter
also changes.

• The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the
capacitor with the 12 kΩ input resistance of the ADC will also change.

handbook, full pagewidth

3 V

ground

system

clock

overload

flag

left

input

right

input

8LM32A07

8LM32A07

X4

X5

L1

L2

C1

47 µF

(16 V)

C6

47 µF

(16 V)

C12

100 µF

(16 V)

R30

47 Ω

V

DDD

C11

100 µF

(16 V)

100 nF

V

DDA

V

DDD

SYSCLK

DATAO

BCK

WS

DATAI

OVERFL

VINL

VINR

RESET

L3MODE

L3CLOCK

L3DATA

12

18
16

17
19

9

3

5

20

13
14
15

100 µF

(16 V)

100 nF

(63 V)

V

SSA(ADC)

1

V

DDA

R21

C2

C21

1 Ω

R24

C25

100 nF

V

DDA(ADC)VADCNVADCP

26711

(63 V)

UDA1343TT

27

V

SSO

C26

100 nF

(63 V)

C7

100 µF

(16 V)

V

25

DDO

V

R25
1 Ω

DDO

22

V

SSA(DAC)

C27

100 nF

(63 V)

C10

100 µF

(16 V)

V

V

23

DDA

SSD

V

DDD

10

V

DDA(DAC)

R29
1 Ω

R28
1 Ω

V

DDD

V

ref(A)

4

VOUTL

26

VOUTR

24

V

ref(D)

28

C5

47 µF
(16 V)

C8

47 µF
(16 V)

C22
100 nF
(63 V)

C23
100 nF
(63 V)

R22
10 kΩ

R27
10 kΩ

C3
47 µF
(16 V)

R23

100 Ω

R26

100 Ω

C4
47 µF
(16 V)

X2

X3

MGL891

left

output

right

output

Fig.12 Application diagram.

2001 Jul 25 29

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

PACKAGE OUTLINE

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

D

c

y

Z

28

pin 1 index

15

A

2

A

1

114

w M

b

e

p

E

H

E

L

L

detail X

A

X

v M

A

Q

(A )

3

A

θ

p

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.10

OUTLINE

VERSION

SOT361-1 MO-153

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

b

3

p

0.30

0.19

(1)E(2) (1)

cD

0.2

9.8

4.5

0.1

9.6

REFERENCES

4.3

0.65

2001 Jul 25 30

eHELLpQZywv θ

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21.0

0.8

0.5

ISSUE DATE

95-02-04
99-12-27

o

8

o

0

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very brief insighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides, the footprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2001 Jul 25 31

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2001 Jul 25 32

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

Objective data Development This data sheet contains data from the objective specification for product

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Product data Production This data sheet contains data from the product specification. Philips

(1)

STATUS

(2)

DEFINITIONS

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any otherconditionsabovethose given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythat such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorselling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of these products, conveys nolicenceortitle
under any patent, copyright, or mask work right to these
products,and makes no representations orwarrantiesthat
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2001 Jul 25 33

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

NOTES

2001 Jul 25 34

Philips Semiconductors Product specification

Economy audio CODEC with features UDA1343TT

NOTES

2001 Jul 25 35

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,

Tel: [phone], Fax: [phone]
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips DevelopmentCorporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2001

Internet: http://www.semiconductors.philips.com

72

Printed in The Netherlands 753503/02/pp36 Date of release: 2001 Jul 25 Document order number: 9397750 07922