Datasheet UDA1342TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1342TS

Audio CODEC

Product specification
Supersedes data of 2000 Mar 29
File under Integrated Circuits, IC01

2000 Jul 31

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 ADC analog front-end

8.2.1 Application with 2 V (RMS) input

8.2.2 Double differential mode

8.3 Decimation filter (ADC)

8.4 Digital mixer (ADC)

8.5 Interpolation filter (DAC)

8.6 Mute

8.7 Digital mixer (DAC)

8.8 Noise shaper

8.9 Filter stream DAC

8.10 Digital interface

8.11 Sampling speed

8.12 Power-on reset

8.13 Control modes

8.14 Static pin mode

8.14.1 System clock setting select

8.14.2 Digital interface format select

8.14.3 ADC input channel select

8.15 L3-bus interface

8.15.1 Introduction

8.15.2 Device addressing

8.15.3 Register addressing

8.15.4 Data write mode

8.15.5 Data read mode

8.16 I2C-bus interface

8.16.1 Addressing

8.16.2 Slave address

8.16.3 Register address

8.16.4 Write cycle

8.16.5 Read cycle
9 REGISTER MAPPING

9.1 Reset

9.2 Quick mode switch

9.3 Bypass mixer DC filter

9.4 DC filter

9.5 ADC mode

9.6 ADC polarity

9.7 System clock frequency

9.8 Data format

9.9 DAC power control

9.10 Input oversampling rate

9.11 DAC polarity

9.12 DAC mixing position switch

9.13 DAC mixer

9.14 Silence detection period

9.15 Multi purpose output

9.16 Mode

9.17 Bass boost

9.18 Treble

9.19 Silence detector switch

9.20 Mute

9.21 Quick mute mode

9.22 De-emphasis

9.23 ADC input amplifier gain

9.24 DAC volume control

9.25 DAC mixer volume control

9.26 ADC mixer gain control
10 LIMITING VALUES
11 HANDLING
12 QUALITY SPECIFICATION
13 THERMAL CHARACTERISTICS
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS
16 TIMING
17 APPLICATION INFORMATION
18 PACKAGE OUTLINE
19 SOLDERING

19.1 Introduction to soldering surface mount
packages

19.2 Reflow soldering

19.3 Wave soldering

19.4 Manual soldering

19.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

20 DATA SHEET STATUS
21 DEFINITIONS
22 DISCLAIMERS
23 PURCHASE OF PHILIPS I2C COMPONENTS

2000 Jul 31 2

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

1 FEATURES General

• 2.7 to 3.6 V power supply

• 5 V tolerant digital inputs

• High pin compatibility with UDA1341TS

• 24 bits data path

• Selectable control via L3-bus interface, I2C-bus

interface or static pin control; choice of 2 device
addresses in L3-bus and I2C-bus mode

• Supports sample frequencies from 16 to 110 kHz

• Separate power control for ADC and DAC

• ADC and Programmable Gain Amplifiers (PGA) plus

integrated high-pass filter to cancel DC offset

• Integrated digital filter plus DAC

• Digital silence detection

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application.

Multiple format data interface

• I2S-bus, MSB-justified and LSB-justified format
compatible

• 1fsto 4fs input and 1fsoutput format data rate.

DAC digital sound processing

• Separate digital logarithmic volume control for left and
right channels in L3-bus mode or I2C-bus mode

• Digital tone control, bass boost and treble in L3-bus
mode or I2C-bus mode

• Digital de-emphasis for sample frequencies of
32, 44.1, 48 and 96 kHz in L3-bus mode or I2C-bus
mode

• Soft or quick mute in L3-bus mode or I2C-bus mode

• Output signalpolarity control in L3-bus mode or I2C-bus

mode

• Digital mixer for ADC output signal and digital serial
input signal.

Advanced audio configuration

• 4 channel (2 × stereo) single-ended inputs with
programmable gain amplifiers and 2 channel
(1 × stereo) single-ended outputs configuration

• Output signal polarity control in L3-bus mode or I2C-bus
mode

• High linearity, wide dynamic range, low distortion

• Double differential input configuration for enhanced

ADC sound quality.

2 APPLICATIONS

• Eminently suitable for MiniDisc (MD) home andportable
applications.

3 GENERAL DESCRIPTION

The UDA1342TS is a single-chip 4 channel
analog-to-digital converter and 2 channel digital-to-analog
converter with signal processing features employing
bitstream conversion techniques. The low power
consumption and low voltage requirements make the
device eminently suitable foruse in low-voltagelow-power
portable digital audio equipment which incorporates
recording and playback functions.

The UDA1342TS supports the I2S-bus data format with
wordlengths of up to24 bits,the MSB-justified data format
with word lengths of up to 24 bits and the LSB-justified
serial data format with word lengths of 16, 20 and 24 bits.
The device also supports a combination of the
MSB-justified output format and the LSB-justified input
format.

2000 Jul 31 3

TheUDA1342TShasspecialsoundprocessingfeaturesin
the playback mode such as de-emphasis, volume, mute,
bass boost and treble, which can be controlled by the
microcontroller via the L3-bus or I2C-bus interface.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDD

T

amb

Analog-to-digital convertor

V

i(rms)

(THD+N)/S

(THD+N)/S

S/N

48

S/N

96

α

cs

ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
ADC analog supply current 1 ADC + 1 PGA enabled − 10.0 − mA

2 ADCs + 2 PGAs enabled − 20.0 − mA
all ADCs + all PGAs

− 200 −µA

power-down

DAC analog supply current operating − 6.0 − mA

DAC power-down − 250 −µA

digital supply current operating − 9.0 − mA

ADC power-down − 4.5 − mA
DAC power-down − 5.5 − mA

ambient temperature −40 − +85 °C

input voltage (RMS value) at 0 dB (FS) digital output − 0.9 − V
total harmonic distortion-plus-noise

48

to signal ratio at fs=48kHz

normal mode

at −1dB −−90 − dB
at −60 dB; A-weighted −−40 − dB

double differential

at −1dB −−93 − dB
at −60 dB; A-weighted −−41 − dB

total harmonic distortion-plus-noise

96

to signal ratio at fs=96kHz

normal mode

at −1dB −−84 − dB
at −60 dB; A-weighted −−39 − dB

signal-to-noise ratio at fs= 48 kHz normal mode;

− 100 − dB

Vi= 0 V; A-weighted
double differential mode;

V

= 0 V; A-weighted

i

signal-to-noise ratio at fs= 96 kHz normal mode;

− 101 − dB

− 99 − dB

Vi= 0 V; A-weighted

channel separation − 100 − dB

2000 Jul 31 4

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital-to-analog convertor

V

o(rms)

output voltage (RMS value) at 0 dB (FS) digital input;

note 1

(THD+N)/S

(THD+N)/S

S/N

48

S/N

96

α

cs

total harmonic distortion-plus-noise

48

to signal ratio at fs=48kHz
total harmonic distortion-plus-noise

96

to signal ratio at fs=96kHz

at 0 dB −−90 − dB
at −60 dB; A-weighted −−40 − dB
at 0 dB −−83 − dB

at −60 dB; A-weighted −−39 − dB
signal-to-noise ratio at fs= 48 kHz code = 0; A-weighted − 100 − dB
signal-to-noise ratio at fs= 96 kHz code = 0; A-weighted − 99 − dB
channel separation − 100 − dB

Note

1. The output voltage of the DAC is proportionally to the DAC power supply voltage.

− 0.9 − V

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1342TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

2000 Jul 31 5

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

6 BLOCK DIAGRAM

handbook, full pagewidth

VINL2

VINL1

DATAO

BCK

WS

DATAI

V

DDA(ADC)VSSA(ADC)

31

6 8

PGA

2 4

PGA

ADC

UDA1342TS

DC-CANCELLATION FILTER

18
16
17
19

V

ADC

DECIMATION FILTER

DIGITAL MIXER (ADC)

DIGITAL

INTERFACE

DIGITAL MIXER (DAC)

DSP FEATURES

INTERPOLATION FILTER

DDD

10 11

ADC

V

SSD

ADC

PGA

V

ADCPVADCN

75

PGA

L3-BUS/

2

I

C-BUS

INTERFACE

VINR2

VINR1

9

IPSEL

22

STATUS

23

QMUTE

13

L3MODE

14

L3CLOCK

15

L3DATA

21

STATIC

12

SYSCLK

NOISE SHAPER

DAC

VOUTL

26

V

25

DDA(DAC)

28

V

ref

Fig.1 Block diagram.

2000 Jul 31 6

DAC

V

SSA(DAC)

20

TEST1

24

VOUTR

27

MGT016

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

7 PINNING

SYMBOL PIN TYPE DESCRIPTION

V

SSA(ADC)

VINL1 2 analog input pad ADC input left 1
V

DDA(ADC)

VINR1 4 analog input pad ADC input right 1
V

ADCN

VINL2 6 analog input pad ADC input left 2
V

ADCP

VINR2 8 analog input pad ADC input right 2
IPSEL 9 5 V tolerant digital input pad channel select input: input left 1 and right 1 or

V

DDD

V

SSD

SYSCLK 12 5 V tolerant digital input pad system clock input: 256f
L3MODE 13 5 V tolerant digital input pad L3-bus mode input or mode selection input
L3CLOCK 14 5 V tolerant digital input pad L3-bus/I

L3DATA 15 5 V tolerant open drain input/output L3-bus/I

BCK 16 5 V tolerant digital input pad bit clock input
WS 17 5 V tolerant digital input pad word select input
DATAO 18 5 V tolerant 2 mA slew rate controlled digital

DATAI 19 5 V tolerant digital input pad data input
TEST1 20 5 V tolerant digital input pad test control input; to be connected to ground
STATIC 21 5 V tolerant digital input pad mode selection input: static pin control or

STATUS 22 5 V tolerant 2 mA slew rate controlled digital

QMUTE 23 5 V tolerant digital input pad quick mute input
VOUTR 24 analog output pad DAC output right
V

DDA(DAC)

VOUTL 26 analog output pad DAC output left
V

SSA(DAC)

V

ref

1 analog ground pad ADC analog ground

3 analog supply pad ADC analog supply voltage

5 analog pad ADC reference voltage N

7 analog pad ADC reference voltage P

input left 2 and right 2
10 digital supply pad digital supply voltage
11 digital ground pad digital ground

, 384fs, 512fs or 768f

s

2

C-bus clock input or clock selection

input

2

C-bus data input/output or format

selection input

data output

output

L3-bus/I

2

C-bus control

general purpose output

output

25 analog supply pad DAC analog supply voltage

27 analog ground pad DAC analog ground
28 analog pad reference voltage for ADC and DAC

s

2000 Jul 31 7

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.2 ADC analog front-end

handbook, halfpage

V

SSA(ADC)

VINL1

V

DDA(ADC)

VINR1

V

ADCN
VINL2

V

ADCP

VINR2

IPSEL
V

V

SYSCLK

L3MODE

L3CLOCK

DDD

SSD

1
2
3
4
5
6
7

UDA1342TS

8

9
10
11
12
13

MGT017

Fig.2 Pin configuration.

8 FUNCTIONAL DESCRIPTION

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

V

ref

V

SSA(DAC)
VOUTL
V

DDA(DAC)
VOUTR

QMUTE
STATUS
STATIC
TEST1
DATAI
DATAO
WS
BCK
L3DATA

The analog front-end of the UDA1342TS consists of two
stereo ADCs with a programmable gain stage (gain from
0 to 24 dB with 3 dB steps)which can be controlledvia the
L3-bus/I2C-bus interface.

8.2.1 APPLICATION WITH 2 V (RMS) INPUT
In applications in which a 2 V (RMS) input signal is used,

a15kΩresistor must be usedinserieswith the input of the
ADC(see Fig.3). This formsa voltage divider together with
the internal ADC resistor and ensures thatonly 1 V (RMS)
maximum is input to the IC. Using this application for a
2 V (RMS) input signal, the gain switch must be set to
0 dB. When a 1 V (RMS)input signal isinput to the ADC in
the same application, the gain switch must be set to 6 dB.

An overview of the maximum input voltages allowed
againstthe presence of an external resistorandthe setting
of the gain switch is given in Table 1.

Table 1 Application modes using input gain stage

RESISTOR

(15 kΩ)

PGA GAIN

MAXIMUM INPUT

VOLTAGE

Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)

8.1 System clock

The UDA1342TS operatesin slave mode only, this means
that in allapplications the system must providethe system
clock. The system clock frequency is selectable and
depends on the mode of operation:

• L3-bus/I2C-bus mode: 256fs, 384fs, 512fs or 768f

s

• Static pin mode: 256fs or 384fs.
Thesystemclock must be locked in frequencytothedigital

interface signals.

Remarks:

• The bit clock frequency f

can be up to 128fs, or in

BCK

other words the bit clock frequency is 128 times the
word select frequency fWS or less: f

BCK

≤ 128f

WS

• The WS edge MUST fall on the negative edge of the
BCK signal at all times for proper operation of the digital
interface

• The UDA1342TS operates with sample frequencies
from 16 to 110 kHz, howeverfor a system clock of 768f

s

the sampling frequency must be limited to 55 kHz.

2000 Jul 31 8

handbook, halfpage

input signal

2 V (RMS)

Fig.3 Schematic of ADC front-end.

15 kΩ

VINL1,
VINR1,
VINL2,
VINR2

10 kΩ

V

ref

gain = 0 dB

10 kΩ

2,
4,
6,
8

UDA1342TS

MGT018

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.2.2 DOUBLE DIFFERENTIAL MODE
Since the UDA1342TS is equipped with two stereo ADCs,

these two pairs of stereo ADCs can be used to convert a
single stereo signal to a signal with a higher performance
by using the ADCs in the double differential mode.

This mode and the input signals, being channel 1 or 2 as
input to the double differential configuration, can be
selected via the L3-bus/I2C-bus interface.

8.3 Decimation filter (ADC)

Thedecimation from 64fsto1fsisperformed in twostages.

4

xsin

The first stage realizes a characteristic with a



-----------



x

decimation factor of 8. The second stage consists of three
half-bandfilters, each decimating by a factorof 2.The filter
characteristics are shown in Table 2.

Table 2 Decimation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Pass-band droop 0.45f

s

Stop band >0.55f
Dynamic range 0 to 0.45f

s

s

s

±0.01

−0.2

−70

>135

8.6 Mute

Muting the DAC will result in a cosine roll-off soft mute,
using 32 × 32 = 1024 samples in the normal mode: this
results in 24 ms at f

= 44.1 kHz. The cosine roll-off curve

s

is illustrated in Fig.4.
This cosine roll-off functions are implemented in the DAC

data path before the digital mixer and before the master
mute (see Fig.5).

In the L3-bus and I2C-bus mode, the setting of the master
mute can be overruled always by pin QMUTE. This quick
mute uses the same cosine roll-off, but now for only
32 samples: this is 750 µs at fs= 44.1 kHz.

handbook, halfpage

1

mute

factor

0.8

0.6

0.4

MGU119

8.4 Digital mixer (ADC)

The two stereo ADC outputs are mixed with gain
coefficients from +24 to −63.5 dB to be set via the
microcontroller interface.

In front of the mixer there is a DC filter. In order to prevent
clipping, it is needed tofilter out the DC component before
mixing or amplifying the signals.

Themixing function canbe enabled via themicrocontroller
interface.

8.5 Interpolation filter (DAC)

The digital interpolation filter interpolates from 1f

to 64f

s

by means of a cascade of FIR filters. The filter
characteristics are shown in Table 3.

Table 3 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f

s

s

s

±0.025

−60

>135

0.2

0

01051525

20

t (ms)

Fig.4 Mute as a function of raised cosine roll-off.

8.7 Digital mixer (DAC)

TheADC output signal and the digitalinterfaceinput signal
can be mixed without an external DSP (see Fig.5).

This mixer can be controlled via the microcontroller

s

interface.
In order to prevent clipping when mixing two 0 dB signals,

thesignals are attenuated digitallyby−6 dB before mixing.
After mixing the signal is gained by 6 dB after the master
volume. This wayclipping at the digital mixeris prevented.
After the 6 dB gain, the signals can clip again, but this
clipping can be removed by decreasing the master
volume.

2000 Jul 31 9

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

from

decimation

filter

from

digital

interface

input

DE-EMPHASIS

VOLUME

AND

MUTE

VOLUME

AND

MUTE

+ +

Fig.5 Digital mixer (DAC).

8.8 Noise shaper

The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).

8.9 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

to

digital

interface

output

master

BASS BOOST

AND

TREBLE

VOLUME

AND

MUTE

MGT019

to

interpolation

filter

8.10 Digital interface

The UDA1342TS supports the following data input/output
formats for the various modes (see Fig.6).

L3-bus and I2C-bus mode:

• I2S-bus format with data word length of up to 24 bits

• MSB-justifiedserial format with data wordlengthofup to

24 bits

• LSB-justified serial format with data word lengths of
16, 20 or 24 bits

• MSB-justified data output and
LSB-justified 16, 20 and 24 bits data input.

Static pin mode:

• I2S-bus format with data word length of up to 24 bits

• MSB-justified data output and

LSB-justified 16, 20 and 24 bits data input.

The output voltage of the FSDAC is proportionally to the
power supply voltage.

2000 Jul 31 10

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 11

handbook, full pagewidth

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

LEFT

I

LEFT

MSB-JUSTIFIED FORMAT

LEFT

LEFT

MSB B2 B3 B4 B5 B6

RIGHT

3

21> = 812 3

MSB MSBB2

2

S-BUS FORMAT

RIGHT

> = 8 > = 8

321321

16

15 2 1

MSB

B2

16

1518 1720 19 2 1

> = 8

B15

LSB

LSB-JUSTIFIED FORMAT 16 BITS

B19

LSB

LSB-JUSTIFIED FORMAT 20 BITS

RIGHT

16

MSB B2

RIGHT

16

MSB B2 B3 B4 B5 B6

15 2 1

B15 LSB

1518 1720 19 2 1

B19 LSB

WS

BCK

DATA

MSB

LEFT

16

1518 1720 1922 212324 2 1

B23

B2

B3 B4

B5 B6 B7 B8 B9 B10

LSB-JUSTIFIED FORMAT 24 BITS

LSB

MSB

B2

B3 B4

RIGHT

16

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B23 LSB

MGT020

Fig.6 Serial interface input/output formats.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.11 Sampling speed

The UDA1342TS operates with sample frequencies from
16 to 110 kHz. This range holds for the CODEC as a
whole. The DAC part can be configured in the L3-bus and
I2C-bus mode toaccept 2 times and even 4 times the data
speed (e.g. fsis 96 or 192 kHz), but in these modes not all
of the features can be used.

Some examples of the input oversampling rate settings
are shown in Table 4.

Table 4 Examples of the input oversampling rate settings

SYSTEM

SYSTEM CLOCK

CLOCK

FREQUENCY

SETTING

12.288 MHz (256 × 48 kHz) 256f

22.5792 MHz (512 × 44.1 kHz) 512f
256f

s

s
s

SAMPLING

FREQUENCY

(kHz)

44.1 single speed all

88.2 single speed all

176.4 double speed only master volume and mute

33.8688 MHz (768 × 44.1 kHz) 768f
384f

s
s

44.1 single speed all

88.2 single speed all

176.4 double speed only master volume and mute

Important: in the double speed mode an input signal of
0 dB is allowed, but in the quad speed mode the input
signal must be limited to −6 dB to prevent the system from
clipping.

INPUT OVER-

SAMPLING

FEATURES SUPPORTED

RATE

48 single speed all
96 double speed only master volume and mute

192 quad speed no features

8.12 Power-on reset

The UDA1342TS has an internal Power-on reset circuit
(see Fig.7) which resets the test control block. All the
digital sound processing features and the system
controlling features are set to their default setting in the
L3-bus and I2C-bus mode.

The reset time (see Fig.8) is determined by an external
capacitorwhichis connected between pin V
The reset time should be at least 1 µs for V
When V

DDA(DAC)

again for V

is switched off, the device will be reset

< 0.75 V.

ref

andground.

ref

< 1.25 V.

ref

During the reset time the system clock should be running.

2000 Jul 31 12

handbook, halfpage

3.0 V

V

DDA(DAC)

V

C1 >
10 µF

ref

25

8 kΩ

RESET

28

CIRCUIT

8 kΩ

UDA1342TS

Fig.7 Power-on reset circuit.

MGU001

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

3.0

handbook, halfpage

V

DDD
(V)

1.5

8.13 Control modes

V

DDA(DAC)

(V)

V

(V)

1.25

0.75

ref

3.0

1.5

3.0

1.5

0

0

0

>1 µs

Fig.8 Power-on reset timing.

t

t

t

MGU002

Table 6 Pin function in the selected mode

The control mode can be set with pin STATIC and
pin L3MODE:

• Static pin mode

• I2C-bus mode

• L3-bus mode.

Table 5 Mode selection

PIN STATIC PIN L3MODE SELECTION

LOW − L3-bus mode

2

HIGH LOW I

C-bus mode

HIGH HIGH static pin mode

The pin functions in the various modes are summarized in
Table 6.

2000 Jul 31 13

FUNCTION

PIN NAME

L3-BUS

MODE

I2C-BUS

MODE

STATIC PIN

MODE

L3CLOCK L3CLOCK SCL clock select

L3MODE L3MODE LOW level HIGH level

L3DATA L3DATA SDA format select
QMUTE QMUTE QMUTE format select

IPSEL A0 A0 channel select

2

All features in the L3-bus and I

C-bus mode are explained

in Sections 8.15 and 8.16.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.14 Static pin mode

The controllable features in the static pin mode are:

• System clock frequency

• Data input and output format select

• ADC input channel select.

8.14.1 SYSTEM CLOCK SETTING SELECT
In the static pin mode pin L3CLOCK is used to select the

system clock setting.

Table 7 System clock setting

PIN

L3CLOCK

0 256f
1 384f

SYSTEM CLOCK SETTING

s
s

8.14.2 DIGITAL INTERFACE FORMAT SELECT
In the static pin mode the digital interface audio formats

can be selected via pins L3DATA and QMUTE. The
following interface formats can be selected (see Table 8):

• I2S-bus format with data word length of up to 24 bits

• MSB-justified output format and LSB-justified input

format with data word length of 16, 20 or 24 bits.

Table 8 Data format select in static pin mode

PIN

L3DATA

00I

PIN

QMUTE

INPUT/OUTPUT FORMAT

2

S

0 1 LSB-justified 16 bits input and

MSB-justified output

1 0 LSB-justified 20 bits input and

MSB-justified output

1 1 LSB-justified 24 bits input and

MSB-justified output

8.14.3 ADC INPUT CHANNEL SELECT
In the static pin mode pin IPSEL selects the ADC input

channel.

Table 9 ADC input channel select

PIN

IPSEL

CHANNEL SELECT

0 input channel 1 (pins VINL1 and VINR1)
1 input channel 2 (pins VINL2 and VINR2)

8.15 L3-bus interface

All digital processing features and system controlling
features of the UD1342TS can be controlled by a
microcontroller via the L3-bus interface.

The controllable features are:

• Reset

• System clock frequency

• Data input and output format

• Multi purpose output

• ADC features

– Operation mode control
– Polarity control
– Input amplifier gain control
– Mixer control
– DC filtering.

• DAC features
– Power control
– Polarity control
– Input data oversampling rate
– Mixer position selection
– Mixer control
– Silence detector
– De-emphasis
– Volume
– Flat/min./max. switch
– Bass boost
– Treble
– Mute
– Quick mute mode.

8.15.1 INTRODUCTION

Theexchange of data andcontrol information betweenthe
microcontroller and the UDA1342TS is accomplished
through a serial hardware interface comprising the
following pins:

• L3DATA: microcontroller interface data line

• L3MODE: microcontroller interface mode line

• L3CLOCK: microcontroller interface clock line.

The UDA1342TS acts as a slave receiver or a slave
transmitter. Therefore L3CLOCK and L3MODE lines
transfer only input data and the L3DATA line transfers
bidirectional data.

2000 Jul 31 14

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

Information transfer via the microcontroller bus is
organized LSB first and in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: address mode and data transfer mode.

Important:

• When the device is powered-up, at least one L3CLOCK
pulse must be sent to the L3-bus interface to wake-up
the interface prior to sending information to the device.
This is onlyneeded once after the device is powered-up.

• Inside the microcontroller there is a hand-shake
mechanism which handles properdata transfer fromthe
microcontroller clock to destination clock domains. This
means that when data is sent to the microcontroller
interface, the system clock must be running.

• TheL3-bus interface is designedin such a waythat data
is clocked into the device (write mode) on the positive
clock edge, while the devicestarts the output data (read
mode) on the negative clock edge. The microcontroller
must read the data from the device on the positive clock
edge to ensure the data is always stable.

8.15.2 DEVICE ADDRESSING

The device address mode is used to select a device for
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits. The
fundamental timing in the address mode is shown in
Fig.13.

The device address consists of one byte, which is split up
in two parts (see Table 10):

• Bits 0and 1 are calledData Operation Mode (DOM)bits
and represent the type of data transfer

• Bits 2 to 7 represent a 6-bit device address.

Table 10 L3-bus interface slave address

DOM DEVICE ADDRESS

LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB

W 1 IPSEL 01000

R/

The UDA1342TS can be set to different addresses
(00 1000 or 10 1000) by setting pin IPSEL to HIGH or
LOW level. In the event that the device receives a different
address, it will deselect its microcontroller interface logic.

Table 11 Selection of data transfer

DOM

BIT 0 BIT 1

0 0 not used
1 0 not used
0 1 data write or prepare read
1 1 data read

8.15.3 REGISTER ADDRESSING
After sending the device address, including the flags

(DOM bits) whether the information is read or written, the
data transfer mode isentered and onebyte is sent withthe
destination register address (see Table 12) using 7 bits,
and one bit which signals whether information will be read
or written.

Thefundamental timing forthe data transfer modeis given
in Fig.14.

Table 12 L3-bus register address

LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB

R/

WA6A5A4A3A2A1A0

Basically there are 3 cases for register addressing:

1. Register addressing for L3-bus write: the first bit is at
logic 0 indicating a write action to the destination
register,andisfollowedby7 bitsindicatingtheregister
address.

2. Prepare read addressing: the first bit of the byte is at
logic 1, signalling data will be read from the register
indicated.

3. Read action itself: in this case the device returns a
register address prior to sending data from that
register. When the first bit of the byte is at logic 0, the
registeraddresswas valid and if the firstbitisat logic 1
the register address was invalid.

Important:

1. Each time a new destination address needs to be
written, the device address must be sent again.

2. When addressing the device for the first time after
power-up of the device, at least one L3CLOCK cycle
must be given to enable the L3-bus interface.

TRANSFER

Basically, 2 types of data transfer can be defined: data
transfer to the device and data transfer from the device
(see Table 11).

2000 Jul 31 15

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.15.4 DATA WRITE MODE
The data write format is given in Table 13 and illustrated

in Fig.9.
When writing data to a device four bytes must be sent:

1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value,including ‘01’ for
signalling write to the device.

2. One byte starting with a logic 0 for signalling write
followed by 7 bits indicating the register address.

3. One byte which is the Most Significant Data (MSD)
byte 1.

4. One byte which is the Least Significant Data (LSD)
byte 2.

8.15.5 DATA READ MODE

The data write format is given in Table 14 and illustrated
in Fig.10.

Whenreadingfromthedevice, a prepare read must first be
done. After the prepare read, the device address is sent
again. The device then returns with the register address,
indicating whether the address was valid or not, and the
data of the register.

The data read mode is explained below:

1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value,including ‘01’ for
signalling write to the device.

2. Onebyte is sent with theregister address which needs
to be read. This byte starts with a logic 1, which
indicates that there will be a read action from the
register.

3. One byte withthe device address including ‘11’ is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller.

4. The device now writes the requested register address
on the L3-bus, indicating whether the requested
register was valid (logic 0) or invalid (logic 1).

5. The device writes data from the requested register to
the L3-bus with the MSD byte 1 first, followed by the
LSD byte 2.

Table 13 L3-bus format for data write

L3MODE DATA TYPE

Address device address 0 1 IPSEL 01000
Data transfer 1 register address 0 A6 A5 A4 A3 A2 A1 A0
Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8
Data transfer 3 LSD byte 2 D7 D6 D5 D4 D3 D2 D1 D0

Table 14 L3-bus format for prepare read and read data

L3MODE DATA TYPE

Prepare read

Address device address 0 1 IPSEL 01000
Data transfer 1 register address 1 A6 A5 A4 A3 A2 A1 A0

Read data

Address device address 1 1 IPSEL 01000
Data transfer 1 register address 0/1 A6 A5 A4 A3 A2 A1 A0
Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8
Data transfer 3 LSD byte 2 D7 D6 D5 D4 D3 D2 D1 D0

FIRST IN TIME LAST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LAST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2000 Jul 31 16

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 17

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

register address

data byte 1 data byte 2

MGS753

L3DATA

device address

0

10

DOM bits

write

Fig.9 Data write mode for L3-bus version 2.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

L3CLOCK

L3MODE

L3DATA

device address

0

111

DOM bits

prepare read send by the device

register address device address register address

1

read

0/1

valid/non-valid

Fig.10 Data read mode for L3-bus version 2.

data byte 1 data byte 2

MGS754

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

8.16 I2C-bus interface

Besides the L3-bus mode the UDA1342TS supports the
I2C-bus mode; all the features can be controlled by the
microcontroller with the same register addresses as used
in the L3-bus mode.

Theexchange of data andcontrol information betweenthe
microcontroller and the UDA1342TS in the I2C-bus mode
is accomplished through a serial hardware interface
comprising the following pins and signals:

• L3CLOCK: Serial Clock Line (SCL)

• L3DATA: Serial Data line (SDA).

The clock and data timing of the I2C-bus transfer is shown
in Fig.15.

8.16.1 ADDRESSING
Before any data is transmitted on the I2C-bus, the device

whichshouldrespond is addressed first. Theaddressingis
alwaysdonewith the first byte transmitted after the START
procedure (S).

8.16.2 SLAVE ADDRESS
The UDA1342TS acts as a slave receiver or a slave

transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is an input or output
signal (bidirectional line).

8.16.3 R

EGISTER ADDRESS

The UDA1342TS register address format is given in
Table 16.

2

Table 16 I

C-bus register address format

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

0A6A5A4A3A2A1A0

2

The register mapping of the I

C-bus and L3-bus interfaces

is the same (see Section 9).

The UDA1342TS slave address format is shown in
Table 15.

Table 15 I

2

C-bus slave address format

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

001101IPSEL R/

W

The slave address bit IPSEL corresponds to the hardware
address pin IPSEL which allows selecting the slave
address.

2000 Jul 31 18

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 19

8.16.4 WRITE CYCLE
The write cycle is used to write data from the microcontroller to the internal registers. The I2C-bus format for a write cycle is shown in Table 17.
The device and register addresses are one byte each, data is always two bytes (2-bytes data).
The format of the write cycle is as follows:

1. The microcontroller starts with a START condition S.

2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W = 0).

3. This is followed by an acknowledge (A) from the UDA1342TS.

4. The microcontroller then writes the register address (8 bits) where writing of the register content of the UDA1342TS must start.

5. The UDA1342TS acknowledges this register address.

6. The microcontroller sends 2-bytes data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where each
byte is acknowledged by the UDA1342TS.

7. After the last acknowledge the UDA1342TS frees the I2C-bus and the microcontroller can generate a STOP condition (P).

Table 17 Master transmitter writes to UDA1342TS registers

ACKNOWLEDGE FROM UDA1342TS

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

DEVICE

ADDRESS

S 0011 01X 0 A 0XXX XXXX A MSD1 A LSD1 A MSD2 A LSD2 A MSDn A LSDn A P

8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits

Note

1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted.

R/W

REGISTER

ADDRESS

DAT A

(1)

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 20

8.16.5 READ CYCLE

The read cycle is used to read data from the internal registers of the UDA1342TS to the microcontroller. The I2C-bus format for a read cycle is shown
in Table 18.

The format of the read cycle is as follows:

1. The microcontroller starts with a START condition S.

2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W = 0).

3. This is followed by an acknowledge (A) from the UDA1342TS.

4. The microcontroller then writes the register address where reading of the register content of the UDA1342TS must start.

5. The UDA1342TS acknowledges this register address.

6. Then the microcontroller generates a repeated START (Sr).

7. Again the device address 0011 01X is given, but this time followed by a read command (bit R/W = 1).

8. The UDA1342TS sends the two-byte data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where
each byte is acknowledged by the microcontroller (master).

9. The microcontroller stops this cycle by generating a negative acknowledge (NA).

10. The UDA1342TS then frees the I2C-bus and the microcontroller can generate a STOP condition (P).

Table 18 Master transmitter reads from UDA1342TS registers

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

ACKNOWLEDGE FROM UDA1342TS ACKNOWLEDGE FROM MASTER

DEVICE

ADDRESS

S 0011 01X 0 A 0XXX XXXX A Sr 0011 01X 1 A MSD1 A LSD1 A MSD2 A LSD2 A MSDn A LSDn NA P

8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits

Note

1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted.

R/W

REGISTER

ADDRESS

DEVICE

ADDRESS

R/WDATA

(1)

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 21

9 REGISTER MAPPING

The addresses of the control registers with default values at Power-on reset are shown in Table 19. Functions of the registers are shown in
Tables 20 to 45.

Table 19 Register map

ADDRESS FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00H system RST QS MDC DC AM2 AM1 AM0 PAD 0 SC1 SC0 IF2 IF1 IF0 DP PDA

− 001101000000010

01H sub system −−−−−−−−OS1 OS0 MPS MIX SD1 SD0 MP1 MP0

−−−−−−−−00000000
02H to 0FH reserved −−−−−−−−−−−−−−−−
10H DAC features M1 M0 BB3 BB2 BB1 BB0 TR1 TR0 SDS MTB MTA MT QM DE2 DE1 DE0

0000000000000000

11H DAC master volume VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0

0000000000000000

12H DAC mixer volume VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0

0000000000000000
13H to 1FH reserved −−−−−−−−−−−−−−−−
20H ADC input and mixer

gain channel 1

21H ADC input and mixer

gain channel 2

22H to 2FH reserved −−−−−−−−−−−−−−−−
30H evaluation 0 0 0 0000000000000
31H to FFH reserved −−−−−−−−−−−−−−−−

0 0 0 0 IA3 IA2 IA1 IA0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

0000000000000000

0 0 0 0 IB3 IB2 IB1 IB0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0

0000000000000000

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

9.1 Reset

A 1-bit value to initialize the L3-bus and I2C-bus registers
except the system register (00H) with default settings by
setting bit RST = 1.

Table 20 Reset bit

RST FUNCTION

0 no reset
1 reset registers to default

9.2 Quick mode switch

A 1-bit value toenable the quickmode change of theADC.
The soft mode change works only between modes if
bit AM2 = 1.

Table 21 Quick mode switch

QS FUNCTION

0 soft mode change
1 quick mode change

9.3 Bypass mixer DC filter

A 1-bit value todisable the DC filterof the ADC mixer. This
DC filter is in front of the mixer to prevent clipping inside
the mixer due to DC signals.

9.5 ADC mode

A 3-bit value to select the mode of the ADC.

Table 24 ADC mode

AM2 AM1 AM0 FUNCTION

0 0 0 ADC power-off
0 0 1 input 1 select (input 2 off)
0 1 0 input 2 select (input 1 off)
0 1 1 not used
1 0 0 channel swap and signal inversion
1 0 1 input 1 select (double differential

mode)

1 1 0 input 2 select (double differential

mode)

1 1 1 mixing mode

9.6 ADC polarity

A 1-bit value to control the ADC polarity.

Table 25 Polarity control of the ADC

PAD FUNCTION

0 non-inverting
1 inverting

Table 22 Mixer DC filtering

MDC FUNCTION

0 enable mixer DC filtering
1 disable mixer DC filtering

9.4 DC filter

A1-bit value to enable the DC filterofthe ADC output. This
DC filter is inside the decimation filter.

Table 23 DC-filtering

DC FUNCTION

0 disable output DC filtering
1 enable output DC filtering

9.7 System clock frequency

A 2-bit value to select the external clock frequency.

Table 26 System clock frequency settings

SC1 SC0 FUNCTION

0 0 256f
0 1 384f
1 0 512f
1 1 768f

s
s
s
s

2000 Jul 31 22

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

9.8 Data format

A 3-bit value to select the data format.

Table 27 Data format selection

IF2 IF1 IF0 FUNCTION

2

000I
0 0 1 LSB-justified16 bits
0 1 0 LSB-justified 20 bits
0 1 1 LSB-justified 24 bits
1 0 0 MSB-justified
1 0 1 LSB-justified 16 bits input and

1 1 0 LSB-justified 20 bits input and

1 1 1 LSB-justified 24 bits input and

9.9 DAC power control

A 1-bit value to disable the DAC to reduce power
consumption. The DAC power-off is not recommended
when the DAC outputs are DC loaded.

S-bus

MSB-justified output

MSB-justified output

MSB-justified output

9.11 DAC polarity

A 1-bit value to control the DAC polarity.

Table 29 Polarity control of DAC

PDA FUNCTION

0 non-inverting
1 inverting

9.12 DAC mixing position switch

A1-bit value to select the mixingpositionof the ADC signal
in the DAC.

Table 30 DAC mixing position switch

MPS FUNCTION

0 before sound features
1 after sound features

9.13 DAC mixer

A 1-bit value to enable the digital mixer of the DAC.

Table 31 DAC mixer

Table 28 DAC power control

DP FUNCTION

0 DAC power-off
1 DAC power-on

9.10 Input oversampling rate

A 2-bit value to select the oversampling rate of the input
signal (see Table 32). In the quad speed input rate, care
must be taken that the input signal is smaller than

−5.67 dB (FS).

Table 32 Input oversampling rate

OS1 OS0 MODE

0 0 single speed 16 to 110 kHz supported all digital filters and all features, including mixing

0 1 double speed 32 to 220 kHz not supported first digital filter is bypassed, only master volume

1 0 quad speed 64 to 440 kHz not supported no mixing nor any sound feature is supported
1 1 reserved −− −

SAMPLING

FREQUENCY

ADC DAC FEATURES

MIX FUNCTION

0 disable mixer
1 enable mixer

are available

and master mute features are available

2000 Jul 31 23

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

9.14 Silence detection period

A 2-bit value to define the silence period for the silence
detector.

Table 33 Silence detection period

SD1 SD0 FUNCTION

0 0 3200 samples
0 1 4800 samples
1 0 9600 samples
1 1 19200 samples

9.15 Multi purpose output

A 2-bit value to select the output signal on pin STATUS.

Table 34 Multi purpose output selection

MP1 MP0 FUNCTION

0 0 no output
0 1 overflow (ADC) detection
1 0 reserved
1 1 digital silence detection

Table 36 Bass boost settings

BASS BOOST (dB)

BB3 BB2 BB1 BB0

FLAT MIN. MAX.

0000000
0001022
0010044
0011066
0100088
010101010
011001212
011101414
100001616
100101818
101001820
101101822
110001824
110101824
111001824
111101824

9.16 Mode

A2-bit value to programthe mode of thesound processing
filters of bass boost and treble.

Table 35 Flat/min./max. switch position

M1 M0 FUNCTION

0 0 flat
0 1 min.
1 0 min.
1 1 max.

9.17 Bass boost

A 4-bit value to program the bass boost settings. The used
set depends on the setting of bits M1 and M0.
At fs= 44.1 kHz the −3 dB point for minimum setting is
250 Hzandthe−3 dBpointformaximum setting is 300 Hz.
The default value is 0000.

9.18 Treble

A 2-bit value to program the treble setting. The used set
dependson the setting ofbits M1 and M0. At fs= 44.1 kHz
the −3 dB point for minimum setting is 3.0 kHz and the

−3 dB point for maximum setting is 1.5 kHz. The default
value is 00.

Table 37 Treble settings

TREBLE (dB)

TR1 TR0

FLAT MIN. MAX.

00 0 0 0
01 0 2 2
10 0 4 4
11 0 6 6

2000 Jul 31 24

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

9.19 Silence detector switch

A 1-bit value to enable the silence detector.

Table 38 Silence detector switch

SDS FUNCTION

0 disable silence detector
1 enable silence detector

9.20 Mute

Three 1-bit values to enable the digital mute. Bit MT is the
master mute, using bit MTA the signal from the digital
interface can be soft muted when the DAC mixer is
enabled and using bit MTB the signal from ADC can be
soft muted.

Table 39 Mute

MT

MTA

FUNCTION

MTB

0 no muting
1 muting

9.23 ADC input amplifier gain

Two 4-bit values to program the gain of the input
amplifiers. Bits IA applies for input amplifier A and bits IB
to input amplifier B.

Table 42 ADC input amplifier gain settings

IA3
IB3

IA2
IB2

IA1
IB1

IA0
IB0

AMPLIFIER GAIN (dB)

0000 0
0001 3
0010 6
0011 9
0100 12
0101 15
0110 18
0111 21
1000 24

9.21 Quick mute mode

A 1-bit value to enable the quick mute function of the
master mute.

Table 40 Quick mute mode settings

QM FUNCTION

0 soft mute mode
1 quick mute mode

9.22 De-emphasis

A 3-bit value to enable the digital de-emphasis filter.

Table 41 De-emphasis settings

DE2 DE1 DE0 FUNCTION

0 0 0 no de-emphasis
0 0 1 de-emphasis at fs= 32 kHz
0 1 0 de-emphasis at f
0 1 1 de-emphasis at f
1 0 0 de-emphasis at f

= 44.1 kHz

s

= 48 kHz

s

= 96 kHz

s

2000 Jul 31 25

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

9.24 DAC volume control

Four 8-bit values to program the volume attenuations. The range is from 0 to −66 dB and −∞ dB in steps of 0.25 dB.
Bits VL and VR are master volumes for the left and right channels.

Table 43 DAC volume settings

VL7
VR7

00000000 0
00000001 −0.25
00000010 −0.50
00000011 −0.75
00000100 −1.00

:::::::: :
11000100 −49.0
11000101 −49.25
11000110 −49.5
11000111 −49.75
11001000 −50.0
11001100 −52.0
11010000 −54.0
11010100 −57.0
11011000 −60.0
11011100 −66.0
11100000 −∞

:::::::: :
11111111 −∞

VL6

VR6

VL5
VR5

VL4

VR4

VL3

VR3

VL2
VR2

VL1

VR1

VL0

VR0

VOLUME (dB)

9.25 DAC mixer volume control

Four 8-bit values to program the volume attenuations. The range is from 0 to −60 dB and −∞ dB in steps of 0.25 dB.
When the DAC mixer is enabled, the signal from the digital interface can be controlled by bits VA and the signal from the
ADC can be controlled by bits VB.

Table 44 DAC volume settings

VA7
VB7

00000000 0
00000001 −0.25
00000010 −0.50
00000011 −0.75
00000100 −1.00

:::::::: :
10101100 −43.0
10101101 −43.25

2000 Jul 31 26

VA6
VB6

VA5
VB5

VA4
VB4

VA3

VB3

VA2
VB2

VA1

VB1

VA0

VB0

VOLUME (dB)

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

VA7
VB7

10101110 −43.5
10101111 −43.75
10110000 −44.0
10110100 −46.0
10111000 −48.0
10111100 −51.0
11000000 −54.0
11000100 −60.0
11001000 −∞

:::::::: :
11111111 −∞

9.26 ADC mixer gain control

Two 8-bit values to program the channel 1 and 2 mixing, when the mixer mode is selected. Bits MA applies to channel 1
and bits MB to channel 2. The range is from +24 to −63.5 dB and −∞ dB in steps of 0.5 dB.

Table 45 ADC mixer gain settings

MA7
MB7

00110000 +24.0
00101111 +23.5
00101110 +23.0

:::::::: :
00000010 +1.0
00000001 +0.5
00000000 0
11111111 −0.5

:::::::: :
10000100 −62.0
10000011 −62.5
10000010 −63.0
10000001 −63.5
10000000 −∞

VA6
VB6

MA6
MB6

VA5
VB5

MA5
MB5

VA4
VB4

MA4
MB4

VA3

VB3

MA3
MB3

VA2
VB2

MA2
MB2

VA1

VB1

MA1
MB1

VA0

VB0

MA0
MB0

VOLUME (dB)

MIXER GAIN (dB)

2000 Jul 31 27

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

xtal(max)

T

stg

T

amb

V

es

I

lu(prot)

I

sc(DAC)

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.

4. DAC operation after short-circuiting cannot be warranted.

supply voltage note 1 − 4V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage note 2 −1100 +1100 V

note 3 −250 +250 V
latch-up protection current T
short-circuit current of DAC T

= 125 °C; VDD= 3.6 V - 200 mA

amb

=0°C; VDD= 3 V; note 4

amb

output short-circuited to V
output short-circuited to V

SSA(DAC)
DDA(DAC)

− 450 mA

− 325 mA

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

12 QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

.

13 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 90 K/W

14 DC CHARACTERISTICS

V

DDD=VDDA(ADC)=VDDA(DAC)

= 3.0 V; T

=25°C; RL=5kΩ; all voltages measured with respect to ground; unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies; note 1

V

DDA(ADC)

V

DDA(DAC)

V

DDD

ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V

2000 Jul 31 28

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DDA(ADC)

I

DDA(DAC)

I

DDD

Digital input pins (5 V tolerant TTL compatible)

V

IH

V

IL

I

 input leakage current −−1µA

LI

C

i

Digital output pins

V

OH

V

OL

Reference voltage

V

ref

R

o(Vref)

Analog-to-digital converter

V

ADCP

V

ADCN

R

i

C

i

Digital-to-analog converter

I

o(max)

R

L

C

L

Notes

1. All supply connections must be made to the same power supply unit.

2. V

3. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in
order to prevent oscillations in the output operational amplifier.

ADC analog supply current 1 ADC + 1 PGA enabled − 10 − mA

2 ADCs + 2 PGAs enabled − 20 − mA
all ADCs + all PGAs

− 200 −µA

power-down

DAC analog supply current operating − 6.0 − mA

DAC power-down − 250 −µA

digital supply current operating − 9.0 − mA

ADC power-down − 4.5 − mA
DAC power-down − 5.5 − mA

HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage −0.5 − +0.8 V

input capacitance −−10 pF

HIGH-level output voltage IOH= −2 mA 0.85V

−−V

DDD

LOW-level output voltage IOL=2mA −−0.4 V

reference voltage with respect to V

SSA(ADC)

;

0.45V

DDA

0.5V

DDA

0.55V

DDA

note 2

output resistance on pin V

positive reference voltage of

ref

− 5 − kΩ

− V

DDA(ADC)

− V

the ADC
negative reference voltage

− 0.0 − V

of the ADC
input resistance − 10 − kΩ
input capacitance − 24 − pF

maximum output current (THD + N)/S < 0.1% − 1.6 − mA
load resistance 3 −−kΩ
load capacitance note 3 −−50 pF

DDA=VDDA(DAC)=VDDA(ADC)

.

V

2000 Jul 31 29

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

15 AC CHARACTERISTICS

V

DDD=VDDA(ADC)=VDDA(DAC)

to ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital converter

V

i(rms)

input voltage
(RMS value)

∆V

i

unbalance between
channels

(THD + N)/S

total harmonic

48

distortion-plus-noise to
signal ratio at fs= 48 kHz

= 3.0 V; fi= 1 kHz at −1 dB; T

0 dB setting − 900 − mV
3 dB setting − 640 − mV
6 dB setting − 450 − mV
9 dB setting − 320 − mV
12 dB setting − 225 − mV
15 dB setting − 160 − mV
18 dB setting − 122.5 − mV
21 dB setting − 80 − mV
24 dB setting − 61.25 − mV

normal mode; at −1dB

0 dB setting −−90 − dB
3 dB setting −−90 − dB
6 dB setting −−90 − dB
9 dB setting −−90 − dB
12 dB setting −−89 − dB
15 dB setting −−89 − dB
18 dB setting −−88 − dB
21 dB setting −−87 − dB
24 dB setting −−85 − dB

normal mode; at −60 dB; A-weighted

0 dB setting −−40 − dB
3 dB setting −−37 − dB
6 dB setting −−36 − dB
9 dB setting −−35 − dB
12 dB setting −−33 − dB
15 dB setting −−31 − dB
18 dB setting −−30 − dB
21 dB setting −−28 − dB
24 dB setting −−26 − dB

double differential mode

at 0 dB gain −−93 − dB
at 0 dB gain; −60 dB input;

A-weighted

=25°C; RL=5kΩ; all voltages measured with respect

amb

− <0.1 − dB

−−41 − dB

2000 Jul 31 30

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(THD + N)/S96total harmonic

distortion-plus-noise to
signal ratio at fs= 96 kHz

S/N

48

signal-to-noise ratio at
fs= 48 kHz

S/N

96

signal-to-noise ratio at
fs= 96 kHz

α

cs

channel separation − 100 − dB

PSRR power supply rejection

ratio

Digital-to-analog converter

V

o(rms)

output voltage
(RMS value)

∆V

o

unbalance between
channels

(THD+N)/S

total harmonic

48

distortion-plus-noise to
signal ratio at fs= 48 kHz

(THD+N)/S

total harmonic

96

distortion-plus-noise to
signal ratio at fs= 96 kHz

S/N

48

signal-to-noise ratio at
fs= 48 kHz

S/N

96

signal-to-noise at
fs= 96 kHz

α

cs

channel separation − 100 − dB

PSRR power supply rejection

ratio

normal mode

at 0 dB gain −−84 − dB
at −60 dB; A-weighted −−39 − dB

Vi= 0 V; A-weighted

normal mode − 100 − dB
double differential mode − 101 − dB

Vi= 0 V; A-weighted; normal mode − 99 − dB

f

ripple

= 1 kHz; V

= 30 mV (p-p) − 30 − dB

ripple

at 0 dB (FS) digital input − 0.9 − V

− <0.1 − dB

at 0 dB −−90 − dB
at −60 dB; A-weighted −−40 − dB

at 0 dB −−83 − dB
at −60 dB; A-weighted −−39 − dB

code = 0; A-weighted − 100 − dB

code = 0; A-weighted − 99 − dB

f

ripple

= 1 kHz; V

= 30 mV (p-p) − 60 − dB

ripple

2000 Jul 31 31

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

16 TIMING

V

DDD=VDDA(ADC)=VDDA(DAC)

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing; note 1 (see Fig.11)

T

sys

t

CWL

t

CWH

system clock cycle time f

system clock LOW time f

system clock HIGH time f

Serial interface input/output data timing (see Fig.12)
f

BCK

T

cy(BCK)

t

BCKH

t

BCKL

t

r

t

f

t

su(WS)

t

h(WS)

t

su(DATAI)

t

h(DATAI)

t

h(DATAO)

t

d(DATAO-BCK)

t

d(DATAO-WS)

bit clock frequency −−128f
bit clock cycle time T

bit clock HIGH time 30 −− ns
bit clock LOW time 30 −− ns
rise time −−20 ns
fall time −−20 ns
word select set-up time 10 −− ns
word select hold time 10 −− ns
data input set-up time 10 −− ns
data input hold time 10 −− ns
data output hold time 0 −− ns
data output to bit clock delay −−30 ns

data output to word select delay −−30 ns
L3-bus interface timing (see Figs 13 and 14)
t

r

t

f

T

cy(CLK)L3

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

rise time note 2 −−10 ns/V

fall time note 2 −−10 ns/V

L3CLOCK cycle time note 3 500 −− ns

L3CLOCK HIGH time 250 −− ns

L3CLOCK LOW time 250 −− ns

L3MODE set-up time in address

mode
t

h(L3)A

L3MODE hold time in address

mode
t

su(L3)D

L3MODE set-up time in data

transfer mode
t

h(L3)D

L3MODE hold time in data

transfer mode

= 2.7 to 3.6 V; T

= −20 to +85 °C; all voltages referenced to ground; unless otherwise

amb

= 256f
f
f
f

f

f

sys
sys
sys
sys
sys
sys
sys
sys

cy(s)

s

= 384f

s

= 512f

s

= 768f

s

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

= sample

35 81 250 ns
23 54 170 ns
17 41 130 ns
17 27 90 ns

sys
sys
sys
sys

−−

− 0.7T

− 0.6T

− 0.7T

− 0.6T

1

⁄

128Tcy(s)

sys
sys
sys
sys

s

frequency cycle time

190 −− ns

190 −− ns

190 −− ns

190 −− ns

ns
ns
ns
ns

Hz
s

2000 Jul 31 32

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

stp(L3)

L3MODE stop time in data
transfer mode

t

su(L3)DA

L3DATA set-up time in address
and data transfer mode

t

h(L3)DA

L3DATA hold time in address and
data transfer mode

t

su(L3)R

t

h(L3)R

t

en(L3)R

t

dis(L3)R

2

C-bus interface timing (see Fig.15)

I

f

SCL

t

LOW

t

HIGH

t

r

t

f

t

HD;STA

t

SU;STA

t

SU;STO

t

BUF

L3DATA set-up time for read data 50 −− ns
L3DATA hold time for read data 360 −− ns
L3DATA enable time for read data 380 −− ns
L3DATA disable time for read data 50 −− ns

SCL clock frequency 0 − 400 kHz
SCL LOW time 1.3 −− µs
SCL HIGH time 0.6 −− µs
rise time SDA and SCL note 4 20 + 0.1Cb− 300 ns
fall time SDA and SCL note 4 20 + 0.1Cb− 300 ns
hold time START condition note 5 0.6 −− µs
set-up time repeated START 0.6 −− µs
set-up time STOP condition 0.6 −− µs
bus free time between a STOP

and START condition

t

SU;DAT

t

HD;DAT

t

SP

C

b

data set-up time 100 −− ns
data hold time 0 −− µs
pulse width of spikes note 6 0 − 50 ns
capacitive load for each bus line −−400 pF

Notes

1. The typical value of the timing is specified at 48 kHz sampling frequency.

2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
small as possible.

3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to1⁄

4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.

5. After this period, the first clock pulse is generated.

6. To be suppressed by the input filter.

190 −− ns

190 −− ns

30 −− ns

1.3 −− µs

cycle.

64fs

2000 Jul 31 33

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

handbook, full pagewidth

WS

BCK

t

CWH

t

CWL

T

sys

MGR984

Fig.11 Timing of system clock.

t

BCKH

t

r

T

cy(BCK)

t

f

t

BCKL

t

h(WS)

t

d(DATAO-WS)

t

su(WS)

t

h(DATAO)

t

d(DATAO-BCK)

DATAO

DATAI

Fig.12 Serial interface input data timing.

2000 Jul 31 34

t

su(DATAI)

t

h(DATAI)

MGS756

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h(L3)A

t

CLK(L3)L

t

su(L3)DA

t

CLK(L3)H

t

BIT 0

su(L3)A

Fig.13 Timing of address mode.

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

BIT 7

MGL723

handbook, full pagewidth

L3CLOCK

L3MODE

L3DATA

write

L3DATA

read

t

su(L3)D

t

en(L3)R

t

CLK(L3)L

T

cy(CLK)L3

t

su(L3)R

t

su(L3)DA

BIT 0

t

CLK(L3)H

t

h(L3)DA

t

h(L3)R

Fig.14 Timing of data transfer mode for write and read.

t

h(L3)D

BIT 7

t

dis(L3)R

t

stp(L3)

MGU015

2000 Jul 31 35

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jul 31 36

SDA

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

SCL

t

BUF

P

S

t

LOW

t

HD;STA

t

r

t

HD;DAT

t

HIGH

t

f

t

SU;DAT

t

SU;STA

Sr

t

HD;STA

t

SP

t

SU;STO

MBC611

P

Fig.15 Timing of the I2C-bus transfer.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

17 APPLICATION INFORMATION

handbook, full pagewidth

ground

system

clock

I2S-bus

input 1

input 2

L3-bus

+3 V

DA

left

right

left

right

L1

BLM32A07

L2

BLM32A07

47 µF

(16 V)

47 µF

(16 V)

I2C-bus

R13

47 Ω

C1

C3

C12

100 µF

(16 V)

C2

47 µF

(16 V)

C4

47 µF

(16 V)

V

V

C13

100 µF

(16 V)

SYSCLK

DATAO

R1

0 Ω

R2

0 Ω

R3

0 Ω

R4

0 Ω

L3MODE

L3CLOCK

L3DATA

DDD

DDA

BCK

DATAI

VINL1

VINR1

VINL2

VINR2

WS

12

18
16
17
19

2

4

6

8

13
14
15

V

DDA

100 µF

(16 V)

100 nF

(63 V)

V

SSA(ADC)

1

R16
1 Ω

C10

C23

V

DDA(ADC)VADCNVADCP

3

11

V

R17
220 Ω

C11

100 µF

(16 V)

C24

100 nF

(63 V)

5727

UDA1342TS

10

V

V

DDD

DDD

R14
1 Ω

SSD

C21

100 nF

(63 V)

C8

100 µF

(16 V)

R15
1 Ω

C9

100 µF

(16 V)

C22

100 nF

(63 V)

V

SSA(DAC)VDDA(DAC)

25

V

ref

28

VOUTL

26

VOUTR

24

IPSEL

9

QMUTE

23

STATUS

22

STATIC

21

TEST1

20

MGT021

C5

47 µF

(16 V)

C6

47 µF

(16 V)

C20
100 nF
(63 V)

R5

100 Ω

R11
10 kΩ

R6

100 Ω

R12
10 kΩ

C7
47 µF
(16 V)

left

output

right

output

Fig.16 Application diagram.

2000 Jul 31 37

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

18 PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

D

c

y

Z

28 15

A

2

A

pin 1 index

114

w M

b

e

p

1

E

H

E

detail X

Q

L

p

L

(A )

A

X

v M

A

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

0.21

mm

2.0

OUTLINE
VERSION

SOT341-1 MO-150

0.05

1.80

0.25

1.65

IEC JEDEC EIAJ

0.38

0.25

p

0.20

0.09

(1)E(1) (1)

cD

10.4

5.4

10.0

REFERENCES

0.65 1.25

5.2

2000 Jul 31 38

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

1.1

0.7

ISSUE DATE

95-02-04
99-12-27

o

8

o

0

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

19 SOLDERING

19.1 Introduction to soldering surface mount

packages

Thistextgives a very brief insight toacomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

19.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

19.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

2000 Jul 31 39

19.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

19.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Jul 31 40

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

20 DATA SHEET STATUS

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification Development This data sheet contains the design target or goal specifications for

product development. Specification may change in any manner without
notice.

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification Production This data sheet contains final specifications. Philips Semiconductors

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

21 DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values givenare in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any other conditionsabovethosegiven in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythat such applications will be
suitable for the specified use without further testing or
modification.

22 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingthese products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofany of these products, conveys no licenceortitle
under any patent, copyright, or mask work right to these
products,and makes no representations orwarrantiesthat
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2

23 PURCHASE OF PHILIPS I

Purchase of Philips I

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2000 Jul 31 41

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

NOTES

2000 Jul 31 42

Philips Semiconductors Product specification

Audio CODEC UDA1342TS

NOTES

2000 Jul 31 43

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation,Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753503/25/02/pp44 Date of release: 2000 Jul 31 Document order number: 9397 750 07241