Datasheet UDA1340M-N1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1997 May 20
File under Integrated Circuits, IC01

1997 Jul 09

INTEGRATED CIRCUITS

UDA1340

Low-voltage low-power stereo
audio CODEC with DSP features

1997 Jul 09 2

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

FEATURES

General

• Low power consumption

• 3.0 V power supply

• 256, 384 and 512f

s

system clock

• Small package size (SSOP28)

• ADC plus integrated high pass filter to cancel DC offset

• Overload detector for easy record level control

• Separate power control for ADC and DAC

• Integrated digital filter plus DAC

• No analog post filter required for DAC

• Easy application

• Functions controllable by microcontroller interface.

Multiple format input interface

• I

2

S-bus, MSB-justified and LSB-justified format

compatible

• 1fs input and output format data rate.

DAC digital sound processing

• Digital volume control

• Digital tone control, bass boost and treble

• dB-linear volume and tone control (low microcontroller

load)

• Digital de-emphasis for 32, 44.1 and 48 kHz f

s

• Soft mute.

Advanced audio configuration

• Stereo single-ended input configuration

• Stereo line output (under microcontroller volume

control)

• Power-down click prevention circuitry

• High linearity, dynamic range, low distortion.

GENERAL DESCRIPTION

The UDA1340 is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.

The UDA1340 supports the I

2

S-bus data format with word
lengths of up to 20 bits, the MSB-justified data format with
word lengths of up to 20 bits and the LSB justified serial
data format with word lengths of 16, 18 and 20 bits.

The UDA1340 has special sound processing features in
playback mode, de-emphasis, volume, bass boost, treble,
and soft mute, which can be controlled via the
microcontroller interface.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1340M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

1997 Jul 09 3

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA(ADC)

ADC analog supply voltage 2.7 3.0 3.6 V

V

DDA(DAC)

DAC analog supply voltage 2.7 3.0 3.6 V

V

DDO

operational amplifiers supply voltage 2.7 3.0 3.6 V

V

DDD

digital supply voltage 2.7 3.0 3.6 V

I

DDA(ADC)

ADC supply current − 4.5 − mA

I

DDA(DAC)

DAC supply current − 3.5 − mA

I

DDO

operational amplifier supply current − 4 − mA

I

DDD

digital supply current − 6 − mA

I

PD(ADC)

digital ADC power-down supply current − 3 − mA

I

PD(DAC)

digital DAC power-down supply current − 3 − mA

T

amb

operating ambient temperature −20 − +85

°

C

Analog-to-digital converter

V

I(rms)

input voltage (RMS value) − 0.8 − V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−35 −30 dBA

S/N signal-to-noise ratio V

i

= 0 V; A-weighted − 95 − dBA

α

cs

channel separation − 100 − dB

Digital-to-analog converter

V

o(rms)

output voltage (RMS value) − 0.8 − V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−35 − dBA

S/N signal-to-noise ratio code = 0; A weighted − 100 − dBA

α

cs

channel separation − 100 − dB

Power performance

P

ADDA

power consumption in record and
playback mode

− 54 − mW

P

DA

power consumption in playback only
mode

− 33 − mW

P

AD

power consumption in record only
mode

− 27 − mW

P

PD

power consumption in power-down
mode

− 6 − mW

1997 Jul 09 4

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGG839

ADC

3 5

10

11

18
16
17
19

25 27 23 22

12

15

14

13

20

21

8

VINL

V

DDD

V

SSD

DATAO

BCK

WS

DATAI

OVERFL

VOUTL

28

24

9

26

VOUTR

SYSCLK

L3DATA

L3CLOCK

L3MODE

TEST3

TEST2

TEST1

VINR

21

76 4

DECIMATION FILTER

DC-CANCELLATION FILTER

DIGITAL INTERFACE

L3-BUS

INTERFACE

ADC

DAC

V

ref(D)

V

DDO

V

SSO

DAC

INTERPOLATION FILTER

NOISE SHAPER

DSP FEATURES

V

DDA(ADC)VSSA(ADC)

V

ADCP

V

ADCN

V

ref(A)

UDA1340

V

DDA(DAC)VSSA(DAC)

1997 Jul 09 5

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

PINNING

SYMBOL PIN

Description

V

SSA(ADC)

1 ADC analog ground

V

DDA(ADC)

2 ADC analog supply voltage
VINL 3 ADC input left
V

ref(A)

4 ADC reference voltage
VINR 5 ADC input right
V

ADCN

6 ADC negative reference voltage
V

ADCP

7 ADC positive reference voltage
TEST1 8 test control 1 (pull-down)
OVERFL 9 overload flag output
V

DDD

10 digital supply voltage

V

SSD

11 digital ground

SYSCLK 12 system clock 256, 384 or 512f

s

L3MODE 13 L3-bus mode input
L3CLOCK 14 L3-bus clock input
L3DATA 15 L3-bus data input
BCK 16 bit clock input
WS 17 word selection input
DATAO 18 data output
DATAI 19 data input
TEST3 20 test output
TEST2 21 test control 2 (pull-down)
V

SSA(DAC)

22 DAC analog ground

V

DDA(DAC)

23 DAC analog supply voltage
VOUTR 24 DAC output right
V

DDO

25 operational amplifier supply voltage
VOUTL 26 DAC output left
V

SSO

27 operational amplifier ground
V

ref(D)

28 DAC reference voltage

Fig.2 Pin configuration.

handbook, halfpage

V

SSA(ADC)

V

DDA(ADC)

VINL

V

ref(A)

VINR

V

ADCN

V

ADCP

TEST1

OVERFL

V

DDD

V

SSD

SYSCLK

L3MODE

L3CLOCK

V

ref(D)

V

SSO

VOUTL
V

DDO

V

DDA(DAC)

V

SSA(DAC)

VOUTR

TEST2
TEST3
DATAI
DATAO
WS
BCK
L3DATA

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

UDA1340

MGG838

1997 Jul 09 6

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

FUNCTIONAL DESCRIPTION
System clock

The UDA1340 accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f

s

, 384fs and 512fs.
The system clock must be locked in frequency to the digital
interface input signals.

Multiple format input/output interface

The UDA1340 supports the following data input/output
formats:

• I

2

S-bus with data word length of up to 20 bits

• MSB justified serial format with data word length of up to

20 bits

• LSB justified serial format with data word lengths of

16, 18 or 20 bits.

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1340 consists of two
third-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

Decimation filter (ADC)

The decimation from 128f

s

is performed in two stages.
The first stage realizes 3rd-order characteristic. This
filter decreases the sample rate by 16. The second stage,

an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.

Table 1 Decimation filter characteristics

ITEM CONDITION VALUE (dB)

Passband Ripple 0 − 0.45f

s

±0.05

Stop band >0.55f

s

−60

Dynamic range 0 − 0.45f

s

108

Gain overall −1.16

sin x

x

----------- -

DC cancellation filter (ADC)

An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 2.

Table 2 DC cancellation filter characteristics

Mute (ADC)

On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:

DC cancel off: time = , t = 23.2 ms when
f

s

= 44.1 kHz

DC cancel on: time = , t = 279 ms when
f

s

= 44.1 kHz

Overload detection (ADC)

In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f

s

cycles
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.

ITEM CONDITION VALUE (dB)

Passband ripple none
Passband gain 0
Droop at 0.00045f

s

0.031

Attenuation at DC at 0.00000036f

s

>40

Dynamic range 0 − 0.45f

s

>110

1024

f

s

------------ -

12288

f

s

----------------

1997 Jul 09 7

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

Interpolation filter (DAC)

The digital filter interpolates from 1fsto 128fs by means of
a cascade of a recursive filter and an FIR filter.

Table 3 Interpolation filter characteristics

Noise shaper (DAC)

The 3rd-order noise shaper operates at 128f

s

. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.

ITEM CONDITION VALUE (dB)

Passband ripple 0 − 0.45f

s

±0.03

Stop band >0.55f

s

−50

Dynamic range 0 − 0.45f

s

108

Gain DC −3.5

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

1997 Jul 09 8

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

book, full pagewidth

LSB-JUSTIFIED FORMAT 16 BITS

LSB-JUSTIFIED FORMAT 18 BITS

LSB-JUSTIFIED FORMAT 20 BITS

MSB-JUSTIFIED FORMAT

WS

LEFT

LEFT

LEFT

LEFT

RIGHT

RIGHT

RIGHT

RIGHT

32

2

215161718 1

1516 1

1321

MSB B2 MSBLSB LSB MSB B2B2

MSB LSBB2

MSB B2 B3 B4

B15

LSB

B17

215161718 1

MSB B2 B3 B4

LSB

B17

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

21516 1

MSB LSBB2 B15

>=8 >=8

BCK

DATA

WS

LEFT

RIGHT

321321

MSB B2 MSBLSB LSB MSBB2

>=8 >=8

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

INPUT FORMAT I

2

S-BUS

MGG841

Fig.3 Serial interface formats.

1997 Jul 09 9

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

L3-Interface

The UDA1340 has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:

• System clock frequency

• Data input format

• Power control

• DC-filtering

• De-emphasis

• Volume

• Flat/min/max switch

• Bass boost

• Treble

• Mute.

The exchange of data and control information between the
microcontroller and the UDA1340 is accomplished through
a serial hardware interface comprising the following pins:

L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.

Information transfer via the microcontroller bus is
organized in accordance with the so called ‘L3’ format, in
which two different modes of operation can be
distinguished; address mode and data transfer mode
(see Figs 4 and 5).

The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1340 can only be in one direction,
input to the UDA1340 to program its sound processing and
other functional features.

Address mode

The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.4. Data bits 0 to 1 indicate the type of
subsequent data transfer as given in Table 4.

Table 4 Selection of data transfer

Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1340 is 000101 (bit 7 to bit 2). In the event that the
UDA1340 receives a different address, it will deselect its
microcontroller interface logic.

Data transfer mode

The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1340 receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4.
The maximum input clock and data rate is 64f

s

.
All transfers are byte wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1340 after the
eighth bit of a byte has been received. A multibyte transfer
is illustrated in Fig.6.

P

ROGRAMMING THE SOUND PROCESSING AND OTHER

FEATURES

The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, BIT 1 and BIT 0
(see Table 4). The second selection is performed by the
2 MSBs of the data byte (BIT 7 and BIT 6). The other bits
in the data byte (BIT 5 to BIT 0) is the value that is placed
in the selected registers.

When the data transfer of type ‘data’ is selected, the
features VOLUME, BASS BOOST, TREBLE,
DE-EMPHASIS, MUTE, MODE and POWER CONTROL
can be controlled. When the data transfer of type ‘status’
is selected, the features SYSTEM CLOCK FREQUENCY,
DATA INPUT FORMAT and DC-FILTER can be
controlled.

BIT 1 BIT 0 TRANSFER

0 0 DATA (volume, bass boost, treble,

de-emphasis, mute, mode and power

control)
0 1 not used
1 0 STATUS (system clock frequency, data

input format and DC-filter)
1 1 not used

1997 Jul 09 10

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

Fig.4 Timing address mode.

handbook, full pagewidth

t

h;MA

t

s;MA

t

h;DAT

t

s;DAT

T

cy

BIT 0

L3MODE

L3CLOCK

L3DATA

BIT 7

MGD016

t

LC

t

HC

t

s;MA

t

h;MA

Fig.5 Timing for data transfer mode.

handbook, full pagewidth

t

halt

t

s;MT

t

h;DAT

t

s;DAT

t

h;DAT

t

halt

t

h;MT

MGD017

T

cy

BIT 0

L3MODE

L3CLOCK

L3DATA

write

BIT 7

t

LC

t

HC

1997 Jul 09 11

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

Table 5 Data transfer of type ‘status’; note 1

Note

1. X = don’t care.

Table 6 Data transfer of type ‘data’; note 1

Note

1. X = don’t care.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 X SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (1 : 0)

data Input Format (2 : 0)
DC-filter

1XXXXXXXnot used

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
0 1 BB3 BB2 BB1 BB0 TR1 TR0 Bass Boost (3 : 0)

Treble (1 : 0)

1 0 X DE1 DE0 MT M1 M0 DE-emphasis (1 : 0)

MuTe
Mode (1 : 0)

11XXXXPC1PC0Power Control (1 : 0)

Fig.6 Multibyte transfer.

h

andbook, full pagewidth

t

halt

address

L3DATA

L3CLOCK

L3MODE

addressdata byte #1 data byte #2

MGD018

1997 Jul 09 12

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

SYSTEM CLOCK FREQUENCY
A 2-bit value (SC1 and SC0) to select the used external

clock frequency (see Table 7).

Table 7 System clock frequency settings

D

ATA INPUT FORMAT

A 3-bit value (IF2 to IF0) to select the used data format
(see Table 8).

Table 8 Data input format settings

SC1 SC0 FUNCTION

0 0 512f

s

0 1 384f

s

1 0 256f

s

1 1 not used

IF2 IF1 IF0 FUNCTION

000 I

2

S-bus
0 0 1 LSB justified, 16 bits
0 1 0 LSB justified, 18 bits
0 1 1 LSB justified, 20 bits
1 0 0 MSB justified
1 0 1 not used
1 1 0 not used
1 1 1 not used

DC-FILTER
A 1-bit value to enable the digital DC-filter (see Table 9).

Table 9 DC-filtering

V

OLUME CONTROL

A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in
steps of 1 dB (see Table 10).

Table 10 Volume settings

DC FUNCTION

0 no DC-filtering
1 DC-filtering

VC5 VC4 VC3 VC2 VC1 VC0

VOLUME

(dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
111011 −58
111100 −59
111101 −60
111110 −∞
111111 −∞

1997 Jul 09 13

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

BASS BOOST
A 4-bit value to program the bass boost setting. The used set depends on the MODE bits.

Table 11 Bass boost settings

T

REBLE

A 2-bit value to program the treble setting. The used set depends on the MODE bits.

Table 12 Treble settings

BB3 BB2 BB1 BB0

BASS BOOST

FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)

0000 0 0 0
0001 0 2 2
0010 0 4 4
0011 0 6 6
0100 0 8 8
0101 0 10 10
0110 0 12 12
0111 0 14 14
1000 0 16 16
1001 0 18 18
1010 0 18 20
1011 0 18 22
1100 0 18 24
1101 0 18 24
1110 0 18 24
1111 0 18 24

TR1 TR0

TREBLE

FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)

00000
01022
10044
11066

1997 Jul 09 14

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.

Table 13 De-emphasis settings

M

UTE

A 1-bit value to enable the digital mute.

Table 14 Mute

MODE
A 2-bit value to program the mode of the sound processing

filters of Bass Boost and Treble. There are three modes:
flat, min. and max.

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz

MT FUNCTION

0 no muting
1 muting

Table 15 The flat/min./max. switch

P

OWER CONTROL

A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.

Table 16 Power control settings

M1 M0 FUNCTION

0 0 flat
0 1 min.
1 0 min.
1 1 max.

PC1 PC0

FUNCTION

ADC DAC

00offoff
0 1 off on
1 0 on off
1 1 on on

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V

DDD=VDDA=VDDO

= 3 V; T

amb

=25°C; unless otherwise specified.

Notes

1. All V

DD

and VSS connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pins 24, 26 and 28 which can
withstand ESD pulses of −1500 V to +1500 V.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

supply voltage note 1 − 5.0 V

T

xtal(max)

maximum crystal temperature − 150 °C

T

stg

storage temperature −65 +125 °C

T

amb

operating ambient temperature −20 +85 °C

V

es

electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 90 K/W

1997 Jul 09 15

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

DC CHARACTERISTICS

V

DDD=VDDA=VDDO

=3V; T

amb

=25°C; RL=5kΩ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27);

unless otherwise specified.

Notes

1. All power supply pins (V

DD

and VSS) must be connected to the same external power supply unit.

2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output
in order to prevent oscillations in the output operational amplifier.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA(ADC)

ADC analog supply voltage 2.7 3.0 3.6 V

V

DDA(DAC)

DAC analog supply voltage 2.7 3.0 3.6 V

V

DDO

operational amplifiers supply voltage 2.7 3.0 3.6 V

V

DDD

digital supply voltage 2.7 3.0 3.6 V

I

DDA(ADC)

ADC supply current operation mode − 4.5 − mA

ADC power-down − 200 −µA

I

DDA(DAC)

DAC supply current operation mode − 3.5 − mA

DAC power-down − 15 −µA

I

DDO

operational amplifier supply current operation mode − 4 − mA

DAC power-down − 15 −µA

I

DDD

digital supply current operation mode − 6 − mA

DAC power-down − 3 − mA
ADC power-down − 3 − mA

Digital input pins

V

IH

HIGH level input voltage 0.8V

DDD

− V

DDD

+ 0.5 V

V

IL

LOW level input voltage −0.5 − +0.2V

DDD

V

I

LI

 input leakage current −−10 µA

C

i

input capacitance −−10 pF

Digital output pins

V

OH

HIGH level output voltage IOH= −2 mA 0.85V

DDD

−− V

V

OL

LOW level output voltage IOL=2mA −−0.4 V

Analog-to-digital converter

V

ref

reference voltage with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

R

o(ref)

V

refA

reference output resistance pin 4 − 24 − kΩ

R

i

input resistance 1 kHz − 9.8 − kΩ

C

i

input capacitance − 20 − pF

Digital-to-analog converter

V

ref

reference voltage with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

R

o(ref)

V

refD

reference output resistance pin 28 − 28 − kΩ

R

o

DAC output resistance − 0.13 3.0 Ω

I

o(max)

maximum output current (THD + N)/S < 0.1%

RL=5kΩ

− 0.22 − mA

R

L

load resistance 3 −− kΩ

C

L

load capacitance note 2 −−200 pF

1997 Jul 09 16

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA=VDDO

=3V; fi= 1 kHz; T

amb

=25°C; RL=5kΩ all voltages referenced to ground

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital converter

V

i(rms)

input voltage (RMS value) − 0.8 − V

∆V

i

unbalance between channels − 0.1 − dB

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−35 −30 dBA

S/N signal-to-noise ratio V

i

= 0 V; A-weighted − 95 − dBA

α

CS

channel separation − 100 − dB

PSRR power supply rejection ratio f

ripple

= 1 kHz;

V

ripple(p-p)

=30mV

− 30 − dB

Digital-to-analog converter

V

o(rms)

output voltage (RMS value) − 0.8 − V

∆V

o

unbalance between channels − 0.1 − dB

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−35 − dBA

S/N signal-to-noise ratio code = 0; A-weighted − 100 − dBA

α

cs

channel separation − 80 − dB

PSRR power supply rejection ratio f

ripple

= 1 kHz;

V

ripple(p-p)

= 100 mV

− 50 − dB

1997 Jul 09 17

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA=VDDO

= 2.7 to 3.6 V; T

amb

= −20 to +85 °C; RL=5kΩ; all voltages referenced to ground

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

T

cy

clock cycle f

sys

= 256f

s

78 88 131 ns

f

sys

= 384f

s

52 59 87 ns

f

sys

= 512f

s

39 44 66 ns

t

CWL

f

sys

LOW level pulse width f

sys

< 19.2 MHz 30 − 70 %T

sys

f

sys

≥ 19.2 MHz 40 − 60 %T

sys

t

CWH

f

sys

HIGH level pulse width f

sys

< 19.2 MHz 30 − 70 %T

sys

f

sys

≥ 19.2 MHz 40 − 60 %T

sys

Serial input/output data timing; see Fig.7
t

BCK

bit clock period

1

⁄64fs−−ns

t

BCK(H)

bit clock HIGH time 100 −−ns

t

BCK(L)

bit clock LOW time 100 −−ns

t

r

rise time −−20 ns

t

f

fall time −−20 ns

t

s;DATI

data input set-up time 20 −−ns

t

h;DATI

data input hold time 0 −−ns

t

d(DATO)(BCK)

data output delay time (from BCK falling edge) −−80 ns

t

d(DATO)(WS)

data output delay time (from WS edge) MSB-justified format −−80 ns

t

h;DATO

data output hold time 0 −−ns

t

s;WS

word selection set-up time 20 −−ns

t

h;WS

word selection hold time 10 −−ns
Address and data transfer mode timing; see Figs 4 and 5
T

cy

L3CLK cycle time 500 −−ns
t

HC

L3CLK HIGH period 250 −−ns
t

LC

L3CLK LOW period 250 −−ns
t

s;MA

L3MODE set-up time address mode 190 −−ns
t

h;MA

L3MODE hold time address mode 190 −−ns
t

s;MT

L3MODE set-up time data transfer mode 190 −−ns
t

h;MT

L3MODE hold time data transfer mode 190 −−ns
t

s;DAT

L3DATA set-up time data transfer mode

and address mode

190 −−ns

t

h;DAT

L3DATA hold time data transfer mode

and address mode

30 −−ns

t

halt

L3MODE halt time 190 −−ns

1997 Jul 09 18

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

Fig.7 Serial interface timing.

handbook, full pagewidth

MGG840

WS

BCK

DATAO

DATAI

t

f

t

r

t

h;WS

t

s;WS

t

BCK(H)

t

BCK(L)

T

cy

t

h;DATO

t

s;DATI

t

h;DATI

t

d(DATO)(BCK)

t

d(DATO)(WS)

1997 Jul 09 19

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

APPLICATION INFORMATION

Fig.8 Application diagram.

handbook, full pagewidth

MGK582

47 Ω

R30

C11

100 µF

(16 V)

C12

100 µF

(16 V)

V

DDA

V

DDD

L1

8LM32A07

8LM32A07

L2

3 V

ground

1

V

SSA(ADC)

UDA1340

12

4

SYSCLK

V

ref(A)

10

26711

V

DDD

V

DDA(ADC)VADCNVADCPVSSD

system

clock

18

DATAO

16

BCK

17

WS

overload

flag

9

OVERFL

R32
1 MΩ

C1

C31
1 nF
(63 V)

47 µF
(16 V)

3

VINL

26

VOUTL

R23

100 Ω
R22
10 kΩ

24

VOUTR

R26

100 Ω
R27

10 kΩ

R33
680 kΩ

C6

C32
1 nF
(63 V)

47 µF
(16 V)

5

VINR

19

DATAI

13

L3MODE

14

L3CLOCK

15

L3DATA

100 nF

(63 V)

R21
1 Ω

R24

C2

100 µF

(16 V)

C25

100 nF
(63 V)

C21

V

DDA

C3
47 µF
(16 V)

C8

47 µF
(16 V)

C5

47 µF
(16 V)

C22
100 nF
(63 V)

28

V

ref(D)

C4
47 µF
(16 V)

C23
100 nF
(63 V)

100 nF

(63 V)

R28
1 Ω

C9

100 µF

(16 V)

C29

V

DDD

V

SSO

27

V

DDO

25

R25
1 Ω

C7

100 µF

(16 V)

C26

100 nF
(63 V)

V

DDO

V

DDA(DAC)

V

SSA(DAC)

23

22

R29
1 Ω

C10

100 µF
(16 V)

C27

100 nF

(63 V)

V

DDA

left

output

right

output

left

input

right

input

X5

X4

X2

X3

1997 Jul 09 20

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

PACKAGE OUTLINE

UNIT A1A

2

A3b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

10.4

10.0

5.4

5.2

0.65 1.25

7.9

7.6

0.9

0.7

1.1

0.7

8
0

o
o

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150AH

93-09-08
95-02-04

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

114

28 15

0.25

y

pin 1 index

0 2.5 5 mm

scale

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

A

max.

2.0

1997 Jul 09 21

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Jul 09 22

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1997 Jul 09 23

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 547027/1200/02/pp24 Date of release: 1997 Jul 09 Document order number: 9397 750 02548