Datasheet UDA1335H Datasheet (Philips)

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DATA SH EET

UDA1335H

Universal Serial Bus (USB) Audio
Playback Recording Peripheral
(APRP)

Preliminary specification
File under Integrated Circuits, IC01

1998 Aug 28

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

FEATURES
General

• USB stereo audio record and playback system with
20 bits analog-to-digital conversion (with 5 to 55 kHz
sample frequency range) and adaptive 20 bits
digital-to-analog conversion (with 5 to 55 kHz sample
frequency range) with integrated filtering

• USB-compliant audio/HID device

• Supports 12 Mbits/s ‘full speed’ serial data transmission

• Fully automatic ‘Plug-and-Play’ operation

• Supports multiple audio data formats (8, 16 and 24 bits)

• 5.0 and 3.3 V power supply

• Low power consumption

• Efficient power management

• On-chip master clock oscillators, only an external crystal

is required

• High linearity

• Wide dynamic range

• Superior signal-to-noise ratio

• Low total harmonic distortion

• Supports headphone and line output

• Partly programmable USB descriptors and configuration

via the I

Sound processing (for digital-to analog conversion)

• Separate digital volume control for left and right channel

• Soft mute

• Digital bass and treble tone control

• External Digital Sound Processor (DSP) option possible

via standard I

• Selectable clipping prevention

• Selectable Dynamic Bass Boost (DBB)

• On-chip digital de-emphasis.

2

C-bus.

2

S-bus or Japanese digital I/O format

UDA1335H

Document references

•

“USB Specification”

•

“USB Device Class Definition for Audio Devices”

•

“Device Class Definition for Human Interface Devices
(HID)”

•

“USB HID Usage Table”

•

“USB Common Class Specification”

GENERAL DESCRIPTION

The UDA1335H is a stereo CMOS codec incorporating
bitstream converters designed for implementation in
USB-compliant audio peripherals and multimedia audio
applications. The UDA1335H is an adaptive asynchronous
sink USB audio device with a continuous sampling
frequency range from 5 to 55 kHz. It contains a USB
interface, an embedded microcontroller, an
Analog-to-Digital Interface (ADIF) and an Asynchronous
Digital-to-Analog Converter (ADAC).

The USB interface is the interface between the USB, the
ADIF, the ADAC and the microcontroller. The USB
interface consists of an analog front-end and a USB
processor. The analog front-end transforms the differential
USB data into a digital data stream. The USB processor
buffers the incoming and outgoing data from the analog
front-end and handles all low-level USB protocols.
The USB processor selects the relevant data from the
universal serial bus, performs an extensive error detection
and separates control information (input and output) and
audio information (input and output). The control
information is made accessible to the microcontroller.
The audio information received from the PC becomes
available at the digital I/O output or is fed directly to the
ADAC. The audio information to be transmitted to the PC
is delivered by the ADIF or by the digital I

The microcontroller handles the high-level USB protocols,
translates the incoming control requests and manages the
user interface via general purpose pins and an I2C-bus.

.

2

S-bus interface.

1998 Aug 28 2

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

The firmware for the microcontroller must be located in an
external (E)PROM.

The ADAC enables the wide and continuous range of input
sampling frequencies. By means of a Sample Frequency
Generator (SFG), the ADAC is able to reconstruct the
average sample frequency from the incoming audio
samples. The ADAC also performs the sound processing.
The ADAC consists of a FIFO, a unique audio feature
processing DSP, the SFG, digital upsampling filters, a
variable hold register, a Noise Shaper (NS) and a Filter
Stream DAC (FSDAC) with integrated filter and line output
drivers. The audio information is applied to the ADAC via
the USB processor or via the digital I/O input.

The ADIF consists of an Programmable Gain Amplifier
(PGA), an Analog-to-Digital Converter (ADC) and a
Decimator Filter (DF). An Analog Phase Lock Loop (APLL)
or oscillator is used for clocking the ADIF. The clock
frequency for the ADIF can be controlled via the
microcontroller. Several clock frequencies are possible for
sampling the analog input signal at different sampling
rates.

UDA1335H

Via the digital I/O-bus, an external DSP can be used for
adding extra sound processing features for the audio
received from the PC.

The UDA1335H supports the digital I/O and the I2S-bus
interface, with standard I2S-bus data input format and the
LSB justified serial data input format with word lengths of
16, 18 and 20 bits.

The wide dynamic range of the bitstream conversion
technique used in the UDA1335H guarantees a high audio
sound quality.

APPLICATIONS

• USB monitors

• USB speakers

• USB headsets

• USB telephone/answering machines

• USB links in consumer audio devices.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

UDA1335H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT319-2

1998 Aug 28 3

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDE

V

DDI

I

DD(tot)

I

DD(tot)(ps)

Dynamic performance DAC

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio at bipolar zero A-weighted at code 0000H 90 95 − dBA
V

o(FS)(rms)

supply voltage periphery 4.75 5.0 5.25 V
supply voltage core 3.0 3.3 3.6 V
total supply current − 60 tbf mA
total supply current in power-saving

note 1 − 360 −µA

mode

= 44.1 kHz; RL=5kΩ

f

s

noise-to-signal ratio

f

= 1 kHz (0 dB) −−90 −80 dB

i

− 0.0032 0.01 %

f

= 1 kHz (−60 dB) −−30 −20 dB

i

− 3.2 10 %

full-scale output voltage

VDD= 3.3 V − 0.66 − V

(RMS value)

Dynamic performance PGA and ADC

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

S/N signal-to-noise ratio V

General characteristics

f

i(s)

T

amb

audio input sample frequency 5 − 55 kHz
operating ambient temperature 0 25 70 °C

Note

1. Exclusive the I

current which depends on the components connected to the I/O pins.

DDE

f

= 44.1 kHz;

s

PGA gain = 0 dB

f

= 1 kHz; (0 dB);

i

Vi= 1.0 V (RMS)
f

= 1 kHz (−60 dB) −−30 −20 dB

i

−−85 −80 dB

− 0.0056 0.01 %

− 3.2 10.0 %

= 0.0 V 90 95 − dBA

i

1998 Aug 28 4

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

BLOCK DIAGRAM

handbook, full pagewidth

V

SSX

XTAL1b
XTAL2b

V

DDX

V

DDA3
XTAL2a
XTAL1a

V

SSA3

GP2/DO

GP3/WSO

GP4/BCKO

GP1/DI

GP0/BCKI

GP5/WSI

CLK
27

24
25
26
28
52
53
54
55

63
1
2
13
17
15

OSC

48 MHz

OSC
ADC

TIMING

ANALOG

PLL

D+
8 6

ANALOG FRONT-END

USB-PROCESSOR

UDA1335H

D−

P0.7 to P0.0

7, 5, 3, 64,
62, 60, 58, 56

DIGITAL I/O

P2.0 to P2.7

14, 16, 18, 20,
22, 23, 29, 30

MICRO-

CONTROLLER

V

9

DDI

V

10

SSI

V

11

SSE

V

12

DDE

V

32

DDO

V

33

SSO

V

38

DDA1

V

39

SSA1

V

42

DDA2

V

44

SSA2

SCL

19

SDA

21

PSEN

WS

BCK

ALE

VINL

VINR

VRN
VRP

31

57

DA

59
61

48

EA

50

43

PGA

47

PGA

49
51

INTERFACE

MUX

SAMPLE

I2S-BUS

LEFT

Σ∆ ADC

DECIMATOR

FILTER

FREQUENCY
GENERATOR

UDA1335H

RIGHT

Σ∆ ADC

REFERENCE VOLTAGE

45, 46 41 40
n.c.

V

ref(AD)

AUDIO FEATURE

PROCESSING DSP

UPSAMPLE FILTERS

VARIABLE HOLD REGISTER

3rd-ORDER NOISE SHAPER

V

ref(DA)

FIFO

LEFT

DAC

RIGHT

DAC

TEST

CONTROL

BLOCK

−
+

+

−

35
36

34

37

MBK838

4

SHTCB
TC
RTCB

VOUTL

VOUTR

Fig.1 Block diagram.

1998 Aug 28 5

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

PINNING

SYMBOL

GP3/WSO 1 I/O general purpose pin 3 or word select output
GP4/BCKO 2 I/O general purpose pin 4 or bit clock output
P0.5 3 I/O port 0.5 of the microcontroller
SHTCB 4 I shift clock of the test control block (active HIGH)
P0.6 5 I/O port 0.6 of the microcontroller
D− 6 I/O negative data line of the differential data bus, conforms to the USB standard
P0.7 7 I/O port 0.7 of the microcontroller
D+ 8 I/O positive data line of the differential data bus, conforms to the USB standard
V

DDI

V

SSI

V

SSE

V

DDE

GP1/DI 13 I/O general purpose pin 1 or data input
P2.0 14 I/O port 2.0 of the microcontroller
GP5/WSI 15 I/O general purpose pin 5 or word select input
P2.1 16 I/O port 2.1 of the microcontroller
GP0/BCKI 17 I/O general purpose pin 0 or bit clock input
P2.2 18 I/O port 2.2 of the microcontroller
SCL 19 I/O serial clock line I
P2.3 20 I/O port 2.3 of the microcontroller
SDA 21 I/O serial data line I
P2.4 22 I/O port 2.4 of the microcontroller
P2.5 23 I/O port 2.5 of the microcontroller
V

SSX

XTAL1b 25 I crystal input (analog; 48 MHz)
XTAL2b 26 O crystal output (analog; 48 MHz)
CLK 27 O 48 MHz clock output signal
V

DDX

P2.6 29 I/O port 2.6 of the microcontroller
P2.7 30 I/O port 2.7 of the microcontroller
PSEN 31 I/O program store enable (active LOW)
V

DDO

V

SSO

VOUTL 34 O voltage output left channel
TC 35 I test control input (active HIGH)
RTCB 36 I asynchronous reset input of the test control block (active HIGH)
VOUTR 37 O voltage output right channel
V

DDA1

V

SSA1

PIN

QFP64

I/O DESCRIPTION

9 − digital supply voltage for core
10 − digital ground for core
11 − digital ground for I/O pads
12 − digital supply voltage for I/O pads

2

C-bus

2

C-bus

24 − crystal oscillator ground (48 MHz)

28 − supply crystal oscillator (48 MHz)

32 − supply voltage for operational amplifier
33 − operational amplifier ground

38 − analog supply voltage 1
39 − analog ground 1

1998 Aug 28 6

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

SYMBOL

V

ref(DA)

V

ref(AD)

V

DDA2

VINL 43 I input signal left channel PGA
V

SSA2

n.c. 45 − not connected
n.c. 46 − not connected
VINR 47 I input signal right channel PGA
EA 48 − external access (active LOW)
VRN 49 I negative reference input voltage ADC
ALE 50 − address latch enable (active HIGH)
VRP 51 I positive reference input voltage ADC
V

DDA3

XTAL2a 53 O crystal output (analog; ADC)
XTAL1a 54 I crystal input (analog; ADC)
V

SSA3

P0.0 56 I/O port 0.0 of the microcontroller
DA 57 I data Input (digital)
P0.1 58 I/O port 0.1 of the microcontroller
WS 59 I word select input (digital)
P0.2 60 I/O port 0.2 of the microcontroller
BCK 61 I bit clock input (digital)
P0.3 62 I/O port 0.3 of the microcontroller
GP2/DO 63 I/O general purpose pin 2 or data output
P0.4 64 I/O port 0.4 of the microcontroller

PIN

QFP64

40 O reference voltage output DAC
41 O reference voltage output ADC
42 − analog supply voltage 2

44 − analog ground 2

52 − supply voltage for crystal oscillator and analog PLL

55 − crystal oscillator and analog PLL ground

I/O DESCRIPTION

UDA1335H

1998 Aug 28 7

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

handbook, full pagewidth

P0.4

GP2/DO

P0.3

BCK

P0.2WSP0.1DAP0.0

64

63

62

61

60

GP3/WSO

GP4/BCKO

SHTCB

GP1/DI

GP5/WSI

GP0/BCKI

V

V

V

P0.5

P0.6

D−

P0.7

D+

DDI

V

SSI

SSE

DDE

P2.0

P2.1

P2.2

SCL

1
2
3
4
5
6
7
8
9

23

P2.5

UDA1335H

24

SSX

V

10
11
12
13
14
15
16
17
18
19

20

21

22

SDA

P2.3

P2.4

59

58

25

26

XTAL1b

XTAL2b

57

27

CLK

56

28

DDX

V

SSA3

V
55

29

P2.6

XTAL1a

XTAL2a

54

53

30

31

P2.7

PSEN

DDA3

V
52

32

DDO

V

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

MBK841

VRP
ALE
VRN
EA
VINR
n.c.
n.c.
V

SSA2

VINL
V

DDA2

V

ref(AD)

V

ref(DA)

V

SSA1

V

DDA1

VOUTR
RTCB
TC
VOUTL
V

SSO

UDA1335H

Fig.2 Pin configuration.

1998 Aug 28 8

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

FUNCTIONAL DESCRIPTION
The Universal Serial Bus (USB)

Data and power is transferred via the USB over a 4-wire
cable. The signalling occurs over two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90 Ω intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.

The analog front-end

The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to V
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).

The USB processor

The USB processor forms the interface between the
analog front-end, the ADIF, the ADAC and the
microcontroller. The USB processor consists of:

• The Philips Serial Interface Engine (PSIE)

• The Memory Management Unit (MMU)

• The Audio Sample Redistribution (ASR) module.

DD

UDA1335H

The MMU is the digital back-end of the USB processor.
It handles the temporary data storage of all USB packets
that are received or sent over the bus. Three types of
packets are defined on the USB. These are:

• Token packets

• Data packets

• Handshake packets.

The token packet contains information about the
destination of the data packet. The audio data is
transferred via an isochronous data sink endpoint or
source endpoint and, consequently, no handshaking
mechanism is used. The MMU also generates a 1 kHz
clock that is locked to the USB Start Of Frame (SOF)
token.

The Audio Sample Redistribution (ASR)

The ASR reads the audio samples from the MMU and
distributes these samples equidistant over a 1 ms frame
period. The distributed audio samples are translated by
the digital I/O module to standard I
Japanese digital I/O format. The ASR generates the bit
clock and the word select signal of the digital I/O.
The digital I/O formats the received audio samples to one
of the four specified serial digital audio formats
(I2S-bus, 16, 18 or 20 bits LSB-justified).

2

S-bus format or

The Philips Serial Interface Engine and Memory
Management Unit (PSIE/MMU)

The PSIE/MMU translates the electrical USB signals into
bytes and signals. Depending upon the USB device
address and the USB endpoint address, the USB data is
directed to the correct endpoint buffer on the PSIE/MMU
interface. The data transfer could be of bulk, isochronous,
control or interrupt type. The USB device address is
configured during the enumeration process.

The UDA1335H has four endpoints. These are:

• Control endpoint 0

• Status interrupt endpoint

• Isochronous data sink endpoint

• Isochronous data source endpoint.

The amount of bytes/packet on the control endpoint is
limited by the PSIE/MMU hardware to 8 bytes/packet.

The PSIE is the digital front-end of the USB processor.
This module recovers the 12 MHz USB clock, detects the
USB sync word and handles all low-level USB protocols
and error checking.

The microcontroller

The microcontroller receives the control information
selected from the USB by the USB processor. It handles
the high-level USB protocols and the user interfaces.

The major task of the software process, that is mapped
upon the microcontroller, is to control the different modules
of the UDA1335H in such a way that it behaves as a USB
device.

Therefore the microcontroller:

• Interprets the USB requests and maps them upon the
UDA1335H application

• Controls the internal operation of the UDA1335H, the
digital I/O pins and the GP I/O pins

• Communicates with the external world (external
controller, EEPROM) using the I
GP I/O pins.

The microcontroller does not handle the audio stream.
The UDA1335H will be delivered with USB compliant
firmware. The firmware must be located in an external
(E)PROM.

2

C-bus facility and the

1998 Aug 28 9

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

The Analog-to-Digital Interface (ADIF)

The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The timing of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
clock with a range between 5 to 55 kHz. Digital serial input
is possible with four formats (I2S-bus, 16, 18 or 20 bits
LSB-justified).

The Programmable Gain Amplifier circuit (PGA)

This circuit can be used for a microphone or line input.
The input audio signals can be amplified by 7 different
gains. The preferred gain is selected during start-up of the
device (configuration map).

UDA1335H

The Decimation Filter (DF)

The decimator filter converts the audio data from 128f
down to 1fs with a word width of 8, 16 or 24 bits. This data
will be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.

The timing of the analog-to-digital interface

The clock source of the ADIF is the analog PLL or the ADC
oscillator. The preferred clock source can be selected
during start-up of the device (configuration map). The ADC
clock used for the ADC and decimation filters is obtained
by dividing the clock signal coming from the analog PLL or
from the ADC oscillator by a factor Q.

Using the analog PLL the user can select 3 clock
frequencies via the microcontroller.

By connecting the appropriate crystal the user can choose
any clock signal between 8.192 and 14.08 MHz via the
ADC oscillator.

s

The gain settings are given in Table 1.

Table 1 The selectable gains of the PGA

SETTING GAIN UNIT

000 −3dB
001 0 dB
010 3 dB
011 9 dB
100 15 dB
101 21 dB
11X 27 dB

The Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1335H consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.

Table 2 The analog PLL clock output frequencies

FCODE

00 11.2896
01 8.1920
10 12.2880
11 11.2896

The dividing factor Q can be selected via the
microcontroller. With this dividing factor Q the user can
select a range of ADC clock signals allowing several
different sample frequencies (see Table 3).

APLL CLOCK

FREQUENCY (MHz)

1998 Aug 28 10

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

Table 3 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source

(analog input topology 1), see note 1.

APLL CLOCK

FREQUENCY (MHz)

8.1920 1 4.096 32

11.2896 1 5.6448 44.1

12.2880 1 6.144 48

Note

1. By using the APLL as a clock source 12 sample frequencies will be reported to the USB host.

DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)

2 2.048 16
4 1.024 8
8 0.512 (not supported) 4 (not supported)

2 2.8224 22.05
4 1.4112 11.025
8 0.7056 5.5125

2 3.072 24
4 1.536 12
8 0.768 6

Table 4 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source

(analog input topology 4), see note 1

OSCAD CLOCK

FREQUENCY (MHz)

(2)

f

osc

Notes

1. By using the OSCAD as a clock source, the sample frequency and the Q dividing factor must be filled in the
configuration map. Only this one sample frequency will be reported to the USB host.

2. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.

3. The Q factor can be 1, 2, 4 or 8.

4. Sample frequencies below 5 kHz and above 55 kHz are not supported.

DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)

(3)

Q

f

/(2Q) f

osc

/(256Q)

osc

(4)

1998 Aug 28 11

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

The Asynchronous Digital-to-Analog Converter
(ADAC)

The ADAC receives USB audio information from the USB
processor or from the digital I/O-bus. The ADAC is able to
reconstruct the sample clock from the rate at which the
audio samples arrive and handles the audio sound
processing. After the processing, the audio signal is
upsampled, noise-shaped and converted to analog output
voltages capable of driving a line output. The ADAC
consists of:

• A Sample Frequency Generator (SFG)

• FIFO registers

• An audio feature processing DSP

• Two digital upsampling filters and a variable hold

register

• A digital Noise Shaper (NS)

• A Filter Stream DAC (FSDAC) with integrated filter and

line output drivers.

The Sample Frequency Generator (SFG)

The SFG controls the timing signals for the asynchronous
digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the upsampling
filters.

First-In First-Out (FIFO) registers

The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO (in conjunction with the
SFG) is necessary to remove all jitter present on the
incoming audio signal.

UDA1335H

Table 5 Frequency domains for audio processing by the

DSP

DOMAIN SAMPLE FREQUENCY (kHz)

1 5 to 12
212to25
325to40
440to55

The upsampling filters and variable hold function

After the audio feature processing DSP two upsampling
filters and a variable hold function increase the
oversampling rate to 128f

The noise shaper

A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.

USB Audio Playback Recording Peripheral (APRP)
descriptors

.

s

The audio feature processing DSP

A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the USB APRP”. Depending on the sampling
rate (f

) the DSP knows four frequency domains in which

s

the treble and bass are regulated. The domain is chosen
automatically.

1998 Aug 28 12

In a typical USB environment the PC has to know which
kind of devices are connected. For this purpose each
device contains a number of USB descriptors. These
descriptors describe, from different points of view (USB
configuration, USB interface and USB endpoint), the
capabilities of a device. Each of them can be requested by
the host. The collection of descriptors is denoted as a
descriptor map. This descriptor map will be reported to the
USB host during enumeration and on request.

The USB descriptors and their most important fields, in
relationship to the characteristics of the UDA1335H are
explained briefly below.

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

AUDIO FUNCTION TOPOLOGIES
Four audio function Input topologies and two audio function output topologies are supported by the UDA1335H. Each

configuration map can select only one Input and one output topology. The descriptors and the supported requests
depend on the selected topologies in the active configuration map. Figures 3 and 4 illustrate the different audio Input and
output topologies.

handbook, full pagewidth

INPUT TERMINAL

IT

Fig.3 One audio output function topology (with or without bass boost) is supported.

FEATURE UNIT

FU

OUTPUT TERMINAL

OT

MBK530

handbook, full pagewidth

Analog
Input Terminal

IT OT

a. Analog topology 1 (using APLL clock source).

Input Terminal 1

Input Terminal 2

IT

IT

SELECTOR UNIT

SU

b. Analog topology 2.

Digital
Input Terminal

IT OT

c. Digital topology 3.

Analog
Input Terminal

IT OT

d. Analog topology 4 (using OSCAD clock source).

OT

Output
Terminal

Output
Terminal

Output
Terminal

Output
Terminal

MGL437

Fig.4 Four input function topologies are supported.

1998 Aug 28 13

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

GENERAL DESCRIPTORS
The UDA1335H supports one configuration containing a

control interface, two audio interfaces and a HID interface.
The descriptor map that describes this configuration is
partly fixed and partly programmable.

The programmable part can be retrieved from one of four
configuration maps located in the firmware or from an
I2C-bus EEPROM. At start-up time one of four internal
configuration maps can be selected depending on the
logical combination of GP3 and GP4. It is possible to
overwrite this configuration map with a configuration map
loaded from an I2C-bus EEPROM.

UDIO DEVICE CLASS SPECIFIC DESCRIPTORS

A
The audio device class is partly specified with standard

descriptors and partly with specific audio device class
descriptors. The standard descriptors specify the number
and the type of the interface or endpoint. The UDA1335H
supports 7 different audio modes:

• 8-bit PCM mono or stereo audio data

• 16-bit PCM mono or stereo audio data

• 24-bit PCM mono or stereo audio data

• Zero bandwidth mode.

Each mode is defined as an alternate setting of the audio
interface, selectable with the standard audio streaming
interface descriptor bAlternateSetting field.

The seven alternate settings are described in more detail
by the specific audio device class descriptors.

The UDA1335H supports the input terminal, output
terminal and the feature unit descriptors.

The input and output terminals are not controllable via the
USB. The feature unit provides the basic manipulation of
the incoming logical channels.

The supported sound features are:

• Volume control

• Mute control

• Treble control

• Bass control

• Bass Boost control.

The maximum number of audio data samples within a USB
packet arriving on the isochronous sink endpoint is
restricted by the buffer capacity of this isochronous
endpoint. The maximum buffer capacity is 336 bytes/ms.

UDA1335H

T

HE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR

FOR THE ISOCHRONOUS DATA SINK ENDPOINT

In this section the descriptors are given for interface 1
which is used for receiving isochronous audio data from
the host.

Although in this specific UDA1335H application no
endpoint control properties can be used on the
isochronous adaptive sink endpoint, the descriptors are
still necessary to inform the host about the definition of this
endpoint: isochronous, adaptive, sink, continuous
sampling frequency (at input side of this endpoint) with a
lower boundary of 5 kHz and an upper boundary of
55 kHz.

The audio class specific descriptors can be requested with
the ‘Get Descriptor: configuration request’, which returns
all the descriptors, except the device descriptor.

For each alternate setting with audio, a maximum
bandwidth is claimed as indicated in the standard
isochronous audio data endpoint descriptor
wMaxPacketSize field. To allow a small overshoot in the
number of audio samples per packet, the top sample
frequency of 55 kHz is taken in the calculation of the
bandwidth for each alternate setting. For each alternate
setting, with its own isochronous audio data endpoint
descriptor, wMaxPacketSize field is then defined as
described in Table 6.

Table 6 Audio bandwidth at each audio mode

ALTERNATE

SETTING

1 8-bit PCM, mono 3800
2 8-bit PCM, stereo 7000
3 16-bit PCM, mono 7000
4 16-bit PCM, stereo E000
5 24-bit PCM, mono A800
6 24-bit PCM, stereo 5001

THE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR

FOR THE ISOCHRONOUS DATA SOURCE ENDPOINT

Interface 2 is used for sending isochronous audio data to
the host. It has the same alternate settings as interface 1.

AUDIO MODE

wMaxPacketSize

(HEX)

The input terminals can be defined by means of

wTerminalType.

1998 Aug 28 14

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS
The inputs defined on the UDA1335H are transmitted via

the USB to the host according to the HID class. The host
responds with the appropriate settings via the audio device
class for the audio related parts or via the HID class for the
HID related inputs and outputs of the UDA1335H.

A HID descriptor is necessary to inform the host about the
conception of the user interface. The host communicates
via the HID device driver using either the control pipe or
the interrupt pipe. The UDA1335H is using USB
endpoint 0 (control pipe) to respond to the HID specific
‘Get/Set Report request’ to receive or transmit data from or
to the UDA1335H. The UDA1335H uses the status
interrupt endpoint as interrupt pipe for polling
asynchronous data.

The UDA1335H is a high-speed device. The maximum
transaction size is 64 bytes per USB frame and the polling
rate is defined at a maximum of every 1 ms.

The host requests the configuration descriptor which
includes the standard interface descriptor, the HID
endpoint descriptor and the HID descriptor. The HID
device driver of the host then requests the report
descriptor.

Report descriptors are composed of pieces of information
about the device. Each piece of information is called an
item. All items have a 1-byte prefix that contains the item
tag, type and size. In the UDA1335H only the short item
basic type is used.

The hosts HID device driver will parse the report descriptor
and the defined items. By examining all of these items, the
HID class driver is able to determine the size and
composition of data reports from the device.

The main items of the UDA1335H are input reports. Input
reports are sent via the interrupt pipe (UDA1335H USB
endpoint 3). Input reports can be requested by the host via
the control endpoint (USB endpoint 0).

The UDA1335H supports a maximum of two push-buttons
(six with I2C-bus expanders), which represent a certain
feature of the UDA1335H.

UDA1335H

Controlling the USB APRP

The sound features as defined in the

Definition for Audio Devices”

UDA1335H specific feature registers by the
microcontroller. These specific sound features are:

• Volume control (separate for left and right stereo
channels, no master channel)

• Mute control (only master channel)

• Treble control (only master channel)

• Bass control (only master channel)

• Dynamic bass boost control (only master channel).

These specific features can be activated via the host
(audio device class requests) or via the GP I/O pins (HID
plus audio device class requests). The user is able to
download the necessary configuration data for different
applications (definition of the function of the GP pins, with
or without digital I/O functionality etc.) via the configuration
map. The mapping and control of the standard USB audio
features and UDA1335H specific features is described
below.

Volume control

Volume control is possible via the host or via predefined
GP I/O pins. The setting of 0 dB is always referenced to
the maximum available volume setting. Table 7 gives the
mapping of wVolume value (as defined in the

are mapped on the

Device Class Definition for Audio Devices”

actual volume setting of the USB APRP. When using the
UDA1335H, the range is 0 dB down to −60 dB (in steps of
1 dB) and −∞ dB. Independant control of ‘left’/’right’
volume is possible.

It should be noted that wVolume
used. Values above 0 dB are returned as 0 dB.
The volume value at start-up of the device is defined in the
selected configuration map.

Balance control is possible via the separate volume control
option of both channels. Therefore the characteristics of
the balance control are equal to the volume control
characteristics.

“USB Device Class

) upon the

B7 to B0 are not

LSB

“USB

If pressed by the user the pushbutton will go to its ‘ON’
state, if not pressed the push-button will go back to its
‘OFF’ state.

For more information about the input functions of the
UDA1335H see the application documentation of the
device.

1998 Aug 28 15

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

Table 7 Volume control characteristics

wVOLUME (MSB)

B15 B14 B13 B12 B11 B10 B9 B8

00000000 0 0
11111111 −1 −1
11111110 −2 −2
11111101 −3 −3
11111100 −4 −4
11111011 −5 −5
11111010 −6 −6
11111001 −7 −7
11111000 −8 −8
11110111 −9 −9
11110110 −10 −10

... ... ... ... ... ... ... ... ... ...

11000101 −59 −59
11000100 −60 −60
11000011 −61 −∞
11000010 −62 −∞

... ... ... ... ... ... ... ... ... ...

10000000 −∞ −∞

VOLUME USB

SIDE (dB)

VOLUME USB

APRP (dB)

1998 Aug 28 16

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

Mute control

Mute is one of the sound features as defined in the

Device Class Definition for Audio Devices”

control request data bMute controls the position of the
mute switch. The position can be either on or off. When
bMute is true the feature unit is muted. When bMute is
false the feature unit is not muted.

When the mute is active for the master channel, the value
of the sample is decreased smoothly to zero following a
raised cosine curve. There are 32 coefficients used to step
down the value of the data, each one being used 32 times
before stepping to the next. This amounts to a mute
transition of 23 ms at fs= 44.1 kHz. When the mute is
released, the samples are returned to the full level again
following a raised cosine curve with the same coefficients
being used in reversed order.

Table 8 Treble control characteristics

bTREBLE

B7 B6 B5 B4 B3 B2 B1 B0

00000000 0.00 0
00000001 0.25
00000010 0.50
00000011 0.75
00000100 1.00
00000101 1.25 2
00000110 1.50
00000111 1.75
00001000 2.00
00001001 2.25
00001010 2.50
00001011 2.75
00001100 3.00
00001101 3.25 4

00010101 5.25 6

00011101 7.25 6

00100101 9.25 6

01111111 31.75 6

. The mute

“USB

The mute, on the master channel is synchronized to the
sample clock, so that operation always takes place on
complete samples.

A mute can be given via the host or by pressing a
predefined GP pin.

Treble control

The treble control is available for the master channel of the
UDA1335H. The treble range is from 0 to 6 dB in steps of
2 dB. It should be noted that the negative treble values as
defined in the

Devices”

below 0 dB are returned as 0 dB. The corner frequency is
1500 Hz. Table 8 gives the mapping of the bTreble value
upon the actual treble setting of the USB APRP.

“USB Device Class Definition for Audio

are not supported by the UDA1335H; values

TREBLE USB HOST

(dB)

...

...

...

...

TREBLE USB APRP

UDA1335H

(dB)

1998 Aug 28 17

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

Bass control

The bass control is available for the master channel of the UDA1335H. The bass range is from 0 to approximately 24 dB
in steps of 2 dB. It should be noted that the negative bass values as defined in the

Devices”

Table 9 gives the mapping of the bBass value upon the actual bass setting of the USB APRP.

Table 9 Bass control characteristics

are not supported by the UDA1335H; values below 0 dB are returned as 0 dB. The corner frequency is 75 Hz.

bBASS

B7 B6 B5 B4 B3 B2 B1 B0

00000000 0.00 0
00000001 0.25
00000010 0.50
00000011 0.75
00000100 1.00
00000101 1.25 1.7
00000110 1.50
00000111 1.75
00001000 2.00
00001001 2.25
00001010 2.50
00001011 2.75
00001100 3.00
00001101 3.25 3.6

00010101 5.25 5.4

00011101 7.25 7.4

00100101 9.25 9.4

00101101 11.25 11.3

00110101 13.25 13.3

00111101 15.25 15.2

01000101 17.25 17.3

01001101 19.25 19.2

00111011 21.25 21.2

BASS USB HOST

“USB Device Class Definition for Audio

BASS USB APRP

(dB)

...

...

...

...

...

...

...

...

...

...

(dB)

1998 Aug 28 18

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

bBASS

B7 B6 B5 B4 B3 B2 B1 B0

01010101 23.25 23.2

01100101 25.25 23.2

01101101 27.25 23.2

01110101 29.25 23.2

01111101 31.25 23.2

01111111 31.75 23.2

Dynamic bass boost control

Bass boost is one of the sound features as defined in the

“USB Device Class Definition for Audio Devices”

The bass boost control request databBassBoost controls
the position of the bass boost switch. The position can be
either on or off. When bBassBoost is true the bass boost
is activated. When bBassBoost is false the bass boost is
off.

When clipping prevention is active, the bass is reduced to
avoid clipping with high volume settings. Bass boost is
selectable via the configuration map.

Clipping prevention

When clipping prevention is ON and the sum of bass plus
volume gives clipping, the bass is reduced. When clipping
prevention is ON and the sum of treble plus volume gives
clipping, the treble is reduced. Clipping prevention and
clipping level are selectable via the configuration map.
For more information about clipping prevention and the
clipping level see the application documentation.

De-emphasis

De-emphasis is one of the properties which is not
supported by the USB. De-emphasis for 44.1 kHz can be
predefined in the configuration map selected at start-up of
the UDA1335H.

.

Start-up and configuration of the UDA1335H

S

TART-UP OF THE UDA1335H

After power-on, an internal power-on reset signal becomes
HIGH after a certain RC time (R = 5000 Ω, C = C
During 20 ms after power-on reset the UDA1335H has to
initiate the internal settings. After the power-on reset the
UDA1335H becomes master of the I2C-bus.
The UDA1335H tries to read the eventually connected
I2C-bus EEPROM and if an dedicated EEPROM is
detected, the internal descriptors are overwritten and the
selected port configuration is applied. If no EEPROM is
detected, the UDA1335H tries to read the logic levels of
GP3 and GP4. A choice can be made from four
configuration maps via these two GP pins.

ONFIGURATION SELECTION OF THE UDA1335H VIA A DIODE

C

MATRIX

The UDA1335H uses a configuration map to hold a
number of specific configurable data on hardware,
product, component and USB configuration level.
At start-up, without EEPROM, the UDA1335H will scan the
logic levels of GP3 and GP4. With these two GP pins it is
possible to select one of the four possible configuration
maps which are held in the external (E)PROM. This
selection can be achieved via a diode matrix (see Fig.5).

BASS USB HOST

(dB)

...

...

...

...

...

BASS USB APRP

(dB)

ref

).

1998 Aug 28 19

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

After selecting an internal configuration map the user
cannot change the chosen settings for the GP pins,
internal configuration, descriptors etc.

The UDA1335H supports a maximum of two push-buttons
(six with I2C-bus expanders), which represent a certain
feature of the UDA1335H.

The UDA1335H supports a maximum of three outputs for
e.g. user LEDs.

For more information about the four configuration maps
located in the (E)PROM and the input and output functions
of the UDA1335H see the application documentation.

C

ONFIGURATION OPTIONS OF THE UDA1335H VIA AN

I2C-BUS EEPROM
At start-up, the UDA1335H will address I2C-bus slave

address 0 × A0H and will check the first two byte locations
of the I2C-bus device with 0 × 55H and 0 × AAH. If a match
occurs, the UDA1335H assumes that this I2C-bus device
is an EEPROM which is dedicated to the UDA1335H. It will
then read the configuration map stored in this EEPROM
instead of one of four configuration maps located in the

UDA1335H

firmware of the microcontroller. The layout of the
configuration map is fixed, the values (except
bytes 0 and 1) are user definable. If the user wants to
change e.g. the manufacturer name this can be achieved
via the EEPROM code.

The communication between the UDA1335H and the
external I
protocol given in the Philips specification

how to use it (including specifications)”

ordered using the code 9398 393 40011. The I2C-bus has
two lines; a clock line SCL and a serial data line SDA
(see Fig.6).

2

C-bus device is based on the standard I2C-bus

“The I2C-bus and

, which can be

handbook, full pagewidth

USB-B

connector

5

6

10 nF

3.3 V 3.3 V 3.3 V 3.3 V

22 kΩ

TR3

1.5 kΩ

1
2
3
4

V

10 nF

bus

22 pF 22 pF

22 kΩ

22 kΩ 22 kΩ

KEY 1

SW1

TR1 TR2

22 Ω

22 Ω

KEY 2

SW2

22 kΩ

22 kΩ

GP3
GP4

1

V

bus

1

D2

2

D1

2

22 kΩ

GP5

D−
D+

MGL480

Fig.5 Diode matrix selection.

1998 Aug 28 20

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

SP

t

HD;STA

t

P

SU;STO

t

Sr

UDA1335H

MBC611

f

t

r

t

LOW

t

BUF

t

SU;STA

t

SU;DAT

t

HIGH

t

HD;DAT

t

HD;STA

t

S

C-bus.

2

handbook, full pagewidth

Fig.6 Definition of timing of the I

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1998 Aug 28 21

SDA

P

SCL

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

Table 10 Control options for the UDA1335H via the EEPROM configuration map; note 1

BYTE

(HEX)

0 recognition pattern do not

1 recognition pattern do not

2 clocks control register selection ADC clock source 7 0 = ADC clock from APLL

3 reset generator and

4 power control register

5 ASR control register robust word clock 7 1

AFFECTS COMMENTS BIT VALUE

55H

change it

AAH

change it

1 = ADC clock from OSCAD

divide factor 6 and 5 00 = ADC clock divided-by-1

01 = ADC clock divided-by-2
10 = ADC clock divided-by-4

11 = ADC clock divided-by-8
clock ADAC 4 0
clock 48 MHz internal 3 0
clock recovered PSIE/MMU 2 0
ADC clock 1 0
power on OSCAD 0 0

00H

APLL control register

00H

analog modules

2

serial I

phase inversion (right output) 4 0 = mono phase inversal off

bits per sample modi 3 and 2 00 = reserved

mono or stereo operation 1 0 = mono

ASR register start-up mode 0 1

S-bus output format 6 and 5 00 = I2S-bus

01 = 16-bit LSB

10 = 18-bit LSB

11 = 20-bit LSB

1 = mono phase inversal on

01 = 8-bit audio

10 = 16-bit audio

11 = 24-bit audio

1 = stereo

UDA1335H

1998 Aug 28 22

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

BYTE

(HEX)

6 PGA control register

7 PGA control register

AFFECTS COMMENTS BIT VALUE

reserved 7 X

input terminal 1
(all analog input
topologies)

input terminal 2
(only for analog input
topology 2)

PGA internal setting
(do not change it)

PGA gain selection right
channel

PGA gain selection left channel 2 to 0 000 = −3dB

reserved 7 X
PGA internal setting

(do not change it)
PGA gain selection right

channel

PGA gain selection left channel 2 to 0 000 = −3dB

UDA1335H

60

5 to 3 000 = −3dB

001 = 0 dB

010 = 3 dB

011=9dB

100 = 15 dB

101 = 21 dB

110=27dB

111 = 27 dB

001 = 0 dB

010 = 3 dB

011=9dB

100 = 15 dB

101 = 21 dB

110=27dB

111 = 27 dB

60

5 to 3 000 = −3dB

001 = 0 dB

010 = 3 dB

011=9dB

100 = 15 dB

101 = 21 dB

110=27dB

111 = 27 dB

001 = 0 dB

010 = 3 dB

011=9dB

100 = 15 dB

101 = 21 dB

110=27dB

111 = 27 dB

1998 Aug 28 23

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

BYTE

(HEX)

8 ADIF control register reserved 7 X

9 ADAC feature setting

A ADAC lock mode

AFFECTS COMMENTS BIT VALUE

register

register

number of bits per audio
sample to be transmitted to the
host

mono/stereo selection 4 0 = mono

selection audio input channel 3 0 = digital serial audio input

selection high-pass filter of the
decimation module

2

I

S-bus input serial input format 1 and 0 00 = I2S-bus

selection ADAC mode register 7 0
audio feature mode 6 and 5 11
de-emphasis 4 0 = de-emphasis off

channel manipulation 3 0 = L → L, R → R

synchronous/asynchronous 2 0
mute control 1 1
reset ADAC 0 0
selection ADAC mode register 7 1
digital PLL lock speed 6 and 5 00
digital PLL lock mode 4 1
digital PLL mode 3 and 2 00

2

serial I

S-bus input format 1 and 0 00 = I2S-bus

6 and 5 00 = reserved

2 0 = high-pass filter off

UDA1335H

01 = 8 bits audio samples

10 = 16 bits audio samples

11 = 24 bits audio samples

1 = stereo

1 = analog input

1 = high-pass filter on

01 = 16-bit LSB

10 = 18-bit LSB

11 = 20-bit LSB

1 = de-emphasis on

1=L→R, R →L

01 = 16-bit LSB

10 = 18-bit LSB

11 = 20-bit LSB

1998 Aug 28 24

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

BYTE

(HEX)

B I/O selection register clipping 7 0 = clipping prevention OFF

C output pin function 1 functions are available if
D output pin function 2
E output pin function 3
FI

10 rise time power amplifier, steps

11 time between mute and play,

12 time between mute and

13 selector preferred state (only

14 DBB value steps of 1 dB with

15 start-up volume value in dB volume = −register value

AFFECTS COMMENTS BIT VALUE

1 = clipping prevention ON
expander 6 0 = no I

1= I
selector output (GP2) 5 0 = selector state normal

1 = selector state inverted
mute/standby expander 4 0 = mute

1 = standby
mute/standby USB APRP 3 0 = mute

1 = standby
output pin 3 2 polarity output pins
output pin 2 1 0 = inverted logic
output pin 1 0 1 = normal logic

declared in ADC:

0 = mute LED; 1 = DBB LED

2

S-bus and topology

selection register

output I2S-bus 7 0 = no I2S-bus used

1=I

2

4-pin or 6-pin I

HID usage 5 0 = HID not included

reserved 4 X
topology selection 3 low nibble:

of 20 ms

steps of 1 s

standby, steps of 5 s

applicable in input topology 2)

maximum 255 dB

S-bus 6 only if I2S-bus is used:

0 = 4-pin I2S-bus

1 = 6-pin I2S-bus

1 = HID included

2
1
0

1 = input topology 1

2 = input topology 2

3 = input topology 3

4 = input topology 4

all other values =

input topology 1

0 = terminal Input 1 or terminal

input 2

0 = no DBB active

1 to FF = DBB active

2

C-bus expander used

2

C-bus expander used

2

S-bus used

1998 Aug 28 25

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

BYTE

(HEX)

16 maximum distortion in dB
17 sample frequency LSB
18 mid

19 MSB
1A/1B pointer to device descriptor 0030
1C/1D pointer to configuration

1E/1F pointer to HID descriptor 01F0

20/21 pointer to HID report descriptor 0210

22 number of string pointers

23/24 pointer to string 0 025E
25/26 pointer to string 1 0260
27/28 pointer to string 2 0290

29/2A pointer to string 3 02D0

::

23 + 2N/

24+2N

30 → device descriptor
45 →

AFFECTS COMMENTS BIT VALUE

0045

descriptor

(N + 1) maximum for N is 31

pointer to string N

configuration descriptor
including ADC

32

UDA1335H

1F0 →
210 →

212 →
25E → string 0 language string
260 → string 1 manufacturer string
290 → string 2 product string
2D0 → string 3 serial number

Notes

1. An extensive description of the USB control options is available in the

Devices”

2. The serial number is only supported in the external configuration map and not in the four internal configuration maps.

The general purpose I/O pins (GP0 to GP5) and I

The UDA1335H has 6 General Purpose (GP) I/O pins; these are pins GP0 to GP5. These can be used either for digital
I/O functions or for general purposes.

There are basically three port configurations:

• No digital I/O communication

• 4-pin digital I/O communication

• 6-pin digital I/O communication.

.

and HID descriptors
wDescriptorLength

HID report descriptor

(2)

2

C-bus expander option

“USB Device Class Definition for Audio

1998 Aug 28 26

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

These port configurations can be chosen via the configuration map at start-up of the UDA1335H.
The user can also make use of an I2C-bus expander. The usage of an I2C-bus expander (yes/no) can be indicated via

the configuration map. Some of the supported HID functions are located in the I2C-bus expander. If this expander is not
used, the HID functions normally located in the expander must be declared as “unassigned” in the HID report descriptor.
The bit which indicates if an external expander is used must then be put on zero.

2

Table 11 Definition of the general purpose pins and I

PINS NO I

General purpose I/O

GP5 connect/disconnect connect/disconnect WS input
GP4 HID input 2 BCK output BCK output
GP3 HID input 1 WS output WS output
GP2 selector output DATA output DATA output
GP1 mute or standby output DATA input DATA input
GP0 interrupt input interrupt input BCK input

2

I

C-bus expander; note 7

P0 HID input 3 HID input 3 connect/disconnect
P1 HID input 4 HID input 4 HID input 4
P2 HID input 5 HID input 5 HID input 5
P3 HID input 6 HID input 6 HID input 6
P4 output pin 1 output pin 1 output pin 1
P5 output pin 2 output pin 2 output pin 2
P6 output pin 3 selector output selector output
P7 mute or standby output mute or standby output mute or standby output

2

S-BUS USAGE 4-PIN I2S-BUS USAGE 6-PIN I2S-BUS USAGE

C-bus expander pins; notes 1 to 6

Notes

1. Connect/disconnect: This pin can be used to avoid malfunction during initialisation phase of the UDA1335H. While
initialization takes place, the USB can be kept disconnected while the software of the microcontroller reads in the
configuration map. When the UDA1335H is ready, the USB becomes connected and enumeration can start. Using
the 6-pin I

2. HID input 1 to 6 and interrupt input: A change on the expander can be signalled to the UDA1335H via the interrupt
input. After detecting this signal the UDA1335H will decode the buttons. When no expander is used, the interrupt pin
must be connected to the ground. The HID input pins and the interrupt input pin on the UDA1335H are scanned each
20 ms. If the interrupt in pin indicates a change on the expander, the expander input pins are scanned once. Using
the 6-pin I2S-bus, the interrupt pin is not available and the inputs on the expander are scanned every 20 ms. All input
pins must have a pull-up resistor.

3. Selector output: This pin can be used for switching the audio selector as illustrated in Fig.4. If the configuration map
does not request this output pin, the output is always LOW.

4. Mute output: This output is activated if the isochronous signal is not available during a certain time. The output levels
and the time are programmable in the configuration map.

5. Standby output: This output is activated if the UDA1335H is muted during a certain time. The output levels and the
time are programmable in the configuration map.

6. Output pins 1 to 3: All the output pins are set via the I2C-bus. The function is according the configuration map.

7. For the I2C-bus expander, the PCF8574P remote 8-bit I/O expander for I2C-bus can be used.

1998 Aug 28 27

2

S-bus, the connect/disconnect will be moved to the I2C-bus expander.

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

Filter characteristics

The overall filter characteristic of the UDA1335H in flat mode is given in the Fig.7. The overall filter characteristic of the
UDA1335H includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC
(fs= 44.1 kHz)

MGM110

handbook, full pagewidth

−0

−20

volume

(dB)

−40

−60

−80

−100

−120

−140

−160

10 20 30 40 50 60 70 80 90 1000

f (kHz)

Fig.7 Overall filter characteristics of the UDA1335H.

1998 Aug 28 28

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

DSP extension port

An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1335H supports
the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits.
Using the 4-pin digital I/O-bus the UDA1335H device acts as a master, controlling the BCK and WS signals.

The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the
WS signal does not have a constant time period, but is jittery. Using the 6-pin digital I/O-pins GP2, GP3 and GP4 are
output pins (master) and GP0, GP1 and GP5 are input pins (slave).

The characteristic timing of the I2S-bus input interface is illustrated in Figs 8 and 9.

handbook, full pagewidth

WS

t

r

t

BCK(H)

RIGHT

t

f

t

BCK(L)

t

h;WS

t

s;WS

LEFT

BCK

DATA

T

cy

LSB MSB

t

s;DAT

t

h;DAT

MGK003

Fig.8 Timing of digital I/O input signals.

1998 Aug 28 29

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

21516 1

MSB LSBB2 B15

RIGHT

RIGHT

UDA1335H

215161718 1

LSB

2151617181920 1

B17

RIGHT

MSB B2 B3 B4

LSB

B19

MSB B2 B3 B4 B5 B6

MGK002

ook, full pagewidth

321321

RIGHT

>=8 >=8

LEFT

S-BUS

2

INPUT FORMAT I

MSB B2 MSBLSB LSB MSBB2

LEFT

2

B15

LSB-JUSTIFIED FORMAT 16 BITS

1516 1

MSB LSBB2

215161718 1

LEFT

LSB

B17

LSB-JUSTIFIED FORMAT 18 BITS

MSB B2 B3 B4

2151617181920 1

LEFT

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

MSB B2 B3 B4 B5 B6

Fig.9 Input formats.

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1998 Aug 28 30

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

All digital I/Os

V

I/O

I

O

DC input/output voltage range −0.5 − V
output current V

= 5.0 V −−4mA

DDE

Temperature values

T

j

T

stg

T

amb

junction temperature 0 − 125 °C
storage temperature −55 − +150 °C
operating ambient temperature 0 25 70 °C

Electrostatic handling

V

es

electrostatic handling note 1 −3000 − +3000 V

note 2 −300 − +300 V

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series conductor.

DDE

V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

thj-a

thermal resistance from junction to ambient in free air 48 K/W

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
V
V

DDE
DD
I

supply voltage periphery (I/O) 4.75 5.0 5.25 V
supply voltage (core) 3.0 3.3 3.6 V
DC input voltage range

for D+ and D− 0.0 − V
for VINL and VINR − 0.5V

DD

for digital I/Os 0.0 − V

DD

− V

DDE

V

V

1998 Aug 28 31

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

DC CHARACTERISTICS

= 5.0 V; VDD= 3.3 V; T

V

DDE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDE

V

DDI

V

DDA1

V

DDA2

V

DDA3

V

DDO

V

DDX

I

DDE

I

DDI

I

DDA1

I

DDA2

I

DDA3

I

DDO

I

DDX

P

tot

P

ps

digital supply voltage periphery 4.75 5.0 5.25 V
digital supply voltage core 3.0 3.3 3.6 V
analog supply voltage 1 3.0 3.3 3.6 V
analog supply voltage 2 3.0 3.3 3.6 V
analog supply voltage 3 3.0 3.3 3.6 V
operational amplifier supply voltage 3.0 3.3 3.6 V
crystal oscillator supply voltage 3.0 3.3 3.6 V
digital supply current periphery note 1 − 3.7 − mA
digital supply current core − 39.0 − mA
analog supply current 1 − 3.6 − mA
analog supply current 2 − 8.0 − mA
analog supply current 3 − 0.9 9.0
operational amplifier supply current − 3.0 − mA
crystal oscillator supply current − 1.2 13.0
total power dissipation − 200 − mW
total power dissipation in power

saving mode

amb

=25°C; f

= 48 MHz; fs= 44.1 kHz; unless otherwise specified.

osc

note 4 − 1.2 − mW

(2)

(3)

mA

mA

Inputs/outputs D+ and D−

V

I

V

O(H)

V

O(L)

 high impedance data line output

I

LO

static DC input voltage −0.5 − V
static DC output voltage HIGH RL=15kΩ

static DC output voltage LOW RL=15kΩ

leakage current

V

I(diff)

V

CM(diff)

V

SE(R)(th)

differential input sensitivity 0.2 −− V
differential common mode range 0.8 − 2.5 V
single-ended receiver threshold

voltage

C

IN

transceiver input capacitance pin to GND −− 20 pF

connected to GND

connected to V

DD

DDI

V

2.8 − 3.6 V

−− 0.3 V

−− 10 µA

0.8 − 2.0 V

1998 Aug 28 32

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital input pins

V

IL

V

IH

I

 input leakage current −− 1 µA

LI

C

I

LOW-level input voltage −− 0.3V
HIGH-level input voltage 0.7V

− V

DDE

DDE

DDE

input capacitance −− 5pF

PGA and ADC

V

ref(AD)

V

ref(ADC)(pos)

reference voltage PGA and ADC − 0.5V
positive reference voltage of the

− V

DDA2

DDA2

− V

− V

ADC

V

ref(ADC)(neg)

negative reference voltage of the

− 0.0 − V

ADC

V

I(PGA)

DC input voltage VINL and VINR of

− 0.5V

DDA2

− V

the PGA

R

I(PGA)

DC input resistance at VINL and

− 12.5 − kΩ

VINR of the PGA

V
V

Filter stream DAC

V

ref(DA)

V

O(CM)

R

O(VOUT)

reference voltage DAC − 0.5V
common mode output voltage − 0.5V
output resistance at VOUTL and

− 11 −Ω

DDA1
DDA1

− V

− V

VOUTR

R

O(L)

C

O(L)

output load resistance 2.0 −− kΩ
output load capacitance −− 50 pF

Notes

1. This value depends strongly on the application. The specified value is the typical value obtained using the application
diagram as illustrated in Fig.10.

2. At start-up of the OSCAD oscillator.

3. At start-up of the OSC48 oscillator.

4. Exclusive the I

current which depends on the components connected to the I/O pins.

DDE

1998 Aug 28 33

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

AC CHARACTERISTICS

= 5.0 V; V

V

DDE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Driver characteristics D+ and D- (full-speed mode)

f

o(s)

t

r

t

f

t

rf(m)

V

cr

R

o(drive)

Data source timings D+ and D- (full-speed mode)

f

i(s)

f

fs(D)

t

fr(D)

t

J1(diff)

t

J2(diff)

t

W(EOP)

t

EOP(diff)

t

JR1

t

JR2

t

EOPR1

t

EOPR2

= 3.3 V; T

DDI

amb

=25°C; f

= 48 MHz; fs= 44.1 kHz; unless otherwise specified.

osc

audio sample output frequency 5 − 55 kHz
rise time CL=50pF 4 − 20 ns
fall time CL=50pF 4 − 20 ns
rise/fall time matching (tr/tf)90−110 %
output signal crossover voltage 1.3 − 2.0 V
driver output resistance steady-state drive 28 − 43 Ω

audio sample input frequency 5 − 55 kHz
full speed data rate 11.97 12.00 12.03 Mbits/s
frame interval 0.9995 1.0000 1.0005 ms
source differential jitter to next

−3.5 +0.0 +3.5 ns

transition
source differential jitter for

−4.0 +0.0 +4.0 ns

paired transitions
source end of packet width 160 − 175 ns
differential to end of packet

−2.0 − +5.0 ns

transition skew
receiver data jitter tolerance to

−18.5 0.0 +18.5 ns

next transition
receiver data jitter tolerance for

−9.0 0.0 +9.0 ns

paired transitions
end of packet width at receiver

40 −− ns

must reject as end of packet
end of packet width at receiver

82 −− ns

must accept as end of packet

Serial input/output data timing

f

s

f

i(WS)

t

r

t

f

t

BCK(H)

t

BCK(L)

t

s;DAT

t

h;DAT

t

s;WS

t

h;WS

system clock frequency − 12 − MHz
word selection input frequency 5 − 55 kHz
rise time −−20 ns
fall time −−20 ns
bit clock HIGH time 55 −− ns
bit clock LOW time 55 −− ns
data set-up time 10 −− ns
data hold time 20 −− ns
word selection set-up time 20 −− ns
word selection hold time 10 −− ns

1998 Aug 28 34

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SDA and SCL lines (standard mode I2C-bus)

f

SCL

t

BUF

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

t

SU;STO

t

HD;DAT

t

SU;DAT

t

r

t

f

C

L(bus)

Oscillator 1 (system clock)

f

osc

δ duty factor − 50 − %
g

m

R

o

C

i(XTAL1a)

C

i(XTAL2a)

I

start

Oscillator 2 (for ADC clock)

f

osc

δ duty cycle − 50 − %
g

m

R

o

C

i(XTAL1b)

C

i(XTAL2b)

I

start

SCL clock frequency 0 − 100 kHz
bus free time between a STOP

4.7 −− µs

and START condition
hold time (repeated) START

4.0 −− µs

condition
LOW period of the SCL clock 4.7 −− µs
HIGH period of the SCL clock 4.0 −− µs
set-up time for a repeated

4.7 −− µs

START condition
set-up time for STOP condition 4.0 −− µs
data hold time 5.0 − 0.9 µs
data set-up time 250 −− ns
rise time of both SDA and SCL

−−1000 ns

signals
fall time of both SDA and SCL

−−300 ns

signals
capacitive load for each bus line −−400 pF

oscillator frequency − 48 − MHz

transconductance 12.8 22.1 30.2 mS
output resistance 0.6 1.1 2.3 kΩ
parasitic input capacitance

4.5 4.8 5.2 pF

XTAL1a
parasitic input capacitance

4.1 4.6 5.0 pF

XTAL2a
start-up current 3.7 7.6 13.0 mA

oscillator frequency 8.192 − 14.08 MHz

transconductance 8.1 13.6 18.1 mA/V
output resistance 1.3 2.0 4.0 kΩ
parasitic input capacitance

5.0 5.4 5.7 pF

XTAL1b
parasitic input capacitance

4.1 4.6 5.0 pF

XTAL2b
start-up current 2.4 5.0 8.4 mA

1998 Aug 28 35

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog PLL (for ADC clock)

f

clk(PLL)

δ duty factor − 50 − %
t

strt(PO)

Power-on reset

t

su(PO)

PGA and ADC

V

i(FS)(rms)

C

i(PGA)

(THD + N)/S total harmonic distortion plus

S/N signal to noise ratio V

α

ct

f

s

OL

(FS)

PLL clock frequency 8.1920 11.2896 12.2880 MHz

start-up time after power-on −−10 ms

power-on set-up-time note 1 5C

full-scale input voltage
(RMS value)

PGA gain = −3dB − 1414
PGA gain=0dB − 1000 − mV

ref

(2)

−− ms

(5)

− mV

PGA gain=3dB − 708 − mV
PGA gain=9dB − 355 − mV
PGA gain = 15 dB − 178 − mV
PGA gain = 21 dB − 89 − mV
PGA gain = 27 dB − 44 − mV

input capacitance of the PGA −−20 pF

f

= 44.1 kHz at input

s

noise-to-signal ratio

signal of 1 kHz; PGA
gain = 0 dB; note 3

V

(0 dB) (1.0 V RMS) −−85 −80 dB

i

− 0.0056 0.01 %

Vi(−60 dB) −−30 −20 dB

− 3.2 10.0 %

= 0.0 V 90 95 − dBA

i

crosstalk between channels PGA gain=0dB − 100 − dB
sample frequency (128fs) 0.640 − 7.04 MHz
full-scale digital output level PGA gain=0dB;

−−2.0 − dB

Vi= 1 V (RMS)

1998 Aug 28 36

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Filter stream DAC

RES resolution 16 −− bits
V

o(FS)(rms)

SVRR supply voltage ripple rejection at

∆V

 channel unbalance maximum volume − 0.03 − dB

o

α

ct

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio at bipolar

full-scale output voltage

VDD= 3.3 V − 0.66 − V

(RMS value)

f

V

DDA

and V

DDO

ripple

V

ripple(p-p)

= 1 kHz;

= 0.1 V

− 60 − dB

crosstalk between channels RL=5kΩ−95 − dB

f

= 44.1 kHz;

s

noise-to-signal ratio

zero

RL=5kΩ; note 4

at input signal of
1 kHz (0 dB)

at input signal of
1 kHz (−60 dB)

A-weighting at code
0000H

−−90 −80 dB

− 0.0032 0.01 %

−−30 −20 dB

− 3.2 10 %
90 95 − dB

Notes

1. Strongly depends on the external decoupling capacitor connected to V

2. C

in µF.

ref

ref(DA)

.

3. Measured with the APLL as ADC clock source.

4. Measured with I2S-bus input as digital source.

5. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not
be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping.

APPLICATION INFORMATION

The UDA1335H can only be used in combination with an external (E)PROM. This (E)PROM can be connected to the
port pins (P0 and P2) of the UDA1335H and must contain the firmware for the microcontroller. The UDA1335H will be

2

delivered with standard USB compliant firmware. The I

C-bus EEPROM is optional and can be used to configure client

specific configurations and descriptors.
More information about the firmware, descriptors and configurations can be obtained from several application notes.

1998 Aug 28 37

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

handbook, full pagewidth

BCKI

digital

input

WSI

X4

1

1

2

2

3

3

45

4

L1

C15

10 nF
(50 V)

8
7
6

playback

recording

digital

input

V

USB

C16
10 nF
(50 V)

DI

BCK

WS

DA

analog

input

recording

10 nF (63 V)

C18
22 pF
(63 V)

C44

+V

C

R48

1.5 kΩ

C17
22 pF
(63 V)

47 µF (16 V)

47 µF (16 V)

L5

1.5 µH

C22

UDA1335H

+V

A

R35
1 Ω

C34

47 µF

(16 V)

C38

100 nF

(63 V)

V

V

DDA1

SSA1

3839

GP0/BCKI

17

GP5/WSI

15

GP1/DI

13

BCK

61

WS

59

DA

57

R7

D−

1

VINR

VINL

XTAL2b

6

D+

8

47

43

26

UDA1335H

22 Ω

R16

22 Ω

C8

47 µF
(16 V)

100 nF

(63 V)

V

SSA2

C32

C21

+V

A

R27
1 Ω

V

DDA2

4244

C38

12 pF (63 V)

C37

4.7 pF (50 V)

ADC XTAL

V

V

A(ext)

D(ext)

L8

BLM32A07

L7

BLM32A07

L6

BLM32A07

GND

C47
100 µF
(16 V)

C46
100 µF
(16 V)

Fig.10 Application diagram (continued in Fig.11).

1998 Aug 28 38

C5
18 pF
(50 V)

C45
100 µF
(16 V)

+V

+V

+V

X1 48 MHz

XTAL1b

XTAL2a
XTAL1a

C6
18 pF
(50 V)

A

C

D

MBK839

25

53
54

10

9

11

V

SSI

C25

100 nF
(63 V)

C24

100 nF

(63 V)

V

DDI

L2
BLM32A07

R17
1 Ω

+V

C

V

SSE

C26

100 nF

(63 V)

C27

100 nF

(63 V)

12

V

DDE

L3
BLM32A07

R25
1 Ω

+V

D

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

handbook, full pagewidth

C7

47 µF

(16 V)

C19

100 nF

(63 V)

V

SSA3

5255

+V

A

R10
1 Ω

V

DDA3

UDA1335H

C11

100 nF

(63 V)

+V

A

R8
1 Ω

VRPVRN

5149

P0.0

56

P0.1

58

P0.2

60

P0.3

62

P0.4

64

P0.5

3

P0.6

5

P0.7

7

ALE

50

P2.0

14

P2.1

16

P2.2

18

P2.3

20

P2.4

22

P2.5

23

PSEN

31

EA

48

21
19

40
41

37

34

+V

SDA
SCL
V

ref(DA)

V

ref(AD)

VOUTR

VOUTL

R20

D

1 Ω

47 µF (16 V)

47 µF (16 V)

C35

C48

C36
100 nF
(63 V)

C28
100 nF
(63 V)

D

7

18

D

6

17

D

5

14

D

4

13

D

3

8

2
1
0

V

74HCT373D

7
4
3

11
1

A0

1

A1

2

A2

3

SS

4

C31
47 µF
(16 V)

analog
output

playback

D1

R28

4.7 kΩ

D4

PCF85116-3

D
D
D

LE

OE

19
16
15
12

9
6
5
2

20

10

C29
100 nF
(63 V)

Q
Q
Q
Q
Q
Q
Q
Q
V

GND

8
7
6
5

UDA1335H

R39
10 kΩ

A0

10

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

A9
A10
A11
A12
A13

OE
CE

PGM

V

PP

+V

D

1

2

(I

25
24
21
23
2
26

22
20
27
1

2

C-bus)

D2

EEPM27128

7
6
5
4
3
2
1
0
CC

+V

D

100 nF

C24

(50 V)

V
PTC

SCL
SDA

C41
47 µF
(16 V)

DD

+V

R38
10 kΩ

D

O0

11

O1

12

O2

13

O3

15

O4

16

O5

17

O6

18

O7

19

V

CC

C25

+V

100 nF

(50 V)

D

28

GND

14

GP4/BCKO

33

V

SSO

100 nF

(63 V)

47 µF
(16 V)

C33

C39

2

GP3/WSO

1

GP2/DO

63

RTCB

36

TC

35

SHTCB

4

32

V

DDO

R43
1 Ω

+V

A

28

24

V

V

SSX

DDX

C28

100 nF

L13

(63 V)

BLM32A07

C18

100 nF

R26

(63 V)

1 Ω

+V

C

MBK840

BCKO
WSO
DO

digital
output

playback

Fig.11 Application diagram (continued from Fig.10).

1998 Aug 28 39

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

51 33

52

32

Z

A

E

UDA1335H

SOT319-2

pin 1 index

64

1

w M

b

0.50

0.35

p

D

H

D

0 5 10 mm

(1)

(1) (1)(1)

D

0.25

0.14

20.1

19.9

14.1

13.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

19

Z

D

scale

eH

H

24.2

1

23.6

20

D

B

e

w M

b

p

E

18.2

17.6

H

E

v M

A

v M

B

LL

p

1.0

0.6

A

2

A

E

A

1

detail X

Zywv θ

Z

E

D

1.2

0.2 0.10.21.95

0.8

1.2

0.8

(A )

3

θ

L

p

L

o

7

o

0

OUTLINE

VERSION

SOT319-2

IEC JEDEC EIAJ

REFERENCES

1998 Aug 28 40

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“Data Handbook IC26; Integrated Circuit Packages”

our
(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the

IC26; Integrated Circuit Packages; Section: Packing
Methods”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

.

“Data Handbook

UDA1335H

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Aug 28 41

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio

UDA1335H

Playback Recording Peripheral (APRP)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Aug 28 42

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)

NOTES

UDA1335H

1998 Aug 28 43

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

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254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545102/750/01/pp44 Date of release: 1998 Aug 28 Document order number: 9397 750 03922