Datasheet UDA1330ATS-N2, UDA1330ATS-N1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1999 Dec 20
File under Integrated Circuits, IC01

2000 Apr 18

INTEGRATED CIRCUITS

UDA1330ATS

Low-cost stereo filter DAC

2000 Apr 18 2

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

FEATURES
General

• Low power consumption

• Power supply voltage from 2.7 to 5.5 V

• Selectable controlvia L3 microcontroller interface or via

static pin control

• System clock frequencies of 256fs, 384fsand 512f

s

selectable via L3 interface or 256fsand 384fs via static
pin control

• Supports sampling frequencies (fs) from 16 to 55 kHz

• Integrated digital filter plus non inverting

Digital-to-Analog Converter (DAC)

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

• Small package size (SSOP16)

• TTL tolerant input pads

• Pin and function compatible with the UDA1320ATS.

Multiple format input interface

• L3 mode: I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible

• Static pin mode: I2S-bus and LSB-justified
16, 18 and 20 bits format compatible

• 1fsinput format data rate.

DAC digital sound processing

• Digital logarithmic volume control in L3 mode

• Digital de-emphasis for 32, 44.1 and 48 kHz sampling

frequenciesinL3 mode or 44.1 kHz sampling frequency
in static pin mode

• Soft mute control both in static pin mode and L3 mode.

Advanced audio configuration

• Stereo line output (volume control in L3 mode)

• High linearity, wide dynamic range and low distortion.

APPLICATIONS

• PC audio applications

• Car radio applications.

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing
bitstream conversion techniques.

The UDA1330ATS supports the I2S-bus data format with
wordlengths of upto20 bits, the MSB-justified dataformat
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.

The UDA1330ATS canbe used in two modes: L3 mode or
the static pin mode.

In the L3 mode, all digital sound processing features must
becontrolled via the L3 interface, includingtheselectionof
the system clock setting.

In the two static modes, the UDA1330ATS can be
operated in the 256fsand 384fs system clock mode.
Muting, de-emphasis for 44.1 kHz and four digital input
formats (I2S-bus or LSB-justified 16, 18, and 20 bits) can
be selected via static pins. The L3 interface cannot be
used in this application mode, so volume control is not
available in this mode.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1330ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2000 Apr 18 3

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

QUICK REFERENCE DATA

Note

1. The output voltage scales linearly with the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

DAC analog supply voltage 2.7 5.0 5.5 V

V

DDD

digital supply voltage 2.7 5.0 5.5 V

I

DDA

DAC analog supply current V

DDA

= 5.0 V
operating − 9.5 − mA
power-down − 400 −µA

V

DDA

= 3.3 V
operating − 7.0 − mA
power-down − 250 −µA

I

DDD

digital supply current V

DDD

= 5.0 V − 5.5 − mA

V

DDD

= 3.3 V − 3.0 − mA

T

amb

ambient temperature −40 − +85 °C

Digital-to-analog converter (V

DDA=VDDD

= 5.0 V)

V

o(rms)

output voltage (RMS value) note 1 − 1.45 − V

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB −−90 −85 dB
at −60 dB; A-weighted −−40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted − +100 −95 dB

α

cs

channel separation − 100 − dB

Digital-to-analog converter (V

DDA=VDDD

= 3.3 V)

V

o(rms)

output voltage (RMS value) note 1 − 1.0 − V

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB −−85 − dB
at −60 dB; A-weighted −−38 − dB

S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB

α

cs

channel separation − 100 − dB

Power dissipation

P power dissipation playback mode

V

DDA=VDDD

= 5.0 V − 75 − mW

V

DDA=VDDD

= 3.3 V − 33 − mW

2000 Apr 18 4

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGL401

DAC

UDA1330ATS

NOISE SHAPER

INTERPOLATION FILTER

VOLUME/MUTE/DE-EMPHASIS

CONTROL

INTERFACE

14

15

DAC

6

DIGITAL INTERFACE

8

16

9

10

3

2

1

4

5

11

7

13 12

VOUTR

BCK

V

SSA

WS

VOUTL

DATAI

V

DDA

V

DDD

V

ref(DAC)

V

SSD

APPL0

SYSCLK

APPL1

APPSEL

APPL2
APPL3

Fig.1 Block diagram.

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input
WS 2 word select input
DATAI 3 data input
V

DDD

4 digital supply voltage

V

SSD

5 digital ground

SYSCLK 6 system clock input: 256f

s

, 384f

s

and 512f

s

APPSEL 7 application mode select input
APPL3 8 application input 3
APPL2 9 application input 2
APPL1 10 application input 1
APPL0 11 application input 0
V

ref(DAC)

12 DAC reference voltage

V

DDA

13 analog supply voltage for DAC
VOUTL 14 left channel output
V

SSA

15 analog ground
VOUTR 16 right channel output

Fig.2 Pin configuration.

handbook, halfpage

UDA1330ATS

MGL402

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

VOUTRBCK
V

SSA

WS

VOUTL

DATAI

V

DDA

V

DDD

V

ref(DAC)

V

SSD

APPL0SYSCLK
APPL1APPSEL
APPL2APPL3

2000 Apr 18 5

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

FUNCTIONAL DESCRIPTION
System clock

The UDA1330ATS operates in slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (f

sys

) is
selectable and depends on the application mode. The
options are: 256fs, 384fsand 512fs for the L3 mode and
256fsor 384fs for the static pin mode. The system clock
must be locked in frequency to the digital interface input
signals.

The UDA1330ATS supports sampling frequencies from
16 to 55 kHz.

Application modes

The application mode can be set with the three-level
pin APPSEL (see Table 1):

• L3 mode

• Static pin mode with f

sys

= 384f

s

• Static pin mode with f

sys

= 256fs.

Table 1 Selecting application mode and system clock

frequency via pin APPSEL

The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).

Table 2 Functions of application input pins

For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1to HIGH; setting pin APPL1to LOW will disable
de-emphasis.

In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.

Multiple format input interface

D

ATA FORMATS

Thedigitalinterface of the UDA1330ATS supportsmultiple
format inputs (see Fig.3).

Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all

LSB-justified formats.
The BCK clock can be up to 64fs, or in other words the

BCK frequency is 64 times the Word Select (WS)
frequency or less: f

BCK

≤ 64 × fWS.

Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.

The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes

L3 MODE
This mode supports the following input formats:

• I2S-bus format with data word length of up to 20 bits

• MSB-justified format with data word length up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

STATIC PIN MODE
This mode supports the following input formats:

• I2S-bus format with data word length of up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).

Table 3 Input format selection using SF0 and SF1

VOLTAGE ON

PIN APPSEL

MODE f

sys

V

SSD

L3 mode 256fs, 384fsor 512f

s

0.5V

DDD

static pin mode

384f

s

V

DDD

256f

s

PIN

FUNCTION

L3 MODE STATIC PIN MODE

APPL0 TEST MUTE
APPL1 L3CLOCK DEEM
APPL2 L3MODE SF0
APPL3 L3DATA SF1

FORMAT SF0 SF1

I

2

S-bus 0 0
LSB-justified 16 bits 0 1
LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1

2000 Apr 18 6

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Interpolation filter (DAC)

Thedigital filter interpolates from1fsto 128fsbycascading
a recursive filter and an FIR filter (see Table 4).

Table 4 Interpolation filter characteristics

Noise shaper

The 3rd-order noise shaper operates at 128f

s

. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream DAC (FSDAC).

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC scales linearly with the
power supply voltage.

Pin compatibility

In the L3 mode the UDA1330ATS can be used on boards
that are designed for the UDA1320ATS.

Remark: It should be noted that the UDA1330ATS is
designed for 5 V operation while the UDA1320ATS is
designed for 3 V operation. This means that the
UDA1330ATS can be used with the UDA1320ATS supply
voltage range, but the UDA1320ATS can not beused with
the 5 V supply voltage.

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f

s

±0.1

Stop band >0.55f

s

−50

Dynamic range 0 to 0.45f

s

108

2000 Apr 18 7

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

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16

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

WS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19

LSB

16

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB MSBB2

21> = 812 3

LEFT

I

2

S-BUS FORMAT

WS

BCK

DATA

RIGHT

3

> = 8

MSB B2

MBL140

16

MSB

B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

WS

BCK

DATA

RIGHT

15 2 1

B15

LSB

16

MSB B2

15 2 1

B15 LSB

16

MSB B2 B3 B4

LEFT

LSB-JUSTIFIED FORMAT 18 BITS

WS

BCK

DATA

RIGHT

1518 17 2 1

MSB B2 B3 B4

B17

LSB

16 1518 17 2 1

B17 LSB

MSB-JUSTIFIED FORMAT

WS

LEFT

RIGHT

321321

MSB B2 MSBLSB LSB MSB B2B2

> = 8 > = 8

BCK

DATA

Fig.3 Digital interface input format data format.Fig.3 Digital interface input format data format.

2000 Apr 18 8

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

L3 INTERFACE

The following system and digital sound processing
features can be controlled in the L3 mode of the
UDA1330ATS:

• System clock frequency

• Data input format

• De-emphasis for 32, 44.1 and 48 kHz

• Volume

• Soft mute.

Theexchange of dataand control information betweenthe
microcontroller and the UDA1330ATS is accomplished
through a serial interface comprising the following signals:

• L3DATA

• L3MODE

• L3CLOCK.

Information transfer through the microcontroller bus is
organized in accordance with the L3 interface format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.

Address mode

The address mode (see Fig.4) is required to select a
device communicating via the L3 interface and to define
the destination registers for the data transfer mode.

Data bits 7 to 2 represent a 6-bit device address where
bit 7 is the MSB. The address of the UDA1330ATS is
000101 (bit 7 to bit 2). If the UDA1330ATS receives a
different address, it will deselect its microcontroller
interface logic.

Data transfer mode

The selected address remains active during subsequent
data transfers until the UDA1330ATS receives a new
address command.

The fundamental timing of data transfers (see Fig.5) is
essentially the same as the address mode. The maximum
input clock frequency and data rate is 64fs.

Data transfer can only be in one direction, consisting of
input to the UDA1330ATS to program sound processing
andother functional features. Alldata transfersareby 8-bit
bytes. Data will be stored in the UDA1330ATS after
reception of a complete byte.

A multibyte transfer is illustrated in Fig.6.

Registers

The sound processing and other feature values are stored
inindependent registers. The first selectionof theregisters
is achieved by the choice of data type that is transferred.
Thisis performed intheaddress mode usingbit 1 and bit 0
(see Table 5).

Table 5 Selection of data transfer

The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) represent the value that is placed in the
selected registers.

The ‘status’ settings are given in Table 6 and the ‘data’
settings are given in Table 7.

BIT 1 BIT 0 TRANSFER

0 0 data (volume, de-emphasis, mute)
0 1 not used
1 0 status (system clock frequency,

data input format)

1 1 not used

2000 Apr 18 9

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

t

h(L3)A

t

h(L3)DA

t

su(L3)DA

T

cy(CLK)(L3)

BIT 0

L3MODE

L3CLOCK

L3DATA

BIT 7

MGL723

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

su(L3)A

t

h(L3)A

Fig.4 Timing address mode.

handbook, full pagewidth

t

stp(L3)

t

stp(L3)

t

su(L3)D

t

su(L3)DA

t

h(L3)DA

t

h(L3)D

MGL882

T

cy(CLK)L3

L3MODE

L3CLOCK

t

CLK(L3)H

t

CLK(L3)L

BIT 0

L3DATA

WRITE

BIT 7

Fig.5 Timing data transfer mode.

2000 Apr 18 10

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

t

stp(L3)

address

L3DATA

L3CLOCK

L3MODE

addressdata byte #1 data byte #2

MGL725

Fig.6 Multibyte data transfer.

Programming the features

When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.

Table 6 Data transfer of type ‘status’

When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.

Table 7 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 0 SC = system clock frequency (2 bits); see Table 8

IF = data input format (3 bits); see Table 9

10000000not used

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 VC = volume control (6 bits); see Table 11
01000000not used
1 0 0 DE1 DE0 MT 0 0 DE = de-emphasis (2 bits); see Table 10

MT = mute (1 bit); see Table 12

11000001default setting

2000 Apr 18 11

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

SYSTEM CLOCK FREQUENCY
The system clock frequency is a 2-bit value to select the

external clock frequency.

Table 8 System clock settings

DATA FORMAT
The data format is a 3-bit value to select the used data

format.

Table 9 Data input format settings

DE-EMPHASIS
De-emphasis is a 2-bit value to enable the digital

de-emphasis filter.

Table 10 De-emphasis settings

VOLUME CONTROL
The volume control is a 6-bit value to program the volume

attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.

Table 11 Volume settings

MUTE
Mute is a 1-bit value to enable the digital mute.

Table 12 Mute setting

SC1 SC0 FUNCTION

0 0 512f

s

0 1 384f

s

1 0 256f

s

1 1 not used

IF2 IF1 IF0 FORMAT

000I

2

S-bus
0 0 1 LSB-justified 16 bits
0 1 0 LSB-justified 18 bits
0 1 1 LSB-justified 20 bits
1 0 0 MSB-justified
1 0 1 not used
1 1 0 not used
1 1 1 not used

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :

110011

−51

110100
110101

−52

110110
110111

−54

111000
111001

−57111010
111011
111100

−60
111101

111110

−∞

111111

MT FUNCTION

0 no muting
1 muting

2000 Apr 18 12

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

4. Short-circuit test at T

amb

=0°C and V

DDA

= 3 V. DAC operation after short-circuiting cannot be warranted.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

digital supply voltage note 1 − 6.0 V

V

DDA

analog supply voltage note 1 − 6.0 V

T

xtal(max)

maximum crystal temperature − 150 °C

T

stg

storage temperature −65 +125 °C

T

amb

ambient temperature −40 +85 °C

V

es

electrostatic handling voltage note 2 −3000 +3000 V

note 3 −250 +250 V

I

sc(DAC)

short-circuit current of DAC note 4

output short-circuited to V

SSA(DAC)

− 450 mA

output short-circuited toV

DDA(DAC)

− 300 mA

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 190 K/W

2000 Apr 18 13

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

DC CHARACTERISTICS

V

DDD=VDDA

= 5.0 V; T

amb

=25°C; RL=5kΩ; all voltages referenced to ground (pins V

SSA

and V

SSD

); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

DAC analog supply voltage note 1 2.7 5.0 5.5 V

V

DDD

digital supply voltage note 1 2.7 5.0 5.5 V

I

DDA

DAC analog supply current V

DDA

= 5.0 V
operating − 9.5 − mA
power-down − 400 −µA

V

DDA

= 3.3 V
operating − 7.0 − mA
power-down − 250 −µA

I

DDD

digital supply current V

DDD

= 5.0 V − 5.5 − mA

V

DDD

= 3.3 V − 3.0 − mA

Power dissipation

P power dissipation playback mode

V

DDA=VDDD

= 5.0 V − 75 − mW

V

DDA=VDDD

= 3.3 V − 33 − mW
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2)
V

IH

HIGH-level input voltage V

DDD

= 5.0 V 2.2 −−V

V

DDD

= 3.3 V 1.45 −−V

V

IL

LOW-level input voltage V

DDD

= 5.0 V −−0.8 V

V

DDD

= 3.3 V −−0.5 V

I

LI

 input leakage current −−1µA

C

i

input capacitance −−10 pF

Three-level input: APPSEL

V

IH

HIGH-level input voltage 0.9V

DDD

− V

DDD

+ 0.5 V

V

IM

MIDDLE-levelinput voltage 0.4V

DDD

− 0.6V

DDD

V

V

IL

LOW-level input voltage −0.5 − +0.1V

DDD

V

2000 Apr 18 14

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Notes

1. All supply connections must be made to the same external power supply unit.

2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between

2.7 and 4.5 V.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

AC CHARACTERISTICS

fi= 1 kHz; T

amb

=25°C; RL=5kΩ; all voltages referenced to ground (pins V

SSA

and V

SSD

); unless otherwise specified.

DAC

V

ref(DAC)

reference voltage with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

I

o(max)

maximum output current (THD + N)/S < 0.1%;

RL=5kΩ

− 0.36 − mA

R

o

output resistance − 0.15 2.0 Ω

R

L

load resistance 3 −−kΩ

C

L

load capacitance note 3 −−50 pF

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Digital-to-analog converter (V

DDA=VDDD

= 5.0 V)

V

o(rms)

output voltage (RMS value) 1.45 − V

∆V

o

unbalance between channels 0.1 − dB

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB −90 −85 dB
at −60 dB; A-weighted −40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted +100 −95 dB

α

cs

channel separation 100 − dB

Digital-to-analog converter (V

DDA=VDDD

= 3.3 V)

V

o(rms)

output voltage (RMS value) 1.0 − V

∆V

o

unbalance between channels 0.1 − dB

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB −85 − dB
at −60 dB; A-weighted −38 − dB

S/N signal-to-noise ratio code = 0; A-weighted 100 − dB

α

cs

channel separation 100 − dB

PSRR power supply ripple rejection f

ripple

= 1 kHz;

V

ripple

= 100 mV (p-p)

60 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Apr 18 15

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

TIMING

V

DDD=VDDA

= 4.5 to 5.5 V; T

amb

= −40 to +85 °C; RL=5kΩ; all voltages referenced to ground (pins V

SSA

and V

SSD

);

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock (see Fig.7)

T

sys

system clock cycle time f

sys

= 256f

s

78 88 244 ns

f

sys

= 384f

s

52 59 162 ns

f

sys

= 512f

s

39 44 122 ns

t

CWL

LOW-level system clock pulse width f

sys

< 19.2 MHz 0.3T

sys

− 0.7T

sys

ns

f

sys

≥ 19.2 MHz 0.4T

sys

− 0.6T

sys

ns

t

CWH

HIGH-level system clock pulse width f

sys

< 19.2 MHz 0.3T

sys

− 0.7T

sys

ns

f

sys

≥ 19.2 MHz 0.4T

sys

− 0.6T

sys

ns
Digital interface (see Fig.8)
T

cy(BCK)

bit clock cycle time 300 −−ns

t

BCKH

bit clock HIGH time 100 −−ns

t

BCKL

bit clock LOW time 100 −−ns

t

r

rise time −−20 ns

t

f

fall time −−20 ns

t

su(DATAI)

data input set-up time 20 −−ns

t

h(DATAI)

data input hold time 0 −−ns

t

su(WS)

word select set-up time 20 −−ns

t

h(WS)

word select hold time 10 −−ns
Control interface L3 mode (see Figs 4 and 5)
T

cy(CLK)L3

L3CLOCK cycle time 500 −−ns
t

CLK(L3)H

L3CLOCK HIGH time 250 −−ns
t

CLK(L3)L

L3CLOCK LOW time 250 −−ns
t

su(L3)A

L3MODE set-up time for address mode 190 −−ns
t

h(L3)A

L3MODE hold time for address mode 190 −−ns
t

su(L3)D

L3MODE set-up time for data transfer

mode

190 −−ns

t

h(L3)D

L3MODE hold time for data transfer

mode

190 −−ns

t

su(L3)DA

L3DATA set-up time fordata transferand

address mode

190 −−ns

t

h(L3)DA

L3DATA hold time for data transfer and

address mode

30 −−ns

t

stp(L3)

L3MODE stop time for data transfer

mode

190 −−ns

2000 Apr 18 16

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

MGR984

T

sys

t

CWH

t

CWL

Fig.7 System clock timing.

handbook, full pagewidth

MGL880

t

f

t

h(WS)

t

su(WS)

t

su(DATAI)

t

h(DATAI)

t

BCKH

t

BCKL

T

cy(BCK)

t

r

WS

BCK

DATAI

Fig.8 Serial interface timing.

2000 Apr 18 17

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

APPLICATION INFORMATION

Fig.9 Application diagram.

handbook, full pagewidth

MGL403

47 Ω

R1

UDA1330ATS

6

SYSCLK

system

clock

1

BCK

2

WS

3

DATAI

14

VOUTL

R4

100 Ω

R5
10 kΩ

16

VOUTR

R6

100 Ω
R7
10 kΩ

7

APPSEL

10

APPL1

9

APPL2

8

APPL3

11

APPL0

47 µF
(16 V)

C3

47 µF
(16 V)

C2

left
output

right
output

12

V

ref(DAC)

C4
47 µF
(16 V)

C7
100 nF
(63 V)

45

V

DDD

V

SSD

R3
1 Ω

digital

supply voltage

C6

15 13

V

SSA

V

DDA

R2
1 Ω

C1

100 µF

(16 V)

C5

100 nF

(63 V)

100 nF

(63 V)

analog

supply voltage

2000 Apr 18 18

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

PACKAGE OUTLINE

UNIT A1A2A

3

b

p

cD

(1)E(1)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.15

0.00

1.4

1.2

0.32

0.20

0.25

0.13

5.30

5.10

4.5

4.3

0.65

6.6

6.2

0.65

0.45

0.48

0.18

10

0

o

o

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

1.0

SOT369-1 MO-152

95-02-04
99-12-27

w M

θ

A

A

1

A

2

b

p

D

y

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

0.25

18

16

9

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

A

max.

1.5

2000 Apr 18 19

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very briefinsight toacomplex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides,the footprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Apr 18 20

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e)equal toor larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

2000 Apr 18 21

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification Development This data sheet contains the design target or goal specifications for

product development. Specification may change in any manner without
notice.

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification Production This data sheet contains final specifications. Philips Semiconductors

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at any otherconditionsabove those given inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result inpersonal injury. Philips
Semiconductorscustomersusingor selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of these products,conveys nolicence ortitle
under any patent, copyright, or mask work right to these
products,and makes no representationsorwarranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2000 Apr 18 22

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

NOTES

2000 Apr 18 23

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

69

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Printed in The Netherlands 753503/25/04/pp24 Date of release: 2000 Apr 18 Document order number: 9397 750 06964