Datasheet UDA1330ATS-N1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1998 Mar 06
File under Integrated Circuits, IC01

1998 Mar 24

INTEGRATED CIRCUITS

UDA1330ATS

Low-cost stereo filter DAC

1998 Mar 24 2

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

FEATURES
General

• Low power consumption

• 4.5 to 5.5 V power supply

• Selectable control via L3 microcontroller interface or via

static pin control

• System clock frequencies of 256, 384 and 512f

s

,
selectable via the L3 interface or 256fsand 384fs clock
mode selectable via the static pin control

• Supports sampling frequencies (fs) from 16 to 48 kHz

• Integrated digital filter plus non inverting

Digital-to-Analog Converter (DAC)

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

• Small package size (SSOP16).

Multiple format input interface

• I

2

S-bus, MSB-justified and LSB-justified 16, 18 and

20 bits format compatible (in L3 mode)

• I2S-bus and LSB-justified 16, 18 and 20 bits format
compatible

• 1fs input format data rate.

DAC digital sound processing

• Digital logarithmic volume control via L3 control

• Digital de-emphasis for 32, 44.1 and 48 kHz sampling

frequencies via L3 control or 44.1 kHz sampling
frequency via static pin control

• Soft mute via static pin control or via L3 interface.

Advanced audio configuration

• Stereo line output (under L3 volume control)

• High linearity, wide dynamic range, low distortion.

APPLICATIONS

• 5 V PC audio applications

• Car radio applications.

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing
bitstream conversion techniques. The UDA1330ATS can
be used in two modes, either the L3 mode or the static pin
mode.

The UDA1330ATS supports the I

2

S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.

In the L3 mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.

In the two static modes, the UDA1330ATS can be
operated in the 256fs and 384fs system clock mode.
The mute, de-emphasis for 44.1 kHz and 4 digital input
formats (I2S-bus and 16, 18, and 20 bits LSB formats) can
be selected via static pins. The L3 interface cannot be
used in this application mode. Volume control is also not
available in this mode.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1330ATS/N1 SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1998 Mar 24 3

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

QUICK REFERENCE DATA

Note

1. The output voltage scales linearly with the power supply voltage.

BLOCK DIAGRAM

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

analog supply voltage 4.5 5.0 5.5 V

V

DDD

digital supply voltage 4.5 5.0 5.5 V

I

DDA

DAC supply current − 9.5 − mA

I

DDD

digital supply current − 5.5 − mA

T

amb

operating ambient temperature −20 − +85 °C

DAC

V

o(rms)

output voltage (RMS value) note 1 − 1.45 − V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−88 −83 dB
at −60 dB; A-weighted −−40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted − 100 −95 dB

α

cs

channel separation − 100 − dB

T

amb

operating ambient temperature −20 − +85 °C

Fig.1 Block diagram.

handbook, full pagewidth

MGL401

DAC

UDA1330ATS

NOISE SHAPER

INTERPOLATION FILTER

VOLUME/MUTE/DE-EMPHASIS

CONTROL

INTERFACE

14

15

DAC

6

DIGITAL INTERFACE

8

16

9

10

3

2

1

4

5

11

7

13 12

V

O(R)

BCK

V

SSA

WS

V

O(L)

DATAI

V

DDA

V

DDD

V

ref(DAC)

V

SSD

APPL0

SYSCLK

APPL1

APPSEL

APPL2
APPL3

1998 Mar 24 4

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input
WS 2 word select input
DATAI 3 data input
V

DDD

4 digital power supply

V

SSD

5 digital ground

SYSCLK 6 system clock input 256, 384

and 512f

s

APPSEL 7 application mode select input
APPL3 8 application input pin 3
APPL2 9 application input pin 2
APPL1 10 application input pin 1
APPL0 11 application input pin 0
V

ref(DAC)

12 DAC reference voltage

V

DDA

13 analog supply voltage

V

O(L)

14 left output voltage

V

SSA

15 analog ground

V

O(R)

16 right output voltage

Fig.2 Pin configuration.

handbook, halfpage

UDA1330ATS

MGL402

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

O(R)

BCK

V

SSA

WS

V

O(L)

DATAI

V

DDA

V

DDD

V

ref(DAC)

V

SSD

APPL0SYSCLK
APPL1APPSEL
APPL2APPL3

FUNCTIONAL DESCRIPTION
System clock

The UDA1330ATS operates in slave mode only. In all
applications, therefore, the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.

The options are 256, 384 and 512f

s

for the L3 mode and
256fs plus 384fs for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.

The UDA1330ATS supports sampling frequencies from
16 to 48 kHz.

Application modes

Operation can be set with the tri-value APPSEL pin, to
L3 mode (APPSEL = V

SSD

) or to either of two static modes

(APPSEL = 0.5V

DDD

or APPSEL = V

DDD

), see Table 1 for

APPL0 to APPL3 pin functions (active = HIGH).

Table 1 Selection modes via APPSEL

For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.

It should be noted that when the L3 interface is used, an
L3 initialisation must be done when the IC is powered up.

PIN

APPSEL

V

SSD

0.5V

DDD

(384fs)

V

DDD

(256fs)

APPL0 TEST MUTE MUTE
APPL1 L3CLOCK DEEM DEEM
APPL2 L3MODE SF0 SF0
APPL3 L3DATA SF1 SF1

1998 Mar 24 5

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Multiple format input interface

L3

MODE

• I2S-bus with data word length of up to 20 bits

• MSB-justified format with data word length up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

S

TATIC PIN MODE

The UDA1330ATS supports the following data input name
formats in the static pin mode (via SF0 and SF1):

• I2S-bus with data word length of up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

See Table 2, for the static pin codes of the 4 formats,
selectable via SF0 and SF1.

The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes.

Table 2 Input format selection using SF0 and SF1

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed. The WS signal
must have a 50% duty factor for all LSB-justified modes.

For the digital data interface the bit clock frequency should
be less than or equal to 64 times the word frequency;
f

BCK

= ≤ 64fWS.

Pin compatibility

In L3 interface mode the UDA1330ATS can be used on
boards that are designed for the UDA1320ATS.

IMPORTANT: It should be noted that the UDA1330ATS is
designed for 5 V operation while the UDA1320ATS is
designed for 3 V operation.

FORMAT SF0 SF1

I

2

S-bus 0 0
LSB-justified 16 bits 0 1
LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1

Interpolation filter (DAC)

The digital filter interpolates from 1 to 128fs by cascading
a recursive filter and an FIR filter, see Table 3.

Table 3 Interpolation filter characteristics

Noise shaper

The 3rd-order noise shaper operates at 128f

s

. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter-Stream DAC (FSDAC).

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to be
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage scales linearly with the power supply
voltage.

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f

s

±0.1

Stop band >0.55f

s

−50

Dynamic range 0 to 0.45f

s

108

1998 Mar 24 6

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

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dbook, full pagewidth

LSB-JUSTIFIED FORMAT 16 BITS

LSB-JUSTIFIED FORMAT 18 BITS

LSB-JUSTIFIED FORMAT 20 BITS

MSB-JUSTIFIED FORMAT

WS

LEFT

LEFT

LEFT

LEFT

RIGHT

RIGHT

RIGHT

RIGHT

32

2

215161718 1

1516 1

1321

MSB B2 MSBLSB LSB MSB B2B2

MSB LSBB2

MSB B2 B3 B4

B15

LSB

B17

215161718 1

MSB B2 B3 B4

LSB

B17

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

21516 1

MSB LSBB2 B15

≥8 ≥8

BCK

DATAI

WS

LEFT

RIGHT

321321

MSB B2 MSBLSB LSB MSBB2

≥8 ≥8

BCK

DATAI

WS

BCK

DATAI

WS

BCK

DATAI

WS

BCK

DATAI

INPUT FORMAT I

2

S-BUS

MBK071

Fig.3 Serial interface; input format I2S-bus.

1998 Mar 24 7

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

L3 INTERFACE DESCRIPTION
The L3 interface

The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1330ATS.

• System clock frequency

• Data input format

• De-emphasis for 32, 44.1 and 48 kHz

• Volume

• Soft mute.

The exchange of data and control information between the
microcontroller and the UDA1330ATS is accomplished
through a serial interface comprising the following pins:

• L3DATA

• L3MODE

• L3CLOCK.

Information transfer through the microcontroller bus is
organized in accordance with the L3 format, in which two
different modes of operation can be distinguished; address
mode and data transfer mode (see Figs 4 and 6).

The address mode is required to select a device
communicating via the L3 bus and to define the
destination registers for the data transfer mode. Data
transfer can only be in one direction, consisting of input to
the UDA1330ATS to program sound processing and other
functional features.

Data bits 7 to 2 represent a 6-bit device address, bit 7
being the MSB. The address of the UDA1330ATS is
000101 (bit 7 to bit 2). If the UDA1330ATS receives a
different address, it will deselect its microcontroller
interface logic.

Data transfer mode

The selected address remains active during subsequent
data transfers until the UDA1330ATS receives a new
address command. The fundamental timing of data
transfers is essentially the same as in the address mode,
see Fig.4. The maximum input clock and data rate is 64fs.
All transfers are by 8-bit bytes. Data will be stored in the
UDA1330ATS after reception of a complete byte.
See Fig.5 for a multi-byte transfer.

Table 4 Selection of data transfer

The sound feature values are stored in independent
registers. The first selection of the registers is achieved by
the choice of data type that is transferred (‘STATUS’ or
‘DATA’ transfer). This is performed in the address mode
using bit 1 and bit 0, see Table 4. The settings that can be
controlled with ‘STATUS’ transfer are given in Table 5, and
the settings that can be controlled using ‘DATA’ transfer
are given in Table 6.

The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) is the value that is placed in the selected
registers.

BIT 1 BIT 0 TRANSFER

0 0 DATA (volume, de-emphasis, mute)
0 1 not used
1 0 STATUS (system clock frequency,

data input format)

1 1 not used

1998 Mar 24 8

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Fig.4 Timing address mode.

handbook, full pagewidth

t

h(L3)A

t

h(L3)DA

t

su(L3)DA

T

cy(CLK)(L3)

BIT 0

L3MODE

L3CLCK

L3DATA

BIT 7

MBK072

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

su(L3)A

t

h(L3)A

Fig.5 Multi-byte transfer.

handbook, full pagewidth

t

stp(L3)

address

L3DATA

L3CLK

L3MODE

addressdata byte #1 data byte #2

MBK074

1998 Mar 24 9

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Table 5 Data transfer of type ‘status’

Table 6 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 0 System Clock frequency (1 : 0);

data Input Format (2 : 0)

10000000reserved

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
01000000reserved
1 0 0 DE1 DE0 MT 0 0 DE-emphasis (1 : 0); MuTe
11000001default setting

Fig.6 Timing for data transfer mode.

handbook, full pagewidth

t

stp(L3)

t

stp(L3)

t

su(L3)D

t

h(L3)DA

t

su(L3)DA

t

h(L3)DA

t

h(L3)D

MBK073

T

cy(CLK)L3

BIT 0

L3MODE

L3CLCK

L3DATA

write

BIT 7

t

CLK(L3)H

t

CLK(L3)L

1998 Mar 24 10

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Programming the features

When the data transfer of type ‘STATUS’ is selected, the
features SYSTEM CLOCK FREQUENCY and DATA
INPUT FORMAT can be controlled.

System clock frequency: a 2-bit value to select the used
external clock frequency.

Table 7 System clock settings

Data input format: a 3-bit value to select the data format.

Table 8 Data input format settings

When the data transfer of type ‘DATA’ is selected, the
features VOLUME, DE-EMPHASIS and MUTE can be
controlled.

Volume control: a 6-bit value to program the volume
attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB.

SC1 SC0 FUNCTION

0 0 512f

s

0 1 384f

s

1 0 256f

s

1 1 not used

IF2 IF1 IF0 FUNCTION

000I

2

S-bus
0 0 1 LSB-justified, 16 bits
0 1 0 LSB-justified, 18 bits
0 1 1 LSB-justified, 20 bits
1 0 0 MSB-justified
1 0 1 not used
1 1 0 not used
1 1 1 not used

Table 9 Volume settings

De-emphasis: a 2-bit value to enable the digital

de-emphasis filter.

Table 10 De-emphasis settings

Mute: a 1-bit value to enable the digital mute.

Table 11 Mute setting

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
111101 −60
111111 −∞

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz

MT FUNCTION

0 no muting
1 muting

1998 Mar 24 11

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 3 which can withstand ESD
pulses of −2500 V to +2500 V.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

. The number of the quality specification can be found in the

“Quality Reference

Handbook”

. The handbook can be ordered using the code 9397 750 00192.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

digital supply voltage note 1 − 6.0 V

V

DDA

analog supply voltage note 1 − 6.0 V

T

xtal(max)

maximum crystal temperature − 150 °C

T

stg

storage temperature −65 +125 °C

T

amb

operating ambient temperature −20 +85 °C

V

es

electrostatic handling note 2 −3000 +3000 V

note 3 −250 +250 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 190 K/W

1998 Mar 24 12

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

DC CHARACTERISTICS

V

DDD=VDDA

= 5.0 V; T

amb

=25°C; RL=5kΩ; all voltages referenced to ground (pins 5 and 15); unless otherwise

specified.

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA

= 5.0 V; fi= 1 kHz; T

amb

=25°C; RL=5kΩ; all voltages referenced to ground (pins 5 and 15); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

DAC analog supply voltage note 1 4.0 5.0 5.5 V

V

DDD

digital supply voltage note 1 4.0 5.0 5.5 V

I

DDA

analog supply current − 9.5 − mA

I

DDD

digital supply current − 5.5 − mA

Digital input pins

V

IH

HIGH-level input voltage 0.8V

DDD

−−V

V

IL

LOW-level input voltage −−0.2V

DDD

V

I

LI

 input leakage current −−1µA

C

I

input capacitance −−10 pF

DAC

V

ref(DAC)

reference voltage with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

I

O(max)

maximum output current (THD + N)/S < 0.1%;

RL=5kΩ

− 0.36 − mA

R

O

output resistance − 0.15 2.0 Ω

R

L

load resistance 3 −−kΩ

C

L

load capacitance note 2 −−50 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

V

o(rms)

output voltage (RMS value) − 1.45 − V

∆V

o

unbalance between channels − 0.1 − dB

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−88 −83 dB
at −60 dB; A-weighted −−40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted − 100 −95 dB

α

cs

channel separation − 100 − dB

PSRR power supply ripple rejection

ratio

f

ripple

= 1 kHz;

V

ripple

= 100 mV (p-p)

− 50 − dB

1998 Mar 24 13

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA

= 4.5 to 5.5 V; T

amb

= −20 to +85 °C; RL=5kΩ; all voltages referenced to ground (pins 5 and 15); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

T

sys

system clock cycle f

sys

= 256f

s

78 88 244 ns

f

sys

= 384f

s

52 59 162 ns

f

sys

= 512f

s

39 44 122 ns

t

CLK(sys)L

LOW-level system clock pulse width f

sys

< 19.2 MHz 0.30T

sys

− 0.70T

sys

ns

f

sys

≥ 19.2 MHz 0.40T

sys

− 0.60T

sys

ns

t

CLK(sys)H

HIGH-level system clock pulse width f

sys

< 19.2 MHz 0.30T

sys

− 0.70T

sys

ns

f

sys

≥ 19.2 MHz 0.40T

sys

− 0.60T

sys

ns
Serial input data timing (see Fig.7)
T

cy(CLK)(bit)

bit clock period 300 −− ns

t

CLKH(bit)

bit clock HIGH time 100 −−ns

t

CLKL(bit)

bit clock LOW time 100 −−ns

t

r

rise time −−20 ns

t

f

fall time −−20 ns

t

su(i)(D)

data input set-up time 20 −− ns

t

h(i)(D)

data input hold time 0 −−ns

t

su(WS)

word selection set-up time 20 −− ns

t

h(WS)

word selection hold time 10 −− ns
Microcontroller interface timing (see Figs 4 and 6)
T

cy(CLK)(L3)

L3CLK 500 −− ns
t

CLK(L3)H

L3CLK HIGH period 250 −− ns
t

CLK(L3)L

L3CLK LOW period 250 −−ns
t

su(L3)A

L3MODE set-up time addressing mode 190 −−ns
t

h(L3)A

L3MODE hold time addressing mode 190 −− ns
t

su(L3)D

L3MODE set-up time data transfer mode 190 −− ns
t

h(L3)D

L3MODE hold time data transfer mode 190 −−ns
t

su(L3)DA

L3DATA set-up time data transfer and

addressing mode

190 −− ns

t

h(L3)DA

L3DATA hold time data transfer and

addressing mode

30 −− ns

t

stp(L3)

L3MODE halt time 190 −− ns

1998 Mar 24 14

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

Fig.7 Serial interface timing.

handbook, full pagewidth

MBK075

t

f

t

h(WS)

t

su(WS)

t

su(i)(D)

t

h(i)(D)

t

CLKH(bit)

t

CLKH(bit)
T

cy(CLK)(bit)

t

r

WS

BCLK

DATAI

1998 Mar 24 15

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

APPLICATION INFORMATION

Fig.8 Application diagram.

handbook, full pagewidth

MGL403

47 Ω

R1

UDA1330ATS

6

SYSCLK

system

clock

1

BCK

2

WS

3

DATAI

14

V

O(L)

R4

100 Ω

R5
10 kΩ

16

V

O(R)

R6

100 Ω
R7
10 kΩ

7

APPSEL

10

APPL1

9

APPL2

8

APPL3

11

APPL0

47 µF
(16 V)

C3

47 µF
(16 V)

C2

left
output

right
output

12

V

ref(DAC)

C4
47 µF
(16 V)

C7
100 nF
(63 V)

45

V

DDD

V

SSD

R3
1 Ω

digital

supply voltage

C6

15 13

V

SSA

V

DDA

R2
1 Ω

C1

100 µF

(16 V)

C5

100 nF

(63 V)

100 nF

(63 V)

analog

supply voltage

1998 Mar 24 16

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

PACKAGE OUTLINE

UNIT A1A2A

3

b

p

cD

(1)E(1)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.15

0.00

1.4

1.2

0.32

0.20

0.25

0.13

5.30

5.10

4.5

4.3

0.65

6.6

6.2

0.65

0.45

0.48

0.18

10

0

o

o

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

1.0

SOT369-1

94-04-20
95-02-04

w M

θ

A

A

1

A

2

b

p

D

y

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

0.25

18

16

9

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

A

max.

1.5

1998 Mar 24 17

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Mar 24 18

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1998 Mar 24 19

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1330ATS

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 545102/1200/02/pp20 Date of release: 1998Mar 24 Document order number: 9397 750 03595